Merge "Disallow flashing locked device" into main
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index da701e4..d6f3fa4 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -2,7 +2,7 @@
windows_vm: windows-2019
ubuntu_vm: ubuntu-22.04
macos_vm: macOS-12
- ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20230624-20Jul2023
+ ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20230804-25Aug2023
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# since our $(ci_runner_image) user is not root.
@@ -67,16 +67,6 @@
:^doc/ :^arch/arm/dts/ :^scripts/kconfig/lkc.h
:^include/linux/kconfig.h :^tools/ && exit 1 || exit 0
- - job: cppcheck
- displayName: 'Static code analysis with cppcheck'
- pool:
- vmImage: $(ubuntu_vm)
- container:
- image: $(ci_runner_image)
- options: $(container_option)
- steps:
- - script: cppcheck -j$(nproc) --force --quiet --inline-suppr .
-
- job: docs
displayName: 'Build documentation'
pool:
@@ -92,28 +82,6 @@
make htmldocs KDOC_WERROR=1
make infodocs
- - job: todo
- displayName: 'Search for TODO within source tree'
- pool:
- vmImage: $(ubuntu_vm)
- container:
- image: $(ci_runner_image)
- options: $(container_option)
- steps:
- - script: grep -r TODO .
- - script: grep -r FIXME .
- - script: grep -r HACK . | grep -v HACKKIT
-
- - job: sloccount
- displayName: 'Some statistics about the code base'
- pool:
- vmImage: $(ubuntu_vm)
- container:
- image: $(ci_runner_image)
- options: $(container_option)
- steps:
- - script: sloccount .
-
- job: maintainers
displayName: 'Ensure all configs have MAINTAINERS entries'
pool:
@@ -123,10 +91,10 @@
options: $(container_option)
steps:
- script: |
- ./tools/buildman/buildman --maintainer-check || exit 0
+ ./tools/buildman/buildman --maintainer-check
- job: tools_only
- displayName: 'Ensure host tools build'
+ displayName: 'Ensure host tools and env tools build'
pool:
vmImage: $(ubuntu_vm)
container:
@@ -135,16 +103,7 @@
steps:
- script: |
make tools-only_config tools-only -j$(nproc)
-
- - job: envtools
- displayName: 'Ensure env tools build'
- pool:
- vmImage: $(ubuntu_vm)
- container:
- image: $(ci_runner_image)
- options: $(container_option)
- steps:
- - script: |
+ make mrproper
make tools-only_config envtools -j$(nproc)
- job: utils
@@ -163,10 +122,10 @@
. /tmp/venv/bin/activate
pip install -r test/py/requirements.txt
pip install -r tools/buildman/requirements.txt
- export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl
+ export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only
export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}
- ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board sandbox_spl
+ ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board tools-only
set -ex
./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test
./tools/buildman/buildman -t
@@ -196,8 +155,8 @@
export PATH=${PATH}:~/.local/bin
echo "[MASTER]" >> .pylintrc
echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
- export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl
- ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board sandbox_spl
+ export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only
+ ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board tools-only
set -ex
pylint --version
export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
@@ -225,19 +184,109 @@
steps:
- script: make pip
-- stage: test_py
+ - job: create_test_py_wrapper_script
+ displayName: 'Create and stage a wrapper for test.py runs'
+ pool:
+ vmImage: $(ubuntu_vm)
+ steps:
+ - checkout: none
+ - script: |
+ cat << EOF > test.sh
+ #!/bin/bash
+ set -ex
+ # the below corresponds to .gitlab-ci.yml "before_script"
+ cd \${WORK_DIR}
+ git config --global --add safe.directory \${WORK_DIR}
+ git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
+ ln -s travis-ci /tmp/uboot-test-hooks/bin/\`hostname\`
+ ln -s travis-ci /tmp/uboot-test-hooks/py/\`hostname\`
+ grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
+ grub-mkimage --prefix=\"\" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
+ if [[ "\${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
+ wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
+ export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
+ fi
+ if [[ "\${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "\${TEST_PY_BD}" == "sifive_unleashed" ]]; then
+ wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
+ export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
+ fi
+ # the below corresponds to .gitlab-ci.yml "script"
+ cd \${WORK_DIR}
+ export UBOOT_TRAVIS_BUILD_DIR=/tmp/\${TEST_PY_BD}
+ if [ -n "\${BUILD_ENV}" ]; then
+ export \${BUILD_ENV};
+ fi
+ pip install -r tools/buildman/requirements.txt
+ tools/buildman/buildman -o \${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e --board \${TEST_PY_BD} \${OVERRIDE}
+ cp ~/grub_x86.efi \${UBOOT_TRAVIS_BUILD_DIR}/
+ cp ~/grub_x64.efi \${UBOOT_TRAVIS_BUILD_DIR}/
+ cp /opt/grub/grubriscv64.efi \${UBOOT_TRAVIS_BUILD_DIR}/grub_riscv64.efi
+ cp /opt/grub/grubaa64.efi \${UBOOT_TRAVIS_BUILD_DIR}/grub_arm64.efi
+ cp /opt/grub/grubarm.efi \${UBOOT_TRAVIS_BUILD_DIR}/grub_arm.efi
+ # create sdcard / spi-nor images for sifive unleashed using genimage
+ if [[ "\${TEST_PY_BD}" == "sifive_unleashed" ]]; then
+ mkdir -p root;
+ cp \${UBOOT_TRAVIS_BUILD_DIR}/spl/u-boot-spl.bin .;
+ cp \${UBOOT_TRAVIS_BUILD_DIR}/u-boot.itb .;
+ rm -rf tmp;
+ genimage --inputpath . --config board/sifive/unleashed/genimage_sdcard.cfg;
+ cp images/sdcard.img \${UBOOT_TRAVIS_BUILD_DIR}/;
+ rm -rf tmp;
+ genimage --inputpath . --config board/sifive/unleashed/genimage_spi-nor.cfg;
+ cp images/spi-nor.img \${UBOOT_TRAVIS_BUILD_DIR}/;
+ fi
+ if [[ "\${TEST_PY_BD}" == "coreboot" ]]; then
+ wget -O - "https://drive.google.com/uc?id=1uJ2VkUQ8czWFZmhJQ90Tp8V_zrJ6BrBH&export=download" |xz -dc >\${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
+ wget -O - "https://drive.google.com/uc?id=149Cz-5SZXHNKpi9xg6R_5XITWohu348y&export=download" >cbfstool;
+ chmod a+x cbfstool;
+ ./cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f \${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
+ fi
+ virtualenv -p /usr/bin/python3 /tmp/venv
+ . /tmp/venv/bin/activate
+ pip install -r test/py/requirements.txt
+ pip install pytest-azurepipelines
+ export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:\${PATH}
+ export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci
+ # "\${var:+"-k \$var"}" expands to "" if \$var is empty, "-k \$var" if not
+ ./test/py/test.py -ra -o cache_dir="\$UBOOT_TRAVIS_BUILD_DIR"/.pytest_cache --bd \${TEST_PY_BD} \${TEST_PY_ID} \${TEST_PY_TEST_SPEC:+"-k \${TEST_PY_TEST_SPEC}"} --build-dir "\$UBOOT_TRAVIS_BUILD_DIR" --report-dir "\$UBOOT_TRAVIS_BUILD_DIR"
+ # the below corresponds to .gitlab-ci.yml "after_script"
+ rm -rf /tmp/uboot-test-hooks /tmp/venv
+ EOF
+ - task: CopyFiles@2
+ displayName: 'Copy test.sh for later usage'
+ inputs:
+ contents: 'test.sh'
+ targetFolder: '$(Build.ArtifactStagingDirectory)'
+ - publish: '$(Build.ArtifactStagingDirectory)/test.sh'
+ displayName: 'Publish test.sh'
+ artifact: testsh
+
+- stage: test_py_sandbox
jobs:
- - job: test_py
- displayName: 'test.py'
+ - job: test_py_sandbox
+ displayName: 'test.py for sandbox'
pool:
vmImage: $(ubuntu_vm)
strategy:
matrix:
sandbox:
TEST_PY_BD: "sandbox"
+ sandbox_asan:
+ TEST_PY_BD: "sandbox"
+ OVERRIDE: "-a ASAN"
+ TEST_PY_TEST_SPEC: "version"
sandbox_clang:
TEST_PY_BD: "sandbox"
OVERRIDE: "-O clang-16"
+ sandbox_clang_asan:
+ TEST_PY_BD: "sandbox"
+ OVERRIDE: "-O clang-16 -a ASAN"
+ TEST_PY_TEST_SPEC: "version"
+ sandbox64:
+ TEST_PY_BD: "sandbox64"
+ sandbox64_clang:
+ TEST_PY_BD: "sandbox64"
+ OVERRIDE: "-O clang-16"
sandbox_nolto:
TEST_PY_BD: "sandbox"
BUILD_ENV: "NO_LTO=1"
@@ -250,13 +299,58 @@
sandbox_noinst:
TEST_PY_BD: "sandbox_noinst"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
+ sandbox_noinst_load_fit_full:
+ TEST_PY_BD: "sandbox_noinst"
+ TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
+ OVERRIDE: "-a CONFIG_SPL_LOAD_FIT_FULL=y"
sandbox_flattree:
TEST_PY_BD: "sandbox_flattree"
sandbox_trace:
TEST_PY_BD: "sandbox"
BUILD_ENV: "FTRACE=1 NO_LTO=1"
TEST_PY_TEST_SPEC: "trace"
- OVERRIDE: "-a CONFIG_TRACE=y -a CONFIG_TRACE_EARLY=y -a CONFIG_TRACE_EARLY_SIZE=0x01000000"
+ OVERRIDE: "-a CONFIG_TRACE=y -a CONFIG_TRACE_EARLY=y -a CONFIG_TRACE_EARLY_SIZE=0x01000000 -a CONFIG_TRACE_BUFFER_SIZE=0x02000000"
+ steps:
+ - download: current
+ artifact: testsh
+ - script: |
+ # make current directory writeable to uboot user inside the container
+ # as sandbox testing need create files like spi flash images, etc.
+ # (TODO: clean up this in the future)
+ chmod 777 .
+ chmod 755 $(Pipeline.Workspace)/testsh/test.sh
+ # Filesystem tests need extra docker args to run
+ set --
+ # mount -o loop needs the loop devices
+ if modprobe loop; then
+ for d in $(find /dev -maxdepth 1 -name 'loop*'); do
+ set -- "$@" --device $d:$d
+ done
+ fi
+ # Needed for mount syscall (for guestmount as well)
+ set -- "$@" --cap-add SYS_ADMIN
+ # Default apparmor profile denies mounts
+ set -- "$@" --security-opt apparmor=unconfined
+ # Some tests using libguestfs-tools need the fuse device to run
+ docker run "$@" --device /dev/fuse:/dev/fuse \
+ -v $PWD:$(work_dir) \
+ -v $(Pipeline.Workspace):$(Pipeline.Workspace) \
+ -e WORK_DIR="${WORK_DIR}" \
+ -e TEST_PY_BD="${TEST_PY_BD}" \
+ -e TEST_PY_ID="${TEST_PY_ID}" \
+ -e TEST_PY_TEST_SPEC="${TEST_PY_TEST_SPEC}" \
+ -e OVERRIDE="${OVERRIDE}" \
+ -e BUILD_ENV="${BUILD_ENV}" $(ci_runner_image) \
+ $(Pipeline.Workspace)/testsh/test.sh
+
+- stage: test_py_qemu
+ jobs:
+ - job: test_py_qemu
+ displayName: 'test.py for QEMU platforms'
+ pool:
+ vmImage: $(ubuntu_vm)
+ strategy:
+ matrix:
coreboot:
TEST_PY_BD: "coreboot"
TEST_PY_ID: "--id qemu"
@@ -353,97 +447,25 @@
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep"
steps:
+ - download: current
+ artifact: testsh
- script: |
- cat << EOF > test.sh
- set -ex
- # make environment variables available as tests are running inside a container
- export WORK_DIR="${WORK_DIR}"
- export TEST_PY_BD="${TEST_PY_BD}"
- export TEST_PY_ID="${TEST_PY_ID}"
- export TEST_PY_TEST_SPEC="${TEST_PY_TEST_SPEC}"
- export OVERRIDE="${OVERRIDE}"
- export BUILD_ENV="${BUILD_ENV}"
- EOF
- cat << "EOF" >> test.sh
- # the below corresponds to .gitlab-ci.yml "before_script"
- cd ${WORK_DIR}
- git config --global --add safe.directory ${WORK_DIR}
- git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
- ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
- ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
- grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
- grub-mkimage --prefix=\"\" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
- if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
- wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ;
- export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
- fi
- if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
- wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ;
- export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
- fi
- # the below corresponds to .gitlab-ci.yml "script"
- cd ${WORK_DIR}
- export UBOOT_TRAVIS_BUILD_DIR=/tmp/${TEST_PY_BD};
- if [ -n "${BUILD_ENV}" ]; then
- export ${BUILD_ENV};
- fi
- pip install -r tools/buildman/requirements.txt
- tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e --board ${TEST_PY_BD} ${OVERRIDE}
- cp ~/grub_x86.efi ${UBOOT_TRAVIS_BUILD_DIR}/
- cp ~/grub_x64.efi ${UBOOT_TRAVIS_BUILD_DIR}/
- cp /opt/grub/grubriscv64.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_riscv64.efi
- cp /opt/grub/grubaa64.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_arm64.efi
- cp /opt/grub/grubarm.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_arm.efi
- # create sdcard / spi-nor images for sifive unleashed using genimage
- if [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
- mkdir -p root;
- cp ${UBOOT_TRAVIS_BUILD_DIR}/spl/u-boot-spl.bin .;
- cp ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.itb .;
- rm -rf tmp;
- genimage --inputpath . --config board/sifive/unleashed/genimage_sdcard.cfg;
- cp images/sdcard.img ${UBOOT_TRAVIS_BUILD_DIR}/;
- rm -rf tmp;
- genimage --inputpath . --config board/sifive/unleashed/genimage_spi-nor.cfg;
- cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/;
- fi
- if [[ "${TEST_PY_BD}" == "coreboot" ]]; then
- wget -O - "https://drive.google.com/uc?id=1uJ2VkUQ8czWFZmhJQ90Tp8V_zrJ6BrBH&export=download" |xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
- wget -O - "https://drive.google.com/uc?id=149Cz-5SZXHNKpi9xg6R_5XITWohu348y&export=download" >cbfstool;
- chmod a+x cbfstool;
- ./cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
- fi
- virtualenv -p /usr/bin/python3 /tmp/venv
- . /tmp/venv/bin/activate
- pip install -r test/py/requirements.txt
- pip install pytest-azurepipelines
- export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:${PATH};
- export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci;
- # "${var:+"-k $var"}" expands to "" if $var is empty, "-k $var" if not
- ./test/py/test.py -ra -o cache_dir="$UBOOT_TRAVIS_BUILD_DIR"/.pytest_cache --bd ${TEST_PY_BD} ${TEST_PY_ID} ${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"} --build-dir "$UBOOT_TRAVIS_BUILD_DIR" --report-dir "$UBOOT_TRAVIS_BUILD_DIR";
- # the below corresponds to .gitlab-ci.yml "after_script"
- rm -rf /tmp/uboot-test-hooks /tmp/venv
- EOF
- cat test.sh
# make current directory writeable to uboot user inside the container
# as sandbox testing need create files like spi flash images, etc.
# (TODO: clean up this in the future)
chmod 777 .
- # Filesystem tests need extra docker args to run
- set --
- if [[ "${TEST_PY_BD}" == "sandbox" ]]; then
- # mount -o loop needs the loop devices
- if modprobe loop; then
- for d in $(find /dev -maxdepth 1 -name 'loop*'); do
- set -- "$@" --device $d:$d
- done
- fi
- # Needed for mount syscall (for guestmount as well)
- set -- "$@" --cap-add SYS_ADMIN
- # Default apparmor profile denies mounts
- set -- "$@" --security-opt apparmor=unconfined
- fi
+ chmod 755 $(Pipeline.Workspace)/testsh/test.sh
# Some tests using libguestfs-tools need the fuse device to run
- docker run "$@" --device /dev/fuse:/dev/fuse -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/test.sh
+ docker run "$@" --device /dev/fuse:/dev/fuse \
+ -v $PWD:$(work_dir) \
+ -v $(Pipeline.Workspace):$(Pipeline.Workspace) \
+ -e WORK_DIR="${WORK_DIR}" \
+ -e TEST_PY_BD="${TEST_PY_BD}" \
+ -e TEST_PY_ID="${TEST_PY_ID}" \
+ -e TEST_PY_TEST_SPEC="${TEST_PY_TEST_SPEC}" \
+ -e OVERRIDE="${OVERRIDE}" \
+ -e BUILD_ENV="${BUILD_ENV}" $(ci_runner_image) \
+ $(Pipeline.Workspace)/testsh/test.sh
retryCountOnTaskFailure: 2 # QEMU may be too slow, etc.
- stage: world_build
@@ -457,84 +479,26 @@
# Use almost the same target division in .travis.yml, only merged
# 3 small build jobs (arc/microblaze/xtensa) into one.
matrix:
- arc_nios2_m68k_microblaze_xtensa:
- BUILDMAN: "arc nios2 microblaze m68k xtensa"
- amlogic:
- BUILDMAN: "amlogic"
- arm11_arm7_arm920t_arm946es:
- BUILDMAN: "arm11 arm7 arm920t arm946es"
- arm926ejs:
- BUILDMAN: "arm926ejs -x freescale,siemens,at91,kirkwood,omap"
- at91_non_armv7:
- BUILDMAN: "at91 -x armv7"
- at91_non_arm926ejs:
- BUILDMAN: "at91 -x arm926ejs"
- boundary_engicam_toradex:
- BUILDMAN: "boundary engicam toradex"
- arm_bcm:
- BUILDMAN: "bcm -x mips"
- nxp_arm32:
- BUILDMAN: "freescale -x powerpc,m68k,aarch64,ls101,ls102,ls104,ls108,ls20,lx216"
- nxp_ls101x_ls108x:
- BUILDMAN: "freescale&ls101 freescale&ls108"
- nxp_ls102x:
- BUILDMAN: "freescale&ls102 -x keymile"
- nxp_ls104x:
- BUILDMAN: "freescale&ls104"
- nxp_ls20xx_lx216x:
- BUILDMAN: "freescale&ls20 freescale&lx216"
- imx6:
- BUILDMAN: "mx6 -x boundary,engicam,freescale,technexion,toradex"
+ am33xx_at91_kirkwood_mvebu_omap:
+ BUILDMAN: "am33xx at91_kirkwood mvebu omap -x siemens"
+ amlogic_bcm_boundary_engicam_siemens_technexion_oradex:
+ BUILDMAN: "amlogic bcm boundary engicam siemens technexion toradex -x mips"
+ arm_nxp_minus_imx:
+ BUILDMAN: "freescale -x powerpc,m68k,imx,mx"
imx:
- BUILDMAN: "mx -x mx6,imx8,freescale,technexion,toradex"
- imx8_imx9:
- BUILDMAN: "imx8 imx9 -x engicam,technexion,toradex"
- keymiles_siemens_technexion:
- BUILDMAN: "keymile siemens technexion"
- keystone2_keystone3:
- BUILDMAN: "k2 k3 -x siemens,toradex"
- sandbox_asan:
- BUILDMAN: "sandbox"
- OVERRIDE: "-a ASAN"
- sandbox_clang_asan:
- BUILDMAN: "sandbox"
- OVERRIDE: "-O clang-16 -a ASAN"
- samsung_socfpga_renesas:
- BUILDMAN: "samsung socfpga renesas"
- sun4i_sun9i:
- BUILDMAN: "sun4i sun9i"
- sun5i_sun6i:
- BUILDMAN: "sun5i sun6i"
- sun7i:
- BUILDMAN: "sun7i"
- sun8i:
- BUILDMAN: "sun8i"
- sun50i:
- BUILDMAN: "sun50i"
- arm_catch_all:
- BUILDMAN: "arm -x arm11,arm7,arm9,aarch64,at91,bcm,freescale,kirkwood,mvebu,renesas,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,toradex,socfpga,k2,k3,zynq"
- sandbox_x86:
- BUILDMAN: "sandbox x86"
- kirkwood_mvebu_uniphier:
- BUILDMAN: "kirkwood mvebu uniphier"
- mips:
- BUILDMAN: "mips"
+ BUILDMAN: "mx imx -x boundary,engicam,technexion,toradex"
+ rk:
+ BUILDMAN: "rk"
+ sunxi:
+ BUILDMAN: "sunxi"
powerpc:
- BUILDMAN: "powerpc -x keymile"
- tegra:
- BUILDMAN: "tegra -x toradex"
- am33xx_omap:
- BUILDMAN: "am33xx omap -x siemens"
+ BUILDMAN: "powerpc"
+ arm_catch_all:
+ BUILDMAN: "arm -x aarch64,am33xx,at91,bcm,ls1,kirkwood,mvebu,omap,rk,siemens,mx,sunxi,technexion,toradex"
aarch64_catch_all:
- BUILDMAN: "aarch64 -x amlogic,bcm,imx8,imx9,k3,tegra,ls1,ls2,lx216,mvebu,uniphier,renesas,sunxi,samsung,socfpga,rk,versal,zynq"
- rk_non_rockchip_64bit:
- BUILDMAN: "rk&aarch64 -x rockchip"
- rk_rockchip_64bit:
- BUILDMAN: "rk&aarch64&rockchip"
- zynq_zynqmp_versal:
- BUILDMAN: "zynq&armv7 versal zynqmp&aarch64"
- riscv:
- BUILDMAN: "riscv"
+ BUILDMAN: "aarch64 -x amlogic,bcm,engicam,imx,ls1,ls2,lx216,mvebu,rk,siemens,sunxi,toradex"
+ everything_but_arm_and_powerpc:
+ BUILDMAN: "-x arm,powerpc"
steps:
- script: |
cat << EOF > build.sh
diff --git a/.get_maintainer.conf b/.get_maintainer.conf
index df595f5..f916cfb 100644
--- a/.get_maintainer.conf
+++ b/.get_maintainer.conf
@@ -1 +1 @@
---find-maintainer-files --maintainer-path=.
+--find-maintainer-files --git --maintainer-path=.
diff --git a/.gitignore b/.gitignore
index dffe500..d09f92a 100644
--- a/.gitignore
+++ b/.gitignore
@@ -36,7 +36,7 @@
*.tab.[ch]
# Build tree
-/build-*
+/build*
#
# Top-level generic files
@@ -45,8 +45,10 @@
/MLO*
/SPL*
/System.map
-/u-boot*
/boards.cfg
+/mkimage-in-simple-bin*
+/simple-bin*
+/u-boot*
/*.log
#
@@ -66,6 +68,8 @@
#
# Generated include files
#
+/include/autoconf.mk*
+/include/config.h
/include/config/
/include/generated/
@@ -108,5 +112,8 @@
/pylint.cur
/pylint.out/
-# moveconfig database
-/moveconfig.db
+# qconfig database
+/qconfig.db
+
+# Clang's compilation database file
+/compile_commands.json
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 2ceeb94..fee1651 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -10,7 +10,7 @@
# Grab our configured image. The source for this is found
# in the u-boot tree at tools/docker/Dockerfile
-image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20230624-20Jul2023
+image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20230804-25Aug2023
# We run some tests in different order, to catch some failures quicker.
stages:
@@ -21,6 +21,8 @@
.buildman_and_testpy_template: &buildman_and_testpy_dfn
stage: test.py
retry: 2 # QEMU may be too slow, etc.
+ rules:
+ - when: always
before_script:
# Clone uboot-test-hooks
- git config --global --add safe.directory "${CI_PROJECT_DIR}"
@@ -30,12 +32,12 @@
- grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
- grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
- if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
- wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ;
- export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
+ wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
+ export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
fi
- if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
- wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ;
- export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
+ wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
+ export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
fi
after_script:
@@ -93,8 +95,13 @@
- "*.css"
expire_in: 1 week
-build all 32bit ARM platforms:
+.world_build:
stage: world build
+ rules:
+ - when: always
+
+build all 32bit ARM platforms:
+ extends: .world_build
script:
- ret=0;
git config --global --add safe.directory "${CI_PROJECT_DIR}";
@@ -106,7 +113,7 @@
fi;
build all 64bit ARM platforms:
- stage: world build
+ extends: .world_build
script:
- virtualenv -p /usr/bin/python3 /tmp/venv
- . /tmp/venv/bin/activate
@@ -120,7 +127,7 @@
fi;
build all PowerPC platforms:
- stage: world build
+ extends: .world_build
script:
- ret=0;
git config --global --add safe.directory "${CI_PROJECT_DIR}";
@@ -131,7 +138,7 @@
fi;
build all other platforms:
- stage: world build
+ extends: .world_build
script:
- ret=0;
git config --global --add safe.directory "${CI_PROJECT_DIR}";
@@ -141,8 +148,13 @@
exit $ret;
fi;
-check for new CONFIG symbols outside Kconfig:
+.testsuites:
stage: testsuites
+ rules:
+ - when: always
+
+check for new CONFIG symbols outside Kconfig:
+ extends: .testsuites
script:
- git config --global --add safe.directory "${CI_PROJECT_DIR}"
# If grep succeeds and finds a match the test fails as we should
@@ -151,25 +163,9 @@
:^doc/ :^arch/arm/dts/ :^scripts/kconfig/lkc.h
:^include/linux/kconfig.h :^tools/ && exit 1 || exit 0
-# QA jobs for code analytics
-# static code analysis with cppcheck (we can add --enable=all later)
-cppcheck:
- stage: testsuites
- script:
- - cppcheck -j$(nproc) --force --quiet --inline-suppr .
-
-# search for TODO within source tree
-grep TODO/FIXME/HACK:
- stage: testsuites
- script:
- - grep -r TODO .
- - grep -r FIXME .
- # search for HACK within source tree and ignore HACKKIT board
- - grep -r HACK . | grep -v HACKKIT
-
# build documentation
docs:
- stage: testsuites
+ extends: .testsuites
script:
- virtualenv -p /usr/bin/python3 /tmp/venvhtml
- . /tmp/venvhtml/bin/activate
@@ -177,32 +173,22 @@
- make htmldocs KDOC_WERROR=1
- make infodocs
-# some statistics about the code base
-sloccount:
- stage: testsuites
- script:
- - sloccount .
-
# ensure all configs have MAINTAINERS entries
Check for configs without MAINTAINERS entry:
- stage: testsuites
+ extends: .testsuites
script:
- - ./tools/buildman/buildman --maintainer-check || exit 0
+ - ./tools/buildman/buildman --maintainer-check
# Ensure host tools build
-Build tools-only:
- stage: testsuites
+Build tools-only and envtools:
+ extends: .testsuites
script:
- - make tools-only_config tools-only -j$(nproc)
-
-# Ensure env tools build
-Build envtools:
- stage: testsuites
- script:
- - make tools-only_config envtools -j$(nproc)
+ - make tools-only_config tools-only -j$(nproc);
+ make mrproper;
+ make tools-only_config envtools -j$(nproc)
Run binman, buildman, dtoc, Kconfig and patman testsuites:
- stage: testsuites
+ extends: .testsuites
script:
- git config --global user.name "GitLab CI Runner";
git config --global user.email trini@konsulko.com;
@@ -212,12 +198,12 @@
. /tmp/venv/bin/activate;
pip install -r test/py/requirements.txt;
pip install -r tools/buildman/requirements.txt;
- export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl;
+ export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only;
export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt";
export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}";
set +e;
./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w
- --board sandbox_spl;
+ --board tools-only;
set -e;
./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test;
./tools/buildman/buildman -t;
@@ -227,7 +213,7 @@
# Check for any pylint regressions
Run pylint:
- stage: testsuites
+ extends: .testsuites
script:
- git config --global --add safe.directory "${CI_PROJECT_DIR}"
- pip install -r test/py/requirements.txt
@@ -236,10 +222,10 @@
- export PATH=${PATH}:~/.local/bin
- echo "[MASTER]" >> .pylintrc
- echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
- - export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl
+ - export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only
- set +e
- ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w
- --board sandbox_spl
+ --board tools-only
- set -e
- pylint --version
- export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt"
@@ -247,7 +233,7 @@
# Check for pre-schema driver model tags
Check for pre-schema tags:
- stage: testsuites
+ extends: .testsuites
script:
- git config --global --add safe.directory "${CI_PROJECT_DIR}";
# If grep succeeds and finds a match the test fails as we should
@@ -256,7 +242,7 @@
# Check we can package the Python tools
Check packing of Python tools:
- stage: testsuites
+ extends: .testsuites
script:
- make pip
@@ -278,6 +264,23 @@
BUILD_ENV: "NO_LTO=1"
<<: *buildman_and_testpy_dfn
+sandbox64 test.py:
+ variables:
+ TEST_PY_BD: "sandbox64"
+ <<: *buildman_and_testpy_dfn
+
+sandbox64 with clang test.py:
+ variables:
+ TEST_PY_BD: "sandbox64"
+ OVERRIDE: "-O clang-16"
+ <<: *buildman_and_testpy_dfn
+
+sandbox64 without LTO test.py:
+ variables:
+ TEST_PY_BD: "sandbox64"
+ BUILD_ENV: "NO_LTO=1"
+ <<: *buildman_and_testpy_dfn
+
sandbox_spl test.py:
variables:
TEST_PY_BD: "sandbox_spl"
@@ -290,6 +293,13 @@
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
<<: *buildman_and_testpy_dfn
+sandbox_noinst with LOAD_FIT_FULL test.py:
+ variables:
+ TEST_PY_BD: "sandbox_noinst"
+ TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
+ OVERRIDE: "-a CONFIG_SPL_LOAD_FIT_FULL=y"
+ <<: *buildman_and_testpy_dfn
+
sandbox_vpl test.py:
variables:
TEST_PY_BD: "sandbox_vpl"
@@ -302,7 +312,7 @@
TEST_PY_BD: "sandbox"
BUILD_ENV: "FTRACE=1 NO_LTO=1"
TEST_PY_TEST_SPEC: "trace"
- OVERRIDE: "-a CONFIG_TRACE=y -a CONFIG_TRACE_EARLY=y -a CONFIG_TRACE_EARLY_SIZE=0x01000000"
+ OVERRIDE: "-a CONFIG_TRACE=y -a CONFIG_TRACE_EARLY=y -a CONFIG_TRACE_EARLY_SIZE=0x01000000 -a CONFIG_TRACE_BUFFER_SIZE=0x02000000"
<<: *buildman_and_testpy_dfn
evb-ast2500 test.py:
diff --git a/.mailmap b/.mailmap
index 05cb310..d1f08f3 100644
--- a/.mailmap
+++ b/.mailmap
@@ -80,6 +80,8 @@
Neal Frager <neal.frager@amd.com> <neal.frager@xilinx.com>
Neil Armstrong <neil.armstrong@linaro.org> <narmstrong@baylibre.com>
Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.de>
+This contributor prefers not to receive mails <noreply@example.com> <pali@kernel.org>
+This contributor prefers not to receive mails <noreply@example.com> <pali.rohar@gmail.com>
Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com>
Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com>
Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
diff --git a/Kconfig b/Kconfig
index 6ba605a..00ed1ec 100644
--- a/Kconfig
+++ b/Kconfig
@@ -277,10 +277,17 @@
default 0x10000 if ARCH_IMX8 || ARCH_IMX8M
default 0x2000
help
- Before relocation, memory is very limited on many platforms. Still,
- we can provide a small malloc() pool if needed. Driver model in
- particular needs this to operate, so that it can allocate the
- initial serial device and any others that are needed.
+ Size of the malloc() pool for use before relocation. If
+ this is defined, then a very simple malloc() implementation
+ will become available before relocation. The address is just
+ below the global data, and the stack is moved down to make
+ space.
+
+ This feature allocates regions with increasing addresses
+ within the region. calloc() is supported, but realloc()
+ is not available. free() is supported but does nothing.
+ The memory will be freed (or in fact just forgotten) when
+ U-Boot relocates itself.
config SYS_MALLOC_LEN
hex "Define memory for Dynamic allocation"
@@ -295,32 +302,49 @@
This defines memory to be allocated for Dynamic allocation
TODO: Use for other architectures
-config SPL_SYS_MALLOC_F_LEN
- hex "Size of malloc() pool in SPL"
- depends on SYS_MALLOC_F && SPL
- default 0x0 if !SPL_FRAMEWORK
- default 0x2800 if RCAR_GEN3
- default 0x2000 if IMX8MQ
- default SYS_MALLOC_F_LEN
+config SPL_SYS_MALLOC_F
+ bool "Enable malloc() pool in SPL"
+ depends on SPL_FRAMEWORK && SYS_MALLOC_F && SPL
+ default y
help
In SPL memory is very limited on many platforms. Still,
we can provide a small malloc() pool if needed. Driver model in
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
- It is possible to enable CFG_SYS_SPL_MALLOC_START to start a new
+config SPL_SYS_MALLOC_F_LEN
+ hex "Size of malloc() pool in SPL"
+ depends on SPL_SYS_MALLOC_F
+ default 0x2800 if RCAR_GEN3
+ default 0x2000 if IMX8MQ
+ default SYS_MALLOC_F_LEN
+ help
+ Sets the size of the malloc() pool in SPL. This is used for
+ driver model and other features, which must allocate memory for
+ data structures.
+
+ It is possible to enable CFG_SPL_SYS_MALLOC_START to start a new
malloc() region in SDRAM once it is inited.
-config TPL_SYS_MALLOC_F_LEN
- hex "Size of malloc() pool in TPL"
+config TPL_SYS_MALLOC_F
+ bool "Enable malloc() pool in TPL"
depends on SYS_MALLOC_F && TPL
- default SPL_SYS_MALLOC_F_LEN
+ default y if SPL_SYS_MALLOC_F
help
In TPL memory is very limited on many platforms. Still,
we can provide a small malloc() pool if needed. Driver model in
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
+config TPL_SYS_MALLOC_F_LEN
+ hex "Size of malloc() pool in TPL"
+ depends on TPL_SYS_MALLOC_F
+ default SPL_SYS_MALLOC_F_LEN
+ help
+ Sets the size of the malloc() pool in TPL. This is used for
+ driver model and other features, which must allocate memory for
+ data structures.
+
config VALGRIND
bool "Inform valgrind about memory allocations"
depends on !RISCV
@@ -336,16 +360,25 @@
it can be handled accurately by Valgrind. If you aren't planning on
using valgrind to debug U-Boot, say 'n'.
-config VPL_SYS_MALLOC_F_LEN
- hex "Size of malloc() pool in VPL before relocation"
+config VPL_SYS_MALLOC_F
+ bool "Enable malloc() pool in VPL"
depends on SYS_MALLOC_F && VPL
- default SYS_MALLOC_F_LEN
+ default y if SPL_SYS_MALLOC_F
help
- Before relocation, memory is very limited on many platforms. Still,
+ In VPL memory is very limited on many platforms. Still,
we can provide a small malloc() pool if needed. Driver model in
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
+config VPL_SYS_MALLOC_F_LEN
+ hex "Size of malloc() pool in VPL before relocation"
+ depends on VPL_SYS_MALLOC_F
+ default SPL_SYS_MALLOC_F_LEN
+ help
+ Sets the size of the malloc() pool in VPL. This is used for
+ driver model and other features, which must allocate memory for
+ data structures.
+
menuconfig EXPERT
bool "Configure standard U-Boot features (expert users)"
default y
@@ -596,10 +629,95 @@
This provides an option to bringup different processors
in multiprocessor cases.
-endmenu # General setup
+config HAVE_TEXT_BASE
+ bool
+ depends on !NIOS2 && !XTENSA
+ depends on !EFI_APP
+ default y
+
+config TEXT_BASE
+ depends on HAVE_TEXT_BASE
+ default 0x0 if POSITION_INDEPENDENT
+ default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3
+ default 0x81700000 if MACH_SUNIV
+ default 0x2a000000 if MACH_SUN9I
+ default 0x4a000000 if SUNXI_MINIMUM_DRAM_MB >= 256
+ default 0x42e00000 if SUNXI_MINIMUM_DRAM_MB >= 64
+ hex "Text Base"
+ help
+ The address in memory that U-Boot will be copied and executed from
+ initially.
+
+config HAVE_SYS_UBOOT_START
+ bool "Use custom U-Boot Start"
+ depends on HAVE_TEXT_BASE
+ help
+ By default, the address in memory that U-Boot will be copied from
+ (TEXT_BASE) and the entry point are the same. Select this to start the
+ execution of U-Boot from a different address.
+ This may be required if a header or vector table needs to be copied
+ but not executed.
+
+config SYS_UBOOT_START
+ hex
+ depends on HAVE_TEXT_BASE
+ default TEXT_BASE
+ prompt "U-Boot entry" if HAVE_SYS_UBOOT_START
+ help
+ If TEXT_BASE differs from the start of execution, this sets the
+ address in memory that U-Boot will start execution from initially.
+
+config HAVE_SYS_MONITOR_BASE
+ bool
+ depends on ARC || MIPS || M68K || NIOS2 || PPC || XTENSA || X86 \
+ || ENV_IS_IN_FLASH || MTD_NOR_FLASH
+ depends on !EFI_APP
+ default y
+
+config SYS_MONITOR_BASE
+ depends on HAVE_SYS_MONITOR_BASE
+ hex "Physical start address of boot monitor code"
+ default TEXT_BASE
+ help
+ The physical start address of boot monitor code (which is the same as
+ CONFIG_TEXT_BASE when linking) and the same as CFG_SYS_FLASH_BASE
+ when booting from flash.
+
+config SPL_SYS_MONITOR_BASE
+ depends on MPC85xx && SPL && HAVE_SYS_MONITOR_BASE
+ hex "Physical start address of SPL monitor code"
+ default SPL_TEXT_BASE
+
+config TPL_SYS_MONITOR_BASE
+ depends on MPC85xx && TPL && HAVE_SYS_MONITOR_BASE
+ hex "Physical start address of TPL monitor code"
+
+config DYNAMIC_SYS_CLK_FREQ
+ bool "Determine CPU clock frequency at run-time"
+ help
+ Implement a get_board_sys_clk function that will determine the CPU
+ clock frequency at run time, rather than define it statically.
+
+config SYS_CLK_FREQ
+ depends on !DYNAMIC_SYS_CLK_FREQ
+ int "CPU clock frequency"
+ default 125000000 if ARCH_LS1012A
+ default 100000000 if ARCH_P2020 || ARCH_T1024 || ARCH_T1042 || \
+ ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
+ default 66666666 if ARCH_P1010 || ARCH_P1020 || ARCH_T4240
+ default 66660000 if ARCH_T2080
+ default 33333333 if RCAR_GEN3
+ default 24000000 if ARCH_EXYNOS
+ default 20000000 if RCAR_GEN2
+ default 0
+ help
+ A static value for the CPU frequency. Note that if not required
+ for a given SoC, this can be left at 0.
source "api/Kconfig"
+endmenu # General setup
+
source "boot/Kconfig"
source "common/Kconfig"
diff --git a/MAINTAINERS b/MAINTAINERS
index 1999191..40b7794 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -58,10 +58,10 @@
ANDROID AB
M: Igor Opaniuk <igor.opaniuk@gmail.com>
-R: Sam Protsenko <joe.skb7@gmail.com>
+R: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
+F: boot/android_ab.c
F: cmd/ab_select.c
-F: common/android_ab.c
F: doc/android/ab.rst
F: include/android_ab.h
F: test/py/tests/test_android/test_ab.py
@@ -117,12 +117,13 @@
APPLE M1 SOC SUPPORT
M: Mark Kettenis <kettenis@openbsd.org>
S: Maintained
-F: arch/arm/include/asm/arch-m1/
+F: arch/arm/include/asm/arch-apple/
F: arch/arm/mach-apple/
F: configs/apple_m1_defconfig
F: drivers/iommu/apple_dart.c
F: drivers/nvme/nvme_apple.c
F: drivers/pci/pcie_apple.c
+F: drivers/phy/phy-apple-atc.c
F: drivers/pinctrl/pinctrl-apple.c
F: drivers/watchdog/apple_wdt.c
F: include/configs/apple.h
@@ -160,6 +161,7 @@
F: drivers/adc/meson-saradc.c
F: drivers/phy/meson*
F: drivers/mmc/meson_gx_mmc.c
+F: drivers/sm/meson-sm.c
F: drivers/spi/meson_spifc.c
F: drivers/pinctrl/meson/
F: drivers/power/domain/meson-gx-pwrc-vpu.c
@@ -298,7 +300,9 @@
F: arch/arm/include/asm/mach-imx/
F: board/freescale/*mx*/
F: board/freescale/common/
+F: common/spl/spl_imx_container.c
F: drivers/serial/serial_mxc.c
+F: include/imx_container.h
ARM HISILICON
M: Peter Griffin <peter.griffin@linaro.org>
@@ -563,7 +567,9 @@
F: arch/arm/dts/am335x-sancloud*
ARM SNAPDRAGON
-M: Ramon Fried <rfried.dev@gmail.com>
+M: Caleb Connolly <caleb.connolly@linaro.org>
+M: Neil Armstrong <neil.armstrong@linaro.org>
+R: Sumit Garg <sumit.garg@linaro.org>
S: Maintained
F: arch/arm/mach-snapdragon/
F: drivers/gpio/msm_gpio.c
@@ -621,7 +627,7 @@
F: drivers/remoteproc/stm32_copro.c
F: drivers/reset/stm32-reset.c
F: drivers/rng/optee_rng.c
-F: drivers/rng/stm32mp1_rng.c
+F: drivers/rng/stm32_rng.c
F: drivers/rtc/stm32_rtc.c
F: drivers/serial/serial_stm32.*
F: drivers/spi/stm32_qspi.c
@@ -661,11 +667,15 @@
F: tools/sunxi*
ARM TEGRA
-M: Tom Warren <twarren@nvidia.com>
+M: Thierry Reding <treding@nvidia.com>
+M: Svyatoslav Ryhel <clamor95@gmail.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-tegra.git
-F: arch/arm/mach-tegra/
+F: arch/arm/dts/tegra*
F: arch/arm/include/asm/arch-tegra*/
+F: arch/arm/mach-tegra/
+F: drivers/*/tegra*
+F: drivers/*/tegra*/
ARM TI
M: Tom Rini <trini@konsulko.com>
@@ -681,6 +691,7 @@
F: arch/arm/include/asm/ti-common/
F: board/ti/
F: drivers/dma/ti*
+F: drivers/dma/ti*/
F: drivers/firmware/ti_sci.*
F: drivers/gpio/omap_gpio.c
F: drivers/memory/ti-aemif.c
@@ -692,6 +703,7 @@
F: drivers/phy/phy-ti-am654.c
F: drivers/phy/ti-pipe3-phy.c
F: drivers/ram/k3*
+F: drivers/ram/k3*/
F: drivers/remoteproc/ipu_rproc.c
F: drivers/remoteproc/k3_system_controller.c
F: drivers/remoteproc/pruc_rpoc.c
@@ -944,6 +956,7 @@
DFU
M: Lukasz Majewski <lukma@denx.de>
+M: Mattijs Korpershoek <mkorpershoek@baylibre.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-dfu.git
F: cmd/dfu.c
@@ -1019,8 +1032,10 @@
M: Joe Hershberger <joe.hershberger@ni.com>
S: Maintained
F: env/
+F: include/env/
F: include/env*
F: test/env/
+F: tools/env/
F: tools/env*
F: tools/mkenvimage.c
@@ -1050,7 +1065,8 @@
F: test/py/tests/test_event_dump.py
FASTBOOT
-S: Orphaned
+M: Mattijs Korpershoek <mkorpershoek@baylibre.com>
+S: Maintained
F: cmd/fastboot.c
F: doc/android/fastboot*.rst
F: include/fastboot.h
@@ -1517,7 +1533,6 @@
F: test/py/tests/test_stackprotector.py
TARGET_BCMNS3
-M: Bharat Gooty <bharat.gooty@broadcom.com>
M: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
S: Maintained
F: board/broadcom/bcmns3/
@@ -1547,7 +1562,6 @@
F: arch/arm/mach-omap2/sec-common.c
F: arch/arm/mach-omap2/config_secure.mk
F: arch/arm/mach-k3/security.c
-F: arch/arm/mach-k3/config_secure.mk
F: configs/am335x_hs_evm_defconfig
F: configs/am335x_hs_evm_uart_defconfig
F: configs/am43xx_hs_evm_defconfig
@@ -1560,8 +1574,6 @@
F: configs/k2e_hs_evm_defconfig
F: configs/k2g_hs_evm_defconfig
F: configs/k2l_hs_evm_defconfig
-F: configs/am65x_hs_evm_r5_defconfig
-F: configs/am65x_hs_evm_a53_defconfig
TPM DRIVERS
M: Ilias Apalodimas <ilias.apalodimas@linaro.org>
diff --git a/Makefile b/Makefile
index 0e5b189..0724819 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
-VERSION = 2023
-PATCHLEVEL = 10
+VERSION = 2024
+PATCHLEVEL = 01
SUBLEVEL =
EXTRAVERSION =
NAME =
@@ -490,6 +490,15 @@
export RCS_TAR_IGNORE := --exclude SCCS --exclude BitKeeper --exclude .svn \
--exclude CVS --exclude .pc --exclude .hg --exclude .git
+export PYTHON_ENABLE
+
+# This is y if U-Boot should not build any Python tools or libraries. Typically
+# you would need to set this if those tools/libraries (typically binman and
+# pylibfdt) cannot be built by your environment and are provided separately.
+ifeq ($(NO_PYTHON),)
+PYTHON_ENABLE=y
+endif
+
# ===========================================================================
# Rules shared between *config targets and build targets
@@ -882,7 +891,7 @@
libs-$(CONFIG_UT_OPTEE) += test/optee/
libs-$(CONFIG_UT_OVERLAY) += test/overlay/
-libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/)
+libs-y += $(if $(wildcard $(srctree)/board/$(BOARDDIR)/Makefile),board/$(BOARDDIR)/)
libs-y := $(sort $(libs-y))
@@ -1295,7 +1304,7 @@
fi
ifeq ($(CONFIG_INIT_SP_RELATIVE)$(CONFIG_OF_SEPARATE),yy)
-ifneq ($(CONFIG_SYS_MALLOC_F_LEN),)
+ifneq ($(CONFIG_SYS_MALLOC_F),)
subtract_sys_malloc_f_len = space=$$(($${space} - $(CONFIG_SYS_MALLOC_F_LEN)))
else
subtract_sys_malloc_f_len = true
@@ -1375,14 +1384,6 @@
u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE
$(call if_changed,objcopy)
-#
-# U-Boot entry point, needed for booting of full-blown U-Boot
-# from the SPL U-Boot version.
-#
-ifndef CFG_SYS_UBOOT_START
-CFG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE)
-endif
-
# Boards with more complex image requirements can provide an .its source file
# or a generator script
# NOTE: Please do not use this. We are migrating away from Makefile rules to use
@@ -1405,7 +1406,7 @@
ifdef CONFIG_SPL_LOAD_FIT
MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-p $(CONFIG_FIT_EXTERNAL_OFFSET) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(DEVICE_TREE))) \
@@ -1413,10 +1414,10 @@
$(patsubst %,-b arch/$(ARCH)/dts/%.dtbo,$(subst ",,$(CONFIG_OF_OVERLAY_LIST)))
else
MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
MKIMAGEFLAGS_u-boot-ivt.img = -A $(ARCH) -T firmware_ivt -C none -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
u-boot-ivt.img: MKIMAGEOUTPUT = u-boot-ivt.img.log
endif
@@ -1447,7 +1448,7 @@
UBOOT_BIN := u-boot.bin
MKIMAGEFLAGS_u-boot-lzma.img = -A $(ARCH) -T standalone -C lzma -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
u-boot.bin.lzma: u-boot.bin FORCE
@@ -1850,7 +1851,7 @@
touch $@ ; \
fi
-include/generated/env.txt: $(wildcard $(ENV_FILE))
+include/generated/env.txt: $(wildcard $(ENV_FILE)) include/generated/autoconf.h
$(call cmd,envc)
# Write out the resulting environment, converted to a C string
@@ -2175,16 +2176,16 @@
$(foreach d, spl tpl vpl, $(patsubst %,$d/%, \
$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
-CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
- include/generated/env.* drivers/video/u_boot_logo.S \
+CLEAN_FILES += include/autoconf.mk* include/bmp_logo.h include/bmp_logo_data.h \
+ include/config.h include/generated/env.* drivers/video/u_boot_logo.S \
tools/version.h u-boot* MLO* SPL System.map fit-dtb.blob* \
u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \
lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \
idbloader.img flash.bin flash.log defconfig keep-syms-lto.c \
mkimage-out.spl.mkimage mkimage.spl.mkimage imx-boot.map \
itb.fit.fit itb.fit.itb itb.map spl.map mkimage-out.rom.mkimage \
- mkimage.rom.mkimage rom.map simple-bin.map simple-bin-spi.map \
- idbloader-spi.img lib/efi_loader/helloworld_efi.S
+ mkimage.rom.mkimage mkimage-in-simple-bin* rom.map simple-bin* \
+ idbloader-spi.img lib/efi_loader/helloworld_efi.S *.itb
# ANDROID: bl31.elf was checked into Git so it isn't an artifact that needs rm
ifneq (,$(shell grep '^!bl31.elf$$' "$(srctree)/.gitignore"))
@@ -2471,7 +2472,7 @@
sed -e '/^\s*$$/d' | \
sort -t '=' -k 1,1 -s -o $@
-u-boot-initial-env: $(env_h) FORCE
+u-boot-initial-env: scripts_basic $(env_h) FORCE
$(Q)$(MAKE) $(build)=tools $(objtree)/tools/printinitialenv
$(call if_changed,genenv)
diff --git a/README b/README
index 4663a5e..f7ac43f 100644
--- a/README
+++ b/README
@@ -1305,24 +1305,6 @@
- CONFIG_SYS_MALLOC_LEN:
Size of DRAM reserved for malloc() use.
-- CONFIG_SYS_MALLOC_F_LEN
- Size of the malloc() pool for use before relocation. If
- this is defined, then a very simple malloc() implementation
- will become available before relocation. The address is just
- below the global data, and the stack is moved down to make
- space.
-
- This feature allocates regions with increasing addresses
- within the region. calloc() is supported, but realloc()
- is not available. free() is supported but does nothing.
- The memory will be freed (or in fact just forgotten) when
- U-Boot relocates itself.
-
-- CONFIG_SYS_MALLOC_SIMPLE
- Provides a simple and small malloc() and calloc() for those
- boards which do not use the full malloc in SPL (which is
- enabled with CONFIG_SYS_SPL_MALLOC).
-
- CFG_SYS_BOOTMAPSZ:
Maximum size of memory mapped by the startup code of
the Linux kernel; all data that must be processed by
diff --git a/arch/Kconfig b/arch/Kconfig
index c9a3359..4f5b751 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -68,7 +68,6 @@
bool "M68000 architecture"
select HAVE_PRIVATE_LIBGCC
select USE_PRIVATE_LIBGCC
- select NEEDS_MANUAL_RELOC
select SYS_BOOT_GET_CMDLINE
select SYS_BOOT_GET_KBD
select SYS_CACHE_SHIFT_4
@@ -209,6 +208,8 @@
imply PHYSMEM
imply GENERATE_ACPI_TABLE
imply BINMAN
+ imply CMD_MBR
+ imply CMD_MMC
config SH
bool "SuperH architecture"
@@ -252,6 +253,7 @@
imply DM_SPI
imply DM_SPI_FLASH
imply DM_USB
+ imply LAST_STAGE_INIT
imply VIDEO
imply SYSRESET
imply SPL_SYSRESET
diff --git a/arch/arc/include/asm/sections.h b/arch/arc/include/asm/sections.h
index 1c9c9db..ffad4a6 100644
--- a/arch/arc/include/asm/sections.h
+++ b/arch/arc/include/asm/sections.h
@@ -8,7 +8,8 @@
#include <asm-generic/sections.h>
-extern ulong __ivt_start;
-extern ulong __ivt_end;
+extern char __ivt_start[];
+extern char __ivt_end[];
+extern char __text_end[];
#endif /* __ASM_ARC_SECTIONS_H */
diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c
index 2dd0034..44ec586 100644
--- a/arch/arc/lib/bootm.c
+++ b/arch/arc/lib/bootm.c
@@ -3,7 +3,6 @@
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
*/
-#include <common.h>
#include <bootstage.h>
#include <env.h>
#include <image.h>
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
index d97a578..22e7488 100644
--- a/arch/arc/lib/cache.c
+++ b/arch/arc/lib/cache.c
@@ -4,7 +4,6 @@
*/
#include <config.h>
-#include <common.h>
#include <cpu_func.h>
#include <asm/global_data.h>
#include <linux/bitops.h>
diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c
index 1567857..803dfd4 100644
--- a/arch/arc/lib/cpu.c
+++ b/arch/arc/lib/cpu.c
@@ -3,7 +3,6 @@
* Copyright (C) 2013-2014, 2018 Synopsys, Inc. All rights reserved.
*/
-#include <common.h>
#include <clock_legacy.h>
#include <init.h>
#include <malloc.h>
diff --git a/arch/arc/lib/init_helpers.c b/arch/arc/lib/init_helpers.c
index 023eae1..858b388 100644
--- a/arch/arc/lib/init_helpers.c
+++ b/arch/arc/lib/init_helpers.c
@@ -5,7 +5,6 @@
#include <init.h>
#include <asm/cache.h>
-#include <common.h>
int init_cache_f_r(void)
{
diff --git a/arch/arc/lib/interrupts.c b/arch/arc/lib/interrupts.c
index db21fbb..523b44c 100644
--- a/arch/arc/lib/interrupts.c
+++ b/arch/arc/lib/interrupts.c
@@ -3,8 +3,8 @@
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
*/
-#include <common.h>
#include <irq_func.h>
+#include <vsprintf.h>
#include <asm/arcregs.h>
#include <asm/ptrace.h>
diff --git a/arch/arc/lib/relocate.c b/arch/arc/lib/relocate.c
index 7f531c9..95b6d51 100644
--- a/arch/arc/lib/relocate.c
+++ b/arch/arc/lib/relocate.c
@@ -3,35 +3,29 @@
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
*/
-#include <common.h>
#include <elf.h>
#include <log.h>
-#include <asm-generic/sections.h>
+#include <asm/sections.h>
#include <asm/global_data.h>
-extern ulong __image_copy_start;
-extern ulong __ivt_start;
-extern ulong __ivt_end;
-extern ulong __text_end;
-
DECLARE_GLOBAL_DATA_PTR;
int copy_uboot_to_ram(void)
{
- size_t len = (size_t)&__image_copy_end - (size_t)&__image_copy_start;
+ size_t len = (size_t)__image_copy_end - (size_t)__image_copy_start;
if (gd->flags & GD_FLG_SKIP_RELOC)
return 0;
- memcpy((void *)gd->relocaddr, (void *)&__image_copy_start, len);
+ memcpy((void *)gd->relocaddr, (void *)__image_copy_start, len);
return 0;
}
int clear_bss(void)
{
- ulong dst_addr = (ulong)&__bss_start + gd->reloc_off;
- size_t len = (size_t)&__bss_end - (size_t)&__bss_start;
+ ulong dst_addr = (ulong)__bss_start + gd->reloc_off;
+ size_t len = (size_t)__bss_end - (size_t)__bss_start;
memset((void *)dst_addr, 0x00, len);
@@ -43,8 +37,8 @@
*/
int do_elf_reloc_fixups(void)
{
- Elf32_Rela *re_src = (Elf32_Rela *)(&__rel_dyn_start);
- Elf32_Rela *re_end = (Elf32_Rela *)(&__rel_dyn_end);
+ Elf32_Rela *re_src = (Elf32_Rela *)__rel_dyn_start;
+ Elf32_Rela *re_end = (Elf32_Rela *)__rel_dyn_end;
if (gd->flags & GD_FLG_SKIP_RELOC)
return 0;
@@ -60,8 +54,8 @@
offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
/* Check that the location of the relocation is in .text */
- if (offset_ptr_rom >= (Elf32_Addr *)&__image_copy_start &&
- offset_ptr_rom < (Elf32_Addr *)&__image_copy_end) {
+ if (offset_ptr_rom >= (Elf32_Addr *)__image_copy_start &&
+ offset_ptr_rom < (Elf32_Addr *)__image_copy_end) {
unsigned int val, do_swap = 0;
/* Switch to the in-RAM version */
offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom +
@@ -69,11 +63,11 @@
#ifdef __LITTLE_ENDIAN__
/* If location in ".text" section swap value */
- if (((u32)offset_ptr_rom >= (u32)&__text_start &&
- (u32)offset_ptr_rom <= (u32)&__text_end)
+ if (((u32)offset_ptr_rom >= (u32)__text_start &&
+ (u32)offset_ptr_rom <= (u32)__text_end)
#if defined(__ARC700__) || defined(__ARC600__)
- || ((u32)offset_ptr_rom >= (u32)&__ivt_start &&
- (u32)offset_ptr_rom <= (u32)&__ivt_end)
+ || ((u32)offset_ptr_rom >= (u32)__ivt_start &&
+ (u32)offset_ptr_rom <= (u32)__ivt_end)
#endif
)
do_swap = 1;
@@ -96,8 +90,8 @@
val = (val << 16) | (val >> 16);
/* Check that the target points into executable */
- if (val < (unsigned int)&__image_copy_start ||
- val > (unsigned int)&__image_copy_end) {
+ if (val < (unsigned int)__image_copy_start ||
+ val > (unsigned int)__image_copy_end) {
/* TODO: Use panic() instead of debug()
*
* For some reason GCC might generate
@@ -106,7 +100,7 @@
* ----------------------->8--------------------
* static int setup_mon_len(void)
* {
- * gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
+ * gd->mon_len = (ulong)__bss_end - CONFIG_SYS_MONITOR_BASE;
* return 0;
* }
* ----------------------->8--------------------
diff --git a/arch/arc/lib/reset.c b/arch/arc/lib/reset.c
index b8589d0..fa60fa9 100644
--- a/arch/arc/lib/reset.c
+++ b/arch/arc/lib/reset.c
@@ -4,7 +4,6 @@
*/
#include <command.h>
-#include <common.h>
#include <cpu_func.h>
__weak void reset_cpu(void)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 328e2dd..d812685 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -787,6 +787,7 @@
select FIT
select REGEX
select FIT_SIGNATURE if ARM64
+ imply TI_SECURE_DEVICE
config ARCH_OMAP2PLUS
bool "TI OMAP2+"
@@ -998,6 +999,7 @@
select OF_BOARD_SETUP
select OF_CONTROL
select PCI
+ select PHY
select PINCTRL
select POSITION_INDEPENDENT
select POWER_DOMAIN
@@ -1036,6 +1038,16 @@
imply DM_RTC
imply RTC_PL031
imply OF_HAS_PRIOR_STAGE
+ imply VIDEO
+ imply VIDEO_BOCHS
+ imply SYS_WHITE_ON_BLACK
+ imply SYS_CONSOLE_IS_IN_ENV
+ imply PRE_CONSOLE_BUFFER
+ imply USB
+ imply USB_XHCI_HCD
+ imply USB_XHCI_PCI
+ imply USB_KEYBOARD
+ imply CMD_USB
config ARCH_RMOBILE
bool "Renesas ARM SoCs"
@@ -1123,7 +1135,6 @@
select DM_MMC if MMC
select DM_SCSI if SCSI
select DM_SERIAL
- select GPIO_EXTRA_HEADER
select OF_BOARD_SETUP
select OF_CONTROL
select OF_SEPARATE
@@ -1147,6 +1158,8 @@
imply CMD_GPT
imply CMD_UBI if MTD_RAW_NAND
imply DISTRO_DEFAULTS
+ imply DM_REGULATOR
+ imply DM_REGULATOR_FIXED
imply FAT_WRITE
imply FIT
imply OF_LIBFDT_OVERLAY
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index 4d21e3d..6d6166c 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -100,7 +100,7 @@
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
- mx28_fixup_vt((uint32_t)&_start);
+ mx28_fixup_vt((uint32_t)_start);
/*
* Enable NAND clock
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index 5598c55..5e7bdb7 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -103,7 +103,7 @@
*/
/* cppcheck-suppress nullPointer */
- memcpy(0x0, &_start, 0x60);
+ memcpy(0x0, _start, 0x60);
}
static void mxs_spl_console_init(void)
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index ccc2f20..4eb34b7 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -58,6 +58,17 @@
default 0x3c00 if MACH_SUN8I && MACH_SUN8I_H3
default 0x10000
+config ARM_GIC_BASE_ADDRESS
+ hex
+ depends on ARMV7_NONSEC
+ depends on ARCH_EXYNOS5 || MACH_SUN8I_R528
+ default 0x10480000 if ARCH_EXYNOS5
+ default 0x03020000 if MACH_SUN8I_R528
+ help
+ Override the GIC base address if the Arm Cortex defined
+ CBAR/PERIPHBASE system register holds the wrong value.
+ Used by the PSCI code to configure the secure side of the GIC.
+
config ARMV7_VIRT
bool "Enable support for hardware virtualization" if EXPERT
depends on CPU_V7_HAS_VIRT && ARMV7_NONSEC
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 3e292bf..46ace7e 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -98,7 +98,6 @@
config SYS_FSL_QSPI_SKIP_CLKSEL
bool "Skip setting QSPI clock during SoC init"
- default 0
help
To improve startup times when booting from QSPI flash, the QSPI
frequency can be set very early in the boot process. If this option
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index a5c5c78..1c3d24b 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -136,7 +136,7 @@
*/
off = fdt_add_mem_rsv(blob, CONFIG_TEXT_BASE - UBOOT_HEAD_LEN,
CONFIG_SYS_MONITOR_LEN +
- CONFIG_SYS_SPL_MALLOC_SIZE + UBOOT_HEAD_LEN);
+ CONFIG_SPL_SYS_MALLOC_SIZE + UBOOT_HEAD_LEN);
if (off < 0)
printf("Failed to reserve memory for SD boot deep sleep: %s\n",
fdt_strerror(off));
diff --git a/arch/arm/cpu/armv7/mpu_v7r.c b/arch/arm/cpu/armv7/mpu_v7r.c
index 57ab640..1d31c63 100644
--- a/arch/arm/cpu/armv7/mpu_v7r.c
+++ b/arch/arm/cpu/armv7/mpu_v7r.c
@@ -2,7 +2,7 @@
/*
* Cortex-R Memory Protection Unit specific code
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 9004074..bed40fa 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -112,8 +112,8 @@
ENDPROC(_do_nonsec_entry)
.macro get_cbar_addr addr
-#ifdef CFG_ARM_GIC_BASE_ADDRESS
- ldr \addr, =CFG_ARM_GIC_BASE_ADDRESS
+#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
+ ldr \addr, =CONFIG_ARM_GIC_BASE_ADDRESS
#else
mrc p15, 4, \addr, c15, c0, 0 @ read CBAR
bfc \addr, #0, #15 @ clear reserved bits
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index e1d3638..5cb8cfa 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.c
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -11,8 +11,6 @@
#include <asm/cache.h>
#include <asm/arch/cpu.h>
-#include <asm/arch/cpucfg.h>
-#include <asm/arch/prcm.h>
#include <asm/armv7.h>
#include <asm/gic.h>
#include <asm/io.h>
@@ -28,6 +26,17 @@
#define GICC_BASE (SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
/*
+ * Offsets into the CPUCFG block applicable to most SUNXIs.
+ */
+#define SUNXI_CPU_RST(cpu) (0x40 + (cpu) * 0x40 + 0x0)
+#define SUNXI_CPU_STATUS(cpu) (0x40 + (cpu) * 0x40 + 0x8)
+#define SUNXI_GEN_CTRL (0x184)
+#define SUNXI_PRIV0 (0x1a4)
+#define SUN7I_CPU1_PWR_CLAMP (0x1b0)
+#define SUN7I_CPU1_PWROFF (0x1b4)
+#define SUNXI_DBG_CTRL1 (0x1e4)
+
+/*
* R40 is different from other single cluster SoCs.
*
* The power clamps are located in the unused space after the per-core
@@ -38,6 +47,24 @@
#define SUN8I_R40_PWR_CLAMP(cpu) (0x120 + (cpu) * 0x4)
#define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0 (0xbc)
+/*
+ * R528 is also different, as it has both cores powered up (but held in reset
+ * state) after the SoC is reset. Like the R40, it uses a "soft" entry point
+ * address register, but unlike the R40, it uses a newer "CPUX" block to manage
+ * CPU state, rather than the older CPUCFG system.
+ */
+#define SUN8I_R528_SOFT_ENTRY (0x1c8)
+#define SUN8I_R528_C0_RST_CTRL (0x0000)
+#define SUN8I_R528_C0_CTRL_REG0 (0x0010)
+#define SUN8I_R528_C0_CPU_STATUS (0x0080)
+
+#define SUN8I_R528_C0_STATUS_STANDBYWFI (16)
+
+/* Only newer cores have this additional IP block. */
+#ifndef SUNXI_R_CPUCFG_BASE
+#define SUNXI_R_CPUCFG_BASE 0
+#endif
+
static void __secure cp15_write_cntp_tval(u32 tval)
{
asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
@@ -76,11 +103,8 @@
isb();
}
-static void __secure clamp_release(u32 __maybe_unused *clamp)
+static void __secure clamp_release(u32 *clamp)
{
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
- defined(CONFIG_MACH_SUN8I_H3) || \
- defined(CONFIG_MACH_SUN8I_R40)
u32 tmp = 0x1ff;
do {
tmp >>= 1;
@@ -88,24 +112,54 @@
} while (tmp);
__mdelay(10);
-#endif
}
-static void __secure clamp_set(u32 __maybe_unused *clamp)
+static void __secure clamp_set(u32 *clamp)
{
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
- defined(CONFIG_MACH_SUN8I_H3) || \
- defined(CONFIG_MACH_SUN8I_R40)
writel(0xff, clamp);
-#endif
}
-static void __secure sunxi_power_switch(u32 *clamp, u32 *pwroff, bool on,
- int cpu)
+static void __secure sunxi_cpu_set_entry(int __always_unused cpu, void *entry)
{
+ if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) {
+ writel((u32)entry,
+ SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
+ } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
+ writel((u32)entry,
+ SUNXI_R_CPUCFG_BASE + SUN8I_R528_SOFT_ENTRY);
+ } else {
+ writel((u32)entry, SUNXI_CPUCFG_BASE + SUNXI_PRIV0);
+ }
+}
+
+static void __secure sunxi_cpu_set_power(int cpu, bool on)
+{
+ u32 *clamp = NULL;
+ u32 *pwroff;
+
+ /* sun7i (A20) is different from other single cluster SoCs */
+ if (IS_ENABLED(CONFIG_MACH_SUN7I)) {
+ clamp = (void *)SUNXI_CPUCFG_BASE + SUN7I_CPU1_PWR_CLAMP;
+ pwroff = (void *)SUNXI_CPUCFG_BASE + SUN7I_CPU1_PWROFF;
+ cpu = 0;
+ } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) {
+ clamp = (void *)SUNXI_CPUCFG_BASE + SUN8I_R40_PWR_CLAMP(cpu);
+ pwroff = (void *)SUNXI_CPUCFG_BASE + SUN8I_R40_PWROFF;
+ } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
+ /* R528 leaves both cores powered up, manages them via reset */
+ return;
+ } else {
+ if (IS_ENABLED(CONFIG_MACH_SUN6I) ||
+ IS_ENABLED(CONFIG_MACH_SUN8I_H3))
+ clamp = (void *)SUNXI_PRCM_BASE + 0x140 + cpu * 0x4;
+
+ pwroff = (void *)SUNXI_PRCM_BASE + 0x100;
+ }
+
if (on) {
/* Release power clamp */
- clamp_release(clamp);
+ if (clamp)
+ clamp_release(clamp);
/* Clear power gating */
clrbits_le32(pwroff, BIT(cpu));
@@ -114,82 +168,80 @@
setbits_le32(pwroff, BIT(cpu));
/* Activate power clamp */
- clamp_set(clamp);
+ if (clamp)
+ clamp_set(clamp);
}
}
-#ifdef CONFIG_MACH_SUN8I_R40
-/* secondary core entry address is programmed differently on R40 */
-static void __secure sunxi_set_entry_address(void *entry)
+static void __secure sunxi_cpu_set_reset(int cpu, bool reset)
{
- writel((u32)entry,
- SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
+ if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
+ if (reset)
+ clrbits_le32(SUNXI_CPUCFG_BASE + SUN8I_R528_C0_RST_CTRL,
+ BIT(cpu));
+ else
+ setbits_le32(SUNXI_CPUCFG_BASE + SUN8I_R528_C0_RST_CTRL,
+ BIT(cpu));
+
+ return;
+ }
+
+ writel(reset ? 0b00 : 0b11, SUNXI_CPUCFG_BASE + SUNXI_CPU_RST(cpu));
}
-#else
-static void __secure sunxi_set_entry_address(void *entry)
-{
- struct sunxi_cpucfg_reg *cpucfg =
- (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
- writel((u32)entry, &cpucfg->priv0);
+static void __secure sunxi_cpu_set_locking(int cpu, bool lock)
+{
+ if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
+ /* Not required on R528 */
+ return;
+ }
+
+ if (lock)
+ clrbits_le32(SUNXI_CPUCFG_BASE + SUNXI_DBG_CTRL1, BIT(cpu));
+ else
+ setbits_le32(SUNXI_CPUCFG_BASE + SUNXI_DBG_CTRL1, BIT(cpu));
}
-#endif
-#ifdef CONFIG_MACH_SUN7I
-/* sun7i (A20) is different from other single cluster SoCs */
-static void __secure sunxi_cpu_set_power(int __always_unused cpu, bool on)
+static bool __secure sunxi_cpu_poll_wfi(int cpu)
{
- struct sunxi_cpucfg_reg *cpucfg =
- (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+ if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
+ return !!(readl(SUNXI_CPUCFG_BASE + SUN8I_R528_C0_CPU_STATUS) &
+ BIT(SUN8I_R528_C0_STATUS_STANDBYWFI + cpu));
+ }
- sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff,
- on, 0);
+ return !!(readl(SUNXI_CPUCFG_BASE + SUNXI_CPU_STATUS(cpu)) & BIT(2));
}
-#elif defined CONFIG_MACH_SUN8I_R40
-static void __secure sunxi_cpu_set_power(int cpu, bool on)
-{
- struct sunxi_cpucfg_reg *cpucfg =
- (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
- sunxi_power_switch((void *)cpucfg + SUN8I_R40_PWR_CLAMP(cpu),
- (void *)cpucfg + SUN8I_R40_PWROFF,
- on, cpu);
+static void __secure sunxi_cpu_invalidate_cache(int cpu)
+{
+ if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
+ clrbits_le32(SUNXI_CPUCFG_BASE + SUN8I_R528_C0_CTRL_REG0,
+ BIT(cpu));
+ return;
+ }
+
+ clrbits_le32(SUNXI_CPUCFG_BASE + SUNXI_GEN_CTRL, BIT(cpu));
}
-#else /* ! CONFIG_MACH_SUN7I && ! CONFIG_MACH_SUN8I_R40 */
-static void __secure sunxi_cpu_set_power(int cpu, bool on)
-{
- struct sunxi_prcm_reg *prcm =
- (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
- sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff,
- on, cpu);
-}
-#endif /* CONFIG_MACH_SUN7I */
-
-void __secure sunxi_cpu_power_off(u32 cpuid)
+static void __secure sunxi_cpu_power_off(u32 cpuid)
{
- struct sunxi_cpucfg_reg *cpucfg =
- (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
u32 cpu = cpuid & 0x3;
/* Wait for the core to enter WFI */
- while (1) {
- if (readl(&cpucfg->cpu[cpu].status) & BIT(2))
- break;
+ while (!sunxi_cpu_poll_wfi(cpu))
__mdelay(1);
- }
/* Assert reset on target CPU */
- writel(0, &cpucfg->cpu[cpu].rst);
+ sunxi_cpu_set_reset(cpu, true);
/* Lock CPU (Disable external debug access) */
- clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
+ sunxi_cpu_set_locking(cpu, true);
/* Power down CPU */
sunxi_cpu_set_power(cpuid, false);
- /* Unlock CPU (Disable external debug access) */
- setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
+ /* Unlock CPU (Reenable external debug access) */
+ sunxi_cpu_set_locking(cpu, false);
}
static u32 __secure cp15_read_scr(void)
@@ -246,33 +298,31 @@
int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc,
u32 context_id)
{
- struct sunxi_cpucfg_reg *cpucfg =
- (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
u32 cpu = (mpidr & 0x3);
/* store target PC and context id */
psci_save(cpu, pc, context_id);
/* Set secondary core power on PC */
- sunxi_set_entry_address(&psci_cpu_entry);
+ sunxi_cpu_set_entry(cpu, &psci_cpu_entry);
/* Assert reset on target CPU */
- writel(0, &cpucfg->cpu[cpu].rst);
+ sunxi_cpu_set_reset(cpu, true);
/* Invalidate L1 cache */
- clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu));
+ sunxi_cpu_invalidate_cache(cpu);
/* Lock CPU (Disable external debug access) */
- clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
+ sunxi_cpu_set_locking(cpu, true);
/* Power up target CPU */
sunxi_cpu_set_power(cpu, true);
/* De-assert reset on target CPU */
- writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);
+ sunxi_cpu_set_reset(cpu, false);
- /* Unlock CPU (Disable external debug access) */
- setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
+ /* Unlock CPU (Reenable external debug access) */
+ sunxi_cpu_set_locking(cpu, false);
return ARM_PSCI_RET_SUCCESS;
}
diff --git a/arch/arm/cpu/armv7/sunxi/sram.c b/arch/arm/cpu/armv7/sunxi/sram.c
index 28564c2..28ff6a1 100644
--- a/arch/arm/cpu/armv7/sunxi/sram.c
+++ b/arch/arm/cpu/armv7/sunxi/sram.c
@@ -12,6 +12,7 @@
#include <common.h>
#include <init.h>
#include <asm/io.h>
+#include <asm/arch/cpu.h>
void sunxi_sram_init(void)
{
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index c82b215..5ffeca1 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -26,8 +26,8 @@
static unsigned long get_gicd_base_address(void)
{
-#ifdef CFG_ARM_GIC_BASE_ADDRESS
- return CFG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
+#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
+ return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
#else
unsigned periphbase;
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 0b94707..b55a423 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -93,16 +93,10 @@
if (el == 1) {
tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
- if (gd->arch.has_hafdbs)
- tcr |= TCR_EL1_HA | TCR_EL1_HD;
} else if (el == 2) {
tcr = TCR_EL2_RSVD | (ips << 16);
- if (gd->arch.has_hafdbs)
- tcr |= TCR_EL2_HA | TCR_EL2_HD;
} else {
tcr = TCR_EL3_RSVD | (ips << 16);
- if (gd->arch.has_hafdbs)
- tcr |= TCR_EL3_HA | TCR_EL3_HD;
}
/* PTWs cacheable, inner/outer WBWA and inner shareable */
@@ -206,9 +200,6 @@
attrs != PTE_BLOCK_MEMTYPE(MT_NORMAL_NC))
continue;
- if (gd->arch.has_hafdbs && (pte & (PTE_RDONLY | PTE_DBM)) != PTE_DBM)
- continue;
-
end = va + BIT(level2shift(level)) - 1;
/* No intersection with RAM? */
@@ -318,7 +309,7 @@
for (i = idx; size; i++) {
u64 next_size, *next_table;
- if (level >= gd->arch.first_block_level &&
+ if (level >= 1 &&
size >= map_size && !(virt & (map_size - 1))) {
if (level == 3)
table[i] = phys | attrs | PTE_TYPE_PAGE;
@@ -357,12 +348,6 @@
if (va_bits < 39)
level = 1;
- if (!gd->arch.first_block_level)
- gd->arch.first_block_level = 1;
-
- if (gd->arch.has_hafdbs)
- attrs |= PTE_DBM | PTE_RDONLY;
-
map_range(map->virt, map->phys, map->size, level,
(u64 *)gd->arch.tlb_addr, attrs);
}
@@ -376,7 +361,7 @@
for (i = idx; size; i++) {
u64 next_size;
- if (level >= gd->arch.first_block_level &&
+ if (level >= 1 &&
size >= map_size && !(virt & (map_size - 1))) {
virt += map_size;
size -= map_size;
@@ -414,16 +399,7 @@
__weak u64 get_page_table_size(void)
{
u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
- u64 size, mmfr1;
-
- asm volatile("mrs %0, id_aa64mmfr1_el1" : "=r" (mmfr1));
- if ((mmfr1 & 0xf) == 2) {
- gd->arch.has_hafdbs = true;
- gd->arch.first_block_level = 2;
- } else {
- gd->arch.has_hafdbs = false;
- gd->arch.first_block_level = 1;
- }
+ u64 size;
/* Account for all page tables we would need to cover our memory map */
size = one_pt * count_ranges();
diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S
index 2fe38a1..939869b 100644
--- a/arch/arm/cpu/armv8/fel_utils.S
+++ b/arch/arm/cpu/armv8/fel_utils.S
@@ -10,6 +10,7 @@
#include <config.h>
#include <asm/system.h>
#include <linux/linkage.h>
+#include <asm/arch/cpu.h>
/*
* We don't overwrite save_boot_params() here, to save the FEL state upon
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index a8b493e..080fe3f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -390,66 +390,6 @@
bool
default y if ARCH_LS1043A
-menu "Layerscape PPA"
-config FSL_LS_PPA
- bool "FSL Layerscape PPA firmware support"
- depends on !ARMV8_PSCI
- select ARMV8_SEC_FIRMWARE_SUPPORT
- select SEC_FIRMWARE_ARMV8_PSCI
- select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
- help
- The FSL Primary Protected Application (PPA) is a software component
- which is loaded during boot stage, and then remains resident in RAM
- and runs in the TrustZone after boot.
- Say y to enable it.
-
-config SPL_FSL_LS_PPA
- bool "FSL Layerscape PPA firmware support for SPL build"
- depends on !ARMV8_PSCI
- select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
- select SEC_FIRMWARE_ARMV8_PSCI
- select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
- help
- The FSL Primary Protected Application (PPA) is a software component
- which is loaded during boot stage, and then remains resident in RAM
- and runs in the TrustZone after boot. This is to load PPA during SPL
- stage instead of the RAM version of U-Boot. Once PPA is initialized,
- the rest of U-Boot (including RAM version) runs at EL2.
-choice
- prompt "FSL Layerscape PPA firmware loading-media select"
- depends on FSL_LS_PPA
- default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
- default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
- default SYS_LS_PPA_FW_IN_XIP
-
-config SYS_LS_PPA_FW_IN_XIP
- bool "XIP"
- help
- Say Y here if the PPA firmware locate at XIP flash, such
- as NOR or QSPI flash.
-
-config SYS_LS_PPA_FW_IN_MMC
- bool "eMMC or SD Card"
- help
- Say Y here if the PPA firmware locate at eMMC/SD card.
-
-config SYS_LS_PPA_FW_IN_NAND
- bool "NAND"
- help
- Say Y here if the PPA firmware locate at NAND flash.
-
-endchoice
-
-config LS_PPA_ESBC_HDR_SIZE
- hex "Length of PPA ESBC header"
- depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
- default 0x2000
- help
- Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
- NAND to memory to validate PPA image.
-
-endmenu
-
config SYS_FSL_ERRATUM_A008997
bool "Workaround for USB PHY erratum A008997"
@@ -739,7 +679,7 @@
config SYS_FSL_BOOTROM_BASE
hex
depends on FSL_LSCH2
- default 0
+ default 0x0
config SYS_FSL_BOOTROM_SIZE
hex
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 598c36e..eefdf12 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -10,7 +10,6 @@
obj-$(CONFIG_OF_LIBFDT) += fdt.o
endif
obj-$(CONFIG_SPL) += spl.o
-obj-$(CONFIG_$(SPL_)FSL_LS_PPA) += ppa.o
ifneq ($(CONFIG_FSL_LSCH3),)
obj-y += fsl_lsch3_speed.o
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon
index b3c6693..2bbe4e2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon
@@ -30,7 +30,7 @@
leave it absent to favor the stored sectors. It is easier to deploy the FIT
image with embedded static device tree to multiple boards.
-Macro CONFIG_SYS_SPL_ARGS_ADDR serves two purposes. One is the pointer to load
+Macro CONFIG_SPL_PAYLOAD_ARGS_ADDR serves two purposes. One is the pointer to load
the stored sectors to. Normally this is the static device tree. The second
purpose is the memory location of signature header for secure boot. After the
FIT image is loaded into memory, it is validated against the signature header
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
index ad20d71..c22e732 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
@@ -23,8 +23,8 @@
out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
}
-#ifdef CONFIG_SYS_DPAA_FMAN
-void set_fman_icids(struct fman_icid_id_table *tbl, int size)
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
+static void set_fman_icids(struct fman_icid_id_table *tbl, int size)
{
int i;
ccsr_fman_t *fm = (void *)CFG_SYS_FSL_FM1_ADDR;
@@ -71,7 +71,7 @@
return 0;
}
-int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
+static int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
struct icid_id_table *tbl, int size)
{
int i, err, off;
@@ -98,7 +98,7 @@
}
#ifdef CONFIG_SYS_DPAA_FMAN
-int get_fman_port_icid(int port_id, struct fman_icid_id_table *tbl,
+static int get_fman_port_icid(int port_id, struct fman_icid_id_table *tbl,
const int size)
{
int i;
@@ -111,7 +111,7 @@
return -1;
}
-void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph,
+static void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph,
const char *compat)
{
int noff, len, icid;
@@ -140,7 +140,7 @@
}
}
-void fdt_fixup_fman_icids(void *blob, int smmu_ph)
+static void fdt_fixup_fman_icids(void *blob, int smmu_ph)
{
static const char * const compats[] = {
"fsl,fman-v3-port-oh",
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
deleted file mode 100644
index 117b7a0..0000000
--- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
+++ /dev/null
@@ -1,284 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2016 NXP Semiconductor, Inc.
- */
-#include <common.h>
-#include <log.h>
-#include <malloc.h>
-#include <config.h>
-#include <errno.h>
-#include <asm/cache.h>
-#include <asm/global_data.h>
-#include <asm/system.h>
-#include <asm/types.h>
-#include <asm/arch/soc.h>
-#ifdef CONFIG_FSL_LSCH3
-#include <asm/arch/immap_lsch3.h>
-#elif defined(CONFIG_FSL_LSCH2)
-#include <asm/arch/immap_lsch2.h>
-#endif
-#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT)
-#include <asm/armv8/sec_firmware.h>
-#endif
-#ifdef CONFIG_CHAIN_OF_TRUST
-#include <fsl_validate.h>
-#endif
-
-#ifdef CONFIG_SYS_LS_PPA_FW_IN_NAND
-#include <nand.h>
-#elif defined(CONFIG_SYS_LS_PPA_FW_IN_MMC)
-#include <mmc.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int ppa_init(void)
-{
- unsigned int el = current_el();
- void *ppa_fit_addr;
- u32 *boot_loc_ptr_l, *boot_loc_ptr_h;
- u32 *loadable_l, *loadable_h;
- int ret;
-
-#ifdef CONFIG_CHAIN_OF_TRUST
- uintptr_t ppa_esbc_hdr = 0;
- uintptr_t ppa_img_addr = 0;
-#if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \
- defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
- void *ppa_hdr_ddr;
-#endif
-#endif
-
- /* Skip if running at lower exception level */
- if (el < 3) {
- debug("Skipping PPA init, running at EL%d\n", el);
- return 0;
- }
-
-#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
- ppa_fit_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
- debug("%s: PPA image load from XIP\n", __func__);
-#ifdef CONFIG_CHAIN_OF_TRUST
- ppa_esbc_hdr = CONFIG_SYS_LS_PPA_ESBC_ADDR;
-#endif
-#else /* !CONFIG_SYS_LS_PPA_FW_IN_XIP */
- size_t fw_length, fdt_header_len = sizeof(struct fdt_header);
-
- /* Copy PPA image from MMC/SD/NAND to allocated memory */
-#ifdef CONFIG_SYS_LS_PPA_FW_IN_MMC
- struct mmc *mmc;
- int dev = CONFIG_SYS_MMC_ENV_DEV;
- struct fdt_header *fitp;
- u32 cnt;
- u32 blk;
-
- debug("%s: PPA image load from eMMC/SD\n", __func__);
-
- ret = mmc_initialize(gd->bd);
- if (ret) {
- printf("%s: mmc_initialize() failed\n", __func__);
- return ret;
- }
- mmc = find_mmc_device(dev);
- if (!mmc) {
- printf("PPA: MMC cannot find device for PPA firmware\n");
- return -ENODEV;
- }
-
- ret = mmc_init(mmc);
- if (ret) {
- printf("%s: mmc_init() failed\n", __func__);
- return ret;
- }
-
- fitp = malloc(roundup(fdt_header_len, 512));
- if (!fitp) {
- printf("PPA: malloc failed for FIT header(size 0x%zx)\n",
- roundup(fdt_header_len, 512));
- return -ENOMEM;
- }
-
- blk = CONFIG_SYS_LS_PPA_FW_ADDR / 512;
- cnt = DIV_ROUND_UP(fdt_header_len, 512);
- debug("%s: MMC read PPA FIT header: dev # %u, block # %u, count %u\n",
- __func__, dev, blk, cnt);
- ret = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, fitp);
- if (ret != cnt) {
- free(fitp);
- printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n",
- CONFIG_SYS_LS_PPA_FW_ADDR);
- return -EIO;
- }
-
- ret = fdt_check_header(fitp);
- if (ret) {
- free(fitp);
- printf("%s: fdt_check_header() failed\n", __func__);
- return ret;
- }
-
-#ifdef CONFIG_CHAIN_OF_TRUST
- ppa_hdr_ddr = malloc(CONFIG_LS_PPA_ESBC_HDR_SIZE);
- if (!ppa_hdr_ddr) {
- printf("PPA: malloc failed for PPA header\n");
- return -ENOMEM;
- }
-
- blk = CONFIG_SYS_LS_PPA_ESBC_ADDR >> 9;
- cnt = DIV_ROUND_UP(CONFIG_LS_PPA_ESBC_HDR_SIZE, 512);
- ret = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, ppa_hdr_ddr);
- if (ret != cnt) {
- free(ppa_hdr_ddr);
- printf("MMC/SD read of PPA header failed\n");
- return -EIO;
- }
- debug("Read PPA header to 0x%p\n", ppa_hdr_ddr);
-
- ppa_esbc_hdr = (uintptr_t)ppa_hdr_ddr;
-#endif
-
- fw_length = fdt_totalsize(fitp);
- free(fitp);
-
- fw_length = roundup(fw_length, 512);
- ppa_fit_addr = malloc(fw_length);
- if (!ppa_fit_addr) {
- printf("PPA: malloc failed for PPA image(size 0x%zx)\n",
- fw_length);
- return -ENOMEM;
- }
-
- blk = CONFIG_SYS_LS_PPA_FW_ADDR / 512;
- cnt = DIV_ROUND_UP(fw_length, 512);
- debug("%s: MMC read PPA FIT image: dev # %u, block # %u, count %u\n",
- __func__, dev, blk, cnt);
- ret = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, ppa_fit_addr);
- if (ret != cnt) {
- free(ppa_fit_addr);
- printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n",
- CONFIG_SYS_LS_PPA_FW_ADDR);
- return -EIO;
- }
-
-#elif defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
- struct fdt_header fit;
-
- debug("%s: PPA image load from NAND\n", __func__);
-
- nand_init();
- ret = nand_read(get_nand_dev_by_index(0),
- (loff_t)CONFIG_SYS_LS_PPA_FW_ADDR,
- &fdt_header_len, (u_char *)&fit);
- if (ret == -EUCLEAN) {
- printf("NAND read of PPA FIT header at offset 0x%x failed\n",
- CONFIG_SYS_LS_PPA_FW_ADDR);
- return -EIO;
- }
-
- ret = fdt_check_header(&fit);
- if (ret) {
- printf("%s: fdt_check_header() failed\n", __func__);
- return ret;
- }
-
-#ifdef CONFIG_CHAIN_OF_TRUST
- ppa_hdr_ddr = malloc(CONFIG_LS_PPA_ESBC_HDR_SIZE);
- if (!ppa_hdr_ddr) {
- printf("PPA: malloc failed for PPA header\n");
- return -ENOMEM;
- }
-
- fw_length = CONFIG_LS_PPA_ESBC_HDR_SIZE;
-
- ret = nand_read(get_nand_dev_by_index(0),
- (loff_t)CONFIG_SYS_LS_PPA_ESBC_ADDR,
- &fw_length, (u_char *)ppa_hdr_ddr);
- if (ret == -EUCLEAN) {
- free(ppa_hdr_ddr);
- printf("NAND read of PPA firmware at offset 0x%x failed\n",
- CONFIG_SYS_LS_PPA_FW_ADDR);
- return -EIO;
- }
- debug("Read PPA header to 0x%p\n", ppa_hdr_ddr);
-
- ppa_esbc_hdr = (uintptr_t)ppa_hdr_ddr;
-#endif
-
- fw_length = fdt_totalsize(&fit);
-
- ppa_fit_addr = malloc(fw_length);
- if (!ppa_fit_addr) {
- printf("PPA: malloc failed for PPA image(size 0x%zx)\n",
- fw_length);
- return -ENOMEM;
- }
-
- ret = nand_read(get_nand_dev_by_index(0),
- (loff_t)CONFIG_SYS_LS_PPA_FW_ADDR,
- &fw_length, (u_char *)ppa_fit_addr);
- if (ret == -EUCLEAN) {
- free(ppa_fit_addr);
- printf("NAND read of PPA firmware at offset 0x%x failed\n",
- CONFIG_SYS_LS_PPA_FW_ADDR);
- return -EIO;
- }
-#else
-#error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
-#endif
-
-#endif
-
-#ifdef CONFIG_CHAIN_OF_TRUST
- ppa_img_addr = (uintptr_t)ppa_fit_addr;
- if (fsl_check_boot_mode_secure() != 0) {
- /*
- * In case of failure in validation, fsl_secboot_validate
- * would not return back in case of Production environment
- * with ITS=1. In Development environment (ITS=0 and
- * SB_EN=1), the function may return back in case of
- * non-fatal failures.
- */
- ret = fsl_secboot_validate(ppa_esbc_hdr,
- PPA_KEY_HASH,
- &ppa_img_addr);
- if (ret != 0)
- printf("SEC firmware(s) validation failed\n");
- else
- printf("SEC firmware(s) validation Successful\n");
- }
-#if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \
- defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
- free(ppa_hdr_ddr);
-#endif
-#endif
-
-#ifdef CONFIG_FSL_LSCH3
- struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
- boot_loc_ptr_l = &gur->bootlocptrl;
- boot_loc_ptr_h = &gur->bootlocptrh;
-
- /* Assign addresses to loadable ptrs */
- loadable_l = &gur->scratchrw[4];
- loadable_h = &gur->scratchrw[5];
-#elif defined(CONFIG_FSL_LSCH2)
- struct ccsr_scfg __iomem *scfg = (void *)(CFG_SYS_FSL_SCFG_ADDR);
- boot_loc_ptr_l = &scfg->scratchrw[1];
- boot_loc_ptr_h = &scfg->scratchrw[0];
-
- /* Assign addresses to loadable ptrs */
- loadable_l = &scfg->scratchrw[2];
- loadable_h = &scfg->scratchrw[3];
-#endif
-
- debug("fsl-ppa: boot_loc_ptr_l = 0x%p, boot_loc_ptr_h =0x%p\n",
- boot_loc_ptr_l, boot_loc_ptr_h);
- ret = sec_firmware_init(ppa_fit_addr, boot_loc_ptr_l, boot_loc_ptr_h,
- loadable_l, loadable_h);
-
-#if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \
- defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
- free(ppa_fit_addr);
-#endif
-
- return ret;
-}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 61fced4..232adfa 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -21,7 +21,6 @@
#include <i2c.h>
#include <fsl_csu.h>
#include <asm/arch/fdt.h>
-#include <asm/arch/ppa.h>
#include <asm/arch/soc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -62,9 +61,6 @@
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
-#ifdef CONFIG_SPL_FSL_LS_PPA
- ppa_init();
-#endif
}
void tzpc_init(void)
@@ -78,6 +74,11 @@
#endif
}
+__weak int init_func_vid(void)
+{
+ return 0;
+}
+
void board_init_f(ulong dummy)
{
int ret;
@@ -115,36 +116,6 @@
init_func_vid();
#endif
dram_init();
-#ifdef CONFIG_SPL_FSL_LS_PPA
-#ifndef CFG_SYS_MEM_RESERVE_SECURE
-#error Need secure RAM for PPA
-#endif
- /*
- * Secure memory location is determined in dram_init_banksize().
- * gd->ram_size is deducted by the size of secure ram.
- */
- dram_init_banksize();
-
- /*
- * After dram_init_bank_size(), we know U-Boot only uses the first
- * memory bank regardless how big the memory is.
- */
- gd->ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
-
- /*
- * If PPA is loaded, U-Boot will resume running at EL2.
- * Cache and MMU will be enabled. Need a place for TLB.
- * U-Boot will be relocated to the end of available memory
- * in first bank. At this point, we cannot know how much
- * memory U-Boot uses. Put TLB table lower by SPL_TLB_SETBACK
- * to avoid overlapping. As soon as the RAM version U-Boot sets
- * up new MMU, this space is no longer needed.
- */
- gd->ram_top -= SPL_TLB_SETBACK;
- gd->arch.tlb_size = PGTABLE_SIZE;
- gd->arch.tlb_addr = (gd->ram_top - gd->arch.tlb_size) & ~(0x10000 - 1);
- gd->arch.tlb_allocated = gd->arch.tlb_addr;
-#endif /* CONFIG_SPL_FSL_LS_PPA */
#if defined(CONFIG_QSPI_AHB_INIT) && defined(CONFIG_QSPI_BOOT)
qspi_ahb_init();
#endif
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index cd9af8d..0492143 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -58,7 +58,7 @@
.globl save_boot_params_ret
save_boot_params_ret:
-#if CONFIG_POSITION_INDEPENDENT
+#if CONFIG_POSITION_INDEPENDENT && !defined(CONFIG_SPL_BUILD)
/* Verify that we're 4K aligned. */
adr x0, _start
ands x0, x0, #0xfff
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 85fd5b1..9d28a48 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -66,6 +66,7 @@
kirkwood-ns2max.dtb \
kirkwood-ns2mini.dtb \
kirkwood-nsa310s.dtb \
+ kirkwood-nsa325.dtb \
kirkwood-openrd-base.dtb \
kirkwood-openrd-client.dtb \
kirkwood-openrd-ultimate.dtb \
@@ -177,6 +178,7 @@
rk3566-soquartz-blade.dtb \
rk3566-soquartz-cm4.dtb \
rk3566-soquartz-model-a.dtb \
+ rk3568-bpi-r2-pro.dtb \
rk3568-evb.dtb \
rk3568-lubancat-2.dtb \
rk3568-nanopi-r5c.dtb \
@@ -189,6 +191,10 @@
rk3588-edgeble-neu6a-io.dtb \
rk3588-edgeble-neu6b-io.dtb \
rk3588-evb1-v10.dtb \
+ rk3588-nanopc-t6.dtb \
+ rk3588s-orangepi-5.dtb \
+ rk3588-orangepi-5-plus.dtb \
+ rk3588-quartzpro64.dtb \
rk3588s-rock-5a.dtb \
rk3588-rock-5b.dtb
@@ -317,6 +323,7 @@
dtb-$(CONFIG_ARCH_MVEBU) += \
armada-3720-db.dtb \
armada-3720-espressobin.dtb \
+ armada-3720-ripe-atlas.dtb \
armada-3720-turris-mox.dtb \
armada-3720-eDPU.dtb \
armada-3720-uDPU.dtb \
@@ -370,6 +377,12 @@
zynq-cse-nand.dtb \
zynq-cse-nor.dtb \
zynq-cse-qspi-single.dtb \
+ zynq-cse-qspi-parallel.dtb \
+ zynq-cse-qspi-stacked.dtb \
+ zynq-cse-qspi-x1-single.dtb \
+ zynq-cse-qspi-x1-stacked.dtb \
+ zynq-cse-qspi-x2-single.dtb \
+ zynq-cse-qspi-x2-stacked.dtb \
zynq-dlc20-rev1.0.dtb \
zynq-microzed.dtb \
zynq-minized.dtb \
@@ -395,25 +408,50 @@
zynqmp-a2197-revA.dtb \
zynqmp-dlc21-revA.dtb \
zynqmp-e-a2197-00-revA.dtb \
+ zynqmp-e-a2197-00-revB.dtb \
zynqmp-g-a2197-00-revA.dtb \
zynqmp-m-a2197-01-revA.dtb \
zynqmp-m-a2197-02-revA.dtb \
zynqmp-m-a2197-03-revA.dtb \
zynqmp-p-a2197-00-revA.dtb \
+ zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo \
+ zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo \
+ zynqmp-p-a2197-00-revA-x-prc-03-revA.dtbo \
+ zynqmp-p-a2197-00-revA-x-prc-04-revA.dtbo \
+ zynqmp-p-a2197-00-revA-x-prc-05-revA.dtbo \
zynqmp-mini.dtb \
zynqmp-mini-emmc0.dtb \
zynqmp-mini-emmc1.dtb \
zynqmp-mini-nand.dtb \
zynqmp-mini-qspi.dtb \
+ zynqmp-mini-qspi-parallel.dtb \
+ zynqmp-mini-qspi-single.dtb \
+ zynqmp-mini-qspi-stacked.dtb \
+ zynqmp-mini-qspi-x1-single.dtb \
+ zynqmp-mini-qspi-x1-stacked.dtb \
+ zynqmp-mini-qspi-x2-single.dtb \
+ zynqmp-mini-qspi-x2-stacked.dtb \
+ zynqmp-sc-revB.dtb \
+ zynqmp-sc-revC.dtb \
+ zynqmp-sc-vek280-revA.dtbo \
+ zynqmp-sc-vek280-revB.dtbo \
+ zynqmp-sc-vhk158-revA.dtbo \
+ zynqmp-sc-vpk120-revB.dtbo \
+ zynqmp-sc-vpk180-revA.dtbo \
+ zynqmp-sc-vpk180-revB.dtbo \
+ zynqmp-sc-vn-p-b2197-00-revA.dtbo \
zynqmp-sm-k24-revA.dtb \
zynqmp-smk-k24-revA.dtb \
zynqmp-sm-k26-revA.dtb \
zynqmp-smk-k26-revA.dtb \
+ zynqmp-sck-kd-g-revA.dtbo \
zynqmp-sck-kr-g-revA.dtbo \
zynqmp-sck-kr-g-revB.dtbo \
zynqmp-sck-kv-g-revA.dtbo \
zynqmp-sck-kv-g-revB.dtbo \
zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb \
+ zynqmp-vpk120-revA.dtb \
+ zynqmp-vp-x-a2785-00-revA.dtb \
zynqmp-zcu100-revC.dtb \
zynqmp-zcu102-revA.dtb \
zynqmp-zcu102-revB.dtb \
@@ -429,6 +467,8 @@
zynqmp-zcu1285-revA.dtb \
zynqmp-zcu208-revA.dtb \
zynqmp-zcu216-revA.dtb \
+ zynqmp-zcu670-revA.dtb \
+ zynqmp-zcu670-revB.dtb \
zynqmp-zc1232-revA.dtb \
zynqmp-zc1254-revA.dtb \
zynqmp-zc1751-xm015-dc1.dtb \
@@ -441,13 +481,27 @@
versal-mini-emmc0.dtb \
versal-mini-emmc1.dtb \
versal-mini-ospi-single.dtb \
+ versal-mini-ospi-stacked.dtb \
+ versal-mini-qspi-parallel.dtb \
versal-mini-qspi-single.dtb \
+ versal-mini-qspi-stacked.dtb \
+ versal-mini-qspi-x1-single.dtb \
+ versal-mini-qspi-x1-stacked.dtb \
+ versal-mini-qspi-x2-single.dtb \
+ versal-mini-qspi-x2-stacked.dtb \
xilinx-versal-virt.dtb
dtb-$(CONFIG_ARCH_VERSAL_NET) += \
versal-net-mini.dtb \
versal-net-mini-emmc.dtb \
versal-net-mini-ospi-single.dtb \
+ versal-net-mini-ospi-stacked.dtb \
versal-net-mini-qspi-single.dtb \
+ versal-net-mini-qspi-parallel.dtb \
+ versal-net-mini-qspi-stacked.dtb \
+ versal-net-mini-qspi-x1-single.dtb \
+ versal-net-mini-qspi-x1-stacked.dtb \
+ versal-net-mini-qspi-x2-single.dtb \
+ versal-net-mini-qspi-x2-stacked.dtb \
xilinx-versal-net-virt.dtb
dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
zynqmp-r5.dtb
@@ -667,6 +721,7 @@
sun7i-a20-haoyu-marsboard.dtb \
sun7i-a20-hummingbird.dtb \
sun7i-a20-i12-tvbox.dtb \
+ sun7i-a20-icnova-a20-adb4006.dtb \
sun7i-a20-icnova-swac.dtb \
sun7i-a20-itead-ibox.dtb \
sun7i-a20-lamobo-r1.dtb \
@@ -754,6 +809,8 @@
sun8i-s3-pinecube.dtb \
sun8i-v3-sl631-imx179.dtb \
sun8i-v3s-licheepi-zero.dtb
+dtb-$(CONFIG_MACH_SUN8I_R528) += \
+ sun8i-t113s-mangopi-mq-r-t113.dtb
dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-bananapi-m2-plus.dtb \
sun50i-h5-emlid-neutis-n5-devboard.dtb \
@@ -778,6 +835,7 @@
sun50i-h6-tanix-tx6-mini.dtb
dtb-$(CONFIG_MACH_SUN50I_H616) += \
sun50i-h616-orangepi-zero2.dtb \
+ sun50i-h618-orangepi-zero3.dtb \
sun50i-h616-x96-mate.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-amarula-relic.dtb \
@@ -1025,6 +1083,7 @@
imx8mm-venice-gw7902.dtb \
imx8mm-venice-gw7903.dtb \
imx8mm-venice-gw7904.dtb \
+ imx8mm-venice-gw7905-0x.dtb \
imx8mm-verdin-wifi-dev.dtb \
phycore-imx8mm.dtb \
imx8mn-bsh-smm-s2.dtb \
@@ -1042,13 +1101,21 @@
imx8mq-phanbell.dtb \
imx8mp-beacon-kit.dtb \
imx8mp-data-modul-edm-sbc.dtb \
+ imx8mp-dhcom-som-overlay-rev100.dtbo \
+ imx8mp-dhcom-som-overlay-eth1xfast.dtbo \
+ imx8mp-dhcom-som-overlay-eth2xfast.dtbo \
+ imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo \
imx8mp-dhcom-pdk2.dtb \
imx8mp-dhcom-pdk3.dtb \
+ imx8mp-dhcom-pdk3-overlay-rev100.dtbo \
imx8mp-evk.dtb \
imx8mp-icore-mx8mp-edimm2.2.dtb \
imx8mp-msc-sm2s.dtb \
imx8mp-phyboard-pollux-rdk.dtb \
imx8mp-venice.dtb \
+ imx8mp-venice-gw71xx-2x.dtb \
+ imx8mp-venice-gw72xx-2x.dtb \
+ imx8mp-venice-gw73xx-2x.dtb \
imx8mp-venice-gw74xx.dtb \
imx8mp-venice-gw7905-2x.dtb \
imx8mp-verdin-wifi-dev.dtb \
@@ -1099,6 +1166,9 @@
r8a779f0-spider-u-boot.dtb \
r8a779g0-white-hawk-u-boot.dtb
+dtb-$(CONFIG_TARGET_RZG2L) += \
+ r9a07g044l2-smarc.dts
+
ifdef CONFIG_RCAR_64
DTC_FLAGS += -R 4 -p 0x1000
endif
@@ -1198,9 +1268,15 @@
dtb-$(CONFIG_TARGET_SAMA5D27_WLSOM1_EK) += \
at91-sama5d27_wlsom1_ek.dtb
+dtb-$(CONFIG_TARGET_KSTR_SAMA5D27) += \
+ at91-kstr-sama5d27.dtb
+
dtb-$(CONFIG_TARGET_SAMA5D2_ICP) += \
at91-sama5d2_icp.dtb
+dtb-$(CONFIG_TARGET_SAMA5D29_CURIOSITY) += \
+ at91-sama5d29_curiosity.dtb
+
dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \
sama5d31ek.dtb \
sama5d33ek.dtb \
@@ -1334,6 +1410,8 @@
dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
k3-am625-r5-sk.dtb \
+ k3-am625-beagleplay.dtb \
+ k3-am625-r5-beagleplay.dtb \
k3-am625-verdin-wifi-dev.dtb \
k3-am625-verdin-r5.dtb
@@ -1432,6 +1510,8 @@
# Add any required device tree compiler flags here
DTC_FLAGS += -a 0x8
+DTC_FLAGS_imx8mp-dhcom-pdk3-overlay-rev100 += -Wno-avoid_default_addr_size -Wno-reg_format
+
PHONY += dtbs
dtbs: $(addprefix $(obj)/, $(dtb-y))
@:
diff --git a/arch/arm/dts/ac5-98dx35xx-atl-x240.dts b/arch/arm/dts/ac5-98dx35xx-atl-x240.dts
index c19b259..820ec18 100644
--- a/arch/arm/dts/ac5-98dx35xx-atl-x240.dts
+++ b/arch/arm/dts/ac5-98dx35xx-atl-x240.dts
@@ -16,7 +16,7 @@
gpio0 = &gpio0;
gpio1 = &gpio1;
spi0 = &spi0;
- i2c0 = &i2cgpio;
+ i2c0 = &i2c0;
usb0 = &usb0;
pinctrl0 = &pinctrl0;
};
@@ -40,19 +40,6 @@
default-state = "on";
};
};
-
- i2cgpio: i2c-gpio-0 {
- compatible = "i2c-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_gpio>;
- scl-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- status = "okay";
- };
};
&nand {
@@ -83,7 +70,9 @@
status = "okay";
};
-&i2cgpio {
+&i2c0 {
+ status = "okay";
+
mux@71 {
#address-cells = <1>;
#size-cells = <0>;
@@ -188,8 +177,8 @@
* LED_OE_N [23]
* USB_PWR_FLT_N [24]
* SFP_INT_N [25]
- * I2C0_SCL [26] (GPIO)
- * I2C0_SDA [27] (GPIO)
+ * I2C0_SCL [26]
+ * I2C0_SDA [27]
* USB_EN [28]
* MONITOR_INT_N [29]
* XM1_MDC [30]
@@ -212,7 +201,7 @@
/* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 1 1 1 1 0xff 0xff 0 0
- 0 0 0 0 0 0 0xff 0xff 0 0
+ 0 0 0 0 0 0 1 1 0 0
1 1 1 1 0 0 0 0 0 0
0 0 0 1 1 1 >;
@@ -220,9 +209,4 @@
marvell,pins = <0 1 2 3 4 5 6 7 8 9 10 11 16 17>;
marvell,function = <2>;
};
-
- i2c0_gpio: i2c0-gpio-pins {
- marvell,pins = <26 27>;
- marvell,function = <0>;
- };
};
diff --git a/arch/arm/dts/am335x-baltos.dts b/arch/arm/dts/am335x-baltos.dts
index b3c13c9..34b87d4 100644
--- a/arch/arm/dts/am335x-baltos.dts
+++ b/arch/arm/dts/am335x-baltos.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/dts/am335x-evm-u-boot.dtsi b/arch/arm/dts/am335x-evm-u-boot.dtsi
index 82a483a..72402c8 100644
--- a/arch/arm/dts/am335x-evm-u-boot.dtsi
+++ b/arch/arm/dts/am335x-evm-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am33xx-u-boot.dtsi"
diff --git a/arch/arm/dts/am335x-evmsk.dts b/arch/arm/dts/am335x-evmsk.dts
index 5d96225..e026765 100644
--- a/arch/arm/dts/am335x-evmsk.dts
+++ b/arch/arm/dts/am335x-evmsk.dts
@@ -5,7 +5,7 @@
/*
* AM335x Starter Kit
- * http://www.ti.com/tool/tmdssk3358
+ * https://www.ti.com/tool/tmdssk3358
*/
/dts-v1/;
diff --git a/arch/arm/dts/am335x-icev2-u-boot.dtsi b/arch/arm/dts/am335x-icev2-u-boot.dtsi
index 67bfac9..ac1feaa 100644
--- a/arch/arm/dts/am335x-icev2-u-boot.dtsi
+++ b/arch/arm/dts/am335x-icev2-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am33xx-u-boot.dtsi"
diff --git a/arch/arm/dts/am335x-icev2.dts b/arch/arm/dts/am335x-icev2.dts
index a542724..bcfdbb7 100644
--- a/arch/arm/dts/am335x-icev2.dts
+++ b/arch/arm/dts/am335x-icev2.dts
@@ -5,7 +5,7 @@
/*
* AM335x ICE V2 board
- * http://www.ti.com/tool/tmdsice3359
+ * https://www.ti.com/tool/tmdsice3359
*/
/dts-v1/;
diff --git a/arch/arm/dts/am335x-pxm2.dtsi b/arch/arm/dts/am335x-pxm2.dtsi
index a51d6ac..a495609 100644
--- a/arch/arm/dts/am335x-pxm2.dtsi
+++ b/arch/arm/dts/am335x-pxm2.dtsi
@@ -3,7 +3,7 @@
* Heiko Schocher <hs@denx.de>
*
* Based on:
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/dts/am335x-pxm50.dts b/arch/arm/dts/am335x-pxm50.dts
index f4e66d2..69ed32c 100644
--- a/arch/arm/dts/am335x-pxm50.dts
+++ b/arch/arm/dts/am335x-pxm50.dts
@@ -2,7 +2,7 @@
* Copyright (C) 2014 DENX Software Engineering GmbH
* Heiko Schocher <hs@denx.de>
*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/dts/am335x-rut.dts b/arch/arm/dts/am335x-rut.dts
index 7760b97..0dcd561 100644
--- a/arch/arm/dts/am335x-rut.dts
+++ b/arch/arm/dts/am335x-rut.dts
@@ -3,7 +3,7 @@
* Heiko Schocher <hs@denx.de>
*
* Based on:
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts b/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts
index a2676d1..271d1ab 100644
--- a/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts
+++ b/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2021 Sancloud Ltd
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/dts/am335x-sancloud-bbe-lite-u-boot.dtsi b/arch/arm/dts/am335x-sancloud-bbe-lite-u-boot.dtsi
index fd47bc2..db02888 100644
--- a/arch/arm/dts/am335x-sancloud-bbe-lite-u-boot.dtsi
+++ b/arch/arm/dts/am335x-sancloud-bbe-lite-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2021 SanCloud Ltd
*/
diff --git a/arch/arm/dts/am335x-sancloud-bbe-lite.dts b/arch/arm/dts/am335x-sancloud-bbe-lite.dts
index 8ffbc72..daa90f6 100644
--- a/arch/arm/dts/am335x-sancloud-bbe-lite.dts
+++ b/arch/arm/dts/am335x-sancloud-bbe-lite.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2021 SanCloud Ltd
*/
/dts-v1/;
diff --git a/arch/arm/dts/am4372-generic-u-boot.dtsi b/arch/arm/dts/am4372-generic-u-boot.dtsi
index 1dd0a5d..40f3756 100644
--- a/arch/arm/dts/am4372-generic-u-boot.dtsi
+++ b/arch/arm/dts/am4372-generic-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am4372-u-boot.dtsi"
diff --git a/arch/arm/dts/am4372-generic.dts b/arch/arm/dts/am4372-generic.dts
index b8a2bb8..2524e04 100644
--- a/arch/arm/dts/am4372-generic.dts
+++ b/arch/arm/dts/am4372-generic.dts
@@ -2,7 +2,7 @@
/*
* Device Tree Source for Generic AM4372 EVM
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/dts/am4372-u-boot.dtsi b/arch/arm/dts/am4372-u-boot.dtsi
index 2fac2fc..0c498bc 100644
--- a/arch/arm/dts/am4372-u-boot.dtsi
+++ b/arch/arm/dts/am4372-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
/{
diff --git a/arch/arm/dts/am437x-gp-evm-u-boot.dtsi b/arch/arm/dts/am437x-gp-evm-u-boot.dtsi
index da0b136..6393170 100644
--- a/arch/arm/dts/am437x-gp-evm-u-boot.dtsi
+++ b/arch/arm/dts/am437x-gp-evm-u-boot.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/dts/am437x-idk-evm-u-boot.dtsi b/arch/arm/dts/am437x-idk-evm-u-boot.dtsi
index 4e6ad94..7c9f80e 100644
--- a/arch/arm/dts/am437x-idk-evm-u-boot.dtsi
+++ b/arch/arm/dts/am437x-idk-evm-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am4372-u-boot.dtsi"
diff --git a/arch/arm/dts/am437x-sk-evm-u-boot.dtsi b/arch/arm/dts/am437x-sk-evm-u-boot.dtsi
index 43e519c..580ba35 100644
--- a/arch/arm/dts/am437x-sk-evm-u-boot.dtsi
+++ b/arch/arm/dts/am437x-sk-evm-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am4372-u-boot.dtsi"
diff --git a/arch/arm/dts/am571x-idk-u-boot.dtsi b/arch/arm/dts/am571x-idk-u-boot.dtsi
index 6519920..98a7a7e 100644
--- a/arch/arm/dts/am571x-idk-u-boot.dtsi
+++ b/arch/arm/dts/am571x-idk-u-boot.dtsi
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am57xx-idk-common-u-boot.dtsi"
diff --git a/arch/arm/dts/am5729-beagleboneai.dts b/arch/arm/dts/am5729-beagleboneai.dts
index f772aef..75a29e6 100644
--- a/arch/arm/dts/am5729-beagleboneai.dts
+++ b/arch/arm/dts/am5729-beagleboneai.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2014-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2019 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/dts/am572x-idk-u-boot.dtsi b/arch/arm/dts/am572x-idk-u-boot.dtsi
index 6519920..98a7a7e 100644
--- a/arch/arm/dts/am572x-idk-u-boot.dtsi
+++ b/arch/arm/dts/am572x-idk-u-boot.dtsi
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am57xx-idk-common-u-boot.dtsi"
diff --git a/arch/arm/dts/am574x-idk-u-boot.dtsi b/arch/arm/dts/am574x-idk-u-boot.dtsi
index 6519920..98a7a7e 100644
--- a/arch/arm/dts/am574x-idk-u-boot.dtsi
+++ b/arch/arm/dts/am574x-idk-u-boot.dtsi
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am57xx-idk-common-u-boot.dtsi"
diff --git a/arch/arm/dts/am57xx-beagle-x15-revb1-u-boot.dtsi b/arch/arm/dts/am57xx-beagle-x15-revb1-u-boot.dtsi
index 49b1621..2af4e60 100644
--- a/arch/arm/dts/am57xx-beagle-x15-revb1-u-boot.dtsi
+++ b/arch/arm/dts/am57xx-beagle-x15-revb1-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/am57xx-beagle-x15-revc-u-boot.dtsi b/arch/arm/dts/am57xx-beagle-x15-revc-u-boot.dtsi
index 49b1621..2af4e60 100644
--- a/arch/arm/dts/am57xx-beagle-x15-revc-u-boot.dtsi
+++ b/arch/arm/dts/am57xx-beagle-x15-revc-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/am57xx-beagle-x15-u-boot.dtsi b/arch/arm/dts/am57xx-beagle-x15-u-boot.dtsi
index 49b1621..2af4e60 100644
--- a/arch/arm/dts/am57xx-beagle-x15-u-boot.dtsi
+++ b/arch/arm/dts/am57xx-beagle-x15-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/am57xx-cl-som-am57x-u-boot.dtsi b/arch/arm/dts/am57xx-cl-som-am57x-u-boot.dtsi
index 49b1621..2af4e60 100644
--- a/arch/arm/dts/am57xx-cl-som-am57x-u-boot.dtsi
+++ b/arch/arm/dts/am57xx-cl-som-am57x-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/am57xx-idk-common-u-boot.dtsi b/arch/arm/dts/am57xx-idk-common-u-boot.dtsi
index b07aea0..31faec4 100644
--- a/arch/arm/dts/am57xx-idk-common-u-boot.dtsi
+++ b/arch/arm/dts/am57xx-idk-common-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/am57xx-sbc-am57x-u-boot.dtsi b/arch/arm/dts/am57xx-sbc-am57x-u-boot.dtsi
index 49b1621..2af4e60 100644
--- a/arch/arm/dts/am57xx-sbc-am57x-u-boot.dtsi
+++ b/arch/arm/dts/am57xx-sbc-am57x-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/armada-3720-ripe-atlas.dts b/arch/arm/dts/armada-3720-ripe-atlas.dts
new file mode 100644
index 0000000..4457845
--- /dev/null
+++ b/arch/arm/dts/armada-3720-ripe-atlas.dts
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0+ or X11
+/*
+ * Device Tree file for CZ.NIC' RIPE Atlas Probe
+ * 2021 by Marek Behún <marek.behun@nic.cz>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include "armada-372x.dtsi"
+
+/ {
+ model = "CZ.NIC's RIPE Atlas Probe";
+ compatible = "cznic,ripe-atlas", "marvell,armada3720",
+ "marvell,armada3710";
+
+ aliases {
+ ethernet0 = ð0;
+ mmc0 = &sdhci0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led {
+ gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_ACTIVITY;
+ };
+ };
+
+ vsdc_reg: vsdc-reg {
+ compatible = "regulator-gpio";
+ regulator-name = "vsdc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+
+ gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ enable-active-high;
+ };
+};
+
+&comphy {
+ status = "disabled";
+};
+
+&mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&smi_pins>;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+ð0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&phy1>;
+ status = "okay";
+};
+
+&sdhci0 {
+ bus-width = <8>;
+ non-removable;
+ vqmmc-supply = <&vsdc_reg>;
+ marvell,pad-type = "sd";
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/at91-kstr-sama5d27-u-boot.dtsi b/arch/arm/dts/at91-kstr-sama5d27-u-boot.dtsi
new file mode 100644
index 0000000..cec35ab
--- /dev/null
+++ b/arch/arm/dts/at91-kstr-sama5d27-u-boot.dtsi
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * at91-kstr-sama5d27-u-boot.dtsi - Device Tree Include file w/ U-Boot specific
+ * properties for Conclusive KSTR-SAMA5D27 board
+ *
+ * Copyright (C) 2023 Conclusive Engineering Sp. z o. o.
+ *
+ */
+
+/ {
+ chosen {
+ bootph-all;
+ };
+};
+
+&sdmmc0 {
+ bootph-all;
+};
+
+&uart1 {
+ bootph-all;
+};
+
+&pinctrl_uart1_default {
+ bootph-all;
+};
+
+&pinctrl_macb0_phy_irq {
+ bootph-all;
+};
+
+&pinctrl_macb0_rmii {
+ bootph-all;
+};
+
+&pinctrl_sdmmc0_cmd_dat_default {
+ bootph-all;
+};
+
+&pinctrl_sdmmc0_ck_cd_default {
+ bootph-all;
+};
diff --git a/arch/arm/dts/at91-kstr-sama5d27.dts b/arch/arm/dts/at91-kstr-sama5d27.dts
new file mode 100644
index 0000000..c226a21
--- /dev/null
+++ b/arch/arm/dts/at91-kstr-sama5d27.dts
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * at91-kstr-sama5d27.dts - Device Tree file for Conclusive KSTR-SAMA5D27 board
+ *
+ * Copyright (C) 2019-2023 Conclusive Engineering Sp. z o. o.
+ *
+ */
+/dts-v1/;
+
+#include "sama5d2.dtsi"
+#include "sama5d2-pinfunc.h"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
+
+/ {
+ model = "Conclusive KSTR-SAMA5D27";
+ compatible = "conclusive,kstr-sama5d27", "atmel,sama5d2", "atmel,sama5";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ aliases {
+ i2c2 = &i2c6;
+ };
+};
+
+&main_xtal {
+ clock-frequency = <12000000>;
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+ status = "okay";
+};
+
+&macb0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>;
+ phy-mode = "rmii";
+ status = "okay";
+
+ ethernet-phy@0 {
+ reg = <0x0>;
+ reset-gpios = <&pioA 44 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&flx4 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "okay";
+};
+
+&i2c6 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx4_i2c>;
+ status = "okay";
+
+ eeprom: eeprom@50 {
+ compatible = "microchip,24c32", "atmel,24c32";
+ reg = <0x50>;
+ read-only;
+ pagesize = <32>;
+ status = "okay";
+ };
+};
+
+&pioA {
+ pinctrl {
+ pinctrl_uart1_default: uart1_default {
+ pinmux = <PIN_PD2__URXD1>,
+ <PIN_PD3__UTXD1>;
+ bias-disable;
+ };
+
+ pinctrl_macb0_phy_irq: macb0_phy_irq {
+ pinmux = <PIN_PB13__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_macb0_rmii: macb0_rmii {
+ pinmux = <PIN_PB14__GTXCK>,
+ <PIN_PB15__GTXEN>,
+ <PIN_PB16__GRXDV>,
+ <PIN_PB17__GRXER>,
+ <PIN_PB18__GRX0>,
+ <PIN_PB19__GRX1>,
+ <PIN_PB20__GTX0>,
+ <PIN_PB21__GTX1>,
+ <PIN_PB22__GMDC>,
+ <PIN_PB23__GMDIO>;
+ bias-disable;
+ };
+
+ pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default {
+ pinmux = <PIN_PA1__SDMMC0_CMD>,
+ <PIN_PA2__SDMMC0_DAT0>,
+ <PIN_PA3__SDMMC0_DAT1>,
+ <PIN_PA4__SDMMC0_DAT2>,
+ <PIN_PA5__SDMMC0_DAT3>;
+ bias-pull-up;
+ };
+
+ pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default {
+ pinmux = <PIN_PA0__SDMMC0_CK>,
+ <PIN_PA11__SDMMC0_VDDSEL>,
+ <PIN_PA13__SDMMC0_CD>;
+ bias-disable;
+ };
+
+ pinctrl_flx4_i2c: flx4_i2c {
+ pinmux = <PIN_PC28__FLEXCOM4_IO0>,
+ <PIN_PC29__FLEXCOM4_IO1>;
+ bias-disable;
+ };
+ };
+};
diff --git a/arch/arm/dts/at91-sam9x60_curiosity-u-boot.dtsi b/arch/arm/dts/at91-sam9x60_curiosity-u-boot.dtsi
index 0c3c040..dd46233 100644
--- a/arch/arm/dts/at91-sam9x60_curiosity-u-boot.dtsi
+++ b/arch/arm/dts/at91-sam9x60_curiosity-u-boot.dtsi
@@ -14,16 +14,30 @@
apb {
bootph-all;
-
- pinctrl {
- bootph-all;
- };
};
};
chosen {
bootph-all;
};
+
+ config {
+ u-boot,boot-led = "blue";
+ };
+
+ leds {
+ led-red {
+ default-state = "off";
+ };
+
+ led-green {
+ default-state = "off";
+ };
+
+ led-blue {
+ default-state = "off";
+ };
+ };
};
&clk32 {
@@ -42,6 +56,10 @@
bootph-all;
};
+&pinctrl {
+ bootph-all;
+};
+
&pinctrl_dbgu {
bootph-all;
};
diff --git a/arch/arm/dts/at91-sam9x60_curiosity.dts b/arch/arm/dts/at91-sam9x60_curiosity.dts
index d6ae3d6..99867d2 100644
--- a/arch/arm/dts/at91-sam9x60_curiosity.dts
+++ b/arch/arm/dts/at91-sam9x60_curiosity.dts
@@ -7,64 +7,23 @@
* Author: Durai Manickam KR <durai.manickamkr@microchip.com>
*/
/dts-v1/;
+#include <dt-bindings/input/input.h>
#include <dt-bindings/mfd/atmel-flexcom.h>
#include "sam9x60.dtsi"
/ {
- model = "Microchip SAM9X60 CURIOSITY";
+ model = "Microchip SAM9X60 Curiosity";
compatible = "microchip,sam9x60-curiosity", "microchip,sam9x60", "atmel,at91sam9";
- ahb {
- apb {
- flx0: flexcom@f801c600 {
- atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
- status = "okay";
-
- i2c@600 {
- compatible = "atmel,sama5d2-i2c";
- reg = <0x600 0x200>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flx0>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
- status = "okay";
-
- eeprom@53 {
- compatible = "atmel,24c32";
- reg = <0x53>;
- pagesize = <16>;
- };
- };
- };
-
- pinctrl {
- pinctrl_flx0: flx0_default {
- atmel,pins =
- <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE
- AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
- };
-
- pinctrl_onewire_tm_default: onewire_tm_default {
- atmel,pins =
- <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
- };
-
- usb1 {
- pinctrl_usb_default: usb_default {
- atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
- AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
- };
- };
- };
- };
- };
-
chosen {
stdout-path = &dbgu;
i2c0 = &flx0;
};
+ memory {
+ reg = <0x20000000 0x8000000>;
+ };
+
clocks {
slow_xtal: slow_xtal {
clock-frequency = <32768>;
@@ -75,8 +34,39 @@
};
};
- memory {
- reg = <0x20000000 0x8000000>;
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_key_gpio_default>;
+
+ button-user {
+ label = "PB_USER";
+ gpios = <&pioA 29 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_PROG1>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-red {
+ label = "red";
+ gpios = <&pioD 17 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-green {
+ label = "green";
+ gpios = <&pioD 19 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-blue {
+ label = "blue";
+ gpios = <&pioD 21 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
};
onewire_tm: onewire {
@@ -92,11 +82,172 @@
};
};
+&ebi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
+ status = "okay";
+
+ nand_controller: nand-controller {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>;
+ status = "okay";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ uboot@40000 {
+ label = "u-boot";
+ reg = <0x40000 0xc0000>;
+ };
+
+ ubootenvred@100000 {
+ label = "U-Boot Env Redundant";
+ reg = <0x100000 0x40000>;
+ };
+
+ ubootenv@140000 {
+ label = "U-Boot Env";
+ reg = <0x140000 0x40000>;
+ };
+
+ dtb@180000 {
+ label = "device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel@200000 {
+ label = "kernel";
+ reg = <0x200000 0x600000>;
+ };
+
+ rootfs@800000 {
+ label = "rootfs";
+ reg = <0x800000 0x1f800000>;
+ };
+ };
+ };
+ };
+};
+
+&flx0 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "okay";
+
+ i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+ status = "okay";
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+ };
+};
+
&macb0 {
phy-mode = "rmii";
status = "okay";
};
+&pinctrl {
+ ebi {
+ pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
+ atmel,pins =
+ <AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+ };
+
+ pinctrl_ebi_addr_nand: ebi-addr-0 {
+ atmel,pins =
+ <AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+ };
+ };
+
+ flexcom {
+ pinctrl_flx0: flx0_default {
+ atmel,pins =
+ <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ };
+
+ gpio-keys {
+ pinctrl_key_gpio_default: pinctrl-key-gpio {
+ atmel,pins = <AT91_PIOA 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+
+ leds {
+ pinctrl_gpio_leds: gpio-leds {
+ atmel,pins = <AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOD 19 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+
+ nand {
+ pinctrl_nand_oe_we: nand-oe-we-0 {
+ atmel,pins =
+ <AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+ };
+
+ pinctrl_nand_rb: nand-rb-0 {
+ atmel,pins =
+ <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
+
+ pinctrl_nand_cs: nand-cs-0 {
+ atmel,pins =
+ <AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
+ };
+
+ pinctrl_onewire_tm_default: onewire_tm_default {
+ atmel,pins =
+ <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
+
+ usb1 {
+ pinctrl_usb_default: usb_default {
+ atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+};
+
&usb1 {
num-ports = <3>;
atmel,vbus-gpio = <0
diff --git a/arch/arm/dts/at91-sama5d29_curiosity-u-boot.dtsi b/arch/arm/dts/at91-sama5d29_curiosity-u-boot.dtsi
new file mode 100644
index 0000000..798761c
--- /dev/null
+++ b/arch/arm/dts/at91-sama5d29_curiosity-u-boot.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * at91-sama5d29_curiosity-u-boot.dtsi - Device Tree file for SAMA5D2 SoC u-boot properties.
+ *
+ * Copyright (c) 2023, Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Mihai Sain <mihai.sain@microchip.com>
+ *
+ */
+
+/ {
+ chosen {
+ bootph-all;
+ };
+};
+
+&pinctrl_qspi1_default {
+ bootph-all;
+};
+
+&pinctrl_sdmmc0_default {
+ bootph-all;
+};
+
+&pinctrl_sdmmc1_default {
+ bootph-all;
+};
+
+&hlcdc {
+ bootph-all;
+};
+
+&pioA {
+ bootph-all;
+};
+
+&qspi1 {
+ bootph-all;
+
+ flash@0 {
+ bootph-all;
+ };
+};
+
+&sdmmc0 {
+ bootph-all;
+};
+
+&sdmmc1 {
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+};
diff --git a/arch/arm/dts/at91-sama5d29_curiosity.dts b/arch/arm/dts/at91-sama5d29_curiosity.dts
new file mode 100644
index 0000000..eff0e91
--- /dev/null
+++ b/arch/arm/dts/at91-sama5d29_curiosity.dts
@@ -0,0 +1,219 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * at91-sama5d29_curiosity.dts - Device Tree file for SAMA5D29 CURIOSITY board
+ *
+ * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Mihai Sain <mihai.sain@microchip.com>
+ *
+ */
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include "sama5d2.dtsi"
+#include "sama5d2-pinfunc.h"
+
+/ {
+ model = "Microchip SAMA5D29-Curiosity";
+ compatible = "atmel,sama5d29-curiosity", "atmel,sama5d2", "atmel,sama5";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait";
+ stdout-path = &uart0;
+ };
+
+ memory {
+ reg = <0x20000000 0x20000000>; // 512 MiB LPDDR2-333
+ };
+
+ clocks {
+ slow_xtal: slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal: main_xtal {
+ clock-frequency = <24000000>;
+ };
+ };
+
+ onewire_tm: onewire {
+ gpios = <&pioA PIN_PC9 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_onewire_tm_default>;
+ status = "okay";
+
+ w1_eeprom: w1_eeprom@0 {
+ compatible = "maxim,ds24b33";
+ status = "okay";
+ };
+ };
+
+ ahb {
+ usb1: ohci@400000 {
+ num-ports = <3>;
+ atmel,vbus-gpio = <&pioA PIN_PB13 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_default>;
+ status = "okay";
+ };
+
+ usb2: ehci@500000 {
+ status = "okay";
+ };
+
+ sdmmc0: sdio-host@a0000000 {
+ bus-width = <4>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc0_default>;
+ status = "okay";
+ };
+
+ sdmmc1: sdio-host@b0000000 {
+ bus-width = <4>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc1_default>;
+ status = "okay";
+ };
+
+ apb {
+ hlcdc: hlcdc@f0000000 {
+ atmel,vl-bpix = <4>;
+ atmel,output-mode = <24>;
+ atmel,guard-time = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb666>;
+ status = "okay";
+
+ display-timings { // PDA TM5000
+ 800x480 {
+ clock-frequency = <33000000>;
+ xres = <800>;
+ yres = <480>;
+ hactive = <800>;
+ vactive = <480>;
+ hsync-len = <64>;
+ hfront-porch = <1>;
+ hback-porch = <64>;
+ vfront-porch = <1>;
+ vback-porch = <22>;
+ vsync-len = <23>;
+ };
+ };
+ };
+
+ qspi1: spi@f0024000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi1_default>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <80000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ m25p,fast-read;
+ };
+ };
+
+ uart0: serial@f801c000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
+ status = "okay";
+ };
+
+ pioA: pinctrl@fc038000 {
+ pinctrl_lcd_base: lcd_base {
+ pinmux = <PIN_PC30__LCDVSYNC>,
+ <PIN_PC31__LCDHSYNC>,
+ <PIN_PD1__LCDDEN>,
+ <PIN_PD0__LCDPCK>;
+ bias-disable;
+ };
+
+ pinctrl_lcd_pwm: lcd_pwm {
+ pinmux = <PIN_PC28__LCDPWM>;
+ bias-disable;
+ };
+
+ pinctrl_lcd_rgb666: lcd_rgb666 {
+ pinmux = <PIN_PC10__LCDDAT2>,
+ <PIN_PC11__LCDDAT3>,
+ <PIN_PC12__LCDDAT4>,
+ <PIN_PC13__LCDDAT5>,
+ <PIN_PC14__LCDDAT6>,
+ <PIN_PC15__LCDDAT7>,
+ <PIN_PC16__LCDDAT10>,
+ <PIN_PC17__LCDDAT11>,
+ <PIN_PC18__LCDDAT12>,
+ <PIN_PC19__LCDDAT13>,
+ <PIN_PC20__LCDDAT14>,
+ <PIN_PC21__LCDDAT15>,
+ <PIN_PC22__LCDDAT18>,
+ <PIN_PC23__LCDDAT19>,
+ <PIN_PC24__LCDDAT20>,
+ <PIN_PC25__LCDDAT21>,
+ <PIN_PC26__LCDDAT22>,
+ <PIN_PC27__LCDDAT23>;
+ bias-disable;
+ };
+
+ pinctrl_qspi1_default: qspi1_default {
+ pinmux = <PIN_PB5__QSPI1_SCK>,
+ <PIN_PB6__QSPI1_CS>,
+ <PIN_PB7__QSPI1_IO0>,
+ <PIN_PB8__QSPI1_IO1>,
+ <PIN_PB9__QSPI1_IO2>,
+ <PIN_PB10__QSPI1_IO3>;
+ bias-pull-up;
+ };
+
+ pinctrl_sdmmc0_default: sdmmc0_default {
+ pinmux = <PIN_PA0__SDMMC0_CK>,
+ <PIN_PA1__SDMMC0_CMD>,
+ <PIN_PA2__SDMMC0_DAT0>,
+ <PIN_PA3__SDMMC0_DAT1>,
+ <PIN_PA4__SDMMC0_DAT2>,
+ <PIN_PA5__SDMMC0_DAT3>,
+ <PIN_PA11__SDMMC0_VDDSEL>,
+ <PIN_PA13__SDMMC0_CD>;
+ bias-disable;
+ };
+
+ pinctrl_sdmmc1_default: sdmmc1_default {
+ pinmux = <PIN_PA18__SDMMC1_DAT0>,
+ <PIN_PA19__SDMMC1_DAT1>,
+ <PIN_PA20__SDMMC1_DAT2>,
+ <PIN_PA21__SDMMC1_DAT3>,
+ <PIN_PA22__SDMMC1_CK>,
+ <PIN_PA28__SDMMC1_CMD>,
+ <PIN_PA30__SDMMC1_CD>;
+ bias-disable;
+ };
+
+ pinctrl_uart0_default: uart0_default {
+ pinmux = <PIN_PB26__URXD0>,
+ <PIN_PB27__UTXD0>;
+ bias-disable;
+ };
+
+ pinctrl_usb_default: usb_default {
+ pinmux = <PIN_PA6__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_usba_vbus: usba_vbus {
+ pinmux = <PIN_PB13__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_onewire_tm_default: onewire_tm_default {
+ pinmux = <PIN_PC9__GPIO>;
+ bias-pull-up;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/avnet-ultra96-rev1.dts b/arch/arm/dts/avnet-ultra96-rev1.dts
index 96a6403..4c1bd69 100644
--- a/arch/arm/dts/avnet-ultra96-rev1.dts
+++ b/arch/arm/dts/avnet-ultra96-rev1.dts
@@ -2,7 +2,7 @@
/*
* dts file for Avnet Ultra96 rev1
*
- * (C) Copyright 2018 - 2020, Xilinx, Inc.
+ * (C) Copyright 2018, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
diff --git a/arch/arm/dts/axp209.dtsi b/arch/arm/dts/axp209.dtsi
index ca240cd..469d0f7 100644
--- a/arch/arm/dts/axp209.dtsi
+++ b/arch/arm/dts/axp209.dtsi
@@ -48,6 +48,13 @@
* http://dl.linux-sunxi.org/AXP/AXP209%20Datasheet%20v1.0_cn.pdf
*/
+/ {
+ pmic-temp {
+ compatible = "iio-hwmon";
+ io-channels = <&axp_adc 4>; /* Internal temperature */
+ };
+};
+
&axp209 {
compatible = "x-powers,axp209";
interrupt-controller;
diff --git a/arch/arm/dts/beacon-renesom-baseboard.dtsi b/arch/arm/dts/beacon-renesom-baseboard.dtsi
index 8166e3c..2e9927b 100644
--- a/arch/arm/dts/beacon-renesom-baseboard.dtsi
+++ b/arch/arm/dts/beacon-renesom-baseboard.dtsi
@@ -367,7 +367,7 @@
assigned-clocks = <&versaclock6_bb 1>, <&versaclock6_bb 2>,
<&versaclock6_bb 3>, <&versaclock6_bb 4>;
- assigned-clock-rates = <24000000>, <24000000>, <24000000>,
+ assigned-clock-rates = <24000000>, <24000000>, <24576000>,
<24576000>;
OUT1 {
@@ -437,20 +437,6 @@
};
};
- /* 0 - lcd_reset */
- /* 1 - lcd_pwr */
- /* 2 - lcd_select */
- /* 3 - backlight-enable */
- /* 4 - Touch_shdwn */
- /* 5 - LCD_H_pol */
- /* 6 - lcd_V_pol */
- gpio_exp1: gpio@20 {
- compatible = "onnn,pca9654";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
touchscreen@26 {
compatible = "ilitek,ili2117";
reg = <0x26>;
@@ -482,6 +468,16 @@
};
};
};
+
+ gpio_exp1: gpio@70 {
+ compatible = "nxp,pca9538";
+ reg = <0x70>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "lcd_reset", "lcd_pwr", "lcd_select",
+ "backlight-enable", "Touch_shdwn",
+ "LCD_H_pol", "lcd_V_pol";
+ };
};
&lvds0 {
@@ -638,6 +634,25 @@
#clock-cells = <1>;
clock-frequency = <11289600>;
+ /* Reference versaclock instead of audio_clk_a */
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&versaclock6_bb 4>, <&audio_clk_b>,
+ <&audio_clk_c>,
+ <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
+
status = "okay";
ports {
diff --git a/arch/arm/dts/beacon-renesom-som.dtsi b/arch/arm/dts/beacon-renesom-som.dtsi
index d3fc8ff..68b04e5 100644
--- a/arch/arm/dts/beacon-renesom-som.dtsi
+++ b/arch/arm/dts/beacon-renesom-som.dtsi
@@ -59,7 +59,7 @@
status = "okay";
phy0: ethernet-phy@0 {
- compatible = "ethernet-phy-id004d.d074",
+ compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <0>;
interrupt-parent = <&gpio2>;
diff --git a/arch/arm/dts/bitmain-antminer-s9.dts b/arch/arm/dts/bitmain-antminer-s9.dts
index 6c47396..f5ad95a 100644
--- a/arch/arm/dts/bitmain-antminer-s9.dts
+++ b/arch/arm/dts/bitmain-antminer-s9.dts
@@ -52,6 +52,11 @@
&nfc0 {
status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nand@0 {
+ reg = <0>;
+ };
};
&smcc {
diff --git a/arch/arm/dts/cn9130-crb.dtsi b/arch/arm/dts/cn9130-crb.dtsi
index b229725..7dd36ca 100644
--- a/arch/arm/dts/cn9130-crb.dtsi
+++ b/arch/arm/dts/cn9130-crb.dtsi
@@ -125,11 +125,6 @@
marvell,function = <0>;
};
- cp0_spi1_pins_crb: cp0-spi-pins-crb {
- marvell,pins = < 13 14 15 16 >;
- marvell,function = <3>;
- };
-
cp0_smi_pins_crb: cp0-smi-pins-crb {
marvell,pins = < 40 41 >;
marvell,function = <8>;
@@ -170,7 +165,7 @@
&cp0_spi1 {
pinctrl-names = "default";
- pinctrl-0 = <&cp0_spi1_pins_crb>;
+ pinctrl-0 = <&cp0_spi1_pins>;
reg = <0x700680 0x50>, /* control */
<0x2000000 0x1000000>, /* CS0 */
<0 0xffffffff>, /* CS1 */
diff --git a/arch/arm/dts/cn9130-db.dtsi b/arch/arm/dts/cn9130-db.dtsi
index 1b28732..4b21ff4 100644
--- a/arch/arm/dts/cn9130-db.dtsi
+++ b/arch/arm/dts/cn9130-db.dtsi
@@ -183,7 +183,7 @@
/* U55 */
&cp0_spi1 {
pinctrl-names = "default";
- pinctrl-0 = <&cp0_spi0_pins>;
+ pinctrl-0 = <&cp0_spi1_pins>;
reg = <0x700680 0x50>, /* control */
<0x2000000 0x1000000>, /* CS0 */
<0 0xffffffff>, /* CS1 */
diff --git a/arch/arm/dts/cn9130.dtsi b/arch/arm/dts/cn9130.dtsi
index 68b767a..efcb2e9 100644
--- a/arch/arm/dts/cn9130.dtsi
+++ b/arch/arm/dts/cn9130.dtsi
@@ -66,7 +66,7 @@
marvell,pins = < 56 57 58 59 60 61 >;
marvell,function = <14>;
};
- cp0_spi0_pins: cp0-spi-pins-0 {
+ cp0_spi1_pins: cp0-spi-pins-1 {
marvell,pins = < 13 14 15 16 >;
marvell,function = <3>;
};
diff --git a/arch/arm/dts/condor-common.dtsi b/arch/arm/dts/condor-common.dtsi
index dfbe35b..7c34d14 100644
--- a/arch/arm/dts/condor-common.dtsi
+++ b/arch/arm/dts/condor-common.dtsi
@@ -21,6 +21,7 @@
chosen {
stdout-path = "serial0:115200n8";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
};
d1_8v: regulator-2 {
diff --git a/arch/arm/dts/da850-lcdk-u-boot.dtsi b/arch/arm/dts/da850-lcdk-u-boot.dtsi
index bbaebcb..9ab48bc 100644
--- a/arch/arm/dts/da850-lcdk-u-boot.dtsi
+++ b/arch/arm/dts/da850-lcdk-u-boot.dtsi
@@ -2,7 +2,7 @@
/*
* da850-lcdk U-Boot Additions
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
diff --git a/arch/arm/dts/dra7-evm-u-boot.dtsi b/arch/arm/dts/dra7-evm-u-boot.dtsi
index 87b2451..3fe1fb4 100644
--- a/arch/arm/dts/dra7-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra7-evm-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/dra7-ipu-common-early-boot.dtsi b/arch/arm/dts/dra7-ipu-common-early-boot.dtsi
index 90fc4cb..afa4595 100644
--- a/arch/arm/dts/dra7-ipu-common-early-boot.dtsi
+++ b/arch/arm/dts/dra7-ipu-common-early-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
diff --git a/arch/arm/dts/dra71-evm-u-boot.dtsi b/arch/arm/dts/dra71-evm-u-boot.dtsi
index 8e7dc71..339b05f 100644
--- a/arch/arm/dts/dra71-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra71-evm-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/dra72-evm-revc-u-boot.dtsi b/arch/arm/dts/dra72-evm-revc-u-boot.dtsi
index 8e7dc71..339b05f 100644
--- a/arch/arm/dts/dra72-evm-revc-u-boot.dtsi
+++ b/arch/arm/dts/dra72-evm-revc-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/dra72-evm-u-boot.dtsi b/arch/arm/dts/dra72-evm-u-boot.dtsi
index 91a3b6b..dfdd5c5 100644
--- a/arch/arm/dts/dra72-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra72-evm-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/dra76-evm-u-boot.dtsi b/arch/arm/dts/dra76-evm-u-boot.dtsi
index 1216d93..c8da3e4 100644
--- a/arch/arm/dts/dra76-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra76-evm-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
index f2d6b18..c54a59e 100644
--- a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
@@ -93,6 +93,12 @@
&gpio4 {
bootph-some-ram;
+
+ usbh_en {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
};
&gpio5 {
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
index 83750ab..aacf181 100644
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
@@ -64,7 +64,7 @@
&binman {
u-boot-update {
- filename = "u-boot.update";
+ filename = "u-boot-update.bin";
fit {
description = "FIT update image";
diff --git a/arch/arm/dts/hihope-common.dtsi b/arch/arm/dts/hihope-common.dtsi
index b1eb6a0..83104af 100644
--- a/arch/arm/dts/hihope-common.dtsi
+++ b/arch/arm/dts/hihope-common.dtsi
@@ -3,15 +3,26 @@
* Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
* HiHope RZ/G2[MN] Rev.[2.0/3.0/4.0] main board common parts
*
- * Copyright (C) 2021 Renesas Electronics Corp.
+ * Copyright (C) 2019 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &iic_pmic;
serial0 = &scif2;
serial1 = &hscif0;
+ mmc0 = &sdhi3;
+ mmc1 = &sdhi0;
+ mmc2 = &sdhi2;
};
chosen {
@@ -50,7 +61,7 @@
};
};
- reg_1p8v: regulator0 {
+ reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
@@ -59,7 +70,7 @@
regulator-always-on;
};
- reg_3p3v: regulator1 {
+ reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
@@ -137,7 +148,7 @@
};
&gpio6 {
- usb1-reset {
+ usb1-reset-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_LOW>;
output-low;
@@ -328,6 +339,8 @@
vqmmc-supply = <®_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
+ no-sd;
+ no-sdio;
non-removable;
fixed-emmc-driver-type = <1>;
status = "okay";
diff --git a/arch/arm/dts/imx6ull-14x14-evk-u-boot.dtsi b/arch/arm/dts/imx6ull-14x14-evk-u-boot.dtsi
index a6c2cc8..0b18571 100644
--- a/arch/arm/dts/imx6ull-14x14-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx6ull-14x14-evk-u-boot.dtsi
@@ -6,3 +6,7 @@
&pinctrl_uart1 {
bootph-all;
};
+
+&rngb {
+ bootph-all;
+};
diff --git a/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi b/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi
index 843b458..c685682 100644
--- a/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi
+++ b/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi
@@ -6,6 +6,12 @@
usb0 = &usbotg1;
display0 = &lcdif;
};
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ bootph-pre-ram;
+ };
};
&usbotg1 {
@@ -45,6 +51,10 @@
};
};
+&wdog1 {
+ bootph-pre-ram;
+};
+
&iomuxc {
pinctrl_backlight: backlight {
fsl,pins = <
diff --git a/arch/arm/dts/imx7d-sdb-u-boot.dtsi b/arch/arm/dts/imx7d-sdb-u-boot.dtsi
index e4a27b8..71bfd80 100644
--- a/arch/arm/dts/imx7d-sdb-u-boot.dtsi
+++ b/arch/arm/dts/imx7d-sdb-u-boot.dtsi
@@ -1,5 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+
#include "imx7s-u-boot.dtsi"
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ bootph-pre-ram;
+ };
+};
+
&fec2 {
status = "disable";
};
@@ -58,3 +68,7 @@
>;
};
};
+
+&wdog1 {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx7d-smegw01-u-boot.dtsi b/arch/arm/dts/imx7d-smegw01-u-boot.dtsi
index 90f7500..611bfe5 100644
--- a/arch/arm/dts/imx7d-smegw01-u-boot.dtsi
+++ b/arch/arm/dts/imx7d-smegw01-u-boot.dtsi
@@ -1,3 +1,16 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "imx7s-u-boot.dtsi"
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ bootph-pre-ram;
+ };
+};
+
+&wdog1 {
+ bootph-pre-ram;
+};
+
diff --git a/arch/arm/dts/imx7s-warp-u-boot.dtsi b/arch/arm/dts/imx7s-warp-u-boot.dtsi
index 49b992d..4f44598 100644
--- a/arch/arm/dts/imx7s-warp-u-boot.dtsi
+++ b/arch/arm/dts/imx7s-warp-u-boot.dtsi
@@ -1,12 +1,12 @@
/ {
- aliases {
- mmc0 = &usdhc3;
- usb0 = &usbotg1;
- };
+ aliases {
+ mmc0 = &usdhc3;
+ usb0 = &usbotg1;
+ };
- chosen {
- stdout-path = &uart1;
- };
+ chosen {
+ stdout-path = &uart1;
+ };
};
&aips3 {
diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-ied-adc0.dts b/arch/arm/dts/imx8mm-cl-iot-gate-ied-adc0.dtso
similarity index 100%
rename from arch/arm/dts/imx8mm-cl-iot-gate-ied-adc0.dts
rename to arch/arm/dts/imx8mm-cl-iot-gate-ied-adc0.dtso
diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-ied-adc1.dts b/arch/arm/dts/imx8mm-cl-iot-gate-ied-adc1.dtso
similarity index 100%
rename from arch/arm/dts/imx8mm-cl-iot-gate-ied-adc1.dts
rename to arch/arm/dts/imx8mm-cl-iot-gate-ied-adc1.dtso
diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-ied-can0.dts b/arch/arm/dts/imx8mm-cl-iot-gate-ied-can0.dtso
similarity index 100%
rename from arch/arm/dts/imx8mm-cl-iot-gate-ied-can0.dts
rename to arch/arm/dts/imx8mm-cl-iot-gate-ied-can0.dtso
diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-ied-can1.dts b/arch/arm/dts/imx8mm-cl-iot-gate-ied-can1.dtso
similarity index 100%
rename from arch/arm/dts/imx8mm-cl-iot-gate-ied-can1.dts
rename to arch/arm/dts/imx8mm-cl-iot-gate-ied-can1.dtso
diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm0.dts b/arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm0.dtso
similarity index 100%
rename from arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm0.dts
rename to arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm0.dtso
diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm1.dts b/arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm1.dtso
similarity index 100%
rename from arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm1.dts
rename to arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm1.dtso
diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-ied.dts b/arch/arm/dts/imx8mm-cl-iot-gate-ied.dtso
similarity index 100%
rename from arch/arm/dts/imx8mm-cl-iot-gate-ied.dts
rename to arch/arm/dts/imx8mm-cl-iot-gate-ied.dtso
diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi b/arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi
index d93e1cb..c4327d3 100644
--- a/arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi
@@ -6,13 +6,6 @@
#include "imx8mm-u-boot.dtsi"
/ {
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
- };
-
wdt-reboot {
compatible = "wdt-reboot";
bootph-pre-ram;
diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
index 1878c4e..219504f 100644
--- a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
@@ -6,13 +6,6 @@
#include "imx8mm-u-boot.dtsi"
/ {
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
- };
-
wdt-reboot {
compatible = "wdt-reboot";
bootph-pre-ram;
diff --git a/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi b/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi
index 144c42b..a235e08 100644
--- a/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi
@@ -77,10 +77,59 @@
&gpio2 {
bootph-pre-ram;
+
+ dsi-reset-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ output-high;
+ gpios = <2 GPIO_ACTIVE_LOW>;
+ line-name = "DSI_RESET_1V8#";
+ };
+
+
+ dsi-irq-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ input;
+ gpios = <3 GPIO_ACTIVE_LOW>;
+ line-name = "DSI_IRQ_1V8#";
+ };
+
+ graphics-prsnt-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ input;
+ gpios = <7 GPIO_ACTIVE_LOW>;
+ line-name = "GRAPHICS_PRSNT_1V8#";
+ };
};
&gpio3 {
bootph-pre-ram;
+
+ bl-enable-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ output-low;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ line-name = "BL_ENABLE_1V8";
+ };
+
+ tft-enable-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ output-low;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ line-name = "TFT_ENABLE_1V8";
+ };
+
+ graphics-gpio0-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ input;
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ line-name = "GRAPHICS_GPIO0_1V8";
+ };
};
&gpio4 {
diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
index 13688ec..9a5b079 100644
--- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@@ -11,13 +11,6 @@
wdt = <&wdog1>;
bootph-pre-ram;
};
-
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
- };
};
&aips4 {
@@ -72,22 +65,6 @@
bootph-pre-ram;
};
-&crypto {
- bootph-pre-ram;
-};
-
-&sec_jr0 {
- bootph-pre-ram;
-};
-
-&sec_jr1 {
- bootph-pre-ram;
-};
-
-&sec_jr2 {
- bootph-pre-ram;
-};
-
&usbmisc1 {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi b/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi
index 65dfd33..ae542fd 100644
--- a/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi
@@ -16,29 +16,6 @@
wdt = <&wdog1>;
bootph-pre-ram;
};
-
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
- };
-};
-
-&crypto {
- bootph-pre-ram;
-};
-
-&sec_jr0 {
- bootph-pre-ram;
-};
-
-&sec_jr1 {
- bootph-pre-ram;
-};
-
-&sec_jr2 {
- bootph-pre-ram;
};
&i2c1 {
diff --git a/arch/arm/dts/imx8mm-phg-u-boot.dtsi b/arch/arm/dts/imx8mm-phg-u-boot.dtsi
index 3ced97c..c9e0b44 100644
--- a/arch/arm/dts/imx8mm-phg-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-phg-u-boot.dtsi
@@ -11,13 +11,6 @@
wdt = <&wdog1>;
bootph-pre-ram;
};
-
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
- };
};
&aips4 {
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index 6085128..06f2f73 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -7,8 +7,23 @@
binman: binman {
multiple-images;
};
+
+#ifdef CONFIG_OPTEE
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+#endif
};
+#ifdef CONFIG_FSL_CAAM
+&crypto {
+ bootph-pre-ram;
+};
+#endif
+
&soc {
bootph-all;
bootph-pre-ram;
@@ -207,6 +222,20 @@
bootph-pre-ram;
};
+#ifdef CONFIG_FSL_CAAM
+&sec_jr0 {
+ bootph-pre-ram;
+};
+
+&sec_jr1 {
+ bootph-pre-ram;
+};
+
+&sec_jr2 {
+ bootph-pre-ram;
+};
+#endif
+
&spba1 {
bootph-all;
bootph-pre-ram;
diff --git a/arch/arm/dts/imx8mm-venice-gw7905-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7905-0x-u-boot.dtsi
new file mode 100644
index 0000000..c259026
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw7905-0x-u-boot.dtsi
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Gateworks Corporation
+ */
+#include "imx8mm-venice-gw700x-u-boot.dtsi"
+
+&gpio1 {
+ app_gpioa {
+ gpio-hog;
+ input;
+ gpios = <13 GPIO_ACTIVE_HIGH>;
+ line-name = "gpioa";
+ };
+
+ app_gpiob {
+ gpio-hog;
+ input;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
+ line-name = "gpiob";
+ };
+};
+
+&gpio4 {
+ pci_usb_sel {
+ gpio-hog;
+ output-low;
+ gpios = <3 GPIO_ACTIVE_HIGH>;
+ line-name = "pci_usb_sel";
+ };
+
+ pci_wdis {
+ gpio-hog;
+ output-high;
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ line-name = "pci_wdis#";
+ };
+};
+
+&gpio5 {
+ app_gpioc {
+ gpio-hog;
+ input;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ line-name = "gpioc";
+ };
+
+ app_gpiod {
+ gpio-hog;
+ input;
+ gpios = <5 GPIO_ACTIVE_HIGH>;
+ line-name = "gpiod";
+ };
+};
+
+/* Disable SOM interfaces not used on baseboard */
+&fec1 {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/imx8mm-venice-gw7905-0x.dts b/arch/arm/dts/imx8mm-venice-gw7905-0x.dts
new file mode 100644
index 0000000..914753f
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw7905-0x.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx8mm.dtsi"
+#include "imx8mm-venice-gw700x.dtsi"
+#include "imx8mm-venice-gw7905.dtsi"
+
+/ {
+ model = "Gateworks Venice GW7905-0x i.MX8MM Development Kit";
+ compatible = "gateworks,imx8mm-gw7905-0x", "fsl,imx8mm";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+/* Disable SOM interfaces not used on baseboard */
+&fec1 {
+ status = "disabled";
+};
+
+&usdhc1 {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/imx8mm-venice-gw7905.dtsi b/arch/arm/dts/imx8mm-venice-gw7905.dtsi
new file mode 100644
index 0000000..9646eb9
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw7905.dtsi
@@ -0,0 +1,303 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
+/ {
+ led-controller {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ pcie0_refclk: pcie0-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pps>;
+ gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ reg_usb2_vbus: regulator-usb2-vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb2_en>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb2_vbus";
+ gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ compatible = "regulator-fixed";
+ regulator-name = "SD2_3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+/* off-board header */
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&gpio1 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "gpioa", "gpiob", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio4 {
+ gpio-line-names =
+ "", "", "", "pci_usb_sel",
+ "", "", "", "pci_wdis#",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio5 {
+ gpio-line-names =
+ "", "", "", "",
+ "gpioc", "gpiod", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ eeprom@52 {
+ compatible = "atmel,24c32";
+ reg = <0x52>;
+ pagesize = <32>;
+ };
+};
+
+/* off-board header */
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+&pcie_phy {
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+ fsl,clkreq-unsupported;
+ clocks = <&pcie0_refclk>;
+ clock-names = "ref";
+ status = "okay";
+};
+
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+/* GPS */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+/* USB1 - Type C front panel SINK port J14 */
+&usbotg1 {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+/* USB2 4-port USB3.0 HUB:
+ * P1 - USBC connector (host only)
+ * P2 - USB2 test connector
+ * P3 - miniPCIe full card
+ * P4 - miniPCIe half card
+ */
+&usbotg2 {
+ dr_mode = "host";
+ vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
+
+/* microSD */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000040 /* GPIOA */
+ MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x40000040 /* GPIOB */
+ MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000106 /* PCI_USBSEL */
+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000106 /* PCIE_WDIS# */
+ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000040 /* GPIOD */
+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000040 /* GPIOC */
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x6 /* LEDG */
+ MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x6 /* LEDR */
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_pcie0: pciegrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x106
+ >;
+ };
+
+ pinctrl_pps: ppsgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106
+ >;
+ };
+
+ pinctrl_reg_usb2_en: regusb2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x6 /* USBHUB_RST# (ext p/u) */
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
+ >;
+ };
+
+ pinctrl_spi2: spi2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x140
+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x140
+ MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x140
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x140
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
index 2b268f5..8efa4dd 100644
--- a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
@@ -6,13 +6,6 @@
#include "imx8mm-u-boot.dtsi"
/ {
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
- };
-
wdt-reboot {
compatible = "wdt-reboot";
bootph-pre-ram;
@@ -34,6 +27,10 @@
bootph-pre-ram;
};
+&aips4 {
+ bootph-pre-ram;
+};
+
&binman_uboot {
offset = <0x5fc00>;
};
@@ -124,6 +121,19 @@
bootph-pre-ram;
};
+&usbmisc1 {
+ bootph-pre-ram;
+};
+
+/* Verdin USB_1 */
+&usbotg1 {
+ bootph-pre-ram;
+};
+
+&usbphynop1 {
+ bootph-pre-ram;
+};
+
&usdhc1 {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 315714f..c31f3de 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -57,22 +57,6 @@
bootph-pre-ram;
};
-&crypto {
- bootph-pre-ram;
-};
-
-&sec_jr0 {
- bootph-pre-ram;
-};
-
-&sec_jr1 {
- bootph-pre-ram;
-};
-
-&sec_jr2 {
- bootph-pre-ram;
-};
-
&usdhc1 {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi
index bc57566..96b1a1b 100644
--- a/arch/arm/dts/imx8mn-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-u-boot.dtsi
@@ -8,12 +8,14 @@
multiple-images;
};
+#ifdef CONFIG_OPTEE
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
+#endif
wdt-reboot {
compatible = "wdt-reboot";
@@ -52,6 +54,12 @@
/delete-property/ assigned-clock-rates;
};
+#ifdef CONFIG_FSL_CAAM
+&crypto {
+ bootph-pre-ram;
+};
+#endif
+
&iomuxc {
bootph-pre-ram;
};
@@ -61,6 +69,20 @@
bootph-all;
};
+#ifdef CONFIG_FSL_CAAM
+&sec_jr0 {
+ bootph-pre-ram;
+};
+
+&sec_jr1 {
+ bootph-pre-ram;
+};
+
+&sec_jr2 {
+ bootph-pre-ram;
+};
+#endif
+
&spba1 {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
index e0caf31..2bbc4a4 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -39,11 +39,11 @@
};
&i2c1 {
- bootph-pre-ram;
+ bootph-all;
};
&pinctrl_i2c1 {
- bootph-pre-ram;
+ bootph-all;
};
&pinctrl_pmic {
@@ -83,5 +83,5 @@
};
&eeprom_som {
- bootph-pre-ram;
+ bootph-all;
};
diff --git a/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi
index b56f3a2..393fd8e 100644
--- a/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi
@@ -11,13 +11,6 @@
wdt = <&wdog1>;
bootph-pre-ram;
};
-
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
- };
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
@@ -28,10 +21,6 @@
bootph-pre-ram;
};
-&crypto {
- bootph-pre-ram;
-};
-
&eqos {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
@@ -138,18 +127,6 @@
u-boot,off-on-delay-us = <20000>;
};
-&sec_jr0 {
- bootph-pre-ram;
-};
-
-&sec_jr1 {
- bootph-pre-ram;
-};
-
-&sec_jr2 {
- bootph-pre-ram;
-};
-
&tpm {
compatible = "tcg,tpm_tis-spi";
};
diff --git a/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi b/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi
index dd0f34f..a2b5976 100644
--- a/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi
@@ -4,6 +4,7 @@
*/
#include "imx8mp-u-boot.dtsi"
+#include "imx8mp-pinfunc.h"
/ {
aliases {
@@ -17,6 +18,17 @@
dmo,ram-coding-gpios = <&gpio3 20 0>, <&gpio4 3 0>, <&gpio4 1 0>;
};
+ reg_usb1_vbus: regulator-usb1-vbus {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1_vbus>;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "USB1_PWR";
+ };
+
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
@@ -55,10 +67,58 @@
&gpio3 {
bootph-pre-ram;
+
+ bl-enable-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ output-low;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ line-name = "BL_ENABLE_1V8";
+ };
+
+ tft-enable-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ output-low;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ line-name = "TFT_ENABLE_1V8";
+ };
+
+ graphics-gpio0-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ input;
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ line-name = "GRAPHICS_GPIO0_1V8";
+ };
};
&gpio4 {
bootph-pre-ram;
+
+ dsi-reset-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ output-high;
+ gpios = <0 GPIO_ACTIVE_LOW>;
+ line-name = "DSI_RESET_1V8#";
+ };
+
+ graphics-prsnt-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ input;
+ gpios = <18 GPIO_ACTIVE_LOW>;
+ line-name = "GRAPHICS_PRSNT_1V8#";
+ };
+
+ dsi-irq-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ input;
+ gpios = <19 GPIO_ACTIVE_LOW>;
+ line-name = "DSI_IRQ_1V8#";
+ };
};
&gpio5 {
@@ -113,6 +173,10 @@
bootph-pre-ram;
};
+&usb3_phy0 {
+ vbus-supply = <®_usb1_vbus>;
+};
+
&usdhc2 {
bootph-pre-ram;
sd-uhs-sdr104;
@@ -128,3 +192,17 @@
&wdog1 {
bootph-pre-ram;
};
+
+&iomuxc {
+ usb1-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x80
+ >;
+ };
+
+ pinctrl_usb1_vbus: usb1-vbus-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x6
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mp-dhcom-pdk-overlay-eth2xfast.dts b/arch/arm/dts/imx8mp-dhcom-pdk-overlay-eth2xfast.dts
new file mode 100644
index 0000000..3b39777
--- /dev/null
+++ b/arch/arm/dts/imx8mp-dhcom-pdk-overlay-eth2xfast.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023 Marek Vasut <marex@denx.de>
+ */
+/dts-v1/;
+/plugin/;
+
+ðphypdk { /* Micrel KSZ9131RNXI */
+ status = "disabled";
+};
diff --git a/arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dts b/arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dts
new file mode 100644
index 0000000..f27e642
--- /dev/null
+++ b/arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023 Marek Vasut <marex@denx.de>
+ */
+/dts-v1/;
+/plugin/;
+
+ðphy0g {
+ reg = <7>;
+};
diff --git a/arch/arm/dts/imx8mp-dhcom-pdk3.dts b/arch/arm/dts/imx8mp-dhcom-pdk3.dts
index c5f0607..867d238 100644
--- a/arch/arm/dts/imx8mp-dhcom-pdk3.dts
+++ b/arch/arm/dts/imx8mp-dhcom-pdk3.dts
@@ -227,10 +227,6 @@
};
};
-ðphy0g {
- reg = <7>;
-};
-
&fec { /* Second ethernet */
pinctrl-0 = <&pinctrl_fec_rgmii>;
phy-handle = <ðphypdk>;
diff --git a/arch/arm/dts/imx8mp-dhcom-som-overlay-eth1xfast.dts b/arch/arm/dts/imx8mp-dhcom-som-overlay-eth1xfast.dts
new file mode 100644
index 0000000..bb5a2b6
--- /dev/null
+++ b/arch/arm/dts/imx8mp-dhcom-som-overlay-eth1xfast.dts
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023 Marek Vasut <marex@denx.de>
+ */
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/imx8mp-clock.h>
+
+&eqos { /* First ethernet */
+ pinctrl-0 = <&pinctrl_eqos_rmii>;
+ phy-handle = <ðphy0f>;
+ phy-mode = "rmii";
+
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
+ <&clk IMX8MP_SYS_PLL2_100M>,
+ <&clk IMX8MP_SYS_PLL2_50M>;
+ assigned-clock-rates = <0>, <100000000>, <50000000>;
+};
+
+ðphy0g { /* Micrel KSZ9131RNXI */
+ status = "disabled";
+};
+
+ðphy0f { /* SMSC LAN8740Ai */
+ status = "okay";
+};
+
+&fec { /* Second ethernet -- HS connector not populated on 1x RMII PHY SoM */
+ status = "disabled";
+};
+
+/* No WiFi/BT chipset on this SoM variant. */
+
+&uart2 {
+ bluetooth {
+ status = "disabled";
+ };
+};
+
+&usdhc1 {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/imx8mp-dhcom-som-overlay-eth2xfast.dts b/arch/arm/dts/imx8mp-dhcom-som-overlay-eth2xfast.dts
new file mode 100644
index 0000000..82dadce
--- /dev/null
+++ b/arch/arm/dts/imx8mp-dhcom-som-overlay-eth2xfast.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023 Marek Vasut <marex@denx.de>
+ */
+#include "imx8mp-dhcom-som-overlay-eth1xfast.dts"
+
+/* Dual RMII 100/Full Fast ethernet on this SoM variant. */
+
+&fec { /* Second ethernet */
+ pinctrl-0 = <&pinctrl_fec_rmii>;
+ phy-handle = <ðphy1f>;
+ phy-mode = "rmii";
+ status = "okay";
+
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
+ <&clk IMX8MP_SYS_PLL2_100M>,
+ <&clk IMX8MP_SYS_PLL2_50M>,
+ <&clk IMX8MP_SYS_PLL2_50M>;
+ assigned-clock-rates = <0>, <100000000>, <50000000>, <0>;
+};
+
+ðphy1f { /* SMSC LAN8740Ai */
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts b/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts
new file mode 100644
index 0000000..0e5d329
--- /dev/null
+++ b/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023 Marek Vasut <marex@denx.de>
+ */
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "imx8mp-pinfunc.h"
+
+&brcmf {
+ reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+};
+
+&eeprom0 { /* EEPROM with EQoS MAC address */
+ compatible = "atmel,24c02";
+ pagesize = <16>;
+};
+
+&eeprom1 { /* EEPROM with FEC MAC address */
+ compatible = "atmel,24c02";
+ pagesize = <16>;
+};
+
+&eeprom0wl {
+ status = "disabled";
+};
+
+&eeprom1wl {
+ status = "disabled";
+};
+
+ðphy0f { /* SMSC LAN8740Ai */
+ pinctrl-0 = <&pinctrl_ethphy0 &pinctrl_ioexp>;
+ reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
+};
+
+ðphy0g { /* Micrel KSZ9131RNXI */
+ pinctrl-0 = <&pinctrl_ethphy0 &pinctrl_ioexp>;
+ reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
+};
+
+&i2c3 {
+ adc@48 {
+ compatible = "ti,tla2024";
+ interrupts-extended;
+ };
+};
+
+&ioexp {
+ status = "disabled";
+};
+
+®_eth_vio {
+ gpio = <&gpio2 10 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pinctrl_enet_vio>;
+ pinctrl-names = "default";
+};
+
+&rv3032 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc>;
+ interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&uart2 {
+ bluetooth {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_bt>;
+ shutdown-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&usb_dwc3_0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_vbus>;
+};
+
+&usdhc1 {
+ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_wl_reg_en>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_usdhc1_wl_reg_en>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_usdhc1_wl_reg_en>;
+};
+
+&iomuxc {
+ pinctrl-0 = <&pinctrl_hog_base
+ &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
+ &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
+ &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
+ &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
+ /* GPIO_M is connected to CLKOUT2 */
+ &pinctrl_dhcom_int>;
+
+ pinctrl_enet_vio: dhcom-enet-vio-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22
+ >;
+ };
+
+ pinctrl_rtc: dhcom-rtc-grp {
+ fsl,pins = <
+ /* RTC_#INT Interrupt */
+ MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x400001c6
+ >;
+ };
+
+ pinctrl_uart2_bt: dhcom-uart2-bt-grp {
+ fsl,pins = <
+ /* BT_REG_EN */
+ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
+ >;
+ };
+
+ pinctrl_usb0_vbus: dhcom-usb0-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x0
+ >;
+ };
+
+ pinctrl_usdhc1_wl_reg_en: dhcom-usdhc1-wl-reg-en-grp {
+ fsl,pins = <
+ /* WL_REG_EN */
+ MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi b/arch/arm/dts/imx8mp-dhcom-som.dtsi
index 9fd8bce..b504d36 100644
--- a/arch/arm/dts/imx8mp-dhcom-som.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi
@@ -25,9 +25,7 @@
reg_eth_vio: regulator-eth-vio {
compatible = "regulator-fixed";
- gpio = <&gpio2 10 GPIO_ACTIVE_LOW>;
- pinctrl-0 = <&pinctrl_enet_vio>;
- pinctrl-names = "default";
+ gpio = <&ioexp 2 GPIO_ACTIVE_LOW>;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
@@ -49,6 +47,14 @@
startup-delay-us = <100>;
vin-supply = <&buck4>;
};
+
+ reg_vdd_3p3v_awo: regulator-vdd-3p3v-awo { /* VDD_3V3_AWO */
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "VDD_3P3V_AWO";
+ };
};
&A53_0 {
@@ -104,7 +110,7 @@
reg = <0>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
- reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>;
/* Non-default PHY population option. */
status = "disabled";
};
@@ -120,7 +126,7 @@
reg = <5>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
- reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>;
/* Default PHY population option. */
status = "okay";
};
@@ -320,8 +326,9 @@
};
adc@48 {
- compatible = "ti,tla2024";
+ compatible = "ti,ads1015";
reg = <0x48>;
+ interrupts-extended = <&ioexp 7 IRQ_TYPE_EDGE_FALLING>;
#address-cells = <1>;
#size-cells = <0>;
@@ -368,24 +375,52 @@
};
eeprom0: eeprom@50 { /* EEPROM with EQoS MAC address */
- compatible = "atmel,24c02";
- pagesize = <16>;
+ compatible = "atmel,24c32"; /* M24C32-D */
+ pagesize = <32>;
reg = <0x50>;
};
rv3032: rtc@51 {
compatible = "microcrystal,rv3032";
reg = <0x51>;
- interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_rtc>;
+ interrupts-extended = <&ioexp 3 IRQ_TYPE_EDGE_FALLING>;
};
eeprom1: eeprom@53 { /* EEPROM with FEC MAC address */
- compatible = "atmel,24c02";
- pagesize = <16>;
+ compatible = "atmel,24c32"; /* M24C32-D */
+ pagesize = <32>;
reg = <0x53>;
};
+
+ eeprom0wl: eeprom@58 {
+ compatible = "atmel,24c32d-wl"; /* M24C32-D WL page of 0x50 */
+ pagesize = <32>;
+ reg = <0x58>;
+ };
+
+ eeprom1wl: eeprom@5b {
+ compatible = "atmel,24c32d-wl"; /* M24C32-D WL page of 0x53 */
+ pagesize = <32>;
+ reg = <0x5b>;
+ };
+
+ ioexp: gpio@74 {
+ compatible = "nxp,pca9539";
+ reg = <0x74>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ioexp>;
+
+ gpio-line-names =
+ "BT_REG_EN", "WL_REG_EN", "VIO_SWITCHED_#EN", "RTC_#INT",
+ "ENET_QOS_#RST", "RGB_OSZ_ENABLE", "USB1_ID", "ADC_ALTER_RDY",
+ "DHCOM-W", "DHCOM-V", "DHCOM-U", "DHCOM-T",
+ "BT_HOST_WAKE", "BT_DEV_WAKE", "", "";
+ };
};
&i2c4 {
@@ -427,6 +462,23 @@
pinctrl-0 = <&pinctrl_uart2>;
uart-has-rtscts;
status = "okay";
+
+ /*
+ * PLL1 at 80 MHz supplies UART2 root with 80 MHz clock,
+ * which with 16x oversampling yields 5 Mbdps baud base,
+ * which can be well divided by 5/4 to achieve 4 Mbdps,
+ * which is exactly the maximum rate supported by muRata
+ * 2AE bluetooth UART.
+ */
+ assigned-clocks = <&clk IMX8MP_CLK_UART2>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+ assigned-clock-rates = <80000000>;
+
+ bluetooth {
+ compatible = "cypress,cyw4373a0-bt";
+ shutdown-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>;
+ max-speed = <4000000>;
+ };
};
&uart3 {
@@ -451,8 +503,6 @@
};
&usb_dwc3_0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0_vbus>;
dr_mode = "otg";
status = "okay";
};
@@ -496,7 +546,7 @@
* connected to the SoC, but can be connected on to
* SoC pin on the carrier board.
*/
- reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&ioexp 1 GPIO_ACTIVE_LOW>;
};
};
@@ -538,8 +588,9 @@
&pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
&pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
&pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
- /* GPIO_M is connected to CLKOUT2 */
- &pinctrl_dhcom_int>;
+ &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
+ &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
+ &pinctrl_dhcom_s &pinctrl_dhcom_int>;
pinctrl-names = "default";
pinctrl_dhcom_a: dhcom-a-grp {
@@ -626,6 +677,55 @@
>;
};
+ pinctrl_dhcom_m: dhcom-m-grp {
+ fsl,pins = <
+ /* CSIx_MCLK */
+ MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x2
+ >;
+ };
+
+ pinctrl_dhcom_n: dhcom-n-grp {
+ fsl,pins = <
+ /* CSI2_D3- */
+ MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x2
+ >;
+ };
+
+ pinctrl_dhcom_o: dhcom-o-grp {
+ fsl,pins = <
+ /* CSI2_D3+ */
+ MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x2
+ >;
+ };
+
+ pinctrl_dhcom_p: dhcom-p-grp {
+ fsl,pins = <
+ /* CSI2_D2- */
+ MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x2
+ >;
+ };
+
+ pinctrl_dhcom_q: dhcom-q-grp {
+ fsl,pins = <
+ /* CSI2_D2+ */
+ MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x2
+ >;
+ };
+
+ pinctrl_dhcom_r: dhcom-r-grp {
+ fsl,pins = <
+ /* CSI2_D1- */
+ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x2
+ >;
+ };
+
+ pinctrl_dhcom_s: dhcom-s-grp {
+ fsl,pins = <
+ /* CSI2_D1+ */
+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x2
+ >;
+ };
+
pinctrl_dhcom_int: dhcom-int-grp {
fsl,pins = <
/* INT_HIGHEST_PRIO */
@@ -699,17 +799,9 @@
>;
};
- pinctrl_enet_vio: dhcom-enet-vio-grp {
- fsl,pins = <
- MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22
- >;
- };
-
pinctrl_ethphy0: dhcom-ethphy0-grp {
fsl,pins = <
- /* ENET1_#RST Reset */
- MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22
- /* ENET1_#INT Interrupt */
+ /* ENET_QOS_#INT Interrupt */
MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x22
>;
};
@@ -834,6 +926,13 @@
>;
};
+ pinctrl_ioexp: dhcom-ioexp-grp {
+ fsl,pins = <
+ /* #GPIO_EXP_INT */
+ MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22
+ >;
+ };
+
pinctrl_pmic: dhcom-pmic-grp {
fsl,pins = <
/* PMIC_nINT */
@@ -847,10 +946,21 @@
>;
};
- pinctrl_rtc: dhcom-rtc-grp {
+ pinctrl_tc9595: dhcom-tc9595-grp {
fsl,pins = <
- /* RTC_#INT Interrupt */
- MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x40000080
+ /* RESET_DSIBRIDGE */
+ MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000146
+ /* DSI-CONV_INT Interrupt */
+ MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x141
+ >;
+ };
+
+ pinctrl_sai3: dhcom-sai3-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
+ MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
+ MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
+ MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
>;
};
@@ -897,12 +1007,6 @@
>;
};
- pinctrl_usb0_vbus: dhcom-usb0-grp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x0
- >;
- };
-
pinctrl_usb1_vbus: dhcom-usb1-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x6
@@ -918,10 +1022,6 @@
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
- /* BT_REG_EN */
- MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
- /* WL_REG_EN */
- MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
>;
};
@@ -933,10 +1033,6 @@
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
- /* BT_REG_EN */
- MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
- /* WL_REG_EN */
- MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
>;
};
@@ -948,10 +1044,6 @@
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
- /* BT_REG_EN */
- MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
- /* WL_REG_EN */
- MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
>;
};
diff --git a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
index 59d31ee..b05be57 100644
--- a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
@@ -42,6 +42,7 @@
};
&gpio3 {
+ bootph-all;
bootph-pre-ram;
};
@@ -133,3 +134,74 @@
&wdog1 {
bootph-pre-ram;
};
+
+&binman {
+ itb {
+ fit {
+ images {
+ fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast {
+ description = "imx8mp-dhcom-som-overlay-eth1xfast";
+ type = "flat_dt";
+ compression = "none";
+
+ blob-ext {
+ filename = "imx8mp-dhcom-som-overlay-eth1xfast.dtbo";
+ };
+ };
+
+ fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast {
+ description = "imx8mp-dhcom-som-overlay-eth2xfast";
+ type = "flat_dt";
+ compression = "none";
+
+ blob-ext {
+ filename = "imx8mp-dhcom-som-overlay-eth2xfast.dtbo";
+ };
+ };
+
+ fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast {
+ description = "imx8mp-dhcom-pdk-overlay-eth2xfast";
+ type = "flat_dt";
+ compression = "none";
+
+ blob-ext {
+ filename = "imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo";
+ };
+ };
+
+ fdt-dto-imx8mp-dhcom-som-overlay-rev100 {
+ description = "imx8mp-dhcom-som-overlay-rev100";
+ type = "flat_dt";
+ compression = "none";
+
+ blob-ext {
+ filename = "imx8mp-dhcom-som-overlay-rev100.dtbo";
+ };
+ };
+
+ fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100 {
+ description = "imx8mp-dhcom-pdk3-overlay-rev100";
+ type = "flat_dt";
+ compression = "none";
+
+ blob-ext {
+ filename = "imx8mp-dhcom-pdk3-overlay-rev100.dtbo";
+ };
+ };
+ };
+
+ configurations {
+ default = "@config-DEFAULT-SEQ";
+
+ @config-SEQ {
+ fdt = "fdt-1",
+ "fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast",
+ "fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast",
+ "fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast",
+ "fdt-dto-imx8mp-dhcom-som-overlay-rev100",
+ "fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index 6784ed2..9ed62f1 100644
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -11,12 +11,6 @@
wdt = <&wdog1>;
bootph-pre-ram;
};
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
- };
};
®_usdhc2_vmmc {
@@ -71,22 +65,6 @@
bootph-pre-ram;
};
-&crypto {
- bootph-pre-ram;
-};
-
-&sec_jr0 {
- bootph-pre-ram;
-};
-
-&sec_jr1 {
- bootph-pre-ram;
-};
-
-&sec_jr2 {
- bootph-pre-ram;
-};
-
&i2c1 {
bootph-pre-ram;
};
@@ -111,6 +89,19 @@
bootph-pre-ram;
};
+&usb_dwc3_0 {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usb3_0 {
+ status = "okay";
+};
+
+&usb3_phy0 {
+ status = "okay";
+};
+
&usdhc1 {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
index d411cf7..cf2a87a 100644
--- a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
@@ -12,13 +12,6 @@
wdt = <&wdog1>;
bootph-pre-ram;
};
-
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
- };
};
®_usdhc2_vmmc {
@@ -69,22 +62,6 @@
bootph-pre-ram;
};
-&crypto {
- bootph-pre-ram;
-};
-
-&sec_jr0 {
- bootph-pre-ram;
-};
-
-&sec_jr1 {
- bootph-pre-ram;
-};
-
-&sec_jr2 {
- bootph-pre-ram;
-};
-
&i2c1 {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
index c4ea536..22171bd 100644
--- a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
@@ -12,13 +12,6 @@
wdt = <&wdog1>;
bootph-pre-ram;
};
-
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
- };
};
&iomuxc {
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi
index 200938a..4fadcae 100644
--- a/arch/arm/dts/imx8mp-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-u-boot.dtsi
@@ -8,8 +8,23 @@
binman: binman {
multiple-images;
};
+
+#ifdef CONFIG_OPTEE
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+#endif
};
+#ifdef CONFIG_FSL_CAAM
+&crypto {
+ bootph-pre-ram;
+};
+#endif
+
&soc {
bootph-all;
bootph-pre-ram;
@@ -53,6 +68,20 @@
bootph-pre-ram;
};
+#ifdef CONFIG_FSL_CAAM
+&sec_jr0 {
+ bootph-pre-ram;
+};
+
+&sec_jr1 {
+ bootph-pre-ram;
+};
+
+&sec_jr2 {
+ bootph-pre-ram;
+};
+#endif
+
&binman {
u-boot-spl-ddr {
filename = "u-boot-spl-ddr.bin";
@@ -171,14 +200,16 @@
filename = "flash.bin";
pad-byte = <0x00>;
- spl: blob-ext@1 {
+ spl {
filename = "spl.bin";
offset = <0x0>;
+ type = "blob-ext";
};
- uboot: blob-ext@2 {
+ binman_uboot: uboot {
filename = "u-boot.itb";
offset = <0x58000>;
+ type = "blob-ext";
};
};
};
diff --git a/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi
new file mode 100644
index 0000000..5c33f8c
--- /dev/null
+++ b/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Gateworks Corporation
+ */
+#include "imx8mp-venice-gw702x-u-boot.dtsi"
+
+&gpio4 {
+ dio_1 {
+ gpio-hog;
+ input;
+ gpios = <8 GPIO_ACTIVE_HIGH>;
+ line-name = "dio1";
+ };
+
+ dio_0 {
+ gpio-hog;
+ input;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ line-name = "dio0";
+ };
+
+ pci_usb_sel {
+ gpio-hog;
+ output-low;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
+ line-name = "pci_usb_sel";
+ };
+
+ dio_3 {
+ gpio-hog;
+ input;
+ gpios = <24 GPIO_ACTIVE_HIGH>;
+ line-name = "dio3";
+ };
+
+ dio_2 {
+ gpio-hog;
+ input;
+ gpios = <26 GPIO_ACTIVE_HIGH>;
+ line-name = "dio2";
+ };
+
+ pci_wdis {
+ gpio-hog;
+ output-high;
+ gpios = <28 GPIO_ACTIVE_HIGH>;
+ line-name = "pci_wdis#";
+ };
+};
+
+/* gpio-usb-con not supported yet in U-Boot so make this a host for now */
+&usb_dwc3_0 {
+ dr_mode = "host";
+};
diff --git a/arch/arm/dts/imx8mp-venice-gw71xx-2x.dts b/arch/arm/dts/imx8mp-venice-gw71xx-2x.dts
new file mode 100644
index 0000000..53120fc
--- /dev/null
+++ b/arch/arm/dts/imx8mp-venice-gw71xx-2x.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx8mp.dtsi"
+#include "imx8mp-venice-gw702x.dtsi"
+#include "imx8mp-venice-gw71xx.dtsi"
+
+/ {
+ model = "Gateworks Venice GW71xx-2x i.MX8MP Development Kit";
+ compatible = "gateworks,imx8mp-gw71xx-2x", "fsl,imx8mp";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
diff --git a/arch/arm/dts/imx8mp-venice-gw71xx.dtsi b/arch/arm/dts/imx8mp-venice-gw71xx.dtsi
new file mode 100644
index 0000000..86999f5
--- /dev/null
+++ b/arch/arm/dts/imx8mp-venice-gw71xx.dtsi
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
+/ {
+ led-controller {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ pcie0_refclk: pcie0-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pps>;
+ gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+};
+
+/* off-board header */
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&gpio4 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "dio1", "", "", "dio0",
+ "", "", "pci_usb_sel", "",
+ "", "", "", "",
+ "", "", "", "",
+ "dio3", "", "dio2", "",
+ "pci_wdis#", "", "", "";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ accelerometer@19 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_accel>;
+ compatible = "st,lis2de12";
+ reg = <0x19>;
+ st,drdy-int-pin = <1>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "INT1";
+ };
+};
+
+&pcie_phy {
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+ fsl,clkreq-unsupported;
+ clocks = <&pcie0_refclk>;
+ clock-names = "ref";
+ status = "okay";
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+/* GPS */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+/* off-board header */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+/* USB1 Type-C front panel */
+&usb3_0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ fsl,over-current-active-low;
+ status = "okay";
+};
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ /* dual role is implemented but not a full featured OTG */
+ adp-disable;
+ hnp-disable;
+ srp-disable;
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "peripheral";
+ status = "okay";
+
+ connector {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbcon1>;
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ type = "micro";
+ label = "Type-C";
+ id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* USB2 - MiniPCIe socket */
+&usb3_1 {
+ fsl,permanently-attached;
+ fsl,disable-port-power-control;
+ status = "okay";
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */
+ MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */
+ MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */
+ MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000146 /* DIO2 */
+ MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x40000146 /* DIO3 */
+ MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */
+ >;
+ };
+
+ pinctrl_accel: accelgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */
+ MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */
+ >;
+ };
+
+ pinctrl_pcie0: pcie0grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106
+ >;
+ };
+
+ pinctrl_pps: ppsgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146
+ >;
+ };
+
+ pinctrl_usb1: usb1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */
+ >;
+ };
+
+ pinctrl_usbcon1: usbcon1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */
+ >;
+ };
+
+ pinctrl_spi2: spi2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140
+ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
+ MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
+ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
+ MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mp-venice-gw72xx-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw72xx-2x-u-boot.dtsi
new file mode 100644
index 0000000..7f2609a
--- /dev/null
+++ b/arch/arm/dts/imx8mp-venice-gw72xx-2x-u-boot.dtsi
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Gateworks Corporation
+ */
+#include "imx8mp-venice-gw702x-u-boot.dtsi"
+
+&gpio4 {
+ dio_1 {
+ gpio-hog;
+ input;
+ gpios = <8 GPIO_ACTIVE_HIGH>;
+ line-name = "dio1";
+ };
+
+ dio_0 {
+ gpio-hog;
+ input;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ line-name = "dio0";
+ };
+
+ pci_usb_sel {
+ gpio-hog;
+ output-low;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
+ line-name = "pci_usb_sel";
+ };
+
+ mipi_gpio4 {
+ gpio-hog;
+ input;
+ gpios = <17 GPIO_ACTIVE_HIGH>;
+ line-name = "mipi_gpio4";
+ };
+
+ rs485_en {
+ gpio-hog;
+ output-low;
+ gpios = <22 GPIO_ACTIVE_HIGH>;
+ line-name = "rs485_en";
+ };
+
+ rs485_term {
+ gpio-hog;
+ output-low;
+ gpios = <23 GPIO_ACTIVE_HIGH>;
+ line-name = "rs485_term";
+ };
+
+ mipi_gpio1 {
+ gpio-hog;
+ input;
+ gpios = <24 GPIO_ACTIVE_HIGH>;
+ line-name = "mipi_gpio1";
+ };
+
+ mipi_gpio3 {
+ gpio-hog;
+ input;
+ gpios = <25 GPIO_ACTIVE_HIGH>;
+ line-name = "mipi_gpio3";
+ };
+
+ mipi_gpio2 {
+ gpio-hog;
+ input;
+ gpios = <26 GPIO_ACTIVE_HIGH>;
+ line-name = "mipi_gpio2";
+ };
+
+ rs485_hd {
+ gpio-hog;
+ output-low;
+ gpios = <27 GPIO_ACTIVE_HIGH>;
+ line-name = "rs485_hd";
+ };
+
+ pci_wdis {
+ gpio-hog;
+ output-high;
+ gpios = <28 GPIO_ACTIVE_HIGH>;
+ line-name = "pci_wdis#";
+ };
+};
+
+/* gpio-usb-con not supported yet in U-Boot so make this a host for now */
+&usb_dwc3_0 {
+ dr_mode = "host";
+};
diff --git a/arch/arm/dts/imx8mp-venice-gw72xx-2x.dts b/arch/arm/dts/imx8mp-venice-gw72xx-2x.dts
new file mode 100644
index 0000000..255e36f
--- /dev/null
+++ b/arch/arm/dts/imx8mp-venice-gw72xx-2x.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx8mp.dtsi"
+#include "imx8mp-venice-gw702x.dtsi"
+#include "imx8mp-venice-gw72xx.dtsi"
+
+/ {
+ model = "Gateworks Venice GW72xx-2x i.MX8MP Development Kit";
+ compatible = "gateworks,imx8mp-gw72xx-2x", "fsl,imx8mp";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
diff --git a/arch/arm/dts/imx8mp-venice-gw72xx.dtsi b/arch/arm/dts/imx8mp-venice-gw72xx.dtsi
new file mode 100644
index 0000000..e05fdec
--- /dev/null
+++ b/arch/arm/dts/imx8mp-venice-gw72xx.dtsi
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
+/ {
+ led-controller {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ pcie0_refclk: pcie0-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pps>;
+ gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ reg_usb1_vbus: regulator-usb1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb1_en>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb1_vbus";
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb2_vbus: regulator-usb2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb2_en>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb2_vbus";
+ gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_3V3_SD";
+ enable-active-high;
+ gpio = <&gpio2 19 0>; /* SD2_RESET */
+ off-on-delay-us = <12000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ startup-delay-us = <100>;
+ };
+};
+
+/* off-board header */
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&gpio4 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "dio1", "", "", "dio0",
+ "", "", "pci_usb_sel", "",
+ "", "", "", "",
+ "", "", "rs485_en", "rs485_term",
+ "", "", "", "rs485_half",
+ "pci_wdis#", "", "", "";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ accelerometer@19 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_accel>;
+ compatible = "st,lis2de12";
+ reg = <0x19>;
+ st,drdy-int-pin = <1>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "INT1";
+ };
+};
+
+&pcie_phy {
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+ fsl,clkreq-unsupported;
+ clocks = <&pcie0_refclk>;
+ clock-names = "ref";
+ status = "okay";
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+/* GPS */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+/* off-board header */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+/* RS232 */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+/* USB1 - OTG */
+&usb3_0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ fsl,over-current-active-low;
+ status = "okay";
+};
+
+&usb3_phy0 {
+ vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ /* dual role is implemented but not a full featured OTG */
+ adp-disable;
+ hnp-disable;
+ srp-disable;
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "peripheral";
+ status = "okay";
+
+ connector {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbcon1>;
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ type = "micro";
+ label = "otg";
+ id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* USB2 - USB3.0 Hub */
+&usb3_1 {
+ fsl,permanently-attached;
+ fsl,disable-port-power-control;
+ status = "okay";
+};
+
+&usb3_phy1 {
+ vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+/* microSD */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */
+ MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */
+ MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */
+ MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */
+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */
+ MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */
+ MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */
+ >;
+ };
+
+ pinctrl_accel: accelgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */
+ MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */
+ >;
+ };
+
+ pinctrl_pcie0: pcie0grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106
+ >;
+ };
+
+ pinctrl_pps: ppsgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146
+ >;
+ };
+
+ pinctrl_reg_usb1_en: regusb1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */
+ >;
+ };
+
+ pinctrl_usb1: usb1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */
+ >;
+ };
+
+ pinctrl_usbcon1: usbcon1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */
+ >;
+ };
+
+ pinctrl_reg_usb2_en: regusb2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */
+ >;
+ };
+
+ pinctrl_spi2: spi2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140
+ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
+ MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
+ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
+ MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
+ MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi
new file mode 100644
index 0000000..70433c0
--- /dev/null
+++ b/arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Gateworks Corporation
+ */
+#include "imx8mp-venice-gw702x-u-boot.dtsi"
+
+ðphy0 {
+ reset-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <1000>;
+ reset-post-delay-us = <300000>;
+};
+
+&gpio4 {
+ dio_1 {
+ gpio-hog;
+ input;
+ gpios = <8 GPIO_ACTIVE_HIGH>;
+ line-name = "dio1";
+ };
+
+ dio_0 {
+ gpio-hog;
+ input;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ line-name = "dio0";
+ };
+
+ pci_usb_sel {
+ gpio-hog;
+ output-low;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
+ line-name = "pci_usb_sel";
+ };
+
+ mipi_gpio4 {
+ gpio-hog;
+ input;
+ gpios = <17 GPIO_ACTIVE_HIGH>;
+ line-name = "mipi_gpio4";
+ };
+
+ rs485_en {
+ gpio-hog;
+ output-low;
+ gpios = <22 GPIO_ACTIVE_HIGH>;
+ line-name = "rs485_en";
+ };
+
+ rs485_term {
+ gpio-hog;
+ output-low;
+ gpios = <23 GPIO_ACTIVE_HIGH>;
+ line-name = "rs485_term";
+ };
+
+ mipi_gpio1 {
+ gpio-hog;
+ input;
+ gpios = <24 GPIO_ACTIVE_HIGH>;
+ line-name = "mipi_gpio1";
+ };
+
+ mipi_gpio3 {
+ gpio-hog;
+ input;
+ gpios = <25 GPIO_ACTIVE_HIGH>;
+ line-name = "mipi_gpio3";
+ };
+
+ mipi_gpio2 {
+ gpio-hog;
+ input;
+ gpios = <26 GPIO_ACTIVE_HIGH>;
+ line-name = "mipi_gpio2";
+ };
+
+ rs485_hd {
+ gpio-hog;
+ output-low;
+ gpios = <27 GPIO_ACTIVE_HIGH>;
+ line-name = "rs485_hd";
+ };
+
+ pci_wdis {
+ gpio-hog;
+ output-high;
+ gpios = <28 GPIO_ACTIVE_HIGH>;
+ line-name = "pci_wdis#";
+ };
+};
+
+/* gpio-usb-con not supported yet in U-Boot so make this a host for now */
+&usb_dwc3_0 {
+ dr_mode = "host";
+};
diff --git a/arch/arm/dts/imx8mp-venice-gw73xx-2x.dts b/arch/arm/dts/imx8mp-venice-gw73xx-2x.dts
new file mode 100644
index 0000000..000fd15
--- /dev/null
+++ b/arch/arm/dts/imx8mp-venice-gw73xx-2x.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx8mp.dtsi"
+#include "imx8mp-venice-gw702x.dtsi"
+#include "imx8mp-venice-gw73xx.dtsi"
+
+/ {
+ model = "Gateworks Venice GW73xx-2x i.MX8MP Development Kit";
+ compatible = "gateworks,imx8mp-gw73xx-2x", "fsl,imx8mp";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
diff --git a/arch/arm/dts/imx8mp-venice-gw73xx.dtsi b/arch/arm/dts/imx8mp-venice-gw73xx.dtsi
new file mode 100644
index 0000000..1c05398
--- /dev/null
+++ b/arch/arm/dts/imx8mp-venice-gw73xx.dtsi
@@ -0,0 +1,414 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
+/ {
+ led-controller {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ pcie0_refclk: pcie0-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pps>;
+ gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ reg_usb1_vbus: regulator-usb1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb1_en>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb1_vbus";
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb2_vbus: regulator-usb2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb2_en>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb2_vbus";
+ gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_wifi_en: regulator-wifi-en {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_wl>;
+ compatible = "regulator-fixed";
+ regulator-name = "wl";
+ gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <100>;
+ enable-active-high;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_3V3_SD";
+ enable-active-high;
+ gpio = <&gpio2 19 0>; /* SD2_RESET */
+ off-on-delay-us = <12000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ startup-delay-us = <100>;
+ };
+};
+
+/* off-board header */
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&gpio4 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "dio1", "", "", "dio0",
+ "", "", "pci_usb_sel", "",
+ "", "", "", "",
+ "", "", "rs485_en", "rs485_term",
+ "", "", "", "rs485_half",
+ "pci_wdis#", "", "", "";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ accelerometer@19 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_accel>;
+ compatible = "st,lis2de12";
+ reg = <0x19>;
+ st,drdy-int-pin = <1>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "INT1";
+ };
+};
+
+&pcie_phy {
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+ fsl,clkreq-unsupported;
+ clocks = <&pcie0_refclk>;
+ clock-names = "ref";
+ status = "okay";
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+/* GPS */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+/* bluetooth HCI */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>;
+ cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
+ rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4330-bt";
+ shutdown-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* RS232 */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+/* USB1 - OTG */
+&usb3_0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ fsl,over-current-active-low;
+ status = "okay";
+};
+
+&usb3_phy0 {
+ vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ /* dual role is implemented but not a full featured OTG */
+ adp-disable;
+ hnp-disable;
+ srp-disable;
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "peripheral";
+ status = "okay";
+
+ connector {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbcon1>;
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ type = "micro";
+ label = "otg";
+ id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* USB2 - USB3.0 Hub */
+&usb3_1 {
+ fsl,permanently-attached;
+ fsl,disable-port-power-control;
+ status = "okay";
+};
+
+&usb3_phy1 {
+ vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+/* SDIO WiFi */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <4>;
+ non-removable;
+ vmmc-supply = <®_wifi_en>;
+ status = "okay";
+};
+
+/* microSD */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */
+ MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */
+ MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */
+ MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */
+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */
+ MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */
+ MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */
+ >;
+ };
+
+ pinctrl_accel: accelgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */
+ >;
+ };
+
+ pinctrl_bten: btengrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x146
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */
+ MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */
+ >;
+ };
+
+ pinctrl_pcie0: pcie0grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106
+ >;
+ };
+
+ pinctrl_pps: ppsgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146
+ >;
+ };
+
+ pinctrl_reg_wl: regwlgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x146
+ >;
+ };
+
+ pinctrl_reg_usb1_en: regusb1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */
+ >;
+ };
+
+ pinctrl_usb1: usb1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */
+ >;
+ };
+
+ pinctrl_usbcon1: usbcon1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */
+ >;
+ };
+
+ pinctrl_reg_usb2_en: regusb2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */
+ >;
+ };
+
+ pinctrl_spi2: spi2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140
+ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
+ MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
+ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
+ MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
+ MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x140
+ MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
+ MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi
index c3fb040..240fbc1 100644
--- a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi
@@ -6,13 +6,6 @@
#include "imx8mp-u-boot.dtsi"
/ {
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
- };
-
wdt-reboot {
compatible = "wdt-reboot";
bootph-pre-ram;
@@ -53,67 +46,81 @@
&gpio2 {
bootph-pre-ram;
- pcie1_wdis_hog {
+ m2_pin20 {
gpio-hog;
- gpios = <17 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "pcie1_wdis#";
+ input;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ line-name = "m2_pin20";
};
- pcie2_wdis_hog {
+ m2_pin22 {
gpio-hog;
- gpios = <18 GPIO_ACTIVE_HIGH>;
+ input;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ line-name = "m2_pin22";
+ };
+
+ tpm_rst_hog {
+ gpio-hog;
output-high;
- line-name = "pcie2_wdis#";
+ gpios = <12 GPIO_ACTIVE_HIGH>;
+ line-name = "tpm_rst#";
+ };
+
+ pcie1_wdis_hog {
+ gpio-hog;
+ output-high;
+ gpios = <13 GPIO_ACTIVE_HIGH>;
+ line-name = "pcie1_wdis#";
};
pcie3_wdis_hog {
gpio-hog;
- gpios = <14 GPIO_ACTIVE_HIGH>;
output-high;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
line-name = "pcie3_wdis#";
};
+
+ pcie2_wdis_hog {
+ gpio-hog;
+ output-high;
+ gpios = <18 GPIO_ACTIVE_HIGH>;
+ line-name = "pcie2_wdis#";
+ };
};
&gpio3 {
bootph-pre-ram;
- m2_dis2_hog {
+ m2_rst {
gpio-hog;
- gpios = <0 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "m2_gdis#";
- };
-
- m2rst_hog {
- gpio-hog;
+ output-low;
gpios = <6 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "m2_rst#";
- };
-
- m2_off_hog {
- gpio-hog;
- gpios = <14 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "m2_off#";
+ line-name = "m2_rst";
};
};
&gpio4 {
bootph-pre-ram;
- m2_dis1_hog {
+ m2_off {
gpio-hog;
- gpios = <18 GPIO_ACTIVE_HIGH>;
output-high;
+ gpios = <2 GPIO_ACTIVE_HIGH>;
+ line-name = "m2_off#";
+ };
+
+ m2_wdis {
+ gpio-hog;
+ output-high;
+ gpios = <18 GPIO_ACTIVE_HIGH>;
line-name = "m2_wdis#";
};
rs485_en {
gpio-hog;
- gpios = <31 GPIO_ACTIVE_HIGH>;
output-low;
+ gpios = <31 GPIO_ACTIVE_HIGH>;
line-name = "rs485_en";
};
};
@@ -123,15 +130,15 @@
rs485_half {
gpio-hog;
- gpios = <0 GPIO_ACTIVE_HIGH>;
output-low;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
line-name = "rs485_hd";
};
rs485_term {
gpio-hog;
- gpios = <1 GPIO_ACTIVE_HIGH>;
output-low;
+ gpios = <1 GPIO_ACTIVE_HIGH>;
line-name = "rs485_term";
};
};
diff --git a/arch/arm/dts/imx8mp-venice-gw74xx.dts b/arch/arm/dts/imx8mp-venice-gw74xx.dts
index ceeca49..7eb2853 100644
--- a/arch/arm/dts/imx8mp-venice-gw74xx.dts
+++ b/arch/arm/dts/imx8mp-venice-gw74xx.dts
@@ -125,12 +125,22 @@
regulator-max-microvolt = <5000000>;
};
+ reg_can1_stby: regulator-can1-stby {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_can1>;
+ regulator-name = "can1_stby";
+ gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
reg_can2_stby: regulator-can2-stby {
compatible = "regulator-fixed";
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_can>;
+ pinctrl-0 = <&pinctrl_reg_can2>;
regulator-name = "can2_stby";
- gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio5 5 GPIO_ACTIVE_LOW>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
@@ -164,6 +174,21 @@
cpu-supply = <®_arm>;
};
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ tpm@0 {
+ compatible = "tcg,tpm_tis-spi";
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ reg = <0x0>;
+ spi-max-frequency = <36000000>;
+ };
+};
+
/* off-board header */
&ecspi2 {
pinctrl-names = "default";
@@ -204,6 +229,13 @@
};
};
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <®_can1_stby>;
+ status = "okay";
+};
+
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
@@ -214,38 +246,38 @@
&gpio1 {
gpio-line-names =
"", "", "", "", "", "", "", "",
- "", "", "dio0", "", "dio1", "", "", "",
+ "", "dio0", "", "dio1", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio2 {
gpio-line-names =
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "pcie3_wdis#", "",
+ "", "", "", "", "", "", "m2_pin20", "",
+ "", "", "", "", "", "pcie1_wdis#", "pcie3_wdis#", "",
"", "", "pcie2_wdis#", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio3 {
gpio-line-names =
- "m2_gdis#", "", "", "", "", "", "", "m2_rst#",
+ "", "", "", "", "", "", "m2_rst", "",
"", "", "", "", "", "", "", "",
- "m2_off#", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio4 {
gpio-line-names =
+ "", "", "m2_off#", "", "", "", "", "",
"", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "m2_wdis#", "", "", "",
- "", "", "", "", "", "", "", "uart_rs485";
+ "", "", "m2_wdis#", "", "", "", "", "",
+ "", "", "", "", "", "", "", "rs485_en";
};
&gpio5 {
gpio-line-names =
- "uart_half", "uart_term", "", "", "", "", "", "",
+ "rs485_hd", "rs485_term", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
@@ -268,6 +300,8 @@
interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
@@ -286,6 +320,12 @@
label = "vdd_bat";
};
+ channel@16 {
+ gw,mode = <4>;
+ reg = <0x16>;
+ label = "fan_tach";
+ };
+
channel@82 {
gw,mode = <2>;
reg = <0x82>;
@@ -358,6 +398,11 @@
gw,voltage-divider-ohms = <10000 10000>;
};
};
+
+ fan-controller@a {
+ compatible = "gw,gsc-fan";
+ reg = <0x0a>;
+ };
};
gpio: gpio@23 {
@@ -369,85 +414,6 @@
interrupts = <4>;
};
- pmic@25 {
- compatible = "nxp,pca9450c";
- reg = <0x25>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- interrupt-parent = <&gpio3>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
-
- regulators {
- BUCK1 {
- regulator-name = "BUCK1";
- regulator-min-microvolt = <720000>;
- regulator-max-microvolt = <1000000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <3125>;
- };
-
- reg_arm: BUCK2 {
- regulator-name = "BUCK2";
- regulator-min-microvolt = <720000>;
- regulator-max-microvolt = <1025000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <3125>;
- nxp,dvs-run-voltage = <950000>;
- nxp,dvs-standby-voltage = <850000>;
- };
-
- BUCK4 {
- regulator-name = "BUCK4";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3600000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- BUCK5 {
- regulator-name = "BUCK5";
- regulator-min-microvolt = <1650000>;
- regulator-max-microvolt = <1950000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- BUCK6 {
- regulator-name = "BUCK6";
- regulator-min-microvolt = <1045000>;
- regulator-max-microvolt = <1155000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- LDO1 {
- regulator-name = "LDO1";
- regulator-min-microvolt = <1650000>;
- regulator-max-microvolt = <1950000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- LDO3 {
- regulator-name = "LDO3";
- regulator-min-microvolt = <1710000>;
- regulator-max-microvolt = <1890000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- LDO5 {
- regulator-name = "LDO5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
@@ -559,7 +525,6 @@
};
};
-/* off-board header */
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
@@ -568,6 +533,85 @@
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
+
+ pmic@25 {
+ compatible = "nxp,pca9450c";
+ reg = <0x25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ reg_arm: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1025000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <850000>;
+ };
+
+ BUCK4 {
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ BUCK5 {
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <1045000>;
+ regulator-max-microvolt = <1155000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <1710000>;
+ regulator-max-microvolt = <1890000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
};
/* off-board header */
@@ -734,12 +778,14 @@
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */
MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */
- MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_OFF# */
- MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */
- MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */
- MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */
+ MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x40000040 /* M2SKT_OFF# */
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */
- MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000150 /* M2SKT_GDIS# */
+ MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40000040 /* M2SKT_PIN20 */
+ MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x40000040 /* M2SKT_PIN22 */
+ MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x40000150 /* PCIE1_WDIS# */
+ MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */
+ MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */
+ MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */
MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */
MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */
MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */
@@ -792,6 +838,13 @@
>;
};
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
+ MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
+ >;
+ };
+
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
@@ -877,7 +930,7 @@
pinctrl_pcie0: pciegrp {
fsl,pins = <
- MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x110
+ MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x106
>;
};
@@ -893,12 +946,18 @@
>;
};
- pinctrl_reg_can: regcangrp {
+ pinctrl_reg_can1: regcan1grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154
>;
};
+ pinctrl_reg_can2: regcan2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154
+ >;
+ };
+
pinctrl_reg_usb2: regusb2grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140
@@ -911,12 +970,12 @@
>;
};
- pinctrl_sai2: sai2grp {
+ pinctrl_spi1: spi1grp {
fsl,pins = <
- MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
- MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
- MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
- MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6
+ MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82
+ MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82
+ MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82
+ MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140
>;
};
diff --git a/arch/arm/dts/imx8mp-venice-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-u-boot.dtsi
index 99d7639..07813d0 100644
--- a/arch/arm/dts/imx8mp-venice-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-venice-u-boot.dtsi
@@ -73,6 +73,14 @@
bootph-pre-ram;
};
+&i2c3 {
+ bootph-pre-ram;
+};
+
+&pinctrl_i2c3 {
+ bootph-pre-ram;
+};
+
&wdog1 {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/imx8mp-venice.dts b/arch/arm/dts/imx8mp-venice.dts
index 77e5ac4..372db26 100644
--- a/arch/arm/dts/imx8mp-venice.dts
+++ b/arch/arm/dts/imx8mp-venice.dts
@@ -57,6 +57,13 @@
};
};
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
/* console */
&uart2 {
pinctrl-names = "default";
@@ -106,6 +113,13 @@
>;
};
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
+ >;
+ };
+
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
diff --git a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
index 0162f9b..2a1aa19 100644
--- a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
@@ -6,13 +6,6 @@
#include "imx8mp-u-boot.dtsi"
/ {
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
- };
-
wdt-reboot {
compatible = "wdt-reboot";
bootph-pre-ram;
@@ -35,10 +28,6 @@
};
-&crypto {
- bootph-pre-ram;
-};
-
&gpio1 {
bootph-pre-ram;
};
@@ -147,18 +136,6 @@
bootph-pre-ram;
};
-&sec_jr0 {
- bootph-pre-ram;
-};
-
-&sec_jr1 {
- bootph-pre-ram;
-};
-
-&sec_jr2 {
- bootph-pre-ram;
-};
-
&uart3 {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
index 5b465e2..a9dffa5 100644
--- a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
@@ -8,6 +8,7 @@
compatible = "wdt-reboot";
wdt = <&wdog3>;
bootph-pre-ram;
+ bootph-some-ram;
};
firmware {
@@ -30,19 +31,23 @@
&aips2 {
bootph-pre-ram;
+ bootph-some-ram;
};
&aips3 {
bootph-pre-ram;
+ bootph-some-ram;
};
&iomuxc {
bootph-pre-ram;
+ bootph-some-ram;
};
®_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
bootph-pre-ram;
+ bootph-some-ram;
};
&pinctrl_reg_usdhc2_vmmc {
@@ -51,59 +56,73 @@
&pinctrl_uart1 {
bootph-pre-ram;
+ bootph-some-ram;
};
&pinctrl_usdhc2_gpio {
bootph-pre-ram;
+ bootph-some-ram;
};
&pinctrl_usdhc2 {
bootph-pre-ram;
+ bootph-some-ram;
};
&gpio1 {
bootph-pre-ram;
+ bootph-some-ram;
};
&gpio2 {
bootph-pre-ram;
+ bootph-some-ram;
};
&gpio3 {
bootph-pre-ram;
+ bootph-some-ram;
};
&gpio4 {
bootph-pre-ram;
+ bootph-some-ram;
};
&lpuart1 {
bootph-pre-ram;
+ bootph-some-ram;
};
&usdhc1 {
bootph-pre-ram;
+ bootph-some-ram;
};
&usdhc2 {
bootph-pre-ram;
+ bootph-some-ram;
fsl,signal-voltage-switch-extra-delay-ms = <8>;
};
&lpi2c2 {
bootph-pre-ram;
+ bootph-some-ram;
};
&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
bootph-pre-ram;
+ bootph-some-ram;
};
&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
bootph-pre-ram;
+ bootph-some-ram;
};
&pinctrl_lpi2c2 {
bootph-pre-ram;
+ bootph-some-ram;
};
&fec {
@@ -124,5 +143,29 @@
&s4muap {
bootph-pre-ram;
+ bootph-some-ram;
status = "okay";
};
+
+&clk {
+ bootph-all;
+ bootph-pre-ram;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-rates;
+ /delete-property/ assigned-clock-parents;
+};
+
+&osc_32k {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&osc_24m {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&clk_ext1 {
+ bootph-all;
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi
index 13cf32d..90de635 100644
--- a/arch/arm/dts/imx93.dtsi
+++ b/arch/arm/dts/imx93.dtsi
@@ -254,8 +254,8 @@
compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x44380000 0x1000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPUART1_GATE>;
- clock-names = "ipg";
+ clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>;
+ clock-names = "ipg", "per";
status = "disabled";
};
diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi
index 2488e3a..284b90c 100644
--- a/arch/arm/dts/k3-am62-main.dtsi
+++ b/arch/arm/dts/k3-am62-main.dtsi
@@ -55,11 +55,29 @@
#phy-cells = <1>;
};
- epwm_tbclk: clock@4130 {
- compatible = "ti,am62-epwm-tbclk", "syscon";
+ epwm_tbclk: clock-controller@4130 {
+ compatible = "ti,am62-epwm-tbclk";
reg = <0x4130 0x4>;
#clock-cells = <1>;
};
+
+ audio_refclk0: clock-controller@82e0 {
+ compatible = "ti,am62-audio-refclk";
+ reg = <0x82e0 0x4>;
+ clocks = <&k3_clks 157 0>;
+ assigned-clocks = <&k3_clks 157 0>;
+ assigned-clock-parents = <&k3_clks 157 8>;
+ #clock-cells = <0>;
+ };
+
+ audio_refclk1: clock-controller@82e4 {
+ compatible = "ti,am62-audio-refclk";
+ reg = <0x82e4 0x4>;
+ clocks = <&k3_clks 157 10>;
+ assigned-clocks = <&k3_clks 157 10>;
+ assigned-clock-parents = <&k3_clks 157 18>;
+ #clock-cells = <0>;
+ };
};
dmss: bus@48000000 {
@@ -174,7 +192,6 @@
crypto: crypto@40900000 {
compatible = "ti,am62-sa3ul";
reg = <0x00 0x40900000 0x00 0x1200>;
- power-domains = <&k3_pds 70 TI_SCI_PD_SHARED>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
@@ -590,7 +607,7 @@
usb0: usb@31000000 {
compatible = "snps,dwc3";
- reg =<0x00 0x31000000 0x00 0x50000>;
+ reg = <0x00 0x31000000 0x00 0x50000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
interrupt-names = "host", "peripheral";
@@ -613,7 +630,7 @@
usb1: usb@31100000 {
compatible = "snps,dwc3";
- reg =<0x00 0x31100000 0x00 0x50000>;
+ reg = <0x00 0x31100000 0x00 0x50000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
interrupt-names = "host", "peripheral";
@@ -718,6 +735,31 @@
};
};
+ dss: dss@30200000 {
+ compatible = "ti,am625-dss";
+ reg = <0x00 0x30200000 0x00 0x1000>, /* common */
+ <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
+ <0x00 0x30206000 0x00 0x1000>, /* vid */
+ <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
+ <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
+ <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */
+ <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */
+ reg-names = "common", "vidl1", "vid",
+ "ovr1", "ovr2", "vp1", "vp2";
+ power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 186 6>,
+ <&dss_vp1_clk>,
+ <&k3_clks 186 2>;
+ clock-names = "fck", "vp1", "vp2";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+
+ dss_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
hwspinlock: spinlock@2a000000 {
compatible = "ti,am64-hwspinlock";
reg = <0x00 0x2a000000 0x00 0x1000>;
diff --git a/arch/arm/dts/k3-am62-mcu.dtsi b/arch/arm/dts/k3-am62-mcu.dtsi
index 19fc381..80a3e1d 100644
--- a/arch/arm/dts/k3-am62-mcu.dtsi
+++ b/arch/arm/dts/k3-am62-mcu.dtsi
@@ -147,4 +147,28 @@
/* Tightly coupled to M4F */
status = "reserved";
};
+
+ mcu_mcan0: can@4e08000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x4e08000 0x00 0x200>,
+ <0x00 0x4e00000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 188 6>, <&k3_clks 188 1>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ mcu_mcan1: can@4e18000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x4e18000 0x00 0x200>,
+ <0x00 0x4e10000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 189 6>, <&k3_clks 189 1>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
};
diff --git a/arch/arm/dts/k3-am62-verdin-dev.dtsi b/arch/arm/dts/k3-am62-verdin-dev.dtsi
index 846caee..6701cb8 100644
--- a/arch/arm/dts/k3-am62-verdin-dev.dtsi
+++ b/arch/arm/dts/k3-am62-verdin-dev.dtsi
@@ -8,6 +8,42 @@
* https://www.toradex.com/products/carrier-board/verdin-development-board-kit
*/
+/ {
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,bitclock-master = <&codec_dai>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&codec_dai>;
+ simple-audio-card,name = "verdin-nau8822";
+ simple-audio-card,routing =
+ "Headphones", "LHP",
+ "Headphones", "RHP",
+ "Speaker", "LSPK",
+ "Speaker", "RSPK",
+ "Line Out", "AUXOUT1",
+ "Line Out", "AUXOUT2",
+ "LAUX", "Line In",
+ "RAUX", "Line In",
+ "LMICP", "Mic In",
+ "RMICP", "Mic In";
+ simple-audio-card,widgets =
+ "Headphones", "Headphones",
+ "Line Out", "Line Out",
+ "Speaker", "Speaker",
+ "Microphone", "Mic In",
+ "Line", "Line In";
+
+ codec_dai: simple-audio-card,codec {
+ clocks = <&audio_refclk1>;
+ sound-dai = <&nau8822_1a>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp0>;
+ };
+ };
+};
+
/* Verdin ETHs */
&cpsw3g {
pinctrl-names = "default";
@@ -65,6 +101,15 @@
&main_i2c1 {
status = "okay";
+ /* Audio Codec */
+ nau8822_1a: audio-codec@1a {
+ compatible = "nuvoton,nau8822";
+ reg = <0x1a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2s1_mclk>;
+ #sound-dai-cells = <0>;
+ };
+
/* IO Expander */
gpio_expander_21: gpio@21 {
compatible = "nxp,pcal6416";
@@ -144,6 +189,11 @@
status = "okay";
};
+/* Verdin CAN_2 */
+&mcu_mcan0 {
+ status = "okay";
+};
+
/* Verdin UART_4 */
&mcu_uart0 {
status = "okay";
diff --git a/arch/arm/dts/k3-am62-verdin.dtsi b/arch/arm/dts/k3-am62-verdin.dtsi
index 57dd061..40992e7 100644
--- a/arch/arm/dts/k3-am62-verdin.dtsi
+++ b/arch/arm/dts/k3-am62-verdin.dtsi
@@ -19,6 +19,8 @@
};
aliases {
+ can0 = &main_mcan0;
+ can1 = &mcu_mcan0;
ethernet0 = &cpsw_port1;
ethernet1 = &cpsw_port2;
i2c0 = &main_i2c0;
@@ -732,6 +734,14 @@
>;
};
+ /* Verdin CAN_2 */
+ pinctrl_mcu_mcan0: mcu-mcan0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_MCU_IOPAD(0x0038, PIN_INPUT, 0) /* (B3) MCU_MCAN0_RX */ /* SODIMM 26 */
+ AM62X_MCU_IOPAD(0x0034, PIN_OUTPUT, 0) /* (D6) MCU_MCAN0_TX */ /* SODIMM 24 */
+ >;
+ };
+
/* Verdin UART_4 - Reserved to Cortex-M4 */
pinctrl_mcu_uart0: mcu-uart0-default-pins {
pinctrl-single,pins = <
@@ -758,6 +768,11 @@
};
};
+/* VERDIN I2S_1_MCLK */
+&audio_refclk1 {
+ assigned-clock-rates = <25000000>;
+};
+
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii1>;
@@ -800,6 +815,26 @@
};
};
+&dss {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_parallel_rgb>;
+ status = "disabled";
+};
+
+&dss_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* VP2: DPI Output */
+ port@1 {
+ reg = <1>;
+
+ dpi_out: endpoint {
+ remote-endpoint = <&rgb_in>;
+ };
+ };
+};
+
/* Verdin PWM_1, PWM_2 */
&epwm0 {
pinctrl-names = "default";
@@ -1036,6 +1071,7 @@
rgb_in: endpoint {
data-lines = <18>;
+ remote-endpoint = <&dpi_out>;
};
};
@@ -1238,8 +1274,6 @@
status = "disabled";
};
-/* Verdin CAN_2 - Reserved to Cortex-M4 */
-
/* Verdin SPI_1 */
&main_spi1 {
pinctrl-names = "default";
@@ -1333,6 +1367,13 @@
"";
};
+/* Verdin CAN_2 */
+&mcu_mcan0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mcu_mcan0>;
+ status = "disabled";
+};
+
/* Verdin UART_4 - Cortex-M4 UART */
&mcu_uart0 {
pinctrl-names = "default";
diff --git a/arch/arm/dts/k3-am62.dtsi b/arch/arm/dts/k3-am62.dtsi
index 5e72c44..11f14ee 100644
--- a/arch/arm/dts/k3-am62.dtsi
+++ b/arch/arm/dts/k3-am62.dtsi
@@ -102,6 +102,14 @@
};
};
+ dss_vp1_clk: clock-divider-oldi {
+ compatible = "fixed-factor-clock";
+ clocks = <&k3_clks 186 0>;
+ #clock-cells = <0>;
+ clock-div = <7>;
+ clock-mult = <1>;
+ };
+
#include "k3-am62-thermal.dtsi"
};
diff --git a/arch/arm/dts/k3-am625-beagleplay-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am625-beagleplay-ddr4-1600MTs.dtsi
new file mode 100644
index 0000000..3d7a41c
--- /dev/null
+++ b/arch/arm/dts/k3-am625-beagleplay-ddr4-1600MTs.dtsi
@@ -0,0 +1,2195 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * https://beagleboard.org/play
+ *
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
+ *
+ * This file was generated with the
+ * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.06
+ * Thu Feb 09 2023 11:57:18 GMT-0600 (Central Standard Time)
+ * DDR Part number: K4AAG165WA-BCWE K4A4G165WF-BCTD
+ * DDR Type: DDR4
+ * Frequency = 800MHz (1600MTs)
+ * Density: 16Gb
+ * Number of Ranks: 1
+ */
+
+#define DDRSS_PLL_FHS_CNT 6
+#define DDRSS_PLL_FREQUENCY_1 400000000
+#define DDRSS_PLL_FREQUENCY_2 400000000
+
+#define DDRSS_CTL_0_DATA 0x00000A00
+#define DDRSS_CTL_1_DATA 0x00000000
+#define DDRSS_CTL_2_DATA 0x00000000
+#define DDRSS_CTL_3_DATA 0x00000000
+#define DDRSS_CTL_4_DATA 0x00000000
+#define DDRSS_CTL_5_DATA 0x00000000
+#define DDRSS_CTL_6_DATA 0x00000000
+#define DDRSS_CTL_7_DATA 0x000890B8
+#define DDRSS_CTL_8_DATA 0x00000000
+#define DDRSS_CTL_9_DATA 0x00000000
+#define DDRSS_CTL_10_DATA 0x00000000
+#define DDRSS_CTL_11_DATA 0x000890B8
+#define DDRSS_CTL_12_DATA 0x00000000
+#define DDRSS_CTL_13_DATA 0x00000000
+#define DDRSS_CTL_14_DATA 0x00000000
+#define DDRSS_CTL_15_DATA 0x000890B8
+#define DDRSS_CTL_16_DATA 0x00000000
+#define DDRSS_CTL_17_DATA 0x00000000
+#define DDRSS_CTL_18_DATA 0x00000000
+#define DDRSS_CTL_19_DATA 0x01010100
+#define DDRSS_CTL_20_DATA 0x01000100
+#define DDRSS_CTL_21_DATA 0x01000110
+#define DDRSS_CTL_22_DATA 0x02010002
+#define DDRSS_CTL_23_DATA 0x00027100
+#define DDRSS_CTL_24_DATA 0x00061A80
+#define DDRSS_CTL_25_DATA 0x04000400
+#define DDRSS_CTL_26_DATA 0x00000400
+#define DDRSS_CTL_27_DATA 0x00000000
+#define DDRSS_CTL_28_DATA 0x00000000
+#define DDRSS_CTL_29_DATA 0x00000000
+#define DDRSS_CTL_30_DATA 0x00000000
+#define DDRSS_CTL_31_DATA 0x00000000
+#define DDRSS_CTL_32_DATA 0x00000000
+#define DDRSS_CTL_33_DATA 0x00000000
+#define DDRSS_CTL_34_DATA 0x00000000
+#define DDRSS_CTL_35_DATA 0x00000000
+#define DDRSS_CTL_36_DATA 0x00000000
+#define DDRSS_CTL_37_DATA 0x00000000
+#define DDRSS_CTL_38_DATA 0x0400091C
+#define DDRSS_CTL_39_DATA 0x1C1C1C1C
+#define DDRSS_CTL_40_DATA 0x0400091C
+#define DDRSS_CTL_41_DATA 0x1C1C1C1C
+#define DDRSS_CTL_42_DATA 0x0400091C
+#define DDRSS_CTL_43_DATA 0x1C1C1C1C
+#define DDRSS_CTL_44_DATA 0x05050404
+#define DDRSS_CTL_45_DATA 0x00002706
+#define DDRSS_CTL_46_DATA 0x0602001D
+#define DDRSS_CTL_47_DATA 0x05001D0B
+#define DDRSS_CTL_48_DATA 0x00270605
+#define DDRSS_CTL_49_DATA 0x0602001D
+#define DDRSS_CTL_50_DATA 0x05001D0B
+#define DDRSS_CTL_51_DATA 0x00270605
+#define DDRSS_CTL_52_DATA 0x0602001D
+#define DDRSS_CTL_53_DATA 0x07001D0B
+#define DDRSS_CTL_54_DATA 0x00180807
+#define DDRSS_CTL_55_DATA 0x0400DB60
+#define DDRSS_CTL_56_DATA 0x07070009
+#define DDRSS_CTL_57_DATA 0x00001808
+#define DDRSS_CTL_58_DATA 0x0400DB60
+#define DDRSS_CTL_59_DATA 0x07070009
+#define DDRSS_CTL_60_DATA 0x00001808
+#define DDRSS_CTL_61_DATA 0x0400DB60
+#define DDRSS_CTL_62_DATA 0x03000009
+#define DDRSS_CTL_63_DATA 0x0D0C0002
+#define DDRSS_CTL_64_DATA 0x0D0C0D0C
+#define DDRSS_CTL_65_DATA 0x01010000
+#define DDRSS_CTL_66_DATA 0x03191919
+#define DDRSS_CTL_67_DATA 0x0B0B0B0B
+#define DDRSS_CTL_68_DATA 0x00000B0B
+#define DDRSS_CTL_69_DATA 0x00000101
+#define DDRSS_CTL_70_DATA 0x00000000
+#define DDRSS_CTL_71_DATA 0x01000000
+#define DDRSS_CTL_72_DATA 0x01180803
+#define DDRSS_CTL_73_DATA 0x00001860
+#define DDRSS_CTL_74_DATA 0x00000118
+#define DDRSS_CTL_75_DATA 0x00001860
+#define DDRSS_CTL_76_DATA 0x00000118
+#define DDRSS_CTL_77_DATA 0x00001860
+#define DDRSS_CTL_78_DATA 0x00000005
+#define DDRSS_CTL_79_DATA 0x00000000
+#define DDRSS_CTL_80_DATA 0x00000000
+#define DDRSS_CTL_81_DATA 0x00000000
+#define DDRSS_CTL_82_DATA 0x00000000
+#define DDRSS_CTL_83_DATA 0x00000000
+#define DDRSS_CTL_84_DATA 0x00000000
+#define DDRSS_CTL_85_DATA 0x00000000
+#define DDRSS_CTL_86_DATA 0x00000000
+#define DDRSS_CTL_87_DATA 0x00090009
+#define DDRSS_CTL_88_DATA 0x00000009
+#define DDRSS_CTL_89_DATA 0x00000000
+#define DDRSS_CTL_90_DATA 0x00000000
+#define DDRSS_CTL_91_DATA 0x00000000
+#define DDRSS_CTL_92_DATA 0x00000000
+#define DDRSS_CTL_93_DATA 0x00000000
+#define DDRSS_CTL_94_DATA 0x00010001
+#define DDRSS_CTL_95_DATA 0x00040001
+#define DDRSS_CTL_96_DATA 0x04000120
+#define DDRSS_CTL_97_DATA 0x04000120
+#define DDRSS_CTL_98_DATA 0x01200120
+#define DDRSS_CTL_99_DATA 0x01200120
+#define DDRSS_CTL_100_DATA 0x00000000
+#define DDRSS_CTL_101_DATA 0x00000000
+#define DDRSS_CTL_102_DATA 0x00000000
+#define DDRSS_CTL_103_DATA 0x00000000
+#define DDRSS_CTL_104_DATA 0x00000000
+#define DDRSS_CTL_105_DATA 0x00000000
+#define DDRSS_CTL_106_DATA 0x03010000
+#define DDRSS_CTL_107_DATA 0x00010000
+#define DDRSS_CTL_108_DATA 0x00000000
+#define DDRSS_CTL_109_DATA 0x01000000
+#define DDRSS_CTL_110_DATA 0x80104002
+#define DDRSS_CTL_111_DATA 0x00040003
+#define DDRSS_CTL_112_DATA 0x00040005
+#define DDRSS_CTL_113_DATA 0x00030000
+#define DDRSS_CTL_114_DATA 0x00050004
+#define DDRSS_CTL_115_DATA 0x00000004
+#define DDRSS_CTL_116_DATA 0x00040003
+#define DDRSS_CTL_117_DATA 0x00040005
+#define DDRSS_CTL_118_DATA 0x00000000
+#define DDRSS_CTL_119_DATA 0x00061800
+#define DDRSS_CTL_120_DATA 0x00061800
+#define DDRSS_CTL_121_DATA 0x00061800
+#define DDRSS_CTL_122_DATA 0x00061800
+#define DDRSS_CTL_123_DATA 0x00061800
+#define DDRSS_CTL_124_DATA 0x00000000
+#define DDRSS_CTL_125_DATA 0x0000AAA0
+#define DDRSS_CTL_126_DATA 0x00061800
+#define DDRSS_CTL_127_DATA 0x00061800
+#define DDRSS_CTL_128_DATA 0x00061800
+#define DDRSS_CTL_129_DATA 0x00061800
+#define DDRSS_CTL_130_DATA 0x00061800
+#define DDRSS_CTL_131_DATA 0x00000000
+#define DDRSS_CTL_132_DATA 0x0000AAA0
+#define DDRSS_CTL_133_DATA 0x00061800
+#define DDRSS_CTL_134_DATA 0x00061800
+#define DDRSS_CTL_135_DATA 0x00061800
+#define DDRSS_CTL_136_DATA 0x00061800
+#define DDRSS_CTL_137_DATA 0x00061800
+#define DDRSS_CTL_138_DATA 0x00000000
+#define DDRSS_CTL_139_DATA 0x0000AAA0
+#define DDRSS_CTL_140_DATA 0x00000000
+#define DDRSS_CTL_141_DATA 0x00000000
+#define DDRSS_CTL_142_DATA 0x00000000
+#define DDRSS_CTL_143_DATA 0x00000000
+#define DDRSS_CTL_144_DATA 0x00000000
+#define DDRSS_CTL_145_DATA 0x00000000
+#define DDRSS_CTL_146_DATA 0x00000000
+#define DDRSS_CTL_147_DATA 0x00000000
+#define DDRSS_CTL_148_DATA 0x00000000
+#define DDRSS_CTL_149_DATA 0x00000000
+#define DDRSS_CTL_150_DATA 0x00000000
+#define DDRSS_CTL_151_DATA 0x00000000
+#define DDRSS_CTL_152_DATA 0x00000000
+#define DDRSS_CTL_153_DATA 0x00000000
+#define DDRSS_CTL_154_DATA 0x00000000
+#define DDRSS_CTL_155_DATA 0x00000000
+#define DDRSS_CTL_156_DATA 0x080C0000
+#define DDRSS_CTL_157_DATA 0x080C080C
+#define DDRSS_CTL_158_DATA 0x08000000
+#define DDRSS_CTL_159_DATA 0x00000808
+#define DDRSS_CTL_160_DATA 0x000E0000
+#define DDRSS_CTL_161_DATA 0x00080808
+#define DDRSS_CTL_162_DATA 0x0E000000
+#define DDRSS_CTL_163_DATA 0x08080800
+#define DDRSS_CTL_164_DATA 0x00000000
+#define DDRSS_CTL_165_DATA 0x0000080E
+#define DDRSS_CTL_166_DATA 0x00040003
+#define DDRSS_CTL_167_DATA 0x00000007
+#define DDRSS_CTL_168_DATA 0x00000000
+#define DDRSS_CTL_169_DATA 0x00000000
+#define DDRSS_CTL_170_DATA 0x00000000
+#define DDRSS_CTL_171_DATA 0x00000000
+#define DDRSS_CTL_172_DATA 0x00000000
+#define DDRSS_CTL_173_DATA 0x00000000
+#define DDRSS_CTL_174_DATA 0x01000000
+#define DDRSS_CTL_175_DATA 0x00000000
+#define DDRSS_CTL_176_DATA 0x00001500
+#define DDRSS_CTL_177_DATA 0x0000100E
+#define DDRSS_CTL_178_DATA 0x00000000
+#define DDRSS_CTL_179_DATA 0x00000000
+#define DDRSS_CTL_180_DATA 0x00000001
+#define DDRSS_CTL_181_DATA 0x00000002
+#define DDRSS_CTL_182_DATA 0x00000C00
+#define DDRSS_CTL_183_DATA 0x00001000
+#define DDRSS_CTL_184_DATA 0x00000C00
+#define DDRSS_CTL_185_DATA 0x00001000
+#define DDRSS_CTL_186_DATA 0x00000C00
+#define DDRSS_CTL_187_DATA 0x00001000
+#define DDRSS_CTL_188_DATA 0x00000000
+#define DDRSS_CTL_189_DATA 0x00000000
+#define DDRSS_CTL_190_DATA 0x00000000
+#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_192_DATA 0x00000000
+#define DDRSS_CTL_193_DATA 0x00000000
+#define DDRSS_CTL_194_DATA 0x00000000
+#define DDRSS_CTL_195_DATA 0x00000000
+#define DDRSS_CTL_196_DATA 0x00000000
+#define DDRSS_CTL_197_DATA 0x00000000
+#define DDRSS_CTL_198_DATA 0x00000000
+#define DDRSS_CTL_199_DATA 0x00000000
+#define DDRSS_CTL_200_DATA 0x00000000
+#define DDRSS_CTL_201_DATA 0x00000000
+#define DDRSS_CTL_202_DATA 0x00000000
+#define DDRSS_CTL_203_DATA 0x00000000
+#define DDRSS_CTL_204_DATA 0x00042400
+#define DDRSS_CTL_205_DATA 0x00000301
+#define DDRSS_CTL_206_DATA 0x00000000
+#define DDRSS_CTL_207_DATA 0x00000424
+#define DDRSS_CTL_208_DATA 0x00000301
+#define DDRSS_CTL_209_DATA 0x00000000
+#define DDRSS_CTL_210_DATA 0x00000424
+#define DDRSS_CTL_211_DATA 0x00000301
+#define DDRSS_CTL_212_DATA 0x00000000
+#define DDRSS_CTL_213_DATA 0x00000424
+#define DDRSS_CTL_214_DATA 0x00000301
+#define DDRSS_CTL_215_DATA 0x00000000
+#define DDRSS_CTL_216_DATA 0x00000424
+#define DDRSS_CTL_217_DATA 0x00000301
+#define DDRSS_CTL_218_DATA 0x00000000
+#define DDRSS_CTL_219_DATA 0x00000424
+#define DDRSS_CTL_220_DATA 0x00000301
+#define DDRSS_CTL_221_DATA 0x00000000
+#define DDRSS_CTL_222_DATA 0x00000000
+#define DDRSS_CTL_223_DATA 0x00000000
+#define DDRSS_CTL_224_DATA 0x00000000
+#define DDRSS_CTL_225_DATA 0x00000000
+#define DDRSS_CTL_226_DATA 0x00000000
+#define DDRSS_CTL_227_DATA 0x00000000
+#define DDRSS_CTL_228_DATA 0x00000000
+#define DDRSS_CTL_229_DATA 0x00000000
+#define DDRSS_CTL_230_DATA 0x00000000
+#define DDRSS_CTL_231_DATA 0x00000000
+#define DDRSS_CTL_232_DATA 0x00000000
+#define DDRSS_CTL_233_DATA 0x00000000
+#define DDRSS_CTL_234_DATA 0x00000000
+#define DDRSS_CTL_235_DATA 0x00000000
+#define DDRSS_CTL_236_DATA 0x00001401
+#define DDRSS_CTL_237_DATA 0x00001401
+#define DDRSS_CTL_238_DATA 0x00001401
+#define DDRSS_CTL_239_DATA 0x00001401
+#define DDRSS_CTL_240_DATA 0x00001401
+#define DDRSS_CTL_241_DATA 0x00001401
+#define DDRSS_CTL_242_DATA 0x00000493
+#define DDRSS_CTL_243_DATA 0x00000493
+#define DDRSS_CTL_244_DATA 0x00000493
+#define DDRSS_CTL_245_DATA 0x00000493
+#define DDRSS_CTL_246_DATA 0x00000493
+#define DDRSS_CTL_247_DATA 0x00000493
+#define DDRSS_CTL_248_DATA 0x00000000
+#define DDRSS_CTL_249_DATA 0x00000000
+#define DDRSS_CTL_250_DATA 0x00000000
+#define DDRSS_CTL_251_DATA 0x00000000
+#define DDRSS_CTL_252_DATA 0x00000000
+#define DDRSS_CTL_253_DATA 0x00000000
+#define DDRSS_CTL_254_DATA 0x00000000
+#define DDRSS_CTL_255_DATA 0x00000000
+#define DDRSS_CTL_256_DATA 0x00000000
+#define DDRSS_CTL_257_DATA 0x00000000
+#define DDRSS_CTL_258_DATA 0x00000000
+#define DDRSS_CTL_259_DATA 0x00000000
+#define DDRSS_CTL_260_DATA 0x00000000
+#define DDRSS_CTL_261_DATA 0x00000000
+#define DDRSS_CTL_262_DATA 0x00000000
+#define DDRSS_CTL_263_DATA 0x00000000
+#define DDRSS_CTL_264_DATA 0x00000000
+#define DDRSS_CTL_265_DATA 0x00000000
+#define DDRSS_CTL_266_DATA 0x00000000
+#define DDRSS_CTL_267_DATA 0x00000000
+#define DDRSS_CTL_268_DATA 0x00000000
+#define DDRSS_CTL_269_DATA 0x00000000
+#define DDRSS_CTL_270_DATA 0x00000000
+#define DDRSS_CTL_271_DATA 0x00000000
+#define DDRSS_CTL_272_DATA 0x00000000
+#define DDRSS_CTL_273_DATA 0x00000000
+#define DDRSS_CTL_274_DATA 0x00000000
+#define DDRSS_CTL_275_DATA 0x00000000
+#define DDRSS_CTL_276_DATA 0x00000000
+#define DDRSS_CTL_277_DATA 0x00010000
+#define DDRSS_CTL_278_DATA 0x00000000
+#define DDRSS_CTL_279_DATA 0x00000000
+#define DDRSS_CTL_280_DATA 0x00000000
+#define DDRSS_CTL_281_DATA 0x00000101
+#define DDRSS_CTL_282_DATA 0x00000000
+#define DDRSS_CTL_283_DATA 0x00000000
+#define DDRSS_CTL_284_DATA 0x00000000
+#define DDRSS_CTL_285_DATA 0x00000000
+#define DDRSS_CTL_286_DATA 0x00000000
+#define DDRSS_CTL_287_DATA 0x00000000
+#define DDRSS_CTL_288_DATA 0x00000000
+#define DDRSS_CTL_289_DATA 0x00000000
+#define DDRSS_CTL_290_DATA 0x0C181511
+#define DDRSS_CTL_291_DATA 0x00000304
+#define DDRSS_CTL_292_DATA 0x00000000
+#define DDRSS_CTL_293_DATA 0x00000000
+#define DDRSS_CTL_294_DATA 0x00000000
+#define DDRSS_CTL_295_DATA 0x00000000
+#define DDRSS_CTL_296_DATA 0x00000000
+#define DDRSS_CTL_297_DATA 0x00000000
+#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_299_DATA 0x00000000
+#define DDRSS_CTL_300_DATA 0x00000000
+#define DDRSS_CTL_301_DATA 0x00000000
+#define DDRSS_CTL_302_DATA 0x00000000
+#define DDRSS_CTL_303_DATA 0x00000000
+#define DDRSS_CTL_304_DATA 0x00000000
+#define DDRSS_CTL_305_DATA 0x00040000
+#define DDRSS_CTL_306_DATA 0x00800200
+#define DDRSS_CTL_307_DATA 0x00000000
+#define DDRSS_CTL_308_DATA 0x02000400
+#define DDRSS_CTL_309_DATA 0x00000080
+#define DDRSS_CTL_310_DATA 0x00040000
+#define DDRSS_CTL_311_DATA 0x00800200
+#define DDRSS_CTL_312_DATA 0x00000000
+#define DDRSS_CTL_313_DATA 0x00000000
+#define DDRSS_CTL_314_DATA 0x00000000
+#define DDRSS_CTL_315_DATA 0x00000100
+#define DDRSS_CTL_316_DATA 0x01010000
+#define DDRSS_CTL_317_DATA 0x00000000
+#define DDRSS_CTL_318_DATA 0x3FFF0000
+#define DDRSS_CTL_319_DATA 0x000FFF00
+#define DDRSS_CTL_320_DATA 0xFFFFFFFF
+#define DDRSS_CTL_321_DATA 0x00FFFF00
+#define DDRSS_CTL_322_DATA 0x0A000000
+#define DDRSS_CTL_323_DATA 0x0001FFFF
+#define DDRSS_CTL_324_DATA 0x01010101
+#define DDRSS_CTL_325_DATA 0x01010101
+#define DDRSS_CTL_326_DATA 0x00000118
+#define DDRSS_CTL_327_DATA 0x00000C01
+#define DDRSS_CTL_328_DATA 0x00000000
+#define DDRSS_CTL_329_DATA 0x00000000
+#define DDRSS_CTL_330_DATA 0x00000000
+#define DDRSS_CTL_331_DATA 0x01000000
+#define DDRSS_CTL_332_DATA 0x00000100
+#define DDRSS_CTL_333_DATA 0x00010000
+#define DDRSS_CTL_334_DATA 0x00000000
+#define DDRSS_CTL_335_DATA 0x00000000
+#define DDRSS_CTL_336_DATA 0x00000000
+#define DDRSS_CTL_337_DATA 0x00000000
+#define DDRSS_CTL_338_DATA 0x00000000
+#define DDRSS_CTL_339_DATA 0x00000000
+#define DDRSS_CTL_340_DATA 0x00000000
+#define DDRSS_CTL_341_DATA 0x00000000
+#define DDRSS_CTL_342_DATA 0x00000000
+#define DDRSS_CTL_343_DATA 0x00000000
+#define DDRSS_CTL_344_DATA 0x00000000
+#define DDRSS_CTL_345_DATA 0x00000000
+#define DDRSS_CTL_346_DATA 0x00000000
+#define DDRSS_CTL_347_DATA 0x00000000
+#define DDRSS_CTL_348_DATA 0x00000000
+#define DDRSS_CTL_349_DATA 0x00000000
+#define DDRSS_CTL_350_DATA 0x00000000
+#define DDRSS_CTL_351_DATA 0x00000000
+#define DDRSS_CTL_352_DATA 0x00000000
+#define DDRSS_CTL_353_DATA 0x00000000
+#define DDRSS_CTL_354_DATA 0x00000000
+#define DDRSS_CTL_355_DATA 0x00000000
+#define DDRSS_CTL_356_DATA 0x00000000
+#define DDRSS_CTL_357_DATA 0x00000000
+#define DDRSS_CTL_358_DATA 0x00000000
+#define DDRSS_CTL_359_DATA 0x00000000
+#define DDRSS_CTL_360_DATA 0x00000000
+#define DDRSS_CTL_361_DATA 0x00000000
+#define DDRSS_CTL_362_DATA 0x00000000
+#define DDRSS_CTL_363_DATA 0x00000000
+#define DDRSS_CTL_364_DATA 0x00000000
+#define DDRSS_CTL_365_DATA 0x00000000
+#define DDRSS_CTL_366_DATA 0x00000000
+#define DDRSS_CTL_367_DATA 0x00000000
+#define DDRSS_CTL_368_DATA 0x00000000
+#define DDRSS_CTL_369_DATA 0x00000000
+#define DDRSS_CTL_370_DATA 0x0C000000
+#define DDRSS_CTL_371_DATA 0x060C0606
+#define DDRSS_CTL_372_DATA 0x06060C06
+#define DDRSS_CTL_373_DATA 0x00010101
+#define DDRSS_CTL_374_DATA 0x02000000
+#define DDRSS_CTL_375_DATA 0x05020101
+#define DDRSS_CTL_376_DATA 0x00000505
+#define DDRSS_CTL_377_DATA 0x02020200
+#define DDRSS_CTL_378_DATA 0x02020202
+#define DDRSS_CTL_379_DATA 0x02020202
+#define DDRSS_CTL_380_DATA 0x02020202
+#define DDRSS_CTL_381_DATA 0x00000000
+#define DDRSS_CTL_382_DATA 0x00000000
+#define DDRSS_CTL_383_DATA 0x04000100
+#define DDRSS_CTL_384_DATA 0x1E000004
+#define DDRSS_CTL_385_DATA 0x000030C0
+#define DDRSS_CTL_386_DATA 0x00000200
+#define DDRSS_CTL_387_DATA 0x00000200
+#define DDRSS_CTL_388_DATA 0x00000200
+#define DDRSS_CTL_389_DATA 0x00000200
+#define DDRSS_CTL_390_DATA 0x0000DB60
+#define DDRSS_CTL_391_DATA 0x0001E780
+#define DDRSS_CTL_392_DATA 0x0C0D0302
+#define DDRSS_CTL_393_DATA 0x001E090A
+#define DDRSS_CTL_394_DATA 0x000030C0
+#define DDRSS_CTL_395_DATA 0x00000200
+#define DDRSS_CTL_396_DATA 0x00000200
+#define DDRSS_CTL_397_DATA 0x00000200
+#define DDRSS_CTL_398_DATA 0x00000200
+#define DDRSS_CTL_399_DATA 0x0000DB60
+#define DDRSS_CTL_400_DATA 0x0001E780
+#define DDRSS_CTL_401_DATA 0x0C0D0302
+#define DDRSS_CTL_402_DATA 0x001E090A
+#define DDRSS_CTL_403_DATA 0x000030C0
+#define DDRSS_CTL_404_DATA 0x00000200
+#define DDRSS_CTL_405_DATA 0x00000200
+#define DDRSS_CTL_406_DATA 0x00000200
+#define DDRSS_CTL_407_DATA 0x00000200
+#define DDRSS_CTL_408_DATA 0x0000DB60
+#define DDRSS_CTL_409_DATA 0x0001E780
+#define DDRSS_CTL_410_DATA 0x0C0D0302
+#define DDRSS_CTL_411_DATA 0x0000090A
+#define DDRSS_CTL_412_DATA 0x00000000
+#define DDRSS_CTL_413_DATA 0x0302000A
+#define DDRSS_CTL_414_DATA 0x01000500
+#define DDRSS_CTL_415_DATA 0x01010001
+#define DDRSS_CTL_416_DATA 0x00010001
+#define DDRSS_CTL_417_DATA 0x01010001
+#define DDRSS_CTL_418_DATA 0x02010000
+#define DDRSS_CTL_419_DATA 0x00000200
+#define DDRSS_CTL_420_DATA 0x02000201
+#define DDRSS_CTL_421_DATA 0x00000000
+#define DDRSS_CTL_422_DATA 0x00202020
+#define DDRSS_PI_0_DATA 0x00000A00
+#define DDRSS_PI_1_DATA 0x00000000
+#define DDRSS_PI_2_DATA 0x00000000
+#define DDRSS_PI_3_DATA 0x01000000
+#define DDRSS_PI_4_DATA 0x00000001
+#define DDRSS_PI_5_DATA 0x00010064
+#define DDRSS_PI_6_DATA 0x00000000
+#define DDRSS_PI_7_DATA 0x00000000
+#define DDRSS_PI_8_DATA 0x00000000
+#define DDRSS_PI_9_DATA 0x00000000
+#define DDRSS_PI_10_DATA 0x00000000
+#define DDRSS_PI_11_DATA 0x00000000
+#define DDRSS_PI_12_DATA 0x00000000
+#define DDRSS_PI_13_DATA 0x00010001
+#define DDRSS_PI_14_DATA 0x00000000
+#define DDRSS_PI_15_DATA 0x00010001
+#define DDRSS_PI_16_DATA 0x00000005
+#define DDRSS_PI_17_DATA 0x00000000
+#define DDRSS_PI_18_DATA 0x00000000
+#define DDRSS_PI_19_DATA 0x00000000
+#define DDRSS_PI_20_DATA 0x00000000
+#define DDRSS_PI_21_DATA 0x00000000
+#define DDRSS_PI_22_DATA 0x00000000
+#define DDRSS_PI_23_DATA 0x00000000
+#define DDRSS_PI_24_DATA 0x280D0001
+#define DDRSS_PI_25_DATA 0x00000000
+#define DDRSS_PI_26_DATA 0x00010000
+#define DDRSS_PI_27_DATA 0x00003200
+#define DDRSS_PI_28_DATA 0x00000000
+#define DDRSS_PI_29_DATA 0x00000000
+#define DDRSS_PI_30_DATA 0x00060602
+#define DDRSS_PI_31_DATA 0x00000000
+#define DDRSS_PI_32_DATA 0x00000000
+#define DDRSS_PI_33_DATA 0x00000000
+#define DDRSS_PI_34_DATA 0x00000001
+#define DDRSS_PI_35_DATA 0x00000055
+#define DDRSS_PI_36_DATA 0x000000AA
+#define DDRSS_PI_37_DATA 0x000000AD
+#define DDRSS_PI_38_DATA 0x00000052
+#define DDRSS_PI_39_DATA 0x0000006A
+#define DDRSS_PI_40_DATA 0x00000095
+#define DDRSS_PI_41_DATA 0x00000095
+#define DDRSS_PI_42_DATA 0x000000AD
+#define DDRSS_PI_43_DATA 0x00000000
+#define DDRSS_PI_44_DATA 0x00000000
+#define DDRSS_PI_45_DATA 0x00010100
+#define DDRSS_PI_46_DATA 0x00000014
+#define DDRSS_PI_47_DATA 0x000007D0
+#define DDRSS_PI_48_DATA 0x00000300
+#define DDRSS_PI_49_DATA 0x00000000
+#define DDRSS_PI_50_DATA 0x00000000
+#define DDRSS_PI_51_DATA 0x01000000
+#define DDRSS_PI_52_DATA 0x00010101
+#define DDRSS_PI_53_DATA 0x01000000
+#define DDRSS_PI_54_DATA 0x00000000
+#define DDRSS_PI_55_DATA 0x00010000
+#define DDRSS_PI_56_DATA 0x00000000
+#define DDRSS_PI_57_DATA 0x00000000
+#define DDRSS_PI_58_DATA 0x00000000
+#define DDRSS_PI_59_DATA 0x00000000
+#define DDRSS_PI_60_DATA 0x00001400
+#define DDRSS_PI_61_DATA 0x00000000
+#define DDRSS_PI_62_DATA 0x01000000
+#define DDRSS_PI_63_DATA 0x00000404
+#define DDRSS_PI_64_DATA 0x00000001
+#define DDRSS_PI_65_DATA 0x0001010E
+#define DDRSS_PI_66_DATA 0x02040100
+#define DDRSS_PI_67_DATA 0x00010000
+#define DDRSS_PI_68_DATA 0x00000034
+#define DDRSS_PI_69_DATA 0x00000000
+#define DDRSS_PI_70_DATA 0x00000000
+#define DDRSS_PI_71_DATA 0x00000000
+#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_73_DATA 0x00000000
+#define DDRSS_PI_74_DATA 0x00000000
+#define DDRSS_PI_75_DATA 0x00000005
+#define DDRSS_PI_76_DATA 0x01000000
+#define DDRSS_PI_77_DATA 0x04000100
+#define DDRSS_PI_78_DATA 0x00020000
+#define DDRSS_PI_79_DATA 0x00010002
+#define DDRSS_PI_80_DATA 0x00000001
+#define DDRSS_PI_81_DATA 0x00020001
+#define DDRSS_PI_82_DATA 0x00020002
+#define DDRSS_PI_83_DATA 0x00000000
+#define DDRSS_PI_84_DATA 0x00000000
+#define DDRSS_PI_85_DATA 0x00000000
+#define DDRSS_PI_86_DATA 0x00000000
+#define DDRSS_PI_87_DATA 0x00000000
+#define DDRSS_PI_88_DATA 0x00000000
+#define DDRSS_PI_89_DATA 0x00000000
+#define DDRSS_PI_90_DATA 0x00000000
+#define DDRSS_PI_91_DATA 0x00000300
+#define DDRSS_PI_92_DATA 0x0A090B0C
+#define DDRSS_PI_93_DATA 0x04060708
+#define DDRSS_PI_94_DATA 0x01000005
+#define DDRSS_PI_95_DATA 0x00000800
+#define DDRSS_PI_96_DATA 0x00000000
+#define DDRSS_PI_97_DATA 0x00010008
+#define DDRSS_PI_98_DATA 0x00000000
+#define DDRSS_PI_99_DATA 0x0000AA00
+#define DDRSS_PI_100_DATA 0x00000000
+#define DDRSS_PI_101_DATA 0x00010000
+#define DDRSS_PI_102_DATA 0x00000000
+#define DDRSS_PI_103_DATA 0x00000000
+#define DDRSS_PI_104_DATA 0x00000000
+#define DDRSS_PI_105_DATA 0x00000000
+#define DDRSS_PI_106_DATA 0x00000000
+#define DDRSS_PI_107_DATA 0x00000000
+#define DDRSS_PI_108_DATA 0x00000000
+#define DDRSS_PI_109_DATA 0x00000000
+#define DDRSS_PI_110_DATA 0x00000000
+#define DDRSS_PI_111_DATA 0x00000000
+#define DDRSS_PI_112_DATA 0x00000000
+#define DDRSS_PI_113_DATA 0x00000000
+#define DDRSS_PI_114_DATA 0x00000000
+#define DDRSS_PI_115_DATA 0x00000000
+#define DDRSS_PI_116_DATA 0x00000000
+#define DDRSS_PI_117_DATA 0x00000000
+#define DDRSS_PI_118_DATA 0x00000000
+#define DDRSS_PI_119_DATA 0x00000000
+#define DDRSS_PI_120_DATA 0x00000000
+#define DDRSS_PI_121_DATA 0x00000000
+#define DDRSS_PI_122_DATA 0x00000000
+#define DDRSS_PI_123_DATA 0x00000000
+#define DDRSS_PI_124_DATA 0x00000008
+#define DDRSS_PI_125_DATA 0x00000000
+#define DDRSS_PI_126_DATA 0x00000000
+#define DDRSS_PI_127_DATA 0x00000000
+#define DDRSS_PI_128_DATA 0x00000000
+#define DDRSS_PI_129_DATA 0x00000000
+#define DDRSS_PI_130_DATA 0x00000000
+#define DDRSS_PI_131_DATA 0x00000000
+#define DDRSS_PI_132_DATA 0x00000000
+#define DDRSS_PI_133_DATA 0x00010100
+#define DDRSS_PI_134_DATA 0x00000000
+#define DDRSS_PI_135_DATA 0x00000000
+#define DDRSS_PI_136_DATA 0x00027100
+#define DDRSS_PI_137_DATA 0x00061A80
+#define DDRSS_PI_138_DATA 0x00000100
+#define DDRSS_PI_139_DATA 0x00000000
+#define DDRSS_PI_140_DATA 0x00000000
+#define DDRSS_PI_141_DATA 0x00000000
+#define DDRSS_PI_142_DATA 0x00000000
+#define DDRSS_PI_143_DATA 0x00000000
+#define DDRSS_PI_144_DATA 0x01000000
+#define DDRSS_PI_145_DATA 0x00010003
+#define DDRSS_PI_146_DATA 0x02000101
+#define DDRSS_PI_147_DATA 0x01030001
+#define DDRSS_PI_148_DATA 0x00010400
+#define DDRSS_PI_149_DATA 0x06000105
+#define DDRSS_PI_150_DATA 0x01070001
+#define DDRSS_PI_151_DATA 0x00000000
+#define DDRSS_PI_152_DATA 0x00000000
+#define DDRSS_PI_153_DATA 0x00000000
+#define DDRSS_PI_154_DATA 0x00010000
+#define DDRSS_PI_155_DATA 0x00000000
+#define DDRSS_PI_156_DATA 0x00000000
+#define DDRSS_PI_157_DATA 0x00000000
+#define DDRSS_PI_158_DATA 0x00000000
+#define DDRSS_PI_159_DATA 0x00010000
+#define DDRSS_PI_160_DATA 0x00000004
+#define DDRSS_PI_161_DATA 0x00000000
+#define DDRSS_PI_162_DATA 0x00000000
+#define DDRSS_PI_163_DATA 0x00000000
+#define DDRSS_PI_164_DATA 0x00007800
+#define DDRSS_PI_165_DATA 0x00780078
+#define DDRSS_PI_166_DATA 0x00141414
+#define DDRSS_PI_167_DATA 0x0000003A
+#define DDRSS_PI_168_DATA 0x0000003A
+#define DDRSS_PI_169_DATA 0x0004003A
+#define DDRSS_PI_170_DATA 0x04000400
+#define DDRSS_PI_171_DATA 0xC8040009
+#define DDRSS_PI_172_DATA 0x0400091C
+#define DDRSS_PI_173_DATA 0x00091CC8
+#define DDRSS_PI_174_DATA 0x001CC804
+#define DDRSS_PI_175_DATA 0x00000118
+#define DDRSS_PI_176_DATA 0x00001860
+#define DDRSS_PI_177_DATA 0x00000118
+#define DDRSS_PI_178_DATA 0x00001860
+#define DDRSS_PI_179_DATA 0x00000118
+#define DDRSS_PI_180_DATA 0x04001860
+#define DDRSS_PI_181_DATA 0x01010404
+#define DDRSS_PI_182_DATA 0x00001901
+#define DDRSS_PI_183_DATA 0x00190019
+#define DDRSS_PI_184_DATA 0x010C010C
+#define DDRSS_PI_185_DATA 0x0000010C
+#define DDRSS_PI_186_DATA 0x00000000
+#define DDRSS_PI_187_DATA 0x05000000
+#define DDRSS_PI_188_DATA 0x01010505
+#define DDRSS_PI_189_DATA 0x01010101
+#define DDRSS_PI_190_DATA 0x00181818
+#define DDRSS_PI_191_DATA 0x00000000
+#define DDRSS_PI_192_DATA 0x00000000
+#define DDRSS_PI_193_DATA 0x0D000000
+#define DDRSS_PI_194_DATA 0x0A0A0D0D
+#define DDRSS_PI_195_DATA 0x0303030A
+#define DDRSS_PI_196_DATA 0x00000000
+#define DDRSS_PI_197_DATA 0x00000000
+#define DDRSS_PI_198_DATA 0x00000000
+#define DDRSS_PI_199_DATA 0x00000000
+#define DDRSS_PI_200_DATA 0x00000000
+#define DDRSS_PI_201_DATA 0x00000000
+#define DDRSS_PI_202_DATA 0x00000000
+#define DDRSS_PI_203_DATA 0x00000000
+#define DDRSS_PI_204_DATA 0x00000000
+#define DDRSS_PI_205_DATA 0x00000000
+#define DDRSS_PI_206_DATA 0x00000000
+#define DDRSS_PI_207_DATA 0x00000000
+#define DDRSS_PI_208_DATA 0x00000000
+#define DDRSS_PI_209_DATA 0x0D090000
+#define DDRSS_PI_210_DATA 0x0D09000D
+#define DDRSS_PI_211_DATA 0x0D09000D
+#define DDRSS_PI_212_DATA 0x0000000D
+#define DDRSS_PI_213_DATA 0x00000000
+#define DDRSS_PI_214_DATA 0x00000000
+#define DDRSS_PI_215_DATA 0x00000000
+#define DDRSS_PI_216_DATA 0x00000000
+#define DDRSS_PI_217_DATA 0x16000000
+#define DDRSS_PI_218_DATA 0x001600C8
+#define DDRSS_PI_219_DATA 0x001600C8
+#define DDRSS_PI_220_DATA 0x010100C8
+#define DDRSS_PI_221_DATA 0x00001B01
+#define DDRSS_PI_222_DATA 0x1F0F0053
+#define DDRSS_PI_223_DATA 0x05000001
+#define DDRSS_PI_224_DATA 0x001B0A0D
+#define DDRSS_PI_225_DATA 0x1F0F0053
+#define DDRSS_PI_226_DATA 0x05000001
+#define DDRSS_PI_227_DATA 0x001B0A0D
+#define DDRSS_PI_228_DATA 0x1F0F0053
+#define DDRSS_PI_229_DATA 0x05000001
+#define DDRSS_PI_230_DATA 0x00010A0D
+#define DDRSS_PI_231_DATA 0x0C0B0700
+#define DDRSS_PI_232_DATA 0x000D0605
+#define DDRSS_PI_233_DATA 0x0000C570
+#define DDRSS_PI_234_DATA 0x0000001D
+#define DDRSS_PI_235_DATA 0x180A0800
+#define DDRSS_PI_236_DATA 0x0B071C1C
+#define DDRSS_PI_237_DATA 0x0D06050C
+#define DDRSS_PI_238_DATA 0x0000C570
+#define DDRSS_PI_239_DATA 0x0000001D
+#define DDRSS_PI_240_DATA 0x180A0800
+#define DDRSS_PI_241_DATA 0x0B071C1C
+#define DDRSS_PI_242_DATA 0x0D06050C
+#define DDRSS_PI_243_DATA 0x0000C570
+#define DDRSS_PI_244_DATA 0x0000001D
+#define DDRSS_PI_245_DATA 0x180A0800
+#define DDRSS_PI_246_DATA 0x00001C1C
+#define DDRSS_PI_247_DATA 0x000030C0
+#define DDRSS_PI_248_DATA 0x0001E780
+#define DDRSS_PI_249_DATA 0x000030C0
+#define DDRSS_PI_250_DATA 0x0001E780
+#define DDRSS_PI_251_DATA 0x000030C0
+#define DDRSS_PI_252_DATA 0x0001E780
+#define DDRSS_PI_253_DATA 0x04000400
+#define DDRSS_PI_254_DATA 0x03030400
+#define DDRSS_PI_255_DATA 0x00040003
+#define DDRSS_PI_256_DATA 0x04000400
+#define DDRSS_PI_257_DATA 0x0C080C08
+#define DDRSS_PI_258_DATA 0x00000C08
+#define DDRSS_PI_259_DATA 0x000890B8
+#define DDRSS_PI_260_DATA 0x00000000
+#define DDRSS_PI_261_DATA 0x00000000
+#define DDRSS_PI_262_DATA 0x00000000
+#define DDRSS_PI_263_DATA 0x00000120
+#define DDRSS_PI_264_DATA 0x000890B8
+#define DDRSS_PI_265_DATA 0x00000000
+#define DDRSS_PI_266_DATA 0x00000000
+#define DDRSS_PI_267_DATA 0x00000000
+#define DDRSS_PI_268_DATA 0x00000120
+#define DDRSS_PI_269_DATA 0x000890B8
+#define DDRSS_PI_270_DATA 0x00000000
+#define DDRSS_PI_271_DATA 0x00000000
+#define DDRSS_PI_272_DATA 0x00000000
+#define DDRSS_PI_273_DATA 0x02000120
+#define DDRSS_PI_274_DATA 0x00000080
+#define DDRSS_PI_275_DATA 0x00020000
+#define DDRSS_PI_276_DATA 0x00000080
+#define DDRSS_PI_277_DATA 0x00020000
+#define DDRSS_PI_278_DATA 0x00000080
+#define DDRSS_PI_279_DATA 0x00000000
+#define DDRSS_PI_280_DATA 0x00000000
+#define DDRSS_PI_281_DATA 0x00040404
+#define DDRSS_PI_282_DATA 0x00000000
+#define DDRSS_PI_283_DATA 0x02010102
+#define DDRSS_PI_284_DATA 0x67676767
+#define DDRSS_PI_285_DATA 0x00000202
+#define DDRSS_PI_286_DATA 0x00000000
+#define DDRSS_PI_287_DATA 0x00000000
+#define DDRSS_PI_288_DATA 0x00000000
+#define DDRSS_PI_289_DATA 0x00000000
+#define DDRSS_PI_290_DATA 0x00000000
+#define DDRSS_PI_291_DATA 0x0D100F00
+#define DDRSS_PI_292_DATA 0x0003020E
+#define DDRSS_PI_293_DATA 0x00000001
+#define DDRSS_PI_294_DATA 0x01000000
+#define DDRSS_PI_295_DATA 0x00020201
+#define DDRSS_PI_296_DATA 0x00000000
+#define DDRSS_PI_297_DATA 0x00000424
+#define DDRSS_PI_298_DATA 0x00000301
+#define DDRSS_PI_299_DATA 0x00000000
+#define DDRSS_PI_300_DATA 0x00000000
+#define DDRSS_PI_301_DATA 0x00000000
+#define DDRSS_PI_302_DATA 0x00001401
+#define DDRSS_PI_303_DATA 0x00000493
+#define DDRSS_PI_304_DATA 0x00000000
+#define DDRSS_PI_305_DATA 0x00000424
+#define DDRSS_PI_306_DATA 0x00000301
+#define DDRSS_PI_307_DATA 0x00000000
+#define DDRSS_PI_308_DATA 0x00000000
+#define DDRSS_PI_309_DATA 0x00000000
+#define DDRSS_PI_310_DATA 0x00001401
+#define DDRSS_PI_311_DATA 0x00000493
+#define DDRSS_PI_312_DATA 0x00000000
+#define DDRSS_PI_313_DATA 0x00000424
+#define DDRSS_PI_314_DATA 0x00000301
+#define DDRSS_PI_315_DATA 0x00000000
+#define DDRSS_PI_316_DATA 0x00000000
+#define DDRSS_PI_317_DATA 0x00000000
+#define DDRSS_PI_318_DATA 0x00001401
+#define DDRSS_PI_319_DATA 0x00000493
+#define DDRSS_PI_320_DATA 0x00000000
+#define DDRSS_PI_321_DATA 0x00000424
+#define DDRSS_PI_322_DATA 0x00000301
+#define DDRSS_PI_323_DATA 0x00000000
+#define DDRSS_PI_324_DATA 0x00000000
+#define DDRSS_PI_325_DATA 0x00000000
+#define DDRSS_PI_326_DATA 0x00001401
+#define DDRSS_PI_327_DATA 0x00000493
+#define DDRSS_PI_328_DATA 0x00000000
+#define DDRSS_PI_329_DATA 0x00000424
+#define DDRSS_PI_330_DATA 0x00000301
+#define DDRSS_PI_331_DATA 0x00000000
+#define DDRSS_PI_332_DATA 0x00000000
+#define DDRSS_PI_333_DATA 0x00000000
+#define DDRSS_PI_334_DATA 0x00001401
+#define DDRSS_PI_335_DATA 0x00000493
+#define DDRSS_PI_336_DATA 0x00000000
+#define DDRSS_PI_337_DATA 0x00000424
+#define DDRSS_PI_338_DATA 0x00000301
+#define DDRSS_PI_339_DATA 0x00000000
+#define DDRSS_PI_340_DATA 0x00000000
+#define DDRSS_PI_341_DATA 0x00000000
+#define DDRSS_PI_342_DATA 0x00001401
+#define DDRSS_PI_343_DATA 0x00000493
+#define DDRSS_PI_344_DATA 0x00000000
+#define DDRSS_PHY_0_DATA 0x04C00000
+#define DDRSS_PHY_1_DATA 0x00000000
+#define DDRSS_PHY_2_DATA 0x00000200
+#define DDRSS_PHY_3_DATA 0x00000000
+#define DDRSS_PHY_4_DATA 0x00000000
+#define DDRSS_PHY_5_DATA 0x00000000
+#define DDRSS_PHY_6_DATA 0x00000000
+#define DDRSS_PHY_7_DATA 0x00000000
+#define DDRSS_PHY_8_DATA 0x00000001
+#define DDRSS_PHY_9_DATA 0x00000000
+#define DDRSS_PHY_10_DATA 0x00000000
+#define DDRSS_PHY_11_DATA 0x010101FF
+#define DDRSS_PHY_12_DATA 0x00010000
+#define DDRSS_PHY_13_DATA 0x00C00004
+#define DDRSS_PHY_14_DATA 0x00CC0008
+#define DDRSS_PHY_15_DATA 0x00660201
+#define DDRSS_PHY_16_DATA 0x00000000
+#define DDRSS_PHY_17_DATA 0x00000000
+#define DDRSS_PHY_18_DATA 0x00000000
+#define DDRSS_PHY_19_DATA 0x0000AAAA
+#define DDRSS_PHY_20_DATA 0x00005555
+#define DDRSS_PHY_21_DATA 0x0000B5B5
+#define DDRSS_PHY_22_DATA 0x00004A4A
+#define DDRSS_PHY_23_DATA 0x00005656
+#define DDRSS_PHY_24_DATA 0x0000A9A9
+#define DDRSS_PHY_25_DATA 0x0000B7B7
+#define DDRSS_PHY_26_DATA 0x00004848
+#define DDRSS_PHY_27_DATA 0x00000000
+#define DDRSS_PHY_28_DATA 0x00000000
+#define DDRSS_PHY_29_DATA 0x08000000
+#define DDRSS_PHY_30_DATA 0x0F000008
+#define DDRSS_PHY_31_DATA 0x00000F0F
+#define DDRSS_PHY_32_DATA 0x00E4E400
+#define DDRSS_PHY_33_DATA 0x00070820
+#define DDRSS_PHY_34_DATA 0x000C0020
+#define DDRSS_PHY_35_DATA 0x00062000
+#define DDRSS_PHY_36_DATA 0x00000000
+#define DDRSS_PHY_37_DATA 0x55555555
+#define DDRSS_PHY_38_DATA 0xAAAAAAAA
+#define DDRSS_PHY_39_DATA 0x55555555
+#define DDRSS_PHY_40_DATA 0xAAAAAAAA
+#define DDRSS_PHY_41_DATA 0x00005555
+#define DDRSS_PHY_42_DATA 0x01000100
+#define DDRSS_PHY_43_DATA 0x00800180
+#define DDRSS_PHY_44_DATA 0x00000000
+#define DDRSS_PHY_45_DATA 0x00000000
+#define DDRSS_PHY_46_DATA 0x00000000
+#define DDRSS_PHY_47_DATA 0x00000000
+#define DDRSS_PHY_48_DATA 0x00000000
+#define DDRSS_PHY_49_DATA 0x00000000
+#define DDRSS_PHY_50_DATA 0x00000000
+#define DDRSS_PHY_51_DATA 0x00000000
+#define DDRSS_PHY_52_DATA 0x00000000
+#define DDRSS_PHY_53_DATA 0x00000000
+#define DDRSS_PHY_54_DATA 0x00000000
+#define DDRSS_PHY_55_DATA 0x00000000
+#define DDRSS_PHY_56_DATA 0x00000000
+#define DDRSS_PHY_57_DATA 0x00000000
+#define DDRSS_PHY_58_DATA 0x00000000
+#define DDRSS_PHY_59_DATA 0x00000000
+#define DDRSS_PHY_60_DATA 0x00000000
+#define DDRSS_PHY_61_DATA 0x00000000
+#define DDRSS_PHY_62_DATA 0x00000000
+#define DDRSS_PHY_63_DATA 0x00000000
+#define DDRSS_PHY_64_DATA 0x00000000
+#define DDRSS_PHY_65_DATA 0x00000004
+#define DDRSS_PHY_66_DATA 0x00000000
+#define DDRSS_PHY_67_DATA 0x00000000
+#define DDRSS_PHY_68_DATA 0x00000000
+#define DDRSS_PHY_69_DATA 0x00000000
+#define DDRSS_PHY_70_DATA 0x00000000
+#define DDRSS_PHY_71_DATA 0x00000000
+#define DDRSS_PHY_72_DATA 0x041F07FF
+#define DDRSS_PHY_73_DATA 0x00000000
+#define DDRSS_PHY_74_DATA 0x01CCB001
+#define DDRSS_PHY_75_DATA 0x2000CCB0
+#define DDRSS_PHY_76_DATA 0x20000140
+#define DDRSS_PHY_77_DATA 0x07FF0200
+#define DDRSS_PHY_78_DATA 0x0000DD01
+#define DDRSS_PHY_79_DATA 0x10100303
+#define DDRSS_PHY_80_DATA 0x10101010
+#define DDRSS_PHY_81_DATA 0x10101010
+#define DDRSS_PHY_82_DATA 0x00021010
+#define DDRSS_PHY_83_DATA 0x00100010
+#define DDRSS_PHY_84_DATA 0x00100010
+#define DDRSS_PHY_85_DATA 0x00100010
+#define DDRSS_PHY_86_DATA 0x00100010
+#define DDRSS_PHY_87_DATA 0x02020010
+#define DDRSS_PHY_88_DATA 0x51515041
+#define DDRSS_PHY_89_DATA 0x31804000
+#define DDRSS_PHY_90_DATA 0x04BF0340
+#define DDRSS_PHY_91_DATA 0x01008080
+#define DDRSS_PHY_92_DATA 0x04050001
+#define DDRSS_PHY_93_DATA 0x00000504
+#define DDRSS_PHY_94_DATA 0x42100010
+#define DDRSS_PHY_95_DATA 0x010C053E
+#define DDRSS_PHY_96_DATA 0x000F0C14
+#define DDRSS_PHY_97_DATA 0x01000140
+#define DDRSS_PHY_98_DATA 0x007A0120
+#define DDRSS_PHY_99_DATA 0x00000C00
+#define DDRSS_PHY_100_DATA 0x000001CC
+#define DDRSS_PHY_101_DATA 0x20100200
+#define DDRSS_PHY_102_DATA 0x00000005
+#define DDRSS_PHY_103_DATA 0x76543210
+#define DDRSS_PHY_104_DATA 0x00000008
+#define DDRSS_PHY_105_DATA 0x02800280
+#define DDRSS_PHY_106_DATA 0x02800280
+#define DDRSS_PHY_107_DATA 0x02800280
+#define DDRSS_PHY_108_DATA 0x02800280
+#define DDRSS_PHY_109_DATA 0x00000280
+#define DDRSS_PHY_110_DATA 0x00008000
+#define DDRSS_PHY_111_DATA 0x00800080
+#define DDRSS_PHY_112_DATA 0x00800080
+#define DDRSS_PHY_113_DATA 0x00800080
+#define DDRSS_PHY_114_DATA 0x00800080
+#define DDRSS_PHY_115_DATA 0x00800080
+#define DDRSS_PHY_116_DATA 0x00800080
+#define DDRSS_PHY_117_DATA 0x00800080
+#define DDRSS_PHY_118_DATA 0x00800080
+#define DDRSS_PHY_119_DATA 0x01000080
+#define DDRSS_PHY_120_DATA 0x01000000
+#define DDRSS_PHY_121_DATA 0x00000000
+#define DDRSS_PHY_122_DATA 0x00000000
+#define DDRSS_PHY_123_DATA 0x00080200
+#define DDRSS_PHY_124_DATA 0x00000000
+#define DDRSS_PHY_125_DATA 0x00000000
+#define DDRSS_PHY_126_DATA 0x00000000
+#define DDRSS_PHY_127_DATA 0x00000000
+#define DDRSS_PHY_128_DATA 0x00000000
+#define DDRSS_PHY_129_DATA 0x00000000
+#define DDRSS_PHY_130_DATA 0x00000000
+#define DDRSS_PHY_131_DATA 0x00000000
+#define DDRSS_PHY_132_DATA 0x00000000
+#define DDRSS_PHY_133_DATA 0x00000000
+#define DDRSS_PHY_134_DATA 0x00000000
+#define DDRSS_PHY_135_DATA 0x00000000
+#define DDRSS_PHY_136_DATA 0x00000000
+#define DDRSS_PHY_137_DATA 0x00000000
+#define DDRSS_PHY_138_DATA 0x00000000
+#define DDRSS_PHY_139_DATA 0x00000000
+#define DDRSS_PHY_140_DATA 0x00000000
+#define DDRSS_PHY_141_DATA 0x00000000
+#define DDRSS_PHY_142_DATA 0x00000000
+#define DDRSS_PHY_143_DATA 0x00000000
+#define DDRSS_PHY_144_DATA 0x00000000
+#define DDRSS_PHY_145_DATA 0x00000000
+#define DDRSS_PHY_146_DATA 0x00000000
+#define DDRSS_PHY_147_DATA 0x00000000
+#define DDRSS_PHY_148_DATA 0x00000000
+#define DDRSS_PHY_149_DATA 0x00000000
+#define DDRSS_PHY_150_DATA 0x00000000
+#define DDRSS_PHY_151_DATA 0x00000000
+#define DDRSS_PHY_152_DATA 0x00000000
+#define DDRSS_PHY_153_DATA 0x00000000
+#define DDRSS_PHY_154_DATA 0x00000000
+#define DDRSS_PHY_155_DATA 0x00000000
+#define DDRSS_PHY_156_DATA 0x00000000
+#define DDRSS_PHY_157_DATA 0x00000000
+#define DDRSS_PHY_158_DATA 0x00000000
+#define DDRSS_PHY_159_DATA 0x00000000
+#define DDRSS_PHY_160_DATA 0x00000000
+#define DDRSS_PHY_161_DATA 0x00000000
+#define DDRSS_PHY_162_DATA 0x00000000
+#define DDRSS_PHY_163_DATA 0x00000000
+#define DDRSS_PHY_164_DATA 0x00000000
+#define DDRSS_PHY_165_DATA 0x00000000
+#define DDRSS_PHY_166_DATA 0x00000000
+#define DDRSS_PHY_167_DATA 0x00000000
+#define DDRSS_PHY_168_DATA 0x00000000
+#define DDRSS_PHY_169_DATA 0x00000000
+#define DDRSS_PHY_170_DATA 0x00000000
+#define DDRSS_PHY_171_DATA 0x00000000
+#define DDRSS_PHY_172_DATA 0x00000000
+#define DDRSS_PHY_173_DATA 0x00000000
+#define DDRSS_PHY_174_DATA 0x00000000
+#define DDRSS_PHY_175_DATA 0x00000000
+#define DDRSS_PHY_176_DATA 0x00000000
+#define DDRSS_PHY_177_DATA 0x00000000
+#define DDRSS_PHY_178_DATA 0x00000000
+#define DDRSS_PHY_179_DATA 0x00000000
+#define DDRSS_PHY_180_DATA 0x00000000
+#define DDRSS_PHY_181_DATA 0x00000000
+#define DDRSS_PHY_182_DATA 0x00000000
+#define DDRSS_PHY_183_DATA 0x00000000
+#define DDRSS_PHY_184_DATA 0x00000000
+#define DDRSS_PHY_185_DATA 0x00000000
+#define DDRSS_PHY_186_DATA 0x00000000
+#define DDRSS_PHY_187_DATA 0x00000000
+#define DDRSS_PHY_188_DATA 0x00000000
+#define DDRSS_PHY_189_DATA 0x00000000
+#define DDRSS_PHY_190_DATA 0x00000000
+#define DDRSS_PHY_191_DATA 0x00000000
+#define DDRSS_PHY_192_DATA 0x00000000
+#define DDRSS_PHY_193_DATA 0x00000000
+#define DDRSS_PHY_194_DATA 0x00000000
+#define DDRSS_PHY_195_DATA 0x00000000
+#define DDRSS_PHY_196_DATA 0x00000000
+#define DDRSS_PHY_197_DATA 0x00000000
+#define DDRSS_PHY_198_DATA 0x00000000
+#define DDRSS_PHY_199_DATA 0x00000000
+#define DDRSS_PHY_200_DATA 0x00000000
+#define DDRSS_PHY_201_DATA 0x00000000
+#define DDRSS_PHY_202_DATA 0x00000000
+#define DDRSS_PHY_203_DATA 0x00000000
+#define DDRSS_PHY_204_DATA 0x00000000
+#define DDRSS_PHY_205_DATA 0x00000000
+#define DDRSS_PHY_206_DATA 0x00000000
+#define DDRSS_PHY_207_DATA 0x00000000
+#define DDRSS_PHY_208_DATA 0x00000000
+#define DDRSS_PHY_209_DATA 0x00000000
+#define DDRSS_PHY_210_DATA 0x00000000
+#define DDRSS_PHY_211_DATA 0x00000000
+#define DDRSS_PHY_212_DATA 0x00000000
+#define DDRSS_PHY_213_DATA 0x00000000
+#define DDRSS_PHY_214_DATA 0x00000000
+#define DDRSS_PHY_215_DATA 0x00000000
+#define DDRSS_PHY_216_DATA 0x00000000
+#define DDRSS_PHY_217_DATA 0x00000000
+#define DDRSS_PHY_218_DATA 0x00000000
+#define DDRSS_PHY_219_DATA 0x00000000
+#define DDRSS_PHY_220_DATA 0x00000000
+#define DDRSS_PHY_221_DATA 0x00000000
+#define DDRSS_PHY_222_DATA 0x00000000
+#define DDRSS_PHY_223_DATA 0x00000000
+#define DDRSS_PHY_224_DATA 0x00000000
+#define DDRSS_PHY_225_DATA 0x00000000
+#define DDRSS_PHY_226_DATA 0x00000000
+#define DDRSS_PHY_227_DATA 0x00000000
+#define DDRSS_PHY_228_DATA 0x00000000
+#define DDRSS_PHY_229_DATA 0x00000000
+#define DDRSS_PHY_230_DATA 0x00000000
+#define DDRSS_PHY_231_DATA 0x00000000
+#define DDRSS_PHY_232_DATA 0x00000000
+#define DDRSS_PHY_233_DATA 0x00000000
+#define DDRSS_PHY_234_DATA 0x00000000
+#define DDRSS_PHY_235_DATA 0x00000000
+#define DDRSS_PHY_236_DATA 0x00000000
+#define DDRSS_PHY_237_DATA 0x00000000
+#define DDRSS_PHY_238_DATA 0x00000000
+#define DDRSS_PHY_239_DATA 0x00000000
+#define DDRSS_PHY_240_DATA 0x00000000
+#define DDRSS_PHY_241_DATA 0x00000000
+#define DDRSS_PHY_242_DATA 0x00000000
+#define DDRSS_PHY_243_DATA 0x00000000
+#define DDRSS_PHY_244_DATA 0x00000000
+#define DDRSS_PHY_245_DATA 0x00000000
+#define DDRSS_PHY_246_DATA 0x00000000
+#define DDRSS_PHY_247_DATA 0x00000000
+#define DDRSS_PHY_248_DATA 0x00000000
+#define DDRSS_PHY_249_DATA 0x00000000
+#define DDRSS_PHY_250_DATA 0x00000000
+#define DDRSS_PHY_251_DATA 0x00000000
+#define DDRSS_PHY_252_DATA 0x00000000
+#define DDRSS_PHY_253_DATA 0x00000000
+#define DDRSS_PHY_254_DATA 0x00000000
+#define DDRSS_PHY_255_DATA 0x00000000
+#define DDRSS_PHY_256_DATA 0x04C00000
+#define DDRSS_PHY_257_DATA 0x00000000
+#define DDRSS_PHY_258_DATA 0x00000200
+#define DDRSS_PHY_259_DATA 0x00000000
+#define DDRSS_PHY_260_DATA 0x00000000
+#define DDRSS_PHY_261_DATA 0x00000000
+#define DDRSS_PHY_262_DATA 0x00000000
+#define DDRSS_PHY_263_DATA 0x00000000
+#define DDRSS_PHY_264_DATA 0x00000001
+#define DDRSS_PHY_265_DATA 0x00000000
+#define DDRSS_PHY_266_DATA 0x00000000
+#define DDRSS_PHY_267_DATA 0x010101FF
+#define DDRSS_PHY_268_DATA 0x00010000
+#define DDRSS_PHY_269_DATA 0x00C00004
+#define DDRSS_PHY_270_DATA 0x00CC0008
+#define DDRSS_PHY_271_DATA 0x00660201
+#define DDRSS_PHY_272_DATA 0x00000000
+#define DDRSS_PHY_273_DATA 0x00000000
+#define DDRSS_PHY_274_DATA 0x00000000
+#define DDRSS_PHY_275_DATA 0x0000AAAA
+#define DDRSS_PHY_276_DATA 0x00005555
+#define DDRSS_PHY_277_DATA 0x0000B5B5
+#define DDRSS_PHY_278_DATA 0x00004A4A
+#define DDRSS_PHY_279_DATA 0x00005656
+#define DDRSS_PHY_280_DATA 0x0000A9A9
+#define DDRSS_PHY_281_DATA 0x0000B7B7
+#define DDRSS_PHY_282_DATA 0x00004848
+#define DDRSS_PHY_283_DATA 0x00000000
+#define DDRSS_PHY_284_DATA 0x00000000
+#define DDRSS_PHY_285_DATA 0x08000000
+#define DDRSS_PHY_286_DATA 0x0F000008
+#define DDRSS_PHY_287_DATA 0x00000F0F
+#define DDRSS_PHY_288_DATA 0x00E4E400
+#define DDRSS_PHY_289_DATA 0x00070820
+#define DDRSS_PHY_290_DATA 0x000C0020
+#define DDRSS_PHY_291_DATA 0x00062000
+#define DDRSS_PHY_292_DATA 0x00000000
+#define DDRSS_PHY_293_DATA 0x55555555
+#define DDRSS_PHY_294_DATA 0xAAAAAAAA
+#define DDRSS_PHY_295_DATA 0x55555555
+#define DDRSS_PHY_296_DATA 0xAAAAAAAA
+#define DDRSS_PHY_297_DATA 0x00005555
+#define DDRSS_PHY_298_DATA 0x01000100
+#define DDRSS_PHY_299_DATA 0x00800180
+#define DDRSS_PHY_300_DATA 0x00000000
+#define DDRSS_PHY_301_DATA 0x00000000
+#define DDRSS_PHY_302_DATA 0x00000000
+#define DDRSS_PHY_303_DATA 0x00000000
+#define DDRSS_PHY_304_DATA 0x00000000
+#define DDRSS_PHY_305_DATA 0x00000000
+#define DDRSS_PHY_306_DATA 0x00000000
+#define DDRSS_PHY_307_DATA 0x00000000
+#define DDRSS_PHY_308_DATA 0x00000000
+#define DDRSS_PHY_309_DATA 0x00000000
+#define DDRSS_PHY_310_DATA 0x00000000
+#define DDRSS_PHY_311_DATA 0x00000000
+#define DDRSS_PHY_312_DATA 0x00000000
+#define DDRSS_PHY_313_DATA 0x00000000
+#define DDRSS_PHY_314_DATA 0x00000000
+#define DDRSS_PHY_315_DATA 0x00000000
+#define DDRSS_PHY_316_DATA 0x00000000
+#define DDRSS_PHY_317_DATA 0x00000000
+#define DDRSS_PHY_318_DATA 0x00000000
+#define DDRSS_PHY_319_DATA 0x00000000
+#define DDRSS_PHY_320_DATA 0x00000000
+#define DDRSS_PHY_321_DATA 0x00000004
+#define DDRSS_PHY_322_DATA 0x00000000
+#define DDRSS_PHY_323_DATA 0x00000000
+#define DDRSS_PHY_324_DATA 0x00000000
+#define DDRSS_PHY_325_DATA 0x00000000
+#define DDRSS_PHY_326_DATA 0x00000000
+#define DDRSS_PHY_327_DATA 0x00000000
+#define DDRSS_PHY_328_DATA 0x041F07FF
+#define DDRSS_PHY_329_DATA 0x00000000
+#define DDRSS_PHY_330_DATA 0x01CCB001
+#define DDRSS_PHY_331_DATA 0x2000CCB0
+#define DDRSS_PHY_332_DATA 0x20000140
+#define DDRSS_PHY_333_DATA 0x07FF0200
+#define DDRSS_PHY_334_DATA 0x0000DD01
+#define DDRSS_PHY_335_DATA 0x10100303
+#define DDRSS_PHY_336_DATA 0x10101010
+#define DDRSS_PHY_337_DATA 0x10101010
+#define DDRSS_PHY_338_DATA 0x00021010
+#define DDRSS_PHY_339_DATA 0x00100010
+#define DDRSS_PHY_340_DATA 0x00100010
+#define DDRSS_PHY_341_DATA 0x00100010
+#define DDRSS_PHY_342_DATA 0x00100010
+#define DDRSS_PHY_343_DATA 0x02020010
+#define DDRSS_PHY_344_DATA 0x51515041
+#define DDRSS_PHY_345_DATA 0x31804000
+#define DDRSS_PHY_346_DATA 0x04BF0340
+#define DDRSS_PHY_347_DATA 0x01008080
+#define DDRSS_PHY_348_DATA 0x04050001
+#define DDRSS_PHY_349_DATA 0x00000504
+#define DDRSS_PHY_350_DATA 0x42100010
+#define DDRSS_PHY_351_DATA 0x010C053E
+#define DDRSS_PHY_352_DATA 0x000F0C14
+#define DDRSS_PHY_353_DATA 0x01000140
+#define DDRSS_PHY_354_DATA 0x007A0120
+#define DDRSS_PHY_355_DATA 0x00000C00
+#define DDRSS_PHY_356_DATA 0x000001CC
+#define DDRSS_PHY_357_DATA 0x20100200
+#define DDRSS_PHY_358_DATA 0x00000005
+#define DDRSS_PHY_359_DATA 0x76543210
+#define DDRSS_PHY_360_DATA 0x00000008
+#define DDRSS_PHY_361_DATA 0x02800280
+#define DDRSS_PHY_362_DATA 0x02800280
+#define DDRSS_PHY_363_DATA 0x02800280
+#define DDRSS_PHY_364_DATA 0x02800280
+#define DDRSS_PHY_365_DATA 0x00000280
+#define DDRSS_PHY_366_DATA 0x00008000
+#define DDRSS_PHY_367_DATA 0x00800080
+#define DDRSS_PHY_368_DATA 0x00800080
+#define DDRSS_PHY_369_DATA 0x00800080
+#define DDRSS_PHY_370_DATA 0x00800080
+#define DDRSS_PHY_371_DATA 0x00800080
+#define DDRSS_PHY_372_DATA 0x00800080
+#define DDRSS_PHY_373_DATA 0x00800080
+#define DDRSS_PHY_374_DATA 0x00800080
+#define DDRSS_PHY_375_DATA 0x01000080
+#define DDRSS_PHY_376_DATA 0x01000000
+#define DDRSS_PHY_377_DATA 0x00000000
+#define DDRSS_PHY_378_DATA 0x00000000
+#define DDRSS_PHY_379_DATA 0x00080200
+#define DDRSS_PHY_380_DATA 0x00000000
+#define DDRSS_PHY_381_DATA 0x00000000
+#define DDRSS_PHY_382_DATA 0x00000000
+#define DDRSS_PHY_383_DATA 0x00000000
+#define DDRSS_PHY_384_DATA 0x00000000
+#define DDRSS_PHY_385_DATA 0x00000000
+#define DDRSS_PHY_386_DATA 0x00000000
+#define DDRSS_PHY_387_DATA 0x00000000
+#define DDRSS_PHY_388_DATA 0x00000000
+#define DDRSS_PHY_389_DATA 0x00000000
+#define DDRSS_PHY_390_DATA 0x00000000
+#define DDRSS_PHY_391_DATA 0x00000000
+#define DDRSS_PHY_392_DATA 0x00000000
+#define DDRSS_PHY_393_DATA 0x00000000
+#define DDRSS_PHY_394_DATA 0x00000000
+#define DDRSS_PHY_395_DATA 0x00000000
+#define DDRSS_PHY_396_DATA 0x00000000
+#define DDRSS_PHY_397_DATA 0x00000000
+#define DDRSS_PHY_398_DATA 0x00000000
+#define DDRSS_PHY_399_DATA 0x00000000
+#define DDRSS_PHY_400_DATA 0x00000000
+#define DDRSS_PHY_401_DATA 0x00000000
+#define DDRSS_PHY_402_DATA 0x00000000
+#define DDRSS_PHY_403_DATA 0x00000000
+#define DDRSS_PHY_404_DATA 0x00000000
+#define DDRSS_PHY_405_DATA 0x00000000
+#define DDRSS_PHY_406_DATA 0x00000000
+#define DDRSS_PHY_407_DATA 0x00000000
+#define DDRSS_PHY_408_DATA 0x00000000
+#define DDRSS_PHY_409_DATA 0x00000000
+#define DDRSS_PHY_410_DATA 0x00000000
+#define DDRSS_PHY_411_DATA 0x00000000
+#define DDRSS_PHY_412_DATA 0x00000000
+#define DDRSS_PHY_413_DATA 0x00000000
+#define DDRSS_PHY_414_DATA 0x00000000
+#define DDRSS_PHY_415_DATA 0x00000000
+#define DDRSS_PHY_416_DATA 0x00000000
+#define DDRSS_PHY_417_DATA 0x00000000
+#define DDRSS_PHY_418_DATA 0x00000000
+#define DDRSS_PHY_419_DATA 0x00000000
+#define DDRSS_PHY_420_DATA 0x00000000
+#define DDRSS_PHY_421_DATA 0x00000000
+#define DDRSS_PHY_422_DATA 0x00000000
+#define DDRSS_PHY_423_DATA 0x00000000
+#define DDRSS_PHY_424_DATA 0x00000000
+#define DDRSS_PHY_425_DATA 0x00000000
+#define DDRSS_PHY_426_DATA 0x00000000
+#define DDRSS_PHY_427_DATA 0x00000000
+#define DDRSS_PHY_428_DATA 0x00000000
+#define DDRSS_PHY_429_DATA 0x00000000
+#define DDRSS_PHY_430_DATA 0x00000000
+#define DDRSS_PHY_431_DATA 0x00000000
+#define DDRSS_PHY_432_DATA 0x00000000
+#define DDRSS_PHY_433_DATA 0x00000000
+#define DDRSS_PHY_434_DATA 0x00000000
+#define DDRSS_PHY_435_DATA 0x00000000
+#define DDRSS_PHY_436_DATA 0x00000000
+#define DDRSS_PHY_437_DATA 0x00000000
+#define DDRSS_PHY_438_DATA 0x00000000
+#define DDRSS_PHY_439_DATA 0x00000000
+#define DDRSS_PHY_440_DATA 0x00000000
+#define DDRSS_PHY_441_DATA 0x00000000
+#define DDRSS_PHY_442_DATA 0x00000000
+#define DDRSS_PHY_443_DATA 0x00000000
+#define DDRSS_PHY_444_DATA 0x00000000
+#define DDRSS_PHY_445_DATA 0x00000000
+#define DDRSS_PHY_446_DATA 0x00000000
+#define DDRSS_PHY_447_DATA 0x00000000
+#define DDRSS_PHY_448_DATA 0x00000000
+#define DDRSS_PHY_449_DATA 0x00000000
+#define DDRSS_PHY_450_DATA 0x00000000
+#define DDRSS_PHY_451_DATA 0x00000000
+#define DDRSS_PHY_452_DATA 0x00000000
+#define DDRSS_PHY_453_DATA 0x00000000
+#define DDRSS_PHY_454_DATA 0x00000000
+#define DDRSS_PHY_455_DATA 0x00000000
+#define DDRSS_PHY_456_DATA 0x00000000
+#define DDRSS_PHY_457_DATA 0x00000000
+#define DDRSS_PHY_458_DATA 0x00000000
+#define DDRSS_PHY_459_DATA 0x00000000
+#define DDRSS_PHY_460_DATA 0x00000000
+#define DDRSS_PHY_461_DATA 0x00000000
+#define DDRSS_PHY_462_DATA 0x00000000
+#define DDRSS_PHY_463_DATA 0x00000000
+#define DDRSS_PHY_464_DATA 0x00000000
+#define DDRSS_PHY_465_DATA 0x00000000
+#define DDRSS_PHY_466_DATA 0x00000000
+#define DDRSS_PHY_467_DATA 0x00000000
+#define DDRSS_PHY_468_DATA 0x00000000
+#define DDRSS_PHY_469_DATA 0x00000000
+#define DDRSS_PHY_470_DATA 0x00000000
+#define DDRSS_PHY_471_DATA 0x00000000
+#define DDRSS_PHY_472_DATA 0x00000000
+#define DDRSS_PHY_473_DATA 0x00000000
+#define DDRSS_PHY_474_DATA 0x00000000
+#define DDRSS_PHY_475_DATA 0x00000000
+#define DDRSS_PHY_476_DATA 0x00000000
+#define DDRSS_PHY_477_DATA 0x00000000
+#define DDRSS_PHY_478_DATA 0x00000000
+#define DDRSS_PHY_479_DATA 0x00000000
+#define DDRSS_PHY_480_DATA 0x00000000
+#define DDRSS_PHY_481_DATA 0x00000000
+#define DDRSS_PHY_482_DATA 0x00000000
+#define DDRSS_PHY_483_DATA 0x00000000
+#define DDRSS_PHY_484_DATA 0x00000000
+#define DDRSS_PHY_485_DATA 0x00000000
+#define DDRSS_PHY_486_DATA 0x00000000
+#define DDRSS_PHY_487_DATA 0x00000000
+#define DDRSS_PHY_488_DATA 0x00000000
+#define DDRSS_PHY_489_DATA 0x00000000
+#define DDRSS_PHY_490_DATA 0x00000000
+#define DDRSS_PHY_491_DATA 0x00000000
+#define DDRSS_PHY_492_DATA 0x00000000
+#define DDRSS_PHY_493_DATA 0x00000000
+#define DDRSS_PHY_494_DATA 0x00000000
+#define DDRSS_PHY_495_DATA 0x00000000
+#define DDRSS_PHY_496_DATA 0x00000000
+#define DDRSS_PHY_497_DATA 0x00000000
+#define DDRSS_PHY_498_DATA 0x00000000
+#define DDRSS_PHY_499_DATA 0x00000000
+#define DDRSS_PHY_500_DATA 0x00000000
+#define DDRSS_PHY_501_DATA 0x00000000
+#define DDRSS_PHY_502_DATA 0x00000000
+#define DDRSS_PHY_503_DATA 0x00000000
+#define DDRSS_PHY_504_DATA 0x00000000
+#define DDRSS_PHY_505_DATA 0x00000000
+#define DDRSS_PHY_506_DATA 0x00000000
+#define DDRSS_PHY_507_DATA 0x00000000
+#define DDRSS_PHY_508_DATA 0x00000000
+#define DDRSS_PHY_509_DATA 0x00000000
+#define DDRSS_PHY_510_DATA 0x00000000
+#define DDRSS_PHY_511_DATA 0x00000000
+#define DDRSS_PHY_512_DATA 0x00000100
+#define DDRSS_PHY_513_DATA 0x00000000
+#define DDRSS_PHY_514_DATA 0x00000000
+#define DDRSS_PHY_515_DATA 0x00000000
+#define DDRSS_PHY_516_DATA 0x00000000
+#define DDRSS_PHY_517_DATA 0x00000100
+#define DDRSS_PHY_518_DATA 0x00000000
+#define DDRSS_PHY_519_DATA 0x00000000
+#define DDRSS_PHY_520_DATA 0x00000000
+#define DDRSS_PHY_521_DATA 0x00000000
+#define DDRSS_PHY_522_DATA 0x00000000
+#define DDRSS_PHY_523_DATA 0x00000000
+#define DDRSS_PHY_524_DATA 0x00000000
+#define DDRSS_PHY_525_DATA 0x00DCBA98
+#define DDRSS_PHY_526_DATA 0x00000000
+#define DDRSS_PHY_527_DATA 0x00000000
+#define DDRSS_PHY_528_DATA 0x00000000
+#define DDRSS_PHY_529_DATA 0x00000000
+#define DDRSS_PHY_530_DATA 0x00000000
+#define DDRSS_PHY_531_DATA 0x00000000
+#define DDRSS_PHY_532_DATA 0x00000000
+#define DDRSS_PHY_533_DATA 0x00000000
+#define DDRSS_PHY_534_DATA 0x00000000
+#define DDRSS_PHY_535_DATA 0x00000000
+#define DDRSS_PHY_536_DATA 0x00000000
+#define DDRSS_PHY_537_DATA 0x00000000
+#define DDRSS_PHY_538_DATA 0x00000000
+#define DDRSS_PHY_539_DATA 0x00000000
+#define DDRSS_PHY_540_DATA 0x0A418820
+#define DDRSS_PHY_541_DATA 0x103F0000
+#define DDRSS_PHY_542_DATA 0x000F0100
+#define DDRSS_PHY_543_DATA 0x0000000F
+#define DDRSS_PHY_544_DATA 0x020002CC
+#define DDRSS_PHY_545_DATA 0x00030000
+#define DDRSS_PHY_546_DATA 0x00000300
+#define DDRSS_PHY_547_DATA 0x00000300
+#define DDRSS_PHY_548_DATA 0x00000300
+#define DDRSS_PHY_549_DATA 0x00000300
+#define DDRSS_PHY_550_DATA 0x00000300
+#define DDRSS_PHY_551_DATA 0x42080010
+#define DDRSS_PHY_552_DATA 0x0000003E
+#define DDRSS_PHY_553_DATA 0x00000000
+#define DDRSS_PHY_554_DATA 0x00000000
+#define DDRSS_PHY_555_DATA 0x00000000
+#define DDRSS_PHY_556_DATA 0x00000000
+#define DDRSS_PHY_557_DATA 0x00000000
+#define DDRSS_PHY_558_DATA 0x00000000
+#define DDRSS_PHY_559_DATA 0x00000000
+#define DDRSS_PHY_560_DATA 0x00000000
+#define DDRSS_PHY_561_DATA 0x00000000
+#define DDRSS_PHY_562_DATA 0x00000000
+#define DDRSS_PHY_563_DATA 0x00000000
+#define DDRSS_PHY_564_DATA 0x00000000
+#define DDRSS_PHY_565_DATA 0x00000000
+#define DDRSS_PHY_566_DATA 0x00000000
+#define DDRSS_PHY_567_DATA 0x00000000
+#define DDRSS_PHY_568_DATA 0x00000000
+#define DDRSS_PHY_569_DATA 0x00000000
+#define DDRSS_PHY_570_DATA 0x00000000
+#define DDRSS_PHY_571_DATA 0x00000000
+#define DDRSS_PHY_572_DATA 0x00000000
+#define DDRSS_PHY_573_DATA 0x00000000
+#define DDRSS_PHY_574_DATA 0x00000000
+#define DDRSS_PHY_575_DATA 0x00000000
+#define DDRSS_PHY_576_DATA 0x00000000
+#define DDRSS_PHY_577_DATA 0x00000000
+#define DDRSS_PHY_578_DATA 0x00000000
+#define DDRSS_PHY_579_DATA 0x00000000
+#define DDRSS_PHY_580_DATA 0x00000000
+#define DDRSS_PHY_581_DATA 0x00000000
+#define DDRSS_PHY_582_DATA 0x00000000
+#define DDRSS_PHY_583_DATA 0x00000000
+#define DDRSS_PHY_584_DATA 0x00000000
+#define DDRSS_PHY_585_DATA 0x00000000
+#define DDRSS_PHY_586_DATA 0x00000000
+#define DDRSS_PHY_587_DATA 0x00000000
+#define DDRSS_PHY_588_DATA 0x00000000
+#define DDRSS_PHY_589_DATA 0x00000000
+#define DDRSS_PHY_590_DATA 0x00000000
+#define DDRSS_PHY_591_DATA 0x00000000
+#define DDRSS_PHY_592_DATA 0x00000000
+#define DDRSS_PHY_593_DATA 0x00000000
+#define DDRSS_PHY_594_DATA 0x00000000
+#define DDRSS_PHY_595_DATA 0x00000000
+#define DDRSS_PHY_596_DATA 0x00000000
+#define DDRSS_PHY_597_DATA 0x00000000
+#define DDRSS_PHY_598_DATA 0x00000000
+#define DDRSS_PHY_599_DATA 0x00000000
+#define DDRSS_PHY_600_DATA 0x00000000
+#define DDRSS_PHY_601_DATA 0x00000000
+#define DDRSS_PHY_602_DATA 0x00000000
+#define DDRSS_PHY_603_DATA 0x00000000
+#define DDRSS_PHY_604_DATA 0x00000000
+#define DDRSS_PHY_605_DATA 0x00000000
+#define DDRSS_PHY_606_DATA 0x00000000
+#define DDRSS_PHY_607_DATA 0x00000000
+#define DDRSS_PHY_608_DATA 0x00000000
+#define DDRSS_PHY_609_DATA 0x00000000
+#define DDRSS_PHY_610_DATA 0x00000000
+#define DDRSS_PHY_611_DATA 0x00000000
+#define DDRSS_PHY_612_DATA 0x00000000
+#define DDRSS_PHY_613_DATA 0x00000000
+#define DDRSS_PHY_614_DATA 0x00000000
+#define DDRSS_PHY_615_DATA 0x00000000
+#define DDRSS_PHY_616_DATA 0x00000000
+#define DDRSS_PHY_617_DATA 0x00000000
+#define DDRSS_PHY_618_DATA 0x00000000
+#define DDRSS_PHY_619_DATA 0x00000000
+#define DDRSS_PHY_620_DATA 0x00000000
+#define DDRSS_PHY_621_DATA 0x00000000
+#define DDRSS_PHY_622_DATA 0x00000000
+#define DDRSS_PHY_623_DATA 0x00000000
+#define DDRSS_PHY_624_DATA 0x00000000
+#define DDRSS_PHY_625_DATA 0x00000000
+#define DDRSS_PHY_626_DATA 0x00000000
+#define DDRSS_PHY_627_DATA 0x00000000
+#define DDRSS_PHY_628_DATA 0x00000000
+#define DDRSS_PHY_629_DATA 0x00000000
+#define DDRSS_PHY_630_DATA 0x00000000
+#define DDRSS_PHY_631_DATA 0x00000000
+#define DDRSS_PHY_632_DATA 0x00000000
+#define DDRSS_PHY_633_DATA 0x00000000
+#define DDRSS_PHY_634_DATA 0x00000000
+#define DDRSS_PHY_635_DATA 0x00000000
+#define DDRSS_PHY_636_DATA 0x00000000
+#define DDRSS_PHY_637_DATA 0x00000000
+#define DDRSS_PHY_638_DATA 0x00000000
+#define DDRSS_PHY_639_DATA 0x00000000
+#define DDRSS_PHY_640_DATA 0x00000000
+#define DDRSS_PHY_641_DATA 0x00000000
+#define DDRSS_PHY_642_DATA 0x00000000
+#define DDRSS_PHY_643_DATA 0x00000000
+#define DDRSS_PHY_644_DATA 0x00000000
+#define DDRSS_PHY_645_DATA 0x00000000
+#define DDRSS_PHY_646_DATA 0x00000000
+#define DDRSS_PHY_647_DATA 0x00000000
+#define DDRSS_PHY_648_DATA 0x00000000
+#define DDRSS_PHY_649_DATA 0x00000000
+#define DDRSS_PHY_650_DATA 0x00000000
+#define DDRSS_PHY_651_DATA 0x00000000
+#define DDRSS_PHY_652_DATA 0x00000000
+#define DDRSS_PHY_653_DATA 0x00000000
+#define DDRSS_PHY_654_DATA 0x00000000
+#define DDRSS_PHY_655_DATA 0x00000000
+#define DDRSS_PHY_656_DATA 0x00000000
+#define DDRSS_PHY_657_DATA 0x00000000
+#define DDRSS_PHY_658_DATA 0x00000000
+#define DDRSS_PHY_659_DATA 0x00000000
+#define DDRSS_PHY_660_DATA 0x00000000
+#define DDRSS_PHY_661_DATA 0x00000000
+#define DDRSS_PHY_662_DATA 0x00000000
+#define DDRSS_PHY_663_DATA 0x00000000
+#define DDRSS_PHY_664_DATA 0x00000000
+#define DDRSS_PHY_665_DATA 0x00000000
+#define DDRSS_PHY_666_DATA 0x00000000
+#define DDRSS_PHY_667_DATA 0x00000000
+#define DDRSS_PHY_668_DATA 0x00000000
+#define DDRSS_PHY_669_DATA 0x00000000
+#define DDRSS_PHY_670_DATA 0x00000000
+#define DDRSS_PHY_671_DATA 0x00000000
+#define DDRSS_PHY_672_DATA 0x00000000
+#define DDRSS_PHY_673_DATA 0x00000000
+#define DDRSS_PHY_674_DATA 0x00000000
+#define DDRSS_PHY_675_DATA 0x00000000
+#define DDRSS_PHY_676_DATA 0x00000000
+#define DDRSS_PHY_677_DATA 0x00000000
+#define DDRSS_PHY_678_DATA 0x00000000
+#define DDRSS_PHY_679_DATA 0x00000000
+#define DDRSS_PHY_680_DATA 0x00000000
+#define DDRSS_PHY_681_DATA 0x00000000
+#define DDRSS_PHY_682_DATA 0x00000000
+#define DDRSS_PHY_683_DATA 0x00000000
+#define DDRSS_PHY_684_DATA 0x00000000
+#define DDRSS_PHY_685_DATA 0x00000000
+#define DDRSS_PHY_686_DATA 0x00000000
+#define DDRSS_PHY_687_DATA 0x00000000
+#define DDRSS_PHY_688_DATA 0x00000000
+#define DDRSS_PHY_689_DATA 0x00000000
+#define DDRSS_PHY_690_DATA 0x00000000
+#define DDRSS_PHY_691_DATA 0x00000000
+#define DDRSS_PHY_692_DATA 0x00000000
+#define DDRSS_PHY_693_DATA 0x00000000
+#define DDRSS_PHY_694_DATA 0x00000000
+#define DDRSS_PHY_695_DATA 0x00000000
+#define DDRSS_PHY_696_DATA 0x00000000
+#define DDRSS_PHY_697_DATA 0x00000000
+#define DDRSS_PHY_698_DATA 0x00000000
+#define DDRSS_PHY_699_DATA 0x00000000
+#define DDRSS_PHY_700_DATA 0x00000000
+#define DDRSS_PHY_701_DATA 0x00000000
+#define DDRSS_PHY_702_DATA 0x00000000
+#define DDRSS_PHY_703_DATA 0x00000000
+#define DDRSS_PHY_704_DATA 0x00000000
+#define DDRSS_PHY_705_DATA 0x00000000
+#define DDRSS_PHY_706_DATA 0x00000000
+#define DDRSS_PHY_707_DATA 0x00000000
+#define DDRSS_PHY_708_DATA 0x00000000
+#define DDRSS_PHY_709_DATA 0x00000000
+#define DDRSS_PHY_710_DATA 0x00000000
+#define DDRSS_PHY_711_DATA 0x00000000
+#define DDRSS_PHY_712_DATA 0x00000000
+#define DDRSS_PHY_713_DATA 0x00000000
+#define DDRSS_PHY_714_DATA 0x00000000
+#define DDRSS_PHY_715_DATA 0x00000000
+#define DDRSS_PHY_716_DATA 0x00000000
+#define DDRSS_PHY_717_DATA 0x00000000
+#define DDRSS_PHY_718_DATA 0x00000000
+#define DDRSS_PHY_719_DATA 0x00000000
+#define DDRSS_PHY_720_DATA 0x00000000
+#define DDRSS_PHY_721_DATA 0x00000000
+#define DDRSS_PHY_722_DATA 0x00000000
+#define DDRSS_PHY_723_DATA 0x00000000
+#define DDRSS_PHY_724_DATA 0x00000000
+#define DDRSS_PHY_725_DATA 0x00000000
+#define DDRSS_PHY_726_DATA 0x00000000
+#define DDRSS_PHY_727_DATA 0x00000000
+#define DDRSS_PHY_728_DATA 0x00000000
+#define DDRSS_PHY_729_DATA 0x00000000
+#define DDRSS_PHY_730_DATA 0x00000000
+#define DDRSS_PHY_731_DATA 0x00000000
+#define DDRSS_PHY_732_DATA 0x00000000
+#define DDRSS_PHY_733_DATA 0x00000000
+#define DDRSS_PHY_734_DATA 0x00000000
+#define DDRSS_PHY_735_DATA 0x00000000
+#define DDRSS_PHY_736_DATA 0x00000000
+#define DDRSS_PHY_737_DATA 0x00000000
+#define DDRSS_PHY_738_DATA 0x00000000
+#define DDRSS_PHY_739_DATA 0x00000000
+#define DDRSS_PHY_740_DATA 0x00000000
+#define DDRSS_PHY_741_DATA 0x00000000
+#define DDRSS_PHY_742_DATA 0x00000000
+#define DDRSS_PHY_743_DATA 0x00000000
+#define DDRSS_PHY_744_DATA 0x00000000
+#define DDRSS_PHY_745_DATA 0x00000000
+#define DDRSS_PHY_746_DATA 0x00000000
+#define DDRSS_PHY_747_DATA 0x00000000
+#define DDRSS_PHY_748_DATA 0x00000000
+#define DDRSS_PHY_749_DATA 0x00000000
+#define DDRSS_PHY_750_DATA 0x00000000
+#define DDRSS_PHY_751_DATA 0x00000000
+#define DDRSS_PHY_752_DATA 0x00000000
+#define DDRSS_PHY_753_DATA 0x00000000
+#define DDRSS_PHY_754_DATA 0x00000000
+#define DDRSS_PHY_755_DATA 0x00000000
+#define DDRSS_PHY_756_DATA 0x00000000
+#define DDRSS_PHY_757_DATA 0x00000000
+#define DDRSS_PHY_758_DATA 0x00000000
+#define DDRSS_PHY_759_DATA 0x00000000
+#define DDRSS_PHY_760_DATA 0x00000000
+#define DDRSS_PHY_761_DATA 0x00000000
+#define DDRSS_PHY_762_DATA 0x00000000
+#define DDRSS_PHY_763_DATA 0x00000000
+#define DDRSS_PHY_764_DATA 0x00000000
+#define DDRSS_PHY_765_DATA 0x00000000
+#define DDRSS_PHY_766_DATA 0x00000000
+#define DDRSS_PHY_767_DATA 0x00000000
+#define DDRSS_PHY_768_DATA 0x00000100
+#define DDRSS_PHY_769_DATA 0x00000000
+#define DDRSS_PHY_770_DATA 0x00000000
+#define DDRSS_PHY_771_DATA 0x00000000
+#define DDRSS_PHY_772_DATA 0x00000000
+#define DDRSS_PHY_773_DATA 0x00000100
+#define DDRSS_PHY_774_DATA 0x00000000
+#define DDRSS_PHY_775_DATA 0x00000000
+#define DDRSS_PHY_776_DATA 0x00000000
+#define DDRSS_PHY_777_DATA 0x00000000
+#define DDRSS_PHY_778_DATA 0x00000000
+#define DDRSS_PHY_779_DATA 0x00000000
+#define DDRSS_PHY_780_DATA 0x00000000
+#define DDRSS_PHY_781_DATA 0x00DCBA98
+#define DDRSS_PHY_782_DATA 0x00000000
+#define DDRSS_PHY_783_DATA 0x00000000
+#define DDRSS_PHY_784_DATA 0x00000000
+#define DDRSS_PHY_785_DATA 0x00000000
+#define DDRSS_PHY_786_DATA 0x00000000
+#define DDRSS_PHY_787_DATA 0x00000000
+#define DDRSS_PHY_788_DATA 0x00000000
+#define DDRSS_PHY_789_DATA 0x00000000
+#define DDRSS_PHY_790_DATA 0x00000000
+#define DDRSS_PHY_791_DATA 0x00000000
+#define DDRSS_PHY_792_DATA 0x00000000
+#define DDRSS_PHY_793_DATA 0x00000000
+#define DDRSS_PHY_794_DATA 0x00000000
+#define DDRSS_PHY_795_DATA 0x00000000
+#define DDRSS_PHY_796_DATA 0x16A4A0E6
+#define DDRSS_PHY_797_DATA 0x103F0000
+#define DDRSS_PHY_798_DATA 0x000F0000
+#define DDRSS_PHY_799_DATA 0x0000000F
+#define DDRSS_PHY_800_DATA 0x020002CC
+#define DDRSS_PHY_801_DATA 0x00030000
+#define DDRSS_PHY_802_DATA 0x00000300
+#define DDRSS_PHY_803_DATA 0x00000300
+#define DDRSS_PHY_804_DATA 0x00000300
+#define DDRSS_PHY_805_DATA 0x00000300
+#define DDRSS_PHY_806_DATA 0x00000300
+#define DDRSS_PHY_807_DATA 0x42080010
+#define DDRSS_PHY_808_DATA 0x0000003E
+#define DDRSS_PHY_809_DATA 0x00000000
+#define DDRSS_PHY_810_DATA 0x00000000
+#define DDRSS_PHY_811_DATA 0x00000000
+#define DDRSS_PHY_812_DATA 0x00000000
+#define DDRSS_PHY_813_DATA 0x00000000
+#define DDRSS_PHY_814_DATA 0x00000000
+#define DDRSS_PHY_815_DATA 0x00000000
+#define DDRSS_PHY_816_DATA 0x00000000
+#define DDRSS_PHY_817_DATA 0x00000000
+#define DDRSS_PHY_818_DATA 0x00000000
+#define DDRSS_PHY_819_DATA 0x00000000
+#define DDRSS_PHY_820_DATA 0x00000000
+#define DDRSS_PHY_821_DATA 0x00000000
+#define DDRSS_PHY_822_DATA 0x00000000
+#define DDRSS_PHY_823_DATA 0x00000000
+#define DDRSS_PHY_824_DATA 0x00000000
+#define DDRSS_PHY_825_DATA 0x00000000
+#define DDRSS_PHY_826_DATA 0x00000000
+#define DDRSS_PHY_827_DATA 0x00000000
+#define DDRSS_PHY_828_DATA 0x00000000
+#define DDRSS_PHY_829_DATA 0x00000000
+#define DDRSS_PHY_830_DATA 0x00000000
+#define DDRSS_PHY_831_DATA 0x00000000
+#define DDRSS_PHY_832_DATA 0x00000000
+#define DDRSS_PHY_833_DATA 0x00000000
+#define DDRSS_PHY_834_DATA 0x00000000
+#define DDRSS_PHY_835_DATA 0x00000000
+#define DDRSS_PHY_836_DATA 0x00000000
+#define DDRSS_PHY_837_DATA 0x00000000
+#define DDRSS_PHY_838_DATA 0x00000000
+#define DDRSS_PHY_839_DATA 0x00000000
+#define DDRSS_PHY_840_DATA 0x00000000
+#define DDRSS_PHY_841_DATA 0x00000000
+#define DDRSS_PHY_842_DATA 0x00000000
+#define DDRSS_PHY_843_DATA 0x00000000
+#define DDRSS_PHY_844_DATA 0x00000000
+#define DDRSS_PHY_845_DATA 0x00000000
+#define DDRSS_PHY_846_DATA 0x00000000
+#define DDRSS_PHY_847_DATA 0x00000000
+#define DDRSS_PHY_848_DATA 0x00000000
+#define DDRSS_PHY_849_DATA 0x00000000
+#define DDRSS_PHY_850_DATA 0x00000000
+#define DDRSS_PHY_851_DATA 0x00000000
+#define DDRSS_PHY_852_DATA 0x00000000
+#define DDRSS_PHY_853_DATA 0x00000000
+#define DDRSS_PHY_854_DATA 0x00000000
+#define DDRSS_PHY_855_DATA 0x00000000
+#define DDRSS_PHY_856_DATA 0x00000000
+#define DDRSS_PHY_857_DATA 0x00000000
+#define DDRSS_PHY_858_DATA 0x00000000
+#define DDRSS_PHY_859_DATA 0x00000000
+#define DDRSS_PHY_860_DATA 0x00000000
+#define DDRSS_PHY_861_DATA 0x00000000
+#define DDRSS_PHY_862_DATA 0x00000000
+#define DDRSS_PHY_863_DATA 0x00000000
+#define DDRSS_PHY_864_DATA 0x00000000
+#define DDRSS_PHY_865_DATA 0x00000000
+#define DDRSS_PHY_866_DATA 0x00000000
+#define DDRSS_PHY_867_DATA 0x00000000
+#define DDRSS_PHY_868_DATA 0x00000000
+#define DDRSS_PHY_869_DATA 0x00000000
+#define DDRSS_PHY_870_DATA 0x00000000
+#define DDRSS_PHY_871_DATA 0x00000000
+#define DDRSS_PHY_872_DATA 0x00000000
+#define DDRSS_PHY_873_DATA 0x00000000
+#define DDRSS_PHY_874_DATA 0x00000000
+#define DDRSS_PHY_875_DATA 0x00000000
+#define DDRSS_PHY_876_DATA 0x00000000
+#define DDRSS_PHY_877_DATA 0x00000000
+#define DDRSS_PHY_878_DATA 0x00000000
+#define DDRSS_PHY_879_DATA 0x00000000
+#define DDRSS_PHY_880_DATA 0x00000000
+#define DDRSS_PHY_881_DATA 0x00000000
+#define DDRSS_PHY_882_DATA 0x00000000
+#define DDRSS_PHY_883_DATA 0x00000000
+#define DDRSS_PHY_884_DATA 0x00000000
+#define DDRSS_PHY_885_DATA 0x00000000
+#define DDRSS_PHY_886_DATA 0x00000000
+#define DDRSS_PHY_887_DATA 0x00000000
+#define DDRSS_PHY_888_DATA 0x00000000
+#define DDRSS_PHY_889_DATA 0x00000000
+#define DDRSS_PHY_890_DATA 0x00000000
+#define DDRSS_PHY_891_DATA 0x00000000
+#define DDRSS_PHY_892_DATA 0x00000000
+#define DDRSS_PHY_893_DATA 0x00000000
+#define DDRSS_PHY_894_DATA 0x00000000
+#define DDRSS_PHY_895_DATA 0x00000000
+#define DDRSS_PHY_896_DATA 0x00000000
+#define DDRSS_PHY_897_DATA 0x00000000
+#define DDRSS_PHY_898_DATA 0x00000000
+#define DDRSS_PHY_899_DATA 0x00000000
+#define DDRSS_PHY_900_DATA 0x00000000
+#define DDRSS_PHY_901_DATA 0x00000000
+#define DDRSS_PHY_902_DATA 0x00000000
+#define DDRSS_PHY_903_DATA 0x00000000
+#define DDRSS_PHY_904_DATA 0x00000000
+#define DDRSS_PHY_905_DATA 0x00000000
+#define DDRSS_PHY_906_DATA 0x00000000
+#define DDRSS_PHY_907_DATA 0x00000000
+#define DDRSS_PHY_908_DATA 0x00000000
+#define DDRSS_PHY_909_DATA 0x00000000
+#define DDRSS_PHY_910_DATA 0x00000000
+#define DDRSS_PHY_911_DATA 0x00000000
+#define DDRSS_PHY_912_DATA 0x00000000
+#define DDRSS_PHY_913_DATA 0x00000000
+#define DDRSS_PHY_914_DATA 0x00000000
+#define DDRSS_PHY_915_DATA 0x00000000
+#define DDRSS_PHY_916_DATA 0x00000000
+#define DDRSS_PHY_917_DATA 0x00000000
+#define DDRSS_PHY_918_DATA 0x00000000
+#define DDRSS_PHY_919_DATA 0x00000000
+#define DDRSS_PHY_920_DATA 0x00000000
+#define DDRSS_PHY_921_DATA 0x00000000
+#define DDRSS_PHY_922_DATA 0x00000000
+#define DDRSS_PHY_923_DATA 0x00000000
+#define DDRSS_PHY_924_DATA 0x00000000
+#define DDRSS_PHY_925_DATA 0x00000000
+#define DDRSS_PHY_926_DATA 0x00000000
+#define DDRSS_PHY_927_DATA 0x00000000
+#define DDRSS_PHY_928_DATA 0x00000000
+#define DDRSS_PHY_929_DATA 0x00000000
+#define DDRSS_PHY_930_DATA 0x00000000
+#define DDRSS_PHY_931_DATA 0x00000000
+#define DDRSS_PHY_932_DATA 0x00000000
+#define DDRSS_PHY_933_DATA 0x00000000
+#define DDRSS_PHY_934_DATA 0x00000000
+#define DDRSS_PHY_935_DATA 0x00000000
+#define DDRSS_PHY_936_DATA 0x00000000
+#define DDRSS_PHY_937_DATA 0x00000000
+#define DDRSS_PHY_938_DATA 0x00000000
+#define DDRSS_PHY_939_DATA 0x00000000
+#define DDRSS_PHY_940_DATA 0x00000000
+#define DDRSS_PHY_941_DATA 0x00000000
+#define DDRSS_PHY_942_DATA 0x00000000
+#define DDRSS_PHY_943_DATA 0x00000000
+#define DDRSS_PHY_944_DATA 0x00000000
+#define DDRSS_PHY_945_DATA 0x00000000
+#define DDRSS_PHY_946_DATA 0x00000000
+#define DDRSS_PHY_947_DATA 0x00000000
+#define DDRSS_PHY_948_DATA 0x00000000
+#define DDRSS_PHY_949_DATA 0x00000000
+#define DDRSS_PHY_950_DATA 0x00000000
+#define DDRSS_PHY_951_DATA 0x00000000
+#define DDRSS_PHY_952_DATA 0x00000000
+#define DDRSS_PHY_953_DATA 0x00000000
+#define DDRSS_PHY_954_DATA 0x00000000
+#define DDRSS_PHY_955_DATA 0x00000000
+#define DDRSS_PHY_956_DATA 0x00000000
+#define DDRSS_PHY_957_DATA 0x00000000
+#define DDRSS_PHY_958_DATA 0x00000000
+#define DDRSS_PHY_959_DATA 0x00000000
+#define DDRSS_PHY_960_DATA 0x00000000
+#define DDRSS_PHY_961_DATA 0x00000000
+#define DDRSS_PHY_962_DATA 0x00000000
+#define DDRSS_PHY_963_DATA 0x00000000
+#define DDRSS_PHY_964_DATA 0x00000000
+#define DDRSS_PHY_965_DATA 0x00000000
+#define DDRSS_PHY_966_DATA 0x00000000
+#define DDRSS_PHY_967_DATA 0x00000000
+#define DDRSS_PHY_968_DATA 0x00000000
+#define DDRSS_PHY_969_DATA 0x00000000
+#define DDRSS_PHY_970_DATA 0x00000000
+#define DDRSS_PHY_971_DATA 0x00000000
+#define DDRSS_PHY_972_DATA 0x00000000
+#define DDRSS_PHY_973_DATA 0x00000000
+#define DDRSS_PHY_974_DATA 0x00000000
+#define DDRSS_PHY_975_DATA 0x00000000
+#define DDRSS_PHY_976_DATA 0x00000000
+#define DDRSS_PHY_977_DATA 0x00000000
+#define DDRSS_PHY_978_DATA 0x00000000
+#define DDRSS_PHY_979_DATA 0x00000000
+#define DDRSS_PHY_980_DATA 0x00000000
+#define DDRSS_PHY_981_DATA 0x00000000
+#define DDRSS_PHY_982_DATA 0x00000000
+#define DDRSS_PHY_983_DATA 0x00000000
+#define DDRSS_PHY_984_DATA 0x00000000
+#define DDRSS_PHY_985_DATA 0x00000000
+#define DDRSS_PHY_986_DATA 0x00000000
+#define DDRSS_PHY_987_DATA 0x00000000
+#define DDRSS_PHY_988_DATA 0x00000000
+#define DDRSS_PHY_989_DATA 0x00000000
+#define DDRSS_PHY_990_DATA 0x00000000
+#define DDRSS_PHY_991_DATA 0x00000000
+#define DDRSS_PHY_992_DATA 0x00000000
+#define DDRSS_PHY_993_DATA 0x00000000
+#define DDRSS_PHY_994_DATA 0x00000000
+#define DDRSS_PHY_995_DATA 0x00000000
+#define DDRSS_PHY_996_DATA 0x00000000
+#define DDRSS_PHY_997_DATA 0x00000000
+#define DDRSS_PHY_998_DATA 0x00000000
+#define DDRSS_PHY_999_DATA 0x00000000
+#define DDRSS_PHY_1000_DATA 0x00000000
+#define DDRSS_PHY_1001_DATA 0x00000000
+#define DDRSS_PHY_1002_DATA 0x00000000
+#define DDRSS_PHY_1003_DATA 0x00000000
+#define DDRSS_PHY_1004_DATA 0x00000000
+#define DDRSS_PHY_1005_DATA 0x00000000
+#define DDRSS_PHY_1006_DATA 0x00000000
+#define DDRSS_PHY_1007_DATA 0x00000000
+#define DDRSS_PHY_1008_DATA 0x00000000
+#define DDRSS_PHY_1009_DATA 0x00000000
+#define DDRSS_PHY_1010_DATA 0x00000000
+#define DDRSS_PHY_1011_DATA 0x00000000
+#define DDRSS_PHY_1012_DATA 0x00000000
+#define DDRSS_PHY_1013_DATA 0x00000000
+#define DDRSS_PHY_1014_DATA 0x00000000
+#define DDRSS_PHY_1015_DATA 0x00000000
+#define DDRSS_PHY_1016_DATA 0x00000000
+#define DDRSS_PHY_1017_DATA 0x00000000
+#define DDRSS_PHY_1018_DATA 0x00000000
+#define DDRSS_PHY_1019_DATA 0x00000000
+#define DDRSS_PHY_1020_DATA 0x00000000
+#define DDRSS_PHY_1021_DATA 0x00000000
+#define DDRSS_PHY_1022_DATA 0x00000000
+#define DDRSS_PHY_1023_DATA 0x00000000
+#define DDRSS_PHY_1024_DATA 0x00000100
+#define DDRSS_PHY_1025_DATA 0x00000000
+#define DDRSS_PHY_1026_DATA 0x00000000
+#define DDRSS_PHY_1027_DATA 0x00000000
+#define DDRSS_PHY_1028_DATA 0x00000000
+#define DDRSS_PHY_1029_DATA 0x00000100
+#define DDRSS_PHY_1030_DATA 0x00000000
+#define DDRSS_PHY_1031_DATA 0x00000000
+#define DDRSS_PHY_1032_DATA 0x00000000
+#define DDRSS_PHY_1033_DATA 0x00000000
+#define DDRSS_PHY_1034_DATA 0x00000000
+#define DDRSS_PHY_1035_DATA 0x00000000
+#define DDRSS_PHY_1036_DATA 0x00000000
+#define DDRSS_PHY_1037_DATA 0x00DCBA98
+#define DDRSS_PHY_1038_DATA 0x00000000
+#define DDRSS_PHY_1039_DATA 0x00000000
+#define DDRSS_PHY_1040_DATA 0x00000000
+#define DDRSS_PHY_1041_DATA 0x00000000
+#define DDRSS_PHY_1042_DATA 0x00000000
+#define DDRSS_PHY_1043_DATA 0x00000000
+#define DDRSS_PHY_1044_DATA 0x00000000
+#define DDRSS_PHY_1045_DATA 0x00000000
+#define DDRSS_PHY_1046_DATA 0x00000000
+#define DDRSS_PHY_1047_DATA 0x00000000
+#define DDRSS_PHY_1048_DATA 0x00000000
+#define DDRSS_PHY_1049_DATA 0x00000000
+#define DDRSS_PHY_1050_DATA 0x00000000
+#define DDRSS_PHY_1051_DATA 0x00000000
+#define DDRSS_PHY_1052_DATA 0x2307B9AC
+#define DDRSS_PHY_1053_DATA 0x10030000
+#define DDRSS_PHY_1054_DATA 0x000F0000
+#define DDRSS_PHY_1055_DATA 0x0000000F
+#define DDRSS_PHY_1056_DATA 0x020002CC
+#define DDRSS_PHY_1057_DATA 0x00030000
+#define DDRSS_PHY_1058_DATA 0x00000300
+#define DDRSS_PHY_1059_DATA 0x00000300
+#define DDRSS_PHY_1060_DATA 0x00000300
+#define DDRSS_PHY_1061_DATA 0x00000300
+#define DDRSS_PHY_1062_DATA 0x00000300
+#define DDRSS_PHY_1063_DATA 0x42080010
+#define DDRSS_PHY_1064_DATA 0x0000003E
+#define DDRSS_PHY_1065_DATA 0x00000000
+#define DDRSS_PHY_1066_DATA 0x00000000
+#define DDRSS_PHY_1067_DATA 0x00000000
+#define DDRSS_PHY_1068_DATA 0x00000000
+#define DDRSS_PHY_1069_DATA 0x00000000
+#define DDRSS_PHY_1070_DATA 0x00000000
+#define DDRSS_PHY_1071_DATA 0x00000000
+#define DDRSS_PHY_1072_DATA 0x00000000
+#define DDRSS_PHY_1073_DATA 0x00000000
+#define DDRSS_PHY_1074_DATA 0x00000000
+#define DDRSS_PHY_1075_DATA 0x00000000
+#define DDRSS_PHY_1076_DATA 0x00000000
+#define DDRSS_PHY_1077_DATA 0x00000000
+#define DDRSS_PHY_1078_DATA 0x00000000
+#define DDRSS_PHY_1079_DATA 0x00000000
+#define DDRSS_PHY_1080_DATA 0x00000000
+#define DDRSS_PHY_1081_DATA 0x00000000
+#define DDRSS_PHY_1082_DATA 0x00000000
+#define DDRSS_PHY_1083_DATA 0x00000000
+#define DDRSS_PHY_1084_DATA 0x00000000
+#define DDRSS_PHY_1085_DATA 0x00000000
+#define DDRSS_PHY_1086_DATA 0x00000000
+#define DDRSS_PHY_1087_DATA 0x00000000
+#define DDRSS_PHY_1088_DATA 0x00000000
+#define DDRSS_PHY_1089_DATA 0x00000000
+#define DDRSS_PHY_1090_DATA 0x00000000
+#define DDRSS_PHY_1091_DATA 0x00000000
+#define DDRSS_PHY_1092_DATA 0x00000000
+#define DDRSS_PHY_1093_DATA 0x00000000
+#define DDRSS_PHY_1094_DATA 0x00000000
+#define DDRSS_PHY_1095_DATA 0x00000000
+#define DDRSS_PHY_1096_DATA 0x00000000
+#define DDRSS_PHY_1097_DATA 0x00000000
+#define DDRSS_PHY_1098_DATA 0x00000000
+#define DDRSS_PHY_1099_DATA 0x00000000
+#define DDRSS_PHY_1100_DATA 0x00000000
+#define DDRSS_PHY_1101_DATA 0x00000000
+#define DDRSS_PHY_1102_DATA 0x00000000
+#define DDRSS_PHY_1103_DATA 0x00000000
+#define DDRSS_PHY_1104_DATA 0x00000000
+#define DDRSS_PHY_1105_DATA 0x00000000
+#define DDRSS_PHY_1106_DATA 0x00000000
+#define DDRSS_PHY_1107_DATA 0x00000000
+#define DDRSS_PHY_1108_DATA 0x00000000
+#define DDRSS_PHY_1109_DATA 0x00000000
+#define DDRSS_PHY_1110_DATA 0x00000000
+#define DDRSS_PHY_1111_DATA 0x00000000
+#define DDRSS_PHY_1112_DATA 0x00000000
+#define DDRSS_PHY_1113_DATA 0x00000000
+#define DDRSS_PHY_1114_DATA 0x00000000
+#define DDRSS_PHY_1115_DATA 0x00000000
+#define DDRSS_PHY_1116_DATA 0x00000000
+#define DDRSS_PHY_1117_DATA 0x00000000
+#define DDRSS_PHY_1118_DATA 0x00000000
+#define DDRSS_PHY_1119_DATA 0x00000000
+#define DDRSS_PHY_1120_DATA 0x00000000
+#define DDRSS_PHY_1121_DATA 0x00000000
+#define DDRSS_PHY_1122_DATA 0x00000000
+#define DDRSS_PHY_1123_DATA 0x00000000
+#define DDRSS_PHY_1124_DATA 0x00000000
+#define DDRSS_PHY_1125_DATA 0x00000000
+#define DDRSS_PHY_1126_DATA 0x00000000
+#define DDRSS_PHY_1127_DATA 0x00000000
+#define DDRSS_PHY_1128_DATA 0x00000000
+#define DDRSS_PHY_1129_DATA 0x00000000
+#define DDRSS_PHY_1130_DATA 0x00000000
+#define DDRSS_PHY_1131_DATA 0x00000000
+#define DDRSS_PHY_1132_DATA 0x00000000
+#define DDRSS_PHY_1133_DATA 0x00000000
+#define DDRSS_PHY_1134_DATA 0x00000000
+#define DDRSS_PHY_1135_DATA 0x00000000
+#define DDRSS_PHY_1136_DATA 0x00000000
+#define DDRSS_PHY_1137_DATA 0x00000000
+#define DDRSS_PHY_1138_DATA 0x00000000
+#define DDRSS_PHY_1139_DATA 0x00000000
+#define DDRSS_PHY_1140_DATA 0x00000000
+#define DDRSS_PHY_1141_DATA 0x00000000
+#define DDRSS_PHY_1142_DATA 0x00000000
+#define DDRSS_PHY_1143_DATA 0x00000000
+#define DDRSS_PHY_1144_DATA 0x00000000
+#define DDRSS_PHY_1145_DATA 0x00000000
+#define DDRSS_PHY_1146_DATA 0x00000000
+#define DDRSS_PHY_1147_DATA 0x00000000
+#define DDRSS_PHY_1148_DATA 0x00000000
+#define DDRSS_PHY_1149_DATA 0x00000000
+#define DDRSS_PHY_1150_DATA 0x00000000
+#define DDRSS_PHY_1151_DATA 0x00000000
+#define DDRSS_PHY_1152_DATA 0x00000000
+#define DDRSS_PHY_1153_DATA 0x00000000
+#define DDRSS_PHY_1154_DATA 0x00000000
+#define DDRSS_PHY_1155_DATA 0x00000000
+#define DDRSS_PHY_1156_DATA 0x00000000
+#define DDRSS_PHY_1157_DATA 0x00000000
+#define DDRSS_PHY_1158_DATA 0x00000000
+#define DDRSS_PHY_1159_DATA 0x00000000
+#define DDRSS_PHY_1160_DATA 0x00000000
+#define DDRSS_PHY_1161_DATA 0x00000000
+#define DDRSS_PHY_1162_DATA 0x00000000
+#define DDRSS_PHY_1163_DATA 0x00000000
+#define DDRSS_PHY_1164_DATA 0x00000000
+#define DDRSS_PHY_1165_DATA 0x00000000
+#define DDRSS_PHY_1166_DATA 0x00000000
+#define DDRSS_PHY_1167_DATA 0x00000000
+#define DDRSS_PHY_1168_DATA 0x00000000
+#define DDRSS_PHY_1169_DATA 0x00000000
+#define DDRSS_PHY_1170_DATA 0x00000000
+#define DDRSS_PHY_1171_DATA 0x00000000
+#define DDRSS_PHY_1172_DATA 0x00000000
+#define DDRSS_PHY_1173_DATA 0x00000000
+#define DDRSS_PHY_1174_DATA 0x00000000
+#define DDRSS_PHY_1175_DATA 0x00000000
+#define DDRSS_PHY_1176_DATA 0x00000000
+#define DDRSS_PHY_1177_DATA 0x00000000
+#define DDRSS_PHY_1178_DATA 0x00000000
+#define DDRSS_PHY_1179_DATA 0x00000000
+#define DDRSS_PHY_1180_DATA 0x00000000
+#define DDRSS_PHY_1181_DATA 0x00000000
+#define DDRSS_PHY_1182_DATA 0x00000000
+#define DDRSS_PHY_1183_DATA 0x00000000
+#define DDRSS_PHY_1184_DATA 0x00000000
+#define DDRSS_PHY_1185_DATA 0x00000000
+#define DDRSS_PHY_1186_DATA 0x00000000
+#define DDRSS_PHY_1187_DATA 0x00000000
+#define DDRSS_PHY_1188_DATA 0x00000000
+#define DDRSS_PHY_1189_DATA 0x00000000
+#define DDRSS_PHY_1190_DATA 0x00000000
+#define DDRSS_PHY_1191_DATA 0x00000000
+#define DDRSS_PHY_1192_DATA 0x00000000
+#define DDRSS_PHY_1193_DATA 0x00000000
+#define DDRSS_PHY_1194_DATA 0x00000000
+#define DDRSS_PHY_1195_DATA 0x00000000
+#define DDRSS_PHY_1196_DATA 0x00000000
+#define DDRSS_PHY_1197_DATA 0x00000000
+#define DDRSS_PHY_1198_DATA 0x00000000
+#define DDRSS_PHY_1199_DATA 0x00000000
+#define DDRSS_PHY_1200_DATA 0x00000000
+#define DDRSS_PHY_1201_DATA 0x00000000
+#define DDRSS_PHY_1202_DATA 0x00000000
+#define DDRSS_PHY_1203_DATA 0x00000000
+#define DDRSS_PHY_1204_DATA 0x00000000
+#define DDRSS_PHY_1205_DATA 0x00000000
+#define DDRSS_PHY_1206_DATA 0x00000000
+#define DDRSS_PHY_1207_DATA 0x00000000
+#define DDRSS_PHY_1208_DATA 0x00000000
+#define DDRSS_PHY_1209_DATA 0x00000000
+#define DDRSS_PHY_1210_DATA 0x00000000
+#define DDRSS_PHY_1211_DATA 0x00000000
+#define DDRSS_PHY_1212_DATA 0x00000000
+#define DDRSS_PHY_1213_DATA 0x00000000
+#define DDRSS_PHY_1214_DATA 0x00000000
+#define DDRSS_PHY_1215_DATA 0x00000000
+#define DDRSS_PHY_1216_DATA 0x00000000
+#define DDRSS_PHY_1217_DATA 0x00000000
+#define DDRSS_PHY_1218_DATA 0x00000000
+#define DDRSS_PHY_1219_DATA 0x00000000
+#define DDRSS_PHY_1220_DATA 0x00000000
+#define DDRSS_PHY_1221_DATA 0x00000000
+#define DDRSS_PHY_1222_DATA 0x00000000
+#define DDRSS_PHY_1223_DATA 0x00000000
+#define DDRSS_PHY_1224_DATA 0x00000000
+#define DDRSS_PHY_1225_DATA 0x00000000
+#define DDRSS_PHY_1226_DATA 0x00000000
+#define DDRSS_PHY_1227_DATA 0x00000000
+#define DDRSS_PHY_1228_DATA 0x00000000
+#define DDRSS_PHY_1229_DATA 0x00000000
+#define DDRSS_PHY_1230_DATA 0x00000000
+#define DDRSS_PHY_1231_DATA 0x00000000
+#define DDRSS_PHY_1232_DATA 0x00000000
+#define DDRSS_PHY_1233_DATA 0x00000000
+#define DDRSS_PHY_1234_DATA 0x00000000
+#define DDRSS_PHY_1235_DATA 0x00000000
+#define DDRSS_PHY_1236_DATA 0x00000000
+#define DDRSS_PHY_1237_DATA 0x00000000
+#define DDRSS_PHY_1238_DATA 0x00000000
+#define DDRSS_PHY_1239_DATA 0x00000000
+#define DDRSS_PHY_1240_DATA 0x00000000
+#define DDRSS_PHY_1241_DATA 0x00000000
+#define DDRSS_PHY_1242_DATA 0x00000000
+#define DDRSS_PHY_1243_DATA 0x00000000
+#define DDRSS_PHY_1244_DATA 0x00000000
+#define DDRSS_PHY_1245_DATA 0x00000000
+#define DDRSS_PHY_1246_DATA 0x00000000
+#define DDRSS_PHY_1247_DATA 0x00000000
+#define DDRSS_PHY_1248_DATA 0x00000000
+#define DDRSS_PHY_1249_DATA 0x00000000
+#define DDRSS_PHY_1250_DATA 0x00000000
+#define DDRSS_PHY_1251_DATA 0x00000000
+#define DDRSS_PHY_1252_DATA 0x00000000
+#define DDRSS_PHY_1253_DATA 0x00000000
+#define DDRSS_PHY_1254_DATA 0x00000000
+#define DDRSS_PHY_1255_DATA 0x00000000
+#define DDRSS_PHY_1256_DATA 0x00000000
+#define DDRSS_PHY_1257_DATA 0x00000000
+#define DDRSS_PHY_1258_DATA 0x00000000
+#define DDRSS_PHY_1259_DATA 0x00000000
+#define DDRSS_PHY_1260_DATA 0x00000000
+#define DDRSS_PHY_1261_DATA 0x00000000
+#define DDRSS_PHY_1262_DATA 0x00000000
+#define DDRSS_PHY_1263_DATA 0x00000000
+#define DDRSS_PHY_1264_DATA 0x00000000
+#define DDRSS_PHY_1265_DATA 0x00000000
+#define DDRSS_PHY_1266_DATA 0x00000000
+#define DDRSS_PHY_1267_DATA 0x00000000
+#define DDRSS_PHY_1268_DATA 0x00000000
+#define DDRSS_PHY_1269_DATA 0x00000000
+#define DDRSS_PHY_1270_DATA 0x00000000
+#define DDRSS_PHY_1271_DATA 0x00000000
+#define DDRSS_PHY_1272_DATA 0x00000000
+#define DDRSS_PHY_1273_DATA 0x00000000
+#define DDRSS_PHY_1274_DATA 0x00000000
+#define DDRSS_PHY_1275_DATA 0x00000000
+#define DDRSS_PHY_1276_DATA 0x00000000
+#define DDRSS_PHY_1277_DATA 0x00000000
+#define DDRSS_PHY_1278_DATA 0x00000000
+#define DDRSS_PHY_1279_DATA 0x00000000
+#define DDRSS_PHY_1280_DATA 0x00000000
+#define DDRSS_PHY_1281_DATA 0x00000100
+#define DDRSS_PHY_1282_DATA 0x00000000
+#define DDRSS_PHY_1283_DATA 0x00000000
+#define DDRSS_PHY_1284_DATA 0x00000000
+#define DDRSS_PHY_1285_DATA 0x00000000
+#define DDRSS_PHY_1286_DATA 0x00050000
+#define DDRSS_PHY_1287_DATA 0x04000100
+#define DDRSS_PHY_1288_DATA 0x00000055
+#define DDRSS_PHY_1289_DATA 0x00000000
+#define DDRSS_PHY_1290_DATA 0x00000000
+#define DDRSS_PHY_1291_DATA 0x00000000
+#define DDRSS_PHY_1292_DATA 0x00000000
+#define DDRSS_PHY_1293_DATA 0x01002000
+#define DDRSS_PHY_1294_DATA 0x00004001
+#define DDRSS_PHY_1295_DATA 0x00020028
+#define DDRSS_PHY_1296_DATA 0x00010100
+#define DDRSS_PHY_1297_DATA 0x00000001
+#define DDRSS_PHY_1298_DATA 0x00000000
+#define DDRSS_PHY_1299_DATA 0x0F0F0E06
+#define DDRSS_PHY_1300_DATA 0x00010101
+#define DDRSS_PHY_1301_DATA 0x010F0004
+#define DDRSS_PHY_1302_DATA 0x00000000
+#define DDRSS_PHY_1303_DATA 0x00000000
+#define DDRSS_PHY_1304_DATA 0x00000064
+#define DDRSS_PHY_1305_DATA 0x00000000
+#define DDRSS_PHY_1306_DATA 0x00000000
+#define DDRSS_PHY_1307_DATA 0x01020103
+#define DDRSS_PHY_1308_DATA 0x0F020102
+#define DDRSS_PHY_1309_DATA 0x03030303
+#define DDRSS_PHY_1310_DATA 0x03030303
+#define DDRSS_PHY_1311_DATA 0x00040000
+#define DDRSS_PHY_1312_DATA 0x00004201
+#define DDRSS_PHY_1313_DATA 0x00000000
+#define DDRSS_PHY_1314_DATA 0x00000000
+#define DDRSS_PHY_1315_DATA 0x00000000
+#define DDRSS_PHY_1316_DATA 0x00000000
+#define DDRSS_PHY_1317_DATA 0x00000000
+#define DDRSS_PHY_1318_DATA 0x00000000
+#define DDRSS_PHY_1319_DATA 0x07070001
+#define DDRSS_PHY_1320_DATA 0x00005400
+#define DDRSS_PHY_1321_DATA 0x000040A2
+#define DDRSS_PHY_1322_DATA 0x00024410
+#define DDRSS_PHY_1323_DATA 0x00004410
+#define DDRSS_PHY_1324_DATA 0x00004410
+#define DDRSS_PHY_1325_DATA 0x00004410
+#define DDRSS_PHY_1326_DATA 0x00004410
+#define DDRSS_PHY_1327_DATA 0x00004410
+#define DDRSS_PHY_1328_DATA 0x00004410
+#define DDRSS_PHY_1329_DATA 0x00004410
+#define DDRSS_PHY_1330_DATA 0x00004410
+#define DDRSS_PHY_1331_DATA 0x00004410
+#define DDRSS_PHY_1332_DATA 0x00000000
+#define DDRSS_PHY_1333_DATA 0x00000046
+#define DDRSS_PHY_1334_DATA 0x00000400
+#define DDRSS_PHY_1335_DATA 0x00000008
+#define DDRSS_PHY_1336_DATA 0x00000000
+#define DDRSS_PHY_1337_DATA 0x00000000
+#define DDRSS_PHY_1338_DATA 0x00000000
+#define DDRSS_PHY_1339_DATA 0x00000000
+#define DDRSS_PHY_1340_DATA 0x00000000
+#define DDRSS_PHY_1341_DATA 0x03000000
+#define DDRSS_PHY_1342_DATA 0x00000000
+#define DDRSS_PHY_1343_DATA 0x00000000
+#define DDRSS_PHY_1344_DATA 0x00000000
+#define DDRSS_PHY_1345_DATA 0x04102006
+#define DDRSS_PHY_1346_DATA 0x00041020
+#define DDRSS_PHY_1347_DATA 0x01C98C98
+#define DDRSS_PHY_1348_DATA 0x3F400000
+#define DDRSS_PHY_1349_DATA 0x3F3F1F3F
+#define DDRSS_PHY_1350_DATA 0x0000001F
+#define DDRSS_PHY_1351_DATA 0x00000000
+#define DDRSS_PHY_1352_DATA 0x00000000
+#define DDRSS_PHY_1353_DATA 0x00000000
+#define DDRSS_PHY_1354_DATA 0x00000001
+#define DDRSS_PHY_1355_DATA 0x00000000
+#define DDRSS_PHY_1356_DATA 0x00000000
+#define DDRSS_PHY_1357_DATA 0x00000000
+#define DDRSS_PHY_1358_DATA 0x00000000
+#define DDRSS_PHY_1359_DATA 0x76543210
+#define DDRSS_PHY_1360_DATA 0x00000098
+#define DDRSS_PHY_1361_DATA 0x00000000
+#define DDRSS_PHY_1362_DATA 0x00000000
+#define DDRSS_PHY_1363_DATA 0x00000000
+#define DDRSS_PHY_1364_DATA 0x00040700
+#define DDRSS_PHY_1365_DATA 0x00000000
+#define DDRSS_PHY_1366_DATA 0x00000000
+#define DDRSS_PHY_1367_DATA 0x00000000
+#define DDRSS_PHY_1368_DATA 0x00000002
+#define DDRSS_PHY_1369_DATA 0x00000100
+#define DDRSS_PHY_1370_DATA 0x00000000
+#define DDRSS_PHY_1371_DATA 0x00000FC3
+#define DDRSS_PHY_1372_DATA 0x00020002
+#define DDRSS_PHY_1373_DATA 0x00000000
+#define DDRSS_PHY_1374_DATA 0x00001142
+#define DDRSS_PHY_1375_DATA 0x03020400
+#define DDRSS_PHY_1376_DATA 0x00000080
+#define DDRSS_PHY_1377_DATA 0x03900390
+#define DDRSS_PHY_1378_DATA 0x03900390
+#define DDRSS_PHY_1379_DATA 0x03900390
+#define DDRSS_PHY_1380_DATA 0x03900390
+#define DDRSS_PHY_1381_DATA 0x03900390
+#define DDRSS_PHY_1382_DATA 0x03900390
+#define DDRSS_PHY_1383_DATA 0x00000300
+#define DDRSS_PHY_1384_DATA 0x00000300
+#define DDRSS_PHY_1385_DATA 0x00000300
+#define DDRSS_PHY_1386_DATA 0x00000300
+#define DDRSS_PHY_1387_DATA 0x31823FC7
+#define DDRSS_PHY_1388_DATA 0x00000000
+#define DDRSS_PHY_1389_DATA 0x0C000D3F
+#define DDRSS_PHY_1390_DATA 0x30000D3F
+#define DDRSS_PHY_1391_DATA 0x300D3F11
+#define DDRSS_PHY_1392_DATA 0x01990000
+#define DDRSS_PHY_1393_DATA 0x000D3FCC
+#define DDRSS_PHY_1394_DATA 0x00000C11
+#define DDRSS_PHY_1395_DATA 0x300D3F11
+#define DDRSS_PHY_1396_DATA 0x01990000
+#define DDRSS_PHY_1397_DATA 0x300C3F11
+#define DDRSS_PHY_1398_DATA 0x01990000
+#define DDRSS_PHY_1399_DATA 0x300C3F11
+#define DDRSS_PHY_1400_DATA 0x01990000
+#define DDRSS_PHY_1401_DATA 0x300D3F11
+#define DDRSS_PHY_1402_DATA 0x01990000
+#define DDRSS_PHY_1403_DATA 0x300D3F11
+#define DDRSS_PHY_1404_DATA 0x01990000
+#define DDRSS_PHY_1405_DATA 0x20040004
diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
new file mode 100644
index 0000000..d6c6baa
--- /dev/null
+++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * https://beagleboard.org/play
+ *
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
+ */
+
+#include "k3-am625-sk-binman.dtsi"
+
+/ {
+ chosen {
+ tick-timer = &main_timer0;
+ };
+
+ memory@80000000 {
+ bootph-all;
+ };
+
+ /* Keep the LEDs on by default to indicate life */
+ leds {
+ bootph-all;
+ led-0 {
+ default-state = "on";
+ bootph-all;
+ };
+
+ led-1 {
+ default-state = "on";
+ bootph-all;
+ };
+
+ led-2 {
+ default-state = "on";
+ bootph-all;
+ };
+
+ led-3 {
+ default-state = "on";
+ bootph-all;
+ };
+
+ led-4 {
+ default-state = "on";
+ bootph-all;
+ };
+ };
+};
+
+&cbass_main {
+ bootph-all;
+};
+
+&main_timer0 {
+ clock-frequency = <25000000>;
+ bootph-all;
+};
+
+&dmss {
+ bootph-all;
+};
+
+&secure_proxy_main {
+ bootph-all;
+};
+
+&dmsc {
+ bootph-all;
+};
+
+&k3_pds {
+ bootph-all;
+};
+
+&k3_clks {
+ bootph-all;
+};
+
+&k3_reset {
+ bootph-all;
+};
+
+&dmsc {
+ bootph-all;
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ bootph-all;
+ };
+};
+
+&wkup_conf {
+ bootph-all;
+};
+
+&chipid {
+ bootph-all;
+};
+
+&main_pmx0 {
+ bootph-all;
+};
+
+&main_uart0 {
+ bootph-all;
+};
+
+&console_pins_default {
+ bootph-all;
+};
+
+&cbass_mcu {
+ bootph-all;
+};
+
+&cbass_wakeup {
+ bootph-all;
+};
+
+&mcu_pmx0 {
+ bootph-all;
+};
+
+&main_i2c0 {
+ bootph-all;
+};
+
+&local_i2c_pins_default {
+ bootph-all;
+};
+
+&gpio0_pins_default {
+ bootph-all;
+};
+
+&main_gpio0 {
+ bootph-all;
+};
+
+&main_gpio1 {
+ bootph-all;
+};
+
+&sdhci0 {
+ /* EMMC */
+ bootph-all;
+};
+
+&emmc_pins_default {
+ bootph-all;
+};
+
+&sd_pins_default {
+ bootph-all;
+ /* Force to use SDCD card detect pin */
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
+ AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
+ AM62X_IOPAD(0x0230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
+ AM62X_IOPAD(0x022c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
+ AM62X_IOPAD(0x0228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
+ AM62X_IOPAD(0x0224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
+ AM62X_IOPAD(0x0240, PIN_INPUT, 0) /* (D17) MMC1_SDCD.MMC1_SDCD */
+ >;
+};
+
+&tps65219 {
+ bootph-all;
+};
+
+&sdhci1 {
+ bootph-all;
+};
+
+#ifdef CONFIG_TARGET_AM625_A53_EVM
+
+#define SPL_AM625_BEAGLEPLAY_DTB "spl/dts/k3-am625-beagleplay.dtb"
+#define AM625_BEAGLEPLAY_DTB "arch/arm/dts/k3-am625-beagleplay.dtb"
+
+&spl_am625_sk_dtb {
+ filename = SPL_AM625_BEAGLEPLAY_DTB;
+};
+
+&am625_sk_dtb {
+ filename = AM625_BEAGLEPLAY_DTB;
+};
+
+&spl_am625_sk_dtb_unsigned {
+ filename = SPL_AM625_BEAGLEPLAY_DTB;
+};
+
+&am625_sk_dtb_unsigned {
+ filename = AM625_BEAGLEPLAY_DTB;
+};
+
+#endif
diff --git a/arch/arm/dts/k3-am625-beagleplay.dts b/arch/arm/dts/k3-am625-beagleplay.dts
new file mode 100644
index 0000000..7cfdf56
--- /dev/null
+++ b/arch/arm/dts/k3-am625-beagleplay.dts
@@ -0,0 +1,908 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * https://beagleplay.org/
+ *
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "k3-am625.dtsi"
+
+/ {
+ compatible = "beagle,am625-beagleplay", "ti,am625";
+ model = "BeagleBoard.org BeaglePlay";
+
+ aliases {
+ ethernet0 = &cpsw_port1;
+ ethernet1 = &cpsw_port2;
+ gpio0 = &main_gpio0;
+ gpio1 = &main_gpio1;
+ gpio2 = &mcu_gpio0;
+ i2c0 = &main_i2c0;
+ i2c1 = &main_i2c1;
+ i2c2 = &main_i2c2;
+ i2c3 = &main_i2c3;
+ i2c4 = &wkup_i2c0;
+ i2c5 = &mcu_i2c0;
+ mdio-gpio0 = &mdio0;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ mmc2 = &sdhci2;
+ rtc0 = &rtc;
+ serial0 = &main_uart5;
+ serial1 = &main_uart6;
+ serial2 = &main_uart0;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* 2G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ramoops: ramoops@9ca00000 {
+ compatible = "ramoops";
+ reg = <0x00 0x9c700000 0x00 0x00100000>;
+ record-size = <0x8000>;
+ console-size = <0x8000>;
+ ftrace-size = <0x00>;
+ pmsg-size = <0x8000>;
+ };
+
+ secure_tfa_ddr: tfa@9e780000 {
+ reg = <0x00 0x9e780000 0x00 0x80000>;
+ no-map;
+ };
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>;
+ no-map;
+ };
+
+ wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9db00000 0x00 0xc00000>;
+ no-map;
+ };
+ };
+
+ vsys_5v0: regulator-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_3v3: regulator-2 {
+ /* output of TLV62595DMQR-U12 */
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vsys_5v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ wlan_en: regulator-3 {
+ /* OUTPUT of SN74AVC2T244DQMR */
+ compatible = "regulator-fixed";
+ regulator-name = "wlan_en";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ enable-active-high;
+ regulator-always-on;
+ vin-supply = <&vdd_3v3>;
+ gpio = <&main_gpio0 38 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_en_pins_default>;
+ };
+
+ vdd_3v3_sd: regulator-4 {
+ /* output of TPS22918DBVR-U21 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_3v3_sd_pins_default>;
+
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ regulator-always-on;
+ vin-supply = <&vdd_3v3>;
+ gpio = <&main_gpio1 19 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_sd_dv: regulator-5 {
+ compatible = "regulator-gpio";
+ regulator-name = "sd_hs200_switch";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_sd_dv_pins_default>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ vin-supply = <&ldo1_reg>;
+ gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ function = LED_FUNCTION_HEARTBEAT;
+ default-state = "off";
+ };
+
+ led-1 {
+ gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "disk-activity";
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ default-state = "keep";
+ };
+
+ led-2 {
+ gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_CPU;
+ };
+
+ led-3 {
+ gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_LAN;
+ };
+
+ led-4 {
+ gpios = <&main_gpio0 9 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_WLAN;
+ };
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usr_button_pins_default>;
+
+ usr: button-usr {
+ label = "User Key";
+ linux,code = <BTN_0>;
+ gpios = <&main_gpio0 18 GPIO_ACTIVE_LOW>;
+ };
+
+ };
+
+ hdmi0: connector-hdmi {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&it66121_out>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "it66121 HDMI";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&hdmi_dailink_master>;
+ simple-audio-card,frame-master = <&hdmi_dailink_master>;
+
+ hdmi_dailink_master: simple-audio-card,cpu {
+ sound-dai = <&mcasp1>;
+ system-clock-direction-out;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&it66121>;
+ };
+ };
+
+ /* Workaround for errata i2329 - just use mdio bitbang */
+ mdio0: mdio {
+ compatible = "virtual,mdio-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio0_pins_default>;
+ gpios = <&main_gpio0 86 GPIO_ACTIVE_HIGH>, /* MDC */
+ <&main_gpio0 85 GPIO_ACTIVE_HIGH>; /* MDIO */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw3g_phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ cpsw3g_phy1: ethernet-phy@1 {
+ reg = <1>;
+ reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <25>;
+ reset-deassert-us = <60000>; /* T2 */
+ };
+ };
+};
+
+&main_pmx0 {
+ gpio0_pins_default: gpio0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0004, PIN_INPUT, 7) /* (G25) OSPI0_LBCLKO.GPIO0_1 */
+ AM62X_IOPAD(0x0008, PIN_INPUT, 7) /* (J24) OSPI0_DQS.GPIO0_2 */
+ AM62X_IOPAD(0x000c, PIN_INPUT, 7) /* (E25) OSPI0_D0.GPIO0_3 */
+ AM62X_IOPAD(0x0010, PIN_INPUT, 7) /* (G24) OSPI0_D1.GPIO0_4 */
+ AM62X_IOPAD(0x0014, PIN_INPUT, 7) /* (F25) OSPI0_D2.GPIO0_5 */
+ AM62X_IOPAD(0x0018, PIN_INPUT, 7) /* (F24) OSPI0_D3.GPIO0_6 */
+ AM62X_IOPAD(0x0024, PIN_INPUT, 7) /* (H25) OSPI0_D6.GPIO0_9 */
+ AM62X_IOPAD(0x0028, PIN_INPUT, 7) /* (J22) OSPI0_D7.GPIO0_10 */
+ AM62X_IOPAD(0x002c, PIN_INPUT, 7) /* (F23) OSPI0_CSn0.GPIO0_11 */
+ AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 */
+ AM62X_IOPAD(0x0034, PIN_INPUT, 7) /* (H21) OSPI0_CSn2.GPIO0_13 */
+ AM62X_IOPAD(0x0038, PIN_INPUT, 7) /* (E24) OSPI0_CSn3.GPIO0_14 */
+ AM62X_IOPAD(0x00a4, PIN_INPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */
+ AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */
+ >;
+ };
+
+ vdd_sd_dv_pins_default: vdd-sd-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
+ >;
+ };
+
+ usr_button_pins_default: usr-button-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0048, PIN_INPUT, 7) /* (N25) GPMC0_AD3.GPIO0_18 */
+ >;
+ };
+
+ grove_pins_default: grove-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
+ AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
+ >;
+ };
+
+ local_i2c_pins_default: local-i2c-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
+ AM62X_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
+ >;
+ };
+
+ i2c2_1v8_pins_default: i2c2-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
+ AM62X_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
+ >;
+ };
+
+ mdio0_pins_default: mdio0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0160, PIN_OUTPUT, 7) /* (AD24) MDIO0_MDC.GPIO0_86 */
+ AM62X_IOPAD(0x015c, PIN_INPUT, 7) /* (AB22) MDIO0_MDIO.GPIO0_85 */
+ >;
+ };
+
+ rgmii1_pins_default: rgmii1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x014c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */
+ AM62X_IOPAD(0x0150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */
+ AM62X_IOPAD(0x0154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */
+ AM62X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */
+ AM62X_IOPAD(0x0148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */
+ AM62X_IOPAD(0x0144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */
+ AM62X_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
+ AM62X_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
+ AM62X_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
+ AM62X_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
+ AM62X_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
+ AM62X_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
+ >;
+ };
+
+ emmc_pins_default: emmc-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
+ AM62X_IOPAD(0x0218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
+ AM62X_IOPAD(0x0214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
+ AM62X_IOPAD(0x0210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */
+ AM62X_IOPAD(0x020c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */
+ AM62X_IOPAD(0x0208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */
+ AM62X_IOPAD(0x0204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */
+ AM62X_IOPAD(0x0200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */
+ AM62X_IOPAD(0x01fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */
+ AM62X_IOPAD(0x01f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */
+ >;
+ };
+
+ vdd_3v3_sd_pins_default: vdd-3v3-sd-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1_GPIO1_19 */
+ >;
+ };
+
+ sd_pins_default: sd-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
+ AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
+ AM62X_IOPAD(0x0230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
+ AM62X_IOPAD(0x022c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
+ AM62X_IOPAD(0x0228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
+ AM62X_IOPAD(0x0224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
+ AM62X_IOPAD(0x0240, PIN_INPUT, 7) /* (D17) MMC1_SDCD.GPIO1_48 */
+ >;
+ };
+
+ wifi_pins_default: wifi-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0120, PIN_INPUT, 0) /* (C24) MMC2_CMD */
+ AM62X_IOPAD(0x0118, PIN_INPUT, 0) /* (D25) MMC2_CLK */
+ AM62X_IOPAD(0x0114, PIN_INPUT, 0) /* (B24) MMC2_DAT0 */
+ AM62X_IOPAD(0x0110, PIN_INPUT, 0) /* (C25) MMC2_DAT1 */
+ AM62X_IOPAD(0x010c, PIN_INPUT, 0) /* (E23) MMC2_DAT2 */
+ AM62X_IOPAD(0x0108, PIN_INPUT, 0) /* (D24) MMC2_DAT3 */
+ AM62X_IOPAD(0x0124, PIN_INPUT, 0) /* (A23) MMC2_SDCD */
+ AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */
+ >;
+ };
+
+ wifi_en_pins_default: wifi-en-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x009c, PIN_OUTPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */
+ >;
+ };
+
+ wifi_wlirq_pins_default: wifi-wlirq-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */
+ >;
+ };
+
+ spe_pins_default: spe-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0168, PIN_INPUT, 1) /* (AE21) RGMII2_TXC.RMII2_CRS_DV */
+ AM62X_IOPAD(0x0180, PIN_INPUT, 1) /* (AD23) RGMII2_RXC.RMII2_REF_CLK */
+ AM62X_IOPAD(0x0184, PIN_INPUT, 1) /* (AE23) RGMII2_RD0.RMII2_RXD0 */
+ AM62X_IOPAD(0x0188, PIN_INPUT, 1) /* (AB20) RGMII2_RD1.RMII2_RXD1 */
+ AM62X_IOPAD(0x017c, PIN_INPUT, 1) /* (AD22) RGMII2_RX_CTL.RMII2_RX_ER */
+ AM62X_IOPAD(0x016c, PIN_INPUT, 1) /* (Y18) RGMII2_TD0.RMII2_TXD0 */
+ AM62X_IOPAD(0x0170, PIN_INPUT, 1) /* (AA18) RGMII2_TD1.RMII2_TXD1 */
+ AM62X_IOPAD(0x0164, PIN_INPUT, 1) /* (AA19) RGMII2_TX_CTL.RMII2_TX_EN */
+ AM62X_IOPAD(0x018c, PIN_OUTPUT, 7) /* (AC21) RGMII2_RD2.GPIO1_5 */
+ AM62X_IOPAD(0x0190, PIN_INPUT, 7) /* (AE22) RGMII2_RD3.GPIO1_6 */
+ AM62X_IOPAD(0x01f0, PIN_OUTPUT, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */
+ >;
+ };
+
+ mikrobus_i2c_pins_default: mikrobus-i2c-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A15) UART0_CTSn.I2C3_SCL */
+ AM62X_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (B15) UART0_RTSn.I2C3_SDA */
+ >;
+ };
+
+ mikrobus_uart_pins_default: mikrobus-uart-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x01d8, PIN_INPUT, 1) /* (C15) MCAN0_TX.UART5_RXD */
+ AM62X_IOPAD(0x01dc, PIN_OUTPUT, 1) /* (E15) MCAN0_RX.UART5_TXD */
+ >;
+ };
+
+ mikrobus_spi_pins_default: mikrobus-spi-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x01b0, PIN_INPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */
+ AM62X_IOPAD(0x01ac, PIN_INPUT, 1) /* (E19) MCASP0_AFSR.SPI2_CS0 */
+ AM62X_IOPAD(0x0194, PIN_INPUT, 1) /* (B19) MCASP0_AXR3.SPI2_D0 */
+ AM62X_IOPAD(0x0198, PIN_INPUT, 1) /* (A19) MCASP0_AXR2.SPI2_D1 */
+ >;
+ };
+
+ mikrobus_gpio_pins_default: mikrobus-gpio-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x019c, PIN_INPUT, 7) /* (B18) MCASP0_AXR1.GPIO1_9 */
+ AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */
+ AM62X_IOPAD(0x01a8, PIN_INPUT, 7) /* (D20) MCASP0_AFSX.GPIO1_12 */
+ >;
+ };
+
+ console_pins_default: console-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
+ AM62X_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
+ >;
+ };
+
+ wifi_debug_uart_pins_default: wifi-debug-uart-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x001c, PIN_INPUT, 3) /* (J23) OSPI0_D4.UART6_RXD */
+ AM62X_IOPAD(0x0020, PIN_OUTPUT, 3) /* (J25) OSPI0_D5.UART6_TXD */
+ >;
+ };
+
+ usb1_pins_default: usb1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0258, PIN_INPUT, 0) /* (F18) USB1_DRVVBUS */
+ >;
+ };
+
+ pmic_irq_pins_default: pmic-irq-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (D16) EXTINTn */
+ >;
+ };
+
+ hdmi_gpio_pins_default: hdmi-gpio-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0094, PIN_INPUT_PULLUP | PIN_DEBOUNCE_CONF6, 7) /* (N20) GPMC0_BE1n.GPIO0_36 */
+ AM62X_IOPAD(0x0054, PIN_OUTPUT_PULLUP, 7) /* (P21) GPMC0_AD6.GPIO0_21 */
+ >;
+ };
+
+ mcasp_hdmi_pins_default: mcasp-hdmi-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0090, PIN_INPUT, 2) /* (M24) GPMC0_BE0n_CLE.MCASP1_ACLKX */
+ AM62X_IOPAD(0x0098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */
+ AM62X_IOPAD(0x008c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEn.MCASP1_AXR0 */
+ AM62X_IOPAD(0x0088, PIN_INPUT, 2) /* (L24) GPMC0_OEn_REn.MCASP1_AXR1 */
+ AM62X_IOPAD(0x0084, PIN_INPUT, 2) /* (L23) GPMC0_ADVn_ALE.MCASP1_AXR2 */
+ AM62X_IOPAD(0x007c, PIN_INPUT, 2) /* (P25) GPMC0_CLK.MCASP1_AXR3 */
+ >;
+ };
+
+ dss0_pins_default: dss0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */
+ AM62X_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */
+ AM62X_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */
+ AM62X_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */
+ AM62X_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
+ AM62X_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */
+ AM62X_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */
+ AM62X_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */
+ AM62X_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */
+ AM62X_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */
+ AM62X_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */
+ AM62X_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */
+ AM62X_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */
+ AM62X_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */
+ AM62X_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */
+ AM62X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */
+ AM62X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */
+ AM62X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */
+ AM62X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */
+ AM62X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */
+ AM62X_IOPAD(0x005c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */
+ AM62X_IOPAD(0x0060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */
+ AM62X_IOPAD(0x0064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */
+ AM62X_IOPAD(0x0068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */
+ AM62X_IOPAD(0x006c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */
+ AM62X_IOPAD(0x0070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */
+ AM62X_IOPAD(0x0074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */
+ AM62X_IOPAD(0x0078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */
+ >;
+ };
+};
+
+&mcu_pmx0 {
+ i2c_qwiic_pins_default: i2c-qwiic-default-pins {
+ pinctrl-single,pins = <
+ AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */
+ AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */
+ >;
+ };
+
+ gbe_pmx_obsclk: gbe-pmx-obsclk-default-pins {
+ pinctrl-single,pins = <
+ AM62X_MCU_IOPAD(0x0004, PIN_OUTPUT, 1) /* (B8) MCU_SPI0_CS1.MCU_OBSCLK0 */
+ >;
+ };
+
+ i2c_csi_pins_default: i2c-csi-default-pins {
+ pinctrl-single,pins = <
+ AM62X_MCU_IOPAD(0x004c, PIN_INPUT_PULLUP, 0) /* (B9) WKUP_I2C0_SCL */
+ AM62X_MCU_IOPAD(0x0050, PIN_INPUT_PULLUP, 0) /* (A9) WKUP_I2C0_SDA */
+ >;
+ };
+
+ wifi_32k_clk: mcu-clk-out-default-pins {
+ pinctrl-single,pins = <
+ AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */
+ >;
+ };
+};
+
+&a53_opp_table {
+ /* Requires VDD_CORE to be at 0.85V */
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-supported-hw = <0x01 0x0004>;
+ };
+};
+
+&wkup_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_csi_pins_default>;
+ clock-frequency = <400000>;
+ /* Enable with overlay for camera sensor */
+};
+
+&mcu_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_qwiic_pins_default>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&usbss0 {
+ ti,vbus-divider;
+ status = "okay";
+};
+
+&usb0 {
+ dr_mode = "peripheral";
+};
+
+&usbss1 {
+ ti,vbus-divider;
+ status = "okay";
+};
+
+&usb1 {
+ dr_mode = "host";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_pins_default>;
+};
+
+&cpsw3g {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii1_pins_default>, <&spe_pins_default>,
+ <&gbe_pmx_obsclk>;
+ assigned-clocks = <&k3_clks 157 70>, <&k3_clks 157 20>;
+ assigned-clock-parents = <&k3_clks 157 72>, <&k3_clks 157 22>;
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw_port2 {
+ phy-mode = "rmii";
+ phy-handle = <&cpsw3g_phy1>;
+};
+
+&cpsw3g_mdio {
+ /* Workaround for errata i2329 - Use mdio bitbang */
+ status = "disabled";
+};
+
+&main_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_pins_default>;
+ gpio-line-names = "BL_EN_3V3", "SPE_PO_EN", "RTC_INT", /* 0-2 */
+ "USR0", "USR1", "USR2", "USR3", "", "", "USR4", /* 3-9 */
+ "EEPROM_WP", /* 10 */
+ "CSI2_CAMERA_GPIO1", "CSI2_CAMERA_GPIO2", /* 11-12 */
+ "CC1352P7_BOOT", "CC1352P7_RSTN", "", "", "", /* 13-17 */
+ "USR_BUTTON", "", "", "", "", "", "", "", "", /* 18-26 */
+ "", "", "", "", "", "", "", "", "", "HDMI_INT", /* 27-36 */
+ "", "VDD_WLAN_EN", "", "", "WL_IRQ", "GBE_INTN",/* 37-42 */
+ "", "", "", "", "", "", "", "", "", "", "", "", /* 43-54 */
+ "", "", "", "", "", "", "", "", "", "", "", "", /* 55-66 */
+ "", "", "", "", "", "", "", "", "", "", "", "", /* 67-78 */
+ "", "", "", "", "", "", /* 79-84 */
+ "BITBANG_MDIO_DATA", "BITBANG_MDIO_CLK", /* 85-86 */
+ "", "", "", "", ""; /* 87-91 */
+};
+
+&main_gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mikrobus_gpio_pins_default>;
+ gpio-line-names = "", "", "", "", "", /* 0-4 */
+ "SPE_RSTN", "SPE_INTN", "MIKROBUS_GPIO1_7", /* 5-7 */
+ "MIKROBUS_GPIO1_8", "MIKROBUS_GPIO1_9", /* 8-9 */
+ "MIKROBUS_GPIO1_10", "MIKROBUS_GPIO1_11", /* 10-11 */
+ "MIKROBUS_GPIO1_12", "MIKROBUS_W1_GPIO0", /* 12-13 */
+ "MIKROBUS_GPIO1_14", /* 14 */
+ "", "", "", "", "VDD_3V3_SD", "", "", /* 15-21 */
+ "MIKROBUS_GPIO1_22", "MIKROBUS_GPIO1_23", /* 22-23 */
+ "MIKROBUS_GPIO1_24", "MIKROBUS_GPIO1_25", /* 24-25 */
+ "", "", "", "", "", "", "", "", "", "", "", "", /* 26-37 */
+ "", "", "", "", "", "", "", "", "", "", /* 38-47 */
+ "SD_CD", "SD_VOLT_SEL", "", ""; /* 48-51 */
+};
+
+&main_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&local_i2c_pins_default>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
+
+ rtc: rtc@68 {
+ compatible = "ti,bq32000";
+ reg = <0x68>;
+ interrupt-parent = <&main_gpio0>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ tps65219: pmic@30 {
+ compatible = "ti,tps65219";
+ reg = <0x30>;
+ buck1-supply = <&vsys_5v0>;
+ buck2-supply = <&vsys_5v0>;
+ buck3-supply = <&vsys_5v0>;
+ ldo1-supply = <&vdd_3v3>;
+ ldo2-supply = <&buck2_reg>;
+ ldo3-supply = <&vdd_3v3>;
+ ldo4-supply = <&vdd_3v3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins_default>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ system-power-controller;
+ ti,power-button;
+
+ regulators {
+ buck1_reg: buck1 {
+ regulator-name = "VDD_CORE";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck2_reg: buck2 {
+ regulator-name = "VDD_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck3_reg: buck3 {
+ regulator-name = "VDD_1V2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: ldo1 {
+ /*
+ * Regulator is left as is unused, vdd_sd
+ * is controlled via GPIO with bypass config
+ * as per the NVM configuration
+ */
+ regulator-name = "VDD_SD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-allow-bypass;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: ldo2 {
+ regulator-name = "VDDA_0V85";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3_reg: ldo3 {
+ regulator-name = "VDDA_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4_reg: ldo4 {
+ regulator-name = "VDD_2V5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&main_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&grove_pins_default>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&main_i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_1v8_pins_default>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ it66121: bridge-hdmi@4c {
+ compatible = "ite,it66121";
+ reg = <0x4c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_gpio_pins_default>;
+ vcn33-supply = <&vdd_3v3>;
+ vcn18-supply = <&buck2_reg>;
+ vrf12-supply = <&buck3_reg>;
+ reset-gpios = <&main_gpio0 21 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&main_gpio0>;
+ interrupts = <36 IRQ_TYPE_EDGE_FALLING>;
+ #sound-dai-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ it66121_in: endpoint {
+ bus-width = <24>;
+ remote-endpoint = <&dpi1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ it66121_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+};
+
+&main_i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mikrobus_i2c_pins_default>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&main_spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mikrobus_spi_pins_default>;
+ status = "okay";
+};
+
+&sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+ status = "okay";
+};
+
+&sdhci1 {
+ /* SD/MMC */
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd_pins_default>;
+
+ vmmc-supply = <&vdd_3v3_sd>;
+ vqmmc-supply = <&vdd_sd_dv>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+ cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>;
+ cd-debounce-delay-ms = <100>;
+ ti,fails-without-test-cd;
+ status = "okay";
+};
+
+&sdhci2 {
+ vmmc-supply = <&wlan_en>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_pins_default>, <&wifi_32k_clk>;
+ bus-width = <4>;
+ non-removable;
+ ti,fails-without-test-cd;
+ cap-power-off-card;
+ keep-power-in-suspend;
+ ti,driver-strength-ohm = <50>;
+ assigned-clocks = <&k3_clks 157 158>;
+ assigned-clock-parents = <&k3_clks 157 160>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1807";
+ reg = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_wlirq_pins_default>;
+ interrupt-parent = <&main_gpio0>;
+ interrupts = <41 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&main_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&console_pins_default>;
+ status = "okay";
+};
+
+&main_uart1 {
+ /* Main UART1 is used by TIFS firmware */
+ status = "reserved";
+};
+
+&main_uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mikrobus_uart_pins_default>;
+ status = "okay";
+};
+
+&main_uart6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_debug_uart_pins_default>;
+ status = "okay";
+};
+
+&dss {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dss0_pins_default>;
+};
+
+&dss_ports {
+ /* VP2: DPI Output */
+ port@1 {
+ reg = <1>;
+
+ dpi1_out: endpoint {
+ remote-endpoint = <&it66121_in>;
+ };
+ };
+};
+
+&mcasp1 {
+ status = "okay";
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcasp_hdmi_pins_default>;
+ auxclk-fs-ratio = <2177>;
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 0 0 0
+ 0 0 0 0
+ 0 0 0 0
+ 0 0 0 0
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts b/arch/arm/dts/k3-am625-r5-beagleplay.dts
new file mode 100644
index 0000000..9c9d057
--- /dev/null
+++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * https://beagleboard.org/play
+ *
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
+ */
+
+#include "k3-am625-beagleplay.dts"
+#include "k3-am625-beagleplay-ddr4-1600MTs.dtsi"
+#include "k3-am62-ddr.dtsi"
+
+#include "k3-am625-beagleplay-u-boot.dtsi"
+
+/ {
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a53_0;
+ };
+
+ a53_0: a53@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x00 0x00a90000 0x00 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 135 0>;
+ clocks = <&k3_clks 61 0>;
+ assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+ assigned-clock-parents = <&k3_clks 61 2>;
+ assigned-clock-rates = <200000000>, <1250000000>;
+ ti,sci = <&dmsc>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ bootph-pre-ram;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <36>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_main 22>,
+ <&secure_proxy_main 23>;
+ bootph-pre-ram;
+ };
+};
+
+&dmsc {
+ mboxes= <&secure_proxy_main 0>,
+ <&secure_proxy_main 1>,
+ <&secure_proxy_main 0>;
+ mbox-names = "rx", "tx", "notify";
+ ti,host-id = <35>;
+ ti,secure-host;
+};
+
+&mcu_esm {
+ bootph-pre-ram;
+};
+
+&secure_proxy_sa3 {
+ bootph-pre-ram;
+ /* We require this for boot handshake */
+ status = "okay";
+};
+
+&cbass_main {
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
+ mbox-names = "tx", "rx", "boot_notify";
+ bootph-pre-ram;
+ };
+};
+
+&main_esm {
+ bootph-pre-ram;
+};
+
+&main_pktdma {
+ ti,sci = <&dm_tifs>;
+};
+
+&main_bcdma {
+ ti,sci = <&dm_tifs>;
+};
diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi
index a35d641..41277bf 100644
--- a/arch/arm/dts/k3-am625-sk-binman.dtsi
+++ b/arch/arm/dts/k3-am625-sk-binman.dtsi
@@ -389,7 +389,7 @@
type = "flat_dt";
arch = "arm";
compression = "none";
- blob {
+ spl_am625_sk_dtb_unsigned: blob {
filename = SPL_AM625_SK_DTB;
};
};
@@ -438,7 +438,7 @@
type = "flat_dt";
arch = "arm";
compression = "none";
- blob {
+ am625_sk_dtb_unsigned: blob {
filename = AM625_SK_DTB;
};
hash {
diff --git a/arch/arm/dts/k3-am625-sk-u-boot.dtsi b/arch/arm/dts/k3-am625-sk-u-boot.dtsi
index c1685bc..7ae5e01 100644
--- a/arch/arm/dts/k3-am625-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-sk-u-boot.dtsi
@@ -17,113 +17,175 @@
};
memory@80000000 {
- bootph-pre-ram;
+ bootph-all;
};
};
+&main_conf {
+ bootph-all;
+};
+
&cbass_main {
- bootph-pre-ram;
+ bootph-all;
};
&main_timer0 {
clock-frequency = <25000000>;
- bootph-pre-ram;
+ bootph-all;
};
&dmss {
- bootph-pre-ram;
+ bootph-all;
};
&secure_proxy_main {
- bootph-pre-ram;
+ bootph-all;
};
&dmsc {
- bootph-pre-ram;
+ bootph-all;
};
&k3_pds {
- bootph-pre-ram;
+ bootph-all;
};
&k3_clks {
- bootph-pre-ram;
+ bootph-all;
};
&k3_reset {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_conf {
- bootph-pre-ram;
+ bootph-all;
};
&chipid {
- bootph-pre-ram;
+ bootph-all;
};
&main_pmx0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_uart0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_uart0_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&cbass_mcu {
- bootph-pre-ram;
+ bootph-all;
};
&cbass_wakeup {
- bootph-pre-ram;
+ bootph-all;
};
&mcu_pmx0 {
- bootph-pre-ram;
+ bootph-all;
};
&sdhci1 {
- bootph-pre-ram;
+ bootph-all;
};
&main_mmc1_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&fss {
- bootph-pre-ram;
+ bootph-all;
};
&ospi0_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&ospi0 {
- bootph-pre-ram;
+ bootph-all;
flash@0 {
- bootph-pre-ram;
+ bootph-all;
partitions {
- bootph-pre-ram;
+ bootph-all;
partition@3fc0000 {
- bootph-pre-ram;
+ bootph-all;
};
};
};
};
+&inta_main_dmss {
+ bootph-all;
+};
+
+&main_bcdma {
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>,
+ <0x00 0x48600000 0x00 0x8000>,
+ <0x00 0x484a4000 0x00 0x2000>,
+ <0x00 0x484c2000 0x00 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
+ "ringrt" , "cfg", "tchan", "rchan";
+};
+
+&main_pktdma {
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x20000>,
+ <0x00 0x4b800000 0x00 0x200000>,
+ <0x00 0x485e0000 0x00 0x10000>,
+ <0x00 0x484a0000 0x00 0x2000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x1000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+ "cfg", "tchan", "rchan", "rflow";
+ bootph-all;
+};
+
+&cpsw3g_mdio {
+ bootph-all;
+};
+
+&cpsw3g_phy0 {
+ bootph-all;
+};
+
+&cpsw3g_phy1 {
+ bootph-all;
+};
+
+&main_rgmii1_pins_default {
+ bootph-all;
+};
+
+&main_rgmii2_pins_default {
+ bootph-all;
+};
+
+&phy_gmii_sel {
+ bootph-all;
+};
+
&cpsw3g {
- bootph-pre-ram;
+ bootph-all;
+ ethernet-ports {
+ bootph-all;
+ };
};
&cpsw_port1 {
- bootph-pre-ram;
+ bootph-all;
};
&cpsw_port2 {
diff --git a/arch/arm/dts/k3-am625-sk.dts b/arch/arm/dts/k3-am625-sk.dts
index 3f9ef40..7c98c1b 100644
--- a/arch/arm/dts/k3-am625-sk.dts
+++ b/arch/arm/dts/k3-am625-sk.dts
@@ -212,7 +212,7 @@
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
- flash@0{
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
diff --git a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
index 9bad430..841541b 100644
--- a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
+++ b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
@@ -1,19 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
- * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.08
- * Fri Jun 09 2023 08:01:37 GMT+0200 (Central European Summer Time)
+ * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.10
+ * Mon Dec 11 2023 17:07:35 GMT+0100 (Central European Standard Time)
* DDR Type: LPDDR4
* F0 = 50MHz F1 = NA F2 = 800MHz
* Density (per channel): 16Gb
* Write DBI: Enable
* Number of Ranks: 1
- */
+*/
#define DDRSS_PLL_FHS_CNT 3
#define DDRSS_PLL_FREQUENCY_1 400000000
#define DDRSS_PLL_FREQUENCY_2 400000000
+
#define DDRSS_CTL_0_DATA 0x00000B00
#define DDRSS_CTL_1_DATA 0x00000000
#define DDRSS_CTL_2_DATA 0x00000000
@@ -54,20 +55,20 @@
#define DDRSS_CTL_37_DATA 0x00000000
#define DDRSS_CTL_38_DATA 0x0000040C
#define DDRSS_CTL_39_DATA 0x00000000
-#define DDRSS_CTL_40_DATA 0x0000081C
+#define DDRSS_CTL_40_DATA 0x00000A1C
#define DDRSS_CTL_41_DATA 0x00000000
-#define DDRSS_CTL_42_DATA 0x0000081C
+#define DDRSS_CTL_42_DATA 0x00000A1C
#define DDRSS_CTL_43_DATA 0x00000000
#define DDRSS_CTL_44_DATA 0x05000804
#define DDRSS_CTL_45_DATA 0x00000B00
#define DDRSS_CTL_46_DATA 0x09090004
-#define DDRSS_CTL_47_DATA 0x00000204
+#define DDRSS_CTL_47_DATA 0x00000304
#define DDRSS_CTL_48_DATA 0x00370008
#define DDRSS_CTL_49_DATA 0x09090024
-#define DDRSS_CTL_50_DATA 0x00001910
+#define DDRSS_CTL_50_DATA 0x00002110
#define DDRSS_CTL_51_DATA 0x00370008
#define DDRSS_CTL_52_DATA 0x09090024
-#define DDRSS_CTL_53_DATA 0x09001910
+#define DDRSS_CTL_53_DATA 0x09002110
#define DDRSS_CTL_54_DATA 0x000A0A09
#define DDRSS_CTL_55_DATA 0x0400036D
#define DDRSS_CTL_56_DATA 0x09092004
@@ -223,19 +224,19 @@
#define DDRSS_CTL_206_DATA 0x00000000
#define DDRSS_CTL_207_DATA 0x00000000
#define DDRSS_CTL_208_DATA 0x00000024
-#define DDRSS_CTL_209_DATA 0x00000012
+#define DDRSS_CTL_209_DATA 0x0000001A
#define DDRSS_CTL_210_DATA 0x00000000
#define DDRSS_CTL_211_DATA 0x00000024
-#define DDRSS_CTL_212_DATA 0x00000012
+#define DDRSS_CTL_212_DATA 0x0000001A
#define DDRSS_CTL_213_DATA 0x00000000
#define DDRSS_CTL_214_DATA 0x00000004
#define DDRSS_CTL_215_DATA 0x00000000
#define DDRSS_CTL_216_DATA 0x00000000
#define DDRSS_CTL_217_DATA 0x00000024
-#define DDRSS_CTL_218_DATA 0x00000012
+#define DDRSS_CTL_218_DATA 0x0000001A
#define DDRSS_CTL_219_DATA 0x00000000
#define DDRSS_CTL_220_DATA 0x00000024
-#define DDRSS_CTL_221_DATA 0x00000012
+#define DDRSS_CTL_221_DATA 0x0000001A
#define DDRSS_CTL_222_DATA 0x00000000
#define DDRSS_CTL_223_DATA 0x00000000
#define DDRSS_CTL_224_DATA 0x00000031
@@ -268,21 +269,21 @@
#define DDRSS_CTL_251_DATA 0x00000000
#define DDRSS_CTL_252_DATA 0x00000000
#define DDRSS_CTL_253_DATA 0x00000000
-#define DDRSS_CTL_254_DATA 0x46004646
-#define DDRSS_CTL_255_DATA 0x00002746
-#define DDRSS_CTL_256_DATA 0x00000027
-#define DDRSS_CTL_257_DATA 0x00000027
-#define DDRSS_CTL_258_DATA 0x00000027
-#define DDRSS_CTL_259_DATA 0x00000027
-#define DDRSS_CTL_260_DATA 0x00000027
+#define DDRSS_CTL_254_DATA 0x44004444
+#define DDRSS_CTL_255_DATA 0x00004D44
+#define DDRSS_CTL_256_DATA 0x0000004D
+#define DDRSS_CTL_257_DATA 0x0000004D
+#define DDRSS_CTL_258_DATA 0x0000004D
+#define DDRSS_CTL_259_DATA 0x0000004D
+#define DDRSS_CTL_260_DATA 0x0000004D
#define DDRSS_CTL_261_DATA 0x00000000
#define DDRSS_CTL_262_DATA 0x00000000
-#define DDRSS_CTL_263_DATA 0x0000000F
-#define DDRSS_CTL_264_DATA 0x0000000F
-#define DDRSS_CTL_265_DATA 0x0000000F
-#define DDRSS_CTL_266_DATA 0x0000000F
-#define DDRSS_CTL_267_DATA 0x0000000F
-#define DDRSS_CTL_268_DATA 0x0000000F
+#define DDRSS_CTL_263_DATA 0x0000004D
+#define DDRSS_CTL_264_DATA 0x0000004D
+#define DDRSS_CTL_265_DATA 0x0000004D
+#define DDRSS_CTL_266_DATA 0x0000004D
+#define DDRSS_CTL_267_DATA 0x0000004D
+#define DDRSS_CTL_268_DATA 0x0000004D
#define DDRSS_CTL_269_DATA 0x00000000
#define DDRSS_CTL_270_DATA 0x00001000
#define DDRSS_CTL_271_DATA 0x00000015
@@ -388,13 +389,13 @@
#define DDRSS_CTL_371_DATA 0x01000101
#define DDRSS_CTL_372_DATA 0x01010001
#define DDRSS_CTL_373_DATA 0x00010101
-#define DDRSS_CTL_374_DATA 0x01050503
+#define DDRSS_CTL_374_DATA 0x01070703
#define DDRSS_CTL_375_DATA 0x05020201
#define DDRSS_CTL_376_DATA 0x08080C0C
#define DDRSS_CTL_377_DATA 0x00080308
-#define DDRSS_CTL_378_DATA 0x000B030E
-#define DDRSS_CTL_379_DATA 0x000B0310
-#define DDRSS_CTL_380_DATA 0x0B0B0810
+#define DDRSS_CTL_378_DATA 0x0009030E
+#define DDRSS_CTL_379_DATA 0x00090312
+#define DDRSS_CTL_380_DATA 0x09090806
#define DDRSS_CTL_381_DATA 0x01000000
#define DDRSS_CTL_382_DATA 0x03020301
#define DDRSS_CTL_383_DATA 0x04000102
@@ -416,7 +417,7 @@
#define DDRSS_CTL_399_DATA 0x00003690
#define DDRSS_CTL_400_DATA 0x00007940
#define DDRSS_CTL_401_DATA 0x070D0402
-#define DDRSS_CTL_402_DATA 0x00260405
+#define DDRSS_CTL_402_DATA 0x00260607
#define DDRSS_CTL_403_DATA 0x00000C20
#define DDRSS_CTL_404_DATA 0x00000200
#define DDRSS_CTL_405_DATA 0x00000200
@@ -425,7 +426,7 @@
#define DDRSS_CTL_408_DATA 0x00003690
#define DDRSS_CTL_409_DATA 0x00007940
#define DDRSS_CTL_410_DATA 0x070D0402
-#define DDRSS_CTL_411_DATA 0x00000405
+#define DDRSS_CTL_411_DATA 0x00000607
#define DDRSS_CTL_412_DATA 0x00000000
#define DDRSS_CTL_413_DATA 0x0302000A
#define DDRSS_CTL_414_DATA 0x01000500
@@ -609,8 +610,8 @@
#define DDRSS_PI_169_DATA 0x00020043
#define DDRSS_PI_170_DATA 0x02000200
#define DDRSS_PI_171_DATA 0x00000004
-#define DDRSS_PI_172_DATA 0x0000080C
-#define DDRSS_PI_173_DATA 0x00081C00
+#define DDRSS_PI_172_DATA 0x00000A0C
+#define DDRSS_PI_173_DATA 0x000A1C00
#define DDRSS_PI_174_DATA 0x001C0000
#define DDRSS_PI_175_DATA 0x00000013
#define DDRSS_PI_176_DATA 0x00000059
@@ -624,15 +625,15 @@
#define DDRSS_PI_184_DATA 0x01000100
#define DDRSS_PI_185_DATA 0x00000100
#define DDRSS_PI_186_DATA 0x00000000
-#define DDRSS_PI_187_DATA 0x05050503
+#define DDRSS_PI_187_DATA 0x05070703
#define DDRSS_PI_188_DATA 0x01010C0C
#define DDRSS_PI_189_DATA 0x01010101
#define DDRSS_PI_190_DATA 0x000C0C0A
#define DDRSS_PI_191_DATA 0x00000000
#define DDRSS_PI_192_DATA 0x00000000
#define DDRSS_PI_193_DATA 0x04000000
-#define DDRSS_PI_194_DATA 0x04020808
-#define DDRSS_PI_195_DATA 0x04040204
+#define DDRSS_PI_194_DATA 0x06020808
+#define DDRSS_PI_195_DATA 0x04040206
#define DDRSS_PI_196_DATA 0x00090031
#define DDRSS_PI_197_DATA 0x00110039
#define DDRSS_PI_198_DATA 0x00110039
@@ -661,13 +662,13 @@
#define DDRSS_PI_221_DATA 0x00001900
#define DDRSS_PI_222_DATA 0x32000056
#define DDRSS_PI_223_DATA 0x06000101
-#define DDRSS_PI_224_DATA 0x001D0204
-#define DDRSS_PI_225_DATA 0x32120058
+#define DDRSS_PI_224_DATA 0x001F0204
+#define DDRSS_PI_225_DATA 0x72400056
#define DDRSS_PI_226_DATA 0x05000101
-#define DDRSS_PI_227_DATA 0x001D0408
-#define DDRSS_PI_228_DATA 0x32120058
+#define DDRSS_PI_227_DATA 0x001F0608
+#define DDRSS_PI_228_DATA 0x72400056
#define DDRSS_PI_229_DATA 0x05000101
-#define DDRSS_PI_230_DATA 0x00000408
+#define DDRSS_PI_230_DATA 0x00000608
#define DDRSS_PI_231_DATA 0x05040900
#define DDRSS_PI_232_DATA 0x00060900
#define DDRSS_PI_233_DATA 0x00000315
@@ -741,23 +742,23 @@
#define DDRSS_PI_301_DATA 0x00000000
#define DDRSS_PI_302_DATA 0x00000000
#define DDRSS_PI_303_DATA 0x00000000
-#define DDRSS_PI_304_DATA 0x00100F27
+#define DDRSS_PI_304_DATA 0x00104D4D
#define DDRSS_PI_305_DATA 0x00000000
#define DDRSS_PI_306_DATA 0x00000024
-#define DDRSS_PI_307_DATA 0x00000012
+#define DDRSS_PI_307_DATA 0x0000001A
#define DDRSS_PI_308_DATA 0x000000B1
#define DDRSS_PI_309_DATA 0x00000000
#define DDRSS_PI_310_DATA 0x00000000
-#define DDRSS_PI_311_DATA 0x46000000
-#define DDRSS_PI_312_DATA 0x00150F27
+#define DDRSS_PI_311_DATA 0x44000000
+#define DDRSS_PI_312_DATA 0x00154D4D
#define DDRSS_PI_313_DATA 0x00000000
#define DDRSS_PI_314_DATA 0x00000024
-#define DDRSS_PI_315_DATA 0x00000012
+#define DDRSS_PI_315_DATA 0x0000001A
#define DDRSS_PI_316_DATA 0x000000B1
#define DDRSS_PI_317_DATA 0x00000000
#define DDRSS_PI_318_DATA 0x00000000
-#define DDRSS_PI_319_DATA 0x46000000
-#define DDRSS_PI_320_DATA 0x00150F27
+#define DDRSS_PI_319_DATA 0x44000000
+#define DDRSS_PI_320_DATA 0x00154D4D
#define DDRSS_PI_321_DATA 0x00000000
#define DDRSS_PI_322_DATA 0x00000004
#define DDRSS_PI_323_DATA 0x00000000
@@ -765,23 +766,23 @@
#define DDRSS_PI_325_DATA 0x00000000
#define DDRSS_PI_326_DATA 0x00000000
#define DDRSS_PI_327_DATA 0x00000000
-#define DDRSS_PI_328_DATA 0x00100F27
+#define DDRSS_PI_328_DATA 0x00104D4D
#define DDRSS_PI_329_DATA 0x00000000
#define DDRSS_PI_330_DATA 0x00000024
-#define DDRSS_PI_331_DATA 0x00000012
+#define DDRSS_PI_331_DATA 0x0000001A
#define DDRSS_PI_332_DATA 0x000000B1
#define DDRSS_PI_333_DATA 0x00000000
#define DDRSS_PI_334_DATA 0x00000000
-#define DDRSS_PI_335_DATA 0x46000000
-#define DDRSS_PI_336_DATA 0x00150F27
+#define DDRSS_PI_335_DATA 0x44000000
+#define DDRSS_PI_336_DATA 0x00154D4D
#define DDRSS_PI_337_DATA 0x00000000
#define DDRSS_PI_338_DATA 0x00000024
-#define DDRSS_PI_339_DATA 0x00000012
+#define DDRSS_PI_339_DATA 0x0000001A
#define DDRSS_PI_340_DATA 0x000000B1
#define DDRSS_PI_341_DATA 0x00000000
#define DDRSS_PI_342_DATA 0x00000000
-#define DDRSS_PI_343_DATA 0x46000000
-#define DDRSS_PI_344_DATA 0x00150F27
+#define DDRSS_PI_343_DATA 0x44000000
+#define DDRSS_PI_344_DATA 0x00154D4D
#define DDRSS_PHY_0_DATA 0x04F00000
#define DDRSS_PHY_1_DATA 0x00000000
#define DDRSS_PHY_2_DATA 0x00030200
@@ -856,8 +857,8 @@
#define DDRSS_PHY_71_DATA 0x00000000
#define DDRSS_PHY_72_DATA 0x041F07FF
#define DDRSS_PHY_73_DATA 0x00000000
-#define DDRSS_PHY_74_DATA 0x01CC0B01
-#define DDRSS_PHY_75_DATA 0x1003CC0B
+#define DDRSS_PHY_74_DATA 0x01FF0B01
+#define DDRSS_PHY_75_DATA 0x1003FF0B
#define DDRSS_PHY_76_DATA 0x20000140
#define DDRSS_PHY_77_DATA 0x07FF0200
#define DDRSS_PHY_78_DATA 0x0000DD01
@@ -872,7 +873,7 @@
#define DDRSS_PHY_87_DATA 0x02020010
#define DDRSS_PHY_88_DATA 0x51516041
#define DDRSS_PHY_89_DATA 0x31C06000
-#define DDRSS_PHY_90_DATA 0x07AB0340
+#define DDRSS_PHY_90_DATA 0x06B60340
#define DDRSS_PHY_91_DATA 0x0000C0C0
#define DDRSS_PHY_92_DATA 0x04050000
#define DDRSS_PHY_93_DATA 0x00000504
@@ -1112,8 +1113,8 @@
#define DDRSS_PHY_327_DATA 0x00000000
#define DDRSS_PHY_328_DATA 0x041F07FF
#define DDRSS_PHY_329_DATA 0x00000000
-#define DDRSS_PHY_330_DATA 0x01CC0B01
-#define DDRSS_PHY_331_DATA 0x1003CC0B
+#define DDRSS_PHY_330_DATA 0x01FF0B01
+#define DDRSS_PHY_331_DATA 0x1003FF0B
#define DDRSS_PHY_332_DATA 0x20000140
#define DDRSS_PHY_333_DATA 0x07FF0200
#define DDRSS_PHY_334_DATA 0x0000DD01
@@ -1128,7 +1129,7 @@
#define DDRSS_PHY_343_DATA 0x02020010
#define DDRSS_PHY_344_DATA 0x51516041
#define DDRSS_PHY_345_DATA 0x31C06000
-#define DDRSS_PHY_346_DATA 0x07AB0340
+#define DDRSS_PHY_346_DATA 0x06B60340
#define DDRSS_PHY_347_DATA 0x0000C0C0
#define DDRSS_PHY_348_DATA 0x04050000
#define DDRSS_PHY_349_DATA 0x00000504
@@ -1326,7 +1327,7 @@
#define DDRSS_PHY_541_DATA 0x003F0000
#define DDRSS_PHY_542_DATA 0x000F013F
#define DDRSS_PHY_543_DATA 0x0000000F
-#define DDRSS_PHY_544_DATA 0x020002CC
+#define DDRSS_PHY_544_DATA 0x020002FF
#define DDRSS_PHY_545_DATA 0x00030000
#define DDRSS_PHY_546_DATA 0x00000300
#define DDRSS_PHY_547_DATA 0x00000300
@@ -1582,7 +1583,7 @@
#define DDRSS_PHY_797_DATA 0x00000000
#define DDRSS_PHY_798_DATA 0x000F0000
#define DDRSS_PHY_799_DATA 0x0000000F
-#define DDRSS_PHY_800_DATA 0x020002CC
+#define DDRSS_PHY_800_DATA 0x020002FF
#define DDRSS_PHY_801_DATA 0x00030000
#define DDRSS_PHY_802_DATA 0x00000300
#define DDRSS_PHY_803_DATA 0x00000300
@@ -1838,7 +1839,7 @@
#define DDRSS_PHY_1053_DATA 0x10000000
#define DDRSS_PHY_1054_DATA 0x000F0000
#define DDRSS_PHY_1055_DATA 0x0000000F
-#define DDRSS_PHY_1056_DATA 0x020002CC
+#define DDRSS_PHY_1056_DATA 0x020002FF
#define DDRSS_PHY_1057_DATA 0x00030000
#define DDRSS_PHY_1058_DATA 0x00000300
#define DDRSS_PHY_1059_DATA 0x00000300
@@ -2169,22 +2170,22 @@
#define DDRSS_PHY_1384_DATA 0x00000300
#define DDRSS_PHY_1385_DATA 0x00000300
#define DDRSS_PHY_1386_DATA 0x00000300
-#define DDRSS_PHY_1387_DATA 0x3183BF77
+#define DDRSS_PHY_1387_DATA 0x31833F77
#define DDRSS_PHY_1388_DATA 0x00000000
-#define DDRSS_PHY_1389_DATA 0x0C000DFF
-#define DDRSS_PHY_1390_DATA 0x30000DFF
-#define DDRSS_PHY_1391_DATA 0x3F0DFF11
-#define DDRSS_PHY_1392_DATA 0x01990000
-#define DDRSS_PHY_1393_DATA 0x780DFFCC
+#define DDRSS_PHY_1389_DATA 0x0C000DBF
+#define DDRSS_PHY_1390_DATA 0x30000DBF
+#define DDRSS_PHY_1391_DATA 0x3F0DBF11
+#define DDRSS_PHY_1392_DATA 0x01FF0000
+#define DDRSS_PHY_1393_DATA 0x780DBFFF
#define DDRSS_PHY_1394_DATA 0x00000C11
#define DDRSS_PHY_1395_DATA 0x00018011
#define DDRSS_PHY_1396_DATA 0x0089FF00
#define DDRSS_PHY_1397_DATA 0x000C3F11
-#define DDRSS_PHY_1398_DATA 0x01990000
-#define DDRSS_PHY_1399_DATA 0x000C3F11
-#define DDRSS_PHY_1400_DATA 0x01990000
-#define DDRSS_PHY_1401_DATA 0x3F0DFF11
-#define DDRSS_PHY_1402_DATA 0x01990000
+#define DDRSS_PHY_1398_DATA 0x01FF0000
+#define DDRSS_PHY_1399_DATA 0x000C3F91
+#define DDRSS_PHY_1400_DATA 0x01FF0000
+#define DDRSS_PHY_1401_DATA 0x3F0DBF11
+#define DDRSS_PHY_1402_DATA 0x01FF0000
#define DDRSS_PHY_1403_DATA 0x00018011
#define DDRSS_PHY_1404_DATA 0x0089FF00
#define DDRSS_PHY_1405_DATA 0x20040004
diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
index 5d56460..75cb60b 100644
--- a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
@@ -17,49 +17,76 @@
};
memory@80000000 {
- bootph-pre-ram;
+ bootph-all;
};
};
&cbass_main {
- bootph-pre-ram;
+ bootph-all;
timer@2400000 {
clock-frequency = <25000000>;
- bootph-pre-ram;
+ bootph-all;
};
};
&cbass_mcu {
- bootph-pre-ram;
+ bootph-all;
};
&cbass_wakeup {
- bootph-pre-ram;
+ bootph-all;
};
&chipid {
- bootph-pre-ram;
+ bootph-all;
+};
+
+&main_bcdma {
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>,
+ <0x00 0x48600000 0x00 0x8000>,
+ <0x00 0x484a4000 0x00 0x2000>,
+ <0x00 0x484c2000 0x00 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
+ "ringrt" , "cfg", "tchan", "rchan";
+};
+
+&main_pktdma {
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x20000>,
+ <0x00 0x4b800000 0x00 0x200000>,
+ <0x00 0x485e0000 0x00 0x10000>,
+ <0x00 0x484a0000 0x00 0x2000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x1000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+ "cfg", "tchan", "rchan", "rflow";
+ bootph-all;
};
&cpsw3g {
- bootph-pre-ram;
+ bootph-all;
};
&cpsw3g_phy0 {
- bootph-pre-ram;
+ bootph-all;
};
&cpsw3g_phy1 {
- bootph-pre-ram;
+ bootph-all;
};
&cpsw_port1 {
- bootph-pre-ram;
+ bootph-all;
};
&cpsw_port2 {
- bootph-pre-ram;
+ bootph-all;
};
/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
@@ -67,40 +94,40 @@
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
- bootph-pre-ram;
+ bootph-all;
};
&dmsc {
- bootph-pre-ram;
+ bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- bootph-pre-ram;
+ bootph-all;
};
};
&dmss {
- bootph-pre-ram;
+ bootph-all;
};
&fss {
- bootph-pre-ram;
+ bootph-all;
};
&k3_clks {
- bootph-pre-ram;
+ bootph-all;
};
&k3_pds {
- bootph-pre-ram;
+ bootph-all;
};
&k3_reset {
- bootph-pre-ram;
+ bootph-all;
};
&main_gpio0 {
- bootph-pre-ram;
+ bootph-all;
};
/* On-module I2C - PMIC_I2C */
@@ -130,53 +157,53 @@
};
&main_pmx0 {
- bootph-pre-ram;
+ bootph-all;
};
/* Verdin UART_3, used as the Linux console */
&main_uart0 {
- bootph-pre-ram;
+ bootph-all;
};
/* Verdin UART_1 */
&main_uart1 {
- bootph-pre-ram;
+ bootph-all;
};
&mcu_pmx0 {
- bootph-pre-ram;
+ bootph-all;
};
&pinctrl_ctrl_sleep_moci {
- bootph-pre-ram;
+ bootph-all;
};
&pinctrl_i2c0 {
- bootph-pre-ram;
+ bootph-all;
};
&pinctrl_i2c1 {
- bootph-pre-ram;
+ bootph-all;
};
&pinctrl_sdhci0 {
- bootph-pre-ram;
+ bootph-all;
};
&pinctrl_uart0 {
- bootph-pre-ram;
+ bootph-all;
};
&pinctrl_uart1 {
- bootph-pre-ram;
+ bootph-all;
};
&pinctrl_wkup_uart0 {
- bootph-pre-ram;
+ bootph-all;
};
&sdhci0 {
- bootph-pre-ram;
+ bootph-all;
};
&sdhci2 {
@@ -184,18 +211,18 @@
};
&secure_proxy_main {
- bootph-pre-ram;
+ bootph-all;
};
&verdin_ctrl_sleep_moci {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_conf {
- bootph-pre-ram;
+ bootph-all;
};
/* Verdin UART_2 */
&wkup_uart0 {
- bootph-pre-ram;
+ bootph-all;
};
diff --git a/arch/arm/dts/k3-am62a-main.dtsi b/arch/arm/dts/k3-am62a-main.dtsi
index bc4b50b..4ae7fdc 100644
--- a/arch/arm/dts/k3-am62a-main.dtsi
+++ b/arch/arm/dts/k3-am62a-main.dtsi
@@ -48,6 +48,18 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x00100000 0x20000>;
+
+ phy_gmii_sel: phy@4044 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x4044 0x8>;
+ #phy-cells = <1>;
+ };
+
+ epwm_tbclk: clock-controller@4130 {
+ compatible = "ti,am62-epwm-tbclk";
+ reg = <0x4130 0x4>;
+ #clock-cells = <1>;
+ };
};
dmss: bus@48000000 {
@@ -69,6 +81,67 @@
interrupt-names = "rx_012";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ inta_main_dmss: interrupt-controller@48000000 {
+ compatible = "ti,sci-inta";
+ reg = <0x00 0x48000000 0x00 0x100000>;
+ #interrupt-cells = <0>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ msi-controller;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <28>;
+ ti,interrupt-ranges = <6 70 34>;
+ ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
+ };
+
+ main_bcdma: dma-controller@485c0100 {
+ compatible = "ti,am64-dmss-bcdma";
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
+ msi-parent = <&inta_main_dmss>;
+ #dma-cells = <3>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <26>;
+ ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
+ ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
+ ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
+ };
+
+ main_pktdma: dma-controller@485c0000 {
+ compatible = "ti,am64-dmss-pktdma";
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x40000>,
+ <0x00 0x4b800000 0x00 0x400000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
+ msi-parent = <&inta_main_dmss>;
+ #dma-cells = <2>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <30>;
+ ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
+ <0x24>, /* CPSW_TX_CHAN */
+ <0x25>, /* SAUL_TX_0_CHAN */
+ <0x26>; /* SAUL_TX_1_CHAN */
+ ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
+ <0x11>, /* RING_CPSW_TX_CHAN */
+ <0x12>, /* RING_SAUL_TX_0_CHAN */
+ <0x13>; /* RING_SAUL_TX_1_CHAN */
+ ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
+ <0x2b>, /* CPSW_RX_CHAN */
+ <0x2d>, /* SAUL_RX_0_CHAN */
+ <0x2f>, /* SAUL_RX_1_CHAN */
+ <0x31>, /* SAUL_RX_2_CHAN */
+ <0x33>; /* SAUL_RX_3_CHAN */
+ ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
+ <0x2c>, /* FLOW_CPSW_RX_CHAN */
+ <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
+ <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
+ };
};
dmsc: system-controller@44043000 {
@@ -77,8 +150,8 @@
reg-names = "debug_messages";
ti,host-id = <12>;
mbox-names = "rx", "tx";
- mboxes= <&secure_proxy_main 12>,
- <&secure_proxy_main 13>;
+ mboxes = <&secure_proxy_main 12>,
+ <&secure_proxy_main 13>;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
@@ -96,6 +169,21 @@
};
};
+ secure_proxy_sa3: mailbox@43600000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x43600000 0x00 0x10000>,
+ <0x00 0x44880000 0x00 0x20000>,
+ <0x00 0x44860000 0x00 0x20000>;
+ /*
+ * Marked Disabled:
+ * Node is incomplete as it is meant for bootloaders and
+ * firmware on non-MPU processors
+ */
+ status = "disabled";
+ };
+
main_pmx0: pinctrl@f4000 {
compatible = "pinctrl-single";
reg = <0x00 0xf4000 0x00 0x2ac>;
@@ -104,6 +192,102 @@
pinctrl-single,function-mask = <0xffffffff>;
};
+ main_timer0: timer@2400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2400000 0x00 0x400>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 36 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 36 2>;
+ assigned-clock-parents = <&k3_clks 36 3>;
+ power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer1: timer@2410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2410000 0x00 0x400>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 37 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 37 2>;
+ assigned-clock-parents = <&k3_clks 37 3>;
+ power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer2: timer@2420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2420000 0x00 0x400>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 38 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 38 2>;
+ assigned-clock-parents = <&k3_clks 38 3>;
+ power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer3: timer@2430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2430000 0x00 0x400>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 39 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 39 2>;
+ assigned-clock-parents = <&k3_clks 39 3>;
+ power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer4: timer@2440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2440000 0x00 0x400>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 40 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 40 2>;
+ assigned-clock-parents = <&k3_clks 40 3>;
+ power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer5: timer@2450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2450000 0x00 0x400>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 41 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 41 2>;
+ assigned-clock-parents = <&k3_clks 41 3>;
+ power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer6: timer@2460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2460000 0x00 0x400>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 42 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 42 2>;
+ assigned-clock-parents = <&k3_clks 42 3>;
+ power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer7: timer@2470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2470000 0x00 0x400>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 43 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 43 2>;
+ assigned-clock-parents = <&k3_clks 43 3>;
+ power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
main_uart0: serial@2800000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
@@ -222,6 +406,39 @@
status = "disabled";
};
+ main_spi0: spi@20100000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x20100000 0x00 0x400>;
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 141 0>;
+ status = "disabled";
+ };
+
+ main_spi1: spi@20110000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20110000 0x00 0x400>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 142 0>;
+ status = "disabled";
+ };
+
+ main_spi2: spi@20120000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20120000 0x00 0x400>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 143 0>;
+ status = "disabled";
+ };
+
main_gpio_intr: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x00 0x00a00000 0x00 0x800>;
@@ -295,4 +512,368 @@
no-1-8-v;
status = "disabled";
};
+
+ usbss0: dwc3-usb@f900000 {
+ compatible = "ti,am62-usb";
+ reg = <0x00 0x0f900000 0x00 0x800>;
+ clocks = <&k3_clks 161 3>;
+ clock-names = "ref";
+ ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
+ ranges;
+ status = "disabled";
+
+ usb0: usb@31000000 {
+ compatible = "snps,dwc3";
+ reg = <0x00 0x31000000 0x00 0x50000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
+ interrupt-names = "host", "peripheral";
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ };
+ };
+
+ usbss1: dwc3-usb@f910000 {
+ compatible = "ti,am62-usb";
+ reg = <0x00 0x0f910000 0x00 0x800>;
+ clocks = <&k3_clks 162 3>;
+ clock-names = "ref";
+ ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
+ ranges;
+ status = "disabled";
+
+ usb1: usb@31100000 {
+ compatible = "snps,dwc3";
+ reg = <0x00 0x31100000 0x00 0x50000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
+ interrupt-names = "host", "peripheral";
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ };
+ };
+
+ fss: bus@fc00000 {
+ compatible = "simple-bus";
+ reg = <0x00 0x0fc00000 0x00 0x70000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ ospi0: spi@fc40000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x0fc40000 0x00 0x100>,
+ <0x05 0x00000000 0x01 0x00000000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 75 7>;
+ assigned-clocks = <&k3_clks 75 7>;
+ assigned-clock-parents = <&k3_clks 75 8>;
+ assigned-clock-rates = <166666666>;
+ power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cpsw3g: ethernet@8000000 {
+ compatible = "ti,am642-cpsw-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x8000000 0x0 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
+ clocks = <&k3_clks 13 0>;
+ assigned-clocks = <&k3_clks 13 3>;
+ assigned-clock-parents = <&k3_clks 13 11>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+
+ dmas = <&main_pktdma 0xc600 15>,
+ <&main_pktdma 0xc601 15>,
+ <&main_pktdma 0xc602 15>,
+ <&main_pktdma 0xc603 15>,
+ <&main_pktdma 0xc604 15>,
+ <&main_pktdma 0xc605 15>,
+ <&main_pktdma 0xc606 15>,
+ <&main_pktdma 0xc607 15>,
+ <&main_pktdma 0x4600 15>;
+ dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
+ "tx7", "rx";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ phys = <&phy_gmii_sel 1>;
+ mac-address = [00 00 00 00 00 00];
+ ti,syscon-efuse = <&wkup_conf 0x200>;
+ };
+
+ cpsw_port2: port@2 {
+ reg = <2>;
+ ti,mac-only;
+ label = "port2";
+ phys = <&phy_gmii_sel 2>;
+ mac-address = [00 00 00 00 00 00];
+ };
+ };
+
+ cpsw3g_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x0 0xf00 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 13 0>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ };
+
+ cpts@3d000 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x0 0x3d000 0x0 0x400>;
+ clocks = <&k3_clks 13 3>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+
+ hwspinlock: spinlock@2a000000 {
+ compatible = "ti,am64-hwspinlock";
+ reg = <0x00 0x2a000000 0x00 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ mailbox0_cluster0: mailbox@29000000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29000000 0x00 0x200>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ mailbox0_cluster1: mailbox@29010000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29010000 0x00 0x200>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ mailbox0_cluster2: mailbox@29020000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29020000 0x00 0x200>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ mailbox0_cluster3: mailbox@29030000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29030000 0x00 0x200>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ main_mcan0: can@20701000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x20701000 0x00 0x200>,
+ <0x00 0x20708000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_rti0: watchdog@e000000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e000000 0x00 0x100>;
+ clocks = <&k3_clks 125 0>;
+ power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 125 0>;
+ assigned-clock-parents = <&k3_clks 125 2>;
+ };
+
+ main_rti1: watchdog@e010000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e010000 0x00 0x100>;
+ clocks = <&k3_clks 126 0>;
+ power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 126 0>;
+ assigned-clock-parents = <&k3_clks 126 2>;
+ };
+
+ main_rti2: watchdog@e020000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e020000 0x00 0x100>;
+ clocks = <&k3_clks 127 0>;
+ power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 127 0>;
+ assigned-clock-parents = <&k3_clks 127 2>;
+ };
+
+ main_rti3: watchdog@e030000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e030000 0x00 0x100>;
+ clocks = <&k3_clks 128 0>;
+ power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 128 0>;
+ assigned-clock-parents = <&k3_clks 128 2>;
+ };
+
+ main_rti4: watchdog@e040000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e040000 0x00 0x100>;
+ clocks = <&k3_clks 205 0>;
+ power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 205 0>;
+ assigned-clock-parents = <&k3_clks 205 2>;
+ };
+
+ epwm0: pwm@23000000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23000000 0x00 0x100>;
+ power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ epwm1: pwm@23010000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23010000 0x00 0x100>;
+ power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ epwm2: pwm@23020000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23020000 0x00 0x100>;
+ power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ ecap0: pwm@23100000 {
+ compatible = "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23100000 0x00 0x100>;
+ power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 51 0>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ ecap1: pwm@23110000 {
+ compatible = "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23110000 0x00 0x100>;
+ power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 52 0>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ ecap2: pwm@23120000 {
+ compatible = "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23120000 0x00 0x100>;
+ power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 53 0>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ mcasp0: audio-controller@2b00000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x00 0x02b00000 0x00 0x2000>,
+ <0x00 0x02b08000 0x00 0x400>;
+ reg-names = "mpu", "dat";
+ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 190 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 190 0>;
+ assigned-clock-parents = <&k3_clks 190 2>;
+ power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ mcasp1: audio-controller@2b10000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x00 0x02b10000 0x00 0x2000>,
+ <0x00 0x02b18000 0x00 0x400>;
+ reg-names = "mpu", "dat";
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 191 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 191 0>;
+ assigned-clock-parents = <&k3_clks 191 2>;
+ power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ mcasp2: audio-controller@2b20000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x00 0x02b20000 0x00 0x2000>,
+ <0x00 0x02b28000 0x00 0x400>;
+ reg-names = "mpu", "dat";
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 192 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 192 0>;
+ assigned-clock-parents = <&k3_clks 192 2>;
+ power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
};
diff --git a/arch/arm/dts/k3-am62a-mcu.dtsi b/arch/arm/dts/k3-am62a-mcu.dtsi
index 6d1e501..a6d16a9 100644
--- a/arch/arm/dts/k3-am62a-mcu.dtsi
+++ b/arch/arm/dts/k3-am62a-mcu.dtsi
@@ -15,6 +15,51 @@
status = "disabled";
};
+ /*
+ * The MCU domain timer interrupts are routed only to the ESM module,
+ * and not currently available for Linux. The MCU domain timers are
+ * of limited use without interrupts, and likely reserved by the ESM.
+ */
+ mcu_timer0: timer@4800000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4800000 0x00 0x400>;
+ clocks = <&k3_clks 35 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer1: timer@4810000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4810000 0x00 0x400>;
+ clocks = <&k3_clks 48 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer2: timer@4820000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4820000 0x00 0x400>;
+ clocks = <&k3_clks 49 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer3: timer@4830000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4830000 0x00 0x400>;
+ clocks = <&k3_clks 50 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
mcu_uart0: serial@4a00000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a00000 0x00 0x100>;
@@ -36,4 +81,90 @@
clock-names = "fck";
status = "disabled";
};
+
+ mcu_spi0: spi@4b00000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x04b00000 0x00 0x400>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 147 0>;
+ status = "disabled";
+ };
+
+ mcu_spi1: spi@4b10000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x04b10000 0x00 0x400>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 148 0>;
+ status = "disabled";
+ };
+
+ mcu_gpio_intr: interrupt-controller@4210000 {
+ compatible = "ti,sci-intr";
+ reg = <0x00 0x04210000 0x00 0x200>;
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <5>;
+ ti,interrupt-ranges = <0 104 4>;
+ };
+
+ mcu_gpio0: gpio@4201000 {
+ compatible = "ti,am64-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x04201000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&mcu_gpio_intr>;
+ interrupts = <30>, <31>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <24>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 79 0>;
+ clock-names = "gpio";
+ status = "disabled";
+ };
+
+ mcu_rti0: watchdog@4880000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x04880000 0x00 0x100>;
+ clocks = <&k3_clks 131 0>;
+ power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 131 0>;
+ assigned-clock-parents = <&k3_clks 131 2>;
+ /* Tightly coupled to M4F */
+ status = "reserved";
+ };
+
+ mcu_mcan0: can@4e08000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x4e08000 0x00 0x200>,
+ <0x00 0x4e00000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 188 6>, <&k3_clks 188 1>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ mcu_mcan1: can@4e18000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x4e18000 0x00 0x200>,
+ <0x00 0x4e10000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 189 6>, <&k3_clks 189 1>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
};
diff --git a/arch/arm/dts/k3-am62a-thermal.dtsi b/arch/arm/dts/k3-am62a-thermal.dtsi
new file mode 100644
index 0000000..85ce545
--- /dev/null
+++ b/arch/arm/dts/k3-am62a-thermal.dtsi
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+ main0_thermal: main0-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&wkup_vtm0 0>;
+
+ trips {
+ main0_crit: main0-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main1_thermal: main1-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&wkup_vtm0 1>;
+
+ trips {
+ main1_crit: main1-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main2_thermal: main2-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&wkup_vtm0 2>;
+
+ trips {
+ main2_crit: main2-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-am62a-wakeup.dtsi b/arch/arm/dts/k3-am62a-wakeup.dtsi
index 99afac4..4e8279f 100644
--- a/arch/arm/dts/k3-am62a-wakeup.dtsi
+++ b/arch/arm/dts/k3-am62a-wakeup.dtsi
@@ -31,7 +31,7 @@
wkup_i2c0: i2c@2b200000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x02b200000 0x00 0x100>;
+ reg = <0x00 0x2b200000 0x00 0x100>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -51,4 +51,23 @@
wakeup-source;
status = "disabled";
};
+
+ wkup_rti0: watchdog@2b000000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2b000000 0x00 0x100>;
+ clocks = <&k3_clks 132 0>;
+ power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 132 0>;
+ assigned-clock-parents = <&k3_clks 132 2>;
+ /* Used by DM firmware */
+ status = "reserved";
+ };
+
+ wkup_vtm0: temperature-sensor@b00000 {
+ compatible = "ti,j7200-vtm";
+ reg = <0x00 0xb00000 0x00 0x400>,
+ <0x00 0xb01000 0x00 0x400>;
+ power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
+ #thermal-sensor-cells = <1>;
+ };
};
diff --git a/arch/arm/dts/k3-am62a.dtsi b/arch/arm/dts/k3-am62a.dtsi
index 6eb87c3..61a210e 100644
--- a/arch/arm/dts/k3-am62a.dtsi
+++ b/arch/arm/dts/k3-am62a.dtsi
@@ -8,9 +8,10 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
+#include "k3-pinctrl.h"
+
/ {
model = "Texas Instruments K3 AM62A SoC";
compatible = "ti,am62a7";
@@ -114,6 +115,8 @@
<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
};
};
+
+ #include "k3-am62a-thermal.dtsi"
};
/* Now include the peripherals for each bus segments */
diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts
index bbbd9e5..bc05dcb 100644
--- a/arch/arm/dts/k3-am62a7-r5-sk.dts
+++ b/arch/arm/dts/k3-am62a7-r5-sk.dts
@@ -7,7 +7,6 @@
#include "k3-am62a7-sk.dts"
#include "k3-am62a-ddr-1866mhz-32bit.dtsi"
#include "k3-am62a-ddr.dtsi"
-#include "k3-am62a-sk-binman.dtsi"
#include "k3-am62a7-sk-u-boot.dtsi"
@@ -15,33 +14,6 @@
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
- serial0 = &wkup_uart0;
- serial3 = &main_uart1;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
-
- memory@80000000 {
- device_type = "memory";
- /* 4G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
- <0x00000008 0x80000000 0x00000000 0x80000000>;
- bootph-pre-ram;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
- alignment = <0x1000>;
- no-map;
- };
};
a53_0: a53@0 {
@@ -81,67 +53,39 @@
ti,secure-host;
};
-&cbass_main {
- sa3_secproxy: secproxy@44880000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg = <0x00 0x44880000 0x00 0x20000>,
- <0x0 0x44860000 0x0 0x20000>,
- <0x0 0x43600000 0x0 0x10000>;
- reg-names = "rt", "scfg", "target_data";
- bootph-pre-ram;
- };
+&secure_proxy_sa3 {
+ /* Needed for initial handshake with ROM */
+ status = "okay";
+ bootph-pre-ram;
+};
+&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
- <&sa3_secproxy 0>;
+ <&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
};
-&mcu_pmx0 {
- status = "okay";
+&wkup_uart0_pins_default {
bootph-pre-ram;
-
- wkup_uart0_pins_default: wkup-uart0-pins-default {
- pinctrl-single,pins = <
- AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */
- AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */
- AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */
- AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */
- >;
- bootph-pre-ram;
- };
};
-&main_pmx0 {
+&main_uart1_pins_default {
bootph-pre-ram;
- main_uart1_pins_default: main-uart1-pins-default {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */
- AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */
- AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
- AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
- >;
- bootph-pre-ram;
- };
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
bootph-pre-ram;
};
/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart1_pins_default>;
status = "okay";
bootph-pre-ram;
};
diff --git a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi
index cf938c4..31b89b4 100644
--- a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi
@@ -4,137 +4,186 @@
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include "k3-am62a-sk-binman.dtsi"
+
/ {
chosen {
stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
+ tick-timer = &main_timer0;
};
memory@80000000 {
- bootph-pre-ram;
+ bootph-all;
};
};
-&cbass_main{
- bootph-pre-ram;
+&main_timer0 {
+ bootph-all;
+};
- timer1: timer@2400000 {
- compatible = "ti,omap5430-timer";
- reg = <0x00 0x2400000 0x00 0x80>;
- ti,timer-alwon;
- clock-frequency = <25000000>;
- bootph-pre-ram;
- };
+&cbass_main {
+ bootph-all;
};
&dmss {
- bootph-pre-ram;
+ bootph-all;
};
&secure_proxy_main {
- bootph-pre-ram;
+ bootph-all;
};
&dmsc {
- bootph-pre-ram;
+ bootph-all;
};
&k3_pds {
- bootph-pre-ram;
+ bootph-all;
};
&k3_clks {
- bootph-pre-ram;
+ bootph-all;
};
&k3_reset {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_conf {
- bootph-pre-ram;
+ bootph-all;
};
&chipid {
- bootph-pre-ram;
+ bootph-all;
};
&main_pmx0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_uart0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_uart0_pins_default {
- bootph-pre-ram;
-};
-
-&main_uart1 {
- bootph-pre-ram;
+ bootph-all;
};
&cbass_mcu {
- bootph-pre-ram;
+ bootph-all;
};
&cbass_wakeup {
- bootph-pre-ram;
+ bootph-all;
};
&mcu_pmx0 {
- bootph-pre-ram;
-};
-
-&wkup_uart0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_gpio0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_i2c0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_i2c0_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&main_i2c1 {
- bootph-pre-ram;
+ bootph-all;
};
&main_i2c1_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&exp1 {
- bootph-pre-ram;
+ bootph-all;
};
&sdhci1 {
- bootph-pre-ram;
+ bootph-all;
};
&main_mmc1_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&k3_reset {
- bootph-pre-ram;
+ bootph-all;
};
&dmsc {
- bootph-pre-ram;
+ bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- bootph-pre-ram;
+ bootph-all;
};
};
&vdd_mmc1 {
- bootph-pre-ram;
+ bootph-all;
+};
+
+&main_bcdma {
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>,
+ <0x00 0x48600000 0x00 0x8000>,
+ <0x00 0x484a4000 0x00 0x2000>,
+ <0x00 0x484c2000 0x00 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
+ "ringrt" , "cfg", "tchan", "rchan";
+ bootph-all;
+};
+
+&main_pktdma {
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x20000>,
+ <0x00 0x4b800000 0x00 0x200000>,
+ <0x00 0x485e0000 0x00 0x10000>,
+ <0x00 0x484a0000 0x00 0x2000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x1000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+ "cfg", "tchan", "rchan", "rflow";
+ bootph-all;
+};
+
+&main_mdio1_pins_default {
+ bootph-all;
+};
+
+&cpsw3g_mdio {
+ bootph-all;
+};
+
+&cpsw3g_phy0 {
+ bootph-all;
+};
+
+&main_rgmii1_pins_default {
+ bootph-all;
+};
+
+&phy_gmii_sel {
+ bootph-all;
+};
+
+&cpsw3g {
+ bootph-all;
+ ethernet-ports {
+ bootph-all;
+ };
+};
+
+&cpsw_port1 {
+ bootph-all;
};
diff --git a/arch/arm/dts/k3-am62a7-sk.dts b/arch/arm/dts/k3-am62a7-sk.dts
index 270e669..8f64ac2 100644
--- a/arch/arm/dts/k3-am62a7-sk.dts
+++ b/arch/arm/dts/k3-am62a7-sk.dts
@@ -9,15 +9,17 @@
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am62a7.dtsi"
-#include "k3-am62a-sk-binman.dtsi"
/ {
- compatible = "ti,am62a7-sk", "ti,am62a7";
+ compatible = "ti,am62a7-sk", "ti,am62a7";
model = "Texas Instruments AM62A7 SK";
aliases {
+ serial0 = &wkup_uart0;
serial2 = &main_uart0;
+ serial3 = &main_uart1;
mmc1 = &sdhci1;
};
@@ -77,10 +79,10 @@
regulator-boot-on;
};
- vcc_3v3_sys: regulator-2 {
+ vcc_3v3_main: regulator-2 {
/* output of LM5141-Q1 */
compatible = "regulator-fixed";
- regulator-name = "vcc_3v3_sys";
+ regulator-name = "vcc_3v3_main";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vmain_pd>;
@@ -99,6 +101,17 @@
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
};
+ vcc_3v3_sys: regulator-4 {
+ /* output of TPS222965DSGT */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_sys";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_main>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -112,38 +125,100 @@
default-state = "off";
};
};
+
+ tlv320_mclk: clk-0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12288000>;
+ };
+
+ codec_audio: sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "AM62Ax-SKEVM";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line In",
+ "Microphone", "Microphone Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In",
+ "MIC3R", "Microphone Jack",
+ "Microphone Jack", "Mic Bias";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound_master>;
+ simple-audio-card,frame-master = <&sound_master>;
+ simple-audio-card,bitclock-inversion;
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp1>;
+ };
+
+ sound_master: simple-audio-card,codec {
+ sound-dai = <&tlv320aic3106>;
+ clocks = <&tlv320_mclk>;
+ };
+ };
+};
+
+&mcu_pmx0 {
+ wkup_uart0_pins_default: wkup-uart0-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (C9) WKUP_UART0_RXD */
+ AM62AX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (E9) WKUP_UART0_TXD */
+ AM62AX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C10) WKUP_UART0_CTSn */
+ AM62AX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_RTSn */
+ >;
+ };
+};
+
+/* WKUP UART0 is used for DM firmware logs */
+&wkup_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+ status = "reserved";
};
&main_pmx0 {
- main_uart0_pins_default: main-uart0-pins-default {
+ main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
- AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
- AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
+ AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */
+ AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */
>;
};
- main_i2c0_pins_default: main-i2c0-pins-default {
+ main_uart1_pins_default: main-uart1-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x01e8, PIN_INPUT, 1) /* (C17) I2C1_SCL.UART1_RXD */
+ AM62AX_IOPAD(0x01ec, PIN_OUTPUT, 1) /* (E17) I2C1_SDA.UART1_TXD */
+ AM62AX_IOPAD(0x0194, PIN_INPUT, 2) /* (C19) MCASP0_AXR3.UART1_CTSn */
+ AM62AX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (B19) MCASP0_AXR2.UART1_RTSn */
+ >;
+ };
+
+ main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
>;
};
- main_i2c1_pins_default: main-i2c1-pins-default {
+ main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
>;
};
- main_i2c2_pins_default: main-i2c2-pins-default {
+ main_i2c2_pins_default: main-i2c2-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
>;
};
- main_mmc1_pins_default: main-mmc1-pins-default {
+ main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
@@ -155,11 +230,64 @@
>;
};
- usr_led_pins_default: usr-led-pins-default {
+ usr_led_pins_default: usr-led-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */
>;
};
+
+ main_usb1_pins_default: main-usb1-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */
+ >;
+ };
+
+ main_mdio1_pins_default: main-mdio1-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */
+ AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */
+ >;
+ };
+
+ main_rgmii1_pins_default: main-rgmii1-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */
+ AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */
+ AM62AX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */
+ AM62AX_IOPAD(0x158, PIN_INPUT, 0) /* (V14) RGMII1_RD3 */
+ AM62AX_IOPAD(0x148, PIN_INPUT, 0) /* (AA16) RGMII1_RXC */
+ AM62AX_IOPAD(0x144, PIN_INPUT, 0) /* (AA15) RGMII1_RX_CTL */
+ AM62AX_IOPAD(0x134, PIN_INPUT, 0) /* (Y17) RGMII1_TD0 */
+ AM62AX_IOPAD(0x138, PIN_INPUT, 0) /* (V16) RGMII1_TD1 */
+ AM62AX_IOPAD(0x13c, PIN_INPUT, 0) /* (Y16) RGMII1_TD2 */
+ AM62AX_IOPAD(0x140, PIN_INPUT, 0) /* (AA17) RGMII1_TD3 */
+ AM62AX_IOPAD(0x130, PIN_INPUT, 0) /* (AB17) RGMII1_TXC */
+ AM62AX_IOPAD(0x12c, PIN_INPUT, 0) /* (W16) RGMII1_TX_CTL */
+ >;
+ };
+
+ main_mcasp1_pins_default: main-mcasp1-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x090, PIN_INPUT, 2) /* (L19) GPMC0_BE0n_CLE.MCASP1_ACLKX */
+ AM62AX_IOPAD(0x098, PIN_INPUT, 2) /* (R18) GPMC0_WAIT0.MCASP1_AFSX */
+ AM62AX_IOPAD(0x08c, PIN_OUTPUT, 2) /* (K19) GPMC0_WEn.MCASP1_AXR0 */
+ AM62AX_IOPAD(0x084, PIN_INPUT, 2) /* (L18) GPMC0_ADVn_ALE.MCASP1_AXR2 */
+ >;
+ };
+};
+
+&mcu_pmx0 {
+ status = "okay";
+
+ pmic_irq_pins_default: pmic-irq-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_MCU_IOPAD(0x000, PIN_INPUT, 7) /* (E11) MCU_GPIO0_0 */
+ >;
+ };
+};
+
+&mcu_gpio0 {
+ status = "okay";
};
&main_i2c0 {
@@ -167,13 +295,112 @@
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
+
+ typec_pd0: usb-power-controller@3f {
+ compatible = "ti,tps6598x";
+ reg = <0x3f>;
+
+ connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ self-powered;
+ data-role = "dual";
+ power-role = "sink";
+ port {
+ usb_con_hs: endpoint {
+ remote-endpoint = <&usb0_hs_ep>;
+ };
+ };
+ };
+ };
+
+ tps659312: pmic@48 {
+ compatible = "ti,tps6593-q1";
+ reg = <0x48>;
+ ti,primary-pmic;
+ system-power-controller;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins_default>;
+ interrupt-parent = <&mcu_gpio0>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+
+ buck123-supply = <&vcc_3v3_sys>;
+ buck4-supply = <&vcc_3v3_sys>;
+ buck5-supply = <&vcc_3v3_sys>;
+ ldo1-supply = <&vcc_3v3_sys>;
+ ldo2-supply = <&vcc_3v3_sys>;
+ ldo3-supply = <&buck5>;
+ ldo4-supply = <&vcc_3v3_sys>;
+
+ regulators {
+ buck123: buck123 {
+ regulator-name = "vcc_core";
+ regulator-min-microvolt = <715000>;
+ regulator-max-microvolt = <895000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck4: buck4 {
+ regulator-name = "vcc_1v1";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5: buck5 {
+ regulator-name = "vcc_1v8_sys";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: ldo1 {
+ regulator-name = "vddshv5_sdio";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2: ldo2 {
+ regulator-name = "vpp_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3: ldo3 {
+ regulator-name = "vcc_0v85";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4: ldo4 {
+ regulator-name = "vdda_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
};
&main_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
- clock-frequency = <400000>;
+ clock-frequency = <100000>;
exp1: gpio@22 {
compatible = "ti,tca6424";
@@ -194,6 +421,19 @@
"MCASP1_FET_SEL", "UART1_FET_SEL",
"PD_I2C_IRQ", "IO_EXP_TEST_LED";
};
+
+ tlv320aic3106: audio-codec@1b {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3106";
+ reg = <0x1b>;
+ ai3x-micbias-vg = <1>; /* 2.0V */
+
+ /* Regulators */
+ AVDD-supply = <&vcc_3v3_sys>;
+ IOVDD-supply = <&vcc_3v3_sys>;
+ DRVDD-supply = <&vcc_3v3_sys>;
+ DVDD-supply = <&buck5>;
+ };
};
&sdhci1 {
@@ -223,3 +463,84 @@
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
+
+/* Main UART1 is used for TIFS firmware logs */
+&main_uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
+ status = "reserved";
+};
+
+&usbss0 {
+ status = "okay";
+ ti,vbus-divider;
+};
+
+&usb0 {
+ usb-role-switch;
+
+ port {
+ usb0_hs_ep: endpoint {
+ remote-endpoint = <&usb_con_hs>;
+ };
+ };
+};
+
+&usbss1 {
+ status = "okay";
+};
+
+&usb1 {
+ dr_mode = "host";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usb1_pins_default>;
+};
+
+&cpsw3g {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_rgmii1_pins_default>;
+};
+
+&cpsw_port1 {
+ status = "okay";
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw_port2 {
+ status = "disabled";
+};
+
+&cpsw3g_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mdio1_pins_default>;
+
+ cpsw3g_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,min-output-impedance;
+ };
+};
+
+&mcasp1 {
+ status = "okay";
+ #sound-dai-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcasp1_pins_default>;
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 0 2 0
+ 0 0 0 0
+ 0 0 0 0
+ 0 0 0 0
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
diff --git a/arch/arm/dts/k3-am62a7.dtsi b/arch/arm/dts/k3-am62a7.dtsi
index 331d89f..58f1c43 100644
--- a/arch/arm/dts/k3-am62a7.dtsi
+++ b/arch/arm/dts/k3-am62a7.dtsi
@@ -95,8 +95,9 @@
L2_0: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-level = <2>;
- cache-size = <0x40000>;
+ cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
};
diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi
index 5e8036f..0df54a7 100644
--- a/arch/arm/dts/k3-am64-main.dtsi
+++ b/arch/arm/dts/k3-am64-main.dtsi
@@ -44,11 +44,28 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x43000000 0x20000>;
+ chipid@14 {
+ compatible = "ti,am654-chipid";
+ reg = <0x00000014 0x4>;
+ };
+
serdes_ln_ctrl: mux-controller {
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
};
+
+ phy_gmii_sel: phy@4044 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x4044 0x8>;
+ #phy-cells = <1>;
+ };
+
+ epwm_tbclk: clock-controller@4140 {
+ compatible = "ti,am64-epwm-tbclk";
+ reg = <0x4130 0x4>;
+ #clock-cells = <1>;
+ };
};
gic500: interrupt-controller@1800000 {
@@ -203,29 +220,154 @@
pinctrl-single,function-mask = <0xffffffff>;
};
- main_conf: syscon@43000000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x00 0x43000000 0x00 0x20000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00 0x00 0x43000000 0x20000>;
+ main_timer0: timer@2400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2400000 0x00 0x400>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 36 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 36 1>;
+ assigned-clock-parents = <&k3_clks 36 2>;
+ power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
- chipid@14 {
- compatible = "ti,am654-chipid";
- reg = <0x00000014 0x4>;
- };
+ main_timer1: timer@2410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2410000 0x00 0x400>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 37 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 37 1>;
+ assigned-clock-parents = <&k3_clks 37 2>;
+ power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
- phy_gmii_sel: phy@4044 {
- compatible = "ti,am654-phy-gmii-sel";
- reg = <0x4044 0x8>;
- #phy-cells = <1>;
- };
+ main_timer2: timer@2420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2420000 0x00 0x400>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 38 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 38 1>;
+ assigned-clock-parents = <&k3_clks 38 2>;
+ power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
- epwm_tbclk: clock@4140 {
- compatible = "ti,am64-epwm-tbclk", "syscon";
- reg = <0x4130 0x4>;
- #clock-cells = <1>;
- };
+ main_timer3: timer@2430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2430000 0x00 0x400>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 39 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 39 1>;
+ assigned-clock-parents = <&k3_clks 39 2>;
+ power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer4: timer@2440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2440000 0x00 0x400>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 40 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 40 1>;
+ assigned-clock-parents = <&k3_clks 40 2>;
+ power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer5: timer@2450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2450000 0x00 0x400>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 41 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 41 1>;
+ assigned-clock-parents = <&k3_clks 41 2>;
+ power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer6: timer@2460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2460000 0x00 0x400>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 42 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 42 1>;
+ assigned-clock-parents = <&k3_clks 42 2>;
+ power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer7: timer@2470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2470000 0x00 0x400>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 43 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 43 1>;
+ assigned-clock-parents = <&k3_clks 43 2>;
+ power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer8: timer@2480000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2480000 0x00 0x400>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 44 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 44 1>;
+ assigned-clock-parents = <&k3_clks 44 2>;
+ power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer9: timer@2490000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2490000 0x00 0x400>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 45 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 45 1>;
+ assigned-clock-parents = <&k3_clks 45 2>;
+ power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer10: timer@24a0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24a0000 0x00 0x400>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 46 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 46 1>;
+ assigned-clock-parents = <&k3_clks 46 2>;
+ power-domains = <&k3_pds 46 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer11: timer@24b0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24b0000 0x00 0x400>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 47 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 47 1>;
+ assigned-clock-parents = <&k3_clks 47 2>;
+ power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_esm: esm@420000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x420000 0x00 0x1000>;
+ ti,esm-pins = <160>, <161>;
};
main_uart0: serial@2800000 {
@@ -233,7 +375,6 @@
reg = <0x00 0x02800000 0x00 0x100>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 146 0>;
clock-names = "fclk";
@@ -245,7 +386,6 @@
reg = <0x00 0x02810000 0x00 0x100>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 152 0>;
clock-names = "fclk";
@@ -257,7 +397,6 @@
reg = <0x00 0x02820000 0x00 0x100>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 153 0>;
clock-names = "fclk";
@@ -269,7 +408,6 @@
reg = <0x00 0x02830000 0x00 0x100>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 154 0>;
clock-names = "fclk";
@@ -281,7 +419,6 @@
reg = <0x00 0x02840000 0x00 0x100>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 155 0>;
clock-names = "fclk";
@@ -293,7 +430,6 @@
reg = <0x00 0x02850000 0x00 0x100>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 156 0>;
clock-names = "fclk";
@@ -305,7 +441,6 @@
reg = <0x00 0x02860000 0x00 0x100>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 158 0>;
clock-names = "fclk";
@@ -590,7 +725,7 @@
pinctrl-single,function-mask = <0x000107ff>;
};
- usbss0: cdns-usb@f900000{
+ usbss0: cdns-usb@f900000 {
compatible = "ti,am64-usb";
reg = <0x00 0xf900000 0x00 0x100>;
power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
@@ -601,7 +736,7 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
- usb0: usb@f400000{
+ usb0: usb@f400000 {
compatible = "cdns,usb3";
reg = <0x00 0xf400000 0x00 0x10000>,
<0x00 0xf410000 0x00 0x10000>,
@@ -630,6 +765,7 @@
assigned-clock-parents = <&k3_clks 0 3>;
assigned-clock-rates = <60000000>;
clock-names = "fck";
+ status = "disabled";
adc {
#io-channel-cells = <1>;
@@ -659,6 +795,7 @@
assigned-clock-parents = <&k3_clks 75 7>;
assigned-clock-rates = <166666666>;
power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
};
@@ -676,6 +813,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
mailbox0_cluster3: mailbox@29030000 {
@@ -686,6 +824,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
mailbox0_cluster4: mailbox@29040000 {
@@ -696,6 +835,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
mailbox0_cluster5: mailbox@29050000 {
@@ -706,6 +846,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
mailbox0_cluster6: mailbox@29060000 {
@@ -715,6 +856,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
mailbox0_cluster7: mailbox@29070000 {
@@ -724,6 +866,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
main_r5fss0: r5fss@78000000 {
@@ -1392,4 +1535,12 @@
clock-names = "fck";
status = "disabled";
};
+
+ main_vtm0: temperature-sensor@b00000 {
+ compatible = "ti,j7200-vtm";
+ reg = <0x00 0xb00000 0x00 0x400>,
+ <0x00 0xb01000 0x00 0x400>;
+ power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
+ #thermal-sensor-cells = <1>;
+ };
};
diff --git a/arch/arm/dts/k3-am64-mcu.dtsi b/arch/arm/dts/k3-am64-mcu.dtsi
index 38ddf0b..686d497 100644
--- a/arch/arm/dts/k3-am64-mcu.dtsi
+++ b/arch/arm/dts/k3-am64-mcu.dtsi
@@ -6,11 +6,55 @@
*/
&cbass_mcu {
+ /*
+ * The MCU domain timer interrupts are routed only to the ESM module,
+ * and not currently available for Linux. The MCU domain timers are
+ * of limited use without interrupts, and likely reserved by the ESM.
+ */
+ mcu_timer0: timer@4800000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4800000 0x00 0x400>;
+ clocks = <&k3_clks 35 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer1: timer@4810000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4810000 0x00 0x400>;
+ clocks = <&k3_clks 48 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer2: timer@4820000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4820000 0x00 0x400>;
+ clocks = <&k3_clks 49 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer3: timer@4830000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4830000 0x00 0x400>;
+ clocks = <&k3_clks 50 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
mcu_uart0: serial@4a00000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a00000 0x00 0x100>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
- current-speed = <115200>;
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 149 0>;
clock-names = "fclk";
@@ -21,7 +65,6 @@
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a10000 0x00 0x100>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- current-speed = <115200>;
power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 160 0>;
clock-names = "fclk";
@@ -109,4 +152,10 @@
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
+
+ mcu_esm: esm@4100000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x4100000 0x00 0x1000>;
+ ti,esm-pins = <0>, <1>;
+ };
};
diff --git a/arch/arm/dts/k3-am64-thermal.dtsi b/arch/arm/dts/k3-am64-thermal.dtsi
new file mode 100644
index 0000000..036db56
--- /dev/null
+++ b/arch/arm/dts/k3-am64-thermal.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+ main0_thermal: main0-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&main_vtm0 0>;
+
+ trips {
+ main0_crit: main0-crit {
+ temperature = <105000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main1_thermal: main1-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&main_vtm0 1>;
+
+ trips {
+ main1_crit: main1-crit {
+ temperature = <105000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-am64.dtsi b/arch/arm/dts/k3-am64.dtsi
index c858725..8e9c2bc 100644
--- a/arch/arm/dts/k3-am64.dtsi
+++ b/arch/arm/dts/k3-am64.dtsi
@@ -8,9 +8,10 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
+#include "k3-pinctrl.h"
+
/ {
model = "Texas Instruments K3 AM642 SoC";
compatible = "ti,am642";
@@ -18,22 +19,6 @@
#address-cells = <2>;
#size-cells = <2>;
- aliases {
- serial0 = &mcu_uart0;
- serial1 = &mcu_uart1;
- serial2 = &main_uart0;
- serial3 = &main_uart1;
- serial4 = &main_uart2;
- serial5 = &main_uart3;
- serial6 = &main_uart4;
- serial7 = &main_uart5;
- serial8 = &main_uart6;
- ethernet0 = &cpsw_port1;
- ethernet1 = &cpsw_port2;
- mmc0 = &sdhci0;
- mmc1 = &sdhci1;
- };
-
chosen { };
firmware {
@@ -69,6 +54,7 @@
<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
+ <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
<0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
@@ -105,6 +91,8 @@
ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
};
};
+
+ #include "k3-am64-thermal.dtsi"
};
/* Now include the peripherals for each bus segments */
diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
index 73577e8..b843078 100644
--- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
@@ -7,124 +7,178 @@
/ {
chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
+ tick-timer = &main_timer0;
};
memory@80000000 {
- bootph-pre-ram;
+ bootph-all;
};
};
-&cbass_main{
- bootph-pre-ram;
- timer1: timer@2400000 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x2400000 0x0 0x80>;
- ti,timer-alwon;
- clock-frequency = <200000000>;
- bootph-pre-ram;
- };
+&cbass_main {
+ bootph-all;
+};
+
+&main_timer0 {
+ bootph-all;
+ clock-frequency = <200000000>;
};
&main_conf {
- bootph-pre-ram;
+ bootph-all;
chipid@14 {
- bootph-pre-ram;
+ bootph-all;
};
};
&main_pmx0 {
- bootph-pre-ram;
- main_i2c0_pins_default: main-i2c0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
- AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
- >;
- };
+ bootph-all;
+};
+
+&main_i2c0_pins_default {
+ bootph-all;
};
&main_i2c0 {
- status = "okay";
- bootph-pre-ram;
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
+ bootph-all;
+};
+
+&main_uart0_pins_default {
+ bootph-all;
};
&main_uart0 {
- bootph-pre-ram;
+ bootph-all;
+};
+
+&main_usb0_pins_default {
+ bootph-all;
};
&usb0 {
dr_mode="peripheral";
- bootph-pre-ram;
+ bootph-all;
};
&usbss0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_mmc1_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&main_usb0_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&dmss {
- bootph-pre-ram;
+ bootph-all;
};
&secure_proxy_main {
- bootph-pre-ram;
+ bootph-all;
};
&dmsc {
- bootph-pre-ram;
+ bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- bootph-pre-ram;
+ bootph-all;
};
};
&k3_pds {
- bootph-pre-ram;
+ bootph-all;
};
&k3_clks {
- bootph-pre-ram;
+ bootph-all;
};
&k3_reset {
- bootph-pre-ram;
+ bootph-all;
};
&sdhci0 {
- bootph-pre-ram;
+ bootph-all;
+};
+
+&main_mmc1_pins_default {
+ bootph-all;
};
&sdhci1 {
- bootph-pre-ram;
+ bootph-all;
+};
+
+&inta_main_dmss {
+ bootph-all;
+};
+
+&main_bcdma {
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>,
+ <0x00 0x48600000 0x00 0x8000>,
+ <0x00 0x484a4000 0x00 0x2000>,
+ <0x00 0x484c2000 0x00 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
+ "cfg", "tchan", "rchan";
+};
+
+&main_pktdma {
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x40000>,
+ <0x00 0x4b800000 0x00 0x400000>,
+ <0x00 0x485e0000 0x00 0x20000>,
+ <0x00 0x484a0000 0x00 0x4000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x4000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg",
+ "tchan", "rchan", "rflow";
+ bootph-all;
+};
+
+&mdio1_pins_default {
+ bootph-all;
+};
+
+&cpsw3g_mdio {
+ bootph-all;
+};
+
+&cpsw3g_phy0 {
+ bootph-all;
+};
+
+&rgmii1_pins_default {
+ bootph-all;
+};
+
+&rgmii2_pins_default {
+ bootph-all;
};
&cpsw3g {
- reg = <0x0 0x8000000 0x0 0x200000>,
- <0x0 0x43000200 0x0 0x8>;
- reg-names = "cpsw_nuss", "mac_efuse";
- /delete-property/ ranges;
- pinctrl-0 = <&mdio1_pins_default /* HACK: as MDIO driver is not DM enabled */
- &rgmii1_pins_default
- &rgmii2_pins_default>;
+ bootph-all;
- cpsw-phy-sel@04044 {
- compatible = "ti,am64-phy-gmii-sel";
- reg = <0x0 0x43004044 0x0 0x8>;
+ ethernet-ports {
+ bootph-all;
};
};
+&phy_gmii_sel {
+ bootph-all;
+};
+
+&cpsw_port1 {
+ bootph-all;
+};
+
&cpsw_port2 {
status = "disabled";
};
diff --git a/arch/arm/dts/k3-am642-evm.dts b/arch/arm/dts/k3-am642-evm.dts
index 39feea7..b4a1f73 100644
--- a/arch/arm/dts/k3-am642-evm.dts
+++ b/arch/arm/dts/k3-am642-evm.dts
@@ -6,26 +6,38 @@
/dts-v1/;
#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"
+#include "k3-serdes.h"
+
/ {
compatible = "ti,am642-evm", "ti,am642";
model = "Texas Instruments AM642 EVM";
chosen {
- stdout-path = "serial2:115200n8";
- bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+ stdout-path = &main_uart0;
+ };
+
+ aliases {
+ serial0 = &mcu_uart0;
+ serial1 = &main_uart1;
+ serial2 = &main_uart0;
+ serial3 = &main_uart3;
+ i2c0 = &main_i2c0;
+ i2c1 = &main_i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ ethernet0 = &cpsw_port1;
+ ethernet1 = &cpsw_port2;
};
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
-
};
reserved-memory {
@@ -94,7 +106,7 @@
};
};
- evm_12v0: fixedregulator-evm12v0 {
+ evm_12v0: regulator-0 {
/* main DC jack */
compatible = "regulator-fixed";
regulator-name = "evm_12v0";
@@ -104,7 +116,7 @@
regulator-boot-on;
};
- vsys_5v0: fixedregulator-vsys5v0 {
+ vsys_5v0: regulator-1 {
/* output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
@@ -115,7 +127,7 @@
regulator-boot-on;
};
- vsys_3v3: fixedregulator-vsys3v3 {
+ vsys_3v3: regulator-2 {
/* output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_3v3";
@@ -126,7 +138,7 @@
regulator-boot-on;
};
- vdd_mmc1: fixed-regulator-sd {
+ vdd_mmc1: regulator-3 {
/* TPS2051BD */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
@@ -138,7 +150,7 @@
gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
};
- vddb: fixedregulator-vddb {
+ vddb: regulator-4 {
compatible = "regulator-fixed";
regulator-name = "vddb_3v3_display";
regulator-min-microvolt = <3300000>;
@@ -148,6 +160,20 @@
regulator-boot-on;
};
+ vtt_supply: regulator-5 {
+ compatible = "regulator-fixed";
+ regulator-name = "vtt";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ddr_vtt_pins_default>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vsys_3v3>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
leds {
compatible = "gpio-leds";
@@ -201,7 +227,7 @@
};
&main_pmx0 {
- main_mmc1_pins_default: main-mmc1-pins-default {
+ main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
@@ -215,7 +241,16 @@
>;
};
- main_uart0_pins_default: main-uart0-pins-default {
+ main_uart1_pins_default: main-uart1-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
+ AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
+ AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
+ AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
+ >;
+ };
+
+ main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
@@ -224,7 +259,7 @@
>;
};
- main_spi0_pins_default: main-spi0-pins-default {
+ main_spi0_pins_default: main-spi0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
@@ -233,21 +268,28 @@
>;
};
- main_i2c1_pins_default: main-i2c1-pins-default {
+ main_i2c0_pins_default: main-i2c0-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
+ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
+ >;
+ };
+
+ main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
>;
};
- mdio1_pins_default: mdio1-pins-default {
+ mdio1_pins_default: mdio1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
>;
};
- rgmii1_pins_default: rgmii1-pins-default {
+ rgmii1_pins_default: rgmii1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
@@ -264,7 +306,7 @@
>;
};
- rgmii2_pins_default: rgmii2-pins-default {
+ rgmii2_pins_default: rgmii2-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
@@ -281,13 +323,13 @@
>;
};
- main_usb0_pins_default: main-usb0-pins-default {
+ main_usb0_pins_default: main-usb0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
- ospi0_pins_default: ospi0-pins-default {
+ ospi0_pins_default: ospi0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
@@ -303,36 +345,58 @@
>;
};
- main_ecap0_pins_default: main-ecap0-pins-default {
+ main_ecap0_pins_default: main-ecap0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
>;
};
- main_mcan0_pins_default: main-mcan0-pins-default {
+ main_mcan0_pins_default: main-mcan0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
>;
};
- main_mcan1_pins_default: main-mcan1-pins-default {
+ main_mcan1_pins_default: main-mcan1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
>;
};
+
+ ddr_vtt_pins_default: ddr-vtt-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
+ >;
+ };
};
&main_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
+ current-speed = <115200>;
};
/* main_uart1 is reserved for firmware usage */
&main_uart1 {
status = "reserved";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
+};
+
+&main_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ eeprom@50 {
+ /* AT24CM01 */
+ compatible = "atmel,24c1024";
+ reg = <0x50>;
+ };
};
&main_i2c1 {
@@ -425,8 +489,7 @@
&cpsw3g {
pinctrl-names = "default";
- pinctrl-0 = <&rgmii1_pins_default
- &rgmii2_pins_default>;
+ pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
};
&cpsw_port1 {
@@ -457,6 +520,7 @@
};
&ospi0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
@@ -471,10 +535,53 @@
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ospi.tiboot3";
+ reg = <0x0 0x100000>;
+ };
+
+ partition@100000 {
+ label = "ospi.tispl";
+ reg = <0x100000 0x200000>;
+ };
+
+ partition@300000 {
+ label = "ospi.u-boot";
+ reg = <0x300000 0x400000>;
+ };
+
+ partition@700000 {
+ label = "ospi.env";
+ reg = <0x700000 0x40000>;
+ };
+
+ partition@740000 {
+ label = "ospi.env.backup";
+ reg = <0x740000 0x40000>;
+ };
+
+ partition@800000 {
+ label = "ospi.rootfs";
+ reg = <0x800000 0x37c0000>;
+ };
+
+ partition@3fc0000 {
+ label = "ospi.phypattern";
+ reg = <0x3fc0000 0x40000>;
+ };
+ };
};
};
&mailbox0_cluster2 {
+ status = "okay";
+
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
@@ -486,11 +593,9 @@
};
};
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
&mailbox0_cluster4 {
+ status = "okay";
+
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
@@ -502,41 +607,35 @@
};
};
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
&mailbox0_cluster6 {
+ status = "okay";
+
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+ mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+ mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts
index b490641..64b3c3a 100644
--- a/arch/arm/dts/k3-am642-r5-evm.dts
+++ b/arch/arm/dts/k3-am642-r5-evm.dts
@@ -1,34 +1,20 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
*/
-/dts-v1/;
-
-#include "k3-am642.dtsi"
+#include "k3-am642-evm.dts"
#include "k3-am64-evm-ddr4-1600MTs.dtsi"
#include "k3-am64-ddr.dtsi"
-#include "k3-am64x-binman.dtsi"
+
+#include "k3-am642-evm-u-boot.dtsi"
/ {
- chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
-
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
- memory@80000000 {
- device_type = "memory";
- /* 2G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
-
- bootph-pre-ram;
- };
-
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
@@ -46,34 +32,16 @@
bootph-pre-ram;
};
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
- alignment = <0x1000>;
- no-map;
- };
- };
-
clk_200mhz: dummy-clock-200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
bootph-pre-ram;
};
+};
- vtt_supply: vtt-supply {
- compatible = "regulator-gpio";
- regulator-name = "vtt";
- regulator-min-microvolt = <0>;
- regulator-max-microvolt = <3300000>;
- gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
- states = <0 0x0 3300000 0x1>;
- bootph-pre-ram;
- };
+&vtt_supply {
+ bootph-pre-ram;
};
&cbass_main {
@@ -85,131 +53,16 @@
};
};
-&cbass_main {
- main_esm: esm@420000 {
- compatible = "ti,j721e-esm";
- reg = <0x0 0x420000 0x0 0x1000>;
- ti,esm-pins = <160>, <161>;
- bootph-pre-ram;
- };
+&main_esm {
+ bootph-pre-ram;
};
&cbass_mcu {
bootph-pre-ram;
- mcu_esm: esm@4100000 {
- compatible = "ti,j721e-esm";
- reg = <0x0 0x4100000 0x0 0x1000>;
- ti,esm-pins = <0>, <1>;
- bootph-pre-ram;
- };
};
-&main_pmx0 {
+&mcu_esm {
bootph-pre-ram;
- main_uart0_pins_default: main-uart0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
- AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
- AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
- AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
- >;
- };
-
- main_uart1_pins_default: main-uart1-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
- AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
- AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
- AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
- >;
- };
-
- main_mmc0_pins_default: main-mmc0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
- AM64X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
- AM64X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
- AM64X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
- AM64X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
- AM64X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
- AM64X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
- AM64X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
- AM64X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
- AM64X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
- AM64X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
- >;
- };
-
- main_mmc1_pins_default: main-mmc1-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
- AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
- AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
- AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
- AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
- AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
- AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
- AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
- >;
- };
-
- ddr_vtt_pins_default: ddr-vtt-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
- >;
- };
-
- main_usb0_pins_default: main-usb0-pins-default {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
- >;
- };
-
- mdio1_pins_default: mdio1-pins-default {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
- AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
- >;
- };
-
- rgmii1_pins_default: rgmii1-pins-default {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
- AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
- AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
- AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
- AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
- AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
- AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
- AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
- AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
- AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
- AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
- AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
- >;
- };
-
- rgmii2_pins_default: rgmii2-pins-default {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
- AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
- AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
- AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
- AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
- AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
- AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
- AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
- AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
- AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
- AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
- AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
- >;
- };
};
&dmsc {
@@ -221,65 +74,49 @@
ti,secure-host;
};
-&main_uart0 {
- /delete-property/ power-domains;
- /delete-property/ clocks;
- /delete-property/ clock-names;
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
- status = "okay";
-};
-
-&main_uart1 {
+&vtt_supply {
bootph-pre-ram;
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart1_pins_default>;
};
&memorycontroller {
vtt-supply = <&vtt_supply>;
- pinctrl-names = "default";
- pinctrl-0 = <&ddr_vtt_pins_default>;
};
&sdhci0 {
- /delete-property/ power-domains;
clocks = <&clk_200mhz>;
clock-names = "clk_xin";
- ti,driver-strength-ohm = <50>;
- disable-wp;
- pinctrl-0 = <&main_mmc0_pins_default>;
};
&sdhci1 {
- /delete-property/ power-domains;
clocks = <&clk_200mhz>;
clock-names = "clk_xin";
- ti,driver-strength-ohm = <50>;
- disable-wp;
- pinctrl-0 = <&main_mmc1_pins_default>;
};
&main_gpio0 {
bootph-pre-ram;
+};
+
+/* UART is initialized before SYSFW is started
+ * so we can't do any power-domain/clock operations.
+ * Delete clock/power-domain properties to avoid
+ * UART init failure
+ */
+&main_uart0 {
+ /delete-property/ power-domains;
+ /delete-property/ clocks;
+ /delete-property/ clock-names;
+};
+
+/* timer init is called as part of rproc_start() while
+ * starting System Firmware, so any clock/power-domain
+ * operations will fail as SYSFW is not yet up and running.
+ * Delete all clock/power-domain properties to avoid
+ * timer init failure.
+ * This is an always on timer at 20MHz.
+ */
+&main_timer0 {
+ /delete-property/ clocks;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
/delete-property/ power-domains;
};
-
-/* EEPROM might be read before SYSFW is available */
-&main_i2c0 {
- /delete-property/ power-domains;
-};
-
-&usbss0 {
- ti,vbus-divider;
- ti,usb2-only;
-};
-
-&usb0 {
- dr_mode = "otg";
- maximum-speed = "high-speed";
- pinctrl-names = "default";
- pinctrl-0 = <&main_usb0_pins_default>;
-};
-
-#include "k3-am642-evm-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts
index 32d4c31..daa483a 100644
--- a/arch/arm/dts/k3-am642-r5-sk.dts
+++ b/arch/arm/dts/k3-am642-r5-sk.dts
@@ -3,33 +3,18 @@
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
-/dts-v1/;
-
-#include <dt-bindings/mux/ti-serdes.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/net/ti-dp83867.h>
-#include "k3-am642.dtsi"
+#include "k3-am642-sk.dts"
#include "k3-am64-sk-lp4-1600MTs.dtsi"
#include "k3-am64-ddr.dtsi"
-/ {
- chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
+#include "k3-am642-sk-u-boot.dtsi"
+/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
- memory@80000000 {
- device_type = "memory";
- /* 2G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
- bootph-pre-ram;
- };
-
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
@@ -47,18 +32,6 @@
bootph-pre-ram;
};
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
- alignment = <0x1000>;
- no-map;
- };
- };
-
clk_200mhz: dummy-clock-200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -76,108 +49,16 @@
};
};
-&cbass_main {
- main_esm: esm@420000 {
- compatible = "ti,j721e-esm";
- reg = <0x0 0x420000 0x0 0x1000>;
- ti,esm-pins = <160>, <161>;
- bootph-pre-ram;
- };
+&main_esm {
+ bootph-pre-ram;
};
&cbass_mcu {
bootph-pre-ram;
- mcu_esm: esm@4100000 {
- compatible = "ti,j721e-esm";
- reg = <0x0 0x4100000 0x0 0x1000>;
- ti,esm-pins = <0>, <1>;
- bootph-pre-ram;
- };
};
-&main_pmx0 {
+&mcu_esm {
bootph-pre-ram;
- main_uart0_pins_default: main-uart0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
- AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
- AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
- AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
- >;
- };
-
- main_uart1_pins_default: main-uart1-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
- AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
- AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
- AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
- >;
- };
-
- main_mmc1_pins_default: main-mmc1-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
- AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
- AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
- AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
- AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
- AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
- AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
- AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
- >;
- };
-
- main_usb0_pins_default: main-usb0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
- >;
- };
-
- mdio1_pins_default: mdio1-pins-default {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
- AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
- >;
- };
-
- rgmii1_pins_default: rgmii1-pins-default {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
- AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
- AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
- AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
- AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
- AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
- AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
- AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
- AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
- AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
- AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
- AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
- >;
- };
-
- rgmii2_pins_default: rgmii2-pins-default {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
- AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
- AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
- AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
- AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
- AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
- AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
- AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
- AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
- AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
- AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
- AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
- >;
- };
};
&dmsc {
@@ -189,79 +70,36 @@
ti,secure-host;
};
-&main_uart0 {
- /delete-property/ power-domains;
- /delete-property/ clocks;
- /delete-property/ clock-names;
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
- status = "okay";
-};
-
-&main_uart1 {
- bootph-pre-ram;
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart1_pins_default>;
-};
-
&sdhci1 {
- /delete-property/ power-domains;
clocks = <&clk_200mhz>;
clock-names = "clk_xin";
- ti,driver-strength-ohm = <50>;
- disable-wp;
- pinctrl-0 = <&main_mmc1_pins_default>;
-};
-
-&serdes_ln_ctrl {
- idle-states = <AM64_SERDES0_LANE0_USB>;
};
&serdes_wiz0 {
status = "okay";
};
-&serdes0 {
- serdes0_usb_link: link@0 {
- reg = <0>;
- cdns,num-lanes = <1>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_USB3>;
- resets = <&serdes_wiz0 1>;
- };
+/* UART is initialized before SYSFW is started
+ * so we can't do any power-domain/clock operations.
+ * Delete clock/power-domain properties to avoid
+ * UART init failure
+ */
+&main_uart0 {
+ /delete-property/ power-domains;
+ /delete-property/ clocks;
+ /delete-property/ clock-names;
};
-&usbss0 {
- ti,vbus-divider;
+/* timer init is called as part of rproc_start() while
+ * starting System Firmware, so any clock/power-domain
+ * operations will fail as SYSFW is not yet up and running.
+ * Delete all clock/power-domain properties to avoid
+ * timer init failure.
+ * This is an always on timer at 20MHz.
+ */
+&main_timer0 {
+ /delete-property/ clocks;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ power-domains;
};
-
-&usb0 {
- dr_mode = "host";
- maximum-speed = "super-speed";
- pinctrl-names = "default";
- pinctrl-0 = <&main_usb0_pins_default>;
- phys = <&serdes0_usb_link>;
- phy-names = "cdns3,usb3-phy";
-};
-
-&cpsw3g {
- pinctrl-names = "default";
- pinctrl-0 = <&mdio1_pins_default
- &rgmii1_pins_default
- &rgmii2_pins_default>;
-};
-
-&cpsw_port2 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&cpsw3g_phy1>;
-};
-
-&cpsw3g_mdio {
- cpsw3g_phy1: ethernet-phy@1 {
- reg = <1>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
-};
-
-#include "k3-am642-sk-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
index 3d6be02..2eb227c 100644
--- a/arch/arm/dts/k3-am642-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
@@ -7,209 +7,181 @@
/ {
chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
-
- aliases {
- mmc1 = &sdhci1;
+ tick-timer = &main_timer0;
};
memory@80000000 {
- bootph-pre-ram;
+ bootph-all;
};
};
&cbass_main{
- bootph-pre-ram;
- timer1: timer@2400000 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x2400000 0x0 0x80>;
- ti,timer-alwon;
- clock-frequency = <200000000>;
- bootph-pre-ram;
- };
+ bootph-all;
+};
+
+&main_timer0 {
+ bootph-all;
+ clock-frequency = <200000000>;
};
&main_conf {
- bootph-pre-ram;
+ bootph-all;
chipid@14 {
- bootph-pre-ram;
+ bootph-all;
};
};
&main_pmx0 {
- bootph-pre-ram;
- main_i2c0_pins_default: main-i2c0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
- AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
- >;
- };
+ bootph-all;
+};
+
+&main_i2c0_pins_default {
+ bootph-all;
};
&main_i2c0 {
- bootph-pre-ram;
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
+ bootph-all;
+};
- tps65219: pmic@30 {
- compatible = "ti,tps65219";
- reg = <0x30>;
-
- regulators {
- buck1_reg: buck1 {
- regulator-name = "VDD_CORE";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck2_reg: buck2 {
- regulator-name = "VCC1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck3_reg: buck3 {
- regulator-name = "VDD_LPDDR4";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1_reg: ldo1 {
- regulator-name = "VDDSHV_SD_IO_PMIC";
- regulator-min-microvolt = <33000000>;
- regulator-max-microvolt = <33000000>;
- };
-
- ldo2_reg: ldo2 {
- regulator-name = "VDDAR_CORE";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo3_reg: ldo3 {
- regulator-name = "VDDA_1V8";
- regulator-min-microvolt = <18000000>;
- regulator-max-microvolt = <18000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo4_reg: ldo4 {
- regulator-name = "VDD_PHY_2V5";
- regulator-min-microvolt = <25000000>;
- regulator-max-microvolt = <25000000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
+&main_uart0_pins_default {
+ bootph-all;
};
&main_uart0 {
- bootph-pre-ram;
+ bootph-all;
};
&dmss {
- bootph-pre-ram;
+ bootph-all;
};
&secure_proxy_main {
- bootph-pre-ram;
+ bootph-all;
};
&dmsc {
- bootph-pre-ram;
+ bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- bootph-pre-ram;
+ bootph-all;
};
};
&k3_pds {
- bootph-pre-ram;
+ bootph-all;
};
&k3_clks {
- bootph-pre-ram;
+ bootph-all;
};
&k3_reset {
- bootph-pre-ram;
+ bootph-all;
};
&sdhci0 {
status = "disabled";
- bootph-pre-ram;
+ bootph-all;
};
&sdhci1 {
- bootph-pre-ram;
+ bootph-all;
};
&main_mmc1_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
-&cpsw3g {
- reg = <0x0 0x8000000 0x0 0x200000>,
- <0x0 0x43000200 0x0 0x8>;
- reg-names = "cpsw_nuss", "mac_efuse";
- /delete-property/ ranges;
- bootph-pre-ram;
-
- cpsw-phy-sel@04044 {
- compatible = "ti,am64-phy-gmii-sel";
- reg = <0x0 0x43004044 0x0 0x8>;
- bootph-pre-ram;
- };
-
- ethernet-ports {
- bootph-pre-ram;
- };
-};
-
-&cpsw_port2 {
- bootph-pre-ram;
-};
-
-&main_bcdma {
- bootph-pre-ram;
-};
-
-&main_pktdma {
- bootph-pre-ram;
-};
-
-&rgmii1_pins_default {
- bootph-pre-ram;
-};
-
-&rgmii2_pins_default {
- bootph-pre-ram;
+&inta_main_dmss {
+ bootph-all;
};
&mdio1_pins_default {
- bootph-pre-ram;
+ bootph-all;
+};
+
+&cpsw3g_mdio {
+ bootph-all;
+};
+
+&cpsw3g_phy0 {
+ bootph-all;
};
&cpsw3g_phy1 {
- bootph-pre-ram;
+ bootph-all;
+};
+
+&rgmii1_pins_default {
+ bootph-all;
+};
+
+&rgmii2_pins_default {
+ bootph-all;
+};
+
+&cpsw3g {
+ bootph-all;
+
+ ethernet-ports {
+ bootph-all;
+ };
+};
+
+&phy_gmii_sel {
+ bootph-all;
+};
+
+&cpsw_port2 {
+ bootph-all;
+};
+
+&main_bcdma {
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>,
+ <0x00 0x48600000 0x00 0x8000>,
+ <0x00 0x484a4000 0x00 0x2000>,
+ <0x00 0x484c2000 0x00 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
+ "cfg", "tchan", "rchan";
+ bootph-all;
+};
+
+&main_pktdma {
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x40000>,
+ <0x00 0x4b800000 0x00 0x400000>,
+ <0x00 0x485e0000 0x00 0x20000>,
+ <0x00 0x484a0000 0x00 0x4000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x4000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg",
+ "tchan", "rchan", "rflow";
+ bootph-all;
+};
+
+&rgmii1_pins_default {
+ bootph-all;
+};
+
+&rgmii2_pins_default {
+ bootph-all;
+};
+
+&mdio1_pins_default {
+ bootph-all;
+};
+
+&cpsw3g_phy1 {
+ bootph-all;
};
&main_usb0_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&serdes_ln_ctrl {
@@ -217,26 +189,25 @@
};
&usbss0 {
- bootph-pre-ram;
+ bootph-all;
};
&usb0 {
- dr_mode = "host";
- bootph-pre-ram;
+ bootph-all;
};
&serdes_wiz0 {
- bootph-pre-ram;
+ bootph-all;
};
&serdes0_usb_link {
- bootph-pre-ram;
+ bootph-all;
};
&serdes0 {
- bootph-pre-ram;
+ bootph-all;
};
&serdes_refclk {
- bootph-pre-ram;
+ bootph-all;
};
diff --git a/arch/arm/dts/k3-am642-sk.dts b/arch/arm/dts/k3-am642-sk.dts
index 2e2d40d..722fd28 100644
--- a/arch/arm/dts/k3-am642-sk.dts
+++ b/arch/arm/dts/k3-am642-sk.dts
@@ -5,27 +5,38 @@
/dts-v1/;
-#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/leds/common.h>
#include "k3-am642.dtsi"
+#include "k3-serdes.h"
+
/ {
compatible = "ti,am642-sk", "ti,am642";
model = "Texas Instruments AM642 SK";
chosen {
- stdout-path = "serial2:115200n8";
- bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+ stdout-path = &main_uart0;
+ };
+
+ aliases {
+ serial0 = &mcu_uart0;
+ serial1 = &main_uart1;
+ serial2 = &main_uart0;
+ i2c0 = &main_i2c0;
+ i2c1 = &main_i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ ethernet0 = &cpsw_port1;
+ ethernet1 = &cpsw_port2;
};
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
-
};
reserved-memory {
@@ -94,7 +105,7 @@
};
};
- vusb_main: fixed-regulator-vusb-main5v0 {
+ vusb_main: regulator-0 {
/* USB MAIN INPUT 5V DC */
compatible = "regulator-fixed";
regulator-name = "vusb_main5v0";
@@ -104,7 +115,7 @@
regulator-boot-on;
};
- vcc_3v3_sys: fixedregulator-vcc-3v3-sys {
+ vcc_3v3_sys: regulator-1 {
/* output of LP8733xx */
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sys";
@@ -115,7 +126,7 @@
regulator-boot-on;
};
- vdd_mmc1: fixed-regulator-sd {
+ vdd_mmc1: regulator-2 {
/* TPS2051BD */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
@@ -127,7 +138,7 @@
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
};
- com8_ls_en: regulator-1 {
+ com8_ls_en: regulator-3 {
compatible = "regulator-fixed";
regulator-name = "com8_ls_en";
regulator-min-microvolt = <3300000>;
@@ -139,7 +150,7 @@
gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>;
};
- wlan_en: regulator-2 {
+ wlan_en: regulator-4 {
/* output of SN74AVC4T245RSVR */
compatible = "regulator-fixed";
regulator-name = "wlan_en";
@@ -222,20 +233,21 @@
};
&main_pmx0 {
- main_mmc1_pins_default: main-mmc1-pins-default {
+ main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
- AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */
+ AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
+ AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
+ AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
- AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */
- AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */
- AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */
- AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */
- AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */
- AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */
+ AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
+ AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
+ AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
+ AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
+ AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
>;
};
- main_uart0_pins_default: main-uart0-pins-default {
+ main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
@@ -244,27 +256,43 @@
>;
};
- main_usb0_pins_default: main-usb0-pins-default {
+ main_uart1_pins_default: main-uart1-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
+ AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
+ AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
+ AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
+ >;
+ };
+
+ main_usb0_pins_default: main-usb0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
- main_i2c1_pins_default: main-i2c1-pins-default {
+ main_i2c0_pins_default: main-i2c0-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
+ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
+ >;
+ };
+
+ main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
>;
};
- mdio1_pins_default: mdio1-pins-default {
+ mdio1_pins_default: mdio1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
>;
};
- rgmii1_pins_default: rgmii1-pins-default {
+ rgmii1_pins_default: rgmii1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
@@ -281,7 +309,7 @@
>;
};
- rgmii2_pins_default: rgmii2-pins-default {
+ rgmii2_pins_default: rgmii2-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
@@ -298,7 +326,7 @@
>;
};
- ospi0_pins_default: ospi0-pins-default {
+ ospi0_pins_default: ospi0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
@@ -314,24 +342,24 @@
>;
};
- main_ecap0_pins_default: main-ecap0-pins-default {
+ main_ecap0_pins_default: main-ecap0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
>;
};
- main_wlan_en_pins_default: main-wlan-en-pins-default {
+ main_wlan_en_pins_default: main-wlan-en-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */
>;
};
- main_com8_ls_en_pins_default: main-com8-ls-en-pins-default {
+ main_com8_ls_en_pins_default: main-com8-ls-en-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */
>;
};
- main_wlan_pins_default: main-wlan-pins-default {
+ main_wlan_pins_default: main-wlan-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */
>;
@@ -342,11 +370,26 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
+ current-speed = <115200>;
};
&main_uart1 {
/* main_uart1 is reserved for firmware usage */
status = "reserved";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
+};
+
+&main_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ eeprom@51 {
+ compatible = "atmel,24c512";
+ reg = <0x51>;
+ };
};
&main_i2c1 {
@@ -439,8 +482,7 @@
&cpsw3g {
pinctrl-names = "default";
- pinctrl-0 = <&rgmii1_pins_default
- &rgmii2_pins_default>;
+ pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
};
&cpsw_port1 {
@@ -471,11 +513,8 @@
};
};
-&tscadc0 {
- status = "disabled";
-};
-
&ospi0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
@@ -490,10 +529,53 @@
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ospi.tiboot3";
+ reg = <0x0 0x100000>;
+ };
+
+ partition@100000 {
+ label = "ospi.tispl";
+ reg = <0x100000 0x200000>;
+ };
+
+ partition@300000 {
+ label = "ospi.u-boot";
+ reg = <0x300000 0x400000>;
+ };
+
+ partition@700000 {
+ label = "ospi.env";
+ reg = <0x700000 0x40000>;
+ };
+
+ partition@740000 {
+ label = "ospi.env.backup";
+ reg = <0x740000 0x40000>;
+ };
+
+ partition@800000 {
+ label = "ospi.rootfs";
+ reg = <0x800000 0x37c0000>;
+ };
+
+ partition@3fc0000 {
+ label = "ospi.phypattern";
+ reg = <0x3fc0000 0x40000>;
+ };
+ };
};
};
&mailbox0_cluster2 {
+ status = "okay";
+
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
@@ -505,11 +587,9 @@
};
};
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
&mailbox0_cluster4 {
+ status = "okay";
+
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
@@ -521,41 +601,35 @@
};
};
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
&mailbox0_cluster6 {
+ status = "okay";
+
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+ mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+ mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
diff --git a/arch/arm/dts/k3-am642.dtsi b/arch/arm/dts/k3-am642.dtsi
index 8a76f48..7a6eede 100644
--- a/arch/arm/dts/k3-am642.dtsi
+++ b/arch/arm/dts/k3-am642.dtsi
@@ -58,6 +58,7 @@
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x40000>;
cache-line-size = <64>;
cache-sets = <256>;
diff --git a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi
index e73458c..e9419c4 100644
--- a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi
+++ b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi
@@ -10,7 +10,7 @@
*/
&main_pmx0 {
- cp2102n_reset_pin_default: cp2102n-reset-pin-default {
+ cp2102n_reset_pin_default: cp2102n-reset-default-pins {
pinctrl-single,pins = <
/* (AF12) GPIO1_24, used as cp2102 reset */
AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7)
diff --git a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi
index 082a3c8..d53f133 100644
--- a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi
+++ b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi
@@ -15,18 +15,18 @@
};
leds {
- bootph-pre-ram;
+ bootph-all;
status-led-red {
- bootph-pre-ram;
+ bootph-all;
};
status-led-green {
- bootph-pre-ram;
+ bootph-all;
};
};
};
&cbass_mcu {
- bootph-pre-ram;
+ bootph-all;
mcu_navss: bus@28380000 {
ringacc@2b800000 {
@@ -53,70 +53,70 @@
};
&cbass_wakeup {
- bootph-pre-ram;
+ bootph-all;
};
&cbass_main {
- bootph-pre-ram;
+ bootph-all;
main_navss: bus@30800000 {
- bootph-pre-ram;
+ bootph-all;
};
};
&wkup_pmx0 {
- bootph-pre-ram;
+ bootph-all;
mcu-fss0-ospi0-pins-default {
- bootph-pre-ram;
+ bootph-all;
};
};
&main_pmx0 {
- bootph-pre-ram;
+ bootph-all;
main-uart1-pins-default {
- bootph-pre-ram;
+ bootph-all;
};
};
&main_uart1 {
- bootph-pre-ram;
+ bootph-all;
current-speed = <115200>;
};
&wkup_gpio0 {
- bootph-pre-ram;
+ bootph-all;
};
&ospi0 {
- bootph-pre-ram;
+ bootph-all;
flash@0 {
- bootph-pre-ram;
+ bootph-all;
};
};
&secure_proxy_main {
- bootph-pre-ram;
+ bootph-all;
};
&dmsc {
- bootph-pre-ram;
+ bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- bootph-pre-ram;
+ bootph-all;
};
};
&k3_pds {
- bootph-pre-ram;
+ bootph-all;
};
&k3_clks {
- bootph-pre-ram;
+ bootph-all;
};
&k3_reset {
- bootph-pre-ram;
+ bootph-all;
};
&fss {
- bootph-pre-ram;
+ bootph-all;
};
diff --git a/arch/arm/dts/k3-am65-iot2050-common.dtsi b/arch/arm/dts/k3-am65-iot2050-common.dtsi
index 65da226..fa71781 100644
--- a/arch/arm/dts/k3-am65-iot2050-common.dtsi
+++ b/arch/arm/dts/k3-am65-iot2050-common.dtsi
@@ -14,6 +14,16 @@
/ {
aliases {
+ serial0 = &wkup_uart0;
+ serial1 = &mcu_uart0;
+ serial2 = &main_uart0;
+ serial3 = &main_uart1;
+ i2c0 = &wkup_i2c0;
+ i2c1 = &mcu_i2c0;
+ i2c2 = &main_i2c0;
+ i2c3 = &main_i2c1;
+ i2c4 = &main_i2c2;
+ i2c5 = &main_i2c3;
spi0 = &mcu_spi0;
mmc0 = &sdhci1;
mmc1 = &sdhci0;
@@ -21,7 +31,6 @@
chosen {
stdout-path = "serial3:115200n8";
- bootargs = "earlycon=ns16550a,mmio32,0x02810000";
};
reserved-memory {
@@ -64,6 +73,12 @@
alignment = <0x1000>;
no-map;
};
+
+ /* To reserve the power-on(PON) reason for watchdog reset */
+ wdt_reset_memory_region: wdt-memory@a2200000 {
+ reg = <0x00 0xa2200000 0x00 0x00001000>;
+ no-map;
+ };
};
leds {
@@ -105,7 +120,7 @@
};
&wkup_pmx0 {
- wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
/* (AC7) WKUP_I2C0_SCL */
AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0)
@@ -114,7 +129,7 @@
>;
};
- mcu_i2c0_pins_default: mcu-i2c0-pins-default {
+ mcu_i2c0_pins_default: mcu-i2c0-default-pins {
pinctrl-single,pins = <
/* (AD8) MCU_I2C0_SCL */
AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0)
@@ -123,21 +138,21 @@
>;
};
- arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-pins-default {
+ arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-default-pins {
pinctrl-single,pins = <
/* (R2) WKUP_GPIO0_21 */
AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7)
>;
};
- push_button_pins_default: push-button-pins-default {
+ push_button_pins_default: push-button-default-pins {
pinctrl-single,pins = <
/* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7)
>;
};
- arduino_uart_pins_default: arduino-uart-pins-default {
+ arduino_uart_pins_default: arduino-uart-default-pins {
pinctrl-single,pins = <
/* (P4) MCU_UART0_RXD */
AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4)
@@ -146,7 +161,7 @@
>;
};
- arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-pins-default {
+ arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-default-pins {
pinctrl-single,pins = <
/* (P1) WKUP_GPIO0_31 */
AM65X_WKUP_IOPAD(0x004C, PIN_OUTPUT, 7)
@@ -155,7 +170,7 @@
>;
};
- arduino_io_oe_pins_default: arduino-io-oe-pins-default {
+ arduino_io_oe_pins_default: arduino-io-oe-default-pins {
pinctrl-single,pins = <
/* (N4) WKUP_GPIO0_34 */
AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7)
@@ -170,7 +185,7 @@
>;
};
- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
pinctrl-single,pins = <
/* (V1) MCU_OSPI0_CLK */
AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0)
@@ -185,7 +200,7 @@
>;
};
- db9_com_mode_pins_default: db9-com-mode-pins-default {
+ db9_com_mode_pins_default: db9-com-mode-default-pins {
pinctrl-single,pins = <
/* (AD3) WKUP_GPIO0_5, used as uart0 mode 0 */
AM65X_WKUP_IOPAD(0x00c4, PIN_OUTPUT, 7)
@@ -198,7 +213,7 @@
>;
};
- leds_pins_default: leds-pins-default {
+ leds_pins_default: leds-default-pins {
pinctrl-single,pins = <
/* (T2) WKUP_GPIO0_17, used as user led1 red */
AM65X_WKUP_IOPAD(0x0014, PIN_OUTPUT, 7)
@@ -211,7 +226,7 @@
>;
};
- mcu_spi0_pins_default: mcu-spi0-pins-default {
+ mcu_spi0_pins_default: mcu-spi0-default-pins {
pinctrl-single,pins = <
/* (Y1) MCU_SPI0_CLK */
AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0)
@@ -224,7 +239,7 @@
>;
};
- minipcie_pins_default: minipcie-pins-default {
+ minipcie_pins_default: minipcie-default-pins {
pinctrl-single,pins = <
/* (P2) MCU_OSPI1_DQS.WKUP_GPIO0_27 */
AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7)
@@ -233,7 +248,7 @@
};
&main_pmx0 {
- main_uart1_pins_default: main-uart1-pins-default {
+ main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */
AM65X_IOPAD(0x014c, PIN_OUTPUT, 6) /* (AD23) UART1_TXD */
@@ -242,14 +257,14 @@
>;
};
- main_i2c3_pins_default: main-i2c3-pins-default {
+ main_i2c3_pins_default: main-i2c3-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c0, PIN_INPUT, 2) /* (AF13) I2C3_SCL */
AM65X_IOPAD(0x01d4, PIN_INPUT, 2) /* (AG12) I2C3_SDA */
>;
};
- main_mmc1_pins_default: main-mmc1-pins-default {
+ main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
@@ -262,19 +277,19 @@
>;
};
- usb0_pins_default: usb0-pins-default {
+ usb0_pins_default: usb0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
>;
};
- usb1_pins_default: usb1-pins-default {
+ usb1_pins_default: usb1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
>;
};
- arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-pins-default {
+ arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (AG18) GPIO0_33 */
AM65X_IOPAD(0x008C, PIN_OUTPUT, 7) /* (AF17) GPIO0_35 */
@@ -285,7 +300,7 @@
>;
};
- dss_vout1_pins_default: dss-vout1-pins-default {
+ dss_vout1_pins_default: dss-vout1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */
AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */
@@ -318,13 +333,13 @@
>;
};
- dp_pins_default: dp-pins-default {
+ dp_pins_default: dp-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */
>;
};
- main_i2c2_pins_default: main-i2c2-pins-default {
+ main_i2c2_pins_default: main-i2c2-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL */
AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) I2C2_SDA */
@@ -333,21 +348,21 @@
};
&main_pmx1 {
- main_i2c0_pins_default: main-i2c0-pins-default {
+ main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
>;
};
- main_i2c1_pins_default: main-i2c1-pins-default {
+ main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
>;
};
- ecap0_pins_default: ecap0-pins-default {
+ ecap0_pins_default: ecap0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
>;
@@ -360,15 +375,13 @@
};
&main_uart1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
};
-&main_uart2 {
- status = "disabled";
-};
-
&mcu_uart0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&arduino_uart_pins_default>;
};
@@ -387,13 +400,12 @@
&wkup_gpio0 {
pinctrl-names = "default";
- pinctrl-0 = <
- &arduino_io_d2_to_d3_pins_default
- &arduino_i2c_aio_switch_pins_default
- &arduino_io_oe_pins_default
- &push_button_pins_default
- &db9_com_mode_pins_default
- >;
+ pinctrl-0 =
+ <&arduino_io_d2_to_d3_pins_default>,
+ <&arduino_i2c_aio_switch_pins_default>,
+ <&arduino_io_oe_pins_default>,
+ <&push_button_pins_default>,
+ <&db9_com_mode_pins_default>;
gpio-line-names =
/* 0..9 */
"wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0",
@@ -413,19 +425,21 @@
};
&wkup_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
};
&mcu_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_i2c0_pins_default>;
clock-frequency = <400000>;
psu: regulator@60 {
compatible = "ti,tps62363";
- reg = <0x60>;
+ reg = <0x60>;
regulator-name = "tps62363-vout";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1500000>;
@@ -478,11 +492,12 @@
};
&main_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
- rtc: rtc8564@51 {
+ rtc: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
@@ -495,18 +510,21 @@
};
&main_i2c1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
};
&main_i2c2 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c2_pins_default>;
clock-frequency = <400000>;
};
&main_i2c3 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c3_pins_default>;
clock-frequency = <400000>;
@@ -546,6 +564,7 @@
};
&ecap0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins_default>;
};
@@ -570,25 +589,24 @@
};
&mcu_spi0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_spi0_pins_default>;
#address-cells = <1>;
- #size-cells= <0>;
+ #size-cells = <0>;
ti,pindir-d0-out-d1-in;
};
-&tscadc0 {
- status = "disabled";
-};
-
&tscadc1 {
+ status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5>;
};
};
&ospi0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
@@ -603,8 +621,52 @@
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <2>;
- #address-cells = <1>;
- #size-cells = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ seboot@0 {
+ label = "seboot";
+ reg = <0x0 0x180000>; /* 1.5M */
+ };
+
+ tispl@180000 {
+ label = "tispl";
+ reg = <0x180000 0x200000>; /* 2M */
+ };
+
+ u-boot@380000 {
+ label = "u-boot";
+ reg = <0x380000 0x300000>; /* 3M */
+ };
+
+ env@680000 {
+ label = "env";
+ reg = <0x680000 0x20000>; /* 128K */
+ };
+
+ env-backup@6a0000 {
+ label = "env.backup";
+ reg = <0x6a0000 0x20000>; /* 128K */
+ };
+
+ otpcmd@6c0000 {
+ label = "otpcmd";
+ reg = <0x6c0000 0x10000>; /* 64K */
+ };
+
+ unused@6d0000 {
+ label = "unused";
+ reg = <0x6d0000 0x7b0000>; /* 7872K */
+ };
+
+ seboot-backup@e80000 {
+ label = "seboot.backup";
+ reg = <0xe80000 0x180000>; /* 1.5M */
+ };
+ };
};
};
@@ -628,15 +690,8 @@
};
};
-&pcie0_rc {
- status = "disabled";
-};
-
-&pcie0_ep {
- status = "disabled";
-};
-
&pcie1_rc {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&minipcie_pins_default>;
@@ -646,11 +701,8 @@
reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>;
};
-&pcie1_ep {
- status = "disabled";
-};
-
&mailbox0_cluster0 {
+ status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
@@ -660,6 +712,7 @@
};
&mailbox0_cluster1 {
+ status = "okay";
interrupts = <432>;
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
@@ -668,66 +721,18 @@
};
};
-&mailbox0_cluster2 {
- status = "disabled";
-};
-
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
-&mailbox0_cluster4 {
- status = "disabled";
-};
-
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
-&mailbox0_cluster6 {
- status = "disabled";
-};
-
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
-&mailbox0_cluster8 {
- status = "disabled";
-};
-
-&mailbox0_cluster9 {
- status = "disabled";
-};
-
-&mailbox0_cluster10 {
- status = "disabled";
-};
-
-&mailbox0_cluster11 {
- status = "disabled";
-};
-
&mcu_r5fss0_core0 {
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
- mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
};
&mcu_r5fss0_core1 {
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
- mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
};
-&icssg0_mdio {
- status = "disabled";
-};
-
-&icssg1_mdio {
- status = "disabled";
-};
-
-&icssg2_mdio {
- status = "disabled";
+&mcu_rti1 {
+ memory-region = <&wdt_reset_memory_region>;
};
diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
index ba4e5d3..5ebb87f 100644
--- a/arch/arm/dts/k3-am65-main.dtsi
+++ b/arch/arm/dts/k3-am65-main.dtsi
@@ -35,7 +35,10 @@
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01880000 0x00 0x90000>; /* GICR */
+ <0x00 0x01880000 0x00 0x90000>, /* GICR */
+ <0x00 0x6f000000 0x00 0x2000>, /* GICC */
+ <0x00 0x6f010000 0x00 0x1000>, /* GICH */
+ <0x00 0x6f020000 0x00 0x2000>; /* GICV */
/*
* vcpumntirq:
* virtual CPU interface maintenance interrupt
@@ -88,6 +91,7 @@
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart1: serial@2810000 {
@@ -96,6 +100,7 @@
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart2: serial@2820000 {
@@ -104,29 +109,47 @@
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
crypto: crypto@4e00000 {
compatible = "ti,am654-sa2ul";
reg = <0x0 0x4e00000 0x0 0x1200>;
- power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>;
+ power-domains = <&k3_pds 136 TI_SCI_PD_SHARED>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
- dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
- <&main_udmap 0x4001>;
+ dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>,
+ <&main_udmap 0x4003>;
dma-names = "tx", "rx1", "rx2";
- dma-coherent;
rng: rng@4e10000 {
compatible = "inside-secure,safexcel-eip76";
reg = <0x0 0x4e10000 0x0 0x7d>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 136 1>;
+ status = "disabled"; /* Used by OP-TEE */
};
};
+ /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
+ main_timerio_input: pinctrl@104200 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x104200 0x0 0x30>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000001ff>;
+ };
+
+ /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
+ main_timerio_output: pinctrl@104280 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x104280 0x0 0x20>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ };
+
main_pmx0: pinctrl@11c000 {
compatible = "pinctrl-single";
reg = <0x0 0x11c000 0x0 0x2e4>;
@@ -152,6 +175,7 @@
clock-names = "fck";
clocks = <&k3_clks 110 1>;
power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c1: i2c@2010000 {
@@ -163,6 +187,7 @@
clock-names = "fck";
clocks = <&k3_clks 111 1>;
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c2: i2c@2020000 {
@@ -174,6 +199,7 @@
clock-names = "fck";
clocks = <&k3_clks 112 1>;
power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c3: i2c@2030000 {
@@ -185,6 +211,7 @@
clock-names = "fck";
clocks = <&k3_clks 113 1>;
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
ecap0: pwm@3100000 {
@@ -194,6 +221,7 @@
power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 39 0>;
clock-names = "fck";
+ status = "disabled";
};
main_spi0: spi@2100000 {
@@ -206,6 +234,7 @@
#size-cells = <0>;
dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
dma-names = "tx0", "rx0";
+ status = "disabled";
};
main_spi1: spi@2110000 {
@@ -218,6 +247,7 @@
#size-cells = <0>;
assigned-clocks = <&k3_clks 137 1>;
assigned-clock-rates = <48000000>;
+ status = "disabled";
};
main_spi2: spi@2120000 {
@@ -228,6 +258,7 @@
power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
main_spi3: spi@2130000 {
@@ -238,6 +269,7 @@
power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
main_spi4: spi@2140000 {
@@ -248,6 +280,151 @@
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
+ };
+
+ main_timer0: timer@2400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2400000 0x00 0x400>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 23 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 23 0>;
+ assigned-clock-parents = <&k3_clks 23 1>;
+ power-domains = <&k3_pds 23 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer1: timer@2410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2410000 0x00 0x400>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 24 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 24 0>;
+ assigned-clock-parents = <&k3_clks 24 1>;
+ power-domains = <&k3_pds 24 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer2: timer@2420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2420000 0x00 0x400>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 27 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 27 0>;
+ assigned-clock-parents = <&k3_clks 27 1>;
+ power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer3: timer@2430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2430000 0x00 0x400>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 28 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 28 0>;
+ assigned-clock-parents = <&k3_clks 28 1>;
+ power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer4: timer@2440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2440000 0x00 0x400>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 29 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 29 0>;
+ assigned-clock-parents = <&k3_clks 29 1>;
+ power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer5: timer@2450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2450000 0x00 0x400>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 30 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 30 0>;
+ assigned-clock-parents = <&k3_clks 30 1>;
+ power-domains = <&k3_pds 30 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer6: timer@2460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2460000 0x00 0x400>;
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 31 0>;
+ assigned-clocks = <&k3_clks 31 0>;
+ assigned-clock-parents = <&k3_clks 31 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 31 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer7: timer@2470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2470000 0x00 0x400>;
+ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 32 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 32 0>;
+ assigned-clock-parents = <&k3_clks 32 1>;
+ power-domains = <&k3_pds 32 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer8: timer@2480000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2480000 0x00 0x400>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 33 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 33 0>;
+ assigned-clock-parents = <&k3_clks 33 1>;
+ power-domains = <&k3_pds 33 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer9: timer@2490000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2490000 0x00 0x400>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 34 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 34 0>;
+ assigned-clock-parents = <&k3_clks 34 1>;
+ power-domains = <&k3_pds 34 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer10: timer@24a0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24a0000 0x00 0x400>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 25 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 25 0>;
+ assigned-clock-parents = <&k3_clks 25 1>;
+ power-domains = <&k3_pds 25 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer11: timer@24b0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24b0000 0x00 0x400>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 26 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 26 0>;
+ assigned-clock-parents = <&k3_clks 26 1>;
+ power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
};
sdhci0: mmc@4f80000 {
@@ -292,7 +469,6 @@
ti,otap-del-sel-ddr52 = <0x4>;
ti,otap-del-sel-hs200 = <0x7>;
ti,clkbuf-sel = <0x7>;
- ti,otap-del-sel = <0x2>;
ti,trm-icp = <0x8>;
dma-coherent;
};
@@ -304,21 +480,6 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x00100000 0x1c000>;
- pcie0_mode: pcie-mode@4060 {
- compatible = "syscon";
- reg = <0x00004060 0x4>;
- };
-
- pcie1_mode: pcie-mode@4070 {
- compatible = "syscon";
- reg = <0x00004070 0x4>;
- };
-
- pcie_devid: pcie-devid@210 {
- compatible = "syscon";
- reg = <0x00000210 0x4>;
- };
-
serdes0_clk: clock@4080 {
compatible = "syscon";
reg = <0x00004080 0x4>;
@@ -338,11 +499,11 @@
dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
compatible = "syscon";
- reg = <0x0000041e0 0x14>;
+ reg = <0x000041e0 0x14>;
};
- ehrpwm_tbclk: clock@4140 {
- compatible = "ti,am654-ehrpwm-tbclk", "syscon";
+ ehrpwm_tbclk: clock-controller@4140 {
+ compatible = "ti,am654-ehrpwm-tbclk";
reg = <0x4140 0x18>;
#clock-cells = <1>;
};
@@ -439,7 +600,7 @@
};
main_navss: bus@30800000 {
- compatible = "simple-mfd";
+ compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
@@ -497,6 +658,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster1: mailbox@31f81000 {
@@ -506,6 +668,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster2: mailbox@31f82000 {
@@ -515,6 +678,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster3: mailbox@31f83000 {
@@ -524,6 +688,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster4: mailbox@31f84000 {
@@ -533,6 +698,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster5: mailbox@31f85000 {
@@ -542,6 +708,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster6: mailbox@31f86000 {
@@ -551,6 +718,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster7: mailbox@31f87000 {
@@ -560,6 +728,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster8: mailbox@31f88000 {
@@ -569,6 +738,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster9: mailbox@31f89000 {
@@ -578,6 +748,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster10: mailbox@31f8a000 {
@@ -587,6 +758,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster11: mailbox@31f8b000 {
@@ -596,15 +768,17 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
ringacc: ringacc@3c000000 {
compatible = "ti,am654-navss-ringacc";
- reg = <0x0 0x3c000000 0x0 0x400000>,
- <0x0 0x38000000 0x0 0x400000>,
- <0x0 0x31120000 0x0 0x100>,
- <0x0 0x33000000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ reg = <0x0 0x3c000000 0x0 0x400000>,
+ <0x0 0x38000000 0x0 0x400000>,
+ <0x0 0x31120000 0x0 0x100>,
+ <0x0 0x33000000 0x0 0x40000>,
+ <0x0 0x31080000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
ti,num-rings = <818>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
@@ -614,9 +788,9 @@
main_udmap: dma-controller@31150000 {
compatible = "ti,am654-navss-main-udmap";
- reg = <0x0 0x31150000 0x0 0x100>,
- <0x0 0x34000000 0x0 0x100000>,
- <0x0 0x35000000 0x0 0x100000>;
+ reg = <0x0 0x31150000 0x0 0x100>,
+ <0x0 0x34000000 0x0 0x100000>,
+ <0x0 0x35000000 0x0 0x100000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&inta_main_udmass>;
#dma-cells = <1>;
@@ -687,15 +861,15 @@
pcie0_rc: pcie@5500000 {
compatible = "ti,am654-pcie-rc";
- reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
+ reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
reg-names = "app", "dbics", "config", "atu";
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
- 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
- ti,syscon-pcie-id = <&pcie_devid>;
- ti,syscon-pcie-mode = <&pcie0_mode>;
+ ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
+ <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
+ ti,syscon-pcie-id = <&scm_conf 0x210>;
+ ti,syscon-pcie-mode = <&scm_conf 0x4060>;
bus-range = <0x0 0xff>;
num-viewport = <16>;
max-link-speed = <2>;
@@ -703,32 +877,34 @@
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
device_type = "pci";
+ status = "disabled";
};
pcie0_ep: pcie-ep@5500000 {
compatible = "ti,am654-pcie-ep";
- reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
+ reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
reg-names = "app", "dbics", "addr_space", "atu";
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
- ti,syscon-pcie-mode = <&pcie0_mode>;
+ ti,syscon-pcie-mode = <&scm_conf 0x4060>;
num-ib-windows = <16>;
num-ob-windows = <16>;
max-link-speed = <2>;
dma-coherent;
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
};
pcie1_rc: pcie@5600000 {
compatible = "ti,am654-pcie-rc";
- reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
+ reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
reg-names = "app", "dbics", "config", "atu";
power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000
- 0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
- ti,syscon-pcie-id = <&pcie_devid>;
- ti,syscon-pcie-mode = <&pcie1_mode>;
+ ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
+ <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
+ ti,syscon-pcie-id = <&scm_conf 0x210>;
+ ti,syscon-pcie-mode = <&scm_conf 0x4070>;
bus-range = <0x0 0xff>;
num-viewport = <16>;
max-link-speed = <2>;
@@ -736,19 +912,21 @@
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
msi-map = <0x0 &gic_its 0x10000 0x10000>;
device_type = "pci";
+ status = "disabled";
};
pcie1_ep: pcie-ep@5600000 {
compatible = "ti,am654-pcie-ep";
- reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
+ reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
reg-names = "app", "dbics", "addr_space", "atu";
power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
- ti,syscon-pcie-mode = <&pcie1_mode>;
+ ti,syscon-pcie-mode = <&scm_conf 0x4070>;
num-ib-windows = <16>;
num-ob-windows = <16>;
max-link-speed = <2>;
dma-coherent;
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
};
mcasp0: mcasp@2b00000 {
@@ -766,6 +944,7 @@
clocks = <&k3_clks 104 0>;
clock-names = "fck";
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp1: mcasp@2b10000 {
@@ -783,6 +962,7 @@
clocks = <&k3_clks 105 0>;
clock-names = "fck";
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp2: mcasp@2b20000 {
@@ -800,6 +980,7 @@
clocks = <&k3_clks 106 0>;
clock-names = "fck";
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
cal: cal@6f03000 {
@@ -826,13 +1007,13 @@
dss: dss@4a00000 {
compatible = "ti,am65x-dss";
- reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
- <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
- <0x0 0x04a06000 0x0 0x1000>, /* vid */
- <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
- <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
- <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
- <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
+ reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
+ <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
+ <0x0 0x04a06000 0x0 0x1000>, /* vid */
+ <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
+ <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
+ <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
+ <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
reg-names = "common", "vidl1", "vid",
"ovr1", "ovr2", "vp1", "vp2";
@@ -840,9 +1021,9 @@
power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 67 1>,
- <&k3_clks 216 1>,
- <&k3_clks 67 2>;
+ clocks = <&k3_clks 67 1>,
+ <&k3_clks 216 1>,
+ <&k3_clks 67 2>;
clock-names = "fck", "vp1", "vp2";
/*
@@ -870,6 +1051,7 @@
power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm1: pwm@3010000 {
@@ -879,6 +1061,7 @@
power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm2: pwm@3020000 {
@@ -888,6 +1071,7 @@
power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm3: pwm@3030000 {
@@ -897,6 +1081,7 @@
power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm4: pwm@3040000 {
@@ -906,6 +1091,7 @@
power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm5: pwm@3050000 {
@@ -915,6 +1101,7 @@
power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
icssg0: icssg@b000000 {
@@ -964,6 +1151,18 @@
};
};
+ icssg0_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg0_iepclk_mux>;
+ };
+
+ icssg0_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg0_iepclk_mux>;
+ };
+
icssg0_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@@ -1055,6 +1254,7 @@
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
+ status = "disabled";
};
};
@@ -1105,6 +1305,18 @@
};
};
+ icssg1_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg1_iepclk_mux>;
+ };
+
+ icssg1_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg1_iepclk_mux>;
+ };
+
icssg1_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@@ -1196,6 +1408,7 @@
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
+ status = "disabled";
};
};
@@ -1246,6 +1459,18 @@
};
};
+ icssg2_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg2_iepclk_mux>;
+ };
+
+ icssg2_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg2_iepclk_mux>;
+ };
+
icssg2_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@@ -1337,6 +1562,7 @@
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
+ status = "disabled";
};
};
};
diff --git a/arch/arm/dts/k3-am65-mcu.dtsi b/arch/arm/dts/k3-am65-mcu.dtsi
index c93ff15..edd5cfb 100644
--- a/arch/arm/dts/k3-am65-mcu.dtsi
+++ b/arch/arm/dts/k3-am65-mcu.dtsi
@@ -20,13 +20,32 @@
};
};
+ /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
+ mcu_timerio_input: pinctrl@40f04200 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x40f04200 0x0 0x10>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x00000101>;
+ };
+
+ /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
+ mcu_timerio_output: pinctrl@40f04280 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x40f04280 0x0 0x8>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x00000003>;
+ };
+
mcu_uart0: serial@40a00000 {
compatible = "ti,am654-uart";
- reg = <0x00 0x40a00000 0x00 0x100>;
- interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <96000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ reg = <0x00 0x40a00000 0x00 0x100>;
+ interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <96000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_ram: sram@41c00000 {
@@ -46,6 +65,7 @@
clock-names = "fck";
clocks = <&k3_clks 114 1>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_spi0: spi@40300000 {
@@ -56,6 +76,7 @@
power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
mcu_spi1: spi@40310000 {
@@ -66,6 +87,7 @@
power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
mcu_spi2: spi@40320000 {
@@ -76,6 +98,7 @@
power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
tscadc0: tscadc@40200000 {
@@ -85,10 +108,11 @@
clocks = <&k3_clks 0 2>;
assigned-clocks = <&k3_clks 0 2>;
assigned-clock-rates = <60000000>;
- clock-names = "adc_tsc_fck";
+ clock-names = "fck";
dmas = <&mcu_udmap 0x7100>,
<&mcu_udmap 0x7101 >;
dma-names = "fifo0", "fifo1";
+ status = "disabled";
adc {
#io-channel-cells = <1>;
@@ -103,10 +127,11 @@
clocks = <&k3_clks 1 2>;
assigned-clocks = <&k3_clks 1 2>;
assigned-clock-rates = <60000000>;
- clock-names = "adc_tsc_fck";
+ clock-names = "fck";
dmas = <&mcu_udmap 0x7102>,
<&mcu_udmap 0x7103>;
dma-names = "fifo0", "fifo1";
+ status = "disabled";
adc {
#io-channel-cells = <1>;
@@ -114,8 +139,53 @@
};
};
+ /*
+ * The MCU domain timer interrupts are routed only to the ESM module,
+ * and not currently available for Linux. The MCU domain timers are
+ * of limited use without interrupts, and likely reserved by the ESM.
+ */
+ mcu_timer0: timer@40400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40400000 0x00 0x400>;
+ clocks = <&k3_clks 35 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer1: timer@40410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40410000 0x00 0x400>;
+ clocks = <&k3_clks 36 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer2: timer@40420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40420000 0x00 0x400>;
+ clocks = <&k3_clks 37 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer3: timer@40430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40430000 0x00 0x400>;
+ clocks = <&k3_clks 38 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
mcu_navss: bus@28380000 {
- compatible = "simple-mfd";
+ compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
@@ -126,11 +196,13 @@
mcu_ringacc: ringacc@2b800000 {
compatible = "ti,am654-navss-ringacc";
- reg = <0x0 0x2b800000 0x0 0x400000>,
- <0x0 0x2b000000 0x0 0x400000>,
- <0x0 0x28590000 0x0 0x100>,
- <0x0 0x2a500000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ reg = <0x0 0x2b800000 0x0 0x400000>,
+ <0x0 0x2b000000 0x0 0x400000>,
+ <0x0 0x28590000 0x0 0x100>,
+ <0x0 0x2a500000 0x0 0x40000>,
+ <0x0 0x28440000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg",
+ "proxy_target", "cfg";
ti,num-rings = <286>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
@@ -140,9 +212,9 @@
mcu_udmap: dma-controller@285c0000 {
compatible = "ti,am654-navss-mcu-udmap";
- reg = <0x0 0x285c0000 0x0 0x100>,
- <0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x2aa00000 0x0 0x40000>;
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x2aa00000 0x0 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&inta_main_udmass>;
#dma-cells = <1>;
@@ -159,7 +231,54 @@
};
};
- fss: fss@47000000 {
+ secure_proxy_mcu: mailbox@2a480000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x0 0x2a480000 0x0 0x80000>,
+ <0x0 0x2a380000 0x0 0x80000>,
+ <0x0 0x2a400000 0x0 0x80000>;
+ /*
+ * Marked Disabled:
+ * Node is incomplete as it is meant for bootloaders and
+ * firmware on non-MPU processors
+ */
+ status = "disabled";
+ };
+
+ m_can0: can@40528000 {
+ compatible = "bosch,m_can";
+ reg = <0x0 0x40528000 0x0 0x400>,
+ <0x0 0x40500000 0x0 0x4400>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 102 5>, <&k3_clks 102 0>;
+ clock-names = "hclk", "cclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ m_can1: can@40568000 {
+ compatible = "bosch,m_can";
+ reg = <0x0 0x40568000 0x0 0x400>,
+ <0x0 0x40540000 0x0 0x4400>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 103 5>, <&k3_clks 103 0>;
+ clock-names = "hclk", "cclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ fss: bus@47000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -180,6 +299,7 @@
power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
ospi1: spi@47050000 {
@@ -194,6 +314,7 @@
power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
};
@@ -243,6 +364,7 @@
clocks = <&k3_clks 5 10>;
clock-names = "fck";
bus_freq = <1000000>;
+ status = "disabled";
};
cpts@3d000 {
diff --git a/arch/arm/dts/k3-am65-wakeup.dtsi b/arch/arm/dts/k3-am65-wakeup.dtsi
index 9d21cdf..fd2b998 100644
--- a/arch/arm/dts/k3-am65-wakeup.dtsi
+++ b/arch/arm/dts/k3-am65-wakeup.dtsi
@@ -12,8 +12,8 @@
mbox-names = "rx", "tx";
- mboxes= <&secure_proxy_main 11>,
- <&secure_proxy_main 13>;
+ mboxes = <&secure_proxy_main 11>,
+ <&secure_proxy_main 13>;
reg-names = "debug_messages";
reg = <0x44083000 0x1000>;
@@ -54,6 +54,7 @@
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
wkup_i2c0: i2c@42120000 {
@@ -65,6 +66,7 @@
clock-names = "fck";
clocks = <&k3_clks 115 1>;
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
intr_wkup_gpio: interrupt-controller@42200000 {
@@ -100,8 +102,4 @@
power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
-
- thermal_zones: thermal-zones {
- #include "k3-am654-industrial-thermal.dtsi"
- };
};
diff --git a/arch/arm/dts/k3-am65.dtsi b/arch/arm/dts/k3-am65.dtsi
index a9fc1af..4d7b615 100644
--- a/arch/arm/dts/k3-am65.dtsi
+++ b/arch/arm/dts/k3-am65.dtsi
@@ -8,9 +8,10 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
+#include "k3-pinctrl.h"
+
/ {
model = "Texas Instruments K3 AM654 SoC";
compatible = "ti,am654";
@@ -18,21 +19,6 @@
#address-cells = <2>;
#size-cells = <2>;
- aliases {
- serial0 = &wkup_uart0;
- serial1 = &mcu_uart0;
- serial2 = &main_uart0;
- serial3 = &main_uart1;
- serial4 = &main_uart2;
- i2c0 = &wkup_i2c0;
- i2c1 = &mcu_i2c0;
- i2c2 = &main_i2c0;
- i2c3 = &main_i2c1;
- i2c4 = &main_i2c2;
- i2c5 = &main_i2c3;
- ethernet0 = &cpsw_port1;
- };
-
chosen { };
firmware {
@@ -84,6 +70,7 @@
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
<0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
+ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */
<0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
diff --git a/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi b/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi
index 4a9bf7d..5ab434c 100644
--- a/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi
+++ b/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi
@@ -35,7 +35,7 @@
};
&main_pmx0 {
- main_uart0_pins_default: main-uart0-pins-default {
+ main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
@@ -50,6 +50,7 @@
};
&main_uart0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
diff --git a/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi
index 5638321..cfea21b 100644
--- a/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
* This file was generated by AM65x_DRA80xM_EMIF_Tool_2.02.xlsm
- * http://www.ti.com/lit/pdf/spracj0
+ * https://www.ti.com/lit/pdf/spracj0
* Configuration Parameters
* Memory Type: DDR4
* Data Rate: 1600 MT/s
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index e4cbc47..4fd188f 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -1,11 +1,170 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
-#include "k3-am654-r5-base-board-u-boot.dtsi"
#include "k3-am65x-binman.dtsi"
+/ {
+ chosen {
+ tick-timer = &mcu_timer0;
+ };
+};
+
+&mcu_timer0 {
+ ti,timer-alwon;
+ clock-frequency = <25000000>;
+ bootph-all;
+};
+
+&vtt_supply {
+ bootph-all;
+};
+
+&cbass_main {
+ bootph-all;
+};
+
+&main_navss {
+ bootph-all;
+};
+
+&cbass_mcu {
+ bootph-all;
+};
+
+&mcu_navss {
+ bootph-all;
+};
+
+&mcu_ringacc {
+ bootph-all;
+};
+
+&mcu_udmap {
+ bootph-all;
+};
+
+&wkup_gpio0 {
+ bootph-all;
+};
+
+&secure_proxy_main {
+ bootph-all;
+};
+
+&cbass_wakeup {
+ bootph-all;
+
+ chipid@43000014 {
+ bootph-all;
+ };
+};
+
+&dmsc {
+ bootph-all;
+};
+
+&k3_pds {
+ bootph-all;
+};
+
+&k3_clks {
+ bootph-all;
+};
+
+&k3_reset {
+ bootph-all;
+};
+
+&main_uart0 {
+ bootph-all;
+};
+
+&wkup_vtm0 {
+ bootph-all;
+};
+
+&wkup_pmx0 {
+ bootph-all;
+};
+
+&wkup_uart0_pins_default {
+ bootph-all;
+};
+
+&ddr_vtt_pins_default {
+ bootph-all;
+};
+
+&mcu_uart0_pins_default {
+ bootph-all;
+};
+
+&wkup_i2c0_pins_default {
+ bootph-all;
+};
+
+&mcu_fss0_ospi0_pins_default {
+ bootph-all;
+};
+
+&main_pmx0 {
+ bootph-all;
+};
+
+&main_uart0_pins_default {
+ bootph-all;
+};
+
+&main_mmc0_pins_default {
+ bootph-all;
+};
+
+&main_mmc1_pins_default {
+ bootph-all;
+};
+
+&main_pmx1 {
+ bootph-all;
+};
+
+&sdhci0 {
+ bootph-all;
+};
+
+&sdhci1 {
+ bootph-all;
+};
+
+&wkup_i2c0 {
+ bootph-all;
+};
+
+&vdd_mpu {
+ bootph-all;
+};
+
+&ospi0 {
+ bootph-all;
+
+ flash@0 {
+ bootph-all;
+ };
+};
+
+&dwc3_0 {
+ bootph-all;
+};
+
+&scm_conf {
+ bootph-all;
+};
+
+&fss {
+ bootph-all;
+};
+
&pru0_0 {
remoteproc-name = "pru0_0";
};
@@ -81,3 +240,37 @@
&mcu_r5fss0 {
ti,cluster-mode = <0>;
};
+
+/*
+ * The DMA driver requires a few extra register ranges
+ * which are missing for the am65x. A patch has been
+ * sent and will be synced after the v6.8-rc1 linux
+ * tag is published
+ */
+&main_udmap {
+ reg = <0x0 0x31150000 0x0 0x100>,
+ <0x0 0x34000000 0x0 0x100000>,
+ <0x0 0x35000000 0x0 0x100000>,
+ <0x0 0x30b00000 0x0 0x10000>,
+ <0x0 0x30c00000 0x0 0x10000>,
+ <0x0 0x30d00000 0x0 0x8000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt",
+ "tchan", "rchan", "rflow";
+};
+
+/*
+ * The DMA driver requires a few extra register ranges
+ * which are missing for the am65x. A patch has been
+ * sent and will be synced after the v6.8-rc1 linux
+ * tag is published
+ */
+&mcu_udmap {
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x2aa00000 0x0 0x40000>,
+ <0x0 0x284a0000 0x0 0x4000>,
+ <0x0 0x284c0000 0x0 0x4000>,
+ <0x0 0x28400000 0x0 0x2000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt",
+ "tchan", "rchan", "rflow";
+};
diff --git a/arch/arm/dts/k3-am654-base-board.dts b/arch/arm/dts/k3-am654-base-board.dts
index cfbcebf..1637ec5 100644
--- a/arch/arm/dts/k3-am654-base-board.dts
+++ b/arch/arm/dts/k3-am654-base-board.dts
@@ -10,12 +10,25 @@
#include <dt-bindings/net/ti-dp83867.h>
/ {
- compatible = "ti,am654-evm", "ti,am654";
+ compatible = "ti,am654-evm", "ti,am654";
model = "Texas Instruments AM654 Base Board";
+ aliases {
+ serial0 = &wkup_uart0;
+ serial1 = &mcu_uart0;
+ serial2 = &main_uart0;
+ i2c0 = &wkup_i2c0;
+ i2c1 = &mcu_i2c0;
+ i2c2 = &main_i2c0;
+ i2c3 = &main_i2c1;
+ i2c4 = &main_i2c2;
+ ethernet0 = &cpsw_port1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ };
+
chosen {
stdout-path = "serial2:115200n8";
- bootargs = "earlycon=ns16550a,mmio32,0x02800000";
};
memory@80000000 {
@@ -73,20 +86,20 @@
pinctrl-names = "default";
pinctrl-0 = <&push_button_pins_default>;
- sw5 {
+ switch-5 {
label = "GPIO Key USER1";
linux,code = <BTN_0>;
gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>;
};
- sw6 {
+ switch-6 {
label = "GPIO Key USER2";
linux,code = <BTN_1>;
gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
};
};
- evm_12v0: fixedregulator-evm12v0 {
+ evm_12v0: regulator-0 {
/* main supply */
compatible = "regulator-fixed";
regulator-name = "evm_12v0";
@@ -96,7 +109,7 @@
regulator-boot-on;
};
- vcc3v3_io: fixedregulator-vcc3v3io {
+ vcc3v3_io: regulator-1 {
/* Output of TPS54334 */
compatible = "regulator-fixed";
regulator-name = "vcc3v3_io";
@@ -107,7 +120,7 @@
vin-supply = <&evm_12v0>;
};
- vdd_mmc1_sd: fixedregulator-sd {
+ vdd_mmc1_sd: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1_sd";
regulator-min-microvolt = <3300000>;
@@ -117,24 +130,53 @@
vin-supply = <&vcc3v3_io>;
gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
};
+
+ vtt_supply: regulator-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vtt";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ddr_vtt_pins_default>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc3v3_io>;
+ gpio = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>;
+ };
};
&wkup_pmx0 {
- wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ wkup_uart0_pins_default: wkup-uart0-default-pins {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */
+ AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */
+ AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */
+ AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */
+ >;
+ };
+
+ ddr_vtt_pins_default: ddr-vtt-default-pins {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */
+ >;
+ };
+
+ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
>;
};
- push_button_pins_default: push-button-pins-default {
+ push_button_pins_default: push-button-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */
AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */
>;
};
- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
@@ -150,13 +192,22 @@
>;
};
- wkup_pca554_default: wkup-pca554-default {
+ wkup_pca554_default: wkup-pca554-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
>;
};
- mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+ mcu_uart0_pins_default: mcu-uart0-default-pins {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */
+ AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */
+ AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
+ AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */
+ >;
+ };
+
+ mcu_cpsw_pins_default: mcu-cpsw-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
@@ -173,16 +224,23 @@
>;
};
- mcu_mdio_pins_default: mcu-mdio1-pins-default {
+ mcu_mdio_pins_default: mcu-mdio1-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
>;
};
+
+ mcu_i2c0_pins_default: mcu-i2c0-default-pins {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0) /* (AD8) MCU_I2C0_SCL */
+ AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0) /* (AD7) MCU_I2C0_SDA */
+ >;
+ };
};
&main_pmx0 {
- main_uart0_pins_default: main-uart0-pins-default {
+ main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
@@ -191,14 +249,14 @@
>;
};
- main_i2c2_pins_default: main-i2c2-pins-default {
+ main_i2c2_pins_default: main-i2c2-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */
AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */
>;
};
- main_spi0_pins_default: main-spi0-pins-default {
+ main_spi0_pins_default: main-spi0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */
AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */
@@ -207,7 +265,7 @@
>;
};
- main_mmc0_pins_default: main-mmc0-pins-default {
+ main_mmc0_pins_default: main-mmc0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
@@ -224,7 +282,7 @@
>;
};
- main_mmc1_pins_default: main-mmc1-pins-default {
+ main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
@@ -237,7 +295,7 @@
>;
};
- usb1_pins_default: usb1-pins-default {
+ usb1_pins_default: usb1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
>;
@@ -245,21 +303,21 @@
};
&main_pmx1 {
- main_i2c0_pins_default: main-i2c0-pins-default {
+ main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
>;
};
- main_i2c1_pins_default: main-i2c1-pins-default {
+ main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
>;
};
- ecap0_pins_default: ecap0-pins-default {
+ ecap0_pins_default: ecap0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
>;
@@ -269,19 +327,55 @@
&wkup_uart0 {
/* Wakeup UART is used by System firmware */
status = "reserved";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+};
+
+&mcu_uart0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_uart0_pins_default>;
};
&main_uart0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
&wkup_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
+ eeprom@50 {
+ /* AT24CM01 */
+ compatible = "atmel,24c1024";
+ reg = <0x50>;
+ };
+
+ vdd_mpu: regulator@60 {
+ compatible = "ti,tps62363";
+ reg = <0x60>;
+ regulator-name = "VDD_MPU";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1770000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ti,vsel0-state-high;
+ ti,vsel1-state-high;
+ ti,enable-vout-discharge;
+ };
+
+ gpio@38 {
+ compatible = "nxp,pca9554";
+ reg = <0x38>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
pca9554: gpio@39 {
compatible = "nxp,pca9554";
reg = <0x39>;
@@ -296,7 +390,15 @@
};
};
+&mcu_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_i2c0_pins_default>;
+ clock-frequency = <400000>;
+};
+
&main_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
@@ -310,37 +412,39 @@
};
&main_i2c1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
};
&main_i2c2 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c2_pins_default>;
clock-frequency = <400000>;
};
&ecap0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins_default>;
};
&main_spi0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_spi0_pins_default>;
#address-cells = <1>;
- #size-cells= <0>;
+ #size-cells = <0>;
ti,pindir-d0-out-d1-in;
- flash@0{
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
spi-max-frequency = <48000000>;
- #address-cells = <1>;
- #size-cells= <1>;
};
};
@@ -381,12 +485,14 @@
};
&tscadc0 {
+ status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
&tscadc1 {
+ status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
@@ -400,23 +506,8 @@
status = "disabled";
};
-&pcie0_rc {
- status = "disabled";
-};
-
-&pcie0_ep {
- status = "disabled";
-};
-
-&pcie1_rc {
- status = "disabled";
-};
-
-&pcie1_ep {
- status = "disabled";
-};
-
&mailbox0_cluster0 {
+ status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
@@ -426,6 +517,7 @@
};
&mailbox0_cluster1 {
+ status = "okay";
interrupts = <432>;
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
@@ -434,63 +526,24 @@
};
};
-&mailbox0_cluster2 {
- status = "disabled";
-};
-
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
-&mailbox0_cluster4 {
- status = "disabled";
-};
-
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
-&mailbox0_cluster6 {
- status = "disabled";
-};
-
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
-&mailbox0_cluster8 {
- status = "disabled";
-};
-
-&mailbox0_cluster9 {
- status = "disabled";
-};
-
-&mailbox0_cluster10 {
- status = "disabled";
-};
-
-&mailbox0_cluster11 {
- status = "disabled";
-};
-
&mcu_r5fss0_core0 {
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
- mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
};
&mcu_r5fss0_core1 {
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
- mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
};
&ospi0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
- flash@0{
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
@@ -501,17 +554,65 @@
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ospi.tiboot3";
+ reg = <0x0 0x80000>;
+ };
+
+ partition@80000 {
+ label = "ospi.tispl";
+ reg = <0x80000 0x200000>;
+ };
+
+ partition@280000 {
+ label = "ospi.u-boot";
+ reg = <0x280000 0x400000>;
+ };
+
+ partition@680000 {
+ label = "ospi.env";
+ reg = <0x680000 0x20000>;
+ };
+
+ partition@6a0000 {
+ label = "ospi.env.backup";
+ reg = <0x6a0000 0x20000>;
+ };
+
+ partition@6c0000 {
+ label = "ospi.sysfw";
+ reg = <0x6c0000 0x100000>;
+ };
+
+ partition@800000 {
+ label = "ospi.rootfs";
+ reg = <0x800000 0x37c0000>;
+ };
+
+ partition@3fe0000 {
+ label = "ospi.phypattern";
+ reg = <0x3fe0000 0x20000>;
+ };
+ };
};
};
&mcu_cpsw {
pinctrl-names = "default";
- pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+ pinctrl-0 = <&mcu_cpsw_pins_default>;
};
&davinci_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mdio_pins_default>;
+
phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
@@ -524,30 +625,6 @@
phy-handle = <&phy0>;
};
-&mcasp0 {
- status = "disabled";
-};
-
-&mcasp1 {
- status = "disabled";
-};
-
-&mcasp2 {
- status = "disabled";
-};
-
&dss {
status = "disabled";
};
-
-&icssg0_mdio {
- status = "disabled";
-};
-
-&icssg1_mdio {
- status = "disabled";
-};
-
-&icssg2_mdio {
- status = "disabled";
-};
diff --git a/arch/arm/dts/k3-am654-ddr.dtsi b/arch/arm/dts/k3-am654-ddr.dtsi
index 48698cd..9f0586e 100644
--- a/arch/arm/dts/k3-am654-ddr.dtsi
+++ b/arch/arm/dts/k3-am654-ddr.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
diff --git a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
deleted file mode 100644
index 949320c..0000000
--- a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
+++ /dev/null
@@ -1,208 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - http://www.ti.com/
- */
-
-#include <dt-bindings/pinctrl/k3.h>
-#include <dt-bindings/net/ti-dp83867.h>
-#include "k3-am65x-binman.dtsi"
-
-/ {
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- aliases {
- serial2 = &main_uart0;
- ethernet0 = &cpsw_port1;
- usb0 = &usb0;
- usb1 = &usb1;
- spi0 = &ospi0;
- spi1 = &ospi1;
- };
-};
-
-&cbass_main{
- bootph-pre-ram;
- main_navss: bus@30800000 {
- bootph-pre-ram;
- };
-};
-
-&cbass_mcu {
- bootph-pre-ram;
-
- mcu_navss: bus@28380000 {
- bootph-pre-ram;
-
- ringacc@2b800000 {
- reg = <0x0 0x2b800000 0x0 0x400000>,
- <0x0 0x2b000000 0x0 0x400000>,
- <0x0 0x28590000 0x0 0x100>,
- <0x0 0x2a500000 0x0 0x40000>,
- <0x0 0x28440000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- bootph-pre-ram;
- ti,dma-ring-reset-quirk;
- };
-
- dma-controller@285c0000 {
- reg = <0x0 0x285c0000 0x0 0x100>,
- <0x0 0x284c0000 0x0 0x4000>,
- <0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x284a0000 0x0 0x4000>,
- <0x0 0x2aa00000 0x0 0x40000>,
- <0x0 0x28400000 0x0 0x2000>;
- reg-names = "gcfg", "rchan", "rchanrt", "tchan",
- "tchanrt", "rflow";
- bootph-pre-ram;
- };
- };
-};
-
-&cbass_wakeup {
- bootph-pre-ram;
-
- chipid@43000014 {
- bootph-pre-ram;
- };
-};
-
-&secure_proxy_main {
- bootph-pre-ram;
-};
-
-&dmsc {
- bootph-pre-ram;
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- bootph-pre-ram;
- };
-};
-
-&k3_pds {
- bootph-pre-ram;
-};
-
-&k3_clks {
- bootph-pre-ram;
-};
-
-&k3_reset {
- bootph-pre-ram;
-};
-
-&wkup_pmx0 {
- bootph-pre-ram;
-
- wkup_i2c0_pins_default {
- bootph-pre-ram;
- };
-};
-
-&main_pmx0 {
- bootph-pre-ram;
- usb0_pins_default: usb0_pins_default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
- >;
- bootph-pre-ram;
- };
-};
-
-&main_uart0_pins_default {
- bootph-pre-ram;
-};
-
-&main_pmx1 {
- bootph-pre-ram;
-};
-
-&wkup_pmx0 {
- mcu-fss0-ospi0-pins-default {
- bootph-pre-ram;
- };
-};
-
-&main_uart0 {
- bootph-pre-ram;
-};
-
-&main_mmc0_pins_default {
- bootph-pre-ram;
-};
-
-&main_mmc1_pins_default {
- bootph-pre-ram;
-};
-
-&sdhci0 {
- bootph-pre-ram;
-};
-
-&sdhci1 {
- bootph-pre-ram;
-};
-
-&davinci_mdio {
- phy0: ethernet-phy@0 {
- reg = <0>;
- /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
-};
-
-&mcu_cpsw {
- reg = <0x0 0x46000000 0x0 0x200000>,
- <0x0 0x40f00200 0x0 0x2>;
- reg-names = "cpsw_nuss", "mac_efuse";
- /delete-property/ ranges;
-
- cpsw-phy-sel@40f04040 {
- compatible = "ti,am654-cpsw-phy-sel";
- reg= <0x0 0x40f04040 0x0 0x4>;
- reg-names = "gmii-sel";
- };
-};
-
-&wkup_i2c0 {
- bootph-pre-ram;
-};
-
-&usb1 {
- dr_mode = "peripheral";
-};
-
-&fss {
- bootph-pre-ram;
-};
-
-&ospi0 {
- bootph-pre-ram;
-
- flash@0{
- bootph-pre-ram;
- };
-};
-
-&dwc3_0 {
- status = "okay";
- bootph-pre-ram;
-};
-
-&usb0_phy {
- status = "okay";
- bootph-pre-ram;
-};
-
-&usb0 {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_pins_default>;
- dr_mode = "peripheral";
- bootph-pre-ram;
-};
-
-&scm_conf {
- bootph-pre-ram;
-};
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index 7671875..dea2ba8 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -1,29 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-#include "k3-am654.dtsi"
+#include "k3-am654-base-board.dts"
+#include "k3-am654-base-board-u-boot.dtsi"
#include "k3-am654-base-board-ddr4-1600MTs.dtsi"
#include "k3-am654-ddr.dtsi"
/ {
- compatible = "ti,am654-evm", "ti,am654";
- model = "Texas Instruments AM654 R5 Base Board";
-
- aliases {
- serial0 = &wkup_uart0;
- serial1 = &mcu_uart0;
- serial2 = &main_uart0;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
-
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
@@ -44,51 +31,6 @@
bootph-pre-ram;
};
- vtt_supply: vtt_supply {
- compatible = "regulator-gpio";
- regulator-name = "vtt";
- regulator-min-microvolt = <0>;
- regulator-max-microvolt = <3300000>;
- gpios = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>;
- states = <0 0x0 3300000 0x1>;
- bootph-pre-ram;
- };
-};
-
-&cbass_main {
- timer1: timer@40400000 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x40400000 0x0 0x80>;
- ti,timer-alwon;
- clock-frequency = <25000000>;
- bootph-all;
- };
-};
-
-&cbass_mcu {
- mcu_secproxy: secproxy@28380000 {
- compatible = "ti,am654-secure-proxy";
- reg = <0x0 0x2a380000 0x0 0x80000>,
- <0x0 0x2a400000 0x0 0x80000>,
- <0x0 0x2a480000 0x0 0x80000>;
- reg-names = "rt", "scfg", "target_data";
- #mbox-cells = <1>;
- bootph-pre-ram;
- };
-};
-
-&wkup_gpio0 {
- bootph-pre-ram;
-};
-
-&cbass_wakeup {
- sysctrler: sysctrler {
- compatible = "ti,am654-system-controller";
- mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
- mbox-names = "tx", "rx";
- bootph-pre-ram;
- };
-
clk_200mhz: dummy_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -97,237 +39,120 @@
};
};
+&secure_proxy_mcu {
+ status = "okay";
+ bootph-pre-ram;
+};
+
+&cbass_wakeup {
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
+ mbox-names = "tx", "rx";
+ bootph-pre-ram;
+ };
+};
+
+/*
+ * timer init is called as part of rproc_start() while
+ * starting System Firmware, so any clock/power-domain
+ * operations will fail as SYSFW is not yet up and running.
+ * Delete all clock/power-domain properties to avoid
+ * timer init failure.
+ * This is an always on timer at 20MHz.
+ */
+&mcu_timer0 {
+ /delete-property/ clocks;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ power-domains;
+};
+
&dmsc {
- mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
+ mboxes = <&secure_proxy_mcu 8>,
+ <&secure_proxy_mcu 6>,
+ <&secure_proxy_mcu 5>;
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
};
&wkup_uart0 {
- bootph-pre-ram;
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
+ bootph-pre-ram;
};
&mcu_uart0 {
- bootph-pre-ram;
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_uart0_pins_default>;
clock-frequency = <48000000>;
/delete-property/ power-domains;
status = "okay";
-};
-
-&main_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
- power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
- status = "okay";
+ bootph-pre-ram;
};
&wkup_vtm0 {
compatible = "ti,am654-vtm", "ti,am654-avs";
vdd-supply-3 = <&vdd_mpu>;
vdd-supply-4 = <&vdd_mpu>;
- bootph-pre-ram;
-};
-
-&wkup_pmx0 {
- bootph-pre-ram;
- wkup_uart0_pins_default: wkup_uart0_pins_default {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */
- AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */
- AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */
- AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */
- >;
- bootph-pre-ram;
- };
-
- wkup_vtt_pins_default: wkup_vtt_pins_default {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */
- >;
- bootph-pre-ram;
- };
-
- mcu_uart0_pins_default: mcu_uart0_pins_default {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */
- AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */
- AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
- AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */
- >;
- bootph-pre-ram;
- };
-
- wkup_i2c0_pins_default: wkup-i2c0-pins-default {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
- AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
- >;
- };
-
- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
- AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
- AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */
- AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */
- AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */
- AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */
- AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */
- AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */
- AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */
- AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */
- AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
- >;
- };
-};
-
-&main_pmx0 {
- bootph-pre-ram;
- main_uart0_pins_default: main-uart0-pins-default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
- AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
- AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
- AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
- >;
- bootph-pre-ram;
- };
-
- main_mmc0_pins_default: main_mmc0_pins_default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
- AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
- AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
- AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
- AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
- AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
- AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
- AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
- AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
- AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
- AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
- >;
- bootph-pre-ram;
- };
-
- main_mmc1_pins_default: main_mmc1_pins_default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
- AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
- AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
- AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
- AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
- AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
- AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
- AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
- >;
- bootph-pre-ram;
- };
};
&memorycontroller {
vtt-supply = <&vtt_supply>;
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_vtt_pins_default>;
};
+/*
+ * MMC is probed to pull in firmware, so any clock
+ * or power-domain operation will fail as we do not
+ * have the firmware running at this point. Delete the
+ * power-domain properties to avoid making calls to
+ * SYSFW before it is loaded. Public ROM has already
+ * set it up for us anyway.
+ */
&sdhci0 {
clock-names = "clk_xin";
clocks = <&clk_200mhz>;
- pinctrl-0 = <&main_mmc0_pins_default>;
/delete-property/ power-domains;
- ti,driver-strength-ohm = <50>;
};
+/*
+ * MMC is probed to pull in firmware, so any clock
+ * or power-domain operation will fail as we do not
+ * have the firmware running at this point. Delete the
+ * power-domain properties to avoid making calls to
+ * SYSFW before it is loaded. Public ROM has already
+ * set it up for us anyway.
+ */
&sdhci1 {
clock-names = "clk_xin";
clocks = <&clk_200mhz>;
- pinctrl-0 = <&main_mmc1_pins_default>;
/delete-property/ power-domains;
- ti,driver-strength-ohm = <50>;
-};
-
-&wkup_i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_i2c0_pins_default>;
- clock-frequency = <400000>;
- bootph-pre-ram;
-
- vdd_mpu: tps62363@60 {
- compatible = "ti,tps62363";
- reg = <0x60>;
- regulator-name = "VDD_MPU";
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1770000>;
- regulator-always-on;
- regulator-boot-on;
- ti,vsel0-state-high;
- ti,vsel1-state-high;
- bootph-pre-ram;
- };
};
&ospi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
-
reg = <0x0 0x47040000 0x0 0x100>,
<0x0 0x50000000 0x0 0x8000000>;
-
- flash@0{
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <8>;
- spi-max-frequency = <50000000>;
- cdns,tshsl-ns = <60>;
- cdns,tsd2d-ns = <60>;
- cdns,tchsh-ns = <60>;
- cdns,tslch-ns = <60>;
- cdns,read-delay = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-};
-
-&main_pmx0 {
- bootph-pre-ram;
- usb0_pins_default: usb0_pins_default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
- >;
- bootph-pre-ram;
- };
};
&dwc3_0 {
status = "okay";
- bootph-pre-ram;
/delete-property/ clocks;
/delete-property/ power-domains;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
};
-&usb0_phy {
- status = "okay";
- bootph-pre-ram;
- /delete-property/ clocks;
+&mcu_cpsw {
+ reg = <0x0 0x46000000 0x0 0x200000>,
+ <0x0 0x40f00200 0x0 0x2>;
+ reg-names = "cpsw_nuss", "mac_efuse";
+ /delete-property/ ranges;
+
+ cpsw-phy-sel@40f04040 {
+ compatible = "ti,am654-cpsw-phy-sel";
+ reg= <0x0 0x40f04040 0x0 0x4>;
+ reg-names = "gmii-sel";
+ };
};
-&usb0 {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_pins_default>;
+&usb1 {
dr_mode = "peripheral";
- bootph-pre-ram;
-};
-
-&scm_conf {
- bootph-pre-ram;
};
diff --git a/arch/arm/dts/k3-am654.dtsi b/arch/arm/dts/k3-am654.dtsi
index f0a6541..888567b 100644
--- a/arch/arm/dts/k3-am654.dtsi
+++ b/arch/arm/dts/k3-am654.dtsi
@@ -93,6 +93,7 @@
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
@@ -102,6 +103,7 @@
L2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
@@ -111,5 +113,10 @@
msmc_l3: l3-cache0 {
compatible = "cache";
cache-level = <3>;
+ cache-unified;
+ };
+
+ thermal_zones: thermal-zones {
+ #include "k3-am654-industrial-thermal.dtsi"
};
};
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi b/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi
index d25e8b2..be55494 100644
--- a/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi
+++ b/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi
@@ -22,7 +22,7 @@
};
&main_pmx0 {
- main_mmc0_pins_default: main-mmc0-pins-default {
+ main_mmc0_pins_default: main-mmc0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
@@ -50,7 +50,3 @@
ti,driver-strength-ohm = <50>;
disable-wp;
};
-
-&main_uart0 {
- status = "disabled";
-};
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dts b/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtso
similarity index 100%
rename from arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dts
rename to arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtso
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dts b/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtso
similarity index 100%
rename from arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dts
rename to arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtso
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-m2.dts b/arch/arm/dts/k3-am6548-iot2050-advanced-m2.dts
index 9400e35..774eb14 100644
--- a/arch/arm/dts/k3-am6548-iot2050-advanced-m2.dts
+++ b/arch/arm/dts/k3-am6548-iot2050-advanced-m2.dts
@@ -27,26 +27,26 @@
};
&main_pmx0 {
- main_m2_enable_pins_default: main-m2-enable-pins-default {
+ main_m2_enable_pins_default: main-m2-enable-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */
>;
};
- main_bkey_pcie_reset: main-bkey-pcie-reset {
+ main_bkey_pcie_reset: main-bkey-pcie-reset-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */
>;
};
- main_pmx0_m2_config_pins_default: main-pmx0-m2-config-pins-default {
+ main_pmx0_m2_config_pins_default: main-pmx0-m2-config-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c8, PIN_INPUT_PULLUP, 7) /* (AE13) GPIO1_18 */
AM65X_IOPAD(0x01cc, PIN_INPUT_PULLUP, 7) /* (AD13) GPIO1_19 */
>;
};
- main_m2_pcie_mux_control: main-m2-pcie-mux-control {
+ main_m2_pcie_mux_control: main-m2-pcie-mux-control-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0148, PIN_INPUT_PULLUP, 7) /* (AG22) GPIO0_82 */
AM65X_IOPAD(0x0160, PIN_INPUT_PULLUP, 7) /* (AE20) GPIO0_88 */
@@ -56,7 +56,7 @@
};
&main_pmx1 {
- main_pmx1_m2_config_pins_default: main-pmx1-m2-config-pins-default {
+ main_pmx1_m2_config_pins_default: main-pmx1-m2-config-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0018, PIN_INPUT_PULLUP, 7) /* (B22) GPIO1_88 */
AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7) /* (C23) GPIO1_89 */
@@ -66,20 +66,18 @@
&main_gpio0 {
pinctrl-names = "default";
- pinctrl-0 = <
- &main_m2_pcie_mux_control
- &arduino_io_d4_to_d9_pins_default
- >;
+ pinctrl-0 =
+ <&main_m2_pcie_mux_control>,
+ <&arduino_io_d4_to_d9_pins_default>;
};
&main_gpio1 {
pinctrl-names = "default";
- pinctrl-0 = <
- &main_m2_enable_pins_default
- &main_pmx0_m2_config_pins_default
- &main_pmx1_m2_config_pins_default
- &cp2102n_reset_pin_default
- >;
+ pinctrl-0 =
+ <&main_m2_enable_pins_default>,
+ <&main_pmx0_m2_config_pins_default>,
+ <&main_pmx1_m2_config_pins_default>,
+ <&cp2102n_reset_pin_default>;
};
/*
diff --git a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi
index 79faa1b..4f34347 100644
--- a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi
@@ -1,69 +1,36 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-j721s2-binman.dtsi"
-/ {
- chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
-
- aliases {
- serial0 = &wkup_uart0;
- serial1 = &mcu_uart0;
- serial2 = &main_uart8;
- i2c0 = &wkup_i2c0;
- i2c1 = &mcu_i2c0;
- i2c2 = &mcu_i2c1;
- i2c3 = &main_i2c0;
- ethernet0 = &cpsw_port1;
- mmc1 = &main_sdhci1;
- };
-};
-
&wkup_i2c0 {
- bootph-pre-ram;
+ bootph-all;
};
&cbass_main {
- bootph-pre-ram;
+ bootph-all;
};
&main_navss {
- bootph-pre-ram;
+ bootph-all;
};
&cbass_mcu_wakeup {
- bootph-pre-ram;
-
- timer1: timer@40400000 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x40400000 0x0 0x80>;
- ti,timer-alwon;
- clock-frequency = <250000000>;
- bootph-pre-ram;
- };
+ bootph-all;
chipid@43000014 {
- bootph-pre-ram;
+ bootph-all;
};
};
&mcu_navss {
- bootph-pre-ram;
+ bootph-all;
};
&mcu_ringacc {
- reg = <0x0 0x2b800000 0x0 0x400000>,
- <0x0 0x2b000000 0x0 0x400000>,
- <0x0 0x28590000 0x0 0x100>,
- <0x0 0x2a500000 0x0 0x40000>,
- <0x0 0x28440000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- bootph-pre-ram;
+ bootph-all;
};
&mcu_udmap {
@@ -75,78 +42,94 @@
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
"tchanrt", "rflow";
- bootph-pre-ram;
+ bootph-all;
};
&secure_proxy_main {
- bootph-pre-ram;
+ bootph-all;
};
&sms {
- bootph-pre-ram;
+ bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- bootph-pre-ram;
+ bootph-all;
};
};
&main_pmx0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_uart8_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&main_mmc1_pins_default {
- bootph-pre-ram;
+ bootph-all;
+};
+
+&main_usbss0_pins_default {
+ bootph-all;
};
&wkup_pmx0 {
- bootph-pre-ram;
+ bootph-all;
+};
+
+&wkup_pmx1 {
+ bootph-all;
+};
+
+&wkup_pmx2 {
+ bootph-all;
+};
+
+&wkup_pmx3 {
+ bootph-all;
};
&k3_pds {
- bootph-pre-ram;
+ bootph-all;
};
&k3_clks {
- bootph-pre-ram;
+ bootph-all;
};
&k3_reset {
- bootph-pre-ram;
+ bootph-all;
};
&main_uart8 {
- bootph-pre-ram;
+ bootph-all;
};
&mcu_uart0 {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_uart0 {
- bootph-pre-ram;
-};
-
-&mcu_cpsw {
- reg = <0x0 0x46000000 0x0 0x200000>,
- <0x0 0x40f00200 0x0 0x8>;
- reg-names = "cpsw_nuss", "mac_efuse";
- /delete-property/ ranges;
-
- cpsw-phy-sel@40f04040 {
- compatible = "ti,am654-cpsw-phy-sel";
- reg= <0x0 0x40f04040 0x0 0x4>;
- reg-names = "gmii-sel";
- };
-};
-
-&main_sdhci0 {
- status = "disabled";
+ bootph-all;
};
&main_sdhci1 {
- bootph-pre-ram;
+ bootph-all;
+};
+
+&ospi0 {
+ status = "disabled";
+};
+
+&ospi1 {
+ status = "disabled";
+};
+
+&usbss0 {
+ bootph-all;
+};
+
+&usb0 {
+ dr_mode = "peripheral";
+ bootph-all;
};
diff --git a/arch/arm/dts/k3-am68-sk-base-board.dts b/arch/arm/dts/k3-am68-sk-base-board.dts
index 8fc0332..5df5946 100644
--- a/arch/arm/dts/k3-am68-sk-base-board.dts
+++ b/arch/arm/dts/k3-am68-sk-base-board.dts
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*
- * Base Board: **Yet to Add**
+ * Base Board: https://www.ti.com/lit/zip/SPRR463
*/
/dts-v1/;
@@ -12,21 +12,28 @@
#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy.h>
+#include "k3-serdes.h"
+
/ {
compatible = "ti,am68-sk", "ti,j721s2";
model = "Texas Instruments AM68 SK";
chosen {
stdout-path = "serial2:115200n8";
- bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x2880000";
};
aliases {
+ serial0 = &wkup_uart0;
+ serial1 = &mcu_uart0;
serial2 = &main_uart8;
mmc1 = &main_sdhci1;
+ can0 = &mcu_mcan0;
+ can1 = &mcu_mcan1;
+ can2 = &main_mcan6;
+ can3 = &main_mcan7;
};
- vusb_main: fixedregulator-vusb-main5v0 {
+ vusb_main: regulator-vusb-main5v0 {
/* USB MAIN INPUT 5V DC */
compatible = "regulator-fixed";
regulator-name = "vusb-main5v0";
@@ -36,7 +43,7 @@
regulator-boot-on;
};
- vsys_3v3: fixedregulator-vsys3v3 {
+ vsys_3v3: regulator-vsys3v3 {
/* Output of LM5141 */
compatible = "regulator-fixed";
regulator-name = "vsys_3v3";
@@ -47,7 +54,7 @@
regulator-boot-on;
};
- vdd_mmc1: fixedregulator-sd {
+ vdd_mmc1: regulator-sd {
/* Output of TPS22918 */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
@@ -56,10 +63,10 @@
regulator-boot-on;
enable-active-high;
vin-supply = <&vsys_3v3>;
- gpio = <&exp1 10 GPIO_ACTIVE_HIGH>;
+ gpio = <&exp1 8 GPIO_ACTIVE_HIGH>;
};
- vdd_sd_dv: gpio-regulator-TLV71033 {
+ vdd_sd_dv: regulator-tlv71033 {
/* Output of TLV71033 */
compatible = "regulator-gpio";
regulator-name = "tlv71033";
@@ -73,30 +80,115 @@
states = <1800000 0x0>,
<3300000 0x1>;
};
+
+ vsys_io_1v8: regulator-vsys-io-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_io_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_io_1v2: regulator-vsys-io-1v2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_io_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ transceiver1: can-phy0 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ };
+
+ transceiver2: can-phy1 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ };
+
+ transceiver3: can-phy2 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ };
+
+ transceiver4: can-phy3 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ };
+
+ connector-hdmi {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_hpd_pins_default>;
+ ddc-i2c-bus = <&mcu_i2c1>;
+ /* HDMI_HPD */
+ hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>;
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tfp410_out>;
+ };
+ };
+ };
+
+ bridge-dvi {
+ compatible = "ti,tfp410";
+ /* HDMI_PDn */
+ powerdown-gpios = <&exp2 0 GPIO_ACTIVE_LOW>;
+ ti,deskew = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tfp410_in: endpoint {
+ remote-endpoint = <&dpi_out0>;
+ pclk-sample = <1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tfp410_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
};
&main_pmx0 {
- main_uart8_pins_default: main-uart8-pins-default {
+ main_uart8_pins_default: main-uart8-default-pins {
pinctrl-single,pins = <
- J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */
- J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
>;
};
- main_i2c0_pins_default: i2c0-pins-default {
+ main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
- J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */
- J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */
+ J721S2_IOPAD(0x0e0, PIN_INPUT, 0) /* (AH25) I2C0_SCL */
+ J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */
>;
};
- main_mmc1_pins_default: main-mmc1-pins-default {
+ main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
- J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
@@ -105,102 +197,222 @@
>;
};
- vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
+ vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 */
>;
};
-};
-&wkup_pmx0 {
- mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+ main_usbss0_pins_default: main-usbss0-default-pins {
pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
- J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
- J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
- J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
- J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
- J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
- J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
- J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
- J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
- J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
- J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
- J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
+ J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
>;
};
- mcu_mdio_pins_default: mcu-mdio-pins-default {
+ main_mcan6_pins_default: main-mcan6-default-pins {
pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
- J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
+ J721S2_IOPAD(0x098, PIN_INPUT, 0) /* (V25) MCASP0_AXR10.MCAN6_RX */
+ J721S2_IOPAD(0x094, PIN_INPUT, 0) /* (AA25) MCASP0_AXR9.MCAN6_TX */
+ >;
+ };
+
+ main_mcan7_pins_default: main-mcan7-default-pins {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */
+ J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */
+ >;
+ };
+
+ main_i2c4_pins_default: main-i2c4-default-pins {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */
+ J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */
+ >;
+ };
+
+ rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */
+ J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */
+ J721S2_IOPAD(0x0bc, PIN_INPUT, 7) /* (V28) MCASP1_AFSX.GPIO0_47 */
+ J721S2_IOPAD(0x06c, PIN_INPUT, 7) /* (V26) MCAN1_TX.GPIO0_27 */
+ J721S2_IOPAD(0x004, PIN_INPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */
+ J721S2_IOPAD(0x008, PIN_INPUT, 7) /* (AC24) MCAN12_RX.GPIO0_2 */
+ J721S2_IOPAD(0x0b8, PIN_INPUT, 7) /* (AA24) MCASP1_ACLKX.GPIO0_46 */
+ J721S2_IOPAD(0x00c, PIN_INPUT, 7) /* (AE28) MCAN13_TX.GPIO0_3 */
+ J721S2_IOPAD(0x034, PIN_INPUT, 7) /* (AD24) PMIC_WAKE0.GPIO0_13 */
+ J721S2_IOPAD(0x0a4, PIN_INPUT, 7) /* (T23) MCASP0_AXR13.GPIO0_41 */
+ J721S2_IOPAD(0x0c0, PIN_INPUT, 7) /* (T28) MCASP1_AXR0.GPIO0_48 */
+ J721S2_IOPAD(0x0b4, PIN_INPUT, 7) /* (U25) MCASP1_AXR4.GPIO0_45 */
+ J721S2_IOPAD(0x0cc, PIN_INPUT, 7) /* (AE27) SPI0_CS0.GPIO0_51 */
+ J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */
+ >;
+ };
+
+ dss_vout0_pins_default: dss-vout0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x074, PIN_OUTPUT, 2) /* (R28) MCAN2_TX.VOUT0_DATA0 */
+ J721S2_IOPAD(0x070, PIN_OUTPUT, 2) /* (R27) MCAN1_RX.VOUT0_DATA1 */
+ J721S2_IOPAD(0x04c, PIN_OUTPUT, 2) /* (V27) MCASP1_AXR1.VOUT0_DATA10 */
+ J721S2_IOPAD(0x048, PIN_OUTPUT, 2) /* (AB27) MCASP0_AXR2.VOUT0_DATA11 */
+ J721S2_IOPAD(0x044, PIN_OUTPUT, 2) /* (Y26) MCASP0_AXR1.VOUT0_DATA12 */
+ J721S2_IOPAD(0x040, PIN_OUTPUT, 2) /* (AC28) MCASP0_AXR0.VOUT0_DATA13 */
+ J721S2_IOPAD(0x03c, PIN_OUTPUT, 2) /* (U27) MCASP0_AFSX.VOUT0_DATA14 */
+ J721S2_IOPAD(0x038, PIN_OUTPUT, 2) /* (AB28) MCASP0_ACLKX.VOUT0_DATA15 */
+ J721S2_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AD28) EXT_REFCLK1.VOUT0_DATA16 */
+ J721S2_IOPAD(0x030, PIN_OUTPUT, 2) /* (T26) GPIO0_12.VOUT0_DATA17 */
+ J721S2_IOPAD(0x02c, PIN_OUTPUT, 2) /* (V23) GPIO0_11.VOUT0_DATA18 */
+ J721S2_IOPAD(0x028, PIN_OUTPUT, 2) /* (AB24) MCAN16_RX.VOUT0_DATA19 */
+ J721S2_IOPAD(0x07c, PIN_OUTPUT, 2) /* (T27) MCASP0_AXR3.VOUT0_DATA2 */
+ J721S2_IOPAD(0x024, PIN_OUTPUT, 2) /* (Y28) MCAN16_TX.VOUT0_DATA20 */
+ J721S2_IOPAD(0x020, PIN_OUTPUT, 2) /* (AA23) MCAN15_RX.VOUT0_DATA21 */
+ J721S2_IOPAD(0x01c, PIN_OUTPUT, 2) /* (Y24) MCAN15_TX.VOUT0_DATA22 */
+ J721S2_IOPAD(0x018, PIN_OUTPUT, 2) /* (W23) MCAN14_RX.VOUT0_DATA23 */
+ J721S2_IOPAD(0x068, PIN_OUTPUT, 2) /* (U28) MCAN0_RX.VOUT0_DATA3 */
+ J721S2_IOPAD(0x064, PIN_OUTPUT, 2) /* (W28) MCAN0_TX.VOUT0_DATA4 */
+ J721S2_IOPAD(0x060, PIN_OUTPUT, 2) /* (AC27) MCASP2_AXR1.VOUT0_DATA5 */
+ J721S2_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AA26) MCASP2_AXR0.VOUT0_DATA6 */
+ J721S2_IOPAD(0x058, PIN_OUTPUT, 2) /* (AA27) MCASP2_AFSX.VOUT0_DATA7 */
+ J721S2_IOPAD(0x054, PIN_OUTPUT, 2) /* (Y27) MCASP2_ACLKX.VOUT0_DATA8 */
+ J721S2_IOPAD(0x050, PIN_OUTPUT, 2) /* (W27) MCASP1_AXR2.VOUT0_DATA9 */
+ J721S2_IOPAD(0x084, PIN_OUTPUT, 2) /* (AA28) MCASP0_AXR5.VOUT0_DE */
+ J721S2_IOPAD(0x080, PIN_OUTPUT, 2) /* (U26) MCASP0_AXR4.VOUT0_HSYNC */
+ J721S2_IOPAD(0x078, PIN_OUTPUT, 2) /* (Y25) MCAN2_RX.VOUT0_PCLK */
+ J721S2_IOPAD(0x088, PIN_OUTPUT, 2) /* (AD27) MCASP0_AXR6.VOUT0_VP0_VSYNC */
+ >;
+ };
+
+ hdmi_hpd_pins_default: hdmi-hpd-default-pins {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x000, PIN_INPUT, 7) /* (AG24) EXTINTN.GPIO0_0 */
>;
};
};
-&main_gpio2 {
- status = "disabled";
+&wkup_pmx2 {
+ wkup_uart0_pins_default: wkup-uart0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
+ J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
+ J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
+ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
+ >;
+ };
+
+ mcu_cpsw_pins_default: mcu-cpsw-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
+ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
+ J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
+ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
+ J721S2_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
+ J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
+ J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
+ J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
+ J721S2_WKUP_IOPAD(0x00C, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
+ J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
+ J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
+ J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
+ >;
+ };
+
+ mcu_mdio_pins_default: mcu-mdio-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
+ J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
+ >;
+ };
+
+ mcu_mcan0_pins_default: mcu-mcan0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */
+ J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
+ >;
+ };
+
+ mcu_mcan1_pins_default: mcu-mcan1-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
+ J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/
+ >;
+ };
+
+ mcu_i2c0_pins_default: mcu-i2c0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (G24) MCU_I2C0_SCL */
+ J721S2_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (J25) MCU_I2C0_SDA */
+ >;
+ };
+
+ mcu_i2c1_pins_default: mcu-i2c1-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x078, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */
+ J721S2_WKUP_IOPAD(0x07c, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */
+ >;
+ };
+
+ mcu_uart0_pins_default: mcu-uart0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
+ J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
+ >;
+ };
+
+ mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */
+ J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */
+ J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */
+ J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */
+ J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/
+ J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */
+ J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */
+ J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */
+ J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */
+ >;
+ };
};
-&main_gpio4 {
- status = "disabled";
+&wkup_pmx3 {
+ mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-default-pins-1 {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */
+ >;
+ };
};
-&main_gpio6 {
- status = "disabled";
+&main_gpio0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rpi_header_gpio0_pins_default>;
};
-&wkup_gpio1 {
- status = "disabled";
+&wkup_gpio0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpio0_pins1_default>;
};
&wkup_uart0 {
status = "reserved";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
};
-&main_uart0 {
- status = "disabled";
-};
-
-&main_uart1 {
- status = "disabled";
-};
-
-&main_uart2 {
- status = "disabled";
-};
-
-&main_uart3 {
- status = "disabled";
-};
-
-&main_uart4 {
- status = "disabled";
-};
-
-&main_uart5 {
- status = "disabled";
-};
-
-&main_uart6 {
- status = "disabled";
-};
-
-&main_uart7 {
- status = "disabled";
+&mcu_uart0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_uart0_pins_default>;
};
&main_uart8 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart8_pins_default>;
/* Shared with TFA on this platform */
power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
};
-&main_uart9 {
- status = "disabled";
-};
-
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
@@ -211,45 +423,47 @@
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
- gpio-line-names = "CSI_VIO_SEL", "CSI_SEL_FPC_EXPN", "HDMI_PDN",
- "HDMI_LS_OE", "DP0_3V3_EN", "BOARDID_EEPROM_WP",
- "CAN_STB", "","GPIO_uSD_PWR_EN", "EDP_ENABLE",
- "IO_EXP_PCIE1_M2_RSTZ", "IO_EXP_MCU_RGMII_RSTZ",
- "IO_EXP_CSI1_EXP_RSTZ", "","CSI0_B_GPIO1",
- "CSI1_B_GPIO1";
+ gpio-line-names = " ", " ", " ", " ", " ",
+ "BOARDID_EEPROM_WP", "CAN_STB", " ",
+ "GPIO_uSD_PWR_EN", " ", "IO_EXP_PCIe1_M.2_RTSz",
+ "IO_EXP_MCU_RGMII_RST#", " ", " ", " ", " ";
};
};
-&main_i2c1 {
- status = "disabled";
-};
-
-&main_i2c2 {
- status = "disabled";
-};
-
-&main_i2c3 {
- status = "disabled";
-};
-
&main_i2c4 {
- status = "disabled";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c4_pins_default>;
+ clock-frequency = <400000>;
};
-&main_i2c5 {
- status = "disabled";
+&mcu_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_i2c0_pins_default>;
+ clock-frequency = <400000>;
};
-&main_i2c6 {
- status = "disabled";
-};
+&mcu_i2c1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_i2c1_pins_default>;
+ /* i2c1 is used for DVI DDC, so we need to use 100kHz */
+ clock-frequency = <100000>;
-&main_sdhci0 {
- status = "disabled";
+ exp2: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "HDMI_PDn","HDMI_LS_OE",
+ "DP0_3V3_EN","eDP_ENABLE";
+ };
};
&main_sdhci1 {
/* SD card */
+ status = "okay";
pinctrl-0 = <&main_mmc1_pins_default>;
pinctrl-names = "default";
disable-wp;
@@ -259,7 +473,7 @@
&mcu_cpsw {
pinctrl-names = "default";
- pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+ pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
};
&davinci_mdio {
@@ -277,77 +491,65 @@
};
&mcu_mcan0 {
- status = "disabled";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan0_pins_default>;
+ phys = <&transceiver1>;
};
&mcu_mcan1 {
- status = "disabled";
-};
-
-&main_mcan0 {
- status = "disabled";
-};
-
-&main_mcan1 {
- status = "disabled";
-};
-
-&main_mcan2 {
- status = "disabled";
-};
-
-&main_mcan3 {
- status = "disabled";
-};
-
-&main_mcan4 {
- status = "disabled";
-};
-
-&main_mcan5 {
- status = "disabled";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan1_pins_default>;
+ phys = <&transceiver2>;
};
&main_mcan6 {
- status = "disabled";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan6_pins_default>;
+ phys = <&transceiver3>;
};
&main_mcan7 {
- status = "disabled";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan7_pins_default>;
+ phys = <&transceiver4>;
};
-&main_mcan8 {
- status = "disabled";
+&dss {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dss_vout0_pins_default>;
+ /*
+ * These clock assignments are chosen to enable the following outputs:
+ *
+ * VP0 - DisplayPort SST
+ * VP1 - DPI0
+ * VP2 - DSI
+ * VP3 - DPI1
+ */
+ assigned-clocks = <&k3_clks 158 2>,
+ <&k3_clks 158 5>,
+ <&k3_clks 158 14>,
+ <&k3_clks 158 18>;
+ assigned-clock-parents = <&k3_clks 158 3>,
+ <&k3_clks 158 7>,
+ <&k3_clks 158 16>,
+ <&k3_clks 158 22>;
};
-&main_mcan9 {
- status = "disabled";
-};
+&dss_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
-&main_mcan10 {
- status = "disabled";
-};
+ /* HDMI */
+ port@1 {
+ reg = <1>;
-&main_mcan11 {
- status = "disabled";
-};
-
-&main_mcan12 {
- status = "disabled";
-};
-
-&main_mcan13 {
- status = "disabled";
-};
-
-&main_mcan14 {
- status = "disabled";
-};
-
-&main_mcan15 {
- status = "disabled";
-};
-
-&main_mcan17 {
- status = "disabled";
+ dpi_out0: endpoint {
+ remote-endpoint = <&tfp410_in>;
+ };
+ };
};
diff --git a/arch/arm/dts/k3-am68-sk-r5-base-board.dts b/arch/arm/dts/k3-am68-sk-r5-base-board.dts
index a64baba..695aadc 100644
--- a/arch/arm/dts/k3-am68-sk-r5-base-board.dts
+++ b/arch/arm/dts/k3-am68-sk-r5-base-board.dts
@@ -1,19 +1,18 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-#include "k3-am68-sk-som.dtsi"
+#include "k3-am68-sk-base-board.dts"
#include "k3-j721s2-ddr-evm-lp4-4266.dtsi"
#include "k3-j721s2-ddr.dtsi"
+#include "k3-am68-sk-base-board-u-boot.dtsi"
/ {
chosen {
- firmware-loader = &fs_loader0;
- stdout-path = &main_uart8;
- tick-timer = &timer1;
+ tick-timer = &mcu_timer0;
};
aliases {
@@ -21,11 +20,6 @@
remoteproc1 = &a72_0;
};
- fs_loader0: fs_loader@0 {
- compatible = "u-boot,fs-loader";
- bootph-all;
- };
-
a72_0: a72@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
@@ -42,145 +36,44 @@
bootph-pre-ram;
};
- clk_200mhz: dummy_clock_200mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- bootph-pre-ram;
- };
-
- clk_19_2mhz: dummy_clock_19_2mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <19200000>;
- bootph-pre-ram;
- };
-};
-
-&cbass_mcu_wakeup {
- sa3_secproxy: secproxy@44880000 {
- bootph-pre-ram;
- compatible = "ti,am654-secure-proxy";
- reg = <0x0 0x44880000 0x0 0x20000>,
- <0x0 0x44860000 0x0 0x20000>,
- <0x0 0x43600000 0x0 0x10000>;
- reg-names = "rt", "scfg", "target_data";
- #mbox-cells = <1>;
- };
-
- mcu_secproxy: secproxy@2a380000 {
- compatible = "ti,am654-secure-proxy";
- reg = <0x0 0x2a380000 0x0 0x80000>,
- <0x0 0x2a400000 0x0 0x80000>,
- <0x0 0x2a480000 0x0 0x80000>;
- reg-names = "rt", "scfg", "target_data";
- #mbox-cells = <1>;
- bootph-pre-ram;
- };
-
- sysctrler: sysctrler {
- compatible = "ti,am654-system-controller";
- mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>, <&sa3_secproxy 5>;
- mbox-names = "tx", "rx", "boot_notify";
- bootph-pre-ram;
- };
-
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <3>;
ti,secure-host;
mbox-names = "rx", "tx";
- mboxes= <&mcu_secproxy 21>,
- <&mcu_secproxy 23>;
+ mboxes= <&secure_proxy_mcu 21>,
+ <&secure_proxy_mcu 23>;
bootph-pre-ram;
};
};
-&main_pmx0 {
- main_uart8_pins_default: main-uart8-pins-default {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
- J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
- >;
- };
-
- main_mmc1_pins_default: main-mmc1-pins-default {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
- J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
- J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
- J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
- J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
- J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
- J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
- J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
- >;
- };
-
- main_usbss0_pins_default: main-usbss0-pins-default {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
- >;
- };
-};
-
-&wkup_pmx0 {
- mcu_uart0_pins_default: mcu-uart0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /*(C24) WKUP_GPIO0_13.MCU_UART0_RXD*/
- J721S2_WKUP_IOPAD(0x0f0, PIN_OUTPUT, 0) /*(C25) WKUP_GPIO0_12.MCU_UART0_TXD*/
- >;
- };
-
- wkup_uart0_pins_default: wkup-uart0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /*(E25) WKUP_GPIO0_6.WKUP_UART0_CTSn*/
- J721S2_WKUP_IOPAD(0x0dc, PIN_OUTPUT, 0) /*(F28) WKUP_GPIO0_7.WKUP_UART0_RTSn*/
- J721S2_WKUP_IOPAD(0x0b0, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
- J721S2_WKUP_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
- >;
- };
-
-};
-
-&sms {
- mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
- mbox-names = "tx", "rx", "notify";
- ti,host-id = <4>;
- ti,secure-host;
+&mcu_timer0 {
+ clock-frequency = <250000000>;
bootph-pre-ram;
};
-&wkup_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
+&secure_proxy_mcu {
+ bootph-pre-ram;
};
-&mcu_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_uart0_pins_default>;
+&secure_proxy_sa3 {
+ bootph-pre-ram;
};
-&main_uart8 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart8_pins_default>;
+&cbass_mcu_wakeup {
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>;
+ mbox-names = "tx", "rx", "boot_notify";
+ bootph-pre-ram;
+ };
};
-&main_sdhci0 {
- status = "disabled";
-};
-
-&main_sdhci1 {
- /delete-property/ power-domains;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- pinctrl-0 = <&main_mmc1_pins_default>;
- pinctrl-names = "default";
- clock-names = "clk_xin";
- clocks = <&clk_200mhz>;
- ti,driver-strength-ohm = <50>;
+&sms {
+ mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
+ mbox-names = "tx", "rx", "notify";
+ ti,host-id = <4>;
+ ti,secure-host;
};
&mcu_ringacc {
@@ -190,5 +83,3 @@
&mcu_udmap {
ti,sci = <&dm_tifs>;
};
-
-#include "k3-am68-sk-base-board-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-am68-sk-som.dtsi b/arch/arm/dts/k3-am68-sk-som.dtsi
index cb1c58f..6c9139f 100644
--- a/arch/arm/dts/k3-am68-sk-som.dtsi
+++ b/arch/arm/dts/k3-am68-sk-som.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
@@ -16,7 +16,6 @@
<0x08 0x80000000 0x03 0x80000000>;
};
- /* Reserving memory regions still pending */
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -24,104 +23,29 @@
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>;
- alignment = <0x1000>;
no-map;
};
};
};
-&mailbox0_cluster0 {
- status = "disabled";
+&wkup_pmx2 {
+ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
+ J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
+ >;
+ };
};
-&mailbox0_cluster1 {
- status = "disabled";
-};
+&wkup_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default>;
+ clock-frequency = <400000>;
-&mailbox0_cluster2 {
- status = "disabled";
-};
-
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
-&mailbox0_cluster4 {
- status = "disabled";
-};
-
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
-&mailbox0_cluster6 {
- status = "disabled";
-};
-
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
-&mailbox0_cluster8 {
- status = "disabled";
-};
-
-&mailbox0_cluster9 {
- status = "disabled";
-};
-
-&mailbox0_cluster10 {
- status = "disabled";
-};
-
-&mailbox0_cluster11 {
- status = "disabled";
-};
-
-&mailbox1_cluster0 {
- status = "disabled";
-};
-
-&mailbox1_cluster1 {
- status = "disabled";
-};
-
-&mailbox1_cluster2 {
- status = "disabled";
-};
-
-&mailbox1_cluster3 {
- status = "disabled";
-};
-
-&mailbox1_cluster4 {
- status = "disabled";
-};
-
-&mailbox1_cluster5 {
- status = "disabled";
-};
-
-&mailbox1_cluster6 {
- status = "disabled";
-};
-
-&mailbox1_cluster7 {
- status = "disabled";
-};
-
-&mailbox1_cluster8 {
- status = "disabled";
-};
-
-&mailbox1_cluster9 {
- status = "disabled";
-};
-
-&mailbox1_cluster10 {
- status = "disabled";
-};
-
-&mailbox1_cluster11 {
- status = "disabled";
+ eeprom@51 {
+ /* AT24C512C-MAHM-T */
+ compatible = "atmel,24c512";
+ reg = <0x51>;
+ };
};
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index f25c713..60ca6d2 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -1,200 +1,210 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-j7200-binman.dtsi"
/ {
chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
-
- aliases {
- ethernet0 = &cpsw_port1;
- i2c0 = &wkup_i2c0;
- i2c1 = &mcu_i2c0;
- i2c2 = &mcu_i2c1;
- i2c3 = &main_i2c0;
+ tick-timer = &mcu_timer0;
};
};
&cbass_main {
- bootph-pre-ram;
+ bootph-all;
};
&main_navss {
- bootph-pre-ram;
+ bootph-all;
+};
+
+&main_esm {
+ bootph-all;
};
&cbass_mcu_wakeup {
- bootph-pre-ram;
-
- timer1: timer@40400000 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x40400000 0x0 0x80>;
- ti,timer-alwon;
- clock-frequency = <250000000>;
- bootph-pre-ram;
- };
+ bootph-all;
chipid@43000014 {
- bootph-pre-ram;
+ bootph-all;
};
+};
- mcu_navss: bus@28380000 {
- bootph-pre-ram;
- #address-cells = <2>;
- #size-cells = <2>;
+&mcu_navss {
+ bootph-all;
+};
- ringacc@2b800000 {
- reg = <0x0 0x2b800000 0x0 0x400000>,
- <0x0 0x2b000000 0x0 0x400000>,
- <0x0 0x28590000 0x0 0x100>,
- <0x0 0x2a500000 0x0 0x40000>,
- <0x0 0x28440000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- bootph-pre-ram;
- };
+&mcu_ringacc {
+ bootph-all;
+};
- dma-controller@285c0000 {
- reg = <0x0 0x285c0000 0x0 0x100>,
- <0x0 0x284c0000 0x0 0x4000>,
- <0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x284a0000 0x0 0x4000>,
- <0x0 0x2aa00000 0x0 0x40000>,
- <0x0 0x28400000 0x0 0x2000>;
- reg-names = "gcfg", "rchan", "rchanrt", "tchan",
- "tchanrt", "rflow";
- bootph-pre-ram;
- };
- };
+&mcu_udmap {
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x284c0000 0x0 0x4000>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x284a0000 0x0 0x4000>,
+ <0x0 0x2aa00000 0x0 0x40000>,
+ <0x0 0x28400000 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
+ bootph-all;
};
&secure_proxy_main {
- bootph-pre-ram;
+ bootph-all;
};
&dmsc {
- bootph-pre-ram;
+ bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- bootph-pre-ram;
+ bootph-all;
};
};
&k3_pds {
- bootph-pre-ram;
+ bootph-all;
};
&k3_clks {
- bootph-pre-ram;
+ bootph-all;
};
&k3_reset {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_pmx0 {
- bootph-pre-ram;
+ bootph-all;
+};
+
+&wkup_pmx2 {
+ bootph-all;
};
&main_pmx0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_uart0 {
- bootph-pre-ram;
+ bootph-all;
+};
+
+&main_uart2 {
+ bootph-all;
};
&mcu_uart0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_sdhci0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_sdhci1 {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_i2c0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_i2c0 {
- bootph-pre-ram;
+ bootph-all;
};
-&main_i2c0_pins_default {
- bootph-pre-ram;
+&exp1 {
+ bootph-all;
};
&exp2 {
- bootph-pre-ram;
+ bootph-all;
};
&mcu_cpsw {
- reg = <0x0 0x46000000 0x0 0x200000>,
- <0x0 0x40f00200 0x0 0x8>;
- reg-names = "cpsw_nuss", "mac_efuse";
- /delete-property/ ranges;
+ bootph-all;
+};
- cpsw-phy-sel@40f04040 {
- compatible = "ti,am654-cpsw-phy-sel";
- reg= <0x0 0x40f04040 0x0 0x4>;
- reg-names = "gmii-sel";
+&mcu_uart0 {
+ bootph-all;
+};
+
+&wkup_i2c0 {
+ bootph-all;
+};
+
+&wkup_uart0 {
+ bootph-all;
+};
+
+&fss {
+ bootph-all;
+};
+
+&main_uart0_pins_default {
+ bootph-all;
+};
+
+&main_mmc1_pins_default {
+ bootph-all;
+};
+
+&main_i2c0_pins_default {
+ bootph-all;
+};
+
+&wkup_i2c0_pins_default {
+ bootph-all;
+};
+
+&wkup_uart0_pins_default {
+ bootph-all;
+};
+
+&wkup_gpio_pins_default {
+ bootph-all;
+};
+
+&wkup_gpio0 {
+ bootph-all;
+};
+
+&hbmc {
+ bootph-all;
+
+ flash@0,0 {
+ bootph-all;
};
};
-&main_usbss0_pins_default {
- bootph-pre-ram;
+&hbmc_mux {
+ bootph-all;
};
&usbss0 {
- bootph-pre-ram;
+ bootph-all;
ti,usb2-only;
};
&usb0 {
dr_mode = "peripheral";
- bootph-pre-ram;
+ bootph-all;
};
-&mcu_fss0_hpb0_pins_default {
- bootph-pre-ram;
-};
-
-&fss {
- bootph-pre-ram;
-};
-
-&hbmc {
- bootph-pre-ram;
-
- flash@0,0 {
- bootph-pre-ram;
- };
-};
-
-&hbmc_mux {
- bootph-pre-ram;
+&ospi0 {
+ bootph-all;
};
&serdes_ln_ctrl {
- u-boot,mux-autoprobe;
+ bootph-all;
};
&usb_serdes_mux {
- u-boot,mux-autoprobe;
+ bootph-all;
};
&serdes0 {
- bootph-pre-ram;
-};
-
-&main_r5fss0 {
- ti,cluster-mode = <0>;
+ bootph-all;
};
diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts
index d14f3c1..cee2b4b 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-common-proc-board.dts
@@ -8,13 +8,26 @@
#include "k3-j7200-som-p0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
-#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/phy/phy.h>
+#include "k3-serdes.h"
+
/ {
+ compatible = "ti,j7200-evm", "ti,j7200";
+ model = "Texas Instruments J7200 EVM";
+
+ aliases {
+ serial0 = &wkup_uart0;
+ serial1 = &mcu_uart0;
+ serial2 = &main_uart0;
+ serial3 = &main_uart1;
+ serial5 = &main_uart3;
+ mmc0 = &main_sdhci0;
+ mmc1 = &main_sdhci1;
+ };
+
chosen {
stdout-path = "serial2:115200n8";
- bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
evm_12v0: fixedregulator-evm12v0 {
@@ -78,47 +91,87 @@
};
&wkup_pmx0 {
- mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+ mcu_uart0_pins_default: mcu-uart0-default-pins {
pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
- J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
- J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
- J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
- J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
- J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
- J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
- J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
- J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
- J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
- J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
- J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
+ J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */
+ J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */
+ J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */
+ J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */
>;
};
- mcu_mdio_pins_default: mcu-mdio1-pins-default {
+ wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
- J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
+ J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */
+ J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */
+ >;
+ };
+};
+
+&wkup_pmx2 {
+ mcu_cpsw_pins_default: mcu-cpsw-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
+ J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
+ J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
+ J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
+ J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
+ J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
+ J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
+ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
+ J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
+ J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
+ J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
+ J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
+ >;
+ };
+
+ wkup_gpio_pins_default: wkup-gpio-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
+ >;
+ };
+
+ mcu_mdio_pins_default: mcu-mdio1-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
+ J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
>;
};
};
&main_pmx0 {
- main_i2c0_pins_default: main-i2c0-pins-default {
+ main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
- J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
- J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
+ J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */
+ J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
+ J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */
+ J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */
>;
};
- main_i2c1_pins_default: main-i2c1-pins-default {
+ main_uart1_pins_default: main-uart1-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD */
+ J721E_IOPAD(0xbc, PIN_INPUT, 0) /* (T20) UART1_TXD */
+ >;
+ };
+
+ main_uart3_pins_default: main-uart3-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x60, PIN_INPUT, 11) /* (T15) MCAN8_TX.UART3_CTSn */
+ J721E_IOPAD(0x30, PIN_INPUT, 11) /* (Y18) MCAN2_TX.UART3_RXD */
+ >;
+ };
+
+ main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
>;
};
- main_mmc1_pins_default: main-mmc1-pins-default {
+ main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
@@ -131,27 +184,48 @@
>;
};
- main_usbss0_pins_default: main-usbss0-pins-default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
- >;
- };
-
- vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
+ vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
>;
};
};
+&main_pmx1 {
+ main_usbss0_pins_default: main-usbss0-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
+ >;
+ };
+};
+
&wkup_uart0 {
/* Wakeup UART is used by System firmware */
status = "reserved";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+};
+
+&mcu_uart0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_uart0_pins_default>;
+ clock-frequency = <96000000>;
};
&main_uart0 {
+ status = "okay";
/* Shared with ATF on this platform */
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+};
+
+&main_uart1 {
+ status = "okay";
+ /* Default pinmux */
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
};
&main_uart2 {
@@ -160,59 +234,25 @@
};
&main_uart3 {
- /* UART not brought out */
- status = "disabled";
+ /* Shared with MCAN Interface */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart3_pins_default>;
};
-&main_uart4 {
- /* UART not brought out */
- status = "disabled";
+&main_gpio0 {
+ status = "okay";
};
-&main_uart5 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_uart6 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_uart7 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_uart8 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_uart9 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_gpio2 {
- status = "disabled";
-};
-
-&main_gpio4 {
- status = "disabled";
-};
-
-&main_gpio6 {
- status = "disabled";
-};
-
-&wkup_gpio1 {
- status = "disabled";
+&wkup_gpio0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_gpio_pins_default>;
};
&mcu_cpsw {
pinctrl-names = "default";
- pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+ pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
};
&davinci_mdio {
@@ -229,6 +269,7 @@
};
&main_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
@@ -256,6 +297,7 @@
* The i2c1 of the CPB (as it is labeled) is not connected to j7200.
*/
&main_i2c1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
@@ -273,6 +315,7 @@
&main_sdhci0 {
/* eMMC */
+ status = "okay";
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
@@ -280,6 +323,7 @@
&main_sdhci1 {
/* SD card */
+ status = "okay";
pinctrl-0 = <&main_mmc1_pins_default>;
pinctrl-names = "default";
vmmc-supply = <&vdd_mmc1>;
diff --git a/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi b/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi
index 9ec8dff..f068308 100644
--- a/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi
+++ b/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.6.0
* This file was generated on 06/01/2021
*/
diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi
index e8a41d0..cdb1d6b 100644
--- a/arch/arm/dts/k3-j7200-main.dtsi
+++ b/arch/arm/dts/k3-j7200-main.dtsi
@@ -32,13 +32,20 @@
#size-cells = <1>;
ranges = <0x00 0x00 0x00100000 0x1c000>;
- serdes_ln_ctrl: serdes-ln-ctrl@4080 {
+ serdes_ln_ctrl: mux-controller@4080 {
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
<0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
};
+ cpsw0_phy_gmii_sel: phy@4044 {
+ compatible = "ti,j7200-cpsw5g-phy-gmii-sel";
+ ti,qsgmii-main-ports = <1>;
+ reg = <0x4044 0x10>;
+ #phy-cells = <1>;
+ };
+
usb_serdes_mux: mux-controller@4000 {
compatible = "mmio-mux";
#mux-control-cells = <1>;
@@ -54,7 +61,10 @@
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01900000 0x00 0x100000>; /* GICR */
+ <0x00 0x01900000 0x00 0x100000>, /* GICR */
+ <0x00 0x6f000000 0x00 0x2000>, /* GICC */
+ <0x00 0x6f010000 0x00 0x1000>, /* GICH */
+ <0x00 0x6f020000 0x00 0x2000>; /* GICV */
/* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
@@ -139,6 +149,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster1: mailbox@31f81000 {
@@ -148,6 +159,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster2: mailbox@31f82000 {
@@ -157,6 +169,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster3: mailbox@31f83000 {
@@ -166,6 +179,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster4: mailbox@31f84000 {
@@ -175,6 +189,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster5: mailbox@31f85000 {
@@ -184,6 +199,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster6: mailbox@31f86000 {
@@ -193,6 +209,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster7: mailbox@31f87000 {
@@ -202,6 +219,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster8: mailbox@31f88000 {
@@ -211,6 +229,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster9: mailbox@31f89000 {
@@ -220,6 +239,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster10: mailbox@31f8a000 {
@@ -229,6 +249,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster11: mailbox@31f8b000 {
@@ -238,15 +259,17 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
main_ringacc: ringacc@3c000000 {
compatible = "ti,am654-navss-ringacc";
- reg = <0x00 0x3c000000 0x00 0x400000>,
- <0x00 0x38000000 0x00 0x400000>,
- <0x00 0x31120000 0x00 0x100>,
- <0x00 0x33000000 0x00 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ reg = <0x00 0x3c000000 0x00 0x400000>,
+ <0x00 0x38000000 0x00 0x400000>,
+ <0x00 0x31120000 0x00 0x100>,
+ <0x00 0x33000000 0x00 0x40000>,
+ <0x00 0x31080000 0x00 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
ti,num-rings = <1024>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
@@ -256,9 +279,9 @@
main_udmap: dma-controller@31150000 {
compatible = "ti,j721e-navss-main-udmap";
- reg = <0x00 0x31150000 0x00 0x100>,
- <0x00 0x34000000 0x00 0x100000>,
- <0x00 0x35000000 0x00 0x100000>;
+ reg = <0x00 0x31150000 0x00 0x100>,
+ <0x00 0x34000000 0x00 0x100000>,
+ <0x00 0x35000000 0x00 0x100000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
@@ -289,10 +312,118 @@
};
};
+ cpsw0: ethernet@c000000 {
+ compatible = "ti,j7200-cpswxg-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x00 0xc000000 0x00 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
+ clocks = <&k3_clks 19 33>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
+
+ dmas = <&main_udmap 0xca00>,
+ <&main_udmap 0xca01>,
+ <&main_udmap 0xca02>,
+ <&main_udmap 0xca03>,
+ <&main_udmap 0xca04>,
+ <&main_udmap 0xca05>,
+ <&main_udmap 0xca06>,
+ <&main_udmap 0xca07>,
+ <&main_udmap 0x4a00>;
+ dma-names = "tx0", "tx1", "tx2", "tx3",
+ "tx4", "tx5", "tx6", "tx7",
+ "rx";
+
+ status = "disabled";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpsw0_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ status = "disabled";
+ };
+
+ cpsw0_port2: port@2 {
+ reg = <2>;
+ ti,mac-only;
+ label = "port2";
+ status = "disabled";
+ };
+
+ cpsw0_port3: port@3 {
+ reg = <3>;
+ ti,mac-only;
+ label = "port3";
+ status = "disabled";
+ };
+
+ cpsw0_port4: port@4 {
+ reg = <4>;
+ ti,mac-only;
+ label = "port4";
+ status = "disabled";
+ };
+ };
+
+ cpsw5g_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x00 0xf00 0x00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 19 33>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ status = "disabled";
+ };
+
+ cpts@3d000 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x00 0x3d000 0x00 0x400>;
+ clocks = <&k3_clks 19 16>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+
+ /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
+ main_timerio_input: pinctrl@104200 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x104200 0x0 0x50>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x000001ff>;
+ };
+
+ /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
+ main_timerio_output: pinctrl@104280 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x104280 0x0 0x20>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000001f>;
+ };
+
main_pmx0: pinctrl@11c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
- reg = <0x00 0x11c000 0x00 0x2b4>;
+ reg = <0x00 0x11c000 0x00 0x10c>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ main_pmx1: pinctrl@11c11c {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x00 0x11c11c 0x00 0xc>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
@@ -307,6 +438,7 @@
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 146 2>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart1: serial@2810000 {
@@ -318,6 +450,7 @@
power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 278 2>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart2: serial@2820000 {
@@ -329,6 +462,7 @@
power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 279 2>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart3: serial@2830000 {
@@ -340,6 +474,7 @@
power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 280 2>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart4: serial@2840000 {
@@ -351,6 +486,7 @@
power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 281 2>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart5: serial@2850000 {
@@ -362,6 +498,7 @@
power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 282 2>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart6: serial@2860000 {
@@ -373,6 +510,7 @@
power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 283 2>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart7: serial@2870000 {
@@ -384,6 +522,7 @@
power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 284 2>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart8: serial@2880000 {
@@ -395,6 +534,7 @@
power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 285 2>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart9: serial@2890000 {
@@ -406,6 +546,7 @@
power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 286 2>;
clock-names = "fclk";
+ status = "disabled";
};
main_i2c0: i2c@2000000 {
@@ -417,6 +558,7 @@
clock-names = "fck";
clocks = <&k3_clks 187 1>;
power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
+ status = "disabled";
};
main_i2c1: i2c@2010000 {
@@ -428,6 +570,7 @@
clock-names = "fck";
clocks = <&k3_clks 188 1>;
power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c2: i2c@2020000 {
@@ -439,6 +582,7 @@
clock-names = "fck";
clocks = <&k3_clks 189 1>;
power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c3: i2c@2030000 {
@@ -450,6 +594,7 @@
clock-names = "fck";
clocks = <&k3_clks 190 1>;
power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c4: i2c@2040000 {
@@ -461,6 +606,7 @@
clock-names = "fck";
clocks = <&k3_clks 191 1>;
power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c5: i2c@2050000 {
@@ -472,6 +618,7 @@
clock-names = "fck";
clocks = <&k3_clks 192 1>;
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c6: i2c@2060000 {
@@ -483,6 +630,7 @@
clock-names = "fck";
clocks = <&k3_clks 193 1>;
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_sdhci0: mmc@4f80000 {
@@ -507,6 +655,7 @@
mmc-hs200-1_8v;
mmc-hs400-1_8v;
dma-coherent;
+ status = "disabled";
};
main_sdhci1: mmc@4fb0000 {
@@ -530,6 +679,7 @@
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
dma-coherent;
+ status = "disabled";
};
serdes_wiz0: wiz@5060000 {
@@ -606,10 +756,10 @@
clock-names = "fck";
#address-cells = <3>;
#size-cells = <2>;
- bus-range = <0x0 0xf>;
+ bus-range = <0x0 0xff>;
cdns,no-bar-match-nbits = <64>;
- vendor-id = /bits/ 16 <0x104c>;
- device-id = /bits/ 16 <0xb00f>;
+ vendor-id = <0x104c>;
+ device-id = <0xb00f>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
dma-coherent;
ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
@@ -633,6 +783,7 @@
clocks = <&k3_clks 240 6>;
clock-names = "fck";
max-functions = /bits/ 8 <6>;
+ max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
dma-coherent;
};
@@ -682,6 +833,7 @@
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 105 0>;
clock-names = "gpio";
+ status = "disabled";
};
main_gpio2: gpio@610000 {
@@ -699,6 +851,7 @@
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 107 0>;
clock-names = "gpio";
+ status = "disabled";
};
main_gpio4: gpio@620000 {
@@ -716,6 +869,7 @@
power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 109 0>;
clock-names = "gpio";
+ status = "disabled";
};
main_gpio6: gpio@630000 {
@@ -733,6 +887,353 @@
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 111 0>;
clock-names = "gpio";
+ status = "disabled";
+ };
+
+ main_spi0: spi@2100000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02100000 0x00 0x400>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 266 1>;
+ status = "disabled";
+ };
+
+ main_spi1: spi@2110000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02110000 0x00 0x400>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 267 1>;
+ status = "disabled";
+ };
+
+ main_spi2: spi@2120000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02120000 0x00 0x400>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 268 1>;
+ status = "disabled";
+ };
+
+ main_spi3: spi@2130000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02130000 0x00 0x400>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 269 1>;
+ status = "disabled";
+ };
+
+ main_spi4: spi@2140000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02140000 0x00 0x400>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 270 1>;
+ status = "disabled";
+ };
+
+ main_spi5: spi@2150000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02150000 0x00 0x400>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 271 1>;
+ status = "disabled";
+ };
+
+ main_spi6: spi@2160000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02160000 0x00 0x400>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 272 1>;
+ status = "disabled";
+ };
+
+ main_spi7: spi@2170000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02170000 0x00 0x400>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 273 1>;
+ status = "disabled";
+ };
+
+ watchdog0: watchdog@2200000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x0 0x2200000 0x0 0x100>;
+ clocks = <&k3_clks 252 1>;
+ power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 252 1>;
+ assigned-clock-parents = <&k3_clks 252 5>;
+ };
+
+ watchdog1: watchdog@2210000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x0 0x2210000 0x0 0x100>;
+ clocks = <&k3_clks 253 1>;
+ power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 253 1>;
+ assigned-clock-parents = <&k3_clks 253 5>;
+ };
+
+ main_timer0: timer@2400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2400000 0x00 0x400>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 49 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 49 1>;
+ assigned-clock-parents = <&k3_clks 49 2>;
+ power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer1: timer@2410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2410000 0x00 0x400>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 50 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>;
+ assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>;
+ power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer2: timer@2420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2420000 0x00 0x400>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 51 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 51 1>;
+ assigned-clock-parents = <&k3_clks 51 2>;
+ power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer3: timer@2430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2430000 0x00 0x400>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 52 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>;
+ assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>;
+ power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer4: timer@2440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2440000 0x00 0x400>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 53 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 53 1>;
+ assigned-clock-parents = <&k3_clks 53 2>;
+ power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer5: timer@2450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2450000 0x00 0x400>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 54 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>;
+ assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>;
+ power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer6: timer@2460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2460000 0x00 0x400>;
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 55 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 55 1>;
+ assigned-clock-parents = <&k3_clks 55 2>;
+ power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer7: timer@2470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2470000 0x00 0x400>;
+ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 57 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>;
+ assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>;
+ power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer8: timer@2480000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2480000 0x00 0x400>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 58 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 58 1>;
+ assigned-clock-parents = <&k3_clks 58 2>;
+ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer9: timer@2490000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2490000 0x00 0x400>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 59 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>;
+ assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>;
+ power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer10: timer@24a0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24a0000 0x00 0x400>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 60 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 60 1>;
+ assigned-clock-parents = <&k3_clks 60 2>;
+ power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer11: timer@24b0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24b0000 0x00 0x400>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 62 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>;
+ assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>;
+ power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer12: timer@24c0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24c0000 0x00 0x400>;
+ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 63 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 63 1>;
+ assigned-clock-parents = <&k3_clks 63 2>;
+ power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer13: timer@24d0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24d0000 0x00 0x400>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 64 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>;
+ assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>;
+ power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer14: timer@24e0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24e0000 0x00 0x400>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 65 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 65 1>;
+ assigned-clock-parents = <&k3_clks 65 2>;
+ power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer15: timer@24f0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24f0000 0x00 0x400>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 66 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>;
+ assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>;
+ power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer16: timer@2500000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2500000 0x00 0x400>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 67 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 67 1>;
+ assigned-clock-parents = <&k3_clks 67 2>;
+ power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer17: timer@2510000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2510000 0x00 0x400>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 68 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>;
+ assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>;
+ power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer18: timer@2520000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2520000 0x00 0x400>;
+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 69 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 69 1>;
+ assigned-clock-parents = <&k3_clks 69 2>;
+ power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer19: timer@2530000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2530000 0x00 0x400>;
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 70 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>;
+ assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>;
+ power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
};
main_r5fss0: r5fss@5c00000 {
@@ -774,4 +1275,10 @@
ti,loczrama = <1>;
};
};
+
+ main_esm: esm@700000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x0 0x700000 0x0 0x1000>;
+ ti,esm-pins = <656>, <657>;
+ };
};
diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
index 1044ec6..6ffaf85 100644
--- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
@@ -12,8 +12,8 @@
mbox-names = "rx", "tx";
- mboxes= <&secure_proxy_main 11>,
- <&secure_proxy_main 13>;
+ mboxes = <&secure_proxy_main 11>,
+ <&secure_proxy_main 13>;
reg-names = "debug_messages";
reg = <0x00 0x44083000 0x00 0x1000>;
@@ -34,6 +34,136 @@
};
};
+ mcu_timer0: timer@40400000 {
+ status = "reserved";
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40400000 0x00 0x400>;
+ interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 35 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 35 1>;
+ assigned-clock-parents = <&k3_clks 35 2>;
+ power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ mcu_timer1: timer@40410000 {
+ status = "reserved";
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40410000 0x00 0x400>;
+ interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 71 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
+ assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>;
+ power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ mcu_timer2: timer@40420000 {
+ status = "reserved";
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40420000 0x00 0x400>;
+ interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 72 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 72 1>;
+ assigned-clock-parents = <&k3_clks 72 2>;
+ power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ mcu_timer3: timer@40430000 {
+ status = "reserved";
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40430000 0x00 0x400>;
+ interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 73 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>;
+ assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>;
+ power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ mcu_timer4: timer@40440000 {
+ status = "reserved";
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40440000 0x00 0x400>;
+ interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 74 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 74 1>;
+ assigned-clock-parents = <&k3_clks 74 2>;
+ power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ mcu_timer5: timer@40450000 {
+ status = "reserved";
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40450000 0x00 0x400>;
+ interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 75 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>;
+ assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>;
+ power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ mcu_timer6: timer@40460000 {
+ status = "reserved";
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40460000 0x00 0x400>;
+ interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 76 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 76 1>;
+ assigned-clock-parents = <&k3_clks 76 2>;
+ power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ mcu_timer7: timer@40470000 {
+ status = "reserved";
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40470000 0x00 0x400>;
+ interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 77 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>;
+ assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>;
+ power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ mcu_timer8: timer@40480000 {
+ status = "reserved";
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40480000 0x00 0x400>;
+ interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 78 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 78 1>;
+ assigned-clock-parents = <&k3_clks 78 2>;
+ power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ mcu_timer9: timer@40490000 {
+ status = "reserved";
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40490000 0x00 0x400>;
+ interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 79 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>;
+ assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>;
+ power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
mcu_conf: syscon@40f00000 {
compatible = "syscon", "simple-mfd";
reg = <0x00 0x40f00000 0x00 0x20000>;
@@ -53,10 +183,57 @@
reg = <0x00 0x43000014 0x00 0x4>;
};
+ /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
+ mcu_timerio_input: pinctrl@40f04200 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x40f04200 0x0 0x28>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000F>;
+ status = "reserved";
+ };
+
+ /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
+ mcu_timerio_output: pinctrl@40f04280 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x40f04280 0x0 0x28>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000F>;
+ status = "reserved";
+ };
+
wkup_pmx0: pinctrl@4301c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
- reg = <0x00 0x4301c000 0x00 0x178>;
+ reg = <0x00 0x4301c000 0x00 0x34>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ wkup_pmx1: pinctrl@4301c038 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x00 0x4301c038 0x00 0x8>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ wkup_pmx2: pinctrl@4301c068 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x00 0x4301c068 0x00 0xec>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ wkup_pmx3: pinctrl@4301c174 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x00 0x4301c174 0x00 0x20>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
@@ -79,6 +256,7 @@
power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 287 2>;
clock-names = "fclk";
+ status = "disabled";
};
mcu_uart0: serial@40a00000 {
@@ -90,6 +268,7 @@
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 149 2>;
clock-names = "fclk";
+ status = "disabled";
};
wkup_gpio_intr: interrupt-controller@42200000 {
@@ -118,6 +297,7 @@
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 113 0>;
clock-names = "gpio";
+ status = "disabled";
};
wkup_gpio1: gpio@42100000 {
@@ -134,6 +314,7 @@
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>;
clock-names = "gpio";
+ status = "disabled";
};
mcu_navss: bus@28380000 {
@@ -147,11 +328,13 @@
mcu_ringacc: ringacc@2b800000 {
compatible = "ti,am654-navss-ringacc";
- reg = <0x00 0x2b800000 0x00 0x400000>,
- <0x00 0x2b000000 0x00 0x400000>,
- <0x00 0x28590000 0x00 0x100>,
- <0x00 0x2a500000 0x00 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ reg = <0x00 0x2b800000 0x00 0x400000>,
+ <0x00 0x2b000000 0x00 0x400000>,
+ <0x00 0x28590000 0x00 0x100>,
+ <0x00 0x2a500000 0x00 0x40000>,
+ <0x00 0x28440000 0x00 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg",
+ "proxy_target", "cfg";
ti,num-rings = <286>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
@@ -161,9 +344,9 @@
mcu_udmap: dma-controller@285c0000 {
compatible = "ti,j721e-navss-mcu-udmap";
- reg = <0x00 0x285c0000 0x00 0x100>,
- <0x00 0x2a800000 0x00 0x40000>,
- <0x00 0x2aa00000 0x00 0x40000>;
+ reg = <0x00 0x285c0000 0x00 0x100>,
+ <0x00 0x2a800000 0x00 0x40000>,
+ <0x00 0x2aa00000 0x00 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
@@ -180,6 +363,21 @@
};
};
+ secure_proxy_mcu: mailbox@2a480000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x0 0x2a480000 0x0 0x80000>,
+ <0x0 0x2a380000 0x0 0x80000>,
+ <0x0 0x2a400000 0x0 0x80000>;
+ /*
+ * Marked Disabled:
+ * Node is incomplete as it is meant for bootloaders and
+ * firmware on non-MPU processors
+ */
+ status = "disabled";
+ };
+
mcu_cpsw: ethernet@46000000 {
compatible = "ti,j721e-cpsw-nuss";
#address-cells = <2>;
@@ -249,6 +447,7 @@
clock-names = "fck";
clocks = <&k3_clks 194 1>;
power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_i2c1: i2c@40b10000 {
@@ -260,6 +459,7 @@
clock-names = "fck";
clocks = <&k3_clks 195 1>;
power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
wkup_i2c0: i2c@42120000 {
@@ -271,6 +471,40 @@
clock-names = "fck";
clocks = <&k3_clks 197 1>;
power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
+ status = "disabled";
+ };
+
+ mcu_spi0: spi@40300000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040300000 0x00 0x400>;
+ interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 274 0>;
+ status = "disabled";
+ };
+
+ mcu_spi1: spi@40310000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040310000 0x00 0x400>;
+ interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 275 0>;
+ status = "disabled";
+ };
+
+ mcu_spi2: spi@40320000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040320000 0x00 0x400>;
+ interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 276 0>;
+ status = "disabled";
};
fss: syscon@47000000 {
@@ -314,6 +548,7 @@
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
};
@@ -325,7 +560,7 @@
clocks = <&k3_clks 0 1>;
assigned-clocks = <&k3_clks 0 3>;
assigned-clock-rates = <60000000>;
- clock-names = "adc_tsc_fck";
+ clock-names = "fck";
dmas = <&main_udmap 0x7400>,
<&main_udmap 0x7401>;
dma-names = "fifo0", "fifo1";
@@ -375,4 +610,31 @@
ti,loczrama = <1>;
};
};
+
+ mcu_crypto: crypto@40900000 {
+ compatible = "ti,j721e-sa2ul";
+ reg = <0x00 0x40900000 0x00 0x1200>;
+ power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
+ dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
+ <&mcu_udmap 0x7503>;
+ dma-names = "tx", "rx1", "rx2";
+
+ rng: rng@40910000 {
+ compatible = "inside-secure,safexcel-eip76";
+ reg = <0x00 0x40910000 0x00 0x7d>;
+ interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled"; /* Used by OP-TEE */
+ };
+ };
+
+ wkup_vtm0: temperature-sensor@42040000 {
+ compatible = "ti,j7200-vtm";
+ reg = <0x00 0x42040000 0x00 0x350>,
+ <0x00 0x42050000 0x00 0x350>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+ #thermal-sensor-cells = <1>;
+ };
};
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index e62f921..f0a7360 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -1,13 +1,14 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-#include "k3-j7200-som-p0.dtsi"
+#include "k3-j7200-common-proc-board.dts"
#include "k3-j7200-ddr-evm-lp4-2666.dtsi"
#include "k3-j721e-ddr.dtsi"
+#include "k3-j7200-common-proc-board-u-boot.dtsi"
/ {
aliases {
@@ -15,17 +16,6 @@
remoteproc1 = &a72_0;
};
- chosen {
- stdout-path = &main_uart0;
- tick-timer = &timer1;
- firmware-loader = &fs_loader0;
- };
-
- fs_loader0: fs_loader@0 {
- bootph-all;
- compatible = "u-boot,fs-loader";
- };
-
a72_0: a72@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
@@ -42,17 +32,13 @@
bootph-pre-ram;
};
- clk_200mhz: dummy_clock_200mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- bootph-pre-ram;
- };
-
- clk_19_2mhz: dummy_clock_19_2mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <19200000>;
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <3>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes = <&secure_proxy_mcu 21>,
+ <&secure_proxy_mcu 23>;
bootph-pre-ram;
};
};
@@ -61,275 +47,38 @@
power-domains = <&k3_pds 8 TI_SCI_PD_SHARED>,
<&k3_pds 90 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 8 5>, <&k3_clks 30 9>;
+ bootph-pre-ram;
+};
+
+&mcu_timer0 {
+ clock-frequency = <25000000>;
+ bootph-pre-ram;
+};
+
+&secure_proxy_mcu {
+ bootph-pre-ram;
+ status = "okay";
};
&cbass_mcu_wakeup {
- mcu_secproxy: secproxy@2a380000 {
- bootph-pre-ram;
- compatible = "ti,am654-secure-proxy";
- reg = <0x0 0x2a380000 0x0 0x80000>,
- <0x0 0x2a400000 0x0 0x80000>,
- <0x0 0x2a480000 0x0 0x80000>;
- reg-names = "rt", "scfg", "target_data";
- #mbox-cells = <1>;
- };
-
sysctrler: sysctrler {
- bootph-pre-ram;
compatible = "ti,am654-system-controller";
- mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
+ mboxes= <&secure_proxy_mcu 4>,
+ <&secure_proxy_mcu 5>;
mbox-names = "tx", "rx";
- };
-
- dm_tifs: dm-tifs {
- compatible = "ti,j721e-dm-sci";
- ti,host-id = <3>;
- ti,secure-host;
- mbox-names = "rx", "tx";
- mboxes= <&mcu_secproxy 21>,
- <&mcu_secproxy 23>;
bootph-pre-ram;
};
-
- wkup_vtm0: vtm@42040000 {
- compatible = "ti,am654-vtm", "ti,j721e-avs";
- reg = <0x0 0x42040000 0x0 0x330>;
- power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
- #thermal-sensor-cells = <1>;
- };
};
&dmsc {
- mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
+ mboxes = <&secure_proxy_mcu 8>,
+ <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
-};
-
-&wkup_pmx0 {
bootph-pre-ram;
- wkup_uart0_pins_default: wkup_uart0_pins_default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */
- J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */
- >;
- };
-
- mcu_uart0_pins_default: mcu_uart0_pins_default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) WKUP_GPIO0_13.MCU_UART0_RXD */
- J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) WKUP_GPIO0_12.MCU_UART0_TXD */
- J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) WKUP_GPIO0_14.MCU_UART0_CTSn */
- J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) WKUP_GPIO0_15.MCU_UART0_RTSn */
- >;
- };
-
- wkup_i2c0_pins_default: wkup-i2c0-pins-default {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x100, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
- J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
- >;
- };
-
- mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
- J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
- J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
- J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
- J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
- J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
- J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
- J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
- J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
- J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
- J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
- J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
- J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
- J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
- >;
- };
-
- wkup_gpio_pins_default: wkup-gpio-pins-default {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
- >;
- };
-};
-
-&main_pmx0 {
- bootph-pre-ram;
-
- main_uart0_pins_default: main_uart0_pins_default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */
- J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
- J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */
- J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */
- >;
- };
-
- main_i2c0_pins_default: main-i2c0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
- J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
- >;
- };
-
- main_mmc1_pins_default: main_mmc1_pins_default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
- J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
- J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
- J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
- J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
- J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
- J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
- J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
- >;
- };
-
- main_usbss0_pins_default: main_usbss0_pins_default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
- >;
- };
-};
-
-&wkup_uart0 {
- bootph-pre-ram;
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
- status = "okay";
-};
-
-&mcu_uart0 {
- /delete-property/ power-domains;
- /delete-property/ clocks;
- /delete-property/ clock-names;
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_uart0_pins_default>;
- status = "okay";
- clock-frequency = <96000000>;
-};
-
-&main_uart0 {
- status = "okay";
- power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
- status = "okay";
-};
-
-&main_sdhci0 {
- /delete-property/ power-domains;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- pinctrl-0 = <&main_mmc1_pins_default>;
- pinctrl-names = "default";
- clock-names = "clk_xin";
- clocks = <&clk_200mhz>;
- ti,driver-strength-ohm = <50>;
- non-removable;
- bus-width = <8>;
-};
-
-&main_sdhci1 {
- /delete-property/ power-domains;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- clock-names = "clk_xin";
- clocks = <&clk_200mhz>;
- ti,driver-strength-ohm = <50>;
-};
-
-&wkup_i2c0 {
- bootph-pre-ram;
- lp876441: lp876441@4c {
- compatible = "ti,lp876441";
- reg = <0x4c>;
- bootph-pre-ram;
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- regulators: regulators {
- bootph-pre-ram;
- buck1_reg: buck1 {
- /*VDD_CPU_AVS_REG*/
- regulator-name = "buck1";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1250000>;
- regulator-always-on;
- regulator-boot-on;
- bootph-pre-ram;
- };
- };
- };
-
};
&wkup_vtm0 {
- vdd-supply-2 = <&buck1_reg>;
bootph-pre-ram;
};
-
-&main_i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- exp1: gpio@20 {
- compatible = "ti,tca6416";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- exp2: gpio@22 {
- compatible = "ti,tca6424";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-};
-
-&usbss0 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_usbss0_pins_default>;
- ti,vbus-divider;
- ti,usb2-only;
-};
-
-&usb0 {
- dr_mode = "otg";
- maximum-speed = "high-speed";
-};
-
-&hbmc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
- reg = <0x0 0x47040000 0x0 0x100>,
- <0x0 0x50000000 0x0 0x8000000>;
- ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */
- <0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */
-
- flash@0,0 {
- compatible = "cypress,hyperflash", "cfi-flash";
- reg = <0x0 0x0 0x4000000>;
- };
-};
-
-&mcu_ringacc {
- ti,sci = <&dm_tifs>;
-};
-
-&mcu_udmap {
- ti,sci = <&dm_tifs>;
-};
-#include "k3-j7200-common-proc-board-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-j7200-som-p0.dtsi b/arch/arm/dts/k3-j7200-som-p0.dtsi
index 3472444..5a300d4 100644
--- a/arch/arm/dts/k3-j7200-som-p0.dtsi
+++ b/arch/arm/dts/k3-j7200-som-p0.dtsi
@@ -83,7 +83,7 @@
};
&wkup_pmx0 {
- mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
+ mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
@@ -101,7 +101,7 @@
>;
};
- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
@@ -118,8 +118,17 @@
};
};
+&wkup_pmx2 {
+ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
+ J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
+ >;
+ };
+};
+
&main_pmx0 {
- main_i2c0_pins_default: main-i2c0-pins-default {
+ main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
@@ -140,10 +149,42 @@
flash@0,0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0x00 0x00 0x4000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "hbmc.tiboot3";
+ reg = <0x0 0x100000>;
+ };
+
+ partition@100000 {
+ label = "hbmc.tispl";
+ reg = <0x100000 0x200000>;
+ };
+
+ partition@300000 {
+ label = "hbmc.u-boot";
+ reg = <0x300000 0x400000>;
+ };
+
+ partition@700000 {
+ label = "hbmc.env";
+ reg = <0x700000 0x40000>;
+ };
+
+ partition@800000 {
+ label = "hbmc.rootfs";
+ reg = <0x800000 0x3800000>;
+ };
+ };
};
};
&mailbox0_cluster0 {
+ status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
@@ -158,6 +199,7 @@
};
&mailbox0_cluster1 {
+ status = "okay";
interrupts = <432>;
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
@@ -171,66 +213,26 @@
};
};
-&mailbox0_cluster2 {
- status = "disabled";
-};
-
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
-&mailbox0_cluster4 {
- status = "disabled";
-};
-
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
-&mailbox0_cluster6 {
- status = "disabled";
-};
-
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
-&mailbox0_cluster8 {
- status = "disabled";
-};
-
-&mailbox0_cluster9 {
- status = "disabled";
-};
-
-&mailbox0_cluster10 {
- status = "disabled";
-};
-
-&mailbox0_cluster11 {
- status = "disabled";
-};
-
&mcu_r5fss0_core0 {
- mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
- mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
@@ -252,11 +254,24 @@
};
};
+&wkup_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ };
+};
+
&ospi0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
- flash@0{
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
@@ -267,7 +282,46 @@
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
- #address-cells = <1>;
- #size-cells = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ospi.tiboot3";
+ reg = <0x0 0x100000>;
+ };
+
+ partition@100000 {
+ label = "ospi.tispl";
+ reg = <0x100000 0x200000>;
+ };
+
+ partition@300000 {
+ label = "ospi.u-boot";
+ reg = <0x300000 0x400000>;
+ };
+
+ partition@700000 {
+ label = "ospi.env";
+ reg = <0x700000 0x40000>;
+ };
+
+ partition@740000 {
+ label = "ospi.env.backup";
+ reg = <0x740000 0x40000>;
+ };
+
+ partition@800000 {
+ label = "ospi.rootfs";
+ reg = <0x800000 0x37c0000>;
+ };
+
+ partition@3fc0000 {
+ label = "ospi.phypattern";
+ reg = <0x3fc0000 0x40000>;
+ };
+ };
};
};
diff --git a/arch/arm/dts/k3-j7200-thermal.dtsi b/arch/arm/dts/k3-j7200-thermal.dtsi
new file mode 100644
index 0000000..e7e3a64
--- /dev/null
+++ b/arch/arm/dts/k3-j7200-thermal.dtsi
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+ mcu_thermal: mcu-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 0>;
+
+ trips {
+ wkup_crit: wkup-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ mpu_thermal: mpu-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 1>;
+
+ trips {
+ mpu_crit: mpu-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main_thermal: main-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 2>;
+
+ trips {
+ c7x_crit: c7x-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-j7200.dtsi b/arch/arm/dts/k3-j7200.dtsi
index b7005b8..ef73e6d 100644
--- a/arch/arm/dts/k3-j7200.dtsi
+++ b/arch/arm/dts/k3-j7200.dtsi
@@ -7,9 +7,10 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
+#include "k3-pinctrl.h"
+
/ {
model = "Texas Instruments K3 J7200 SoC";
compatible = "ti,j7200";
@@ -17,21 +18,6 @@
#address-cells = <2>;
#size-cells = <2>;
- aliases {
- serial0 = &wkup_uart0;
- serial1 = &mcu_uart0;
- serial2 = &main_uart0;
- serial3 = &main_uart1;
- serial4 = &main_uart2;
- serial5 = &main_uart3;
- serial6 = &main_uart4;
- serial7 = &main_uart5;
- serial8 = &main_uart6;
- serial9 = &main_uart7;
- serial10 = &main_uart8;
- serial11 = &main_uart9;
- };
-
chosen { };
cpus {
@@ -60,7 +46,7 @@
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
- d-cache-sets = <128>;
+ d-cache-sets = <256>;
next-level-cache = <&L2_0>;
};
@@ -74,7 +60,7 @@
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
- d-cache-sets = <128>;
+ d-cache-sets = <256>;
next-level-cache = <&L2_0>;
};
};
@@ -82,15 +68,17 @@
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
- cache-sets = <2048>;
+ cache-sets = <1024>;
next-level-cache = <&msmc_l3>;
};
msmc_l3: l3-cache0 {
compatible = "cache";
cache-level = <3>;
+ cache-unified;
};
firmware {
@@ -124,9 +112,11 @@
#size-cells = <2>;
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
+ <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
+ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
@@ -165,6 +155,8 @@
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */
};
};
+
+ #include "k3-j7200-thermal.dtsi"
};
/* Now include the peripherals for each bus segments */
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 540c847..b77f8d9 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -1,274 +1,181 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
-#include <dt-bindings/net/ti-dp83867.h>
#include "k3-j721e-binman.dtsi"
-/ {
- chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
-
- aliases {
- ethernet0 = &cpsw_port1;
- spi0 = &ospi0;
- spi1 = &ospi1;
- remoteproc0 = &mcu_r5fss0_core0;
- remoteproc1 = &mcu_r5fss0_core1;
- remoteproc2 = &main_r5fss0_core0;
- remoteproc3 = &main_r5fss0_core1;
- remoteproc4 = &main_r5fss1_core0;
- remoteproc5 = &main_r5fss1_core1;
- remoteproc6 = &c66_0;
- remoteproc7 = &c66_1;
- remoteproc8 = &c71_0;
- i2c0 = &wkup_i2c0;
- i2c1 = &mcu_i2c0;
- i2c2 = &mcu_i2c1;
- i2c3 = &main_i2c0;
- };
+&cbass_main {
+ bootph-all;
};
-&cbass_main{
- bootph-pre-ram;
-
- main_navss: bus@30000000 {
- bootph-pre-ram;
- };
+&main_navss {
+ bootph-all;
};
&cbass_mcu_wakeup {
- bootph-pre-ram;
-
- timer1: timer@40400000 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x40400000 0x0 0x80>;
- ti,timer-alwon;
- clock-frequency = <250000000>;
- bootph-pre-ram;
- };
-
- mcu_navss: bus@28380000 {
- bootph-pre-ram;
-
- ringacc@2b800000 {
- reg = <0x0 0x2b800000 0x0 0x400000>,
- <0x0 0x2b000000 0x0 0x400000>,
- <0x0 0x28590000 0x0 0x100>,
- <0x0 0x2a500000 0x0 0x40000>,
- <0x0 0x28440000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- bootph-pre-ram;
- };
-
- dma-controller@285c0000 {
- reg = <0x0 0x285c0000 0x0 0x100>,
- <0x0 0x284c0000 0x0 0x4000>,
- <0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x284a0000 0x0 0x4000>,
- <0x0 0x2aa00000 0x0 0x40000>,
- <0x0 0x28400000 0x0 0x2000>;
- reg-names = "gcfg", "rchan", "rchanrt", "tchan",
- "tchanrt", "rflow";
- bootph-pre-ram;
- };
- };
+ bootph-all;
chipid@43000014 {
- bootph-pre-ram;
+ bootph-all;
};
};
+&mcu_navss {
+ bootph-all;
+};
+
+&mcu_ringacc {
+ bootph-all;
+};
+
+&mcu_udmap {
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x284c0000 0x0 0x4000>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x284a0000 0x0 0x4000>,
+ <0x0 0x2aa00000 0x0 0x40000>,
+ <0x0 0x28400000 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
+ bootph-all;
+};
+
&secure_proxy_main {
- bootph-pre-ram;
+ bootph-all;
};
&dmsc {
- bootph-pre-ram;
+ bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- bootph-pre-ram;
+ bootph-all;
};
};
&k3_pds {
- bootph-pre-ram;
+ bootph-all;
};
&k3_clks {
- bootph-pre-ram;
+ bootph-all;
};
&k3_reset {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_pmx0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_pmx0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_uart0 {
- bootph-pre-ram;
+ bootph-all;
};
&mcu_uart0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_sdhci0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_sdhci1 {
- bootph-pre-ram;
+ bootph-all;
};
-&wiz3_pll1_refclk {
- assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>;
- assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>;
+&main_uart0_pins_default {
+ bootph-all;
};
&main_usbss0_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&usbss0 {
- bootph-pre-ram;
+ bootph-all;
};
&usb0 {
dr_mode = "peripheral";
- bootph-pre-ram;
-};
-
-&mcu_cpsw {
- reg = <0x0 0x46000000 0x0 0x200000>,
- <0x0 0x40f00200 0x0 0x2>;
- reg-names = "cpsw_nuss", "mac_efuse";
- /delete-property/ ranges;
-
- cpsw-phy-sel@40f04040 {
- compatible = "ti,am654-cpsw-phy-sel";
- reg= <0x0 0x40f04040 0x0 0x4>;
- reg-names = "gmii-sel";
- };
+ bootph-all;
};
&main_mmc1_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_i2c0_pins_default {
- bootph-pre-ram;
+ bootph-all;
+};
+
+&wkup_uart0 {
+ bootph-all;
+ status = "okay";
};
&wkup_i2c0 {
- bootph-pre-ram;
+ bootph-all;
+ status = "okay";
};
&main_i2c0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_i2c0_pins_default {
- bootph-pre-ram;
+ bootph-all;
+};
+
+&main_esm {
+ bootph-all;
};
&exp2 {
- bootph-pre-ram;
+ bootph-all;
};
&mcu_fss0_ospi0_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&fss {
- bootph-pre-ram;
-};
-
-&hbmc {
- bootph-pre-ram;
-
- flash@0,0 {
- bootph-pre-ram;
- };
-};
-
-&hbmc_mux {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_gpio0 {
- bootph-pre-ram;
+ bootph-all;
};
&ospi0 {
- bootph-pre-ram;
+ bootph-all;
flash@0 {
- bootph-pre-ram;
+ bootph-all;
};
};
&ospi1 {
- bootph-pre-ram;
+ bootph-all;
flash@0 {
- bootph-pre-ram;
+ bootph-all;
};
};
&mcu_fss0_hpb0_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_gpio_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&mcu_fss0_ospi1_pins_default {
- bootph-pre-ram;
-};
-
-&main_r5fss0 {
- ti,cluster-mode = <0>;
-};
-
-&main_r5fss1 {
- ti,cluster-mode = <0>;
-};
-
-&wiz3_pll1_refclk {
- assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>;
- assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>;
-};
-
-&serdes_ln_ctrl {
- u-boot,mux-autoprobe;
-};
-
-&usb_serdes_mux {
- u-boot,mux-autoprobe;
-};
-
-&serdes0 {
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
-};
-
-&serdes0_pcie_link {
- assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
- assigned-clock-parents = <&wiz0_pll1_refclk>;
-};
-
-&serdes0_qsgmii_link {
- assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
- assigned-clock-parents = <&wiz0_pll1_refclk>;
+ bootph-all;
};
diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts
index 1b60054..fe5207a 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-common-proc-board.dts
@@ -1,6 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Product Link: https://www.ti.com/tool/J721EXCPXEVM
*/
/dts-v1/;
@@ -12,24 +14,38 @@
#include <dt-bindings/phy/phy-cadence.h>
/ {
+ compatible = "ti,j721e-evm", "ti,j721e";
+ model = "Texas Instruments J721e EVM";
+
+ aliases {
+ serial0 = &wkup_uart0;
+ serial1 = &mcu_uart0;
+ serial2 = &main_uart0;
+ serial3 = &main_uart1;
+ serial4 = &main_uart2;
+ serial6 = &main_uart4;
+ ethernet0 = &cpsw_port1;
+ mmc0 = &main_sdhci0;
+ mmc1 = &main_sdhci1;
+ };
+
chosen {
stdout-path = "serial2:115200n8";
- bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
gpio_keys: gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
- pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;
+ pinctrl-0 = <&sw10_button_pins_default>, <&sw11_button_pins_default>;
- sw10: sw10 {
+ sw10: switch-10 {
label = "GPIO Key USER1";
linux,code = <BTN_0>;
gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
};
- sw11: sw11 {
+ sw11: switch-11 {
label = "GPIO Key USER2";
linux,code = <BTN_1>;
gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
@@ -93,7 +109,7 @@
<3300000 0x1>;
};
- sound0: sound@0 {
+ sound0: sound-0 {
compatible = "ti,j721e-cpb-audio";
model = "j721e-cpb";
@@ -109,16 +125,104 @@
"cpb-codec-scki",
"cpb-codec-scki-48000", "cpb-codec-scki-44100";
};
+
+ transceiver1: can-phy0 {
+ compatible = "ti,tcan1043";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
+ standby-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_LOW>;
+ enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ transceiver2: can-phy1 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
+ standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ transceiver3: can-phy2 {
+ compatible = "ti,tcan1043";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
+ enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ transceiver4: can-phy3 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan2_gpio_pins_default>;
+ standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>;
+ };
+
+ dp_pwr_3v3: regulator-dp-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "dp-pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */
+ enable-active-high;
+ };
+
+ dp0: connector {
+ compatible = "dp-connector";
+ label = "DP0";
+ type = "full-size";
+ dp-pwr-supply = <&dp_pwr_3v3>;
+
+ port {
+ dp_connector_in: endpoint {
+ remote-endpoint = <&dp0_out>;
+ };
+ };
+ };
};
&main_pmx0 {
- sw10_button_pins_default: sw10-button-pins-default {
+ main_uart0_pins_default: main-uart0-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */
+ J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */
+ J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
+ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
+ >;
+ };
+
+ main_uart1_pins_default: main-uart1-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */
+ J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */
+ >;
+ };
+
+ main_uart2_pins_default: main-uart2-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1dc, PIN_INPUT, 3) /* (Y1) SPI1_CLK.UART2_RXD */
+ J721E_IOPAD(0x1e0, PIN_OUTPUT, 3) /* (Y5) SPI1_D0.UART2_TXD */
+ >;
+ };
+
+ main_uart4_pins_default: main-uart4-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x190, PIN_INPUT, 1) /* (W23) RGMII6_TD3.UART4_RXD */
+ J721E_IOPAD(0x194, PIN_OUTPUT, 1) /* (W28) RGMII6_TD2.UART4_TXD */
+ >;
+ };
+
+ sw10_button_pins_default: sw10-button-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
>;
};
- main_mmc1_pins_default: main-mmc1-pins-default {
+ main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
@@ -132,60 +236,66 @@
>;
};
- vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
+ vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
>;
};
- main_usbss0_pins_default: main-usbss0-pins-default {
+ main_usbss0_pins_default: main-usbss0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
>;
};
- main_usbss1_pins_default: main-usbss1-pins-default {
+ main_usbss1_pins_default: main-usbss1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
>;
};
- main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
+ dp0_pins_default: dp0-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
+ >;
+ };
+
+ main_i2c1_exp4_pins_default: main-i2c1-exp4-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
>;
};
- main_i2c0_pins_default: main-i2c0-pins-default {
+ main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
>;
};
- main_i2c1_pins_default: main-i2c1-pins-default {
+ main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
>;
};
- main_i2c3_pins_default: main-i2c3-pins-default {
+ main_i2c3_pins_default: main-i2c3-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
>;
};
- main_i2c6_pins_default: main-i2c6-pins-default {
+ main_i2c6_pins_default: main-i2c6-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
>;
};
- mcasp10_pins_default: mcasp10-pins-default {
+ mcasp10_pins_default: mcasp10-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
@@ -199,27 +309,57 @@
>;
};
- audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default {
+ audi_ext_refclk2_pins_default: audi-ext-refclk2-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */
>;
};
+
+ main_mcan0_pins_default: main-mcan0-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */
+ J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */
+ >;
+ };
+
+ main_mcan2_pins_default: main-mcan2-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */
+ J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */
+ >;
+ };
+
+ main_mcan2_gpio_pins_default: main-mcan2-gpio-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */
+ >;
+ };
};
&wkup_pmx0 {
- sw11_button_pins_default: sw11-button-pins-default {
+ wkup_uart0_pins_default: wkup-uart0-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
+ J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
+ >;
+ };
+
+ mcu_uart0_pins_default: mcu-uart0-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */
+ J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */
+ J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
+ J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
+ >;
+ };
+
+ sw11_button_pins_default: sw11-button-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
>;
};
- wkup_gpio_pins_default: wkup-gpio-pins-default {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */
- >;
- };
-
- mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
+ mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
@@ -232,7 +372,7 @@
>;
};
- mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+ mcu_cpsw_pins_default: mcu-cpsw-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
@@ -249,83 +389,103 @@
>;
};
- mcu_mdio_pins_default: mcu-mdio1-pins-default {
+ mcu_mdio_pins_default: mcu-mdio1-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */
J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */
>;
};
+
+ mcu_mcan0_pins_default: mcu-mcan0-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */
+ J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */
+ >;
+ };
+
+ mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */
+ J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */
+ >;
+ };
+
+ mcu_mcan1_pins_default: mcu-mcan1-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */
+ J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */
+ >;
+ };
+
+ mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */
+ >;
+ };
+
+ wkup_gpio_pins_default: wkup-gpio-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */
+ >;
+ };
};
&wkup_uart0 {
/* Wakeup UART is used by System firmware */
status = "reserved";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+};
+
+&mcu_uart0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_uart0_pins_default>;
};
&main_uart0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+ /* Shared with ATF on this platform */
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
-&main_uart3 {
- /* UART not brought out */
- status = "disabled";
+&main_uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
};
-&main_uart5 {
- /* UART not brought out */
- status = "disabled";
+&main_uart2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart2_pins_default>;
};
-&main_uart6 {
- /* UART not brought out */
- status = "disabled";
+&main_uart4 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart4_pins_default>;
};
-&main_uart7 {
- /* UART not brought out */
- status = "disabled";
+&wkup_gpio0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_gpio_pins_default>;
};
-&main_uart8 {
- /* UART not brought out */
- status = "disabled";
+&main_gpio0 {
+ status = "okay";
};
-&main_uart9 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_gpio2 {
- status = "disabled";
-};
-
-&main_gpio3 {
- status = "disabled";
-};
-
-&main_gpio4 {
- status = "disabled";
-};
-
-&main_gpio5 {
- status = "disabled";
-};
-
-&main_gpio6 {
- status = "disabled";
-};
-
-&main_gpio7 {
- status = "disabled";
-};
-
-&wkup_gpio1 {
- status = "disabled";
+&main_gpio1 {
+ status = "okay";
};
&main_sdhci0 {
/* eMMC */
+ status = "okay";
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
@@ -333,6 +493,7 @@
&main_sdhci1 {
/* SD/MMC */
+ status = "okay";
vmmc-supply = <&vdd_mmc1>;
vqmmc-supply = <&vdd_sd_dv_alt>;
pinctrl-names = "default";
@@ -341,17 +502,12 @@
disable-wp;
};
-&main_sdhci2 {
- /* Unused */
- status = "disabled";
-};
-
&usb_serdes_mux {
idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
};
&serdes_ln_ctrl {
- idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
+ idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
<J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
<J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
<J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
@@ -387,11 +543,6 @@
phy-names = "cdns3,usb3-phy";
};
-&wkup_gpio0 {
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_gpio_pins_default>;
-};
-
&usbss1 {
pinctrl-names = "default";
pinctrl-0 = <&main_usbss1_pins_default>;
@@ -407,7 +558,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
- flash@0{
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <1>;
@@ -418,24 +569,71 @@
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <2>;
- #address-cells = <1>;
- #size-cells = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "qspi.tiboot3";
+ reg = <0x0 0x80000>;
+ };
+
+ partition@80000 {
+ label = "qspi.tispl";
+ reg = <0x80000 0x200000>;
+ };
+
+ partition@280000 {
+ label = "qspi.u-boot";
+ reg = <0x280000 0x400000>;
+ };
+
+ partition@680000 {
+ label = "qspi.env";
+ reg = <0x680000 0x20000>;
+ };
+
+ partition@6a0000 {
+ label = "qspi.env.backup";
+ reg = <0x6a0000 0x20000>;
+ };
+
+ partition@6c0000 {
+ label = "qspi.sysfw";
+ reg = <0x6c0000 0x100000>;
+ };
+
+ partition@800000 {
+ label = "qspi.rootfs";
+ reg = <0x800000 0x37c0000>;
+ };
+
+ partition@3fe0000 {
+ label = "qspi.phypattern";
+ reg = <0x3fe0000 0x20000>;
+ };
+ };
};
};
&tscadc0 {
+ status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
&tscadc1 {
+ status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
&main_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
@@ -472,6 +670,7 @@
};
&main_i2c1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
@@ -497,6 +696,7 @@
};
&main_i2c3 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c3_pins_default>;
clock-frequency = <400000>;
@@ -535,6 +735,7 @@
};
&main_i2c6 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c6_pins_default>;
clock-frequency = <400000>;
@@ -549,7 +750,7 @@
&mcu_cpsw {
pinctrl-names = "default";
- pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+ pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
};
&davinci_mdio {
@@ -585,47 +786,35 @@
<&k3_clks 152 18>; /* PLL23_HSDIV0 */
};
-&mcasp0 {
- status = "disabled";
+&dss_ports {
+ port {
+ dpi0_out: endpoint {
+ remote-endpoint = <&dp0_in>;
+ };
+ };
};
-&mcasp1 {
- status = "disabled";
-};
+&dp0_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
-&mcasp2 {
- status = "disabled";
-};
+ port@0 {
+ reg = <0>;
+ dp0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
-&mcasp3 {
- status = "disabled";
-};
-
-&mcasp4 {
- status = "disabled";
-};
-
-&mcasp5 {
- status = "disabled";
-};
-
-&mcasp6 {
- status = "disabled";
-};
-
-&mcasp7 {
- status = "disabled";
-};
-
-&mcasp8 {
- status = "disabled";
-};
-
-&mcasp9 {
- status = "disabled";
+ port@4 {
+ reg = <4>;
+ dp0_out: endpoint {
+ remote-endpoint = <&dp_connector_in>;
+ };
+ };
};
&mcasp10 {
+ status = "okay";
#sound-dai-cells = <0>;
pinctrl-names = "default";
@@ -643,10 +832,6 @@
rx-num-evt = <0>;
};
-&mcasp11 {
- status = "disabled";
-};
-
&cmn_refclk1 {
clock-frequency = <100000000>;
};
@@ -682,8 +867,8 @@
};
&serdes0 {
- assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
- assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
+ assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
+ assigned-clock-parents = <&wiz0_pll1_refclk>;
serdes0_pcie_link: phy@0 {
reg = <0>;
@@ -692,14 +877,6 @@
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>;
};
-
- serdes0_qsgmii_link: phy@1 {
- reg = <1>;
- cdns,num-lanes = <1>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_QSGMII>;
- resets = <&serdes_wiz0 2>;
- };
};
&serdes1 {
@@ -728,7 +905,26 @@
};
};
+&serdes4 {
+ torrent_phy_dp: phy@0 {
+ reg = <0>;
+ resets = <&serdes_wiz4 1>;
+ cdns,phy-type = <PHY_TYPE_DP>;
+ cdns,num-lanes = <4>;
+ cdns,max-bit-rate = <5400>;
+ #phy-cells = <0>;
+ };
+};
+
+&mhdp {
+ phys = <&torrent_phy_dp>;
+ phy-names = "dpphy";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp0_pins_default>;
+};
+
&pcie0_rc {
+ status = "okay";
reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
@@ -736,6 +932,7 @@
};
&pcie1_rc {
+ status = "okay";
reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
phys = <&serdes1_pcie_link>;
phy-names = "pcie-phy";
@@ -743,49 +940,37 @@
};
&pcie2_rc {
+ status = "okay";
reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
phys = <&serdes2_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <2>;
};
-&pcie0_ep {
- phys = <&serdes0_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <1>;
- status = "disabled";
+&mcu_mcan0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan0_pins_default>;
+ phys = <&transceiver1>;
};
-&pcie1_ep {
- phys = <&serdes1_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <2>;
- status = "disabled";
+&mcu_mcan1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan1_pins_default>;
+ phys = <&transceiver2>;
};
-&pcie2_ep {
- phys = <&serdes2_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <2>;
- status = "disabled";
+&main_mcan0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan0_pins_default>;
+ phys = <&transceiver3>;
};
-&pcie3_rc {
- status = "disabled";
-};
-
-&pcie3_ep {
- status = "disabled";
-};
-
-&dss {
- status = "disabled";
-};
-
-&icssg0_mdio {
- status = "disabled";
-};
-
-&icssg1_mdio {
- status = "disabled";
+&main_mcan2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan2_pins_default>;
+ phys = <&transceiver4>;
};
diff --git a/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi
index 5a6f9b1..66e1581 100644
--- a/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi
+++ b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.1
* This file was generated on 07/17/2022
*/
diff --git a/arch/arm/dts/k3-j721e-ddr-sk-lp4-4266.dtsi b/arch/arm/dts/k3-j721e-ddr-sk-lp4-4266.dtsi
index 6c7328e..18f1944 100644
--- a/arch/arm/dts/k3-j721e-ddr-sk-lp4-4266.dtsi
+++ b/arch/arm/dts/k3-j721e-ddr-sk-lp4-4266.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.6.1
* This file was generated on 07/19/2021
*/
diff --git a/arch/arm/dts/k3-j721e-ddr.dtsi b/arch/arm/dts/k3-j721e-ddr.dtsi
index 3a9ea42..7d2ccd9 100644
--- a/arch/arm/dts/k3-j721e-ddr.dtsi
+++ b/arch/arm/dts/k3-j721e-ddr.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi
index cf34823..f6c7e16 100644
--- a/arch/arm/dts/k3-j721e-main.dtsi
+++ b/arch/arm/dts/k3-j721e-main.dtsi
@@ -5,8 +5,10 @@
* Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-ti.h>
#include <dt-bindings/mux/mux.h>
-#include <dt-bindings/mux/ti-serdes.h>
+
+#include "k3-serdes.h"
/ {
cmn_refclk: clock-cmnrefclk {
@@ -42,7 +44,7 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x00100000 0x1c000>;
- serdes_ln_ctrl: mux@4080 {
+ serdes_ln_ctrl: mux-controller@4080 {
compatible = "mmio-mux";
reg = <0x00004080 0x50>;
#mux-control-cells = <1>;
@@ -60,12 +62,85 @@
<J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
};
+ cpsw0_phy_gmii_sel: phy@4044 {
+ compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
+ ti,qsgmii-main-ports = <2>, <2>;
+ reg = <0x4044 0x20>;
+ #phy-cells = <1>;
+ };
+
usb_serdes_mux: mux-controller@4000 {
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
<0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
- };
+ };
+
+ ehrpwm_tbclk: clock-controller@4140 {
+ compatible = "ti,am654-ehrpwm-tbclk";
+ reg = <0x4140 0x18>;
+ #clock-cells = <1>;
+ };
+ };
+
+ main_ehrpwm0: pwm@3000000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3000000 0x00 0x100>;
+ power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ main_ehrpwm1: pwm@3010000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3010000 0x00 0x100>;
+ power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ main_ehrpwm2: pwm@3020000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3020000 0x00 0x100>;
+ power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ main_ehrpwm3: pwm@3030000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3030000 0x00 0x100>;
+ power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ main_ehrpwm4: pwm@3040000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3040000 0x00 0x100>;
+ power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ main_ehrpwm5: pwm@3050000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3050000 0x00 0x100>;
+ power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
};
gic500: interrupt-controller@1800000 {
@@ -76,7 +151,10 @@
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01900000 0x00 0x100000>; /* GICR */
+ <0x00 0x01900000 0x00 0x100000>, /* GICR */
+ <0x00 0x6f000000 0x00 0x2000>, /* GICC */
+ <0x00 0x6f010000 0x00 0x1000>, /* GICH */
+ <0x00 0x6f020000 0x00 0x2000>; /* GICV */
/* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
@@ -172,6 +250,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster1: mailbox@31f81000 {
@@ -181,6 +260,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster2: mailbox@31f82000 {
@@ -190,6 +270,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster3: mailbox@31f83000 {
@@ -199,6 +280,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster4: mailbox@31f84000 {
@@ -208,6 +290,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster5: mailbox@31f85000 {
@@ -217,6 +300,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster6: mailbox@31f86000 {
@@ -226,6 +310,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster7: mailbox@31f87000 {
@@ -235,6 +320,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster8: mailbox@31f88000 {
@@ -244,6 +330,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster9: mailbox@31f89000 {
@@ -253,6 +340,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster10: mailbox@31f8a000 {
@@ -262,6 +350,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster11: mailbox@31f8b000 {
@@ -271,15 +360,17 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
main_ringacc: ringacc@3c000000 {
compatible = "ti,am654-navss-ringacc";
- reg = <0x0 0x3c000000 0x0 0x400000>,
- <0x0 0x38000000 0x0 0x400000>,
- <0x0 0x31120000 0x0 0x100>,
- <0x0 0x33000000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ reg = <0x0 0x3c000000 0x0 0x400000>,
+ <0x0 0x38000000 0x0 0x400000>,
+ <0x0 0x31120000 0x0 0x100>,
+ <0x0 0x33000000 0x0 0x40000>,
+ <0x0 0x31080000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
ti,num-rings = <1024>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
@@ -289,9 +380,9 @@
main_udmap: dma-controller@31150000 {
compatible = "ti,j721e-navss-main-udmap";
- reg = <0x0 0x31150000 0x0 0x100>,
- <0x0 0x34000000 0x0 0x100000>,
- <0x0 0x35000000 0x0 0x100000>;
+ reg = <0x0 0x31150000 0x0 0x100>,
+ <0x0 0x34000000 0x0 0x100000>,
+ <0x0 0x35000000 0x0 0x100000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
@@ -322,6 +413,115 @@
};
};
+ cpsw0: ethernet@c000000 {
+ compatible = "ti,j721e-cpswxg-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0xc000000 0x0 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>;
+ clocks = <&k3_clks 19 89>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
+
+ dmas = <&main_udmap 0xca00>,
+ <&main_udmap 0xca01>,
+ <&main_udmap 0xca02>,
+ <&main_udmap 0xca03>,
+ <&main_udmap 0xca04>,
+ <&main_udmap 0xca05>,
+ <&main_udmap 0xca06>,
+ <&main_udmap 0xca07>,
+ <&main_udmap 0x4a00>;
+ dma-names = "tx0", "tx1", "tx2", "tx3",
+ "tx4", "tx5", "tx6", "tx7",
+ "rx";
+
+ status = "disabled";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpsw0_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ status = "disabled";
+ };
+
+ cpsw0_port2: port@2 {
+ reg = <2>;
+ ti,mac-only;
+ label = "port2";
+ status = "disabled";
+ };
+
+ cpsw0_port3: port@3 {
+ reg = <3>;
+ ti,mac-only;
+ label = "port3";
+ status = "disabled";
+ };
+
+ cpsw0_port4: port@4 {
+ reg = <4>;
+ ti,mac-only;
+ label = "port4";
+ status = "disabled";
+ };
+
+ cpsw0_port5: port@5 {
+ reg = <5>;
+ ti,mac-only;
+ label = "port5";
+ status = "disabled";
+ };
+
+ cpsw0_port6: port@6 {
+ reg = <6>;
+ ti,mac-only;
+ label = "port6";
+ status = "disabled";
+ };
+
+ cpsw0_port7: port@7 {
+ reg = <7>;
+ ti,mac-only;
+ label = "port7";
+ status = "disabled";
+ };
+
+ cpsw0_port8: port@8 {
+ reg = <8>;
+ ti,mac-only;
+ label = "port8";
+ status = "disabled";
+ };
+ };
+
+ cpsw9g_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x0 0xf00 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 19 89>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ status = "disabled";
+ };
+
+ cpts@3d000 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x0 0x3d000 0x0 0x400>;
+ clocks = <&k3_clks 19 16>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+
main_crypto: crypto@4e00000 {
compatible = "ti,j721e-sa2ul";
reg = <0x0 0x4e00000 0x0 0x1200>;
@@ -333,13 +533,11 @@
dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
<&main_udmap 0x4001>;
dma-names = "tx", "rx1", "rx2";
- dma-coherent;
rng: rng@4e10000 {
compatible = "inside-secure,safexcel-eip76";
reg = <0x0 0x4e10000 0x0 0x7d>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 264 1>;
};
};
@@ -352,6 +550,24 @@
pinctrl-single,function-mask = <0xffffffff>;
};
+ /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
+ main_timerio_input: pinctrl@104200 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x104200 0x00 0x50>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x00000007>;
+ };
+
+ /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
+ main_timerio_output: pinctrl@104280 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x104280 0x00 0x20>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000001f>;
+ };
+
serdes_wiz0: wiz@5000000 {
compatible = "ti,j721e-wiz-16g";
#address-cells = <1>;
@@ -446,7 +662,7 @@
assigned-clock-parents = <&k3_clks 293 13>;
};
- wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{
+ wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div {
clocks = <&wiz1_refclk_dig>;
#clock-cells = <0>;
};
@@ -610,7 +826,7 @@
clock-names = "fck";
#address-cells = <3>;
#size-cells = <2>;
- bus-range = <0x0 0xf>;
+ bus-range = <0x0 0xff>;
vendor-id = <0x104c>;
device-id = <0xb00d>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
@@ -618,26 +834,7 @@
ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
<0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
- };
-
- pcie0_ep: pcie-ep@2900000 {
- compatible = "ti,j721e-pcie-ep";
- reg = <0x00 0x02900000 0x00 0x1000>,
- <0x00 0x02907000 0x00 0x400>,
- <0x00 0x0d000000 0x00 0x00800000>,
- <0x00 0x10000000 0x00 0x08000000>;
- reg-names = "intd_cfg", "user_cfg", "reg", "mem";
- interrupt-names = "link_state";
- interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
- max-link-speed = <3>;
- num-lanes = <2>;
- power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 239 1>;
- clock-names = "fck";
- max-functions = /bits/ 8 <6>;
- max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
- dma-coherent;
+ status = "disabled";
};
pcie1_rc: pcie@2910000 {
@@ -658,7 +855,7 @@
clock-names = "fck";
#address-cells = <3>;
#size-cells = <2>;
- bus-range = <0x0 0xf>;
+ bus-range = <0x0 0xff>;
vendor-id = <0x104c>;
device-id = <0xb00d>;
msi-map = <0x0 &gic_its 0x10000 0x10000>;
@@ -666,26 +863,7 @@
ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
<0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
- };
-
- pcie1_ep: pcie-ep@2910000 {
- compatible = "ti,j721e-pcie-ep";
- reg = <0x00 0x02910000 0x00 0x1000>,
- <0x00 0x02917000 0x00 0x400>,
- <0x00 0x0d800000 0x00 0x00800000>,
- <0x00 0x18000000 0x00 0x08000000>;
- reg-names = "intd_cfg", "user_cfg", "reg", "mem";
- interrupt-names = "link_state";
- interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
- max-link-speed = <3>;
- num-lanes = <2>;
- power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 240 1>;
- clock-names = "fck";
- max-functions = /bits/ 8 <6>;
- max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
- dma-coherent;
+ status = "disabled";
};
pcie2_rc: pcie@2920000 {
@@ -706,7 +884,7 @@
clock-names = "fck";
#address-cells = <3>;
#size-cells = <2>;
- bus-range = <0x0 0xf>;
+ bus-range = <0x0 0xff>;
vendor-id = <0x104c>;
device-id = <0xb00d>;
msi-map = <0x0 &gic_its 0x20000 0x10000>;
@@ -714,26 +892,7 @@
ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
<0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
- };
-
- pcie2_ep: pcie-ep@2920000 {
- compatible = "ti,j721e-pcie-ep";
- reg = <0x00 0x02920000 0x00 0x1000>,
- <0x00 0x02927000 0x00 0x400>,
- <0x00 0x0e000000 0x00 0x00800000>,
- <0x44 0x00000000 0x00 0x08000000>;
- reg-names = "intd_cfg", "user_cfg", "reg", "mem";
- interrupt-names = "link_state";
- interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
- max-link-speed = <3>;
- num-lanes = <2>;
- power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 241 1>;
- clock-names = "fck";
- max-functions = /bits/ 8 <6>;
- max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
- dma-coherent;
+ status = "disabled";
};
pcie3_rc: pcie@2930000 {
@@ -754,7 +913,7 @@
clock-names = "fck";
#address-cells = <3>;
#size-cells = <2>;
- bus-range = <0x0 0xf>;
+ bus-range = <0x0 0xff>;
vendor-id = <0x104c>;
device-id = <0xb00d>;
msi-map = <0x0 &gic_its 0x30000 0x10000>;
@@ -762,28 +921,288 @@
ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
<0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ status = "disabled";
};
- pcie3_ep: pcie-ep@2930000 {
- compatible = "ti,j721e-pcie-ep";
- reg = <0x00 0x02930000 0x00 0x1000>,
- <0x00 0x02937000 0x00 0x400>,
- <0x00 0x0e800000 0x00 0x00800000>,
- <0x44 0x10000000 0x00 0x08000000>;
- reg-names = "intd_cfg", "user_cfg", "reg", "mem";
- interrupt-names = "link_state";
- interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
- max-link-speed = <3>;
- num-lanes = <2>;
- power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 242 1>;
+ serdes_wiz4: wiz@5050000 {
+ compatible = "ti,am64-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ assigned-clocks = <&k3_clks 297 9>;
+ assigned-clock-parents = <&k3_clks 297 10>;
+ assigned-clock-rates = <19200000>;
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x05050000 0x00 0x05050000 0x010000>,
+ <0x0a030a00 0x00 0x0a030a00 0x40>;
+
+ serdes4: serdes@5050000 {
+ /*
+ * Note: we also map DPTX PHY registers as the Torrent
+ * needs to manage those.
+ */
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05050000 0x010000>,
+ <0x0a030a00 0x40>; /* DPTX PHY */
+ reg-names = "torrent_phy", "dptx_phy";
+
+ resets = <&serdes_wiz4 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>;
+ clock-names = "refclk";
+ assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 297 9>,
+ <&k3_clks 297 9>,
+ <&k3_clks 297 9>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ main_timer0: timer@2400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2400000 0x00 0x400>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 49 1>;
clock-names = "fck";
- max-functions = /bits/ 8 <6>;
- max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
- dma-coherent;
- #address-cells = <2>;
- #size-cells = <2>;
+ assigned-clocks = <&k3_clks 49 1>;
+ assigned-clock-parents = <&k3_clks 49 2>;
+ power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer1: timer@2410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2410000 0x00 0x400>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 50 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>;
+ assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>;
+ power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer2: timer@2420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2420000 0x00 0x400>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 51 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 51 1>;
+ assigned-clock-parents = <&k3_clks 51 2>;
+ power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer3: timer@2430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2430000 0x00 0x400>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 52 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>;
+ assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>;
+ power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer4: timer@2440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2440000 0x00 0x400>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 53 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 53 1>;
+ assigned-clock-parents = <&k3_clks 53 2>;
+ power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer5: timer@2450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2450000 0x00 0x400>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 54 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>;
+ assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>;
+ power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer6: timer@2460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2460000 0x00 0x400>;
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 55 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 55 1>;
+ assigned-clock-parents = <&k3_clks 55 2>;
+ power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer7: timer@2470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2470000 0x00 0x400>;
+ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 57 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>;
+ assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>;
+ power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer8: timer@2480000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2480000 0x00 0x400>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 58 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 58 1>;
+ assigned-clock-parents = <&k3_clks 58 2>;
+ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer9: timer@2490000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2490000 0x00 0x400>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 59 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>;
+ assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>;
+ power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer10: timer@24a0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24a0000 0x00 0x400>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 60 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 60 1>;
+ assigned-clock-parents = <&k3_clks 60 2>;
+ power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer11: timer@24b0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24b0000 0x00 0x400>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 62 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>;
+ assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>;
+ power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer12: timer@24c0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24c0000 0x00 0x400>;
+ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 63 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 63 1>;
+ assigned-clock-parents = <&k3_clks 63 2>;
+ power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer13: timer@24d0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24d0000 0x00 0x400>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 64 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>;
+ assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>;
+ power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer14: timer@24e0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24e0000 0x00 0x400>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 65 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 65 1>;
+ assigned-clock-parents = <&k3_clks 65 2>;
+ power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer15: timer@24f0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24f0000 0x00 0x400>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 66 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>;
+ assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>;
+ power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer16: timer@2500000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2500000 0x00 0x400>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 67 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 67 1>;
+ assigned-clock-parents = <&k3_clks 67 2>;
+ power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer17: timer@2510000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2510000 0x00 0x400>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 68 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>;
+ assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>;
+ power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer18: timer@2520000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2520000 0x00 0x400>;
+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 69 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 69 1>;
+ assigned-clock-parents = <&k3_clks 69 2>;
+ power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer19: timer@2530000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2530000 0x00 0x400>;
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 70 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>;
+ assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>;
+ power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
};
main_uart0: serial@2800000 {
@@ -795,6 +1214,7 @@
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 146 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart1: serial@2810000 {
@@ -806,6 +1226,7 @@
power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 278 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart2: serial@2820000 {
@@ -817,6 +1238,7 @@
power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 279 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart3: serial@2830000 {
@@ -828,6 +1250,7 @@
power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 280 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart4: serial@2840000 {
@@ -839,6 +1262,7 @@
power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 281 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart5: serial@2850000 {
@@ -850,6 +1274,7 @@
power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 282 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart6: serial@2860000 {
@@ -861,6 +1286,7 @@
power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 283 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart7: serial@2870000 {
@@ -872,6 +1298,7 @@
power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 284 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart8: serial@2880000 {
@@ -883,6 +1310,7 @@
power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 285 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart9: serial@2890000 {
@@ -894,6 +1322,7 @@
power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 286 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_gpio0: gpio@600000 {
@@ -911,6 +1340,7 @@
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 105 0>;
clock-names = "gpio";
+ status = "disabled";
};
main_gpio1: gpio@601000 {
@@ -927,6 +1357,7 @@
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 106 0>;
clock-names = "gpio";
+ status = "disabled";
};
main_gpio2: gpio@610000 {
@@ -944,6 +1375,7 @@
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 107 0>;
clock-names = "gpio";
+ status = "disabled";
};
main_gpio3: gpio@611000 {
@@ -960,6 +1392,7 @@
power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 108 0>;
clock-names = "gpio";
+ status = "disabled";
};
main_gpio4: gpio@620000 {
@@ -977,6 +1410,7 @@
power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 109 0>;
clock-names = "gpio";
+ status = "disabled";
};
main_gpio5: gpio@621000 {
@@ -993,6 +1427,7 @@
power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 110 0>;
clock-names = "gpio";
+ status = "disabled";
};
main_gpio6: gpio@630000 {
@@ -1010,6 +1445,7 @@
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 111 0>;
clock-names = "gpio";
+ status = "disabled";
};
main_gpio7: gpio@631000 {
@@ -1026,6 +1462,7 @@
power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 112 0>;
clock-names = "gpio";
+ status = "disabled";
};
main_sdhci0: mmc@4f80000 {
@@ -1040,8 +1477,8 @@
bus-width = <8>;
mmc-hs200-1_8v;
mmc-ddr-1_8v;
- ti,otap-del-sel-legacy = <0xf>;
- ti,otap-del-sel-mmc-hs = <0xf>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-mmc-hs = <0x0>;
ti,otap-del-sel-ddr52 = <0x5>;
ti,otap-del-sel-hs200 = <0x6>;
ti,otap-del-sel-hs400 = <0x0>;
@@ -1049,8 +1486,8 @@
ti,itap-del-sel-mmc-hs = <0xa>;
ti,itap-del-sel-ddr52 = <0x3>;
ti,trm-icp = <0x8>;
- ti,strobe-sel = <0x77>;
dma-coherent;
+ status = "disabled";
};
main_sdhci1: mmc@4fb0000 {
@@ -1063,11 +1500,12 @@
assigned-clocks = <&k3_clks 92 0>;
assigned-clock-parents = <&k3_clks 92 1>;
ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0xf>;
+ ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-ddr50 = <0xc>;
+ ti,otap-del-sel-sdr104 = <0x5>;
ti,itap-del-sel-legacy = <0x0>;
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
@@ -1077,6 +1515,7 @@
ti,clkbuf-sel = <0x7>;
dma-coherent;
sdhci-caps-mask = <0x2 0x0>;
+ status = "disabled";
};
main_sdhci2: mmc@4f98000 {
@@ -1089,11 +1528,12 @@
assigned-clocks = <&k3_clks 93 0>;
assigned-clock-parents = <&k3_clks 93 1>;
ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0xf>;
+ ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-ddr50 = <0xc>;
+ ti,otap-del-sel-sdr104 = <0x5>;
ti,itap-del-sel-legacy = <0x0>;
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
@@ -1103,6 +1543,7 @@
ti,clkbuf-sel = <0x7>;
dma-coherent;
sdhci-caps-mask = <0x2 0x0>;
+ status = "disabled";
};
usbss0: cdns-usb@4104000 {
@@ -1174,6 +1615,7 @@
clock-names = "fck";
clocks = <&k3_clks 187 0>;
power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
+ status = "disabled";
};
main_i2c1: i2c@2010000 {
@@ -1185,6 +1627,7 @@
clock-names = "fck";
clocks = <&k3_clks 188 0>;
power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c2: i2c@2020000 {
@@ -1196,6 +1639,7 @@
clock-names = "fck";
clocks = <&k3_clks 189 0>;
power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c3: i2c@2030000 {
@@ -1207,6 +1651,7 @@
clock-names = "fck";
clocks = <&k3_clks 190 0>;
power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c4: i2c@2040000 {
@@ -1218,6 +1663,7 @@
clock-names = "fck";
clocks = <&k3_clks 191 0>;
power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c5: i2c@2050000 {
@@ -1229,6 +1675,7 @@
clock-names = "fck";
clocks = <&k3_clks 192 0>;
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c6: i2c@2060000 {
@@ -1240,6 +1687,7 @@
clock-names = "fck";
clocks = <&k3_clks 193 0>;
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
ufs_wrapper: ufs-wrapper@4e80000 {
@@ -1264,6 +1712,37 @@
};
};
+ mhdp: dp-bridge@a000000 {
+ compatible = "ti,j721e-mhdp8546";
+ /*
+ * Note: we do not map DPTX PHY area, as that is handled by
+ * the PHY driver.
+ */
+ reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
+ <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */
+ reg-names = "mhdptx", "j721e-intg";
+
+ clocks = <&k3_clks 151 36>;
+
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
+
+ power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
+
+ dp0_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@4 {
+ reg = <4>;
+ };
+ };
+ };
+
dss: dss@4a00000 {
compatible = "ti,j721e-dss";
reg =
@@ -1295,11 +1774,11 @@
"vp1", "vp2", "vp3", "vp4",
"wb";
- clocks = <&k3_clks 152 0>,
- <&k3_clks 152 1>,
- <&k3_clks 152 4>,
- <&k3_clks 152 9>,
- <&k3_clks 152 13>;
+ clocks = <&k3_clks 152 0>,
+ <&k3_clks 152 1>,
+ <&k3_clks 152 4>,
+ <&k3_clks 152 9>,
+ <&k3_clks 152 13>;
clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
@@ -1314,8 +1793,6 @@
"common_s2";
dss_ports: ports {
- #address-cells = <1>;
- #size-cells = <0>;
};
};
@@ -1334,6 +1811,7 @@
clocks = <&k3_clks 174 1>;
clock-names = "fck";
power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp1: mcasp@2b10000 {
@@ -1351,6 +1829,7 @@
clocks = <&k3_clks 175 1>;
clock-names = "fck";
power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp2: mcasp@2b20000 {
@@ -1368,6 +1847,7 @@
clocks = <&k3_clks 176 1>;
clock-names = "fck";
power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp3: mcasp@2b30000 {
@@ -1385,6 +1865,7 @@
clocks = <&k3_clks 177 1>;
clock-names = "fck";
power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp4: mcasp@2b40000 {
@@ -1402,6 +1883,7 @@
clocks = <&k3_clks 178 1>;
clock-names = "fck";
power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp5: mcasp@2b50000 {
@@ -1419,6 +1901,7 @@
clocks = <&k3_clks 179 1>;
clock-names = "fck";
power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp6: mcasp@2b60000 {
@@ -1436,6 +1919,7 @@
clocks = <&k3_clks 180 1>;
clock-names = "fck";
power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp7: mcasp@2b70000 {
@@ -1453,6 +1937,7 @@
clocks = <&k3_clks 181 1>;
clock-names = "fck";
power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp8: mcasp@2b80000 {
@@ -1470,6 +1955,7 @@
clocks = <&k3_clks 182 1>;
clock-names = "fck";
power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp9: mcasp@2b90000 {
@@ -1487,6 +1973,7 @@
clocks = <&k3_clks 183 1>;
clock-names = "fck";
power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp10: mcasp@2ba0000 {
@@ -1504,6 +1991,7 @@
clocks = <&k3_clks 184 1>;
clock-names = "fck";
power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp11: mcasp@2bb0000 {
@@ -1521,6 +2009,7 @@
clocks = <&k3_clks 185 1>;
clock-names = "fck";
power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
watchdog0: watchdog@2200000 {
@@ -1632,6 +2121,7 @@
ti,sci-proc-ids = <0x03 0xff>;
resets = <&k3_reset 142 1>;
firmware-name = "j7-c66_0-fw";
+ status = "disabled";
};
c66_1: dsp@4d81800000 {
@@ -1645,6 +2135,7 @@
ti,sci-proc-ids = <0x04 0xff>;
resets = <&k3_reset 143 1>;
firmware-name = "j7-c66_1-fw";
+ status = "disabled";
};
c71_0: dsp@64800000 {
@@ -1657,6 +2148,7 @@
ti,sci-proc-ids = <0x30 0xff>;
resets = <&k3_reset 15 1>;
firmware-name = "j7-c71_0-fw";
+ status = "disabled";
};
icssg0: icssg@b000000 {
@@ -1797,6 +2289,7 @@
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
+ status = "disabled";
};
};
@@ -1938,6 +2431,311 @@
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
+ status = "disabled";
};
};
+
+ main_mcan0: can@2701000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02701000 0x00 0x200>,
+ <0x00 0x02708000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 156 0>, <&k3_clks 156 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan1: can@2711000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02711000 0x00 0x200>,
+ <0x00 0x02718000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 158 0>, <&k3_clks 158 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan2: can@2721000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02721000 0x00 0x200>,
+ <0x00 0x02728000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 160 0>, <&k3_clks 160 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan3: can@2731000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02731000 0x00 0x200>,
+ <0x00 0x02738000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 161 0>, <&k3_clks 161 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan4: can@2741000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02741000 0x00 0x200>,
+ <0x00 0x02748000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 162 0>, <&k3_clks 162 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan5: can@2751000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02751000 0x00 0x200>,
+ <0x00 0x02758000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 163 0>, <&k3_clks 163 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan6: can@2761000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02761000 0x00 0x200>,
+ <0x00 0x02768000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 164 0>, <&k3_clks 164 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan7: can@2771000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02771000 0x00 0x200>,
+ <0x00 0x02778000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 165 0>, <&k3_clks 165 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan8: can@2781000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02781000 0x00 0x200>,
+ <0x00 0x02788000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 166 0>, <&k3_clks 166 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan9: can@2791000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02791000 0x00 0x200>,
+ <0x00 0x02798000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 167 0>, <&k3_clks 167 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan10: can@27a1000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x027a1000 0x00 0x200>,
+ <0x00 0x027a8000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 168 0>, <&k3_clks 168 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan11: can@27b1000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x027b1000 0x00 0x200>,
+ <0x00 0x027b8000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 169 0>, <&k3_clks 169 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan12: can@27c1000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x027c1000 0x00 0x200>,
+ <0x00 0x027c8000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 170 0>, <&k3_clks 170 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan13: can@27d1000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x027d1000 0x00 0x200>,
+ <0x00 0x027d8000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 171 0>, <&k3_clks 171 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_spi0: spi@2100000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02100000 0x00 0x400>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 266 1>;
+ status = "disabled";
+ };
+
+ main_spi1: spi@2110000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02110000 0x00 0x400>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 267 1>;
+ status = "disabled";
+ };
+
+ main_spi2: spi@2120000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02120000 0x00 0x400>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 268 1>;
+ status = "disabled";
+ };
+
+ main_spi3: spi@2130000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02130000 0x00 0x400>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 269 1>;
+ status = "disabled";
+ };
+
+ main_spi4: spi@2140000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02140000 0x00 0x400>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 270 1>;
+ status = "disabled";
+ };
+
+ main_spi5: spi@2150000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02150000 0x00 0x400>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 271 1>;
+ status = "disabled";
+ };
+
+ main_spi6: spi@2160000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02160000 0x00 0x400>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 272 1>;
+ status = "disabled";
+ };
+
+ main_spi7: spi@2170000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02170000 0x00 0x400>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 273 1>;
+ status = "disabled";
+ };
+
+ main_esm: esm@700000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x0 0x700000 0x0 0x1000>;
+ ti,esm-pins = <344>, <345>;
+ };
};
diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
index 22166c7..05d6ef1 100644
--- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
@@ -12,8 +12,8 @@
mbox-names = "rx", "tx";
- mboxes= <&secure_proxy_main 11>,
- <&secure_proxy_main 13>;
+ mboxes = <&secure_proxy_main 11>,
+ <&secure_proxy_main 13>;
reg-names = "debug_messages";
reg = <0x00 0x44083000 0x0 0x1000>;
@@ -62,6 +62,28 @@
pinctrl-single,function-mask = <0xffffffff>;
};
+ /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
+ mcu_timerio_input: pinctrl@40f04200 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x40f04200 0x00 0x28>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
+ mcu_timerio_output: pinctrl@40f04280 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x40f04280 0x00 0x28>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
mcu_ram: sram@41c00000 {
compatible = "mmio-sram";
reg = <0x00 0x41c00000 0x00 0x100000>;
@@ -70,6 +92,145 @@
#size-cells = <1>;
};
+ mcu_timer0: timer@40400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40400000 0x00 0x400>;
+ interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 35 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 35 1>;
+ assigned-clock-parents = <&k3_clks 35 2>;
+ power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer1: timer@40410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40410000 0x00 0x400>;
+ interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 71 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>;
+ assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>;
+ power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer2: timer@40420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40420000 0x00 0x400>;
+ interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 72 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 72 1>;
+ assigned-clock-parents = <&k3_clks 72 2>;
+ power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer3: timer@40430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40430000 0x00 0x400>;
+ interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 73 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>;
+ assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>;
+ power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer4: timer@40440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40440000 0x00 0x400>;
+ interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 74 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 74 1>;
+ assigned-clock-parents = <&k3_clks 74 2>;
+ power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer5: timer@40450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40450000 0x00 0x400>;
+ interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 75 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>;
+ assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 324 1>;
+ power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer6: timer@40460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40460000 0x00 0x400>;
+ interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 76 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 76 1>;
+ assigned-clock-parents = <&k3_clks 76 2>;
+ power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer7: timer@40470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40470000 0x00 0x400>;
+ interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 77 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>;
+ assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 325 1>;
+ power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer8: timer@40480000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40480000 0x00 0x400>;
+ interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 78 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 78 1>;
+ assigned-clock-parents = <&k3_clks 78 2>;
+ power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer9: timer@40490000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40490000 0x00 0x400>;
+ interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 79 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>;
+ assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 326 1>;
+ power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x100>;
@@ -79,6 +240,7 @@
power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 287 0>;
clock-names = "fclk";
+ status = "disabled";
};
mcu_uart0: serial@40a00000 {
@@ -90,6 +252,7 @@
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 149 0>;
clock-names = "fclk";
+ status = "disabled";
};
wkup_gpio_intr: interrupt-controller@42200000 {
@@ -118,6 +281,7 @@
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 113 0>;
clock-names = "gpio";
+ status = "disabled";
};
wkup_gpio1: gpio@42100000 {
@@ -134,6 +298,7 @@
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>;
clock-names = "gpio";
+ status = "disabled";
};
mcu_i2c0: i2c@40b00000 {
@@ -145,6 +310,7 @@
clock-names = "fck";
clocks = <&k3_clks 194 0>;
power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_i2c1: i2c@40b10000 {
@@ -156,6 +322,7 @@
clock-names = "fck";
clocks = <&k3_clks 195 0>;
power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
wkup_i2c0: i2c@42120000 {
@@ -167,31 +334,35 @@
clock-names = "fck";
clocks = <&k3_clks 197 0>;
power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
+ status = "disabled";
};
- fss: fss@47000000 {
- compatible = "syscon", "simple-mfd";
+ fss: bus@47000000 {
+ compatible = "simple-bus";
reg = <0x0 0x47000000 0x0 0x100>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
- hbmc_mux: hbmc-mux {
- compatible = "mmio-mux";
+ hbmc_mux: mux-controller@47000004 {
+ compatible = "reg-mux";
+ reg = <0x00 0x47000004 0x00 0x2>;
#mux-control-cells = <1>;
mux-reg-masks = <0x4 0x2>; /* HBMC select */
};
hbmc: hyperbus@47034000 {
- compatible = "ti,j721e-hbmc", "ti,am654-hbmc";
- reg = <0x0 0x47034000 0x0 0x100>,
- <0x5 0x00000000 0x1 0x0000000>;
+ compatible = "ti,am654-hbmc";
+ reg = <0x00 0x47034000 0x00 0x100>,
+ <0x05 0x00000000 0x01 0x0000000>;
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 102 0>;
+ assigned-clocks = <&k3_clks 102 5>;
+ assigned-clock-rates = <333333333>;
#address-cells = <2>;
#size-cells = <1>;
mux-controls = <&hbmc_mux 0>;
- assigned-clocks = <&k3_clks 102 0>;
- assigned-clock-rates = <250000000>;
+ status = "disabled";
};
ospi0: spi@47040000 {
@@ -209,6 +380,7 @@
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
ospi1: spi@47050000 {
@@ -223,6 +395,7 @@
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
};
@@ -234,10 +407,11 @@
clocks = <&k3_clks 0 1>;
assigned-clocks = <&k3_clks 0 3>;
assigned-clock-rates = <60000000>;
- clock-names = "adc_tsc_fck";
+ clock-names = "fck";
dmas = <&main_udmap 0x7400>,
<&main_udmap 0x7401>;
dma-names = "fifo0", "fifo1";
+ status = "disabled";
adc {
#io-channel-cells = <1>;
@@ -253,10 +427,11 @@
clocks = <&k3_clks 1 1>;
assigned-clocks = <&k3_clks 1 3>;
assigned-clock-rates = <60000000>;
- clock-names = "adc_tsc_fck";
+ clock-names = "fck";
dmas = <&main_udmap 0x7402>,
<&main_udmap 0x7403>;
dma-names = "fifo0", "fifo1";
+ status = "disabled";
adc {
#io-channel-cells = <1>;
@@ -276,11 +451,12 @@
mcu_ringacc: ringacc@2b800000 {
compatible = "ti,am654-navss-ringacc";
- reg = <0x0 0x2b800000 0x0 0x400000>,
- <0x0 0x2b000000 0x0 0x400000>,
- <0x0 0x28590000 0x0 0x100>,
- <0x0 0x2a500000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ reg = <0x0 0x2b800000 0x0 0x400000>,
+ <0x0 0x2b000000 0x0 0x400000>,
+ <0x0 0x28590000 0x0 0x100>,
+ <0x0 0x2a500000 0x0 0x40000>,
+ <0x0 0x28440000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
ti,num-rings = <286>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
@@ -290,9 +466,9 @@
mcu_udmap: dma-controller@285c0000 {
compatible = "ti,j721e-navss-mcu-udmap";
- reg = <0x0 0x285c0000 0x0 0x100>,
- <0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x2aa00000 0x0 0x40000>;
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x2aa00000 0x0 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
@@ -309,6 +485,21 @@
};
};
+ secure_proxy_mcu: mailbox@2a480000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x0 0x2a480000 0x0 0x80000>,
+ <0x0 0x2a380000 0x0 0x80000>,
+ <0x0 0x2a400000 0x0 0x80000>;
+ /*
+ * Marked Disabled:
+ * Node is incomplete as it is meant for bootloaders and
+ * firmware on non-MPU processors
+ */
+ status = "disabled";
+ };
+
mcu_cpsw: ethernet@46000000 {
compatible = "ti,j721e-cpsw-nuss";
#address-cells = <2>;
@@ -408,4 +599,76 @@
ti,loczrama = <1>;
};
};
+
+ mcu_mcan0: can@40528000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x40528000 0x00 0x200>,
+ <0x00 0x40500000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 172 0>, <&k3_clks 172 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ mcu_mcan1: can@40568000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x40568000 0x00 0x200>,
+ <0x00 0x40540000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 173 0>, <&k3_clks 173 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ mcu_spi0: spi@40300000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040300000 0x00 0x400>;
+ interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 274 0>;
+ status = "disabled";
+ };
+
+ mcu_spi1: spi@40310000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040310000 0x00 0x400>;
+ interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 275 0>;
+ status = "disabled";
+ };
+
+ mcu_spi2: spi@40320000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040320000 0x00 0x400>;
+ interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 276 0>;
+ status = "disabled";
+ };
+
+ wkup_vtm0: temperature-sensor@42040000 {
+ compatible = "ti,j721e-vtm";
+ reg = <0x00 0x42040000 0x00 0x350>,
+ <0x00 0x42050000 0x00 0x350>,
+ <0x00 0x43000300 0x00 0x10>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+ #thermal-sensor-cells = <1>;
+ };
};
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
deleted file mode 100644
index f9746d3..0000000
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
- */
-
-#include "k3-j721e-common-proc-board-u-boot.dtsi"
-
-/ {
- chosen {
- firmware-loader = &fs_loader0;
- };
-
- aliases {
- remoteproc0 = &sysctrler;
- remoteproc1 = &a72_0;
- };
-
- fs_loader0: fs_loader@0 {
- bootph-all;
- compatible = "u-boot,fs-loader";
- };
-};
-
-&tps659413a {
- esm: esm {
- compatible = "ti,tps659413-esm";
- bootph-pre-ram;
- };
-};
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 32f71e9..9655ca2 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -1,27 +1,25 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-#include "k3-j721e-som-p0.dtsi"
+#include "k3-j721e-common-proc-board.dts"
#include "k3-j721e-ddr-evm-lp4-4266.dtsi"
#include "k3-j721e-ddr.dtsi"
-#include "k3-j721e-binman.dtsi"
-#include <dt-bindings/phy/phy-cadence.h>
+#include "k3-j721e-common-proc-board-u-boot.dtsi"
/ {
+ chosen {
+ tick-timer = &mcu_timer0;
+ };
+
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a72_0;
};
- chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
-
a72_0: a72@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
@@ -38,244 +36,49 @@
bootph-pre-ram;
};
- clk_200mhz: dummy_clock_200mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- bootph-pre-ram;
- };
-
- clk_19_2mhz: dummy_clock_19_2mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <19200000>;
- bootph-pre-ram;
- };
-};
-
-&cbass_mcu_wakeup {
- mcu_secproxy: secproxy@28380000 {
- bootph-pre-ram;
- compatible = "ti,am654-secure-proxy";
- reg = <0x0 0x2a380000 0x0 0x80000>,
- <0x0 0x2a400000 0x0 0x80000>,
- <0x0 0x2a480000 0x0 0x80000>;
- reg-names = "rt", "scfg", "target_data";
- #mbox-cells = <1>;
- };
-
- sysctrler: sysctrler {
- bootph-pre-ram;
- compatible = "ti,am654-system-controller";
- mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
- mbox-names = "tx", "rx";
- };
-
- wkup_vtm0: wkup_vtm@42040000 {
- compatible = "ti,am654-vtm", "ti,j721e-avs";
- reg = <0x0 0x42040000 0x0 0x330>;
- power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
- #thermal-sensor-cells = <1>;
- };
-
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <3>;
ti,secure-host;
mbox-names = "rx", "tx";
- mboxes= <&mcu_secproxy 21>,
- <&mcu_secproxy 23>;
+ mboxes= <&secure_proxy_mcu 21>,
+ <&secure_proxy_mcu 23>;
bootph-pre-ram;
};
};
-&cbass_main {
- main_esm: esm@700000 {
- compatible = "ti,j721e-esm";
- reg = <0x0 0x700000 0x0 0x1000>;
- ti,esm-pins = <344>, <345>;
- bootph-pre-ram;
- };
+&mcu_timer0 {
+ status = "okay";
+ bootph-pre-ram;
};
&dmsc {
- mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
+ mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
};
-&wkup_pmx0 {
- wkup_uart0_pins_default: wkup_uart0_pins_default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
- J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
- >;
- };
-
- mcu_uart0_pins_default: mcu_uart0_pins_default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */
- J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */
- J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
- J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
- >;
- };
-
- wkup_i2c0_pins_default: wkup-i2c0-pins-default {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
- J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
- >;
- };
-
- mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
- J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
- J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
- J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
- J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
- J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
- J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
- J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
- J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
- J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
- J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
- J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
- J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
- J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
- >;
- };
-
- wkup_gpio_pins_default: wkup-gpio-pins-default {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* WKUP_GPIO0_8 */
- >;
- };
-
- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
- J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
- J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */
- J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */
- J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */
- J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */
- J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */
- J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */
- J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
- J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
- J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
- >;
- };
-
- mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
- J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
- J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
- J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
- J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
- J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
- J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
- J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
- >;
- };
-};
-
-&main_pmx0 {
- main_uart0_pins_default: main_uart0_pins_default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */
- J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */
- J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
- J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
- >;
- };
-
- main_usbss0_pins_default: main_usbss0_pins_default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
- J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
- >;
- };
-
- main_mmc1_pins_default: main_mmc1_pins_default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
- J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
- J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
- J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
- J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
- J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
- J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
- J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
- J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
- >;
- };
-
- main_i2c0_pins_default: main-i2c0-pins-default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
- J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
- >;
- };
-};
-
-&wkup_uart0 {
+&secure_proxy_mcu {
bootph-pre-ram;
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
};
-&wkup_gpio0 {
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_gpio_pins_default>;
+&cbass_mcu_wakeup {
+ sysctrler: sysctrler {
+ bootph-pre-ram;
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
+ mbox-names = "tx", "rx";
+ };
};
-&mcu_uart0 {
- /delete-property/ power-domains;
- /delete-property/ clocks;
- /delete-property/ clock-names;
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_uart0_pins_default>;
- status = "okay";
- clock-frequency = <48000000>;
+&mcu_ringacc {
+ ti,sci = <&dm_tifs>;
};
-&main_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
- status = "okay";
- power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
-};
-
-&main_sdhci0 {
- /delete-property/ power-domains;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- clock-names = "clk_xin";
- clocks = <&clk_200mhz>;
- ti,driver-strength-ohm = <50>;
- non-removable;
- bus-width = <8>;
-};
-
-&main_sdhci1 {
- /delete-property/ power-domains;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc1_pins_default>;
- clock-names = "clk_xin";
- clocks = <&clk_200mhz>;
- ti,driver-strength-ohm = <50>;
+&mcu_udmap {
+ ti,sci = <&dm_tifs>;
};
&wkup_i2c0 {
@@ -300,148 +103,35 @@
bootph-pre-ram;
};
};
+
+ esm: esm {
+ compatible = "ti,tps659413-esm";
+ bootph-pre-ram;
+ };
};
};
+&wkup_uart0_pins_default {
+ bootph-pre-ram;
+};
+
+&mcu_uart0_pins_default {
+ bootph-pre-ram;
+};
+
&wkup_vtm0 {
vdd-supply-2 = <&buck12_reg>;
bootph-pre-ram;
};
-&usbss0 {
- /delete-property/ power-domains;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- clocks = <&clk_19_2mhz>;
- clock-names = "ref";
- pinctrl-names = "default";
- pinctrl-0 = <&main_usbss0_pins_default>;
- ti,vbus-divider;
-};
-
-&main_i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- exp1: gpio@20 {
- compatible = "ti,tca6416";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- exp2: gpio@22 {
- compatible = "ti,tca6424";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-};
-
-&hbmc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
- reg = <0x0 0x47040000 0x0 0x100>,
- <0x0 0x50000000 0x0 0x8000000>;
- ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */
- <0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */
-
- flash@0,0 {
- compatible = "cypress,hyperflash", "cfi-flash";
- reg = <0x0 0x0 0x4000000>;
- };
-};
-
&ospi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
-
+ /* Address change for data region (32-bit) */
reg = <0x0 0x47040000 0x0 0x100>,
<0x0 0x50000000 0x0 0x8000000>;
-
- flash@0{
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <8>;
- spi-max-frequency = <50000000>;
- cdns,tshsl-ns = <60>;
- cdns,tsd2d-ns = <60>;
- cdns,tchsh-ns = <60>;
- cdns,tslch-ns = <60>;
- cdns,read-delay = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
};
&ospi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
- bootph-pre-ram;
-
+ /* Address change for data region (32-bit) */
reg = <0x0 0x47050000 0x0 0x100>,
<0x0 0x58000000 0x0 0x8000000>;
-
- flash@0{
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <40000000>;
- cdns,tshsl-ns = <60>;
- cdns,tsd2d-ns = <60>;
- cdns,tchsh-ns = <60>;
- cdns,tslch-ns = <60>;
- cdns,read-delay = <2>;
- #address-cells = <1>;
- #size-cells = <1>;
- bootph-pre-ram;
- };
-};
-
-&mcu_ringacc {
- ti,sci = <&dm_tifs>;
-};
-
-&mcu_udmap {
- ti,sci = <&dm_tifs>;
-};
-
-&wiz0_pll1_refclk {
- assigned-clocks = <&wiz0_pll1_refclk>;
- assigned-clock-parents = <&cmn_refclk1>;
-};
-
-&wiz0_refclk_dig {
- assigned-clocks = <&wiz0_refclk_dig>;
- assigned-clock-parents = <&cmn_refclk1>;
-};
-
-&serdes0 {
- assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
- assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
-
- serdes0_pcie_link: link@0 {
- reg = <0>;
- cdns,num-lanes = <1>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_PCIE>;
- resets = <&serdes_wiz0 1>;
- };
-
- serdes0_qsgmii_link: phy@1 {
- reg = <1>;
- cdns,num-lanes = <1>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_QSGMII>;
- resets = <&serdes_wiz0 2>;
- };
-};
-
-/* EEPROM might be read before SYSFW is available */
-&wkup_i2c0 {
- /delete-property/ power-domains;
};
diff --git a/arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi
deleted file mode 100644
index 733d69c..0000000
--- a/arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include "k3-j721e-sk-u-boot.dtsi"
-
-/ {
- chosen {
- firmware-loader = &fs_loader0;
- };
-
- aliases {
- remoteproc0 = &sysctrler;
- remoteproc1 = &a72_0;
- remoteproc2 = &main_r5fss0_core0;
- remoteproc3 = &main_r5fss0_core1;
- };
-
- fs_loader0: fs_loader@0 {
- bootph-all;
- compatible = "u-boot,fs-loader";
- };
-};
-
-&tps659412 {
- esm: esm {
- compatible = "ti,tps659413-esm";
- bootph-pre-ram;
- };
-};
diff --git a/arch/arm/dts/k3-j721e-r5-sk.dts b/arch/arm/dts/k3-j721e-r5-sk.dts
index 6986292..b0c108e 100644
--- a/arch/arm/dts/k3-j721e-r5-sk.dts
+++ b/arch/arm/dts/k3-j721e-r5-sk.dts
@@ -5,156 +5,21 @@
/dts-v1/;
-#include "k3-j721e.dtsi"
+#include "k3-j721e-sk.dts"
#include "k3-j721e-ddr-sk-lp4-4266.dtsi"
#include "k3-j721e-ddr.dtsi"
+#include "k3-j721e-sk-u-boot.dtsi"
/ {
- model = "Texas Instruments J721E SK R5";
+ chosen {
+ tick-timer = &mcu_timer0;
+ };
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a72_0;
};
- chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
-
- memory@80000000 {
- device_type = "memory";
- /* 4G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
- <0x00000008 0x80000000 0x00000000 0x80000000>;
- };
-
- reserved_memory: reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>;
- alignment = <0x1000>;
- no-map;
- };
-
- mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa0000000 0x00 0x100000>;
- no-map;
- };
-
- mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa0100000 0x00 0xf00000>;
- no-map;
- };
-
- mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa1000000 0x00 0x100000>;
- no-map;
- };
-
- mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa1100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa2000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa2100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa3000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa3100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa4000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa4100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa5000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa5100000 0x00 0xf00000>;
- no-map;
- };
-
- c66_1_dma_memory_region: c66-dma-memory@a6000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa6000000 0x00 0x100000>;
- no-map;
- };
-
- c66_0_memory_region: c66-memory@a6100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa6100000 0x00 0xf00000>;
- no-map;
- };
-
- c66_0_dma_memory_region: c66-dma-memory@a7000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa7000000 0x00 0x100000>;
- no-map;
- };
-
- c66_1_memory_region: c66-memory@a7100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa7100000 0x00 0xf00000>;
- no-map;
- };
-
- c71_0_dma_memory_region: c71-dma-memory@a8000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa8000000 0x00 0x100000>;
- no-map;
- };
-
- c71_0_memory_region: c71-memory@a8100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa8100000 0x00 0xf00000>;
- no-map;
- };
-
- rtos_ipc_memory_region: ipc-memories@aa000000 {
- reg = <0x00 0xaa000000 0x00 0x01c00000>;
- alignment = <0x1000>;
- no-map;
- };
- };
-
a72_0: a72@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
@@ -171,233 +36,57 @@
bootph-pre-ram;
};
- clk_200mhz: dummy_clock_200mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- bootph-pre-ram;
- };
-
- clk_19_2mhz: dummy_clock_19_2mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <19200000>;
- bootph-pre-ram;
- };
-};
-
-&cbass_mcu_wakeup {
- mcu_secproxy: secproxy@28380000 {
- bootph-pre-ram;
- compatible = "ti,am654-secure-proxy";
- reg = <0x0 0x2a380000 0x0 0x80000>,
- <0x0 0x2a400000 0x0 0x80000>,
- <0x0 0x2a480000 0x0 0x80000>;
- reg-names = "rt", "scfg", "target_data";
- #mbox-cells = <1>;
- };
-
- sysctrler: sysctrler {
- bootph-pre-ram;
- compatible = "ti,am654-system-controller";
- mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
- mbox-names = "tx", "rx";
- };
-
- wkup_vtm0: wkup_vtm@42040000 {
- compatible = "ti,am654-vtm", "ti,j721e-avs";
- reg = <0x0 0x42040000 0x0 0x330>;
- power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
- #thermal-sensor-cells = <1>;
- };
-
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <3>;
ti,secure-host;
mbox-names = "rx", "tx";
- mboxes= <&mcu_secproxy 21>,
- <&mcu_secproxy 23>;
+ mboxes= <&secure_proxy_mcu 21>,
+ <&secure_proxy_mcu 23>;
bootph-pre-ram;
};
};
-&cbass_main {
- main_esm: esm@700000 {
- compatible = "ti,j721e-esm";
- reg = <0x0 0x700000 0x0 0x1000>;
- ti,esm-pins = <344>, <345>;
+&mcu_timer0 {
+ status = "okay";
+ bootph-pre-ram;
+};
+
+&secure_proxy_mcu {
+ bootph-pre-ram;
+ status = "okay";
+};
+
+&cbass_mcu_wakeup {
+ sysctrler: sysctrler {
bootph-pre-ram;
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
+ mbox-names = "tx", "rx";
};
};
&dmsc {
- mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
+ mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
};
-&wkup_pmx0 {
- wkup_uart0_pins_default: wkup_uart0_pins_default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
- J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
- >;
- };
-
- mcu_uart0_pins_default: mcu_uart0_pins_default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */
- J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */
- J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
- J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
- >;
- };
-
- wkup_i2c0_pins_default: wkup-i2c0-pins-default {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
- J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
- >;
- };
-
- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
- J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
- J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */
- J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */
- J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */
- J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */
- J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */
- J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */
- J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
- J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
- J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
- >;
- };
-
- mcu_i2c0_pins_default: mcu_i2c0_pins_default {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (J26) MCU_I2C0_SCL */
- J721E_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (H25) MCU_I2C0_SDA */
- >;
- };
+&mcu_ringacc {
+ ti,sci = <&dm_tifs>;
};
-&main_pmx0 {
- main_uart0_pins_default: main_uart0_pins_default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
- J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
- J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
- J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
- >;
- };
-
- main_usbss0_pins_default: main_usbss0_pins_default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
- J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
- >;
- };
-
- main_usbss1_pins_default: main-usbss1-pins-default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
- >;
- };
-
- main_mmc1_pins_default: main_mmc1_pins_default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
- J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
- J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
- J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
- J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
- J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
- J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
- J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
- >;
- };
-
- main_i2c0_pins_default: main-i2c0-pins-default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
- J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
- >;
- };
-
- main_i2c1_pins_default: main-i2c1-pins-default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
- J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
- >;
- };
-
- main_i2c2_pins_default: main-i2c2-pins-default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x158, PIN_INPUT_PULLUP, 2) /* (U23) RGMII5_TX_CTL.I2C2_SCL */
- J721E_IOPAD(0x15c, PIN_INPUT_PULLUP, 2) /* (U26) RGMII5_RX_CTL.I2C2_SDA */
- >;
- };
-
- main_i2c3_pins_default: main-i2c3-pins-default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
- J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
- >;
- };
-
- main_i2c5_pins_default: main-i2c5-pins-default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
- J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
- >;
- };
+&mcu_udmap {
+ ti,sci = <&dm_tifs>;
};
-&wkup_uart0 {
+&wkup_uart0_pins_default {
bootph-pre-ram;
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
- status = "okay";
};
-&mcu_uart0 {
- /delete-property/ power-domains;
- /delete-property/ clocks;
- /delete-property/ clock-names;
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_uart0_pins_default>;
- status = "okay";
- clock-frequency = <48000000>;
-};
-
-&main_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
- status = "okay";
- power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
-};
-
-&main_sdhci0 {
- status = "disabled";
-};
-
-&main_sdhci1 {
- /delete-property/ power-domains;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc1_pins_default>;
- clock-names = "clk_xin";
- clocks = <&clk_200mhz>;
- ti,driver-strength-ohm = <50>;
+&mcu_uart0_pins_default {
+ bootph-pre-ram;
};
&wkup_i2c0 {
@@ -423,6 +112,11 @@
bootph-pre-ram;
};
};
+
+ esm: esm {
+ compatible = "ti,tps659413-esm";
+ bootph-pre-ram;
+ };
};
};
@@ -431,217 +125,8 @@
bootph-pre-ram;
};
-&usbss0 {
- /delete-property/ power-domains;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- clocks = <&clk_19_2mhz>;
- clock-names = "usb2_refclk";
- pinctrl-names = "default";
- pinctrl-0 = <&main_usbss0_pins_default>;
- ti,vbus-divider;
-};
-
-&usbss1 {
- /delete-property/ power-domains;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- clocks = <&clk_19_2mhz>;
- clock-names = "usb2_refclk";
- pinctrl-names = "default";
- pinctrl-0 = <&main_usbss1_pins_default>;
-};
-
-&main_i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
-};
-
&ospi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
-
+ /* Address change for data region (32-bit) */
reg = <0x0 0x47040000 0x0 0x100>,
<0x0 0x50000000 0x0 0x8000000>;
-
- flash@0{
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <8>;
- spi-rx-bus-width = <8>;
- spi-max-frequency = <25000000>;
- cdns,tshsl-ns = <60>;
- cdns,tsd2d-ns = <60>;
- cdns,tchsh-ns = <60>;
- cdns,tslch-ns = <60>;
- cdns,read-delay = <4>;
- cdns,phy-mode;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-};
-
-&ospi1 {
- status = "disabled";
-};
-
-&mcu_ringacc {
- ti,sci = <&dm_tifs>;
-};
-
-&mcu_udmap {
- ti,sci = <&dm_tifs>;
-};
-
-&mailbox0_cluster0 {
- interrupts = <436>;
-
- mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-
- mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
- ti,mbox-rx = <2 0 0>;
- ti,mbox-tx = <3 0 0>;
- };
-};
-
-&mailbox0_cluster1 {
- interrupts = <432>;
-
- mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-
- mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
- ti,mbox-rx = <2 0 0>;
- ti,mbox-tx = <3 0 0>;
- };
-};
-
-&mailbox0_cluster2 {
- interrupts = <428>;
-
- mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-
- mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
- ti,mbox-rx = <2 0 0>;
- ti,mbox-tx = <3 0 0>;
- };
-};
-
-&mailbox0_cluster3 {
- interrupts = <424>;
-
- mbox_c66_0: mbox-c66-0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-
- mbox_c66_1: mbox-c66-1 {
- ti,mbox-rx = <2 0 0>;
- ti,mbox-tx = <3 0 0>;
- };
-};
-
-&mailbox0_cluster4 {
- interrupts = <420>;
-
- mbox_c71_0: mbox-c71-0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-};
-
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
-&mailbox0_cluster6 {
- status = "disabled";
-};
-
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
-&mailbox0_cluster8 {
- status = "disabled";
-};
-
-&mailbox0_cluster9 {
- status = "disabled";
-};
-
-&mailbox0_cluster10 {
- status = "disabled";
-};
-
-&mailbox0_cluster11 {
- status = "disabled";
-};
-
-&mcu_r5fss0_core0 {
- mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
- memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
- <&mcu_r5fss0_core0_memory_region>;
-};
-
-&mcu_r5fss0_core1 {
- mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
- memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
- <&mcu_r5fss0_core1_memory_region>;
-};
-
-&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
- memory-region = <&main_r5fss0_core0_dma_memory_region>,
- <&main_r5fss0_core0_memory_region>;
-};
-
-&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
- memory-region = <&main_r5fss0_core1_dma_memory_region>,
- <&main_r5fss0_core1_memory_region>;
-};
-
-&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
- memory-region = <&main_r5fss1_core0_dma_memory_region>,
- <&main_r5fss1_core0_memory_region>;
-};
-
-&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
- memory-region = <&main_r5fss1_core1_dma_memory_region>,
- <&main_r5fss1_core1_memory_region>;
-};
-
-&c66_0 {
- mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
- memory-region = <&c66_0_dma_memory_region>,
- <&c66_0_memory_region>;
-};
-
-&c66_1 {
- mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
- memory-region = <&c66_1_dma_memory_region>,
- <&c66_1_memory_region>;
-};
-
-&c71_0 {
- mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
- memory-region = <&c71_0_dma_memory_region>,
- <&c71_0_memory_region>;
-};
-
-/* EEPROM might be read before SYSFW is available */
-&wkup_i2c0 {
- /delete-property/ power-domains;
};
diff --git a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
index 205dacf..370fe51 100644
--- a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
@@ -3,283 +3,155 @@
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
-#include <dt-bindings/net/ti-dp83867.h>
#include "k3-j721e-binman.dtsi"
-/ {
- chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
-
- aliases {
- ethernet0 = &cpsw_port1;
- spi0 = &ospi0;
- remoteproc0 = &mcu_r5fss0_core0;
- remoteproc1 = &mcu_r5fss0_core1;
- remoteproc2 = &main_r5fss0_core0;
- remoteproc3 = &main_r5fss0_core1;
- remoteproc4 = &main_r5fss1_core0;
- remoteproc5 = &main_r5fss1_core1;
- remoteproc6 = &c66_0;
- remoteproc7 = &c66_1;
- remoteproc8 = &c71_0;
- i2c0 = &wkup_i2c0;
- i2c1 = &mcu_i2c0;
- i2c2 = &main_i2c0;
- mmc1 = &main_sdhci1; /* SD Card */
- };
+&cbass_main {
+ bootph-all;
};
-&cbass_main{
- bootph-pre-ram;
-
- main_navss: bus@30000000 {
- bootph-pre-ram;
- };
+&main_navss {
+ bootph-all;
};
&cbass_mcu_wakeup {
- bootph-pre-ram;
-
- timer1: timer@40400000 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x40400000 0x0 0x80>;
- ti,timer-alwon;
- clock-frequency = <25000000>;
- bootph-pre-ram;
- };
-
- mcu_navss: bus@28380000 {
- bootph-pre-ram;
-
- ringacc@2b800000 {
- reg = <0x0 0x2b800000 0x0 0x400000>,
- <0x0 0x2b000000 0x0 0x400000>,
- <0x0 0x28590000 0x0 0x100>,
- <0x0 0x2a500000 0x0 0x40000>,
- <0x0 0x28440000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- bootph-pre-ram;
- };
-
- dma-controller@285c0000 {
- reg = <0x0 0x285c0000 0x0 0x100>,
- <0x0 0x284c0000 0x0 0x4000>,
- <0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x284a0000 0x0 0x4000>,
- <0x0 0x2aa00000 0x0 0x40000>,
- <0x0 0x28400000 0x0 0x2000>;
- reg-names = "gcfg", "rchan", "rchanrt", "tchan",
- "tchanrt", "rflow";
- bootph-pre-ram;
- };
- };
+ bootph-all;
chipid@43000014 {
- bootph-pre-ram;
+ bootph-all;
};
};
+&mcu_navss {
+ bootph-all;
+};
+
+&mcu_ringacc {
+ bootph-all;
+};
+
+&mcu_udmap {
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x284c0000 0x0 0x4000>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x284a0000 0x0 0x4000>,
+ <0x0 0x2aa00000 0x0 0x40000>,
+ <0x0 0x28400000 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
+ bootph-all;
+};
+
&secure_proxy_main {
- bootph-pre-ram;
+ bootph-all;
};
&dmsc {
- bootph-pre-ram;
+ bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- bootph-pre-ram;
+ bootph-all;
};
};
&k3_pds {
- bootph-pre-ram;
+ bootph-all;
};
&k3_clks {
- bootph-pre-ram;
+ bootph-all;
};
&k3_reset {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_pmx0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_pmx0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_uart0 {
- bootph-pre-ram;
+ bootph-all;
};
&mcu_uart0 {
- bootph-pre-ram;
-};
-
-&main_sdhci0 {
- status = "disabled";
+ bootph-all;
};
&main_sdhci1 {
- bootph-pre-ram;
+ bootph-all;
};
-&wiz3_pll1_refclk {
- assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>;
- assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>;
+&main_uart0_pins_default {
+ bootph-all;
};
&main_usbss0_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&usbss0 {
- bootph-pre-ram;
+ bootph-all;
};
&usb0 {
dr_mode = "host";
- bootph-pre-ram;
-};
-
-&wiz2_pll1_refclk {
- assigned-clocks = <&wiz2_pll1_refclk>, <&wiz2_pll0_refclk>;
- assigned-clock-parents = <&k3_clks 294 0>, <&k3_clks 294 11>;
+ bootph-all;
};
&main_usbss1_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&usbss1 {
- bootph-pre-ram;
+ bootph-all;
};
&usb1 {
dr_mode = "host";
- bootph-pre-ram;
-};
-
-&mcu_cpsw {
- reg = <0x0 0x46000000 0x0 0x200000>,
- <0x0 0x40f00200 0x0 0x2>;
- reg-names = "cpsw_nuss", "mac_efuse";
- /delete-property/ ranges;
-
- cpsw-phy-sel@40f04040 {
- compatible = "ti,am654-cpsw-phy-sel";
- reg= <0x0 0x40f04040 0x0 0x4>;
- reg-names = "gmii-sel";
- };
+ bootph-all;
};
&main_mmc1_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_i2c0_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_i2c0 {
- bootph-pre-ram;
+ bootph-all;
};
-&mcu_i2c0 {
- bootph-pre-ram;
-};
-
-&mcu_i2c1 {
- status = "disabled";
-};
-
-&main_i2c0 {
- status = "disabled";
-};
-
-&main_i2c1 {
- status = "disabled";
-};
-
-&main_i2c2 {
- status = "disabled";
-};
-
-&main_i2c3 {
- status = "disabled";
-};
-
-&main_i2c4 {
- status = "disabled";
-};
-
-&main_i2c5 {
- status = "disabled";
-};
-
-&main_i2c6 {
- status = "disabled";
-};
-
-&mcu_i2c0_pins_default {
- bootph-pre-ram;
+&wkup_uart0 {
+ bootph-all;
+ status = "okay";
};
&mcu_fss0_ospi0_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&fss {
- bootph-pre-ram;
+ bootph-all;
};
-&hbmc {
- status = "disabled";
+&main_esm {
+ bootph-all;
};
&ospi0 {
- bootph-pre-ram;
+ bootph-all;
flash@0 {
- bootph-pre-ram;
+ bootph-all;
partition@3fc0000 {
- label = "ospi.phypattern";
- reg = <0x3fc0000 0x40000>;
- bootph-pre-ram;
+ bootph-all;
};
};
};
-
-&serdes_ln_ctrl {
- u-boot,mux-autoprobe;
-};
-
-&usb_serdes_mux {
- u-boot,mux-autoprobe;
-};
-
-&pcie0_rc {
- status = "disabled";
-};
-
-&pcie1_rc {
- status = "disabled";
-};
-
-&pcie0_ep {
- status = "disabled";
-};
-
-&pcie1_ep {
- status = "disabled";
-};
-
-&dss {
- status = "disabled";
-};
diff --git a/arch/arm/dts/k3-j721e-sk.dts b/arch/arm/dts/k3-j721e-sk.dts
index 4443cd0..42fe8ee 100644
--- a/arch/arm/dts/k3-j721e-sk.dts
+++ b/arch/arm/dts/k3-j721e-sk.dts
@@ -1,6 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM
*/
/dts-v1/;
@@ -12,11 +14,19 @@
/ {
compatible = "ti,j721e-sk", "ti,j721e";
- model = "Texas Instruments J721E SK A72";
+ model = "Texas Instruments J721E SK";
+
+ aliases {
+ serial0 = &wkup_uart0;
+ serial1 = &mcu_uart0;
+ serial2 = &main_uart0;
+ serial3 = &main_uart1;
+ ethernet0 = &cpsw_port1;
+ mmc1 = &main_sdhci1;
+ };
chosen {
stdout-path = "serial2:115200n8";
- bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
memory@80000000 {
@@ -195,14 +205,91 @@
regulator-max-microvolt = <3300000>;
regulator-boot-on;
vin-supply = <&vsys_3v3>;
- gpios = <&wkup_gpio0 9 GPIO_ACTIVE_LOW>;
- states = <3300000 0x0>,
- <1800000 0x1>;
+ gpios = <&wkup_gpio0 9 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
+ };
+
+ dp_pwr_3v3: fixedregulator-dp-prw {
+ compatible = "regulator-fixed";
+ regulator-name = "dp-pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp_pwr_en_pins_default>;
+ gpio = <&main_gpio0 111 0>; /* DP0_3V3 _EN */
+ enable-active-high;
+ };
+
+ dp0: connector {
+ compatible = "dp-connector";
+ label = "DP0";
+ type = "full-size";
+ dp-pwr-supply = <&dp_pwr_3v3>;
+
+ port {
+ dp_connector_in: endpoint {
+ remote-endpoint = <&dp0_out>;
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_hpd_pins_default>;
+
+ ddc-i2c-bus = <&main_i2c1>;
+
+ /* HDMI_HPD */
+ hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>;
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tfp410_out>;
+ };
+ };
+ };
+
+ dvi-bridge {
+ compatible = "ti,tfp410";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pdn_pins_default>;
+
+ powerdown-gpios = <&main_gpio0 127 GPIO_ACTIVE_LOW>;
+ ti,deskew = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tfp410_in: endpoint {
+ remote-endpoint = <&dpi1_out>;
+ pclk-sample = <1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tfp410_out: endpoint {
+ remote-endpoint =
+ <&hdmi_connector_in>;
+ };
+ };
+ };
};
};
&main_pmx0 {
- main_mmc1_pins_default: main-mmc1-pins-default {
+ main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
@@ -215,7 +302,7 @@
>;
};
- main_uart0_pins_default: main-uart0-pins-default {
+ main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
@@ -224,50 +311,155 @@
>;
};
- main_i2c0_pins_default: main-i2c0-pins-default {
+ main_uart1_pins_default: main-uart1-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */
+ J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */
+ >;
+ };
+
+ main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
>;
};
- main_i2c1_pins_default: main-i2c1-pins-default {
+ main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
>;
};
- main_i2c3_pins_default: main-i2c3-pins-default {
+ main_i2c3_pins_default: main-i2c3-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
>;
};
- mcu_i2c0_pins_default: mcu-i2c0-pins-default {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (J26) MCU_I2C0_SCL */
- J721E_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (H25) MCU_I2C0_SDA */
- >;
- };
-
- main_usbss0_pins_default: main-usbss0-pins-default {
+ main_usbss0_pins_default: main-usbss0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
>;
};
- main_usbss1_pins_default: main-usbss1-pins-default {
+ main_usbss1_pins_default: main-usbss1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
>;
};
+
+ dp0_pins_default: dp0-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
+ >;
+ };
+
+ dp_pwr_en_pins_default: dp-pwr-en-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */
+ >;
+ };
+
+ dss_vout0_pins_default: dss-vout0-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */
+ J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */
+ J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */
+ J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */
+ J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */
+ J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */
+ J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */
+ J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */
+ J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */
+ J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */
+ J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */
+ J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */
+ J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */
+ J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */
+ J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */
+ J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */
+ J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */
+ J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */
+ J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */
+ J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */
+ J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */
+ J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */
+ J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */
+ J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */
+ J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */
+ J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */
+ J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */
+ J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */
+ >;
+ };
+
+ hdmi_hpd_pins_default: hdmi-hpd-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */
+ >;
+ };
+
+ hdmi_pdn_pins_default: hdmi-pdn-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */
+ >;
+ };
+
+ /* Reset for M.2 E Key slot on PCIe0 */
+ ekey_reset_pins_default: ekey-reset-pns-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */
+ >;
+ };
+
+ main_i2c5_pins_default: main-i2c5-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
+ J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
+ >;
+ };
+
+ rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */
+ J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */
+ J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
+ J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */
+ J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
+ J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
+ J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
+ J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */
+ J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */
+ J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */
+ J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */
+ J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */
+ J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */
+ J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */
+ J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
+ J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */
+ J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
+ J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */
+ J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */
+ J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */
+ J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */
+ J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */
+ J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */
+ >;
+ };
+
+ rpi_header_gpio1_pins_default: rpi-header-gpio1-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */
+ >;
+ };
};
&wkup_pmx0 {
- mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+ mcu_cpsw_pins_default: mcu-cpsw-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
@@ -284,14 +476,14 @@
>;
};
- mcu_mdio_pins_default: mcu-mdio1-pins-default {
+ mcu_mdio_pins_default: mcu-mdio1-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
>;
};
- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
@@ -307,80 +499,92 @@
>;
};
- vdd_mmc1_en_pins_default: vdd-mmc1-en-pins-default {
+ vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */
>;
};
- vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
+ vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */
>;
};
- wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ wkup_uart0_pins_default: wkup-uart0-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
+ J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
+ >;
+ };
+
+ mcu_uart0_pins_default: mcu-uart0-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */
+ J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */
+ J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
+ J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
+ >;
+ };
+
+ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
>;
};
+
+ /* Reset for M.2 M Key slot on PCIe1 */
+ mkey_reset_pins_default: mkey-reset-pns-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */
+ >;
+ };
};
&wkup_uart0 {
/* Wakeup UART is used by System firmware */
status = "reserved";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+};
+
+&wkup_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ eeprom@51 {
+ /* AT24C512C-MAHM-T */
+ compatible = "atmel,24c512";
+ reg = <0x51>;
+ };
+};
+
+&mcu_uart0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_uart0_pins_default>;
};
&main_uart0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
/* Shared with ATF on this platform */
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
-&main_uart2 {
- /* Brought out on RPi header */
- status = "disabled";
-};
-
-&main_uart3 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_uart5 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_uart6 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_uart7 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_uart8 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_uart9 {
- /* Brought out on M.2 E Key */
- status = "disabled";
-};
-
-&main_sdhci0 {
- /* Unused */
- status = "disabled";
+&main_uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
};
&main_sdhci1 {
/* SD Card */
+ status = "okay";
vmmc-supply = <&vdd_mmc1>;
vqmmc-supply = <&vdd_sd_dv_alt>;
pinctrl-names = "default";
@@ -389,16 +593,12 @@
disable-wp;
};
-&main_sdhci2 {
- /* Unused */
- status = "disabled";
-};
-
&ospi0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
- flash@0{
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
@@ -409,57 +609,143 @@
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
- cdns,phy-mode;
- cdns,phy-tx-start = <18>;
- #address-cells = <1>;
- #size-cells = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ospi.tiboot3";
+ reg = <0x0 0x80000>;
+ };
+
+ partition@80000 {
+ label = "ospi.tispl";
+ reg = <0x80000 0x200000>;
+ };
+
+ partition@280000 {
+ label = "ospi.u-boot";
+ reg = <0x280000 0x400000>;
+ };
+
+ partition@680000 {
+ label = "ospi.env";
+ reg = <0x680000 0x40000>;
+ };
+
+ partition@6c0000 {
+ label = "ospi.sysfw";
+ reg = <0x6c0000 0x100000>;
+ };
+
+ partition@7c0000 {
+ label = "ospi.env.backup";
+ reg = <0x7c0000 0x40000>;
+ };
+
+ partition@800000 {
+ label = "ospi.rootfs";
+ reg = <0x800000 0x37c0000>;
+ };
+
+ partition@3fc0000 {
+ label = "ospi.phypattern";
+ reg = <0x3fc0000 0x40000>;
+ };
+ };
};
};
-&ospi1 {
- /* Unused */
- status = "disabled";
-};
-
&main_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
+
+ i2c-mux@71 {
+ compatible = "nxp,pca9543";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x71>;
+
+ /* PCIe1 M.2 M Key I2C */
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ /* PCIe0 M.2 E Key I2C */
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
};
&main_i2c1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
- clock-frequency = <400000>;
+ /* i2c1 is used for DVI DDC, so we need to use 100kHz */
+ clock-frequency = <100000>;
};
&main_i2c3 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c3_pins_default>;
clock-frequency = <400000>;
-};
-&main_i2c4 {
- /* Unused */
- status = "disabled";
+ i2c-mux@70 {
+ compatible = "nxp,pca9543";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+
+ /* CSI0 I2C */
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ /* CSI1 I2C */
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
};
&main_i2c5 {
/* Brought out on RPi Header */
- status = "disabled";
-};
-
-&main_i2c6 {
- /* Unused */
- status = "disabled";
-};
-
-&mcu_i2c0 {
+ status = "okay";
pinctrl-names = "default";
- pinctrl-0 = <&mcu_i2c0_pins_default>;
+ pinctrl-0 = <&main_i2c5_pins_default>;
clock-frequency = <400000>;
};
+&main_gpio0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rpi_header_gpio0_pins_default>;
+};
+
+&main_gpio1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rpi_header_gpio1_pins_default>;
+};
+
+&wkup_gpio0 {
+ status = "okay";
+};
+
&usb_serdes_mux {
idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
};
@@ -479,7 +765,7 @@
};
&serdes3 {
- serdes3_usb_link: link@0 {
+ serdes3_usb_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
@@ -488,6 +774,24 @@
};
};
+&serdes4 {
+ torrent_phy_dp: phy@0 {
+ reg = <0>;
+ resets = <&serdes_wiz4 1>;
+ cdns,phy-type = <PHY_TYPE_DP>;
+ cdns,num-lanes = <4>;
+ cdns,max-bit-rate = <5400>;
+ #phy-cells = <0>;
+ };
+};
+
+&mhdp {
+ phys = <&torrent_phy_dp>;
+ phy-names = "dpphy";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp0_pins_default>;
+};
+
&usbss0 {
pinctrl-names = "default";
pinctrl-0 = <&main_usbss0_pins_default>;
@@ -502,7 +806,7 @@
};
&serdes2 {
- serdes2_usb_link: link@1 {
+ serdes2_usb_link: phy@1 {
reg = <1>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
@@ -524,19 +828,9 @@
phy-names = "cdns3,usb3-phy";
};
-&tscadc0 {
- /* Unused */
- status = "disabled";
-};
-
-&tscadc1 {
- /* Unused */
- status = "disabled";
-};
-
&mcu_cpsw {
pinctrl-names = "default";
- pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+ pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
};
&davinci_mdio {
@@ -553,6 +847,9 @@
};
&dss {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dss_vout0_pins_default>;
+
assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */
<&k3_clks 152 4>, /* VP 2 pixel clock */
<&k3_clks 152 9>, /* VP 3 pixel clock */
@@ -563,87 +860,94 @@
<&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */
};
-&mcasp0 {
- /* Unused */
- status = "disabled";
+&dss_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dpi0_out: endpoint {
+ remote-endpoint = <&dp0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ dpi1_out: endpoint {
+ remote-endpoint = <&tfp410_in>;
+ };
+ };
};
-&mcasp1 {
- /* Unused */
- status = "disabled";
+&dp0_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ dp0_out: endpoint {
+ remote-endpoint = <&dp_connector_in>;
+ };
+ };
};
-&mcasp2 {
- /* Unused */
- status = "disabled";
+&serdes0 {
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
};
-&mcasp3 {
- /* Unused */
- status = "disabled";
+&serdes1 {
+ serdes1_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
+ };
};
-&mcasp4 {
- /* Unused */
- status = "disabled";
+&pcie0_rc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ekey_reset_pins_default>;
+ reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>;
+
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
};
-&mcasp5 {
- /* Unused */
- status = "disabled";
+&pcie1_rc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mkey_reset_pins_default>;
+ reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>;
+
+ phys = <&serdes1_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
};
-&mcasp6 {
- /* Brought out on RPi header */
- status = "disabled";
-};
-
-&mcasp7 {
- /* Unused */
- status = "disabled";
-};
-
-&mcasp8 {
- /* Unused */
- status = "disabled";
-};
-
-&mcasp9 {
- /* Unused */
- status = "disabled";
-};
-
-&mcasp10 {
- /* Unused */
- status = "disabled";
-};
-
-&mcasp11 {
- /* Brought out on M.2 E Key */
- status = "disabled";
-};
-
-&pcie2_rc {
- /* Unused */
- status = "disabled";
-};
-
-&pcie2_ep {
- /* Unused */
- status = "disabled";
-};
-
-&pcie3_rc {
- /* Unused */
- status = "disabled";
-};
-
-&pcie3_ep {
- /* Unused */
+&ufs_wrapper {
status = "disabled";
};
&mailbox0_cluster0 {
+ status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
@@ -658,6 +962,7 @@
};
&mailbox0_cluster1 {
+ status = "okay";
interrupts = <432>;
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
@@ -672,6 +977,7 @@
};
&mailbox0_cluster2 {
+ status = "okay";
interrupts = <428>;
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
@@ -686,6 +992,7 @@
};
&mailbox0_cluster3 {
+ status = "okay";
interrupts = <424>;
mbox_c66_0: mbox-c66-0 {
@@ -700,6 +1007,7 @@
};
&mailbox0_cluster4 {
+ status = "okay";
interrupts = <420>;
mbox_c71_0: mbox-c71-0 {
@@ -708,84 +1016,59 @@
};
};
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
-&mailbox0_cluster6 {
- status = "disabled";
-};
-
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
-&mailbox0_cluster8 {
- status = "disabled";
-};
-
-&mailbox0_cluster9 {
- status = "disabled";
-};
-
-&mailbox0_cluster10 {
- status = "disabled";
-};
-
-&mailbox0_cluster11 {
- status = "disabled";
-};
-
&mcu_r5fss0_core0 {
- mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
- mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&c66_0 {
- mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+ status = "okay";
+ mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
memory-region = <&c66_0_dma_memory_region>,
<&c66_0_memory_region>;
};
&c66_1 {
- mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+ status = "okay";
+ mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
memory-region = <&c66_1_dma_memory_region>,
<&c66_1_memory_region>;
};
&c71_0 {
- mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+ status = "okay";
+ mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};
diff --git a/arch/arm/dts/k3-j721e-som-p0.dtsi b/arch/arm/dts/k3-j721e-som-p0.dtsi
index a725435..7f0686c2 100644
--- a/arch/arm/dts/k3-j721e-som-p0.dtsi
+++ b/arch/arm/dts/k3-j721e-som-p0.dtsi
@@ -1,6 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Product Link: https://www.ti.com/tool/J721EXSOMXEVM
*/
/dts-v1/;
@@ -143,33 +145,14 @@
};
&wkup_pmx0 {
- wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
>;
};
- mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
- J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
- J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
- J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
- J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
- J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
- J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
- J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
- J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
- J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
- J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
- J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
- J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
- J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
- >;
- };
-
- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
@@ -184,26 +167,46 @@
J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
>;
};
+
+ mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CK */
+ J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CKn */
+ J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CSn0 */
+ J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* MCU_HYPERBUS0_CSn1 */
+ J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_RESETn */
+ J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* MCU_HYPERBUS0_RWDS */
+ J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ0 */
+ J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ1 */
+ J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ2 */
+ J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ3 */
+ J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ4 */
+ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ5 */
+ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ6 */
+ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ7 */
+ >;
+ };
};
-&hbmc {
- status = "disabled";
+&wkup_i2c0 {
+ status = "okay";
pinctrl-names = "default";
- pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
- ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */
- <0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */
+ pinctrl-0 = <&wkup_i2c0_pins_default>;
+ clock-frequency = <400000>;
- flash@0,0 {
- compatible = "cypress,hyperflash", "cfi-flash";
- reg = <0x0 0x0 0x4000000>;
+ eeprom@50 {
+ /* CAV24C256WE-GT3 */
+ compatible = "atmel,24c256";
+ reg = <0x50>;
};
};
&ospi0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
- flash@0{
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
@@ -214,12 +217,109 @@
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ospi.tiboot3";
+ reg = <0x0 0x80000>;
+ };
+
+ partition@80000 {
+ label = "ospi.tispl";
+ reg = <0x80000 0x200000>;
+ };
+
+ partition@280000 {
+ label = "ospi.u-boot";
+ reg = <0x280000 0x400000>;
+ };
+
+ partition@680000 {
+ label = "ospi.env";
+ reg = <0x680000 0x20000>;
+ };
+
+ partition@6a0000 {
+ label = "ospi.env.backup";
+ reg = <0x6a0000 0x20000>;
+ };
+
+ partition@6c0000 {
+ label = "ospi.sysfw";
+ reg = <0x6c0000 0x100000>;
+ };
+
+ partition@800000 {
+ label = "ospi.rootfs";
+ reg = <0x800000 0x37c0000>;
+ };
+
+ partition@3fe0000 {
+ label = "ospi.phypattern";
+ reg = <0x3fe0000 0x20000>;
+ };
+ };
+ };
+};
+
+&hbmc {
+ /* OSPI and HBMC are muxed inside FSS, Bootloader will enable
+ * appropriate node based on board detection
+ */
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
+ ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
+ <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
+
+ flash@0,0 {
+ compatible = "cypress,hyperflash", "cfi-flash";
+ reg = <0x00 0x00 0x4000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "hbmc.tiboot3";
+ reg = <0x0 0x80000>;
+ };
+
+ partition@80000 {
+ label = "hbmc.tispl";
+ reg = <0x80000 0x200000>;
+ };
+
+ partition@280000 {
+ label = "hbmc.u-boot";
+ reg = <0x280000 0x400000>;
+ };
+
+ partition@680000 {
+ label = "hbmc.env";
+ reg = <0x680000 0x40000>;
+ };
+
+ partition@6c0000 {
+ label = "hbmc.sysfw";
+ reg = <0x6c0000 0x100000>;
+ };
+
+ partition@800000 {
+ label = "hbmc.rootfs";
+ reg = <0x800000 0x3800000>;
+ };
+ };
};
};
&mailbox0_cluster0 {
+ status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
@@ -234,6 +334,7 @@
};
&mailbox0_cluster1 {
+ status = "okay";
interrupts = <432>;
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
@@ -248,6 +349,7 @@
};
&mailbox0_cluster2 {
+ status = "okay";
interrupts = <428>;
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
@@ -262,6 +364,7 @@
};
&mailbox0_cluster3 {
+ status = "okay";
interrupts = <424>;
mbox_c66_0: mbox-c66-0 {
@@ -276,6 +379,7 @@
};
&mailbox0_cluster4 {
+ status = "okay";
interrupts = <420>;
mbox_c71_0: mbox-c71-0 {
@@ -284,84 +388,59 @@
};
};
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
-&mailbox0_cluster6 {
- status = "disabled";
-};
-
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
-&mailbox0_cluster8 {
- status = "disabled";
-};
-
-&mailbox0_cluster9 {
- status = "disabled";
-};
-
-&mailbox0_cluster10 {
- status = "disabled";
-};
-
-&mailbox0_cluster11 {
- status = "disabled";
-};
-
&mcu_r5fss0_core0 {
- mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
- mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&c66_0 {
- mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+ status = "okay";
+ mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
memory-region = <&c66_0_dma_memory_region>,
<&c66_0_memory_region>;
};
&c66_1 {
- mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+ status = "okay";
+ mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
memory-region = <&c66_1_dma_memory_region>,
<&c66_1_memory_region>;
};
&c71_0 {
- mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+ status = "okay";
+ mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};
diff --git a/arch/arm/dts/k3-j721e-thermal.dtsi b/arch/arm/dts/k3-j721e-thermal.dtsi
new file mode 100644
index 0000000..c252327
--- /dev/null
+++ b/arch/arm/dts/k3-j721e-thermal.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+ wkup_thermal: wkup-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 0>;
+
+ trips {
+ wkup_crit: wkup-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ mpu_thermal: mpu-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 1>;
+
+ trips {
+ mpu_crit: mpu-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ c7x_thermal: c7x-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 2>;
+
+ trips {
+ c7x_crit: c7x-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ gpu_thermal: gpu-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 3>;
+
+ trips {
+ gpu_crit: gpu-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ r5f_thermal: r5f-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 4>;
+
+ trips {
+ r5f_crit: r5f-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-j721e.dtsi b/arch/arm/dts/k3-j721e.dtsi
index f0587fd..a200810 100644
--- a/arch/arm/dts/k3-j721e.dtsi
+++ b/arch/arm/dts/k3-j721e.dtsi
@@ -7,9 +7,10 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
+#include "k3-pinctrl.h"
+
/ {
model = "Texas Instruments K3 J721E SoC";
compatible = "ti,j721e";
@@ -17,22 +18,6 @@
#address-cells = <2>;
#size-cells = <2>;
- aliases {
- serial0 = &wkup_uart0;
- serial1 = &mcu_uart0;
- serial2 = &main_uart0;
- serial3 = &main_uart1;
- serial4 = &main_uart2;
- serial5 = &main_uart3;
- serial6 = &main_uart4;
- serial7 = &main_uart5;
- serial8 = &main_uart6;
- serial9 = &main_uart7;
- serial10 = &main_uart8;
- serial11 = &main_uart9;
- ethernet0 = &cpsw_port1;
- };
-
chosen { };
cpus {
@@ -61,7 +46,7 @@
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
- d-cache-sets = <128>;
+ d-cache-sets = <256>;
next-level-cache = <&L2_0>;
};
@@ -75,7 +60,7 @@
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
- d-cache-sets = <128>;
+ d-cache-sets = <256>;
next-level-cache = <&L2_0>;
};
};
@@ -83,15 +68,17 @@
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
- cache-sets = <2048>;
+ cache-sets = <1024>;
next-level-cache = <&msmc_l3>;
};
msmc_l3: l3-cache0 {
compatible = "cache";
cache-level = <3>;
+ cache-unified;
};
firmware {
@@ -126,16 +113,19 @@
#size-cells = <2>;
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
+ <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
<0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */
<0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */
<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
+ <0x00 0x0c000000 0x00 0x0c000000 0x00 0x0d000000>, /* CPSW9G */
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/
<0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/
<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
<0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
+ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
<0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */
<0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */
<0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
@@ -177,6 +167,8 @@
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
};
};
+
+ #include "k3-j721e-thermal.dtsi"
};
/* Now include the peripherals for each bus segments */
diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
index f940ffe..a3ebf59 100644
--- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
@@ -1,68 +1,36 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-j721s2-binman.dtsi"
-/ {
- chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
-
- aliases {
- serial0 = &wkup_uart0;
- serial1 = &mcu_uart0;
- serial2 = &main_uart8;
- i2c0 = &wkup_i2c0;
- i2c1 = &mcu_i2c0;
- i2c2 = &mcu_i2c1;
- i2c3 = &main_i2c0;
- ethernet0 = &cpsw_port1;
- };
-};
-
&wkup_i2c0 {
- bootph-pre-ram;
+ bootph-all;
};
&cbass_main {
- bootph-pre-ram;
+ bootph-all;
};
&main_navss {
- bootph-pre-ram;
+ bootph-all;
};
&cbass_mcu_wakeup {
- bootph-pre-ram;
-
- timer1: timer@40400000 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x40400000 0x0 0x80>;
- ti,timer-alwon;
- clock-frequency = <250000000>;
- bootph-pre-ram;
- };
+ bootph-all;
chipid@43000014 {
- bootph-pre-ram;
+ bootph-all;
};
};
&mcu_navss {
- bootph-pre-ram;
+ bootph-all;
};
&mcu_ringacc {
- reg = <0x0 0x2b800000 0x0 0x400000>,
- <0x0 0x2b000000 0x0 0x400000>,
- <0x0 0x28590000 0x0 0x100>,
- <0x0 0x2a500000 0x0 0x40000>,
- <0x0 0x28440000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- bootph-pre-ram;
+ bootph-all;
};
&mcu_udmap {
@@ -74,78 +42,86 @@
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
"tchanrt", "rflow";
- bootph-pre-ram;
+ bootph-all;
};
&secure_proxy_main {
- bootph-pre-ram;
+ bootph-all;
};
&sms {
- bootph-pre-ram;
+ bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- bootph-pre-ram;
+ bootph-all;
};
};
&main_pmx0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_uart8_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&main_mmc1_pins_default {
- bootph-pre-ram;
+ bootph-all;
+};
+
+&main_usbss0_pins_default {
+ bootph-all;
};
&wkup_pmx0 {
- bootph-pre-ram;
+ bootph-all;
};
&k3_pds {
- bootph-pre-ram;
+ bootph-all;
};
&k3_clks {
- bootph-pre-ram;
+ bootph-all;
};
&k3_reset {
- bootph-pre-ram;
+ bootph-all;
};
&main_uart8 {
- bootph-pre-ram;
+ bootph-all;
};
&mcu_uart0 {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_uart0 {
- bootph-pre-ram;
-};
-
-&mcu_cpsw {
- reg = <0x0 0x46000000 0x0 0x200000>,
- <0x0 0x40f00200 0x0 0x8>;
- reg-names = "cpsw_nuss", "mac_efuse";
- /delete-property/ ranges;
-
- cpsw-phy-sel@40f04040 {
- compatible = "ti,am654-cpsw-phy-sel";
- reg= <0x0 0x40f04040 0x0 0x4>;
- reg-names = "gmii-sel";
- };
+ bootph-all;
};
&main_sdhci0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_sdhci1 {
- bootph-pre-ram;
+ bootph-all;
+};
+
+&ospi0 {
+ status = "disabled";
+};
+
+&ospi1 {
+ status = "disabled";
+};
+
+&usbss0 {
+ bootph-all;
+};
+
+&usb0 {
+ dr_mode = "peripheral";
+ bootph-all;
};
diff --git a/arch/arm/dts/k3-j721s2-common-proc-board.dts b/arch/arm/dts/k3-j721s2-common-proc-board.dts
index 3bba647..c6b85bb 100644
--- a/arch/arm/dts/k3-j721s2-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721s2-common-proc-board.dts
@@ -2,13 +2,17 @@
/*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*
- * Link to Common Processor Board: https://www.ti.com/lit/zip/sprr439
+ * Common Processor Board: https://www.ti.com/tool/J721EXCPXEVM
*/
/dts-v1/;
#include "k3-j721s2-som-p0.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy.h>
+
+#include "k3-serdes.h"
/ {
compatible = "ti,j721s2-evm", "ti,j721s2";
@@ -16,16 +20,18 @@
chosen {
stdout-path = "serial2:115200n8";
- bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x2880000";
};
aliases {
+ serial1 = &mcu_uart0;
serial2 = &main_uart8;
mmc0 = &main_sdhci0;
mmc1 = &main_sdhci1;
can0 = &main_mcan16;
can1 = &mcu_mcan0;
can2 = &mcu_mcan1;
+ can3 = &main_mcan3;
+ can4 = &main_mcan5;
};
evm_12v0: fixedregulator-evm12v0 {
@@ -106,10 +112,26 @@
standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
};
+ transceiver3: can-phy3 {
+ compatible = "ti,tcan1043";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
+ enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
+ mux-states = <&mux0 1>;
+ };
+
+ transceiver4: can-phy4 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ standby-gpios = <&exp_som 7 GPIO_ACTIVE_HIGH>;
+ mux-states = <&mux1 1>;
+ };
};
&main_pmx0 {
- main_uart8_pins_default: main-uart8-pins-default {
+ main_uart8_pins_default: main-uart8-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */
J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
@@ -118,14 +140,14 @@
>;
};
- main_i2c3_pins_default: main-i2c3-pins-default {
+ main_i2c3_pins_default: main-i2c3-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x064, PIN_INPUT_PULLUP, 13) /* (W28) MCAN0_TX.I2C3_SCL */
J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */
>;
};
- main_mmc1_pins_default: main-mmc1-pins-default {
+ main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
@@ -138,129 +160,173 @@
>;
};
- vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
+ vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */
>;
};
-};
-&wkup_pmx0 {
- mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+ main_usbss0_pins_default: main-usbss0-default-pins {
pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
- J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
- J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
- J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
- J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
- J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
- J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
- J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
- J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
- J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
- J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
- J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
+ J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
>;
};
- mcu_mdio_pins_default: mcu-mdio-pins-default {
+ main_mcan3_pins_default: main-mcan3-default-pins {
pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
- J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
+ J721S2_IOPAD(0x080, PIN_INPUT, 0) /* (U26) MCASP0_AXR4.MCAN3_RX */
+ J721S2_IOPAD(0x07c, PIN_OUTPUT, 0) /* (T27) MCASP0_AXR3.MCAN3_TX */
>;
};
- mcu_mcan0_pins_default: mcu-mcan0-pins-default {
+ main_mcan5_pins_default: main-mcan5-default-pins {
pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */
- J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
- >;
- };
-
- mcu_mcan1_pins_default: mcu-mcan1-pins-default {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
- J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX */
- >;
- };
-
- mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x0c0, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */
- J721S2_WKUP_IOPAD(0x0a8, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */
- >;
- };
-
- mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */
+ J721S2_IOPAD(0x03c, PIN_INPUT, 0) /* (U27) MCASP0_AFSX.MCAN5_RX */
+ J721S2_IOPAD(0x038, PIN_OUTPUT, 0) /* (AB28) MCASP0_ACLKX.MCAN5_TX */
>;
};
};
-&main_gpio2 {
- status = "disabled";
+&wkup_pmx2 {
+ wkup_uart0_pins_default: wkup-uart0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
+ J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
+ J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
+ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
+ >;
+ };
+
+ mcu_uart0_pins_default: mcu-uart0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */
+ J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */
+ J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
+ J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
+ >;
+ };
+
+ mcu_cpsw_pins_default: mcu-cpsw-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
+ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
+ J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
+ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
+ J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
+ J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
+ J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
+ J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
+ J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
+ J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
+ J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
+ J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
+ >;
+ };
+
+ mcu_mdio_pins_default: mcu-mdio-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
+ J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
+ >;
+ };
+
+ mcu_mcan0_pins_default: mcu-mcan0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */
+ J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
+ >;
+ };
+
+ mcu_mcan1_pins_default: mcu-mcan1-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
+ J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /*(C23) WKUP_GPIO0_4.MCU_MCAN1_TX */
+ >;
+ };
+
+ mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */
+ J721S2_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */
+ >;
+ };
+
+ mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */
+ >;
+ };
+
+ mcu_adc0_pins_default: mcu-adc0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (L25) MCU_ADC0_AIN0 */
+ J721S2_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN1 */
+ J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (M24) MCU_ADC0_AIN2 */
+ J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (L24) MCU_ADC0_AIN3 */
+ J721S2_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (L27) MCU_ADC0_AIN4 */
+ J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN5 */
+ J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (M27) MCU_ADC0_AIN6 */
+ J721S2_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (M26) MCU_ADC0_AIN7 */
+ >;
+ };
+
+ mcu_adc1_pins_default: mcu-adc1-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (P25) MCU_ADC1_AIN0 */
+ J721S2_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (R25) MCU_ADC1_AIN1 */
+ J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (P28) MCU_ADC1_AIN2 */
+ J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (P27) MCU_ADC1_AIN3 */
+ J721S2_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (N25) MCU_ADC1_AIN4 */
+ J721S2_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (P26) MCU_ADC1_AIN5 */
+ J721S2_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */
+ J721S2_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */
+ >;
+ };
};
-&main_gpio4 {
- status = "disabled";
+&wkup_pmx1 {
+ mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */
+ J721S2_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */
+ J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */
+ J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */
+ J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */
+ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
+ J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
+ J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
+ >;
+ };
};
-&main_gpio6 {
- status = "disabled";
+&main_gpio0 {
+ status = "okay";
};
-&wkup_gpio1 {
- status = "disabled";
+&wkup_gpio0 {
+ status = "okay";
};
&wkup_uart0 {
status = "reserved";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
};
-&main_uart0 {
- status = "disabled";
-};
-
-&main_uart1 {
- status = "disabled";
-};
-
-&main_uart2 {
- status = "disabled";
-};
-
-&main_uart3 {
- status = "disabled";
-};
-
-&main_uart4 {
- status = "disabled";
-};
-
-&main_uart5 {
- status = "disabled";
-};
-
-&main_uart6 {
- status = "disabled";
-};
-
-&main_uart7 {
- status = "disabled";
+&mcu_uart0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_uart0_pins_default>;
};
&main_uart8 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart8_pins_default>;
/* Shared with TFA on this platform */
power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
};
-&main_uart9 {
- status = "disabled";
-};
-
&main_i2c0 {
clock-frequency = <400000>;
@@ -290,32 +356,9 @@
};
};
-&main_i2c1 {
- status = "disabled";
-};
-
-&main_i2c2 {
- status = "disabled";
-};
-
-&main_i2c3 {
- status = "disabled";
-};
-
-&main_i2c4 {
- status = "disabled";
-};
-
-&main_i2c5 {
- status = "disabled";
-};
-
-&main_i2c6 {
- status = "disabled";
-};
-
&main_sdhci0 {
/* eMMC */
+ status = "okay";
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
@@ -323,6 +366,7 @@
&main_sdhci1 {
/* SD card */
+ status = "okay";
pinctrl-0 = <&main_mmc1_pins_default>;
pinctrl-names = "default";
disable-wp;
@@ -332,7 +376,7 @@
&mcu_cpsw {
pinctrl-names = "default";
- pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+ pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
};
&davinci_mdio {
@@ -349,82 +393,112 @@
phy-handle = <&phy0>;
};
+&serdes_ln_ctrl {
+ idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>,
+ <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>;
+};
+
+&serdes_refclk {
+ clock-frequency = <100000000>;
+};
+
+&serdes0 {
+ status = "okay";
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&usb_serdes_mux {
+ idle-states = <1>; /* USB0 to SERDES lane 1 */
+};
+
+&usbss0 {
+ status = "okay";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ pinctrl-names = "default";
+ ti,vbus-divider;
+ ti,usb2-only;
+};
+
+&usb0 {
+ dr_mode = "otg";
+ maximum-speed = "high-speed";
+};
+
+&ospi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <40000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <2>;
+ };
+};
+
+&pcie1_rc {
+ status = "okay";
+ reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+};
+
&mcu_mcan0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan0_pins_default>;
phys = <&transceiver1>;
};
&mcu_mcan1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan1_pins_default>;
phys = <&transceiver2>;
};
-&main_mcan0 {
- status = "disabled";
+&tscadc0 {
+ pinctrl-0 = <&mcu_adc0_pins_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5 6 7>;
+ };
};
-&main_mcan1 {
- status = "disabled";
-};
-
-&main_mcan2 {
- status = "disabled";
+&tscadc1 {
+ pinctrl-0 = <&mcu_adc1_pins_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5 6 7>;
+ };
};
&main_mcan3 {
- status = "disabled";
-};
-
-&main_mcan4 {
- status = "disabled";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan3_pins_default>;
+ phys = <&transceiver3>;
};
&main_mcan5 {
- status = "disabled";
-};
-
-&main_mcan6 {
- status = "disabled";
-};
-
-&main_mcan7 {
- status = "disabled";
-};
-
-&main_mcan8 {
- status = "disabled";
-};
-
-&main_mcan9 {
- status = "disabled";
-};
-
-&main_mcan10 {
- status = "disabled";
-};
-
-&main_mcan11 {
- status = "disabled";
-};
-
-&main_mcan12 {
- status = "disabled";
-};
-
-&main_mcan13 {
- status = "disabled";
-};
-
-&main_mcan14 {
- status = "disabled";
-};
-
-&main_mcan15 {
- status = "disabled";
-};
-
-&main_mcan17 {
- status = "disabled";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan5_pins_default>;
+ phys = <&transceiver4>;
};
diff --git a/arch/arm/dts/k3-j721s2-main.dtsi b/arch/arm/dts/k3-j721s2-main.dtsi
index 976ba1e..084f8f5 100644
--- a/arch/arm/dts/k3-j721s2-main.dtsi
+++ b/arch/arm/dts/k3-j721s2-main.dtsi
@@ -5,6 +5,17 @@
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy-ti.h>
+
+/ {
+ serdes_refclk: clock-cmnrefclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+};
+
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@@ -26,6 +37,101 @@
};
};
+ scm_conf: syscon@104000 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0x00 0x00104000 0x00 0x18000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x00104000 0x18000>;
+
+ usb_serdes_mux: mux-controller@0 {
+ compatible = "mmio-mux";
+ reg = <0x0 0x4>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
+ };
+
+ phy_gmii_sel_cpsw: phy@34 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x34 0x4>;
+ #phy-cells = <1>;
+ };
+
+ serdes_ln_ctrl: mux-controller@80 {
+ compatible = "mmio-mux";
+ reg = <0x80 0x10>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
+ <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
+ };
+
+ ehrpwm_tbclk: clock-controller@140 {
+ compatible = "ti,am654-ehrpwm-tbclk";
+ reg = <0x140 0x18>;
+ #clock-cells = <1>;
+ };
+ };
+
+ main_ehrpwm0: pwm@3000000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3000000 0x00 0x100>;
+ power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ main_ehrpwm1: pwm@3010000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3010000 0x00 0x100>;
+ power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ main_ehrpwm2: pwm@3020000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3020000 0x00 0x100>;
+ power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ main_ehrpwm3: pwm@3030000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3030000 0x00 0x100>;
+ power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ main_ehrpwm4: pwm@3040000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3040000 0x00 0x100>;
+ power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ main_ehrpwm5: pwm@3050000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3050000 0x00 0x100>;
+ power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
@@ -33,8 +139,11 @@
ranges;
#interrupt-cells = <3>;
interrupt-controller;
- reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
- <0x00 0x01900000 0x00 0x100000>; /* GICR */
+ reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */
+ <0x00 0x01900000 0x00 0x100000>, /* GICR */
+ <0x00 0x6f000000 0x00 0x2000>, /* GICC */
+ <0x00 0x6f010000 0x00 0x1000>, /* GICH */
+ <0x00 0x6f020000 0x00 0x2000>; /* GICV */
/* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
@@ -57,7 +166,7 @@
#interrupt-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <148>;
- ti,interrupt-ranges = <8 360 56>;
+ ti,interrupt-ranges = <8 392 56>;
};
main_pmx0: pinctrl@11c000 {
@@ -69,6 +178,283 @@
pinctrl-single,function-mask = <0xffffffff>;
};
+ /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
+ main_timerio_input: pinctrl@104200 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x104200 0x00 0x50>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x00000007>;
+ };
+
+ /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
+ main_timerio_output: pinctrl@104280 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x104280 0x00 0x20>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000001f>;
+ };
+
+ main_crypto: crypto@4e00000 {
+ compatible = "ti,j721e-sa2ul";
+ reg = <0x00 0x04e00000 0x00 0x1200>;
+ power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
+
+ dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
+ <&main_udmap 0x4a41>;
+ dma-names = "tx", "rx1", "rx2";
+
+ rng: rng@4e10000 {
+ compatible = "inside-secure,safexcel-eip76";
+ reg = <0x00 0x04e10000 0x00 0x7d>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ main_timer0: timer@2400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2400000 0x00 0x400>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 63 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 63 1>;
+ assigned-clock-parents = <&k3_clks 63 2>;
+ power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer1: timer@2410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2410000 0x00 0x400>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 64 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 64 1>;
+ assigned-clock-parents = <&k3_clks 64 2>;
+ power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer2: timer@2420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2420000 0x00 0x400>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 65 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 65 1>;
+ assigned-clock-parents = <&k3_clks 65 2>;
+ power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer3: timer@2430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2430000 0x00 0x400>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 66 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 66 1>;
+ assigned-clock-parents = <&k3_clks 66 2>;
+ power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer4: timer@2440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2440000 0x00 0x400>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 67 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 67 1>;
+ assigned-clock-parents = <&k3_clks 67 2>;
+ power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer5: timer@2450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2450000 0x00 0x400>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 68 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 68 1>;
+ assigned-clock-parents = <&k3_clks 68 2>;
+ power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer6: timer@2460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2460000 0x00 0x400>;
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 69 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 69 1>;
+ assigned-clock-parents = <&k3_clks 69 2>;
+ power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer7: timer@2470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2470000 0x00 0x400>;
+ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 70 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 70 1>;
+ assigned-clock-parents = <&k3_clks 70 2>;
+ power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer8: timer@2480000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2480000 0x00 0x400>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 71 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 71 1>;
+ assigned-clock-parents = <&k3_clks 71 2>;
+ power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer9: timer@2490000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2490000 0x00 0x400>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 72 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 72 1>;
+ assigned-clock-parents = <&k3_clks 72 2>;
+ power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer10: timer@24a0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24a0000 0x00 0x400>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 73 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 73 1>;
+ assigned-clock-parents = <&k3_clks 73 2>;
+ power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer11: timer@24b0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24b0000 0x00 0x400>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 74 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 74 1>;
+ assigned-clock-parents = <&k3_clks 74 2>;
+ power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer12: timer@24c0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24c0000 0x00 0x400>;
+ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 75 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 75 1>;
+ assigned-clock-parents = <&k3_clks 75 2>;
+ power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer13: timer@24d0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24d0000 0x00 0x400>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 76 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 76 1>;
+ assigned-clock-parents = <&k3_clks 76 2>;
+ power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer14: timer@24e0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24e0000 0x00 0x400>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 77 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 77 1>;
+ assigned-clock-parents = <&k3_clks 77 2>;
+ power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer15: timer@24f0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24f0000 0x00 0x400>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 78 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 78 1>;
+ assigned-clock-parents = <&k3_clks 78 2>;
+ power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer16: timer@2500000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2500000 0x00 0x400>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 79 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 79 1>;
+ assigned-clock-parents = <&k3_clks 79 2>;
+ power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer17: timer@2510000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2510000 0x00 0x400>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 80 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 80 1>;
+ assigned-clock-parents = <&k3_clks 80 2>;
+ power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer18: timer@2520000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2520000 0x00 0x400>;
+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 81 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 81 1>;
+ assigned-clock-parents = <&k3_clks 81 2>;
+ power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer19: timer@2530000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2530000 0x00 0x400>;
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 82 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 82 1>;
+ assigned-clock-parents = <&k3_clks 82 2>;
+ power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x200>;
@@ -77,6 +463,7 @@
clocks = <&k3_clks 146 3>;
clock-names = "fclk";
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart1: serial@2810000 {
@@ -87,6 +474,7 @@
clocks = <&k3_clks 350 3>;
clock-names = "fclk";
power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart2: serial@2820000 {
@@ -97,6 +485,7 @@
clocks = <&k3_clks 351 3>;
clock-names = "fclk";
power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart3: serial@2830000 {
@@ -107,6 +496,7 @@
clocks = <&k3_clks 352 3>;
clock-names = "fclk";
power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart4: serial@2840000 {
@@ -117,6 +507,7 @@
clocks = <&k3_clks 353 3>;
clock-names = "fclk";
power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart5: serial@2850000 {
@@ -127,6 +518,7 @@
clocks = <&k3_clks 354 3>;
clock-names = "fclk";
power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart6: serial@2860000 {
@@ -137,6 +529,7 @@
clocks = <&k3_clks 355 3>;
clock-names = "fclk";
power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart7: serial@2870000 {
@@ -147,6 +540,7 @@
clocks = <&k3_clks 356 3>;
clock-names = "fclk";
power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart8: serial@2880000 {
@@ -157,6 +551,7 @@
clocks = <&k3_clks 357 3>;
clock-names = "fclk";
power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart9: serial@2890000 {
@@ -167,6 +562,7 @@
clocks = <&k3_clks 358 3>;
clock-names = "fclk";
power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_gpio0: gpio@600000 {
@@ -183,6 +579,7 @@
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 111 0>;
clock-names = "gpio";
+ status = "disabled";
};
main_gpio2: gpio@610000 {
@@ -199,6 +596,7 @@
power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 112 0>;
clock-names = "gpio";
+ status = "disabled";
};
main_gpio4: gpio@620000 {
@@ -215,6 +613,7 @@
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 113 0>;
clock-names = "gpio";
+ status = "disabled";
};
main_gpio6: gpio@630000 {
@@ -231,6 +630,7 @@
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>;
clock-names = "gpio";
+ status = "disabled";
};
main_i2c0: i2c@2000000 {
@@ -253,6 +653,7 @@
clocks = <&k3_clks 215 1>;
clock-names = "fck";
power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c2: i2c@2020000 {
@@ -264,6 +665,7 @@
clocks = <&k3_clks 216 1>;
clock-names = "fck";
power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c3: i2c@2030000 {
@@ -275,6 +677,7 @@
clocks = <&k3_clks 217 1>;
clock-names = "fck";
power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c4: i2c@2040000 {
@@ -286,6 +689,7 @@
clocks = <&k3_clks 218 1>;
clock-names = "fck";
power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c5: i2c@2050000 {
@@ -297,6 +701,7 @@
clocks = <&k3_clks 219 1>;
clock-names = "fck";
power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c6: i2c@2060000 {
@@ -308,6 +713,7 @@
clocks = <&k3_clks 220 1>;
clock-names = "fck";
power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_sdhci0: mmc@4f80000 {
@@ -317,7 +723,7 @@
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 98 7>, <&k3_clks 98 1>;
- clock-names = "clk_ahb", "clk_xin";
+ clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&k3_clks 98 1>;
assigned-clock-parents = <&k3_clks 98 2>;
bus-width = <8>;
@@ -335,6 +741,7 @@
mmc-hs200-1_8v;
mmc-hs400-1_8v;
dma-coherent;
+ status = "disabled";
};
main_sdhci1: mmc@4fb0000 {
@@ -344,7 +751,7 @@
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 99 8>, <&k3_clks 99 1>;
- clock-names = "clk_ahb", "clk_xin";
+ clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&k3_clks 99 1>;
assigned-clock-parents = <&k3_clks 99 2>;
bus-width = <4>;
@@ -363,7 +770,8 @@
ti,trm-icp = <0x8>;
dma-coherent;
/* Masking support for SDR104 capability */
- // sdhci-caps-mask = <0x00000003 0x00000000>;
+ sdhci-caps-mask = <0x00000003 0x00000000>;
+ status = "disabled";
};
main_navss: bus@30000000 {
@@ -425,6 +833,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster1: mailbox@31f81000 {
@@ -434,6 +843,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster2: mailbox@31f82000 {
@@ -443,6 +853,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster3: mailbox@31f83000 {
@@ -452,6 +863,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster4: mailbox@31f84000 {
@@ -461,6 +873,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster5: mailbox@31f85000 {
@@ -470,6 +883,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster6: mailbox@31f86000 {
@@ -479,6 +893,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster7: mailbox@31f87000 {
@@ -488,6 +903,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster8: mailbox@31f88000 {
@@ -497,6 +913,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster9: mailbox@31f89000 {
@@ -506,6 +923,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster10: mailbox@31f8a000 {
@@ -515,6 +933,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster11: mailbox@31f8b000 {
@@ -524,6 +943,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster0: mailbox@31f90000 {
@@ -533,6 +953,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster1: mailbox@31f91000 {
@@ -542,6 +963,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster2: mailbox@31f92000 {
@@ -551,6 +973,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster3: mailbox@31f93000 {
@@ -560,6 +983,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster4: mailbox@31f94000 {
@@ -569,6 +993,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster5: mailbox@31f95000 {
@@ -578,6 +1003,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster6: mailbox@31f96000 {
@@ -587,6 +1013,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster7: mailbox@31f97000 {
@@ -596,6 +1023,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster8: mailbox@31f98000 {
@@ -605,6 +1033,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster9: mailbox@31f99000 {
@@ -614,6 +1043,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster10: mailbox@31f9a000 {
@@ -623,6 +1053,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster11: mailbox@31f9b000 {
@@ -632,6 +1063,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
main_ringacc: ringacc@3c000000 {
@@ -639,8 +1071,9 @@
reg = <0x0 0x3c000000 0x0 0x400000>,
<0x0 0x38000000 0x0 0x400000>,
<0x0 0x31120000 0x0 0x100>,
- <0x0 0x33000000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ <0x0 0x33000000 0x0 0x40000>,
+ <0x0 0x31080000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
ti,num-rings = <1024>;
ti,sci-rm-range-gp-rings = <0x1>;
ti,sci = <&sms>;
@@ -676,6 +1109,8 @@
reg-names = "cpts";
clocks = <&k3_clks 226 5>;
clock-names = "cpts";
+ assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */
+ assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */
interrupts-extended = <&main_navss_intr 391>;
interrupt-names = "cpts";
ti,cpts-periodic-outputs = <6>;
@@ -683,6 +1118,180 @@
};
};
+ main_cpsw: ethernet@c200000 {
+ compatible = "ti,j721e-cpsw-nuss";
+ reg = <0x00 0xc200000 0x00 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-coherent;
+ clocks = <&k3_clks 28 28>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
+
+ dmas = <&main_udmap 0xc640>,
+ <&main_udmap 0xc641>,
+ <&main_udmap 0xc642>,
+ <&main_udmap 0xc643>,
+ <&main_udmap 0xc644>,
+ <&main_udmap 0xc645>,
+ <&main_udmap 0xc646>,
+ <&main_udmap 0xc647>,
+ <&main_udmap 0x4640>;
+ dma-names = "tx0", "tx1", "tx2", "tx3",
+ "tx4", "tx5", "tx6", "tx7",
+ "rx";
+
+ status = "disabled";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ main_cpsw_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ phys = <&phy_gmii_sel_cpsw 1>;
+ status = "disabled";
+ };
+ };
+
+ main_cpsw_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x00 0xf00 0x00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 28 28>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ status = "disabled";
+ };
+
+ cpts@3d000 {
+ compatible = "ti,am65-cpts";
+ reg = <0x00 0x3d000 0x00 0x400>;
+ clocks = <&k3_clks 28 3>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+
+ usbss0: cdns-usb@4104000 {
+ compatible = "ti,j721e-usb";
+ reg = <0x00 0x04104000 0x00 0x100>;
+ clocks = <&k3_clks 360 16>, <&k3_clks 360 15>;
+ clock-names = "ref", "lpm";
+ assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
+ assigned-clock-parents = <&k3_clks 360 17>;
+ power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-coherent;
+
+ status = "disabled"; /* Needs pinmux */
+
+ usb0: usb@6000000 {
+ compatible = "cdns,usb3";
+ reg = <0x00 0x06000000 0x00 0x10000>,
+ <0x00 0x06010000 0x00 0x10000>,
+ <0x00 0x06020000 0x00 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host", "peripheral", "otg";
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+ };
+ };
+
+ serdes_wiz0: wiz@5060000 {
+ compatible = "ti,j721s2-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x5060000 0x0 0x5060000 0x10000>;
+
+ assigned-clocks = <&k3_clks 365 3>;
+ assigned-clock-parents = <&k3_clks 365 7>;
+
+ serdes0: serdes@5060000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05060000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 365 3>,
+ <&k3_clks 365 3>,
+ <&k3_clks 365 3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled"; /* Needs lane config */
+ };
+ };
+
+ pcie1_rc: pcie@2910000 {
+ compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x800000>,
+ <0x00 0x18000000 0x00 0x1000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 276 41>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x104c>;
+ device-id = <0xb013>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
+ <0 0 0 2 &pcie1_intc 0>, /* INT B */
+ <0 0 0 3 &pcie1_intc 0>, /* INT C */
+ <0 0 0 4 &pcie1_intc 0>; /* INT D */
+
+ status = "disabled"; /* Needs gpio and serdes info */
+
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
@@ -695,6 +1304,7 @@
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan1: can@2711000 {
@@ -709,6 +1319,7 @@
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan2: can@2721000 {
@@ -723,6 +1334,7 @@
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan3: can@2731000 {
@@ -737,6 +1349,7 @@
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan4: can@2741000 {
@@ -751,6 +1364,7 @@
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan5: can@2751000 {
@@ -765,6 +1379,7 @@
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan6: can@2761000 {
@@ -779,6 +1394,7 @@
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan7: can@2771000 {
@@ -793,6 +1409,7 @@
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan8: can@2781000 {
@@ -807,6 +1424,7 @@
<GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan9: can@2791000 {
@@ -821,6 +1439,7 @@
<GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan10: can@27a1000 {
@@ -835,6 +1454,7 @@
<GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan11: can@27b1000 {
@@ -849,6 +1469,7 @@
<GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan12: can@27c1000 {
@@ -863,6 +1484,7 @@
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan13: can@27d1000 {
@@ -877,6 +1499,7 @@
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan14: can@2681000 {
@@ -891,6 +1514,7 @@
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan15: can@2691000 {
@@ -905,6 +1529,7 @@
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan16: can@26a1000 {
@@ -919,6 +1544,7 @@
<GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan17: can@26b1000 {
@@ -933,5 +1559,140 @@
<GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_spi0: spi@2100000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02100000 0x00 0x400>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 339 1>;
+ status = "disabled";
+ };
+
+ main_spi1: spi@2110000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02110000 0x00 0x400>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 340 1>;
+ status = "disabled";
+ };
+
+ main_spi2: spi@2120000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02120000 0x00 0x400>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 341 1>;
+ status = "disabled";
+ };
+
+ main_spi3: spi@2130000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02130000 0x00 0x400>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 342 1>;
+ status = "disabled";
+ };
+
+ main_spi4: spi@2140000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02140000 0x00 0x400>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 343 1>;
+ status = "disabled";
+ };
+
+ main_spi5: spi@2150000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02150000 0x00 0x400>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 344 1>;
+ status = "disabled";
+ };
+
+ main_spi6: spi@2160000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02160000 0x00 0x400>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 345 1>;
+ status = "disabled";
+ };
+
+ main_spi7: spi@2170000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02170000 0x00 0x400>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 346 1>;
+ status = "disabled";
+ };
+
+ dss: dss@4a00000 {
+ compatible = "ti,j721e-dss";
+ reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
+ <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
+ <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
+ <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
+ <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
+ <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
+ <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
+ <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
+ <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
+ <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
+ <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
+ <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
+ <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
+ <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
+ <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
+ <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
+ <0x00 0x04af0000 0x00 0x10000>; /* wb */
+ reg-names = "common_m", "common_s0",
+ "common_s1", "common_s2",
+ "vidl1", "vidl2","vid1","vid2",
+ "ovr1", "ovr2", "ovr3", "ovr4",
+ "vp1", "vp2", "vp3", "vp4",
+ "wb";
+ clocks = <&k3_clks 158 0>,
+ <&k3_clks 158 2>,
+ <&k3_clks 158 5>,
+ <&k3_clks 158 14>,
+ <&k3_clks 158 18>;
+ clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
+ power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common_m",
+ "common_s0",
+ "common_s1",
+ "common_s2";
+ status = "disabled";
+
+ dss_ports: ports {
+ };
};
};
diff --git a/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
index 7521963..2ddad93 100644
--- a/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
@@ -12,8 +12,8 @@
mbox-names = "rx", "tx";
- mboxes= <&secure_proxy_main 11>,
- <&secure_proxy_main 13>;
+ mboxes = <&secure_proxy_main 11>,
+ <&secure_proxy_main 13>;
reg-names = "debug_messages";
reg = <0x00 0x44083000 0x00 0x1000>;
@@ -39,6 +39,21 @@
reg = <0x00 0x43000014 0x00 0x4>;
};
+ secure_proxy_sa3: mailbox@43600000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x43600000 0x00 0x10000>,
+ <0x00 0x44880000 0x00 0x20000>,
+ <0x00 0x44860000 0x00 0x20000>;
+ /*
+ * Marked Disabled:
+ * Node is incomplete as it is meant for bootloaders and
+ * firmware on non-MPU processors
+ */
+ status = "disabled";
+ };
+
mcu_ram: sram@41c00000 {
compatible = "mmio-sram";
reg = <0x00 0x41c00000 0x00 0x100000>;
@@ -50,12 +65,61 @@
wkup_pmx0: pinctrl@4301c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
- reg = <0x00 0x4301c000 0x00 0x178>;
+ reg = <0x00 0x4301c000 0x00 0x034>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
+ wkup_pmx1: pinctrl@4301c038 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x00 0x4301c038 0x00 0x02C>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ wkup_pmx2: pinctrl@4301c068 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x00 0x4301c068 0x00 0x120>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ wkup_pmx3: pinctrl@4301c190 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x00 0x4301c190 0x00 0x004>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
+ mcu_timerio_input: pinctrl@40f04200 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x40f04200 0x00 0x28>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
+ mcu_timerio_output: pinctrl@40f04280 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x40f04280 0x00 0x28>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
wkup_gpio_intr: interrupt-controller@42200000 {
compatible = "ti,sci-intr";
reg = <0x00 0x42200000 0x00 0x400>;
@@ -65,7 +129,7 @@
#interrupt-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <125>;
- ti,interrupt-ranges = <16 928 16>;
+ ti,interrupt-ranges = <16 960 16>;
};
mcu_conf: syscon@40f00000 {
@@ -83,6 +147,146 @@
};
+ mcu_timer0: timer@40400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40400000 0x00 0x400>;
+ interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 35 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 35 1>;
+ assigned-clock-parents = <&k3_clks 35 2>;
+ power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer1: timer@40410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40410000 0x00 0x400>;
+ interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 83 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 83 1>;
+ assigned-clock-parents = <&k3_clks 83 2>;
+ power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer2: timer@40420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40420000 0x00 0x400>;
+ interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 84 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 84 1>;
+ assigned-clock-parents = <&k3_clks 84 2>;
+ power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer3: timer@40430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40430000 0x00 0x400>;
+ interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 85 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 85 1>;
+ assigned-clock-parents = <&k3_clks 85 2>;
+ power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer4: timer@40440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40440000 0x00 0x400>;
+ interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 86 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 86 1>;
+ assigned-clock-parents = <&k3_clks 86 2>;
+ power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer5: timer@40450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40450000 0x00 0x400>;
+ interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 87 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 87 1>;
+ assigned-clock-parents = <&k3_clks 87 2>;
+ power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer6: timer@40460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40460000 0x00 0x400>;
+ interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 88 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 88 1>;
+ assigned-clock-parents = <&k3_clks 88 2>;
+ power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer7: timer@40470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40470000 0x00 0x400>;
+ interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 89 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 89 1>;
+ assigned-clock-parents = <&k3_clks 89 2>;
+ power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer8: timer@40480000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40480000 0x00 0x400>;
+ interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 90 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 90 1>;
+ assigned-clock-parents = <&k3_clks 90 2>;
+ power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer9: timer@40490000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40490000 0x00 0x400>;
+ interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 91 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 91 1>;
+ assigned-clock-parents = <&k3_clks 91 2>;
+ power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x200>;
@@ -91,6 +295,7 @@
clocks = <&k3_clks 359 3>;
clock-names = "fclk";
power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_uart0: serial@40a00000 {
@@ -101,6 +306,7 @@
clocks = <&k3_clks 149 3>;
clock-names = "fclk";
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
wkup_gpio0: gpio@42110000 {
@@ -108,7 +314,7 @@
reg = <0x00 0x42110000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
+ interrupt-parent = <&wkup_gpio_intr>;
interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -117,6 +323,7 @@
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 115 0>;
clock-names = "gpio";
+ status = "disabled";
};
wkup_gpio1: gpio@42100000 {
@@ -124,7 +331,7 @@
reg = <0x00 0x42100000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
+ interrupt-parent = <&wkup_gpio_intr>;
interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -133,6 +340,7 @@
power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 116 0>;
clock-names = "gpio";
+ status = "disabled";
};
wkup_i2c0: i2c@42120000 {
@@ -144,6 +352,7 @@
clocks = <&k3_clks 223 1>;
clock-names = "fck";
power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_i2c0: i2c@40b00000 {
@@ -155,6 +364,7 @@
clocks = <&k3_clks 221 1>;
clock-names = "fck";
power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_i2c1: i2c@40b10000 {
@@ -166,6 +376,7 @@
clocks = <&k3_clks 222 1>;
clock-names = "fck";
power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_mcan0: can@40528000 {
@@ -180,6 +391,7 @@
<GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
mcu_mcan1: can@40568000 {
@@ -194,9 +406,43 @@
<GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
- mcu_navss: bus@28380000{
+ mcu_spi0: spi@40300000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040300000 0x00 0x400>;
+ interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 347 0>;
+ status = "disabled";
+ };
+
+ mcu_spi1: spi@40310000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040310000 0x00 0x400>;
+ interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 348 0>;
+ status = "disabled";
+ };
+
+ mcu_spi2: spi@40320000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040320000 0x00 0x400>;
+ interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 349 0>;
+ status = "disabled";
+ };
+
+ mcu_navss: bus@28380000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
@@ -211,8 +457,9 @@
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
- <0x0 0x2a500000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ <0x0 0x2a500000 0x0 0x40000>,
+ <0x0 0x28440000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
ti,num-rings = <286>;
ti,sci-rm-range-gp-rings = <0x1>;
ti,sci = <&sms>;
@@ -240,6 +487,21 @@
};
};
+ secure_proxy_mcu: mailbox@2a480000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x2a480000 0x00 0x80000>,
+ <0x00 0x2a380000 0x00 0x80000>,
+ <0x00 0x2a400000 0x00 0x80000>;
+ /*
+ * Marked Disabled:
+ * Node is incomplete as it is meant for bootloaders and
+ * firmware on non-MPU processors
+ */
+ status = "disabled";
+ };
+
mcu_cpsw: ethernet@46000000 {
compatible = "ti,j721e-cpsw-nuss";
#address-cells = <2>;
@@ -293,10 +555,104 @@
reg = <0x0 0x3d000 0x0 0x400>;
clocks = <&k3_clks 29 3>;
clock-names = "cpts";
+ assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */
+ assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */
interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cpts";
ti,cpts-ext-ts-inputs = <4>;
ti,cpts-periodic-outputs = <2>;
};
};
+
+ tscadc0: tscadc@40200000 {
+ compatible = "ti,am3359-tscadc";
+ reg = <0x00 0x40200000 0x00 0x1000>;
+ interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 0 0>;
+ assigned-clocks = <&k3_clks 0 2>;
+ assigned-clock-rates = <60000000>;
+ clock-names = "fck";
+ dmas = <&main_udmap 0x7400>,
+ <&main_udmap 0x7401>;
+ dma-names = "fifo0", "fifo1";
+ status = "disabled";
+
+ adc {
+ #io-channel-cells = <1>;
+ compatible = "ti,am3359-adc";
+ };
+ };
+
+ tscadc1: tscadc@40210000 {
+ compatible = "ti,am3359-tscadc";
+ reg = <0x00 0x40210000 0x00 0x1000>;
+ interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 1 0>;
+ assigned-clocks = <&k3_clks 1 2>;
+ assigned-clock-rates = <60000000>;
+ clock-names = "fck";
+ dmas = <&main_udmap 0x7402>,
+ <&main_udmap 0x7403>;
+ dma-names = "fifo0", "fifo1";
+ status = "disabled";
+
+ adc {
+ #io-channel-cells = <1>;
+ compatible = "ti,am3359-adc";
+ };
+ };
+
+ fss: bus@47000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
+ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
+
+ ospi0: spi@47040000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x47040000 0x00 0x100>,
+ <0x05 0x00000000 0x01 0x00000000>;
+ interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 109 5>;
+ assigned-clocks = <&k3_clks 109 5>;
+ assigned-clock-parents = <&k3_clks 109 7>;
+ assigned-clock-rates = <166666666>;
+ power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled"; /* Needs pinmux */
+ };
+
+ ospi1: spi@47050000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x47050000 0x00 0x100>,
+ <0x07 0x00000000 0x01 0x00000000>;
+ interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 110 5>;
+ power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled"; /* Needs pinmux */
+ };
+ };
+
+ wkup_vtm0: temperature-sensor@42040000 {
+ compatible = "ti,j7200-vtm";
+ reg = <0x00 0x42040000 0x0 0x350>,
+ <0x00 0x42050000 0x0 0x350>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>;
+ #thermal-sensor-cells = <1>;
+ };
};
diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
index c74e8e5..03bd680 100644
--- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
@@ -1,20 +1,18 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-#include "k3-j721s2-som-p0.dtsi"
+#include "k3-j721s2-common-proc-board.dts"
#include "k3-j721s2-ddr-evm-lp4-4266.dtsi"
#include "k3-j721s2-ddr.dtsi"
-#include "k3-j721s2-binman.dtsi"
+#include "k3-j721s2-common-proc-board-u-boot.dtsi"
/ {
chosen {
- firmware-loader = &fs_loader0;
- stdout-path = &main_uart8;
- tick-timer = &timer1;
+ tick-timer = &mcu_timer0;
};
aliases {
@@ -22,11 +20,6 @@
remoteproc1 = &a72_0;
};
- fs_loader0: fs_loader@0 {
- compatible = "u-boot,fs-loader";
- bootph-all;
- };
-
a72_0: a72@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
@@ -44,149 +37,46 @@
bootph-pre-ram;
};
- clk_200mhz: dummy_clock_200mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- bootph-pre-ram;
- };
-
- clk_19_2mhz: dummy_clock_19_2mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <19200000>;
- bootph-pre-ram;
- };
-};
-
-&cbass_mcu_wakeup {
- sa3_secproxy: secproxy@44880000 {
- bootph-pre-ram;
- compatible = "ti,am654-secure-proxy";
- reg = <0x0 0x44880000 0x0 0x20000>,
- <0x0 0x44860000 0x0 0x20000>,
- <0x0 0x43600000 0x0 0x10000>;
- reg-names = "rt", "scfg", "target_data";
- #mbox-cells = <1>;
- };
-
- mcu_secproxy: secproxy@2a380000 {
- compatible = "ti,am654-secure-proxy";
- reg = <0x0 0x2a380000 0x0 0x80000>,
- <0x0 0x2a400000 0x0 0x80000>,
- <0x0 0x2a480000 0x0 0x80000>;
- reg-names = "rt", "scfg", "target_data";
- #mbox-cells = <1>;
- bootph-pre-ram;
- };
-
- sysctrler: sysctrler {
- compatible = "ti,am654-system-controller";
- mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>, <&sa3_secproxy 5>;
- mbox-names = "tx", "rx", "boot_notify";
- bootph-pre-ram;
- };
-
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <3>;
ti,secure-host;
mbox-names = "rx", "tx";
- mboxes= <&mcu_secproxy 21>,
- <&mcu_secproxy 23>;
+ mboxes= <&secure_proxy_mcu 21>,
+ <&secure_proxy_mcu 23>;
bootph-pre-ram;
};
};
-&main_pmx0 {
- main_uart8_pins_default: main-uart8-pins-default {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */
- J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
- J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
- J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
- >;
- };
-
- main_mmc1_pins_default: main-mmc1-pins-default {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
- J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
- J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
- J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
- J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
- J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
- J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
- J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
- >;
- };
+&mcu_timer0 {
+ clock-frequency = <250000000>;
+ bootph-pre-ram;
};
-&wkup_pmx0 {
- mcu_uart0_pins_default: mcu-uart0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */
- J721S2_WKUP_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */
- J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
- J721S2_WKUP_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
- >;
- };
+&secure_proxy_sa3 {
+ bootph-pre-ram;
+ status = "okay";
+};
- wkup_uart0_pins_default: wkup-uart0-pins-default {
+&secure_proxy_mcu {
+ bootph-pre-ram;
+ status = "okay";
+};
+
+&cbass_mcu_wakeup {
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>;
+ mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
- J721S2_WKUP_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
- J721S2_WKUP_IOPAD(0x0b0, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
- J721S2_WKUP_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
- >;
};
};
&sms {
- mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
+ mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
- bootph-pre-ram;
-};
-
-&wkup_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
-};
-
-&mcu_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_uart0_pins_default>;
-};
-
-&main_uart8 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart8_pins_default>;
-};
-
-&main_sdhci0 {
- /delete-property/ power-domains;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- clock-names = "clk_xin";
- clocks = <&clk_200mhz>;
- ti,driver-strength-ohm = <50>;
- non-removable;
- bus-width = <8>;
-};
-
-&main_sdhci1 {
- /delete-property/ power-domains;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- pinctrl-0 = <&main_mmc1_pins_default>;
- pinctrl-names = "default";
- clock-names = "clk_xin";
- clocks = <&clk_200mhz>;
- ti,driver-strength-ohm = <50>;
};
&mcu_ringacc {
@@ -196,5 +86,3 @@
&mcu_udmap {
ti,sci = <&dm_tifs>;
};
-
-#include "k3-j721s2-common-proc-board-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-j721s2-som-p0.dtsi b/arch/arm/dts/k3-j721s2-som-p0.dtsi
index c0687fe..a4006f3 100644
--- a/arch/arm/dts/k3-j721s2-som-p0.dtsi
+++ b/arch/arm/dts/k3-j721s2-som-p0.dtsi
@@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
+ * SoM: https://www.ti.com/lit/zip/sprr439
+ *
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
@@ -16,6 +18,7 @@
<0x08 0x80000000 0x03 0x80000000>;
};
+ /* Reserving memory regions still pending */
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -26,7 +29,18 @@
alignment = <0x1000>;
no-map;
};
+ };
+ mux0: mux-controller {
+ compatible = "gpio-mux";
+ #mux-state-cells = <1>;
+ mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ mux1: mux-controller {
+ compatible = "gpio-mux";
+ #mux-state-cells = <1>;
+ mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>;
};
transceiver0: can-phy0 {
@@ -37,15 +51,43 @@
};
};
+&wkup_pmx0 {
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
+ J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
+ J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
+ J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
+ J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
+ J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */
+ J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */
+ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */
+ J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */
+ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
+ J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
+ J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
+ >;
+ };
+};
+
+&wkup_pmx2 {
+ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
+ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
+ >;
+ };
+};
+
&main_pmx0 {
- main_i2c0_pins_default: main-i2c0-pins-default {
+ main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */
J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */
>;
};
- main_mcan16_pins_default: main-mcan16-pins-default {
+ main_mcan16_pins_default: main-mcan16-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */
J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */
@@ -53,7 +95,21 @@
};
};
+&wkup_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ eeprom@50 {
+ /* CAV24C256WE-GT3 */
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ };
+};
+
&main_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
@@ -71,103 +127,27 @@
};
&main_mcan16 {
+ status = "okay";
pinctrl-0 = <&main_mcan16_pins_default>;
pinctrl-names = "default";
phys = <&transceiver0>;
};
-&mailbox0_cluster0 {
- status = "disabled";
-};
+&ospi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
-&mailbox0_cluster1 {
- status = "disabled";
-};
-
-&mailbox0_cluster2 {
- status = "disabled";
-};
-
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
-&mailbox0_cluster4 {
- status = "disabled";
-};
-
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
-&mailbox0_cluster6 {
- status = "disabled";
-};
-
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
-&mailbox0_cluster8 {
- status = "disabled";
-};
-
-&mailbox0_cluster9 {
- status = "disabled";
-};
-
-&mailbox0_cluster10 {
- status = "disabled";
-};
-
-&mailbox0_cluster11 {
- status = "disabled";
-};
-
-&mailbox1_cluster0 {
- status = "disabled";
-};
-
-&mailbox1_cluster1 {
- status = "disabled";
-};
-
-&mailbox1_cluster2 {
- status = "disabled";
-};
-
-&mailbox1_cluster3 {
- status = "disabled";
-};
-
-&mailbox1_cluster4 {
- status = "disabled";
-};
-
-&mailbox1_cluster5 {
- status = "disabled";
-};
-
-&mailbox1_cluster6 {
- status = "disabled";
-};
-
-&mailbox1_cluster7 {
- status = "disabled";
-};
-
-&mailbox1_cluster8 {
- status = "disabled";
-};
-
-&mailbox1_cluster9 {
- status = "disabled";
-};
-
-&mailbox1_cluster10 {
- status = "disabled";
-};
-
-&mailbox1_cluster11 {
- status = "disabled";
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <25000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <4>;
+ };
};
diff --git a/arch/arm/dts/k3-j721s2-thermal.dtsi b/arch/arm/dts/k3-j721s2-thermal.dtsi
new file mode 100644
index 0000000..f7b1a15
--- /dev/null
+++ b/arch/arm/dts/k3-j721s2-thermal.dtsi
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+wkup0_thermal: wkup0-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 0>;
+
+ trips {
+ wkup0_crit: wkup0-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
+
+wkup1_thermal: wkup1-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 1>;
+
+ trips {
+ wkup1_crit: wkup1-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
+
+main0_thermal: main0-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 2>;
+
+ trips {
+ main0_crit: main0-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
+
+main1_thermal: main1-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 3>;
+
+ trips {
+ main1_crit: main1-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
+
+main2_thermal: main2-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 4>;
+
+ trips {
+ main2_crit: main2-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
+
+main3_thermal: main3-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 5>;
+
+ trips {
+ main3_crit: main3-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
+
+main4_thermal: main4-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 6>;
+
+ trips {
+ main4_crit: main4-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-j721s2.dtsi b/arch/arm/dts/k3-j721s2.dtsi
index fe5234c..1f636ac 100644
--- a/arch/arm/dts/k3-j721s2.dtsi
+++ b/arch/arm/dts/k3-j721s2.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Source for J721S2 SoC Family
*
- * TRM (SPRUJ28 – NOVEMBER 2021) : http://www.ti.com/lit/pdf/spruj28
+ * TRM (SPRUJ28 NOVEMBER 2021): https://www.ti.com/lit/pdf/spruj28
*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*
@@ -10,9 +10,10 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
+#include "k3-pinctrl.h"
+
/ {
model = "Texas Instruments K3 J721S2 SoC";
@@ -69,6 +70,7 @@
L2_0: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-level = <2>;
cache-size = <0x100000>;
cache-line-size = <64>;
@@ -79,6 +81,7 @@
msmc_l3: l3-cache0 {
compatible = "cache";
cache-level = <3>;
+ cache-unified;
};
firmware {
@@ -119,6 +122,7 @@
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
<0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
<0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
+ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
@@ -160,6 +164,10 @@
};
};
+
+ thermal_zones: thermal-zones {
+ #include "k3-j721s2-thermal.dtsi"
+ };
};
/* Now include peripherals from each bus segment */
diff --git a/arch/arm/dts/k3-pinctrl.h b/arch/arm/dts/k3-pinctrl.h
index c97548a..2a4e0e0 100644
--- a/arch/arm/dts/k3-pinctrl.h
+++ b/arch/arm/dts/k3-pinctrl.h
@@ -11,6 +11,7 @@
#define PULLUDEN_SHIFT (16)
#define PULLTYPESEL_SHIFT (17)
#define RXACTIVE_SHIFT (18)
+#define DEBOUNCE_SHIFT (11)
#define PULL_DISABLE (1 << PULLUDEN_SHIFT)
#define PULL_ENABLE (0 << PULLUDEN_SHIFT)
@@ -29,9 +30,20 @@
#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP)
#define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN)
+#define PIN_DEBOUNCE_DISABLE (0 << DEBOUNCE_SHIFT)
+#define PIN_DEBOUNCE_CONF1 (1 << DEBOUNCE_SHIFT)
+#define PIN_DEBOUNCE_CONF2 (2 << DEBOUNCE_SHIFT)
+#define PIN_DEBOUNCE_CONF3 (3 << DEBOUNCE_SHIFT)
+#define PIN_DEBOUNCE_CONF4 (4 << DEBOUNCE_SHIFT)
+#define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT)
+#define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT)
+
#define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+
#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
diff --git a/arch/arm/dts/k3-serdes.h b/arch/arm/dts/k3-serdes.h
new file mode 100644
index 0000000..29167f8
--- /dev/null
+++ b/arch/arm/dts/k3-serdes.h
@@ -0,0 +1,204 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for SERDES MUX for TI SoCs
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef DTS_ARM64_TI_K3_SERDES_H
+#define DTS_ARM64_TI_K3_SERDES_H
+
+/* J721E */
+
+#define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0
+#define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1
+#define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2
+#define J721E_SERDES0_LANE0_IP4_UNUSED 0x3
+
+#define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0
+#define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1
+#define J721E_SERDES0_LANE1_USB3_0 0x2
+#define J721E_SERDES0_LANE1_IP4_UNUSED 0x3
+
+#define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0
+#define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1
+#define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2
+#define J721E_SERDES1_LANE0_SGMII_LANE0 0x3
+
+#define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0
+#define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1
+#define J721E_SERDES1_LANE1_USB3_1 0x2
+#define J721E_SERDES1_LANE1_SGMII_LANE1 0x3
+
+#define J721E_SERDES2_LANE0_IP1_UNUSED 0x0
+#define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1
+#define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2
+#define J721E_SERDES2_LANE0_SGMII_LANE0 0x3
+
+#define J721E_SERDES2_LANE1_IP1_UNUSED 0x0
+#define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1
+#define J721E_SERDES2_LANE1_USB3_1 0x2
+#define J721E_SERDES2_LANE1_SGMII_LANE1 0x3
+
+#define J721E_SERDES3_LANE0_IP1_UNUSED 0x0
+#define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1
+#define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2
+#define J721E_SERDES3_LANE0_IP4_UNUSED 0x3
+
+#define J721E_SERDES3_LANE1_IP1_UNUSED 0x0
+#define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1
+#define J721E_SERDES3_LANE1_USB3_0 0x2
+#define J721E_SERDES3_LANE1_IP4_UNUSED 0x3
+
+#define J721E_SERDES4_LANE0_EDP_LANE0 0x0
+#define J721E_SERDES4_LANE0_IP2_UNUSED 0x1
+#define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2
+#define J721E_SERDES4_LANE0_IP4_UNUSED 0x3
+
+#define J721E_SERDES4_LANE1_EDP_LANE1 0x0
+#define J721E_SERDES4_LANE1_IP2_UNUSED 0x1
+#define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2
+#define J721E_SERDES4_LANE1_IP4_UNUSED 0x3
+
+#define J721E_SERDES4_LANE2_EDP_LANE2 0x0
+#define J721E_SERDES4_LANE2_IP2_UNUSED 0x1
+#define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2
+#define J721E_SERDES4_LANE2_IP4_UNUSED 0x3
+
+#define J721E_SERDES4_LANE3_EDP_LANE3 0x0
+#define J721E_SERDES4_LANE3_IP2_UNUSED 0x1
+#define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2
+#define J721E_SERDES4_LANE3_IP4_UNUSED 0x3
+
+/* J7200 */
+
+#define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0
+#define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1
+#define J7200_SERDES0_LANE0_IP3_UNUSED 0x2
+#define J7200_SERDES0_LANE0_IP4_UNUSED 0x3
+
+#define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0
+#define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1
+#define J7200_SERDES0_LANE1_IP3_UNUSED 0x2
+#define J7200_SERDES0_LANE1_IP4_UNUSED 0x3
+
+#define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0
+#define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1
+#define J7200_SERDES0_LANE2_IP3_UNUSED 0x2
+#define J7200_SERDES0_LANE2_IP4_UNUSED 0x3
+
+#define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0
+#define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1
+#define J7200_SERDES0_LANE3_USB 0x2
+#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3
+
+/* AM64 */
+
+#define AM64_SERDES0_LANE0_PCIE0 0x0
+#define AM64_SERDES0_LANE0_USB 0x1
+
+/* J721S2 */
+
+#define J721S2_SERDES0_LANE0_EDP_LANE0 0x0
+#define J721S2_SERDES0_LANE0_PCIE1_LANE0 0x1
+#define J721S2_SERDES0_LANE0_IP3_UNUSED 0x2
+#define J721S2_SERDES0_LANE0_IP4_UNUSED 0x3
+
+#define J721S2_SERDES0_LANE1_EDP_LANE1 0x0
+#define J721S2_SERDES0_LANE1_PCIE1_LANE1 0x1
+#define J721S2_SERDES0_LANE1_USB 0x2
+#define J721S2_SERDES0_LANE1_IP4_UNUSED 0x3
+
+#define J721S2_SERDES0_LANE2_EDP_LANE2 0x0
+#define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1
+#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2
+#define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3
+
+#define J721S2_SERDES0_LANE3_EDP_LANE3 0x0
+#define J721S2_SERDES0_LANE3_PCIE1_LANE3 0x1
+#define J721S2_SERDES0_LANE3_USB 0x2
+#define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3
+
+/* J784S4 */
+
+#define J784S4_SERDES0_LANE0_IP1_UNUSED 0x0
+#define J784S4_SERDES0_LANE0_PCIE1_LANE0 0x1
+#define J784S4_SERDES0_LANE0_IP3_UNUSED 0x2
+#define J784S4_SERDES0_LANE0_IP4_UNUSED 0x3
+
+#define J784S4_SERDES0_LANE1_IP1_UNUSED 0x0
+#define J784S4_SERDES0_LANE1_PCIE1_LANE1 0x1
+#define J784S4_SERDES0_LANE1_IP3_UNUSED 0x2
+#define J784S4_SERDES0_LANE1_IP4_UNUSED 0x3
+
+#define J784S4_SERDES0_LANE2_PCIE3_LANE0 0x0
+#define J784S4_SERDES0_LANE2_PCIE1_LANE2 0x1
+#define J784S4_SERDES0_LANE2_IP3_UNUSED 0x2
+#define J784S4_SERDES0_LANE2_IP4_UNUSED 0x3
+
+#define J784S4_SERDES0_LANE3_PCIE3_LANE1 0x0
+#define J784S4_SERDES0_LANE3_PCIE1_LANE3 0x1
+#define J784S4_SERDES0_LANE3_USB 0x2
+#define J784S4_SERDES0_LANE3_IP4_UNUSED 0x3
+
+#define J784S4_SERDES1_LANE0_QSGMII_LANE3 0x0
+#define J784S4_SERDES1_LANE0_PCIE0_LANE0 0x1
+#define J784S4_SERDES1_LANE0_IP3_UNUSED 0x2
+#define J784S4_SERDES1_LANE0_IP4_UNUSED 0x3
+
+#define J784S4_SERDES1_LANE1_QSGMII_LANE4 0x0
+#define J784S4_SERDES1_LANE1_PCIE0_LANE1 0x1
+#define J784S4_SERDES1_LANE1_IP3_UNUSED 0x2
+#define J784S4_SERDES1_LANE1_IP4_UNUSED 0x3
+
+#define J784S4_SERDES1_LANE2_QSGMII_LANE1 0x0
+#define J784S4_SERDES1_LANE2_PCIE0_LANE2 0x1
+#define J784S4_SERDES1_LANE2_PCIE2_LANE0 0x2
+#define J784S4_SERDES1_LANE2_IP4_UNUSED 0x3
+
+#define J784S4_SERDES1_LANE3_QSGMII_LANE2 0x0
+#define J784S4_SERDES1_LANE3_PCIE0_LANE3 0x1
+#define J784S4_SERDES1_LANE3_PCIE2_LANE1 0x2
+#define J784S4_SERDES1_LANE3_IP4_UNUSED 0x3
+
+#define J784S4_SERDES2_LANE0_QSGMII_LANE5 0x0
+#define J784S4_SERDES2_LANE0_IP2_UNUSED 0x1
+#define J784S4_SERDES2_LANE0_IP3_UNUSED 0x2
+#define J784S4_SERDES2_LANE0_IP4_UNUSED 0x3
+
+#define J784S4_SERDES2_LANE1_QSGMII_LANE6 0x0
+#define J784S4_SERDES2_LANE1_IP2_UNUSED 0x1
+#define J784S4_SERDES2_LANE1_IP3_UNUSED 0x2
+#define J784S4_SERDES2_LANE1_IP4_UNUSED 0x3
+
+#define J784S4_SERDES2_LANE2_QSGMII_LANE7 0x0
+#define J784S4_SERDES2_LANE2_QSGMII_LANE1 0x1
+#define J784S4_SERDES2_LANE2_IP3_UNUSED 0x2
+#define J784S4_SERDES2_LANE2_IP4_UNUSED 0x3
+
+#define J784S4_SERDES2_LANE3_QSGMII_LANE8 0x0
+#define J784S4_SERDES2_LANE3_QSGMII_LANE2 0x1
+#define J784S4_SERDES2_LANE3_IP3_UNUSED 0x2
+#define J784S4_SERDES2_LANE3_IP4_UNUSED 0x3
+
+#define J784S4_SERDES4_LANE0_EDP_LANE0 0x0
+#define J784S4_SERDES4_LANE0_QSGMII_LANE5 0x1
+#define J784S4_SERDES4_LANE0_IP3_UNUSED 0x2
+#define J784S4_SERDES4_LANE0_IP4_UNUSED 0x3
+
+#define J784S4_SERDES4_LANE1_EDP_LANE1 0x0
+#define J784S4_SERDES4_LANE1_QSGMII_LANE6 0x1
+#define J784S4_SERDES4_LANE1_IP3_UNUSED 0x2
+#define J784S4_SERDES4_LANE1_IP4_UNUSED 0x3
+
+#define J784S4_SERDES4_LANE2_EDP_LANE2 0x0
+#define J784S4_SERDES4_LANE2_QSGMII_LANE7 0x1
+#define J784S4_SERDES4_LANE2_IP3_UNUSED 0x2
+#define J784S4_SERDES4_LANE2_IP4_UNUSED 0x3
+
+#define J784S4_SERDES4_LANE3_EDP_LANE3 0x0
+#define J784S4_SERDES4_LANE3_QSGMII_LANE8 0x1
+#define J784S4_SERDES4_LANE3_USB 0x2
+#define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3
+
+#endif /* DTS_ARM64_TI_K3_SERDES_H */
diff --git a/arch/arm/dts/keystone-clocks.dtsi b/arch/arm/dts/keystone-clocks.dtsi
index 457515b..33742d8 100644
--- a/arch/arm/dts/keystone-clocks.dtsi
+++ b/arch/arm/dts/keystone-clocks.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Source for Keystone 2 clock tree
*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
clocks {
diff --git a/arch/arm/dts/keystone-k2e-clocks.dtsi b/arch/arm/dts/keystone-k2e-clocks.dtsi
index f759215..46f8ab3 100644
--- a/arch/arm/dts/keystone-k2e-clocks.dtsi
+++ b/arch/arm/dts/keystone-k2e-clocks.dtsi
@@ -2,7 +2,7 @@
/*
* Keystone 2 Edison SoC specific device tree
*
- * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
clocks {
diff --git a/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi
index 970d452..953c750 100644
--- a/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/{
diff --git a/arch/arm/dts/keystone-k2e-evm.dts b/arch/arm/dts/keystone-k2e-evm.dts
index ed76e56..bf88444 100644
--- a/arch/arm/dts/keystone-k2e-evm.dts
+++ b/arch/arm/dts/keystone-k2e-evm.dts
@@ -2,7 +2,7 @@
/*
* Keystone 2 Edison EVM device tree
*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/dts/keystone-k2e-netcp.dtsi b/arch/arm/dts/keystone-k2e-netcp.dtsi
index 45ebb0a..dd61503 100644
--- a/arch/arm/dts/keystone-k2e-netcp.dtsi
+++ b/arch/arm/dts/keystone-k2e-netcp.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Source for Keystone 2 Edison Netcp driver
*
- * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
qmss: qmss@2a40000 {
diff --git a/arch/arm/dts/keystone-k2e.dtsi b/arch/arm/dts/keystone-k2e.dtsi
index 496bb31..449cddc 100644
--- a/arch/arm/dts/keystone-k2e.dtsi
+++ b/arch/arm/dts/keystone-k2e.dtsi
@@ -2,7 +2,7 @@
/*
* Keystone 2 Edison soc device tree
*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
diff --git a/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi
index 05653af..72b67b2 100644
--- a/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/{
diff --git a/arch/arm/dts/keystone-k2g-evm.dts b/arch/arm/dts/keystone-k2g-evm.dts
index 6376c62..491fdc4 100644
--- a/arch/arm/dts/keystone-k2g-evm.dts
+++ b/arch/arm/dts/keystone-k2g-evm.dts
@@ -2,7 +2,7 @@
/*
* Device Tree Source for K2G EVM
*
- * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi b/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi
index 8e4b36c..3634ed7 100644
--- a/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/{
diff --git a/arch/arm/dts/keystone-k2g-generic.dts b/arch/arm/dts/keystone-k2g-generic.dts
index fc938a4..dc6c31a 100644
--- a/arch/arm/dts/keystone-k2g-generic.dts
+++ b/arch/arm/dts/keystone-k2g-generic.dts
@@ -2,7 +2,7 @@
/*
* Device Tree Source for Generic 66AK2G0X EVM
*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi b/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi
index 8e4b36c..3634ed7 100644
--- a/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/{
diff --git a/arch/arm/dts/keystone-k2g-ice.dts b/arch/arm/dts/keystone-k2g-ice.dts
index cbdb6bf..b898ae6 100644
--- a/arch/arm/dts/keystone-k2g-ice.dts
+++ b/arch/arm/dts/keystone-k2g-ice.dts
@@ -2,7 +2,7 @@
/*
* Device Tree Source for K2G Industrial Communication Engine EVM
*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/dts/keystone-k2g-netcp.dtsi b/arch/arm/dts/keystone-k2g-netcp.dtsi
index 136cd20..2afb488 100644
--- a/arch/arm/dts/keystone-k2g-netcp.dtsi
+++ b/arch/arm/dts/keystone-k2g-netcp.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Source for K2G Netcp driver
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
qmss: qmss@4020000 {
diff --git a/arch/arm/dts/keystone-k2g.dtsi b/arch/arm/dts/keystone-k2g.dtsi
index f12af43..5c3ff12 100644
--- a/arch/arm/dts/keystone-k2g.dtsi
+++ b/arch/arm/dts/keystone-k2g.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Source for K2G SOC
*
- * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/arch/arm/dts/keystone-k2hk-clocks.dtsi b/arch/arm/dts/keystone-k2hk-clocks.dtsi
index 4ba6912..3ca4722 100644
--- a/arch/arm/dts/keystone-k2hk-clocks.dtsi
+++ b/arch/arm/dts/keystone-k2hk-clocks.dtsi
@@ -2,7 +2,7 @@
/*
* Keystone 2 Kepler/Hawking SoC clock nodes
*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
clocks {
diff --git a/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi
index 22df84b..3e38f22 100644
--- a/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/{
diff --git a/arch/arm/dts/keystone-k2hk-evm.dts b/arch/arm/dts/keystone-k2hk-evm.dts
index ea53f3f..6222876 100644
--- a/arch/arm/dts/keystone-k2hk-evm.dts
+++ b/arch/arm/dts/keystone-k2hk-evm.dts
@@ -2,7 +2,7 @@
/*
* Keystone 2 Kepler/Hawking EVM device tree
*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/dts/keystone-k2hk-netcp.dtsi b/arch/arm/dts/keystone-k2hk-netcp.dtsi
index 580af63..3f8c4c2 100644
--- a/arch/arm/dts/keystone-k2hk-netcp.dtsi
+++ b/arch/arm/dts/keystone-k2hk-netcp.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Source for Keystone 2 Hawking Netcp driver
*
- * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
qmss: qmss@2a40000 {
diff --git a/arch/arm/dts/keystone-k2hk.dtsi b/arch/arm/dts/keystone-k2hk.dtsi
index ef02f23..e5ab1fb 100644
--- a/arch/arm/dts/keystone-k2hk.dtsi
+++ b/arch/arm/dts/keystone-k2hk.dtsi
@@ -2,7 +2,7 @@
/*
* Keystone 2 Kepler/Hawking soc specific device tree
*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
diff --git a/arch/arm/dts/keystone-k2l-clocks.dtsi b/arch/arm/dts/keystone-k2l-clocks.dtsi
index 6355280..fcfc2fb 100644
--- a/arch/arm/dts/keystone-k2l-clocks.dtsi
+++ b/arch/arm/dts/keystone-k2l-clocks.dtsi
@@ -2,7 +2,7 @@
/*
* Keystone 2 lamarr SoC clock nodes
*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
clocks {
diff --git a/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi
index 0a507d0..f1aed14 100644
--- a/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
&usb_phy {
diff --git a/arch/arm/dts/keystone-k2l-evm.dts b/arch/arm/dts/keystone-k2l-evm.dts
index 187f2ca..9d2b454 100644
--- a/arch/arm/dts/keystone-k2l-evm.dts
+++ b/arch/arm/dts/keystone-k2l-evm.dts
@@ -2,7 +2,7 @@
/*
* Keystone 2 Lamarr EVM device tree
*
- * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/dts/keystone-k2l-netcp.dtsi b/arch/arm/dts/keystone-k2l-netcp.dtsi
index 54c1128..2caa058 100644
--- a/arch/arm/dts/keystone-k2l-netcp.dtsi
+++ b/arch/arm/dts/keystone-k2l-netcp.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Source for Keystone 2 Lamarr Netcp driver
*
- * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
qmss: qmss@2a40000 {
diff --git a/arch/arm/dts/keystone-k2l.dtsi b/arch/arm/dts/keystone-k2l.dtsi
index dcc83a7..c8893e2 100644
--- a/arch/arm/dts/keystone-k2l.dtsi
+++ b/arch/arm/dts/keystone-k2l.dtsi
@@ -2,7 +2,7 @@
/*
* Keystone 2 Lamarr SoC specific device tree
*
- * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
diff --git a/arch/arm/dts/keystone.dtsi b/arch/arm/dts/keystone.dtsi
index 2afcab7..1538cce 100644
--- a/arch/arm/dts/keystone.dtsi
+++ b/arch/arm/dts/keystone.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/arch/arm/dts/kirkwood-6282.dtsi b/arch/arm/dts/kirkwood-6282.dtsi
new file mode 100644
index 0000000..e732c50
--- /dev/null
+++ b/arch/arm/dts/kirkwood-6282.dtsi
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+ mbus@f1000000 {
+ pciec: pcie@82000000 {
+ compatible = "marvell,kirkwood-pcie";
+ status = "disabled";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ bus-range = <0x00 0xff>;
+
+ ranges =
+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
+ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
+ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
+ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */
+ 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>;
+
+ pcie0: pcie@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ bus-range = <0x00 0xff>;
+ interrupt-names = "intx", "error";
+ interrupts = <9>, <44>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie0_intc 0>,
+ <0 0 0 2 &pcie0_intc 1>,
+ <0 0 0 3 &pcie0_intc 2>,
+ <0 0 0 4 &pcie0_intc 3>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gate_clk 2>;
+ status = "disabled";
+
+ pcie0_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ pcie1: pcie@2,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
+ reg = <0x1000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+ 0x81000000 0 0 0x81000000 0x2 0 1 0>;
+ bus-range = <0x00 0xff>;
+ interrupt-names = "intx", "error";
+ interrupts = <10>, <45>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>,
+ <0 0 0 2 &pcie1_intc 1>,
+ <0 0 0 3 &pcie1_intc 2>,
+ <0 0 0 4 &pcie1_intc 3>;
+ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gate_clk 18>;
+ status = "disabled";
+
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+ };
+ ocp@f1000000 {
+
+ pinctrl: pin-controller@10000 {
+ compatible = "marvell,88f6282-pinctrl";
+
+ pmx_sata0: pmx-sata0 {
+ marvell,pins = "mpp5", "mpp21", "mpp23";
+ marvell,function = "sata0";
+ };
+ pmx_sata1: pmx-sata1 {
+ marvell,pins = "mpp4", "mpp20", "mpp22";
+ marvell,function = "sata1";
+ };
+
+ /*
+ * Default I2C1 pinctrl setting on mpp36/mpp37,
+ * overwrite marvell,pins on board level if required.
+ */
+ pmx_twsi1: pmx-twsi1 {
+ marvell,pins = "mpp36", "mpp37";
+ marvell,function = "twsi1";
+ };
+
+ pmx_sdio: pmx-sdio {
+ marvell,pins = "mpp12", "mpp13", "mpp14",
+ "mpp15", "mpp16", "mpp17";
+ marvell,function = "sdio";
+ };
+ };
+
+ thermal: thermal@10078 {
+ compatible = "marvell,kirkwood-thermal";
+ reg = <0x10078 0x4>;
+ status = "okay";
+ };
+
+ rtc: rtc@10300 {
+ compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
+ reg = <0x10300 0x20>;
+ interrupts = <53>;
+ clocks = <&gate_clk 7>;
+ };
+
+ i2c1: i2c@11100 {
+ compatible = "marvell,mv64xxx-i2c";
+ reg = <0x11100 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <32>;
+ clock-frequency = <100000>;
+ clocks = <&gate_clk 7>;
+ pinctrl-0 = <&pmx_twsi1>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ sata: sata@80000 {
+ compatible = "marvell,orion-sata";
+ reg = <0x80000 0x5000>;
+ interrupts = <21>;
+ clocks = <&gate_clk 14>, <&gate_clk 15>;
+ clock-names = "0", "1";
+ phys = <&sata_phy0>, <&sata_phy1>;
+ phy-names = "port0", "port1";
+ status = "disabled";
+ };
+
+ sdio: mvsdio@90000 {
+ compatible = "marvell,orion-sdio";
+ reg = <0x90000 0x200>;
+ interrupts = <28>;
+ clocks = <&gate_clk 4>;
+ pinctrl-0 = <&pmx_sdio>;
+ pinctrl-names = "default";
+ bus-width = <4>;
+ cap-sdio-irq;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/kirkwood-nsa325.dts b/arch/arm/dts/kirkwood-nsa325.dts
new file mode 100644
index 0000000..efc57cf
--- /dev/null
+++ b/arch/arm/dts/kirkwood-nsa325.dts
@@ -0,0 +1,231 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Device tree file for the Zyxel NSA 325 NAS box.
+ *
+ * Copyright (c) 2015, Hans Ulli Kroll <ulli.kroll@googlemail.com>
+ *
+ *
+ * Based upon the board setup file created by Peter Schildmann
+ */
+
+/dts-v1/;
+
+#include "kirkwood-nsa3x0-common.dtsi"
+
+/ {
+ model = "ZyXEL NSA325";
+ compatible = "zyxel,nsa325", "marvell,kirkwood-88f6282", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x20000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ stdout-path = &uart0;
+ };
+
+ ocp@f1000000 {
+ pinctrl: pin-controller@10000 {
+ pinctrl-names = "default";
+
+ pmx_led_hdd2_green: pmx-led-hdd2-green {
+ marvell,pins = "mpp12";
+ marvell,function = "gpio";
+ };
+
+ pmx_led_hdd2_red: pmx-led-hdd2-red {
+ marvell,pins = "mpp13";
+ marvell,function = "gpio";
+ };
+
+ pmx_mcu_data: pmx-mcu-data {
+ marvell,pins = "mpp14";
+ marvell,function = "gpio";
+ };
+
+ pmx_led_usb_green: pmx-led-usb-green {
+ marvell,pins = "mpp15";
+ marvell,function = "gpio";
+ };
+
+ pmx_mcu_clk: pmx-mcu-clk {
+ marvell,pins = "mpp16";
+ marvell,function = "gpio";
+ };
+
+ pmx_mcu_act: pmx-mcu-act {
+ marvell,pins = "mpp17";
+ marvell,function = "gpio";
+ };
+
+ pmx_led_sys_green: pmx-led-sys-green {
+ marvell,pins = "mpp28";
+ marvell,function = "gpio";
+ };
+
+ pmx_led_sys_orange: pmx-led-sys-orange {
+ marvell,pins = "mpp29";
+ marvell,function = "gpio";
+ };
+
+ pmx_led_hdd1_green: pmx-led-hdd1-green {
+ marvell,pins = "mpp41";
+ marvell,function = "gpio";
+ };
+
+ pmx_led_hdd1_red: pmx-led-hdd1-red {
+ marvell,pins = "mpp42";
+ marvell,function = "gpio";
+ };
+
+ pmx_htp: pmx-htp {
+ marvell,pins = "mpp43";
+ marvell,function = "gpio";
+ };
+
+ /*
+ * Buzzer needs to be switched at around 1kHz so is
+ * not compatible with the gpio-beeper driver.
+ */
+ pmx_buzzer: pmx-buzzer {
+ marvell,pins = "mpp44";
+ marvell,function = "gpio";
+ };
+
+ pmx_vid_b1: pmx-vid-b1 {
+ marvell,pins = "mpp45";
+ marvell,function = "gpio";
+ };
+
+ pmx_power_resume_data: pmx-power-resume-data {
+ marvell,pins = "mpp47";
+ marvell,function = "gpio";
+ };
+
+ pmx_power_resume_clk: pmx-power-resume-clk {
+ marvell,pins = "mpp49";
+ marvell,function = "gpio";
+ };
+
+ pmx_pwr_sata1: pmx-pwr-sata1 {
+ marvell,pins = "mpp47";
+ marvell,function = "gpio";
+ };
+ };
+
+ /* This board uses the pcf8563 RTC instead of the SoC RTC */
+ rtc@10300 {
+ status = "disabled";
+ };
+
+ i2c@11000 {
+ status = "okay";
+
+ pcf8563: pcf8563@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_pwr_sata1>;
+ pinctrl-names = "default";
+
+ usb0_power: regulator@1 {
+ enable-active-high;
+ };
+
+ sata1_power: regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "SATA1 Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red
+ &pmx_led_usb_green
+ &pmx_led_sys_green &pmx_led_sys_orange
+ &pmx_led_copy_green &pmx_led_copy_red
+ &pmx_led_hdd1_green &pmx_led_hdd1_red>;
+ pinctrl-names = "default";
+
+ green-sys {
+ label = "nsa325:green:sys";
+ gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
+ };
+ orange-sys {
+ label = "nsa325:orange:sys";
+ gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+ };
+ green-hdd1 {
+ label = "nsa325:green:hdd1";
+ gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ };
+ red-hdd1 {
+ label = "nsa325:red:hdd1";
+ gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ };
+ green-hdd2 {
+ label = "nsa325:green:hdd2";
+ gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ };
+ red-hdd2 {
+ label = "nsa325:red:hdd2";
+ gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+ };
+ green-usb {
+ label = "nsa325:green:usb";
+ gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
+ };
+ green-copy {
+ label = "nsa325:green:copy";
+ gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ };
+ red-copy {
+ label = "nsa325:red:copy";
+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* The following pins are currently not assigned to a driver,
+ some of them should be configured as inputs.
+ pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act
+ &pmx_htp &pmx_vid_b1
+ &pmx_power_resume_data &pmx_power_resume_clk>; */
+ };
+
+};
+
+&mdio {
+ status = "okay";
+ ethphy0: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+ð0 {
+ status = "okay";
+ ethernet0-port@0 {
+ phy-handle = <ðphy0>;
+ };
+};
+
+&pciec {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/kirkwood-nsa3x0-common.dtsi b/arch/arm/dts/kirkwood-nsa3x0-common.dtsi
new file mode 100644
index 0000000..a21c50d
--- /dev/null
+++ b/arch/arm/dts/kirkwood-nsa3x0-common.dtsi
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+ model = "ZyXEL NSA310";
+
+ ocp@f1000000 {
+ pinctrl: pin-controller@10000 {
+
+ pmx_usb_power: pmx-usb-power {
+ marvell,pins = "mpp21";
+ marvell,function = "gpio";
+ };
+
+ pmx_pwr_off: pmx-pwr-off {
+ marvell,pins = "mpp48";
+ marvell,function = "gpio";
+ };
+
+ pmx_btn_reset: pmx-btn-reset {
+ marvell,pins = "mpp36";
+ marvell,function = "gpio";
+ };
+
+ pmx_btn_copy: pmx-btn-copy {
+ marvell,pins = "mpp37";
+ marvell,function = "gpio";
+ };
+
+ pmx_btn_power: pmx-btn-power {
+ marvell,pins = "mpp46";
+ marvell,function = "gpio";
+ };
+
+ pmx_led_copy_green: pmx-led-copy-green {
+ marvell,pins = "mpp39";
+ marvell,function = "gpio";
+ };
+
+ pmx_led_copy_red: pmx-led-copy-red {
+ marvell,pins = "mpp40";
+ marvell,function = "gpio";
+ };
+ };
+
+ serial@12000 {
+ status = "okay";
+ };
+
+ sata@80000 {
+ status = "okay";
+ nr-ports = <2>;
+ };
+ };
+
+ gpio_poweroff {
+ compatible = "gpio-poweroff";
+ pinctrl-0 = <&pmx_pwr_off>;
+ pinctrl-names = "default";
+ gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>;
+ pinctrl-names = "default";
+
+ power {
+ label = "Power Button";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ };
+ copy {
+ label = "Copy Button";
+ linux,code = <KEY_COPY>;
+ gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+ };
+ reset {
+ label = "Reset Button";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_usb_power>;
+ pinctrl-names = "default";
+
+ usb0_power: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "USB Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&nand {
+ status = "okay";
+ chip-delay = <35>;
+
+ partition@0 {
+ label = "uboot";
+ reg = <0x0000000 0x0100000>;
+ };
+ partition@100000 {
+ label = "uboot_env";
+ reg = <0x0100000 0x0080000>;
+ };
+ partition@180000 {
+ label = "key_store";
+ reg = <0x0180000 0x0080000>;
+ };
+ partition@200000 {
+ label = "info";
+ reg = <0x0200000 0x0080000>;
+ };
+ partition@280000 {
+ label = "etc";
+ reg = <0x0280000 0x0a00000>;
+ };
+ partition@c80000 {
+ label = "kernel_1";
+ reg = <0x0c80000 0x0a00000>;
+ };
+ partition@1680000 {
+ label = "rootfs1";
+ reg = <0x1680000 0x2fc0000>;
+ };
+ partition@4640000 {
+ label = "kernel_2";
+ reg = <0x4640000 0x0a00000>;
+ };
+ partition@5040000 {
+ label = "rootfs2";
+ reg = <0x5040000 0x2fc0000>;
+ };
+};
+
+&pciec {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/meson-a1.dtsi b/arch/arm/dts/meson-a1.dtsi
index 6509329..648e7f4 100644
--- a/arch/arm/dts/meson-a1.dtsi
+++ b/arch/arm/dts/meson-a1.dtsi
@@ -3,9 +3,13 @@
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
+#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
#include <dt-bindings/gpio/meson-a1-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/meson-a1-power.h>
+#include <dt-bindings/reset/amlogic,meson-a1-reset.h>
/ {
compatible = "amlogic,a1";
@@ -37,9 +41,19 @@
l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
};
};
+ efuse: efuse {
+ compatible = "amlogic,meson-gxbb-efuse";
+ clocks = <&clkc_periphs CLKID_OTP>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ secure-monitor = <&sm>;
+ power-domains = <&pwrc PWRC_OTP_ID>;
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -65,7 +79,6 @@
pwrc: power-controller {
compatible = "amlogic,meson-a1-pwrc";
#power-domain-cells = <1>;
- status = "okay";
};
};
@@ -75,6 +88,16 @@
#size-cells = <2>;
ranges;
+ spifc: spi@fd000400 {
+ compatible = "amlogic,a1-spifc";
+ reg = <0x0 0xfd000400 0x0 0x290>;
+ clocks = <&clkc_periphs CLKID_SPIFC>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&pwrc PWRC_SPIFC_ID>;
+ status = "disabled";
+ };
+
apb: bus@fe000000 {
compatible = "simple-bus";
reg = <0x0 0xfe000000 0x0 0x1000000>;
@@ -103,10 +126,200 @@
gpio-ranges = <&periphs_pinctrl 0 0 62>;
};
+ i2c0_f11_pins: i2c0-f11 {
+ mux {
+ groups = "i2c0_sck_f11",
+ "i2c0_sda_f12";
+ function = "i2c0";
+ bias-pull-up;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c0_f9_pins: i2c0-f9 {
+ mux {
+ groups = "i2c0_sck_f9",
+ "i2c0_sda_f10";
+ function = "i2c0";
+ bias-pull-up;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c1_x_pins: i2c1-x {
+ mux {
+ groups = "i2c1_sck_x",
+ "i2c1_sda_x";
+ function = "i2c1";
+ bias-pull-up;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c1_a_pins: i2c1-a {
+ mux {
+ groups = "i2c1_sck_a",
+ "i2c1_sda_a";
+ function = "i2c1";
+ bias-pull-up;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c2_x0_pins: i2c2-x0 {
+ mux {
+ groups = "i2c2_sck_x0",
+ "i2c2_sda_x1";
+ function = "i2c2";
+ bias-pull-up;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c2_x15_pins: i2c2-x15 {
+ mux {
+ groups = "i2c2_sck_x15",
+ "i2c2_sda_x16";
+ function = "i2c2";
+ bias-pull-up;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c2_a4_pins: i2c2-a4 {
+ mux {
+ groups = "i2c2_sck_a4",
+ "i2c2_sda_a5";
+ function = "i2c2";
+ bias-pull-up;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c2_a8_pins: i2c2-a8 {
+ mux {
+ groups = "i2c2_sck_a8",
+ "i2c2_sda_a9";
+ function = "i2c2";
+ bias-pull-up;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c3_x_pins: i2c3-x {
+ mux {
+ groups = "i2c3_sck_x",
+ "i2c3_sda_x";
+ function = "i2c3";
+ bias-pull-up;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c3_f_pins: i2c3-f {
+ mux {
+ groups = "i2c3_sck_f",
+ "i2c3_sda_f";
+ function = "i2c3";
+ bias-pull-up;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ uart_a_pins: uart-a {
+ mux {
+ groups = "uart_a_tx",
+ "uart_a_rx";
+ function = "uart_a";
+ };
+ };
+
+ uart_a_cts_rts_pins: uart-a-cts-rts {
+ mux {
+ groups = "uart_a_cts",
+ "uart_a_rts";
+ function = "uart_a";
+ bias-pull-down;
+ };
+ };
+
+ sdio_pins: sdio {
+ mux0 {
+ groups = "sdcard_d0_x",
+ "sdcard_d1_x",
+ "sdcard_d2_x",
+ "sdcard_d3_x",
+ "sdcard_cmd_x";
+ function = "sdcard";
+ bias-pull-up;
+ };
+
+ mux1 {
+ groups = "sdcard_clk_x";
+ function = "sdcard";
+ bias-disable;
+ };
+ };
+
+ sdio_clk_gate_pins: sdio-clk-gate {
+ mux {
+ groups = "sdcard_clk_x";
+ function = "sdcard";
+ bias-pull-down;
+ };
+ };
+
+ spifc_pins: spifc {
+ mux {
+ groups = "spif_mo",
+ "spif_mi",
+ "spif_clk",
+ "spif_cs",
+ "spif_hold_n",
+ "spif_wp_n";
+ function = "spif";
+ };
+ };
+ };
+
+ gpio_intc: interrupt-controller@440 {
+ compatible = "amlogic,meson-a1-gpio-intc",
+ "amlogic,meson-gpio-intc";
+ reg = <0x0 0x0440 0x0 0x14>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ amlogic,channel-interrupts =
+ <49 50 51 52 53 54 55 56>;
+ };
+
+ clkc_periphs: clock-controller@800 {
+ compatible = "amlogic,a1-peripherals-clkc";
+ reg = <0 0x800 0 0x104>;
+ #clock-cells = <1>;
+ clocks = <&clkc_pll CLKID_FCLK_DIV2>,
+ <&clkc_pll CLKID_FCLK_DIV3>,
+ <&clkc_pll CLKID_FCLK_DIV5>,
+ <&clkc_pll CLKID_FCLK_DIV7>,
+ <&clkc_pll CLKID_HIFI_PLL>,
+ <&xtal>;
+ clock-names = "fclk_div2", "fclk_div3",
+ "fclk_div5", "fclk_div7",
+ "hifi_pll", "xtal";
+ };
+
+ i2c0: i2c@1400 {
+ compatible = "amlogic,meson-axg-i2c";
+ status = "disabled";
+ reg = <0x0 0x1400 0x0 0x20>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc_periphs CLKID_I2C_M_A>;
+ power-domains = <&pwrc PWRC_I2C_ID>;
};
uart_AO: serial@1c00 {
- compatible = "amlogic,meson-gx-uart",
+ compatible = "amlogic,meson-a1-uart",
"amlogic,meson-ao-uart";
reg = <0x0 0x1c00 0x0 0x18>;
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
@@ -116,7 +329,7 @@
};
uart_AO_B: serial@2000 {
- compatible = "amlogic,meson-gx-uart",
+ compatible = "amlogic,meson-a1-uart",
"amlogic,meson-ao-uart";
reg = <0x0 0x2000 0x0 0x18>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
@@ -124,6 +337,150 @@
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
+
+ saradc: adc@2c00 {
+ compatible = "amlogic,meson-g12a-saradc",
+ "amlogic,meson-saradc";
+ reg = <0x0 0x2c00 0x0 0x48>;
+ #io-channel-cells = <1>;
+ power-domains = <&pwrc PWRC_I2C_ID>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>,
+ <&clkc_periphs CLKID_SARADC_EN>,
+ <&clkc_periphs CLKID_SARADC>,
+ <&clkc_periphs CLKID_SARADC_SEL>;
+ clock-names = "clkin", "core",
+ "adc_clk", "adc_sel";
+ status = "disabled";
+ };
+
+ i2c1: i2c@5c00 {
+ compatible = "amlogic,meson-axg-i2c";
+ status = "disabled";
+ reg = <0x0 0x5c00 0x0 0x20>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc_periphs CLKID_I2C_M_B>;
+ power-domains = <&pwrc PWRC_I2C_ID>;
+ };
+
+ i2c2: i2c@6800 {
+ compatible = "amlogic,meson-axg-i2c";
+ status = "disabled";
+ reg = <0x0 0x6800 0x0 0x20>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc_periphs CLKID_I2C_M_C>;
+ power-domains = <&pwrc PWRC_I2C_ID>;
+ };
+
+ i2c3: i2c@6c00 {
+ compatible = "amlogic,meson-axg-i2c";
+ status = "disabled";
+ reg = <0x0 0x6c00 0x0 0x20>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc_periphs CLKID_I2C_M_D>;
+ power-domains = <&pwrc PWRC_I2C_ID>;
+ };
+
+ usb2_phy1: phy@4000 {
+ compatible = "amlogic,a1-usb2-phy";
+ clocks = <&clkc_periphs CLKID_USB_PHY_IN>;
+ clock-names = "xtal";
+ reg = <0x0 0x4000 0x0 0x60>;
+ resets = <&reset RESET_USBPHY>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ power-domains = <&pwrc PWRC_USB_ID>;
+ };
+
+ hwrng: rng@5118 {
+ compatible = "amlogic,meson-rng";
+ reg = <0x0 0x5118 0x0 0x4>;
+ power-domains = <&pwrc PWRC_OTP_ID>;
+ };
+
+ sec_AO: ao-secure@5a20 {
+ compatible = "amlogic,meson-gx-ao-secure", "syscon";
+ reg = <0x0 0x5a20 0x0 0x140>;
+ amlogic,has-chip-id;
+ };
+
+ clkc_pll: pll-clock-controller@7c80 {
+ compatible = "amlogic,a1-pll-clkc";
+ reg = <0 0x7c80 0 0x18c>;
+ #clock-cells = <1>;
+ clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
+ <&clkc_periphs CLKID_HIFIPLL_IN>;
+ clock-names = "fixpll_in", "hifipll_in";
+ };
+
+ sd_emmc: sd@10000 {
+ compatible = "amlogic,meson-axg-mmc";
+ reg = <0x0 0x10000 0x0 0x800>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc_periphs CLKID_SD_EMMC_A>,
+ <&clkc_periphs CLKID_SD_EMMC>,
+ <&clkc_pll CLKID_FCLK_DIV2>;
+ clock-names = "core",
+ "clkin0",
+ "clkin1";
+ assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_SEL2>;
+ assigned-clock-parents = <&xtal>;
+ resets = <&reset RESET_SD_EMMC_A>;
+ power-domains = <&pwrc PWRC_SD_EMMC_ID>;
+ status = "disabled";
+ };
+ };
+
+ usb: usb@fe004400 {
+ status = "disabled";
+ compatible = "amlogic,meson-a1-usb-ctrl";
+ reg = <0x0 0xfe004400 0x0 0xa0>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&clkc_periphs CLKID_USB_CTRL>,
+ <&clkc_periphs CLKID_USB_BUS>,
+ <&clkc_periphs CLKID_USB_CTRL_IN>;
+ clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl";
+ resets = <&reset RESET_USBCTRL>;
+ reset-name = "usb_ctrl";
+
+ dr_mode = "otg";
+
+ phys = <&usb2_phy1>;
+ phy-names = "usb2-phy1";
+
+ dwc3: usb@ff400000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xff400000 0x0 0x100000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,dis_u2_susphy_quirk;
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,parkmode-disable-ss-quirk;
+ };
+
+ dwc2: usb@ff500000 {
+ compatible = "amlogic,meson-a1-usb", "snps,dwc2";
+ reg = <0x0 0xff500000 0x0 0x40000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb2_phy1>;
+ phy-names = "usb2-phy";
+ clocks = <&clkc_periphs CLKID_USB_PHY>;
+ clock-names = "otg";
+ dr_mode = "peripheral";
+ g-rx-fifo-size = <192>;
+ g-np-tx-fifo-size = <128>;
+ g-tx-fifo-size = <128 128 16 16 16>;
+ };
};
gic: interrupt-controller@ff901000 {
diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi
index ddd629e..ac476d5 100644
--- a/arch/arm/dts/mt7988.dtsi
+++ b/arch/arm/dts/mt7988.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/clock/mt7988-clk.h>
#include <dt-bindings/reset/mt7988-reset.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
/ {
compatible = "mediatek,mt7988-rfb";
@@ -161,6 +162,65 @@
#clock-cells = <1>;
};
+ dummy_clk: dummy12m {
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ #clock-cells = <0>;
+ /* must need this line, or uart uanable to get dummy_clk */
+ bootph-all;
+ };
+
+ xhci1: xhci@11200000 {
+ compatible = "mediatek,mt7988-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x2e00>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&tphyu2port0 PHY_TYPE_USB2>,
+ <&tphyu3port0 PHY_TYPE_USB3>;
+ clocks = <&dummy_clk>,
+ <&dummy_clk>,
+ <&dummy_clk>,
+ <&dummy_clk>,
+ <&dummy_clk>;
+ clock-names = "sys_ck",
+ "xhci_ck",
+ "ref_ck",
+ "mcu_ck",
+ "dma_ck";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ status = "okay";
+ };
+
+ usbtphy: usb-phy@11c50000 {
+ compatible = "mediatek,mt7988",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "okay";
+
+ tphyu2port0: usb-phy@11c50000 {
+ reg = <0 0x11c50000 0 0x700>;
+ clocks = <&dummy_clk>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ tphyu3port0: usb-phy@11c50700 {
+ reg = <0 0x11c50700 0 0x900>;
+ clocks = <&dummy_clk>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ mediatek,usb3-pll-ssc-delta;
+ mediatek,usb3-pll-ssc-delta1;
+ status = "okay";
+ };
+ };
+
xfi_pextp0: syscon@11f20000 {
compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";
reg = <0 0x11f20000 0 0x10000>;
diff --git a/arch/arm/dts/nuvoton-npcm845-evb.dts b/arch/arm/dts/nuvoton-npcm845-evb.dts
index 3cab780..a93666c 100644
--- a/arch/arm/dts/nuvoton-npcm845-evb.dts
+++ b/arch/arm/dts/nuvoton-npcm845-evb.dts
@@ -354,4 +354,4 @@
&r1en_pins
&r1oen_pins
>;
-};
\ No newline at end of file
+};
diff --git a/arch/arm/dts/omap3-u-boot.dtsi b/arch/arm/dts/omap3-u-boot.dtsi
index 7366ff5..bc27937 100644
--- a/arch/arm/dts/omap3-u-boot.dtsi
+++ b/arch/arm/dts/omap3-u-boot.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/dts/omap5-u-boot.dtsi b/arch/arm/dts/omap5-u-boot.dtsi
index 720e79b..d1de2e7 100644
--- a/arch/arm/dts/omap5-u-boot.dtsi
+++ b/arch/arm/dts/omap5-u-boot.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/dts/r7s72100-gr-peach.dts b/arch/arm/dts/r7s72100-gr-peach.dts
index 70d034c..105f9c7 100644
--- a/arch/arm/dts/r7s72100-gr-peach.dts
+++ b/arch/arm/dts/r7s72100-gr-peach.dts
@@ -41,6 +41,9 @@
bank-width = <4>;
device-width = <1>;
+ clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>;
+ power-domains = <&cpg_clocks>;
+
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/dts/r7s72100.dtsi b/arch/arm/dts/r7s72100.dtsi
index 2211f88..b07b713 100644
--- a/arch/arm/dts/r7s72100.dtsi
+++ b/arch/arm/dts/r7s72100.dtsi
@@ -313,9 +313,9 @@
mmcif: mmc@e804c800 {
compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
reg = <0xe804c800 0x80>;
- interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
power-domains = <&cpg_clocks>;
reg-io-width = <4>;
@@ -323,12 +323,12 @@
status = "disabled";
};
- sdhi0: sd@e804e000 {
+ sdhi0: mmc@e804e000 {
compatible = "renesas,sdhi-r7s72100";
reg = <0xe804e000 0x100>;
- interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
<&mstp12_clks R7S72100_CLK_SDHI01>;
@@ -339,12 +339,12 @@
status = "disabled";
};
- sdhi1: sd@e804e800 {
+ sdhi1: mmc@e804e800 {
compatible = "renesas,sdhi-r7s72100";
reg = <0xe804e800 0x100>;
- interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
<&mstp12_clks R7S72100_CLK_SDHI11>;
@@ -467,11 +467,12 @@
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0438 4>;
- clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
+ clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>, <&b_clk>, <&b_clk>;
clock-indices = <
R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
+ R7S72100_CLK_SPIBSC0 R7S72100_CLK_SPIBSC1
>;
- clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
+ clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "spibsc0", "spibsc1";
};
mstp10_clks: mstp10_clks@fcfe043c {
@@ -498,7 +499,7 @@
clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
};
- pinctrl: pin-controller@fcfe3000 {
+ pinctrl: pinctrl@fcfe3000 {
compatible = "renesas,r7s72100-ports";
reg = <0xfcfe3000 0x4230>;
@@ -607,6 +608,8 @@
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
clock-frequency = <100000>;
power-domains = <&cpg_clocks>;
@@ -626,6 +629,8 @@
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
clock-frequency = <100000>;
power-domains = <&cpg_clocks>;
@@ -645,6 +650,8 @@
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
clock-frequency = <100000>;
power-domains = <&cpg_clocks>;
@@ -664,12 +671,33 @@
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
clock-frequency = <100000>;
power-domains = <&cpg_clocks>;
status = "disabled";
};
+ irqc: interrupt-controller@fcfef800 {
+ compatible = "renesas,r7s72100-irqc",
+ "renesas,rza1-irqc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0xfcfef800 0x6>;
+ interrupt-map =
+ <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <7 0>;
+ };
+
mtu2: timer@fcff0000 {
compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
reg = <0xfcff0000 0x400>;
diff --git a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts
index 9ae6726..24da6ee 100644
--- a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts
+++ b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts
@@ -58,24 +58,3 @@
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
-
-/* Reference versaclock instead of audio_clk_a */
-&rcar_sound {
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&versaclock6_bb 4>, <&audio_clk_b>,
- <&audio_clk_c>,
- <&cpg CPG_CORE R8A774A1_CLK_S0D4>;
-};
diff --git a/arch/arm/dts/r8a774a1-u-boot.dtsi b/arch/arm/dts/r8a774a1-u-boot.dtsi
index cddffe8..38f5bfe 100644
--- a/arch/arm/dts/r8a774a1-u-boot.dtsi
+++ b/arch/arm/dts/r8a774a1-u-boot.dtsi
@@ -28,7 +28,6 @@
/delete-node/ &hdmi0;
/delete-node/ &lvds0;
/delete-node/ &rcar_sound;
-/delete-node/ &sdhi2;
/delete-node/ &sound_card;
/delete-node/ &vin0;
/delete-node/ &vin1;
diff --git a/arch/arm/dts/r8a774a1.dtsi b/arch/arm/dts/r8a774a1.dtsi
index 7e64324..9065dc2 100644
--- a/arch/arm/dts/r8a774a1.dtsi
+++ b/arch/arm/dts/r8a774a1.dtsi
@@ -1678,7 +1678,7 @@
rcar_sound: sound@ec500000 {
/*
- * #sound-dai-cells is required
+ * #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -2359,8 +2359,8 @@
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2371,6 +2371,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 319>;
+ iommu-map = <0 &ipmmu_hc 0 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
@@ -2386,8 +2388,8 @@
<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2398,6 +2400,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 318>;
+ iommu-map = <0 &ipmmu_hc 1 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
diff --git a/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts
index 89d7083..8b9df6a 100644
--- a/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts
+++ b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts
@@ -14,6 +14,14 @@
compatible = "beacon,beacon-rzg2n", "renesas,r8a774b1";
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &iic_pmic;
serial0 = &scif2;
serial1 = &hscif0;
serial2 = &hscif1;
@@ -46,24 +54,3 @@
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
-
-/* Reference versaclock instead of audio_clk_a */
-&rcar_sound {
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&versaclock6_bb 4>, <&audio_clk_b>,
- <&audio_clk_c>,
- <&cpg CPG_CORE R8A774B1_CLK_S0D4>;
-};
diff --git a/arch/arm/dts/r8a774b1-u-boot.dtsi b/arch/arm/dts/r8a774b1-u-boot.dtsi
index 3b34f82..d4890eb 100644
--- a/arch/arm/dts/r8a774b1-u-boot.dtsi
+++ b/arch/arm/dts/r8a774b1-u-boot.dtsi
@@ -27,7 +27,6 @@
/delete-node/ &hdmi0;
/delete-node/ &lvds0;
/delete-node/ &rcar_sound;
-/delete-node/ &sdhi2;
/delete-node/ &sound_card;
/delete-node/ &vin0;
/delete-node/ &vin1;
diff --git a/arch/arm/dts/r8a774b1.dtsi b/arch/arm/dts/r8a774b1.dtsi
index d541b48..75776de 100644
--- a/arch/arm/dts/r8a774b1.dtsi
+++ b/arch/arm/dts/r8a774b1.dtsi
@@ -1562,7 +1562,7 @@
rcar_sound: sound@ec500000 {
/*
- * #sound-dai-cells is required
+ * #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -2238,8 +2238,8 @@
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2250,6 +2250,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 319>;
+ iommu-map = <0 &ipmmu_hc 0 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
@@ -2265,8 +2267,8 @@
<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2277,6 +2279,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 318>;
+ iommu-map = <0 &ipmmu_hc 1 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
diff --git a/arch/arm/dts/r8a774c0.dtsi b/arch/arm/dts/r8a774c0.dtsi
index 151e32a..ad2e87b 100644
--- a/arch/arm/dts/r8a774c0.dtsi
+++ b/arch/arm/dts/r8a774c0.dtsi
@@ -49,17 +49,14 @@
opp-shared;
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <820000>;
clock-latency-ns = <300000>;
opp-suspend;
};
@@ -1317,7 +1314,7 @@
rcar_sound: sound@ec500000 {
/*
- * #sound-dai-cells is required
+ * #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -1707,8 +1704,8 @@
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -1719,6 +1716,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 319>;
+ iommu-map = <0 &ipmmu_hc 0 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
diff --git a/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
index 3e9ced3..146f78c 100644
--- a/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
+++ b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
@@ -14,6 +14,14 @@
compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1";
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &iic_pmic;
serial0 = &scif2;
serial1 = &hscif0;
serial2 = &hscif1;
@@ -51,24 +59,3 @@
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
-
-/* Reference versaclock instead of audio_clk_a */
-&rcar_sound {
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&versaclock6_bb 4>, <&audio_clk_b>,
- <&audio_clk_c>,
- <&cpg CPG_CORE R8A774E1_CLK_S0D4>;
-};
diff --git a/arch/arm/dts/r8a774e1-u-boot.dtsi b/arch/arm/dts/r8a774e1-u-boot.dtsi
index e862870..45ef5b7 100644
--- a/arch/arm/dts/r8a774e1-u-boot.dtsi
+++ b/arch/arm/dts/r8a774e1-u-boot.dtsi
@@ -30,7 +30,6 @@
/delete-node/ &hdmi0;
/delete-node/ &lvds0;
/delete-node/ &rcar_sound;
-/delete-node/ &sdhi2;
/delete-node/ &sound_card;
/delete-node/ &vin0;
/delete-node/ &vin1;
diff --git a/arch/arm/dts/r8a774e1.dtsi b/arch/arm/dts/r8a774e1.dtsi
index c5a0e78..2acf406 100644
--- a/arch/arm/dts/r8a774e1.dtsi
+++ b/arch/arm/dts/r8a774e1.dtsi
@@ -1774,7 +1774,7 @@
rcar_sound: sound@ec500000 {
/*
- * #sound-dai-cells is required
+ * #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -2471,8 +2471,8 @@
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2483,6 +2483,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 319>;
+ iommu-map = <0 &ipmmu_hc 0 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
@@ -2498,8 +2500,8 @@
<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2510,6 +2512,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 318>;
+ iommu-map = <0 &ipmmu_hc 1 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
diff --git a/arch/arm/dts/r8a7790.dtsi b/arch/arm/dts/r8a7790.dtsi
index db171e3..46fb81f 100644
--- a/arch/arm/dts/r8a7790.dtsi
+++ b/arch/arm/dts/r8a7790.dtsi
@@ -376,6 +376,17 @@
reg = <0 0xe6060000 0 0x250>;
};
+ tpu: pwm@e60f0000 {
+ compatible = "renesas,tpu-r8a7790", "renesas,tpu";
+ reg = <0 0xe60f0000 0 0x148>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 304>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 304>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7790-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
@@ -1037,6 +1048,76 @@
status = "disabled";
};
+ pwm0: pwm@e6e30000 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e30000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@e6e31000 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e31000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@e6e32000 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e32000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@e6e33000 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e33000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@e6e34000 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e34000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm5: pwm@e6e35000 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e35000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@e6e36000 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e36000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
can0: can@e6e80000 {
compatible = "renesas,can-r8a7790",
"renesas,rcar-gen2-can";
@@ -1109,7 +1190,7 @@
rcar_sound: sound@ec500000 {
/*
- * #sound-dai-cells is required
+ * #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -1252,7 +1333,7 @@
dma-names = "rx", "tx", "rxu", "txu";
};
ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x03>, <&audma1 0x04>,
<&audma0 0x49>, <&audma1 0x4a>;
dma-names = "rx", "tx", "rxu", "txu";
diff --git a/arch/arm/dts/r8a7791.dtsi b/arch/arm/dts/r8a7791.dtsi
index d8f91d9..b9d3414 100644
--- a/arch/arm/dts/r8a7791.dtsi
+++ b/arch/arm/dts/r8a7791.dtsi
@@ -1223,7 +1223,7 @@
rcar_sound: sound@ec500000 {
/*
- * #sound-dai-cells is required
+ * #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -1365,7 +1365,7 @@
dma-names = "rx", "tx", "rxu", "txu";
};
ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x03>, <&audma1 0x04>,
<&audma0 0x49>, <&audma1 0x4a>;
dma-names = "rx", "tx", "rxu", "txu";
diff --git a/arch/arm/dts/r8a7793.dtsi b/arch/arm/dts/r8a7793.dtsi
index 9ebe7bf..f51bf68 100644
--- a/arch/arm/dts/r8a7793.dtsi
+++ b/arch/arm/dts/r8a7793.dtsi
@@ -988,7 +988,7 @@
rcar_sound: sound@ec500000 {
/*
- * #sound-dai-cells is required
+ * #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -1111,7 +1111,7 @@
dma-names = "rx", "tx", "rxu", "txu";
};
ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x03>, <&audma1 0x04>,
<&audma0 0x49>, <&audma1 0x4a>;
dma-names = "rx", "tx", "rxu", "txu";
diff --git a/arch/arm/dts/r8a7794.dtsi b/arch/arm/dts/r8a7794.dtsi
index 7aa781f..371dd47 100644
--- a/arch/arm/dts/r8a7794.dtsi
+++ b/arch/arm/dts/r8a7794.dtsi
@@ -955,7 +955,7 @@
rcar_sound: sound@ec500000 {
/*
- * #sound-dai-cells is required
+ * #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
diff --git a/arch/arm/dts/r8a77951.dtsi b/arch/arm/dts/r8a77951.dtsi
index 07c8763..6d15229 100644
--- a/arch/arm/dts/r8a77951.dtsi
+++ b/arch/arm/dts/r8a77951.dtsi
@@ -75,7 +75,6 @@
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
- turbo-mode;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
@@ -1998,7 +1997,7 @@
rcar_sound: sound@ec500000 {
/*
- * #sound-dai-cells is required
+ * #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -2779,8 +2778,8 @@
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2791,6 +2790,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 319>;
+ iommu-map = <0 &ipmmu_hc 0 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
@@ -2806,8 +2807,8 @@
<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2818,6 +2819,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 318>;
+ iommu-map = <0 &ipmmu_hc 1 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
diff --git a/arch/arm/dts/r8a77960.dtsi b/arch/arm/dts/r8a77960.dtsi
index 1424d4a..17062ec 100644
--- a/arch/arm/dts/r8a77960.dtsi
+++ b/arch/arm/dts/r8a77960.dtsi
@@ -70,13 +70,11 @@
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
- turbo-mode;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
- turbo-mode;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
@@ -1870,7 +1868,7 @@
rcar_sound: sound@ec500000 {
/*
- * #sound-dai-cells is required
+ * #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -2567,8 +2565,8 @@
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2579,6 +2577,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 319>;
+ iommu-map = <0 &ipmmu_hc 0 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
@@ -2594,8 +2594,8 @@
<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2606,6 +2606,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 318>;
+ iommu-map = <0 &ipmmu_hc 1 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
diff --git a/arch/arm/dts/r8a77965.dtsi b/arch/arm/dts/r8a77965.dtsi
index 997f295..c758200 100644
--- a/arch/arm/dts/r8a77965.dtsi
+++ b/arch/arm/dts/r8a77965.dtsi
@@ -75,13 +75,11 @@
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
- turbo-mode;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
- turbo-mode;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
@@ -1733,7 +1731,7 @@
rcar_sound: sound@ec500000 {
/*
- * #sound-dai-cells is required
+ * #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -2425,8 +2423,8 @@
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2437,6 +2435,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 319>;
+ iommu-map = <0 &ipmmu_hc 0 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
@@ -2452,8 +2452,8 @@
<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2464,6 +2464,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 318>;
+ iommu-map = <0 &ipmmu_hc 1 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
diff --git a/arch/arm/dts/r8a77970-eagle.dts b/arch/arm/dts/r8a77970-eagle.dts
index 004a5ea..405404c 100644
--- a/arch/arm/dts/r8a77970-eagle.dts
+++ b/arch/arm/dts/r8a77970-eagle.dts
@@ -287,6 +287,9 @@
};
&pfc {
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
avb_pins: avb0 {
groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
function = "avb0";
@@ -316,6 +319,11 @@
groups = "scif0_data";
function = "scif0";
};
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk_b";
+ function = "scif_clk";
+ };
};
&rpc {
@@ -391,3 +399,7 @@
status = "okay";
};
+
+&scif_clk {
+ clock-frequency = <14745600>;
+};
diff --git a/arch/arm/dts/r8a77980-condor.dts b/arch/arm/dts/r8a77980-condor.dts
index 1d32655..68d1f1d 100644
--- a/arch/arm/dts/r8a77980-condor.dts
+++ b/arch/arm/dts/r8a77980-condor.dts
@@ -14,3 +14,11 @@
model = "Renesas Condor board based on r8a77980";
compatible = "renesas,condor", "renesas,r8a77980";
};
+
+&i2c0 {
+ eeprom@50 {
+ compatible = "rohm,br24t01", "atmel,24c01";
+ reg = <0x50>;
+ pagesize = <8>;
+ };
+};
diff --git a/arch/arm/dts/r8a77980-v3hsk.dts b/arch/arm/dts/r8a77980-v3hsk.dts
index d168b0e..77d22df 100644
--- a/arch/arm/dts/r8a77980-v3hsk.dts
+++ b/arch/arm/dts/r8a77980-v3hsk.dts
@@ -122,6 +122,7 @@
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
+ rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio4>;
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
diff --git a/arch/arm/dts/r8a77980.dtsi b/arch/arm/dts/r8a77980.dtsi
index c4ac28a..5ed2daa 100644
--- a/arch/arm/dts/r8a77980.dtsi
+++ b/arch/arm/dts/r8a77980.dtsi
@@ -1386,7 +1386,8 @@
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x8000000>;
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -1399,6 +1400,8 @@
resets = <&cpg 319>;
phys = <&pcie_phy>;
phy-names = "pcie";
+ iommu-map = <0 &ipmmu_vi0 5 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
diff --git a/arch/arm/dts/r8a77990.dtsi b/arch/arm/dts/r8a77990.dtsi
index 3053b4b..1be0b99 100644
--- a/arch/arm/dts/r8a77990.dtsi
+++ b/arch/arm/dts/r8a77990.dtsi
@@ -49,17 +49,14 @@
opp-shared;
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <820000>;
clock-latency-ns = <300000>;
opp-suspend;
};
@@ -1469,7 +1466,7 @@
rcar_sound: sound@ec500000 {
/*
- * #sound-dai-cells is required
+ * #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -1873,8 +1870,8 @@
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -1885,6 +1882,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 319>;
+ iommu-map = <0 &ipmmu_hc 0 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
diff --git a/arch/arm/dts/r8a77995.dtsi b/arch/arm/dts/r8a77995.dtsi
index f040d03..e25024a 100644
--- a/arch/arm/dts/r8a77995.dtsi
+++ b/arch/arm/dts/r8a77995.dtsi
@@ -1037,7 +1037,7 @@
rcar_sound: sound@ec500000 {
/*
- * #sound-dai-cells is required
+ * #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
diff --git a/arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi b/arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi
index e06b8ed..dbc8dca 100644
--- a/arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi
+++ b/arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi
@@ -5,6 +5,8 @@
* Copyright (C) 2021 Glider bv
*/
+#include <dt-bindings/media/video-interfaces.h>
+
&csi40 {
status = "okay";
@@ -105,6 +107,7 @@
port@4 {
reg = <4>;
max96712_out0: endpoint {
+ bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi40_in>;
@@ -125,6 +128,7 @@
port@4 {
reg = <4>;
max96712_out1: endpoint {
+ bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
lane-polarities = <0 0 0 0 1>;
@@ -146,6 +150,7 @@
port@4 {
reg = <4>;
max96712_out2: endpoint {
+ bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
lane-polarities = <0 0 0 0 1>;
diff --git a/arch/arm/dts/r8a779a0-falcon.dts b/arch/arm/dts/r8a779a0-falcon.dts
index b2e67b8..63db822 100644
--- a/arch/arm/dts/r8a779a0-falcon.dts
+++ b/arch/arm/dts/r8a779a0-falcon.dts
@@ -37,8 +37,12 @@
};
};
+&can_clk {
+ clock-frequency = <40000000>;
+};
+
&canfd {
- pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>;
+ pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>;
pinctrl-names = "default";
status = "okay";
@@ -80,6 +84,11 @@
};
+ can_clk_pins: can-clk {
+ groups = "can_clk";
+ function = "can_clk";
+ };
+
canfd0_pins: canfd0 {
groups = "canfd0_data";
function = "canfd0";
diff --git a/arch/arm/dts/r8a779a0.dtsi b/arch/arm/dts/r8a779a0.dtsi
index ed9400f..4e67a03 100644
--- a/arch/arm/dts/r8a779a0.dtsi
+++ b/arch/arm/dts/r8a779a0.dtsi
@@ -606,7 +606,8 @@
};
canfd: can@e6660000 {
- compatible = "renesas,r8a779a0-canfd";
+ compatible = "renesas,r8a779a0-canfd",
+ "renesas,rcar-gen4-canfd";
reg = <0 0xe6660000 0 0x8000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
@@ -656,7 +657,7 @@
avb0: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a779a0",
- "renesas,etheravb-rcar-gen3";
+ "renesas,etheravb-rcar-gen4";
reg = <0 0xe6800000 0 0x800>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
@@ -704,7 +705,7 @@
avb1: ethernet@e6810000 {
compatible = "renesas,etheravb-r8a779a0",
- "renesas,etheravb-rcar-gen3";
+ "renesas,etheravb-rcar-gen4";
reg = <0 0xe6810000 0 0x800>;
interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
@@ -752,7 +753,7 @@
avb2: ethernet@e6820000 {
compatible = "renesas,etheravb-r8a779a0",
- "renesas,etheravb-rcar-gen3";
+ "renesas,etheravb-rcar-gen4";
reg = <0 0xe6820000 0 0x1000>;
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
@@ -800,7 +801,7 @@
avb3: ethernet@e6830000 {
compatible = "renesas,etheravb-r8a779a0",
- "renesas,etheravb-rcar-gen3";
+ "renesas,etheravb-rcar-gen4";
reg = <0 0xe6830000 0 0x1000>;
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
@@ -848,7 +849,7 @@
avb4: ethernet@e6840000 {
compatible = "renesas,etheravb-r8a779a0",
- "renesas,etheravb-rcar-gen3";
+ "renesas,etheravb-rcar-gen4";
reg = <0 0xe6840000 0 0x1000>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
@@ -896,7 +897,7 @@
avb5: ethernet@e6850000 {
compatible = "renesas,etheravb-r8a779a0",
- "renesas,etheravb-rcar-gen3";
+ "renesas,etheravb-rcar-gen4";
reg = <0 0xe6850000 0 0x1000>;
interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
@@ -942,6 +943,56 @@
status = "disabled";
};
+ pwm0: pwm@e6e30000 {
+ compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
+ reg = <0 0xe6e30000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@e6e31000 {
+ compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
+ reg = <0 0xe6e31000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@e6e32000 {
+ compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
+ reg = <0 0xe6e32000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@e6e33000 {
+ compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
+ reg = <0 0xe6e33000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@e6e34000 {
+ compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
+ reg = <0 0xe6e34000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a779a0",
"renesas,rcar-gen4-scif", "renesas,scif";
@@ -1019,7 +1070,7 @@
msiof0: spi@e6e90000 {
compatible = "renesas,msiof-r8a779a0",
- "renesas,rcar-gen3-msiof";
+ "renesas,rcar-gen4-msiof";
reg = <0 0xe6e90000 0 0x0064>;
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 618>;
@@ -1034,7 +1085,7 @@
msiof1: spi@e6ea0000 {
compatible = "renesas,msiof-r8a779a0",
- "renesas,rcar-gen3-msiof";
+ "renesas,rcar-gen4-msiof";
reg = <0 0xe6ea0000 0 0x0064>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 619>;
@@ -1049,7 +1100,7 @@
msiof2: spi@e6c00000 {
compatible = "renesas,msiof-r8a779a0",
- "renesas,rcar-gen3-msiof";
+ "renesas,rcar-gen4-msiof";
reg = <0 0xe6c00000 0 0x0064>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 620>;
@@ -1064,7 +1115,7 @@
msiof3: spi@e6c10000 {
compatible = "renesas,msiof-r8a779a0",
- "renesas,rcar-gen3-msiof";
+ "renesas,rcar-gen4-msiof";
reg = <0 0xe6c10000 0 0x0064>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 621>;
@@ -1079,7 +1130,7 @@
msiof4: spi@e6c20000 {
compatible = "renesas,msiof-r8a779a0",
- "renesas,rcar-gen3-msiof";
+ "renesas,rcar-gen4-msiof";
reg = <0 0xe6c20000 0 0x0064>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
@@ -1094,7 +1145,7 @@
msiof5: spi@e6c28000 {
compatible = "renesas,msiof-r8a779a0",
- "renesas,rcar-gen3-msiof";
+ "renesas,rcar-gen4-msiof";
reg = <0 0xe6c28000 0 0x0064>;
interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;
@@ -2097,7 +2148,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xee480000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 10>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -2106,7 +2157,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xee4c0000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 19>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -2115,7 +2166,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed00000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 0>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -2124,7 +2175,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed40000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 1>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -2133,7 +2184,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed80000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 3>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_A3IR>;
#iommu-cells = <1>;
};
@@ -2142,7 +2193,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeedc0000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 12>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -2151,7 +2202,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeee80000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 14>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -2160,7 +2211,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeeec0000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 15>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -2169,7 +2220,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeee00000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 6>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -2178,7 +2229,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeef00000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 5>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -2187,7 +2238,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeef40000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 11>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -2209,8 +2260,7 @@
interrupt-controller;
reg = <0x0 0xf1000000 0 0x20000>,
<0x0 0xf1060000 0 0x110000>;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
fcpvd0: fcp@fea10000 {
@@ -2857,9 +2907,9 @@
timer {
compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm/dts/r8a779f0.dtsi b/arch/arm/dts/r8a779f0.dtsi
index f20b612..1d5426e 100644
--- a/arch/arm/dts/r8a779f0.dtsi
+++ b/arch/arm/dts/r8a779f0.dtsi
@@ -1059,7 +1059,7 @@
compatible = "renesas,ipmmu-r8a779f0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xee480000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 10>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -1068,7 +1068,7 @@
compatible = "renesas,ipmmu-r8a779f0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xee4c0000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 19>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -1077,7 +1077,7 @@
compatible = "renesas,ipmmu-r8a779f0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed00000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 0>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -1086,7 +1086,7 @@
compatible = "renesas,ipmmu-r8a779f0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed40000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 2>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -1108,8 +1108,7 @@
interrupt-controller;
reg = <0x0 0xf1000000 0 0x20000>,
<0x0 0xf1060000 0 0x110000>;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
prr: chipid@fff00044 {
@@ -1119,7 +1118,7 @@
};
thermal-zones {
- sensor_thermal1: sensor1-thermal {
+ sensor_thermal_rtcore: sensor1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
@@ -1133,7 +1132,7 @@
};
};
- sensor_thermal2: sensor2-thermal {
+ sensor_thermal_apcore0: sensor2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
@@ -1147,7 +1146,7 @@
};
};
- sensor_thermal3: sensor3-thermal {
+ sensor_thermal_apcore4: sensor3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;
@@ -1164,10 +1163,10 @@
timer {
compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
ufs30_clk: ufs30-clk {
diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi b/arch/arm/dts/r8a779g0-u-boot.dtsi
index 150657f..cc8beca 100644
--- a/arch/arm/dts/r8a779g0-u-boot.dtsi
+++ b/arch/arm/dts/r8a779g0-u-boot.dtsi
@@ -7,20 +7,10 @@
#include "r8a779x-u-boot.dtsi"
-/ {
- soc {
- rpc: spi@ee200000 {
- compatible = "renesas,r8a779g0-rpc-if", "renesas,rcar-gen4-rpc-if";
- reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 629>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 629>;
- bank-width = <2>;
- num-cs = <1>;
- status = "disabled";
- };
- };
+&rpc {
+ reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>;
+ bank-width = <2>;
+ num-cs = <1>;
};
&extalr_clk {
diff --git a/arch/arm/dts/r8a779g0-white-hawk-csi-dsi.dtsi b/arch/arm/dts/r8a779g0-white-hawk-csi-dsi.dtsi
index ae7522b..f8537f7 100644
--- a/arch/arm/dts/r8a779g0-white-hawk-csi-dsi.dtsi
+++ b/arch/arm/dts/r8a779g0-white-hawk-csi-dsi.dtsi
@@ -5,7 +5,63 @@
* Copyright (C) 2022 Glider bv
*/
+#include <dt-bindings/media/video-interfaces.h>
+
+&csi40 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csi40_in: endpoint {
+ bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
+ clock-lanes = <0>;
+ data-lanes = <1 2 3>;
+ remote-endpoint = <&max96712_out0>;
+ };
+ };
+ };
+};
+
+&csi41 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csi41_in: endpoint {
+ bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
+ clock-lanes = <0>;
+ data-lanes = <1 2 3>;
+ remote-endpoint = <&max96712_out1>;
+ };
+ };
+ };
+};
+
&i2c0 {
+ pca9654_a: gpio@21 {
+ compatible = "onnn,pca9654";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pca9654_b: gpio@22 {
+ compatible = "onnn,pca9654";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
eeprom@52 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "csi-dsi-sub-board-id";
@@ -13,3 +69,119 @@
pagesize = <8>;
};
};
+
+&i2c1 {
+ gmsl0: gmsl-deserializer@49 {
+ compatible = "maxim,max96712";
+ reg = <0x49>;
+ enable-gpios = <&pca9654_a 0 GPIO_ACTIVE_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@4 {
+ reg = <4>;
+ max96712_out0: endpoint {
+ bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
+ clock-lanes = <0>;
+ data-lanes = <1 2 3>;
+ remote-endpoint = <&csi40_in>;
+ };
+ };
+ };
+ };
+
+ gmsl1: gmsl-deserializer@4b {
+ compatible = "maxim,max96712";
+ reg = <0x4b>;
+ enable-gpios = <&pca9654_b 0 GPIO_ACTIVE_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@4 {
+ reg = <4>;
+ max96712_out1: endpoint {
+ bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
+ clock-lanes = <0>;
+ data-lanes = <1 2 3>;
+ remote-endpoint = <&csi41_in>;
+ };
+ };
+ };
+ };
+};
+
+&isp0 {
+ status = "okay";
+};
+
+&isp1 {
+ status = "okay";
+};
+
+&vin00 {
+ status = "okay";
+};
+
+&vin01 {
+ status = "okay";
+};
+
+&vin02 {
+ status = "okay";
+};
+
+&vin03 {
+ status = "okay";
+};
+
+&vin04 {
+ status = "okay";
+};
+
+&vin05 {
+ status = "okay";
+};
+
+&vin06 {
+ status = "okay";
+};
+
+&vin07 {
+ status = "okay";
+};
+
+&vin08 {
+ status = "okay";
+};
+
+&vin09 {
+ status = "okay";
+};
+
+&vin10 {
+ status = "okay";
+};
+
+&vin11 {
+ status = "okay";
+};
+
+&vin12 {
+ status = "okay";
+};
+
+&vin13 {
+ status = "okay";
+};
+
+&vin14 {
+ status = "okay";
+};
+
+&vin15 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dts b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dts
index efc1b95..bd75603 100644
--- a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dts
+++ b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dts
@@ -28,7 +28,7 @@
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <40000000>;
- status = "okay";
+ status = "disabled";
spi-flash@0 {
#address-cells = <1>;
diff --git a/arch/arm/dts/r8a779g0-white-hawk.dts b/arch/arm/dts/r8a779g0-white-hawk.dts
index 04a2b6b..eff1ef6 100644
--- a/arch/arm/dts/r8a779g0-white-hawk.dts
+++ b/arch/arm/dts/r8a779g0-white-hawk.dts
@@ -13,6 +13,33 @@
/ {
model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0";
compatible = "renesas,white-hawk-breakout", "renesas,white-hawk-cpu", "renesas,r8a779g0";
+
+ can_transceiver0: can-phy0 {
+ compatible = "nxp,tjr1443";
+ #phy-cells = <0>;
+ enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ max-bitrate = <5000000>;
+ };
+};
+
+&can_clk {
+ clock-frequency = <40000000>;
+};
+
+&canfd {
+ pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ channel0 {
+ status = "okay";
+ phys = <&can_transceiver0>;
+ };
+
+ channel1 {
+ status = "okay";
+ };
};
&i2c0 {
@@ -23,3 +50,20 @@
pagesize = <8>;
};
};
+
+&pfc {
+ can_clk_pins: can-clk {
+ groups = "can_clk";
+ function = "can_clk";
+ };
+
+ canfd0_pins: canfd0 {
+ groups = "canfd0_data";
+ function = "canfd0";
+ };
+
+ canfd1_pins: canfd1 {
+ groups = "canfd1_data";
+ function = "canfd1";
+ };
+};
diff --git a/arch/arm/dts/r8a779g0.dtsi b/arch/arm/dts/r8a779g0.dtsi
index 7a87a5d..d3d25e0 100644
--- a/arch/arm/dts/r8a779g0.dtsi
+++ b/arch/arm/dts/r8a779g0.dtsi
@@ -14,6 +14,20 @@
#address-cells = <2>;
#size-cells = <2>;
+ /* External Audio clock - to be overridden by boards that provide it */
+ audio_clkin: audio_clkin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock - to be overridden by boards that provide it */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@@ -431,6 +445,18 @@
#power-domain-cells = <1>;
};
+ tsc: thermal@e6198000 {
+ compatible = "renesas,r8a779g0-thermal";
+ reg = <0 0xe6198000 0 0x200>,
+ <0 0xe61a0000 0 0x200>,
+ <0 0xe61a8000 0 0x200>,
+ <0 0xe61b0000 0 0x200>;
+ clocks = <&cpg CPG_MOD 919>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 919>;
+ #thermal-sensor-cells = <1>;
+ };
+
intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a779g0", "renesas,irqc";
#interrupt-cells = <2>;
@@ -682,6 +708,56 @@
status = "disabled";
};
+ canfd: can@e6660000 {
+ compatible = "renesas,r8a779g0-canfd",
+ "renesas,rcar-gen4-canfd";
+ reg = <0 0xe6660000 0 0x8500>;
+ interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch_int", "g_int";
+ clocks = <&cpg CPG_MOD 328>,
+ <&cpg CPG_CORE R8A779G0_CLK_CANFD>,
+ <&can_clk>;
+ clock-names = "fck", "canfd", "can_clk";
+ assigned-clocks = <&cpg CPG_CORE R8A779G0_CLK_CANFD>;
+ assigned-clock-rates = <80000000>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 328>;
+ status = "disabled";
+
+ channel0 {
+ status = "disabled";
+ };
+
+ channel1 {
+ status = "disabled";
+ };
+
+ channel2 {
+ status = "disabled";
+ };
+
+ channel3 {
+ status = "disabled";
+ };
+
+ channel4 {
+ status = "disabled";
+ };
+
+ channel5 {
+ status = "disabled";
+ };
+
+ channel6 {
+ status = "disabled";
+ };
+
+ channel7 {
+ status = "disabled";
+ };
+ };
+
avb0: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a779g0",
"renesas,etheravb-rcar-gen4";
@@ -1098,6 +1174,454 @@
status = "disabled";
};
+ vin00: video@e6ef0000 {
+ compatible = "renesas,vin-r8a779g0";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 730>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 730>;
+ renesas,id = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin00isp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&isp0vin00>;
+ };
+ };
+ };
+ };
+
+ vin01: video@e6ef1000 {
+ compatible = "renesas,vin-r8a779g0";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 731>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 731>;
+ renesas,id = <1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin01isp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&isp0vin01>;
+ };
+ };
+ };
+ };
+
+ vin02: video@e6ef2000 {
+ compatible = "renesas,vin-r8a779g0";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 800>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 800>;
+ renesas,id = <2>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin02isp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&isp0vin02>;
+ };
+ };
+ };
+ };
+
+ vin03: video@e6ef3000 {
+ compatible = "renesas,vin-r8a779g0";
+ reg = <0 0xe6ef3000 0 0x1000>;
+ interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 801>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 801>;
+ renesas,id = <3>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin03isp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&isp0vin03>;
+ };
+ };
+ };
+ };
+
+ vin04: video@e6ef4000 {
+ compatible = "renesas,vin-r8a779g0";
+ reg = <0 0xe6ef4000 0 0x1000>;
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 802>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 802>;
+ renesas,id = <4>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin04isp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&isp0vin04>;
+ };
+ };
+ };
+ };
+
+ vin05: video@e6ef5000 {
+ compatible = "renesas,vin-r8a779g0";
+ reg = <0 0xe6ef5000 0 0x1000>;
+ interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 803>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 803>;
+ renesas,id = <5>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin05isp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&isp0vin05>;
+ };
+ };
+ };
+ };
+
+ vin06: video@e6ef6000 {
+ compatible = "renesas,vin-r8a779g0";
+ reg = <0 0xe6ef6000 0 0x1000>;
+ interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 804>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 804>;
+ renesas,id = <6>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin06isp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&isp0vin06>;
+ };
+ };
+ };
+ };
+
+ vin07: video@e6ef7000 {
+ compatible = "renesas,vin-r8a779g0";
+ reg = <0 0xe6ef7000 0 0x1000>;
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 805>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 805>;
+ renesas,id = <7>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin07isp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&isp0vin07>;
+ };
+ };
+ };
+ };
+
+ vin08: video@e6ef8000 {
+ compatible = "renesas,vin-r8a779g0";
+ reg = <0 0xe6ef8000 0 0x1000>;
+ interrupts = <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 806>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 806>;
+ renesas,id = <8>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin08isp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&isp1vin08>;
+ };
+ };
+ };
+ };
+
+ vin09: video@e6ef9000 {
+ compatible = "renesas,vin-r8a779g0";
+ reg = <0 0xe6ef9000 0 0x1000>;
+ interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 807>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 807>;
+ renesas,id = <9>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin09isp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&isp1vin09>;
+ };
+ };
+ };
+ };
+
+ vin10: video@e6efa000 {
+ compatible = "renesas,vin-r8a779g0";
+ reg = <0 0xe6efa000 0 0x1000>;
+ interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 808>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 808>;
+ renesas,id = <10>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin10isp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&isp1vin10>;
+ };
+ };
+ };
+ };
+
+ vin11: video@e6efb000 {
+ compatible = "renesas,vin-r8a779g0";
+ reg = <0 0xe6efb000 0 0x1000>;
+ interrupts = <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ renesas,id = <11>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin11isp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&isp1vin11>;
+ };
+ };
+ };
+ };
+
+ vin12: video@e6efc000 {
+ compatible = "renesas,vin-r8a779g0";
+ reg = <0 0xe6efc000 0 0x1000>;
+ interrupts = <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 810>;
+ renesas,id = <12>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin12isp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&isp1vin12>;
+ };
+ };
+ };
+ };
+
+ vin13: video@e6efd000 {
+ compatible = "renesas,vin-r8a779g0";
+ reg = <0 0xe6efd000 0 0x1000>;
+ interrupts = <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ renesas,id = <13>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin13isp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&isp1vin13>;
+ };
+ };
+ };
+ };
+
+ vin14: video@e6efe000 {
+ compatible = "renesas,vin-r8a779g0";
+ reg = <0 0xe6efe000 0 0x1000>;
+ interrupts = <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 812>;
+ renesas,id = <14>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin14isp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&isp1vin14>;
+ };
+ };
+ };
+ };
+
+ vin15: video@e6eff000 {
+ compatible = "renesas,vin-r8a779g0";
+ reg = <0 0xe6eff000 0 0x1000>;
+ interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 813>;
+ renesas,id = <15>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin15isp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&isp1vin15>;
+ };
+ };
+ };
+ };
+
dmac0: dma-controller@e7350000 {
compatible = "renesas,dmac-r8a779g0",
"renesas,rcar-gen4-dmac";
@@ -1131,6 +1655,14 @@
resets = <&cpg 709>;
#dma-cells = <1>;
dma-channels = <16>;
+ iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
+ <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
+ <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
+ <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
+ <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
+ <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
+ <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
+ <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
};
dmac1: dma-controller@e7351000 {
@@ -1166,6 +1698,192 @@
resets = <&cpg 710>;
#dma-cells = <1>;
dma-channels = <16>;
+ iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
+ <&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
+ <&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
+ <&ipmmu_ds0 22>, <&ipmmu_ds0 23>,
+ <&ipmmu_ds0 24>, <&ipmmu_ds0 25>,
+ <&ipmmu_ds0 26>, <&ipmmu_ds0 27>,
+ <&ipmmu_ds0 28>, <&ipmmu_ds0 29>,
+ <&ipmmu_ds0 30>, <&ipmmu_ds0 31>;
+ };
+
+ rcar_sound: sound@ec5a0000 {
+ /*
+ * #sound-dai-cells is required
+ *
+ * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
+ * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
+ */
+ /*
+ * #clock-cells is required
+ *
+ * clkout : #clock-cells = <0>; <&rcar_sound>;
+ * audio_clkout0/1/2/3 : #clock-cells = <1>; <&rcar_sound N>;
+ */
+ compatible = "renesas,rcar_sound-r8a779g0", "renesas,rcar_sound-gen4";
+ reg = <0 0xec5a0000 0 0x020>,
+ <0 0xec540000 0 0x1000>,
+ <0 0xec541000 0 0x050>,
+ <0 0xec400000 0 0x40000>;
+ reg-names = "adg", "ssiu", "ssi", "sdmc";
+
+ clocks = <&cpg CPG_MOD 2926>, <&cpg CPG_MOD 2927>, <&audio_clkin>;
+ clock-names = "ssiu.0", "ssi.0", "clkin";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 2926>, <&cpg 2927>;
+ reset-names = "ssiu.0", "ssi.0";
+ status = "disabled";
+
+ rcar_sound,ssiu {
+ ssiu00: ssiu-0 {
+ dmas = <&dmac0 0x6e>, <&dmac0 0x6f>;
+ dma-names = "tx", "rx";
+ };
+ ssiu01: ssiu-1 {
+ dmas = <&dmac0 0x6c>, <&dmac0 0x6d>;
+ dma-names = "tx", "rx";
+ };
+ ssiu02: ssiu-2 {
+ dmas = <&dmac0 0x6a>, <&dmac0 0x6b>;
+ dma-names = "tx", "rx";
+ };
+ ssiu03: ssiu-3 {
+ dmas = <&dmac0 0x68>, <&dmac0 0x69>;
+ dma-names = "tx", "rx";
+ };
+ ssiu04: ssiu-4 {
+ dmas = <&dmac0 0x66>, <&dmac0 0x67>;
+ dma-names = "tx", "rx";
+ };
+ ssiu05: ssiu-5 {
+ dmas = <&dmac0 0x64>, <&dmac0 0x65>;
+ dma-names = "tx", "rx";
+ };
+ ssiu06: ssiu-6 {
+ dmas = <&dmac0 0x62>, <&dmac0 0x63>;
+ dma-names = "tx", "rx";
+ };
+ ssiu07: ssiu-7 {
+ dmas = <&dmac0 0x60>, <&dmac0 0x61>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
+
+ ipmmu_rt0: iommu@ee480000 {
+ compatible = "renesas,ipmmu-r8a779g0",
+ "renesas,rcar-gen4-ipmmu-vmsa";
+ reg = <0 0xee480000 0 0x20000>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_rt1: iommu@ee4c0000 {
+ compatible = "renesas,ipmmu-r8a779g0",
+ "renesas,rcar-gen4-ipmmu-vmsa";
+ reg = <0 0xee4c0000 0 0x20000>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_ds0: iommu@eed00000 {
+ compatible = "renesas,ipmmu-r8a779g0",
+ "renesas,rcar-gen4-ipmmu-vmsa";
+ reg = <0 0xeed00000 0 0x20000>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_hc: iommu@eed40000 {
+ compatible = "renesas,ipmmu-r8a779g0",
+ "renesas,rcar-gen4-ipmmu-vmsa";
+ reg = <0 0xeed40000 0 0x20000>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_ir: iommu@eed80000 {
+ compatible = "renesas,ipmmu-r8a779g0",
+ "renesas,rcar-gen4-ipmmu-vmsa";
+ reg = <0 0xeed80000 0 0x20000>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
+ power-domains = <&sysc R8A779G0_PD_A3IR>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vc: iommu@eedc0000 {
+ compatible = "renesas,ipmmu-r8a779g0",
+ "renesas,rcar-gen4-ipmmu-vmsa";
+ reg = <0 0xeedc0000 0 0x20000>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_3dg: iommu@eee00000 {
+ compatible = "renesas,ipmmu-r8a779g0",
+ "renesas,rcar-gen4-ipmmu-vmsa";
+ reg = <0 0xeee00000 0 0x20000>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vi0: iommu@eee80000 {
+ compatible = "renesas,ipmmu-r8a779g0",
+ "renesas,rcar-gen4-ipmmu-vmsa";
+ reg = <0 0xeee80000 0 0x20000>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vi1: iommu@eeec0000 {
+ compatible = "renesas,ipmmu-r8a779g0",
+ "renesas,rcar-gen4-ipmmu-vmsa";
+ reg = <0 0xeeec0000 0 0x20000>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vip0: iommu@eef00000 {
+ compatible = "renesas,ipmmu-r8a779g0",
+ "renesas,rcar-gen4-ipmmu-vmsa";
+ reg = <0 0xeef00000 0 0x20000>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vip1: iommu@eef40000 {
+ compatible = "renesas,ipmmu-r8a779g0",
+ "renesas,rcar-gen4-ipmmu-vmsa";
+ reg = <0 0xeef40000 0 0x20000>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_mm: iommu@eefc0000 {
+ compatible = "renesas,ipmmu-r8a779g0",
+ "renesas,rcar-gen4-ipmmu-vmsa";
+ reg = <0 0xeefc0000 0 0x20000>;
+ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
};
mmc0: mmc@ee140000 {
@@ -1179,6 +1897,7 @@
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 706>;
max-frequency = <200000000>;
+ iommus = <&ipmmu_ds0 32>;
status = "disabled";
};
@@ -1205,8 +1924,59 @@
interrupt-controller;
reg = <0x0 0xf1000000 0 0x20000>,
<0x0 0xf1060000 0 0x110000>;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ csi40: csi2@fe500000 {
+ compatible = "renesas,r8a779g0-csi2";
+ reg = <0 0xfe500000 0 0x40000>;
+ interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 331>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 331>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ csi40isp0: endpoint {
+ remote-endpoint = <&isp0csi40>;
+ };
+ };
+ };
+ };
+
+ csi41: csi2@fe540000 {
+ compatible = "renesas,r8a779g0-csi2";
+ reg = <0 0xfe540000 0 0x40000>;
+ interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 400>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 400>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ csi41isp1: endpoint {
+ remote-endpoint = <&isp1csi41>;
+ };
+ };
+ };
};
fcpvd0: fcp@fea10000 {
@@ -1281,6 +2051,172 @@
};
};
+ isp0: isp@fed00000 {
+ compatible = "renesas,r8a779g0-isp";
+ reg = <0 0xfed00000 0 0x10000>;
+ interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&cpg CPG_MOD 612>;
+ power-domains = <&sysc R8A779G0_PD_A3ISP0>;
+ resets = <&cpg 612>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0>;
+
+ isp0csi40: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&csi40isp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ isp0vin00: endpoint {
+ remote-endpoint = <&vin00isp0>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ isp0vin01: endpoint {
+ remote-endpoint = <&vin01isp0>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ isp0vin02: endpoint {
+ remote-endpoint = <&vin02isp0>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ isp0vin03: endpoint {
+ remote-endpoint = <&vin03isp0>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ isp0vin04: endpoint {
+ remote-endpoint = <&vin04isp0>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ isp0vin05: endpoint {
+ remote-endpoint = <&vin05isp0>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ isp0vin06: endpoint {
+ remote-endpoint = <&vin06isp0>;
+ };
+ };
+
+ port@8 {
+ reg = <8>;
+ isp0vin07: endpoint {
+ remote-endpoint = <&vin07isp0>;
+ };
+ };
+ };
+ };
+
+ isp1: isp@fed20000 {
+ compatible = "renesas,r8a779g0-isp";
+ reg = <0 0xfed20000 0 0x10000>;
+ interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&cpg CPG_MOD 613>;
+ power-domains = <&sysc R8A779G0_PD_A3ISP1>;
+ resets = <&cpg 613>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0>;
+
+ isp1csi41: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&csi41isp1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ isp1vin08: endpoint {
+ remote-endpoint = <&vin08isp1>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ isp1vin09: endpoint {
+ remote-endpoint = <&vin09isp1>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ isp1vin10: endpoint {
+ remote-endpoint = <&vin10isp1>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ isp1vin11: endpoint {
+ remote-endpoint = <&vin11isp1>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ isp1vin12: endpoint {
+ remote-endpoint = <&vin12isp1>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ isp1vin13: endpoint {
+ remote-endpoint = <&vin13isp1>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ isp1vin14: endpoint {
+ remote-endpoint = <&vin14isp1>;
+ };
+ };
+
+ port@8 {
+ reg = <8>;
+ isp1vin15: endpoint {
+ remote-endpoint = <&vin15isp1>;
+ };
+ };
+ };
+ };
+
dsi0: dsi-encoder@fed80000 {
compatible = "renesas,r8a779g0-dsi-csi2-tx";
reg = <0 0xfed80000 0 0x10000>;
@@ -1345,11 +2281,69 @@
};
};
+ thermal-zones {
+ sensor_thermal_cr52: sensor1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsc 0>;
+
+ trips {
+ sensor1_crit: sensor1-crit {
+ temperature = <120000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ sensor_thermal_cnn: sensor2-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsc 1>;
+
+ trips {
+ sensor2_crit: sensor2-crit {
+ temperature = <120000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ sensor_thermal_ca76: sensor3-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsc 2>;
+
+ trips {
+ sensor3_crit: sensor3-crit {
+ temperature = <120000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ sensor_thermal_ddr1: sensor4-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsc 3>;
+
+ trips {
+ sensor4_crit: sensor4-crit {
+ temperature = <120000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm/dts/r9a07g044.dtsi b/arch/arm/dts/r9a07g044.dtsi
new file mode 100644
index 0000000..232910e
--- /dev/null
+++ b/arch/arm/dts/r9a07g044.dtsi
@@ -0,0 +1,1273 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r9a07g044-cpg.h>
+
+/ {
+ compatible = "renesas,r9a07g044";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ audio_clk1: audio1-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by boards that provide it */
+ clock-frequency = <0>;
+ };
+
+ audio_clk2: audio2-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by boards that provide it */
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock - to be overridden by boards that provide it */
+ can_clk: can-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
+ extal_clk: extal-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ cluster0_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55";
+ reg = <0>;
+ device_type = "cpu";
+ #cooling-cells = <2>;
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ cpu1: cpu@100 {
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ device_type = "cpu";
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ L3_CA55: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-size = <0x40000>;
+ cache-level = <3>;
+ };
+ };
+
+ gpu_opp_table: opp-table-1 {
+ compatible = "operating-points-v2";
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-125000000 {
+ opp-hz = /bits/ 64 <125000000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-62500000 {
+ opp-hz = /bits/ 64 <62500000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ opp-microvolt = <1100000>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a55-pmu";
+ interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ mtu3: timer@10001200 {
+ compatible = "renesas,r9a07g044-mtu3",
+ "renesas,rz-mtu3";
+ reg = <0 0x10001200 0 0xb00>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
+ "tgiv0", "tgie0", "tgif0",
+ "tgia1", "tgib1", "tgiv1", "tgiu1",
+ "tgia2", "tgib2", "tgiv2", "tgiu2",
+ "tgia3", "tgib3", "tgic3", "tgid3",
+ "tgiv3",
+ "tgia4", "tgib4", "tgic4", "tgid4",
+ "tgiv4",
+ "tgiu5", "tgiv5", "tgiw5",
+ "tgia6", "tgib6", "tgic6", "tgid6",
+ "tgiv6",
+ "tgia7", "tgib7", "tgic7", "tgid7",
+ "tgiv7",
+ "tgia8", "tgib8", "tgic8", "tgid8",
+ "tgiv8", "tgiu8";
+ clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ ssi0: ssi@10049c00 {
+ compatible = "renesas,r9a07g044-ssi",
+ "renesas,rz-ssi";
+ reg = <0 0x10049c00 0 0x400>;
+ interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx";
+ clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
+ <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
+ <&audio_clk1>, <&audio_clk2>;
+ clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+ resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
+ dmas = <&dmac 0x2655>, <&dmac 0x2656>;
+ dma-names = "tx", "rx";
+ power-domains = <&cpg>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ ssi1: ssi@1004a000 {
+ compatible = "renesas,r9a07g044-ssi",
+ "renesas,rz-ssi";
+ reg = <0 0x1004a000 0 0x400>;
+ interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx";
+ clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
+ <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
+ <&audio_clk1>, <&audio_clk2>;
+ clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+ resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
+ dmas = <&dmac 0x2659>, <&dmac 0x265a>;
+ dma-names = "tx", "rx";
+ power-domains = <&cpg>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ ssi2: ssi@1004a400 {
+ compatible = "renesas,r9a07g044-ssi",
+ "renesas,rz-ssi";
+ reg = <0 0x1004a400 0 0x400>;
+ interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rt";
+ clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
+ <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
+ <&audio_clk1>, <&audio_clk2>;
+ clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+ resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;
+ dmas = <&dmac 0x265f>;
+ dma-names = "rt";
+ power-domains = <&cpg>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ ssi3: ssi@1004a800 {
+ compatible = "renesas,r9a07g044-ssi",
+ "renesas,rz-ssi";
+ reg = <0 0x1004a800 0 0x400>;
+ interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx";
+ clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
+ <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
+ <&audio_clk1>, <&audio_clk2>;
+ clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+ resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;
+ dmas = <&dmac 0x2661>, <&dmac 0x2662>;
+ dma-names = "tx", "rx";
+ power-domains = <&cpg>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ spi0: spi@1004ac00 {
+ compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
+ reg = <0 0x1004ac00 0 0x400>;
+ interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error", "rx", "tx";
+ clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>;
+ resets = <&cpg R9A07G044_RSPI0_RST>;
+ dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
+ dma-names = "tx", "rx";
+ power-domains = <&cpg>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@1004b000 {
+ compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
+ reg = <0 0x1004b000 0 0x400>;
+ interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error", "rx", "tx";
+ clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>;
+ resets = <&cpg R9A07G044_RSPI1_RST>;
+ dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
+ dma-names = "tx", "rx";
+ power-domains = <&cpg>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@1004b400 {
+ compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
+ reg = <0 0x1004b400 0 0x400>;
+ interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error", "rx", "tx";
+ clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>;
+ resets = <&cpg R9A07G044_RSPI2_RST>;
+ dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
+ dma-names = "tx", "rx";
+ power-domains = <&cpg>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ scif0: serial@1004b800 {
+ compatible = "renesas,scif-r9a07g044";
+ reg = <0 0x1004b800 0 0x400>;
+ interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif1: serial@1004bc00 {
+ compatible = "renesas,scif-r9a07g044";
+ reg = <0 0x1004bc00 0 0x400>;
+ interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif2: serial@1004c000 {
+ compatible = "renesas,scif-r9a07g044";
+ reg = <0 0x1004c000 0 0x400>;
+ interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif3: serial@1004c400 {
+ compatible = "renesas,scif-r9a07g044";
+ reg = <0 0x1004c400 0 0x400>;
+ interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif4: serial@1004c800 {
+ compatible = "renesas,scif-r9a07g044";
+ reg = <0 0x1004c800 0 0x400>;
+ interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ sci0: serial@1004d000 {
+ compatible = "renesas,r9a07g044-sci", "renesas,sci";
+ reg = <0 0x1004d000 0 0x400>;
+ interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_SCI0_RST>;
+ status = "disabled";
+ };
+
+ sci1: serial@1004d400 {
+ compatible = "renesas,r9a07g044-sci", "renesas,sci";
+ reg = <0 0x1004d400 0 0x400>;
+ interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_SCI1_RST>;
+ status = "disabled";
+ };
+
+ canfd: can@10050000 {
+ compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
+ reg = <0 0x10050000 0 0x8000>;
+ interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g_err", "g_recc",
+ "ch0_err", "ch0_rec", "ch0_trx",
+ "ch1_err", "ch1_rec", "ch1_trx";
+ clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
+ <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
+ <&can_clk>;
+ clock-names = "fck", "canfd", "can_clk";
+ assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
+ assigned-clock-rates = <50000000>;
+ resets = <&cpg R9A07G044_CANFD_RSTP_N>,
+ <&cpg R9A07G044_CANFD_RSTC_N>;
+ reset-names = "rstp_n", "rstc_n";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ channel0 {
+ status = "disabled";
+ };
+ channel1 {
+ status = "disabled";
+ };
+ };
+
+ i2c0: i2c@10058000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
+ reg = <0 0x10058000 0 0x400>;
+ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
+ clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>;
+ clock-frequency = <100000>;
+ resets = <&cpg R9A07G044_I2C0_MRST>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@10058400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
+ reg = <0 0x10058400 0 0x400>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
+ clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>;
+ clock-frequency = <100000>;
+ resets = <&cpg R9A07G044_I2C1_MRST>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@10058800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
+ reg = <0 0x10058800 0 0x400>;
+ interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
+ clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>;
+ clock-frequency = <100000>;
+ resets = <&cpg R9A07G044_I2C2_MRST>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@10058c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
+ reg = <0 0x10058c00 0 0x400>;
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
+ clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>;
+ clock-frequency = <100000>;
+ resets = <&cpg R9A07G044_I2C3_MRST>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ adc: adc@10059000 {
+ compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
+ reg = <0 0x10059000 0 0x400>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
+ <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
+ clock-names = "adclk", "pclk";
+ resets = <&cpg R9A07G044_ADC_PRESETN>,
+ <&cpg R9A07G044_ADC_ADRST_N>;
+ reset-names = "presetn", "adrst-n";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ };
+ channel@1 {
+ reg = <1>;
+ };
+ channel@2 {
+ reg = <2>;
+ };
+ channel@3 {
+ reg = <3>;
+ };
+ channel@4 {
+ reg = <4>;
+ };
+ channel@5 {
+ reg = <5>;
+ };
+ channel@6 {
+ reg = <6>;
+ };
+ channel@7 {
+ reg = <7>;
+ };
+ };
+
+ tsu: thermal@10059400 {
+ compatible = "renesas,r9a07g044-tsu",
+ "renesas,rzg2l-tsu";
+ reg = <0 0x10059400 0 0x400>;
+ clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>;
+ resets = <&cpg R9A07G044_TSU_PRESETN>;
+ power-domains = <&cpg>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ sbc: spi@10060000 {
+ compatible = "renesas,r9a07g044-rpc-if",
+ "renesas,rzg2l-rpc-if";
+ reg = <0 0x10060000 0 0x10000>,
+ <0 0x20000000 0 0x10000000>,
+ <0 0x10070000 0 0x10000>;
+ reg-names = "regs", "dirmap", "wbuf";
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>,
+ <&cpg CPG_MOD R9A07G044_SPI_CLK>;
+ resets = <&cpg R9A07G044_SPI_RST>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ cru: video@10830000 {
+ compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru";
+ reg = <0 0x10830000 0 0x400>;
+ clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
+ <&cpg CPG_MOD R9A07G044_CRU_PCLK>,
+ <&cpg CPG_MOD R9A07G044_CRU_ACLK>;
+ clock-names = "video", "apb", "axi";
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "image_conv", "image_conv_err", "axi_mst_err";
+ resets = <&cpg R9A07G044_CRU_PRESETN>,
+ <&cpg R9A07G044_CRU_ARESETN>;
+ reset-names = "presetn", "aresetn";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0>;
+ cruparallel: endpoint@0 {
+ reg = <0>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+ crucsi2: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&csi2cru>;
+ };
+ };
+ };
+ };
+
+ csi2: csi2@10830400 {
+ compatible = "renesas,r9a07g044-csi2", "renesas,rzg2l-csi2";
+ reg = <0 0x10830400 0 0xfc00>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>,
+ <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
+ <&cpg CPG_MOD R9A07G044_CRU_PCLK>;
+ clock-names = "system", "video", "apb";
+ resets = <&cpg R9A07G044_CRU_PRESETN>,
+ <&cpg R9A07G044_CRU_CMN_RSTB>;
+ reset-names = "presetn", "cmn-rstb";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ csi2cru: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&crucsi2>;
+ };
+ };
+ };
+ };
+
+ dsi: dsi@10850000 {
+ compatible = "renesas,r9a07g044-mipi-dsi",
+ "renesas,rzg2l-mipi-dsi";
+ reg = <0 0x10850000 0 0x20000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "seq0", "seq1", "vin1", "rcv",
+ "ferr", "ppi", "debug";
+ clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
+ <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
+ <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
+ <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
+ <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
+ <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
+ clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
+ resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
+ <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
+ <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
+ reset-names = "rst", "arst", "prst";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ vspd: vsp@10870000 {
+ compatible = "renesas,r9a07g044-vsp2";
+ reg = <0 0x10870000 0 0x10000>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
+ <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
+ <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_LCDC_RESET_N>;
+ renesas,fcp = <&fcpvd>;
+ };
+
+ fcpvd: fcp@10880000 {
+ compatible = "renesas,r9a07g044-fcpvd",
+ "renesas,fcpv";
+ reg = <0 0x10880000 0 0x10000>;
+ clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
+ <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
+ <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_LCDC_RESET_N>;
+ };
+
+ cpg: clock-controller@11010000 {
+ compatible = "renesas,r9a07g044-cpg";
+ reg = <0 0x11010000 0 0x10000>;
+ clocks = <&extal_clk>;
+ clock-names = "extal";
+ #clock-cells = <2>;
+ #reset-cells = <1>;
+ #power-domain-cells = <0>;
+ };
+
+ sysc: system-controller@11020000 {
+ compatible = "renesas,r9a07g044-sysc";
+ reg = <0 0x11020000 0 0x10000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "lpm_int", "ca55stbydone_int",
+ "cm33stbyr_int", "ca55_deny";
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl@11030000 {
+ compatible = "renesas,r9a07g044-pinctrl";
+ reg = <0 0x11030000 0 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&irqc>;
+ interrupt-controller;
+ gpio-ranges = <&pinctrl 0 0 392>;
+ clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_GPIO_RSTN>,
+ <&cpg R9A07G044_GPIO_PORT_RESETN>,
+ <&cpg R9A07G044_GPIO_SPARE_RESETN>;
+ };
+
+ irqc: interrupt-controller@110a0000 {
+ compatible = "renesas,r9a07g044-irqc",
+ "renesas,rzg2l-irqc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0x110a0000 0 0x10000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
+ <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
+ clock-names = "clk", "pclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_IA55_RESETN>;
+ };
+
+ dmac: dma-controller@11820000 {
+ compatible = "renesas,r9a07g044-dmac",
+ "renesas,rz-dmac";
+ reg = <0 0x11820000 0 0x10000>,
+ <0 0x11830000 0 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
+ <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
+ clock-names = "main", "register";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_DMAC_ARESETN>,
+ <&cpg R9A07G044_DMAC_RST_ASYNC>;
+ reset-names = "arst", "rst_async";
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
+ gpu: gpu@11840000 {
+ compatible = "renesas,r9a07g044-mali",
+ "arm,mali-bifrost";
+ reg = <0x0 0x11840000 0x0 0x10000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "job", "mmu", "gpu", "event";
+ clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>,
+ <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>,
+ <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>;
+ clock-names = "gpu", "bus", "bus_ace";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_GPU_RESETN>,
+ <&cpg R9A07G044_GPU_AXI_RESETN>,
+ <&cpg R9A07G044_GPU_ACE_RESETN>;
+ reset-names = "rst", "axi_rst", "ace_rst";
+ operating-points-v2 = <&gpu_opp_table>;
+ };
+
+ gic: interrupt-controller@11900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0x11900000 0 0x40000>,
+ <0x0 0x11940000 0 0x60000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ sdhi0: mmc@11c00000 {
+ compatible = "renesas,sdhi-r9a07g044",
+ "renesas,rcar-gen3-sdhi";
+ reg = <0x0 0x11c00000 0 0x10000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
+ <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
+ <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
+ <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
+ clock-names = "core", "clkh", "cd", "aclk";
+ resets = <&cpg R9A07G044_SDHI0_IXRST>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ sdhi1: mmc@11c10000 {
+ compatible = "renesas,sdhi-r9a07g044",
+ "renesas,rcar-gen3-sdhi";
+ reg = <0x0 0x11c10000 0 0x10000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
+ <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
+ <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
+ <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
+ clock-names = "core", "clkh", "cd", "aclk";
+ resets = <&cpg R9A07G044_SDHI1_IXRST>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ eth0: ethernet@11c20000 {
+ compatible = "renesas,r9a07g044-gbeth",
+ "renesas,rzg2l-gbeth";
+ reg = <0 0x11c20000 0 0x10000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mux", "fil", "arp_ns";
+ phy-mode = "rgmii";
+ clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>,
+ <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>,
+ <&cpg CPG_CORE R9A07G044_CLK_HP>;
+ clock-names = "axi", "chi", "refclk";
+ resets = <&cpg R9A07G044_ETH0_RST_HW_N>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ eth1: ethernet@11c30000 {
+ compatible = "renesas,r9a07g044-gbeth",
+ "renesas,rzg2l-gbeth";
+ reg = <0 0x11c30000 0 0x10000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mux", "fil", "arp_ns";
+ phy-mode = "rgmii";
+ clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>,
+ <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>,
+ <&cpg CPG_CORE R9A07G044_CLK_HP>;
+ clock-names = "axi", "chi", "refclk";
+ resets = <&cpg R9A07G044_ETH1_RST_HW_N>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ phyrst: usbphy-ctrl@11c40000 {
+ compatible = "renesas,r9a07g044-usbphy-ctrl",
+ "renesas,rzg2l-usbphy-ctrl";
+ reg = <0 0x11c40000 0 0x10000>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
+ resets = <&cpg R9A07G044_USB_PRESETN>;
+ power-domains = <&cpg>;
+ #reset-cells = <1>;
+ status = "disabled";
+ };
+
+ ohci0: usb@11c50000 {
+ compatible = "generic-ohci";
+ reg = <0 0x11c50000 0 0x100>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A07G044_USB_U2H0_HRESETN>;
+ phys = <&usb2_phy0 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ohci1: usb@11c70000 {
+ compatible = "generic-ohci";
+ reg = <0 0x11c70000 0 0x100>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>,
+ <&cpg R9A07G044_USB_U2H1_HRESETN>;
+ phys = <&usb2_phy1 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci0: usb@11c50100 {
+ compatible = "generic-ehci";
+ reg = <0 0x11c50100 0 0x100>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A07G044_USB_U2H0_HRESETN>;
+ phys = <&usb2_phy0 2>;
+ phy-names = "usb";
+ companion = <&ohci0>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci1: usb@11c70100 {
+ compatible = "generic-ehci";
+ reg = <0 0x11c70100 0 0x100>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>,
+ <&cpg R9A07G044_USB_U2H1_HRESETN>;
+ phys = <&usb2_phy1 2>;
+ phy-names = "usb";
+ companion = <&ohci1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy0: usb-phy@11c50200 {
+ compatible = "renesas,usb2-phy-r9a07g044",
+ "renesas,rzg2l-usb2-phy";
+ reg = <0 0x11c50200 0 0x700>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy1: usb-phy@11c70200 {
+ compatible = "renesas,usb2-phy-r9a07g044",
+ "renesas,rzg2l-usb2-phy";
+ reg = <0 0x11c70200 0 0x700>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ hsusb: usb@11c60000 {
+ compatible = "renesas,usbhs-r9a07g044",
+ "renesas,rza2-usbhs";
+ reg = <0 0x11c60000 0 0x10000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
+ renesas,buswait = <7>;
+ phys = <&usb2_phy0 3>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ wdt0: watchdog@12800800 {
+ compatible = "renesas,r9a07g044-wdt",
+ "renesas,rzg2l-wdt";
+ reg = <0 0x12800800 0 0x400>;
+ clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>,
+ <&cpg CPG_MOD R9A07G044_WDT0_CLK>;
+ clock-names = "pclk", "oscclk";
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "wdt", "perrout";
+ resets = <&cpg R9A07G044_WDT0_PRESETN>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ wdt1: watchdog@12800c00 {
+ compatible = "renesas,r9a07g044-wdt",
+ "renesas,rzg2l-wdt";
+ reg = <0 0x12800C00 0 0x400>;
+ clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>,
+ <&cpg CPG_MOD R9A07G044_WDT1_CLK>;
+ clock-names = "pclk", "oscclk";
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "wdt", "perrout";
+ resets = <&cpg R9A07G044_WDT1_PRESETN>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ostm0: timer@12801000 {
+ compatible = "renesas,r9a07g044-ostm",
+ "renesas,ostm";
+ reg = <0x0 0x12801000 0x0 0x400>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>;
+ resets = <&cpg R9A07G044_OSTM0_PRESETZ>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ostm1: timer@12801400 {
+ compatible = "renesas,r9a07g044-ostm",
+ "renesas,ostm";
+ reg = <0x0 0x12801400 0x0 0x400>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>;
+ resets = <&cpg R9A07G044_OSTM1_PRESETZ>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ostm2: timer@12801800 {
+ compatible = "renesas,r9a07g044-ostm",
+ "renesas,ostm";
+ reg = <0x0 0x12801800 0x0 0x400>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>;
+ resets = <&cpg R9A07G044_OSTM2_PRESETZ>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+ };
+
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsu 0>;
+ sustainable-power = <717>;
+
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ cooling-device = <&cpu0 0 2>;
+ contribution = <1024>;
+ };
+ };
+
+ trips {
+ sensor_crit: sensor-crit {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+
+ target: trip-point {
+ temperature = <100000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
diff --git a/arch/arm/dts/r9a07g044l2-smarc.dts b/arch/arm/dts/r9a07g044l2-smarc.dts
new file mode 100644
index 0000000..bc2af6c
--- /dev/null
+++ b/arch/arm/dts/r9a07g044l2-smarc.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L SMARC EVK board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g044l2.dtsi"
+#include "rzg2l-smarc-som.dtsi"
+#include "rzg2l-smarc-pinfunction.dtsi"
+#include "rz-smarc-common.dtsi"
+#include "rzg2l-smarc.dtsi"
+
+/ {
+ model = "Renesas SMARC EVK based on r9a07g044l2";
+ compatible = "renesas,smarc-evk", "renesas,r9a07g044l2", "renesas,r9a07g044";
+};
diff --git a/arch/arm/dts/r9a07g044l2.dtsi b/arch/arm/dts/r9a07g044l2.dtsi
new file mode 100644
index 0000000..91dc10b
--- /dev/null
+++ b/arch/arm/dts/r9a07g044l2.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L R9A07G044L2 SoC specific parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g044.dtsi"
+
+/ {
+ compatible = "renesas,r9a07g044l2", "renesas,r9a07g044";
+};
diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts
index f69a38f..0a27fa5 100644
--- a/arch/arm/dts/rk3328-rock64.dts
+++ b/arch/arm/dts/rk3328-rock64.dts
@@ -37,7 +37,8 @@
vin-supply = <&vcc_io>;
};
- vcc_host_5v: vcc-host-5v-regulator {
+ /* Common enable line for all of the rails mentioned in the labels */
+ vcc_host_5v: vcc_host1_5v: vcc_otg_5v: vcc-host-5v-regulator {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
@@ -48,17 +49,6 @@
vin-supply = <&vcc_sys>;
};
- vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
- compatible = "regulator-fixed";
- gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&usb20_host_drv>;
- regulator-name = "vcc_host1_5v";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc_sys>;
- };
-
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
diff --git a/arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi b/arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi
new file mode 100644
index 0000000..60a3b21
--- /dev/null
+++ b/arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+&uart2 {
+ clock-frequency = <24000000>;
+ bootph-pre-ram;
+ status = "okay";
+};
+
diff --git a/arch/arm/dts/rk3568-bpi-r2-pro.dts b/arch/arm/dts/rk3568-bpi-r2-pro.dts
new file mode 100644
index 0000000..f9127dd
--- /dev/null
+++ b/arch/arm/dts/rk3568-bpi-r2-pro.dts
@@ -0,0 +1,852 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ *
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+ model = "Bananapi-R2 Pro (RK3568) DDR4 Board";
+ compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blue_led_pin &green_led_pin>;
+
+ blue_led: led-0 {
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
+ };
+
+ green_led: led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ dc_12v: dc-12v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_receiver_pin>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ pcie30_avdd0v9: pcie30-avdd0v9-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ /* pi6c pcie clock generator feeds both ports */
+ vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <200000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
+ vcc3v3_minipcie: vcc3v3-minipcie-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_minipcie";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&minipcie_enable_h>;
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc3v3_pi6c_05>;
+ };
+
+ /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
+ vcc3v3_ngff: vcc3v3-ngff-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_ngff";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ngffpcie_enable_h>;
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc3v3_pi6c_05>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_usb_host: vcc5v0-usb-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_host_en>;
+ regulator-name = "vcc5v0_usb_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_otg_en>;
+ regulator-name = "vcc5v0_usb_otg";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+};
+
+&combphy0 {
+ /* used for USB3 */
+ status = "okay";
+};
+
+&combphy1 {
+ /* used for USB3 */
+ status = "okay";
+};
+
+&combphy2 {
+ /* used for SATA */
+ status = "okay";
+};
+
+&gmac0 {
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+ clock_in_out = "input";
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_tx_bus2
+ &gmac0_rx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_rgmii_bus>;
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f */
+ snps,reset-delays-us = <0 20000 100000>;
+ tx_delay = <0x4f>;
+ rx_delay = <0x0f>;
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_rgmii_bus>;
+
+ snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f */
+ snps,reset-delays-us = <0 20000 100000>;
+
+ tx_delay = <0x3c>;
+ rx_delay = <0x2f>;
+
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ avdd-0v9-supply = <&vdda0v9_image>;
+ avdd-1v8-supply = <&vcca1v8_image>;
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ rockchip,system-power-controller;
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+ regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2c3 {
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PD3 IRQ_TYPE_EDGE_FALLING>;
+ #clock-cells = <0>;
+ clock-output-names = "rtcic_32kout";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ wakeup-source;
+ };
+};
+
+&i2c5 {
+ /* pin 3 (SDA) + 4 (SCL) of header con2 */
+ status = "disabled";
+};
+
+&i2s0_8ch {
+ /* hdmi sound */
+ status = "okay";
+};
+
+&mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch@0 {
+ compatible = "mediatek,mt7531";
+ reg = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ label = "lan0";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan1";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan2";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan3";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ };
+};
+
+&pcie30phy {
+ data-lanes = <1 2>;
+ phy-supply = <&vcc3v3_pi6c_05>;
+ status = "okay";
+};
+
+&pcie3x1 {
+ /* M.2 slot */
+ num-lanes = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ngffpcie_reset_h>;
+ reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_ngff>;
+ status = "okay";
+};
+
+&pcie3x2 {
+ /* mPCIe slot */
+ num-lanes = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&minipcie_reset_h>;
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_minipcie>;
+ status = "okay";
+};
+
+&pinctrl {
+ leds {
+ blue_led_pin: blue-led-pin {
+ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ green_led_pin: green-led-pin {
+ rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ ir-receiver {
+ ir_receiver_pin: ir-receiver-pin {
+ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ minipcie_enable_h: minipcie-enable-h {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
+ };
+
+ ngffpcie_enable_h: ngffpcie-enable-h {
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
+ };
+
+ minipcie_reset_h: minipcie-reset-h {
+ rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
+ };
+
+ ngffpcie_reset_h: ngffpcie-reset-h {
+ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic_int {
+ rockchip,pins =
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb {
+ vcc5v0_usb_host_en: vcc5v0_usb_host_en {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_3v3>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&pwm8 {
+ /* fan 5v - gnd - pwm */
+ status = "okay";
+};
+
+&pwm10 {
+ /* pin 7 of header con2 */
+ status = "disabled";
+};
+
+&pwm11 {
+ /* pin 15 of header con2 */
+ status = "disabled";
+};
+
+&pwm12 {
+ /* pin 21 of header con2 */
+ /* shared with uart9 + spi3 */
+ pinctrl-0 = <&pwm12m1_pins>;
+ status = "disabled";
+};
+
+&pwm13 {
+ /* pin 24 of header con2 */
+ /* shared with uart9 */
+ pinctrl-0 = <&pwm13m1_pins>;
+ status = "disabled";
+};
+
+&pwm14 {
+ /* pin 23 of header con2 */
+ /* shared with spi3 */
+ pinctrl-0 = <&pwm14m1_pins>;
+ status = "disabled";
+};
+
+&pwm15 {
+ /* pin 19 of header con2 */
+ /* shared with spi3 */
+ pinctrl-0 = <&pwm15m1_pins>;
+ status = "disabled";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&spi3 {
+ /* pin 19 (MO) + 21 (MI) + 23 (CK) of header con2 */
+ /* shared with pwm12/14/15 and uart9 */
+ pinctrl-0 = <&spi3m1_pins>;
+ status = "disabled";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart0 {
+ /* pin 8 (TX) + 10 (RX) (RTS:16, CTS:18) of header con2 */
+ status = "disabled";
+};
+
+&uart2 {
+ /* debug-uart */
+ status = "okay";
+};
+
+&uart7 {
+ /* pin 11 (TX) + 13 (RX) of header con2 */
+ pinctrl-0 = <&uart7m1_xfer>;
+ status = "disabled";
+};
+
+&uart9 {
+ /* pin 21 (TX) + 24 (RX) of header con2 */
+ /* shared with pwm13 and pwm12/spi3 */
+ pinctrl-0 = <&uart9m1_xfer>;
+ status = "disabled";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ phy-supply = <&vcc5v0_usb_otg>;
+ status = "okay";
+};
+
+&usb2phy1 {
+ /* USB for PCIe/M2 */
+ status = "okay";
+};
+
+&usb2phy1_host {
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};
diff --git a/arch/arm/dts/rk3568-generic-u-boot.dtsi b/arch/arm/dts/rk3568-generic-u-boot.dtsi
new file mode 100644
index 0000000..9002258
--- /dev/null
+++ b/arch/arm/dts/rk3568-generic-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+&uart2 {
+ bootph-pre-ram;
+ clock-frequency = <24000000>;
+};
diff --git a/arch/arm/dts/rk3568-generic.dts b/arch/arm/dts/rk3568-generic.dts
new file mode 100644
index 0000000..1006ea5
--- /dev/null
+++ b/arch/arm/dts/rk3568-generic.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Minimal generic DT for RK3566/RK3568 with eMMC and SD-card enabled
+ */
+
+/dts-v1/;
+#include "rk356x.dtsi"
+
+/ {
+ model = "Generic RK3566/RK3568";
+ compatible = "rockchip,rk3568";
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+};
+
+&sdhci {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi b/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
index fe5bc6a..c0798e9 100644
--- a/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
@@ -1,3 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "rk3568-nanopi-r5s-u-boot.dtsi"
+
+&pcie3x2 {
+ /delete-property/ vpcie3v3-supply;
+};
diff --git a/arch/arm/dts/rk3568-nanopi-r5c.dts b/arch/arm/dts/rk3568-nanopi-r5c.dts
index f70ca9f..c718b8d 100644
--- a/arch/arm/dts/rk3568-nanopi-r5c.dts
+++ b/arch/arm/dts/rk3568-nanopi-r5c.dts
@@ -106,7 +106,7 @@
rockchip-key {
reset_button_pin: reset-button-pin {
- rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
diff --git a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
index 0ecca85..880f8ff 100644
--- a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
@@ -11,10 +11,13 @@
/ {
chosen {
stdout-path = &uart2;
- u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
};
};
+&pcie3x1 {
+ /delete-property/ vpcie3v3-supply;
+};
+
&sdhci {
cap-mmc-highspeed;
mmc-ddr-1_8v;
@@ -29,3 +32,8 @@
bootph-all;
status = "okay";
};
+
+&vcc5v0_usb_host {
+ /delete-property/ regulator-always-on;
+ /delete-property/ regulator-boot-on;
+};
diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
index 572bdc5..1136f0b 100644
--- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
@@ -8,9 +8,16 @@
};
};
-/* PCIe PHY driver in U-Boot does not support bifurcation */
&pcie3x1 {
- status = "disabled";
+ pinctrl-0 = <&pcie30x1_reset_h>;
+};
+
+&pinctrl {
+ pcie {
+ pcie30x1_reset_h: pcie30x1-reset-h {
+ rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&sdhci {
diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index 32f687f..354b695 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -64,6 +64,10 @@
bootph-all;
};
+&pcfg_pull_none_smt {
+ bootph-all;
+};
+
&pcfg_pull_none {
bootph-all;
};
@@ -100,6 +104,10 @@
bootph-all;
};
+&i2c0_xfer {
+ bootph-all;
+};
+
&sdmmc0_bus4 {
bootph-all;
};
diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
index 373f369..dd00582 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
@@ -11,7 +11,6 @@
};
chosen {
- stdout-path = &uart2;
u-boot,spl-boot-order = &sdmmc;
};
};
diff --git a/arch/arm/dts/rk3588-edgeble-neu6a.dtsi b/arch/arm/dts/rk3588-edgeble-neu6a.dtsi
index 38e1a1e..727580a 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6a.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6a.dtsi
@@ -25,7 +25,6 @@
no-sdio;
no-sd;
non-removable;
- max-frequency = <200000000>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
status = "okay";
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
index cd7626b..a45b3f5 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
@@ -11,12 +11,6 @@
};
chosen {
- stdout-path = &uart2;
u-boot,spl-boot-order = &sdmmc;
};
};
-
-&sdmmc {
- bus-width = <4>;
- status = "okay";
-};
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts
index e9d5a8b..9933765 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts
+++ b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts
@@ -21,7 +21,73 @@
};
};
+&combphy0_ps {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ wakeup-source;
+ };
+};
+
+&pinctrl {
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+/* FAN */
+&pwm2 {
+ pinctrl-0 = <&pwm2m1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ no-sdio;
+ no-mmc;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
+
+/* RS232 */
+&uart6 {
+ pinctrl-0 = <&uart6m0_xfer>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+/* RS485 */
+&uart7 {
+ pinctrl-0 = <&uart7m2_xfer>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b.dtsi b/arch/arm/dts/rk3588-edgeble-neu6b.dtsi
index 1c5bcf1..017559b 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6b.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6b.dtsi
@@ -18,6 +18,42 @@
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
};
&sdhci {
@@ -25,8 +61,329 @@
no-sdio;
no-sd;
non-removable;
- max-frequency = <200000000>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
status = "okay";
};
+
+&spi2 {
+ status = "okay";
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ spi-max-frequency = <1000000>;
+ reg = <0x0>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+ regulator-name = "vdd_gpu_s0";
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <400>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-name = "vdd_log_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+ regulator-name = "vdd_vdenc_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-init-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-name = "vdd_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-name = "vdd2_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-name = "vdd_2v0_pldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-name = "vcc_3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-name = "vddq_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-name = "vcc_1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_s0: pldo-reg1 {
+ regulator-name = "avcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg2 {
+ regulator-name = "vcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avdd_1v2_s0: pldo-reg3 {
+ regulator-name = "avdd_1v2_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: pldo-reg4 {
+ regulator-name = "vcc_3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-name = "vccio_sd_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-name = "pldo6_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-name = "vdd_0v75_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_ddr_pll_s0: nldo-reg2 {
+ regulator-name = "vdd_ddr_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ avdd_0v75_s0: nldo-reg3 {
+ regulator-name = "avdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: nldo-reg4 {
+ regulator-name = "vdd_0v85_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-name = "vdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi b/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi
index bd2e259..e856678 100644
--- a/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi
@@ -6,16 +6,7 @@
#include "rk3588-u-boot.dtsi"
/ {
- aliases {
- mmc0 = &sdmmc;
- mmc1 = &sdhci;
- };
-
chosen {
- u-boot,spl-boot-order = &sdhci;
+ u-boot,spl-boot-order = "same-as-spl", &sdhci;
};
};
-
-&sdhci {
- bootph-all;
-};
diff --git a/arch/arm/dts/rk3588-evb1-v10.dts b/arch/arm/dts/rk3588-evb1-v10.dts
index b91af02..b9d789d 100644
--- a/arch/arm/dts/rk3588-evb1-v10.dts
+++ b/arch/arm/dts/rk3588-evb1-v10.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3588.dtsi"
@@ -23,12 +24,84 @@
stdout-path = "serial2:1500000n8";
};
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-vol-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ press-threshold-microvolt = <17000>;
+ };
+
+ button-vol-down {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ press-threshold-microvolt = <417000>;
+ };
+
+ button-menu {
+ label = "Menu";
+ linux,code = <KEY_MENU>;
+ press-threshold-microvolt = <890000>;
+ };
+
+ button-escape {
+ label = "Escape";
+ linux,code = <KEY_ESC>;
+ press-threshold-microvolt = <1235000>;
+ };
+ };
+
backlight: backlight {
compatible = "pwm-backlight";
power-supply = <&vcc12v_dcin>;
pwms = <&pwm2 0 25000 0>;
};
+ pcie20_avdd0v85: pcie20-avdd0v85-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie20_avdd0v85";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ vin-supply = <&avdd_0v85_s0>;
+ };
+
+ pcie20_avdd1v8: pcie20-avdd1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie20_avdd1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&avcc_1v8_s0>;
+ };
+
+ pcie30_avdd0v75: pcie30-avdd0v75-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd0v75";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ vin-supply = <&avdd_0v75_s0>;
+ };
+
+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&avcc_1v8_s0>;
+ };
+
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
@@ -38,6 +111,33 @@
regulator-max-microvolt = <12000000>;
};
+ vcc3v3_pcie30: vcc3v3-pcie30-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie30";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc12v_dcin>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc3v3_pcie30_en>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_host";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
@@ -47,6 +147,66 @@
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
+
+ vcc5v0_usbdcin: vcc5v0-usbdcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usbdcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usbdcin>;
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
};
&gmac0 {
@@ -93,7 +253,32 @@
};
};
+&pcie2x1l1 {
+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_1_rst>, <&rtl8111_isolate>;
+ status = "okay";
+};
+
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3_reset>;
+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
+ status = "okay";
+};
+
&pinctrl {
+ rtl8111 {
+ rtl8111_isolate: rtl8111-isolate {
+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
rtl8211f {
rtl8211f_rst: rtl8211f-rst {
rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -106,24 +291,693 @@
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
+
+ pcie2 {
+ pcie2_1_rst: pcie2-1-rst {
+ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie3 {
+ pcie3_reset: pcie3-reset {
+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc3v3_pcie30_en: vcc3v3-pcie30-en {
+ rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&pwm2 {
status = "okay";
};
+&saradc {
+ vref-supply = <&vcc_1v8_s0>;
+ status = "okay";
+};
+
&sdhci {
bus-width = <8>;
no-sdio;
no-sd;
non-removable;
- max-frequency = <200000000>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
status = "okay";
};
+&spi2 {
+ status = "okay";
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <2>;
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ reg = <0x0>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ pinctrl-names = "default";
+ spi-max-frequency = <1000000>;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc5v0_sys>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+
+ regulators {
+ vdd_gpu_s0: dcdc-reg1 {
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_gpu_s0";
+ regulator-enable-ramp-delay = <400>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_npu_s0: dcdc-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_npu_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_log_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: dcdc-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_vdenc_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+
+ };
+
+ vdd_gpu_mem_s0: dcdc-reg5 {
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <400>;
+ regulator-name = "vdd_gpu_mem_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+
+ };
+
+ vdd_npu_mem_s0: dcdc-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_npu_mem_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_2v0_pldo_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vdd_vdenc_mem_s0: dcdc-reg8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_vdenc_mem_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vdd2_ddr_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v1_nldo_s3: dcdc-reg10 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1100000>;
+ };
+ };
+
+ avcc_1v8_s0: pldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "avcc_1v8_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd1_1v8_ddr_s3: pldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd1_1v8_ddr_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_codec_s0: pldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "avcc_1v8_codec_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s3: pldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_3v3_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vccio_sd_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_1v8_s3: pldo-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vccio_1v8_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_0v75_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd2l_0v9_ddr_s3: nldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdd2l_0v9_ddr_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdd_0v75_hdmi_edp_s0: nldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_hdmi_edp_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ avdd_0v75_s0: nldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "avdd_0v75_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: nldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_0v85_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ pmic@1 {
+ compatible = "rockchip,rk806";
+ reg = <0x01>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>,
+ <&rk806_slave_dvs3_null>;
+ pinctrl-names = "default";
+ spi-max-frequency = <1000000>;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_2v0_pldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ rk806_slave_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun0";
+ };
+
+ rk806_slave_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_slave_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_cpu_big1_s0: dcdc-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big0_s0: dcdc-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: dcdc-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: dcdc-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_3v3_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_mem_s0: dcdc-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_big1_mem_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+
+ vdd_cpu_big0_mem_s0: dcdc-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_big0_mem_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: dcdc-reg7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_1v8_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_mem_s0: dcdc-reg8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_lit_mem_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vddq_ddr_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg10 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_ddr_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_cam_s0: pldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_1v8_cam_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ avdd1v8_ddr_pll_s0: pldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "avdd1v8_ddr_pll_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_1v8_pll_s0: pldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_1v8_pll_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_sd_s0: pldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_3v3_sd_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_2v8_cam_s0: pldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_2v8_cam_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "pldo6_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_pll_s0: nldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_0v75_pll_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_pll_s0: nldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_ddr_pll_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ avdd_0v85_s0: nldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "avdd_0v85_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ avdd_1v2_cam_s0: nldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "avdd_1v2_cam_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ avdd_1v2_s0: nldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "avdd_1v2_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy3_host {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi b/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi
new file mode 100644
index 0000000..87831c9
--- /dev/null
+++ b/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 John Clark <inindev@gmail.com>
+ *
+ */
+
+#include "rk3588-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+ };
+};
+
+&fspim1_pins {
+ bootph-all;
+};
+
+&sfc {
+ bootph-pre-ram;
+ u-boot,spl-sfc-no-dma;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspim1_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ bootph-pre-ram;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
diff --git a/arch/arm/dts/rk3588-nanopc-t6.dts b/arch/arm/dts/rk3588-nanopc-t6.dts
new file mode 100644
index 0000000..97af4f9
--- /dev/null
+++ b/arch/arm/dts/rk3588-nanopc-t6.dts
@@ -0,0 +1,916 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2023 Thomas McKahan
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3588.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPC-T6";
+ compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ serial2 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ sys_led: led-0 {
+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ label = "system-led";
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sys_led_pin>;
+ };
+
+ usr_led: led-1 {
+ gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+ label = "user-led";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usr_led_pin>;
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_det>;
+
+ simple-audio-card,name = "realtek,rt5616-codec";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+
+ simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>;
+ simple-audio-card,hp-pin-name = "Headphones";
+
+ simple-audio-card,widgets =
+ "Headphone", "Headphones",
+ "Microphone", "Microphone Jack";
+ simple-audio-card,routing =
+ "Headphones", "HPOL",
+ "Headphones", "HPOR",
+ "MIC1", "Microphone Jack",
+ "Microphone Jack", "micbias1";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s0_8ch>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&rt5616>;
+ };
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ /* vcc5v0_sys powers peripherals */
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ /* vcc4v0_sys powers the RK806, RK860's */
+ vcc4v0_sys: vcc4v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc4v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <4000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-1v1-nldo-s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc4v0_sys>;
+ };
+
+ vcc_3v3_pcie20: vcc3v3-pcie20-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_pcie20";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vbus5v0_typec: vbus5v0-typec-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&typec5v_pwren>;
+ regulator-name = "vbus5v0_typec";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_m2_1_pwren>;
+ regulator-name = "vcc3v3_pcie2x1l0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_pcie30: vcc3v3-pcie30-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_m2_0_pwren>;
+ regulator-name = "vcc3v3_pcie30";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy1_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_b0{
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1{
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2{
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3{
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&gpio0 {
+ gpio-line-names = /* GPIO0 A0-A7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO0 B0-B7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO0 C0-C7 */
+ "", "", "", "",
+ "HEADER_10", "HEADER_08", "HEADER_32", "",
+ /* GPIO0 D0-D7 */
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio1 {
+ gpio-line-names = /* GPIO1 A0-A7 */
+ "HEADER_27", "HEADER_28", "", "",
+ "", "", "", "HEADER_15",
+ /* GPIO1 B0-B7 */
+ "HEADER_26", "HEADER_21", "HEADER_19", "HEADER_23",
+ "HEADER_24", "HEADER_22", "", "",
+ /* GPIO1 C0-C7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO1 D0-D7 */
+ "", "", "", "",
+ "", "", "HEADER_05", "HEADER_03";
+};
+
+&gpio2 {
+ gpio-line-names = /* GPIO2 A0-A7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO2 B0-B7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO2 C0-C7 */
+ "", "CSI1_11", "CSI1_12", "",
+ "", "", "", "",
+ /* GPIO2 D0-D7 */
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio3 {
+ gpio-line-names = /* GPIO3 A0-A7 */
+ "HEADER_35", "HEADER_38", "HEADER_40", "HEADER_36",
+ "HEADER_37", "", "DSI0_12", "",
+ /* GPIO3 B0-B7 */
+ "HEADER_33", "DSI0_10", "HEADER_07", "HEADER_16",
+ "HEADER_18", "HEADER_29", "HEADER_31", "HEADER_12",
+ /* GPIO3 C0-C7 */
+ "DSI0_08", "DSI0_14", "HEADER_11", "HEADER_13",
+ "", "", "", "",
+ /* GPIO3 D0-D7 */
+ "", "", "", "",
+ "", "DSI1_10", "", "";
+};
+
+&gpio4 {
+ gpio-line-names = /* GPIO4 A0-A7 */
+ "DSI1_08", "DSI1_14", "", "DSI1_12",
+ "", "", "", "",
+ /* GPIO4 B0-B7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO4 C0-C7 */
+ "", "", "", "",
+ "CSI0_11", "CSI0_12", "", "",
+ /* GPIO4 D0-D7 */
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc4v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc4v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ vdd_npu_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ rockchip,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_npu_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc4v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c6 {
+ clock-frequency = <200000>;
+ status = "okay";
+
+ fusb302: typec-portc@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&usbc0_int>;
+ pinctrl-names = "default";
+ vbus-supply = <&vbus5v0_typec>;
+
+ connector {
+ compatible = "usb-c-connector";
+ data-role = "dual";
+ label = "USB-C";
+ power-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ op-sink-microwatt = <1000000>;
+ };
+ };
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+ wakeup-source;
+ };
+};
+
+&i2c7 {
+ clock-frequency = <200000>;
+ status = "okay";
+
+ rt5616: codec@1b {
+ compatible = "realtek,rt5616";
+ reg = <0x1b>;
+ clocks = <&cru I2S0_8CH_MCLKOUT>;
+ clock-names = "mclk";
+ #sound-dai-cells = <0>;
+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+ assigned-clock-rates = <12288000>;
+
+ port {
+ rt5616_p0_0: endpoint {
+ remote-endpoint = <&i2s0_8ch_p0_0>;
+ };
+ };
+ };
+
+ /* connected with MIPI-CSI1 */
+};
+
+&i2c8 {
+ pinctrl-0 = <&i2c8m2_xfer>;
+};
+
+&i2s0_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_lrck
+ &i2s0_mclk
+ &i2s0_sclk
+ &i2s0_sdi0
+ &i2s0_sdo0>;
+ status = "okay";
+
+ i2s0_8ch_p0: port {
+ i2s0_8ch_p0_0: endpoint {
+ dai-format = "i2s";
+ mclk-fs = <256>;
+ remote-endpoint = <&rt5616_p0_0>;
+ };
+ };
+};
+
+&pcie2x1l0 {
+ reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc_3v3_pcie20>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_0_rst>;
+ status = "okay";
+};
+
+&pcie2x1l1 {
+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_1_rst>;
+ status = "okay";
+};
+
+&pcie2x1l2 {
+ reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc_3v3_pcie20>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_2_rst>;
+ status = "okay";
+};
+
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x4 {
+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
+ status = "okay";
+};
+
+&pinctrl {
+ gpio-leds {
+ sys_led_pin: sys-led-pin {
+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usr_led_pin: usr-led-pin {
+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ headphone {
+ hp_det: hp-det {
+ rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ pcie {
+ pcie2_0_rst: pcie2-0-rst {
+ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie2_1_rst: pcie2-1-rst {
+ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie2_2_rst: pcie2-2-rst {
+ rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie_m2_0_pwren: pcie-m20-pwren {
+ rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie_m2_1_pwren: pcie-m21-pwren {
+ rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ typec5v_pwren: typec5v-pwren {
+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usbc0_int: usbc0-int {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&pwm1 {
+ pinctrl-0 = <&pwm1m1_pins>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&avcc_1v8_s0>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ max-frequency = <200000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ status = "okay";
+};
+
+&sdmmc {
+ max-frequency = <200000000>;
+ no-sdio;
+ no-mmc;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&spi2 {
+ status = "okay";
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+ num-cs = <1>;
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ spi-max-frequency = <1000000>;
+ reg = <0x0>;
+
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+
+ vcc1-supply = <&vcc4v0_sys>;
+ vcc2-supply = <&vcc4v0_sys>;
+ vcc3-supply = <&vcc4v0_sys>;
+ vcc4-supply = <&vcc4v0_sys>;
+ vcc5-supply = <&vcc4v0_sys>;
+ vcc6-supply = <&vcc4v0_sys>;
+ vcc7-supply = <&vcc4v0_sys>;
+ vcc8-supply = <&vcc4v0_sys>;
+ vcc9-supply = <&vcc4v0_sys>;
+ vcc10-supply = <&vcc4v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc4v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc4v0_sys>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_gpu_s0";
+ regulator-enable-ramp-delay = <400>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_lit_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_log_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-init-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_vdenc_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_ddr_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vdd2_ddr_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_2v0_pldo_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_3v3_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vddq_ddr_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_s0: pldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "avcc_1v8_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avdd_1v2_s0: pldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "avdd_1v2_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: pldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_3v3_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vccio_sd_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "pldo6_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_ddr_pll_s0: nldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_ddr_pll_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ avdd_0v75_s0: nldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "avdd_0v75_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: nldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_0v85_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
+
+&u2phy2_host {
+ status = "okay";
+};
+
+&u2phy3_host {
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi b/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi
new file mode 100644
index 0000000..b0f5c66
--- /dev/null
+++ b/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+ };
+};
+
+&fspim1_pins {
+ bootph-all;
+};
+
+&sdhci {
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+};
+
+&sfc {
+ bootph-pre-ram;
+ u-boot,spl-sfc-no-dma;
+
+ flash@0 {
+ bootph-pre-ram;
+ };
+};
diff --git a/arch/arm/dts/rk3588-orangepi-5-plus.dts b/arch/arm/dts/rk3588-orangepi-5-plus.dts
new file mode 100644
index 0000000..298c183
--- /dev/null
+++ b/arch/arm/dts/rk3588-orangepi-5-plus.dts
@@ -0,0 +1,848 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Ondřej Jirman <megi@xff.cz>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3588.dtsi"
+
+/ {
+ model = "Xunlong Orange Pi 5 Plus";
+ compatible = "xunlong,orangepi-5-plus", "rockchip,rk3588";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ serial2 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ adc-keys-0 {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-maskrom {
+ label = "Mask Rom";
+ linux,code = <KEY_SETUP>;
+ press-threshold-microvolt = <2000>;
+ };
+ };
+
+ adc-keys-1 {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-recovery {
+ label = "Recovery";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <2000>;
+ };
+ };
+
+ speaker_amp: speaker-audio-amplifier {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
+ sound-name-prefix = "Speaker Amp";
+ };
+
+ headphone_amp: headphones-audio-amplifier {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
+ sound-name-prefix = "Headphones Amp";
+ };
+
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_receiver_pin>;
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blue_led_pin>;
+
+ led {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_INDICATOR;
+ function-enumerator = <1>;
+ gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ cooling-levels = <0 70 75 80 100>;
+ fan-supply = <&vcc5v0_sys>;
+ pwms = <&pwm3 0 50000 0>;
+ #cooling-cells = <2>;
+ };
+
+ pwm-leds {
+ compatible = "pwm-leds";
+
+ led {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_INDICATOR;
+ function-enumerator = <2>;
+ max-brightness = <255>;
+ pwms = <&pwm2 0 25000 0>;
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_detect>;
+ simple-audio-card,name = "Analog";
+ simple-audio-card,aux-devs = <&speaker_amp>, <&headphone_amp>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,hp-det-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>;
+ simple-audio-card,bitclock-master = <&daicpu>;
+ simple-audio-card,frame-master = <&daicpu>;
+ /*TODO: SARADC_IN3 is used as MIC detection / key input */
+
+ simple-audio-card,widgets =
+ "Microphone", "Onboard Microphone",
+ "Microphone", "Microphone Jack",
+ "Speaker", "Speaker",
+ "Headphone", "Headphones";
+
+ simple-audio-card,routing =
+ "Headphones", "LOUT1",
+ "Headphones", "ROUT1",
+ "Speaker", "LOUT2",
+ "Speaker", "ROUT2",
+
+ "Headphones", "Headphones Amp OUTL",
+ "Headphones", "Headphones Amp OUTR",
+ "Headphones Amp INL", "LOUT1",
+ "Headphones Amp INR", "ROUT1",
+
+ "Speaker", "Speaker Amp OUTL",
+ "Speaker", "Speaker Amp OUTR",
+ "Speaker Amp INL", "LOUT2",
+ "Speaker Amp INR", "ROUT2",
+
+ /* single ended signal to LINPUT1 */
+ "LINPUT1", "Microphone Jack",
+ "RINPUT1", "Microphone Jack",
+ /* differential signal */
+ "LINPUT2", "Onboard Microphone",
+ "RINPUT2", "Onboard Microphone";
+
+ daicpu: simple-audio-card,cpu {
+ sound-dai = <&i2s0_8ch>;
+ system-clock-frequency = <12288000>;
+ };
+
+ daicodec: simple-audio-card,codec {
+ sound-dai = <&es8388>;
+ system-clock-frequency = <12288000>;
+ };
+ };
+
+ vcc3v3_pcie30: vcc3v3-pcie30-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc3v3_pcie30";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_pcie_eth: vcc3v3-pcie-eth-regulator {
+ compatible = "regulator-fixed";
+ gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
+ regulator-name = "vcc3v3_pcie_eth";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_wf: vcc3v3-wf-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc3v3_wf";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc5v0_usb20: vcc5v0-usb20-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb20_en>;
+ regulator-name = "vcc5v0_usb20";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy1_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c6 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ wakeup-source;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+
+ /* PLDO2 vcca 1.8V, BUCK8 gated by PLDO2 being enabled */
+ es8388: audio-codec@11 {
+ compatible = "everest,es8388";
+ reg = <0x11>;
+ clocks = <&cru I2S0_8CH_MCLKOUT>;
+ clock-names = "mclk";
+ AVDD-supply = <&vcc_1v8_s0>;
+ DVDD-supply = <&vcc_1v8_s0>;
+ HPVDD-supply = <&vcc_3v3_s0>;
+ PVDD-supply = <&vcc_3v3_s0>;
+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+ assigned-clock-rates = <12288000>;
+ #sound-dai-cells = <0>;
+ };
+};
+
+&i2s0_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_lrck
+ &i2s0_mclk
+ &i2s0_sclk
+ &i2s0_sdi0
+ &i2s0_sdo0>;
+ status = "okay";
+};
+
+&i2s2_2ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s2m0_lrck
+ &i2s2m0_sclk
+ &i2s2m0_sdi
+ &i2s2m0_sdo>;
+ status = "okay";
+};
+
+/* phy1 - M.KEY socket */
+&pcie2x1l0 {
+ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_wf>;
+ status = "okay";
+};
+
+/* phy2 - right ethernet port */
+&pcie2x1l1 {
+ reset-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie_eth>;
+ status = "okay";
+};
+
+/* phy0 - left ethernet port */
+&pcie2x1l2 {
+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie_eth>;
+ status = "okay";
+};
+
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x4 {
+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
+ status = "okay";
+};
+
+&pinctrl {
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ blue_led_pin: blue-led {
+ rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ ir-receiver {
+ ir_receiver_pin: ir-receiver-pin {
+ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sound {
+ hp_detect: hp-detect {
+ rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc5v0_usb20_en: vcc5v0-usb20-en {
+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm2 {
+ pinctrl-0 = <&pwm2m1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pwm3 {
+ pinctrl-0 = <&pwm3m1_pins>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8_s0>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ max-frequency = <200000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ max-frequency = <150000000>;
+ no-sdio;
+ no-mmc;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&sfc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspim1_pins>;
+ status = "okay";
+
+ spi_flash: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-max-frequency = <100000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
+&spi2 {
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+ status = "okay";
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ reg = <0x0>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ spi-max-frequency = <1000000>;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vdd2_ddr_s3>;
+ vcc14-supply = <&vdd2_ddr_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: dcdc-reg1 {
+ regulator-name = "vdd_gpu_s0";
+ regulator-boot-on;
+ regulator-enable-ramp-delay = <400>;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: dcdc-reg2 {
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-name = "vdd_log_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <825000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: dcdc-reg4 {
+ regulator-name = "vdd_vdenc_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <825000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-name = "vdd_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-name = "vdd2_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-name = "vdd_2v0_pldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-name = "vcc_3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-name = "vddq_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-name = "vcc_1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_s0: pldo-reg1 {
+ regulator-name = "avcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ /* shorted to avcc_1v8_s0 on the board */
+ vcc_1v8_s0: pldo-reg2 {
+ regulator-name = "vcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avdd_1v2_s0: pldo-reg3 {
+ regulator-name = "avdd_1v2_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: pldo-reg4 {
+ regulator-name = "vcc_3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-name = "vccio_sd_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-name = "pldo6_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-name = "vdd_0v75_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_ddr_pll_s0: nldo-reg2 {
+ regulator-name = "vdd_ddr_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ avdd_0v75_s0: nldo-reg3 {
+ regulator-name = "avdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ /*
+ * The schematic mentions that actual setting
+ * should be 0.8375V. RK3588 datasheet specifies
+ * maximum as 0.825V. So we set datasheet max
+ * here.
+ */
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <825000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: nldo-reg4 {
+ regulator-name = "vdd_0v85_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-name = "vdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ phy-supply = <&vcc5v0_usb20>;
+ status = "okay";
+};
+
+&u2phy3_host {
+ phy-supply = <&vcc5v0_usb20>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
+
+&uart9 {
+ pinctrl-0 = <&uart9m0_xfer>;
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi b/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi
new file mode 100644
index 0000000..191ec98
--- /dev/null
+++ b/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Google, Inc
+ */
+
+#include "rk3588-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+ };
+};
diff --git a/arch/arm/dts/rk3588-quartzpro64.dts b/arch/arm/dts/rk3588-quartzpro64.dts
new file mode 100644
index 0000000..5c59f95
--- /dev/null
+++ b/arch/arm/dts/rk3588-quartzpro64.dts
@@ -0,0 +1,1137 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Ondřej Jirman <megi@xff.cz>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3588.dtsi"
+
+/ {
+ model = "PINE64 QuartzPro64";
+ compatible = "pine64,quartzpro64", "rockchip,rk3588";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ serial2 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ adc-keys-0 {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-maskrom {
+ label = "Mask Rom";
+ linux,code = <KEY_SETUP>;
+ press-threshold-microvolt = <393>;
+ };
+ };
+
+ adc-keys-1 {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-volume-up {
+ label = "V+/REC";
+ linux,code = <KEY_VOLUMEUP>;
+ press-threshold-microvolt = <17821>;
+ };
+
+ button-volume-down {
+ label = "V-";
+ linux,code = <KEY_VOLUMEDOWN>;
+ press-threshold-microvolt = <415384>;
+ };
+
+ button-menu {
+ label = "MENU";
+ linux,code = <KEY_MENU>;
+ press-threshold-microvolt = <890909>;
+ };
+
+ button-esc {
+ label = "ESC";
+ linux,code = <KEY_ESC>;
+ press-threshold-microvolt = <1233962>;
+ };
+ };
+
+ headphone_amp: audio-amplifier-headphone {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+ sound-name-prefix = "Headphones Amp";
+ };
+
+ speaker_amp: audio-amplifier-speaker {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
+ sound-name-prefix = "Speaker Amp";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins>;
+
+ led-1 {
+ color = <LED_COLOR_ID_ORANGE>;
+ function = LED_FUNCTION_INDICATOR;
+ gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_detect>;
+ simple-audio-card,name = "Analog";
+ simple-audio-card,aux-devs = <&speaker_amp>, <&headphone_amp>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
+ simple-audio-card,bitclock-master = <&daicpu>;
+ simple-audio-card,frame-master = <&daicpu>;
+ /* SARADC_IN3 is used as MIC detection / key input */
+
+ simple-audio-card,widgets =
+ "Microphone", "Onboard Microphone",
+ "Microphone", "Microphone Jack",
+ "Speaker", "Speaker",
+ "Headphone", "Headphones";
+
+ simple-audio-card,routing =
+ "Headphones", "LOUT1",
+ "Headphones", "ROUT1",
+ "Speaker", "LOUT2",
+ "Speaker", "ROUT2",
+
+ "Headphones", "Headphones Amp OUTL",
+ "Headphones", "Headphones Amp OUTR",
+ "Headphones Amp INL", "LOUT1",
+ "Headphones Amp INR", "ROUT1",
+
+ "Speaker", "Speaker Amp OUTL",
+ "Speaker", "Speaker Amp OUTR",
+ "Speaker Amp INL", "LOUT2",
+ "Speaker Amp INR", "ROUT2",
+
+ /* single ended signal to LINPUT1 */
+ "LINPUT1", "Microphone Jack",
+ "RINPUT1", "Microphone Jack",
+ /* differential signal */
+ "LINPUT2", "Onboard Microphone",
+ "RINPUT2", "Onboard Microphone";
+
+ daicpu: simple-audio-card,cpu {
+ sound-dai = <&i2s0_8ch>;
+ system-clock-frequency = <12288000>;
+ };
+
+ daicodec: simple-audio-card,codec {
+ sound-dai = <&es8388>;
+ system-clock-frequency = <12288000>;
+ };
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc3v3_bt: vcc3v3-bt-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc3v3_bt";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc_3v3_s0>;
+ };
+
+ vcc3v3_pcie30: vcc3v3-pcie30-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc3v3_pcie30";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc3v3_wf: vcc3v3-wf-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc3v3_wf";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc_3v3_s0>;
+ };
+
+ vcc4v0_sys: vcc4v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc4v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <4000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy1_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gmac0 {
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy>;
+ phy-mode = "rgmii-rxid";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_tx_bus2
+ &gmac0_rx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_rgmii_bus>;
+ rx_delay = <0x00>;
+ tx_delay = <0x43>;
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ wakeup-source;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+
+ es8388: audio-codec@11 {
+ compatible = "everest,es8388";
+ reg = <0x11>;
+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+ assigned-clock-rates = <12288000>;
+ clocks = <&cru I2S0_8CH_MCLKOUT>;
+ clock-names = "mclk";
+ AVDD-supply = <&avcc_1v8_codec_s0>;
+ DVDD-supply = <&avcc_1v8_codec_s0>;
+ HPVDD-supply = <&vcc_3v3_s0>;
+ PVDD-supply = <&vcc_3v3_s0>;
+ #sound-dai-cells = <0>;
+ };
+};
+
+&i2s0_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_lrck
+ &i2s0_mclk
+ &i2s0_sclk
+ &i2s0_sdi0
+ &i2s0_sdo0>;
+ status = "okay";
+};
+
+&mdio0 {
+ rgmii_phy: ethernet-phy@1 {
+ /* RTL8211F */
+ compatible = "ethernet-phy-id001c.c916";
+ reg = <0x1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtl8211f_rst>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pinctrl {
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ leds {
+ led_pins: led-pins {
+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ rtl8111 {
+ rtl8111_isolate: rtl8111-isolate {
+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ rtl8211f {
+ rtl8211f_rst: rtl8211f-rst {
+ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ };
+
+ sound {
+ hp_detect: hp-detect {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+/* WIFI */
+&pcie2x1l0 {
+ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_wf>;
+ status = "okay";
+};
+
+/* GMAC1 */
+&pcie2x1l1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtl8111_isolate>;
+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x4 {
+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8_s0>;
+ status = "okay";
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ max-frequency = <150000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ max-frequency = <150000000>;
+ no-sdio;
+ no-mmc;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&spi2 {
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <2>;
+ status = "okay";
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ reg = <0x0>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ pinctrl-names = "default";
+ spi-max-frequency = <1000000>;
+
+ vcc1-supply = <&vcc4v0_sys>;
+ vcc2-supply = <&vcc4v0_sys>;
+ vcc3-supply = <&vcc4v0_sys>;
+ vcc4-supply = <&vcc4v0_sys>;
+ vcc5-supply = <&vcc4v0_sys>;
+ vcc6-supply = <&vcc4v0_sys>;
+ vcc7-supply = <&vcc4v0_sys>;
+ vcc8-supply = <&vcc4v0_sys>;
+ vcc9-supply = <&vcc4v0_sys>;
+ vcc10-supply = <&vcc4v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc4v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc4v0_sys>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: dcdc-reg1 {
+ regulator-name = "vdd_gpu_s0";
+ regulator-boot-on;
+ regulator-enable-ramp-delay = <400>;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_npu_s0: dcdc-reg2 {
+ regulator-name = "vdd_npu_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-name = "vdd_log_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: dcdc-reg4 {
+ regulator-name = "vdd_vdenc_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+
+ };
+
+ vdd_gpu_mem_s0: dcdc-reg5 {
+ regulator-name = "vdd_gpu_mem_s0";
+ regulator-boot-on;
+ regulator-enable-ramp-delay = <400>;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+
+ };
+
+ vdd_npu_mem_s0: dcdc-reg6 {
+ regulator-name = "vdd_npu_mem_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-name = "vdd_2v0_pldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vdd_vdenc_mem_s0: dcdc-reg8 {
+ regulator-name = "vdd_vdenc_mem_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg9 {
+ regulator-name = "vdd2_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v1_nldo_s3: dcdc-reg10 {
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1100000>;
+ };
+ };
+
+ avcc_1v8_s0: pldo-reg1 {
+ regulator-name = "avcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd1_1v8_ddr_s3: pldo-reg2 {
+ regulator-name = "vdd1_1v8_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_codec_s0: pldo-reg3 {
+ regulator-name = "avcc_1v8_codec_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s3: pldo-reg4 {
+ regulator-name = "vcc_3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-name = "vccio_sd_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: pldo-reg6 {
+ regulator-name = "vcc_1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-name = "vdd_0v75_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ /* reserved for LPDDR5, unused? */
+ vdd2l_0v9_ddr_s3: nldo-reg2 {
+ regulator-name = "vdd2l_0v9_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdd_0v75_hdmi_edp_s0: nldo-reg3 {
+ regulator-name = "vdd_0v75_hdmi_edp_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ avdd_0v75_s0: nldo-reg4 {
+ regulator-name = "avdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: nldo-reg5 {
+ regulator-name = "vdd_0v85_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ pmic@1 {
+ compatible = "rockchip,rk806";
+ reg = <0x01>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>,
+ <&rk806_slave_dvs3_null>;
+ pinctrl-names = "default";
+ spi-max-frequency = <1000000>;
+
+ vcc1-supply = <&vcc4v0_sys>;
+ vcc2-supply = <&vcc4v0_sys>;
+ vcc3-supply = <&vcc4v0_sys>;
+ vcc4-supply = <&vcc4v0_sys>;
+ vcc5-supply = <&vcc4v0_sys>;
+ vcc6-supply = <&vcc4v0_sys>;
+ vcc7-supply = <&vcc4v0_sys>;
+ vcc8-supply = <&vcc4v0_sys>;
+ vcc9-supply = <&vcc4v0_sys>;
+ vcc10-supply = <&vcc4v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc4v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_2v0_pldo_s3>;
+ vcca-supply = <&vcc4v0_sys>;
+
+ rk806_slave_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun0";
+ };
+
+ rk806_slave_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_slave_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_cpu_big1_s0: dcdc-reg1 {
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big0_s0: dcdc-reg2 {
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: dcdc-reg3 {
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: dcdc-reg4 {
+ regulator-name = "vcc_3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_mem_s0: dcdc-reg5 {
+ regulator-name = "vdd_cpu_big1_mem_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+
+ vdd_cpu_big0_mem_s0: dcdc-reg6 {
+ regulator-name = "vdd_cpu_big0_mem_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: dcdc-reg7 {
+ regulator-name = "vcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_mem_s0: dcdc-reg8 {
+ regulator-name = "vdd_cpu_lit_mem_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-name = "vddq_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg10 {
+ regulator-name = "vdd_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ /* reserved, unused? */
+ vcc_1v8_cam_s0: pldo-reg1 {
+ regulator-name = "vcc_1v8_cam_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ avdd1v8_ddr_pll_s0: pldo-reg2 {
+ regulator-name = "avdd1v8_ddr_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_1v8_pll_s0: pldo-reg3 {
+ regulator-name = "vdd_1v8_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ /* reserved, unused? */
+ vcc_3v3_sd_s0: pldo-reg4 {
+ regulator-name = "vcc_3v3_sd_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ /* reserved, unused? */
+ vcc_2v8_cam_s0: pldo-reg5 {
+ regulator-name = "vcc_2v8_cam_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ /* unused */
+ pldo6_s3: pldo-reg6 {
+ regulator-name = "pldo6_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_pll_s0: nldo-reg1 {
+ regulator-name = "vdd_0v75_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_pll_s0: nldo-reg2 {
+ regulator-name = "vdd_ddr_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ avdd_0v85_s0: nldo-reg3 {
+ regulator-name = "avdd_0v85_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ /* reserved, unused */
+ avdd_1v2_cam_s0: nldo-reg4 {
+ regulator-name = "avdd_1v2_cam_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ avdd_1v2_s0: nldo-reg5 {
+ regulator-name = "avdd_1v2_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy3_host {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 1b2fcbb..b595dde 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -4,16 +4,9 @@
*/
#include "rk3588-u-boot.dtsi"
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/usb/pd.h>
/ {
- aliases {
- mmc1 = &sdmmc;
- };
-
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
};
@@ -26,53 +19,9 @@
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
-
- vcc5v0_usbdcin: vcc5v0-usbdcin {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usbdcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc5v0_host: vcc5v0-host-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_host";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_usb: vcc5v0-usb {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usbdcin>;
- };
-
- vbus5v0_typec: vbus5v0-typec {
- compatible = "regulator-fixed";
- regulator-name = "vbus5v0_typec";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
- vin-supply = <&vcc5v0_usb>;
- pinctrl-names = "default";
- pinctrl-0 = <&typec5v_pwren>;
- };
};
-&combphy0_ps {
+&combphy2_psu {
status = "okay";
};
@@ -80,53 +29,18 @@
bootph-all;
};
-&pcie2x1l2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie2x1l2_pins &pcie_reset_h>;
- reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
&pinctrl {
- pcie {
- pcie_reset_h: pcie-reset-h {
- rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie2x1l2_pins: pcie2x1l2-pins {
- rockchip,pins = <3 RK_PC7 4 &pcfg_pull_none>,
- <3 RK_PD0 4 &pcfg_pull_none>;
- };
- };
-
usb {
- vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb-typec {
usbc0_int: usbc0-int {
- rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- typec5v_pwren: typec5v-pwren {
- rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
-&sdmmc {
- bus-width = <4>;
- status = "okay";
-};
-
&sdhci {
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>;
};
&sfc {
@@ -134,8 +48,6 @@
u-boot,spl-sfc-no-dma;
pinctrl-names = "default";
pinctrl-0 = <&fspim2_pins>;
- #address-cells = <1>;
- #size-cells = <0>;
status = "okay";
flash@0 {
@@ -148,127 +60,11 @@
};
};
-&usb_host0_ehci {
- companion = <&usb_host0_ohci>;
- phys = <&u2phy2_host>;
- phy-names = "usb2-phy";
- status = "okay";
-};
-
-&usb_host0_ohci {
- phys = <&u2phy2_host>;
- phy-names = "usb2-phy";
- status = "okay";
-};
-
-&usb2phy2_grf {
- status = "okay";
-};
-
&u2phy0 {
status = "okay";
};
&u2phy0_otg {
- rockchip,typec-vbus-det;
- status = "okay";
-};
-
-&u2phy2 {
- resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
- reset-names = "phy", "apb";
- clock-output-names = "usb480m_phy2";
- status = "okay";
-};
-
-&u2phy2_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
-};
-
-&usb_host1_ehci {
- companion = <&usb_host1_ohci>;
- phys = <&u2phy3_host>;
- phy-names = "usb2-phy";
- status = "okay";
-};
-
-&usb_host1_ohci {
- phys = <&u2phy3_host>;
- phy-names = "usb2-phy";
- status = "okay";
-};
-
-&usb2phy3_grf {
- status = "okay";
-};
-
-&u2phy3 {
- resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
- reset-names = "phy", "apb";
- clock-output-names = "usb480m_phy3";
- status = "okay";
-};
-
-&u2phy3_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
-};
-
-&usbdp_phy0 {
- orientation-switch;
- svid = <0xff01>;
- sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
- sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
- status = "okay";
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
- usbdp_phy0_orientation_switch: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&usbc0_orien_sw>;
- };
-
- usbdp_phy0_dp_altmode_mux: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&dp_altmode_mux>;
- };
- };
-};
-
-&usbdp_phy0_u3 {
- status = "okay";
-};
-
-&usbdrd3_0 {
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- dr_mode = "otg";
- usb-role-switch;
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
- dwc3_0_role_switch: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&usbc0_role_sw>;
- };
- };
-};
-
-&usbdp_phy1 {
- rockchip,dp-lane-mux = <2 3>;
- status = "okay";
-};
-
-&usbdp_phy1_u3 {
- status = "okay";
-};
-
-&usbdrd3_1 {
status = "okay";
};
@@ -280,54 +76,88 @@
status = "okay";
};
+&usbdp_phy1 {
+ status = "okay";
+};
+
+&usbdp_phy1_u3 {
+ status = "okay";
+};
+
+&usbdp_phy0 {
+ orientation-switch;
+ mode-switch;
+ sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbdp_phy0_typec_ss: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&usbc0_ss>;
+ };
+
+ usbdp_phy0_typec_sbu: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&usbc0_sbu>;
+ };
+ };
+};
+
+&usbdp_phy0_u3 {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ usb-role-switch;
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb_host0_xhci_drd_sw: endpoint {
+ remote-endpoint = <&usbc0_hs>;
+ };
+ };
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb_host2_xhci {
+ status = "okay";
+};
+
&i2c4 {
+ pinctrl-names = "default";
pinctrl-0 = <&i2c4m1_xfer>;
status = "okay";
- usbc0: fusb302@22 {
+ usbc0: usb-typec@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&usbc0_int>;
- vbus-supply = <&vbus5v0_typec>;
+ vbus-supply = <&vcc12v_dcin>;
status = "okay";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- usbc0_role_sw: endpoint@0 {
- remote-endpoint = <&dwc3_0_role_switch>;
- };
- };
- };
-
usb_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
- power-role = "dual";
+ power-role = "sink";
try-power-role = "sink";
op-sink-microwatt = <1000000>;
sink-pdos =
- <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
- source-pdos =
- <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
-
- altmodes {
- #address-cells = <1>;
- #size-cells = <0>;
-
- altmode@0 {
- reg = <0>;
- svid = <0xff01>;
- vdo = <0xffffffff>;
- };
- };
+ <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>,
+ <PDO_VAR(5000, 20000, 5000)>;
ports {
#address-cells = <1>;
@@ -335,19 +165,25 @@
port@0 {
reg = <0>;
- usbc0_orien_sw: endpoint {
- remote-endpoint = <&usbdp_phy0_orientation_switch>;
+ usbc0_hs: endpoint {
+ remote-endpoint = <&usb_host0_xhci_drd_sw>;
};
};
port@1 {
reg = <1>;
- dp_altmode_mux: endpoint {
- remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
+ usbc0_ss: endpoint {
+ remote-endpoint = <&usbdp_phy0_typec_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ usbc0_sbu: endpoint {
+ remote-endpoint = <&usbdp_phy0_typec_sbu>;
};
};
};
};
};
};
-
diff --git a/arch/arm/dts/rk3588-rock-5b.dts b/arch/arm/dts/rk3588-rock-5b.dts
index 3e4aee8..741f631 100644
--- a/arch/arm/dts/rk3588-rock-5b.dts
+++ b/arch/arm/dts/rk3588-rock-5b.dts
@@ -3,6 +3,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
#include "rk3588.dtsi"
/ {
@@ -11,6 +12,8 @@
aliases {
mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ mmc2 = &sdio;
serial2 = &uart2;
};
@@ -18,17 +21,9 @@
stdout-path = "serial2:1500000n8";
};
- fan: pwm-fan {
- compatible = "pwm-fan";
- cooling-levels = <0 95 145 195 255>;
- fan-supply = <&vcc5v0_sys>;
- pwms = <&pwm1 0 50000 0>;
- #cooling-cells = <2>;
- };
-
- sound {
+ analog-sound {
compatible = "audio-graph-card";
- label = "Analog";
+ label = "rk3588-es8316";
widgets = "Microphone", "Mic Jack",
"Headphone", "Headphones";
@@ -43,6 +38,78 @@
pinctrl-0 = <&hp_detect>;
};
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_rgb_b>;
+
+ led_rgb_b {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ cooling-levels = <0 95 145 195 255>;
+ fan-supply = <&vcc5v0_sys>;
+ pwms = <&pwm1 0 50000 0>;
+ #cooling-cells = <2>;
+ };
+
+ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_0_vcc3v3_en>;
+ regulator-name = "vcc3v3_pcie2x1l0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie2x1l2";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vcc3v3_pcie30: vcc3v3-pcie30-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3_vcc3v3_en>;
+ regulator-name = "vcc3v3_pcie30";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_host";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
@@ -51,6 +118,24 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy1_ps {
+ status = "okay";
};
&cpu_b0 {
@@ -69,6 +154,22 @@
cpu-supply = <&vdd_cpu_big1_s0>;
};
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
@@ -133,6 +234,8 @@
reg = <0x11>;
clocks = <&cru I2S0_8CH_MCLKOUT>;
clock-names = "mclk";
+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+ assigned-clock-rates = <12288000>;
#sound-dai-cells = <0>;
port {
@@ -161,6 +264,34 @@
};
};
+&pcie2x1l0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_0_rst>;
+ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
+ status = "okay";
+};
+
+&pcie2x1l2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_2_rst>;
+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
+ status = "okay";
+};
+
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3_rst>;
+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
+ status = "okay";
+};
+
&pinctrl {
hym8563 {
hym8563_int: hym8563-int {
@@ -168,29 +299,469 @@
};
};
+ leds {
+ led_rgb_b: led-rgb-b {
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
sound {
hp_detect: hp-detect {
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ pcie2 {
+ pcie2_0_rst: pcie2-0-rst {
+ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie2_2_rst: pcie2-2-rst {
+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie3 {
+ pcie3_rst: pcie3-rst {
+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie3_vcc3v3_en: pcie3-vcc3v3-en {
+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&pwm1 {
status = "okay";
};
+&saradc {
+ vref-supply = <&avcc_1v8_s0>;
+ status = "okay";
+};
+
&sdhci {
bus-width = <8>;
no-sdio;
no-sd;
non-removable;
- max-frequency = <200000000>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
status = "okay";
};
+&sdmmc {
+ max-frequency = <200000000>;
+ no-sdio;
+ no-mmc;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&sdio {
+ max-frequency = <200000000>;
+ no-sd;
+ no-mmc;
+ non-removable;
+ bus-width = <4>;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ wakeup-source;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_pcie2x1l0>;
+ vqmmc-supply = <&vcc_1v8_s3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdiom0_pins>;
+ status = "okay";
+};
+
+&uart6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>;
+ status = "okay";
+};
+
+&spi2 {
+ status = "okay";
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+ num-cs = <1>;
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ spi-max-frequency = <1000000>;
+ reg = <0x0>;
+
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_gpu_s0";
+ regulator-enable-ramp-delay = <400>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_lit_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_log_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_vdenc_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_ddr_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vdd2_ddr_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_2v0_pldo_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_3v3_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vddq_ddr_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_s0: pldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "avcc_1v8_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avdd_1v2_s0: pldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "avdd_1v2_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: pldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_3v3_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vccio_sd_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "pldo6_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_ddr_pll_s0: nldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_ddr_pll_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ avdd_0v75_s0: nldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "avdd_0v75_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: nldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_0v85_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ /* connected to USB hub, which is powered by vcc5v0_sys */
+ phy-supply = <&vcc5v0_sys>;
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy3_host {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi
index 68b419f..31046fc 100644
--- a/arch/arm/dts/rk3588-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-u-boot.dtsi
@@ -3,36 +3,27 @@
* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
*/
-#include "rockchip-u-boot.dtsi"
#include "rk3588s-u-boot.dtsi"
/ {
- usbdrd3_1: usbdrd3_1 {
- compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
+ usb_host1_xhci: usb@fc400000 {
+ compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3";
+ reg = <0x0 0xfc400000 0x0 0x400000>;
+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
<&cru ACLK_USB3OTG1>;
- clock-names = "ref", "suspend", "bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
+ dr_mode = "host";
+ phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
+ power-domains = <&power RK3588_PD_USB>;
+ resets = <&cru SRST_A_USB3OTG1>;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
status = "disabled";
-
- usbdrd_dwc3_1: usb@fc400000 {
- compatible = "snps,dwc3";
- reg = <0x0 0xfc400000 0x0 0x400000>;
- interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
- power-domains = <&power RK3588_PD_USB>;
- resets = <&cru SRST_A_USB3OTG1>;
- reset-names = "usb3-otg";
- dr_mode = "host";
- phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
- phy-names = "usb2-phy", "usb3-phy";
- phy_type = "utmi_wide";
- snps,dis_enblslpm_quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis-del-phy-power-chg-quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- };
};
usbdpphy1_grf: syscon@fd5cc000 {
@@ -57,7 +48,6 @@
clock-names = "phyclk";
clock-output-names = "usb480m_phy1";
#clock-cells = <0>;
- rockchip,usbctrl-grf = <&usb_grf>;
status = "disabled";
u2phy1_otg: otg-port {
diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi
index 8be7555..5519c14 100644
--- a/arch/arm/dts/rk3588.dtsi
+++ b/arch/arm/dts/rk3588.dtsi
@@ -7,6 +7,16 @@
#include "rk3588-pinctrl.dtsi"
/ {
+ pcie30_phy_grf: syscon@fd5b8000 {
+ compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
+ reg = <0x0 0xfd5b8000 0x0 0x10000>;
+ };
+
+ pipe_phy1_grf: syscon@fd5c0000 {
+ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
+ reg = <0x0 0xfd5c0000 0x0 0x100>;
+ };
+
i2s8_8ch: i2s@fddc8000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddc8000 0x0 0x1000>;
@@ -75,6 +85,159 @@
status = "disabled";
};
+ pcie3x4: pcie@fe150000 {
+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0x0f>;
+ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+ <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+ <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+ device_type = "pci";
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
+ <0 0 0 2 &pcie3x4_intc 1>,
+ <0 0 0 3 &pcie3x4_intc 2>,
+ <0 0 0 4 &pcie3x4_intc 3>;
+ linux,pci-domain = <0>;
+ max-link-speed = <3>;
+ msi-map = <0x0000 &its1 0x0000 0x1000>;
+ num-lanes = <4>;
+ phys = <&pcie30phy>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3588_PD_PCIE>;
+ ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
+ <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
+ <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
+ reg = <0xa 0x40000000 0x0 0x00400000>,
+ <0x0 0xfe150000 0x0 0x00010000>,
+ <0x0 0xf0000000 0x0 0x00100000>;
+ reg-names = "dbi", "apb", "config";
+ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
+ reset-names = "pwr", "pipe";
+ status = "disabled";
+
+ pcie3x4_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
+ };
+ };
+
+ pcie3x2: pcie@fe160000 {
+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x10 0x1f>;
+ clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
+ <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
+ <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+ device_type = "pci";
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
+ <0 0 0 2 &pcie3x2_intc 1>,
+ <0 0 0 3 &pcie3x2_intc 2>,
+ <0 0 0 4 &pcie3x2_intc 3>;
+ linux,pci-domain = <1>;
+ max-link-speed = <3>;
+ msi-map = <0x1000 &its1 0x1000 0x1000>;
+ num-lanes = <2>;
+ phys = <&pcie30phy>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3588_PD_PCIE>;
+ ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
+ <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
+ <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
+ reg = <0xa 0x40400000 0x0 0x00400000>,
+ <0x0 0xfe160000 0x0 0x00010000>,
+ <0x0 0xf1000000 0x0 0x00100000>;
+ reg-names = "dbi", "apb", "config";
+ resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
+ reset-names = "pwr", "pipe";
+ status = "disabled";
+
+ pcie3x2_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
+ };
+ };
+
+ pcie2x1l0: pcie@fe170000 {
+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+ bus-range = <0x20 0x2f>;
+ clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
+ <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
+ <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+ device_type = "pci";
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
+ <0 0 0 2 &pcie2x1l0_intc 1>,
+ <0 0 0 3 &pcie2x1l0_intc 2>,
+ <0 0 0 4 &pcie2x1l0_intc 3>;
+ linux,pci-domain = <2>;
+ max-link-speed = <2>;
+ msi-map = <0x2000 &its0 0x2000 0x1000>;
+ num-lanes = <1>;
+ phys = <&combphy1_ps PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3588_PD_PCIE>;
+ ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
+ <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
+ <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
+ reg = <0xa 0x40800000 0x0 0x00400000>,
+ <0x0 0xfe170000 0x0 0x00010000>,
+ <0x0 0xf2000000 0x0 0x00100000>;
+ reg-names = "dbi", "apb", "config";
+ resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
+ reset-names = "pwr", "pipe";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ pcie2x1l0_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>;
+ };
+ };
+
gmac0: ethernet@fe1b0000 {
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe1b0000 0x0 0x10000>;
@@ -123,4 +286,56 @@
queue1 {};
};
};
+
+ sata1: sata@fe220000 {
+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
+ reg = <0 0xfe220000 0 0x1000>;
+ interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
+ <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
+ <&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
+ ports-implemented = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata-port@0 {
+ reg = <0>;
+ hba-port-cap = <HBA_PORT_FBSCP>;
+ phys = <&combphy1_ps PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ snps,rx-ts-max = <32>;
+ snps,tx-ts-max = <32>;
+ };
+ };
+
+ combphy1_ps: phy@fee10000 {
+ compatible = "rockchip,rk3588-naneng-combphy";
+ reg = <0x0 0xfee10000 0x0 0x100>;
+ clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
+ <&cru PCLK_PHP_ROOT>;
+ clock-names = "ref", "apb", "pipe";
+ assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
+ assigned-clock-rates = <100000000>;
+ #phy-cells = <1>;
+ resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
+ reset-names = "phy", "apb";
+ rockchip,pipe-grf = <&php_grf>;
+ rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
+ status = "disabled";
+ };
+
+ pcie30phy: phy@fee80000 {
+ compatible = "rockchip,rk3588-pcie3-phy";
+ reg = <0x0 0xfee80000 0x0 0x20000>;
+ #phy-cells = <0>;
+ clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
+ clock-names = "pclk";
+ resets = <&cru SRST_PCIE30_PHY>;
+ reset-names = "phy";
+ rockchip,pipe-grf = <&php_grf>;
+ rockchip,phy-grf = <&pcie30_phy_grf>;
+ status = "disabled";
+ };
};
diff --git a/arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi b/arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi
new file mode 100644
index 0000000..888d1b9
--- /dev/null
+++ b/arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc;
+ };
+};
+
+&fspim0_pins {
+ bootph-all;
+};
+
+&sfc {
+ bootph-pre-ram;
+ u-boot,spl-sfc-no-dma;
+
+ flash@0 {
+ bootph-pre-ram;
+ };
+};
diff --git a/arch/arm/dts/rk3588s-orangepi-5.dts b/arch/arm/dts/rk3588s-orangepi-5.dts
new file mode 100644
index 0000000..8f399c4
--- /dev/null
+++ b/arch/arm/dts/rk3588s-orangepi-5.dts
@@ -0,0 +1,662 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3588s.dtsi"
+
+/ {
+ model = "Xunlong Orange Pi 5";
+ compatible = "xunlong,orangepi-5", "rockchip,rk3588s";
+
+ aliases {
+ mmc0 = &sdmmc;
+ serial2 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-recovery {
+ label = "Recovery";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <1800>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 =<&leds_gpio>;
+
+ led-1 {
+ gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
+ label = "status_led";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ vbus_typec: vbus-typec-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&typec5v_pwren>;
+ regulator-name = "vbus_typec";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
+ compatible = "regulator-fixed";
+ enable-active-low;
+ gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
+ regulator-name = "vcc_3v3_sd_s0";
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vcc3v3_pcie20: vcc3v3-pcie20-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc3v3_pcie20";
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gmac1 {
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii-rxid";
+ pinctrl-0 = <&gmac1_miim
+ &gmac1_tx_bus2
+ &gmac1_rx_bus2
+ &gmac1_rgmii_clk
+ &gmac1_rgmii_bus>;
+ pinctrl-names = "default";
+ tx_delay = <0x42>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ vdd_npu_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_npu_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6m3_xfer>;
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+ wakeup-source;
+ };
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pcie2x1l2 {
+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie20>;
+ status = "okay";
+};
+
+&pinctrl {
+ gpio-func {
+ leds_gpio: leds-gpio {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb-typec {
+ usbc0_int: usbc0-int {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ typec5v_pwren: typec5v-pwren {
+ rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&saradc {
+ vref-supply = <&avcc_1v8_s0>;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <150000000>;
+ no-mmc;
+ no-sdio;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_sd_s0>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&sfc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspim0_pins>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-max-frequency = <100000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
+&spi2 {
+ status = "okay";
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ reg = <0x0>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ spi-max-frequency = <1000000>;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: dcdc-reg1 {
+ regulator-name = "vdd_gpu_s0";
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <400>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: dcdc-reg2 {
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-name = "vdd_log_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: dcdc-reg4 {
+ regulator-name = "vdd_vdenc_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-name = "vdd_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vcc_1v1_nldo_s3: vdd2_ddr_s3: dcdc-reg6 {
+ regulator-name = "vdd2_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1100000>;
+ regulator-min-microvolt = <1100000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-name = "vdd_2v0_pldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-name = "vcc_3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-name = "vddq_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-name = "vcc_1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_s0: pldo-reg1 {
+ regulator-name = "avcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg2 {
+ regulator-name = "vcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avdd_1v2_s0: pldo-reg3 {
+ regulator-name = "avdd_1v2_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: pldo-reg4 {
+ regulator-name = "vcc_3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-name = "vccio_sd_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-name = "pldo6_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-name = "vdd_0v75_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_ddr_pll_s0: nldo-reg2 {
+ regulator-name = "vdd_ddr_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ avdd_0v75_s0: nldo-reg3 {
+ regulator-name = "avdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: nldo-reg4 {
+ regulator-name = "vdd_0v85_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-name = "vdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy3_host {
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588s-pinctrl.dtsi b/arch/arm/dts/rk3588s-pinctrl.dtsi
index 4818167..63151d9 100644
--- a/arch/arm/dts/rk3588s-pinctrl.dtsi
+++ b/arch/arm/dts/rk3588s-pinctrl.dtsi
@@ -1350,6 +1350,41 @@
i2s2 {
/omit-if-no-ref/
+ i2s2m0_lrck: i2s2m0-lrck {
+ rockchip,pins =
+ /* i2s2m0_lrck */
+ <2 RK_PC0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_mclk: i2s2m0-mclk {
+ rockchip,pins =
+ /* i2s2m0_mclk */
+ <2 RK_PB6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_sclk: i2s2m0-sclk {
+ rockchip,pins =
+ /* i2s2m0_sclk */
+ <2 RK_PB7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_sdi: i2s2m0-sdi {
+ rockchip,pins =
+ /* i2s2m0_sdi */
+ <2 RK_PC3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_sdo: i2s2m0-sdo {
+ rockchip,pins =
+ /* i2s2m0_sdo */
+ <4 RK_PC3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
i2s2m1_lrck: i2s2m1-lrck {
rockchip,pins =
/* i2s2m1_lrck */
@@ -3308,6 +3343,15 @@
uart9 {
/omit-if-no-ref/
+ uart9m0_xfer: uart9m0-xfer {
+ rockchip,pins =
+ /* uart9_rx_m0 */
+ <2 RK_PC4 10 &pcfg_pull_up>,
+ /* uart9_tx_m0 */
+ <2 RK_PC2 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
uart9m1_xfer: uart9m1-xfer {
rockchip,pins =
/* uart9_rx_m1 */
diff --git a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
index 9bb0e4f..584476f 100644
--- a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
@@ -4,31 +4,15 @@
*/
#include "rk3588s-u-boot.dtsi"
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/usb/pd.h>
/ {
- aliases {
- mmc1 = &sdmmc;
- };
-
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
};
};
-&sdmmc {
- bus-width = <4>;
- status = "okay";
-};
-
&sdhci {
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>;
};
-
diff --git a/arch/arm/dts/rk3588s-rock-5a.dts b/arch/arm/dts/rk3588s-rock-5a.dts
index 9018255..8347adc 100644
--- a/arch/arm/dts/rk3588s-rock-5a.dts
+++ b/arch/arm/dts/rk3588s-rock-5a.dts
@@ -3,6 +3,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3588s.dtsi"
@@ -12,12 +13,252 @@
aliases {
mmc0 = &sdhci;
+ mmc1 = &sdmmc;
serial2 = &uart2;
};
+ analog-sound {
+ compatible = "audio-graph-card";
+ label = "rk3588-es8316";
+
+ widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+
+ routing = "MIC2", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+
+ dais = <&i2s0_8ch_p0>;
+ };
+
chosen {
stdout-path = "serial2:1500000n8";
};
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&io_led>;
+
+ io-led {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ cooling-levels = <0 95 145 195 255>;
+ fan-supply = <&vcc_5v0>;
+ pwms = <&pwm3 0 50000 0>;
+ #cooling-cells = <2>;
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_host";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc_5v0: vcc-5v0-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ enable-active-high;
+ gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc_5v0_en>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ vdd_npu_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_npu_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ eeprom: eeprom@50 {
+ compatible = "belling,bl24c16a", "atmel,24c16";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5m2_xfer>;
+};
+
+&i2c7 {
+ status = "okay";
+
+ es8316: audio-codec@11 {
+ compatible = "everest,es8316";
+ reg = <0x11>;
+ clocks = <&cru I2S0_8CH_MCLKOUT>;
+ clock-names = "mclk";
+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+ assigned-clock-rates = <12288000>;
+ #sound-dai-cells = <0>;
+
+ port {
+ es8316_p0_0: endpoint {
+ remote-endpoint = <&i2s0_8ch_p0_0>;
+ };
+ };
+ };
+};
+
+&i2s0_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_lrck
+ &i2s0_mclk
+ &i2s0_sclk
+ &i2s0_sdi0
+ &i2s0_sdo0>;
+ status = "okay";
+
+ i2s0_8ch_p0: port {
+ i2s0_8ch_p0_0: endpoint {
+ dai-format = "i2s";
+ mclk-fs = <256>;
+ remote-endpoint = <&es8316_p0_0>;
+ };
+ };
};
&gmac1 {
@@ -49,11 +290,62 @@
};
&pinctrl {
+ leds {
+ io_led: io-led {
+ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ power {
+ vcc_5v0_en: vcc-5v0-en {
+ rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
rtl8211f {
rtl8211f_rst: rtl8211f-rst {
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ usb {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wifibt {
+ wl_reset: wl-reset {
+ rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ wl_dis: wl-dis {
+ rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_output_high>;
+ };
+
+ wl_wake_host: wl-wake-host {
+ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ bt_dis: bt-dis {
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_output_high>;
+ };
+
+ bt_wake_host: bt-wake-host {
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3m1_pins>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&avcc_1v8_s0>;
+ status = "okay";
};
&sdhci {
@@ -61,13 +353,384 @@
no-sdio;
no-sd;
non-removable;
- max-frequency = <200000000>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
status = "okay";
};
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ max-frequency = <150000000>;
+ no-sdio;
+ no-mmc;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s0>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&spi2 {
+ status = "okay";
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ reg = <0x0>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ spi-max-frequency = <1000000>;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+ regulator-name = "vdd_gpu_s0";
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <400>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-name = "vdd_log_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+ regulator-name = "vdd_vdenc_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-name = "vdd_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-name = "vdd2_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-name = "vdd_2v0_pldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-name = "vcc_3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-name = "vddq_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-name = "vcc_1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_s0: pldo-reg1 {
+ regulator-name = "avcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg2 {
+ regulator-name = "vcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avdd_1v2_s0: pldo-reg3 {
+ regulator-name = "avdd_1v2_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: pldo-reg4 {
+ regulator-name = "vcc_3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-name = "vccio_sd_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-name = "pldo6_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-name = "vdd_0v75_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_ddr_pll_s0: nldo-reg2 {
+ regulator-name = "vdd_ddr_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ avdd_0v75_s0: nldo-reg3 {
+ regulator-name = "avdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: nldo-reg4 {
+ regulator-name = "vdd_0v85_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-name = "vdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ status = "okay";
+ phy-supply = <&vcc5v0_host>;
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy3_host {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
+
+&usb_host0_ehci {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wl_reset &wl_dis &wl_wake_host &bt_dis &bt_wake_host>;
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index 245bc8b..c0fd16c 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -4,7 +4,6 @@
*/
#include "rockchip-u-boot.dtsi"
-#include <dt-bindings/phy/phy.h>
/ {
aliases {
@@ -22,74 +21,46 @@
status = "okay";
};
- usbdrd3_0: usbdrd3_0 {
- compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
+ usb_host0_xhci: usb@fc000000 {
+ compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3";
+ reg = <0x0 0xfc000000 0x0 0x400000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
<&cru ACLK_USB3OTG0>;
- clock-names = "ref", "suspend", "bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- status = "disabled";
-
- usbdrd_dwc3_0: usb@fc000000 {
- compatible = "snps,dwc3";
- reg = <0x0 0xfc000000 0x0 0x400000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
- power-domains = <&power RK3588_PD_USB>;
- resets = <&cru SRST_A_USB3OTG0>;
- reset-names = "usb3-otg";
- dr_mode = "otg";
- phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
- phy-names = "usb2-phy", "usb3-phy";
- phy_type = "utmi_wide";
- snps,dis_enblslpm_quirk;
- snps,dis-u1-entry-quirk;
- snps,dis-u2-entry-quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis-del-phy-power-chg-quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- quirk-skip-phy-init;
- };
- };
-
- usb_host0_ehci: usb@fc800000 {
- compatible = "generic-ehci";
- reg = <0x0 0xfc800000 0x0 0x40000>;
- interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
- clock-names = "usbhost", "arbiter";
+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
+ dr_mode = "otg";
+ phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
power-domains = <&power RK3588_PD_USB>;
+ resets = <&cru SRST_A_USB3OTG0>;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
status = "disabled";
};
- usb_host0_ohci: usb@fc840000 {
- compatible = "generic-ohci";
- reg = <0x0 0xfc840000 0x0 0x40000>;
- interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
- clock-names = "usbhost", "arbiter";
- power-domains = <&power RK3588_PD_USB>;
- status = "disabled";
- };
-
- usb_host1_ehci: usb@fc880000 {
- compatible = "generic-ehci";
- reg = <0x0 0xfc880000 0x0 0x40000>;
- interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
- clock-names = "usbhost", "arbiter";
- power-domains = <&power RK3588_PD_USB>;
- status = "disabled";
- };
-
- usb_host1_ohci: usb@fc8c0000 {
- compatible = "generic-ohci";
- reg = <0x0 0xfc8c0000 0x0 0x40000>;
- interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
- clock-names = "usbhost", "arbiter";
- power-domains = <&power RK3588_PD_USB>;
+ usb_host2_xhci: usb@fcd00000 {
+ compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3";
+ reg = <0x0 0xfcd00000 0x0 0x400000>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
+ <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
+ <&cru CLK_PIPEPHY2_PIPE_U3_G>;
+ clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
+ dr_mode = "host";
+ phys = <&combphy2_psu PHY_TYPE_USB3>;
+ phy-names = "usb3-phy";
+ phy_type = "utmi_wide";
+ resets = <&cru SRST_A_USB3OTG2>;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ snps,dis_rxdet_inp3_quirk;
status = "disabled";
};
@@ -99,9 +70,9 @@
reg = <0x0 0xfd58a000 0x0 0x2000>;
};
- pipe_phy0_grf: syscon@fd5bc000 {
- compatible = "rockchip,pipe-phy-grf", "syscon";
- reg = <0x0 0xfd5bc000 0x0 0x100>;
+ usbdpphy0_grf: syscon@fd5c8000 {
+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
+ reg = <0x0 0xfd5c8000 0x0 0x4000>;
};
usb2phy0_grf: syscon@fd5d0000 {
@@ -121,7 +92,6 @@
clock-names = "phyclk";
clock-output-names = "usb480m_phy0";
#clock-cells = <0>;
- rockchip,usbctrl-grf = <&usb_grf>;
status = "disabled";
u2phy0_otg: otg-port {
@@ -131,29 +101,6 @@
};
};
- usb2phy2_grf: syscon@fd5d8000 {
- compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
- "simple-mfd";
- reg = <0x0 0xfd5d8000 0x0 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- u2phy2: usb2-phy@8000 {
- compatible = "rockchip,rk3588-usb2phy";
- reg = <0x8000 0x10>;
- interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- status = "disabled";
-
- u2phy2_host: host-port {
- #phy-cells = <0>;
- status = "disabled";
- };
- };
- };
-
vo0_grf: syscon@fd5a6000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a6000 0x0 0x2000>;
@@ -165,98 +112,11 @@
reg = <0x0 0xfd5ac000 0x0 0x4000>;
};
- usb2phy3_grf: syscon@fd5dc000 {
- compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
- "simple-mfd";
- reg = <0x0 0xfd5dc000 0x0 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- u2phy3: usb2-phy@c000 {
- compatible = "rockchip,rk3588-usb2phy";
- reg = <0xc000 0x10>;
- interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- status = "disabled";
-
- u2phy3_host: host-port {
- #phy-cells = <0>;
- status = "disabled";
- };
- };
- };
-
usbdpphy0_grf: syscon@fd5c8000 {
compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
reg = <0x0 0xfd5c8000 0x0 0x4000>;
};
- pcie2x1l2: pcie@fe190000 {
- compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x40 0x4f>;
- clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
- <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
- <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
- clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk",
- "aux", "pipe";
- device_type = "pci";
- interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
- <0 0 0 2 &pcie2x1l2_intc 1>,
- <0 0 0 3 &pcie2x1l2_intc 2>,
- <0 0 0 4 &pcie2x1l2_intc 3>;
- linux,pci-domain = <4>;
- num-ib-windows = <8>;
- num-ob-windows = <8>;
- num-viewport = <4>;
- max-link-speed = <2>;
- msi-map = <0x4000 &gic 0x4000 0x1000>;
- num-lanes = <1>;
- phys = <&combphy0_ps PHY_TYPE_PCIE>;
- phy-names = "pcie-phy";
- power-domains = <&power RK3588_PD_PCIE>;
- ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
- <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
- <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
- reg = <0xa 0x41000000 0x0 0x00400000>,
- <0x0 0xfe190000 0x0 0x00010000>,
- <0x0 0xf4000000 0x0 0x00100000>;
- reg-names = "dbi", "apb", "config";
- resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
- reset-names = "pcie", "periph";
- rockchip,pipe-grf = <&php_grf>;
- status = "disabled";
-
- pcie2x1l2_intc: legacy-interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
- };
- };
-
- sfc: spi@fe2b0000 {
- compatible = "rockchip,sfc";
- reg = <0x0 0xfe2b0000 0x0 0x4000>;
- interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
- clock-names = "clk_sfc", "hclk_sfc";
- status = "disabled";
- };
-
rng: rng@fe378000 {
compatible = "rockchip,trngv1";
reg = <0x0 0xfe378000 0x0 0x200>;
@@ -293,22 +153,6 @@
status = "disabled";
};
};
-
- combphy0_ps: phy@fee00000 {
- compatible = "rockchip,rk3588-naneng-combphy";
- reg = <0x0 0xfee00000 0x0 0x100>;
- #phy-cells = <1>;
- clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
- <&cru PCLK_PHP_ROOT>;
- clock-names = "refclk", "apbclk", "phpclk";
- assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
- assigned-clock-rates = <100000000>;
- resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>;
- reset-names = "combphy-apb", "combphy";
- rockchip,pipe-grf = <&php_grf>;
- rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
- status = "disabled";
- };
};
&emmc_bus8 {
diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi
index 7dbac9a..61a9a11 100644
--- a/arch/arm/dts/rk3588s.dtsi
+++ b/arch/arm/dts/rk3588s.dtsi
@@ -8,6 +8,8 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/rk3588-power.h>
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/ata/ahci.h>
/ {
compatible = "rockchip,rk3588";
@@ -397,6 +399,50 @@
};
};
+ usb_host0_ehci: usb@fc800000 {
+ compatible = "rockchip,rk3588-ehci", "generic-ehci";
+ reg = <0x0 0xfc800000 0x0 0x40000>;
+ interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
+ phys = <&u2phy2_host>;
+ phy-names = "usb";
+ power-domains = <&power RK3588_PD_USB>;
+ status = "disabled";
+ };
+
+ usb_host0_ohci: usb@fc840000 {
+ compatible = "rockchip,rk3588-ohci", "generic-ohci";
+ reg = <0x0 0xfc840000 0x0 0x40000>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
+ phys = <&u2phy2_host>;
+ phy-names = "usb";
+ power-domains = <&power RK3588_PD_USB>;
+ status = "disabled";
+ };
+
+ usb_host1_ehci: usb@fc880000 {
+ compatible = "rockchip,rk3588-ehci", "generic-ehci";
+ reg = <0x0 0xfc880000 0x0 0x40000>;
+ interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
+ phys = <&u2phy3_host>;
+ phy-names = "usb";
+ power-domains = <&power RK3588_PD_USB>;
+ status = "disabled";
+ };
+
+ usb_host1_ohci: usb@fc8c0000 {
+ compatible = "rockchip,rk3588-ohci", "generic-ohci";
+ reg = <0x0 0xfc8c0000 0x0 0x40000>;
+ interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
+ phys = <&u2phy3_host>;
+ phy-names = "usb";
+ power-domains = <&power RK3588_PD_USB>;
+ status = "disabled";
+ };
+
sys_grf: syscon@fd58c000 {
compatible = "rockchip,rk3588-sys-grf", "syscon";
reg = <0x0 0xfd58c000 0x0 0x1000>;
@@ -407,6 +453,66 @@
reg = <0x0 0xfd5b0000 0x0 0x1000>;
};
+ pipe_phy0_grf: syscon@fd5bc000 {
+ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
+ reg = <0x0 0xfd5bc000 0x0 0x100>;
+ };
+
+ pipe_phy2_grf: syscon@fd5c4000 {
+ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
+ reg = <0x0 0xfd5c4000 0x0 0x100>;
+ };
+
+ usb2phy2_grf: syscon@fd5d8000 {
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xfd5d8000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy2: usb2-phy@8000 {
+ compatible = "rockchip,rk3588-usb2phy";
+ reg = <0x8000 0x10>;
+ interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
+ reset-names = "phy", "apb";
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy2";
+ #clock-cells = <0>;
+ status = "disabled";
+
+ u2phy2_host: host-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
+ usb2phy3_grf: syscon@fd5dc000 {
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xfd5dc000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy3: usb2-phy@c000 {
+ compatible = "rockchip,rk3588-usb2phy";
+ reg = <0xc000 0x10>;
+ interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
+ reset-names = "phy", "apb";
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy3";
+ #clock-cells = <0>;
+ status = "disabled";
+
+ u2phy3_host: host-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
ioc: syscon@fd5f0000 {
compatible = "rockchip,rk3588-ioc", "syscon";
reg = <0x0 0xfd5f0000 0x0 0x10000>;
@@ -830,6 +936,57 @@
};
};
+ i2s4_8ch: i2s@fddc0000 {
+ compatible = "rockchip,rk3588-i2s-tdm";
+ reg = <0x0 0xfddc0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
+ assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ dmas = <&dmac2 0>;
+ dma-names = "tx";
+ power-domains = <&power RK3588_PD_VO0>;
+ resets = <&cru SRST_M_I2S4_8CH_TX>;
+ reset-names = "tx-m";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ i2s5_8ch: i2s@fddf0000 {
+ compatible = "rockchip,rk3588-i2s-tdm";
+ reg = <0x0 0xfddf0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
+ assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ dmas = <&dmac2 2>;
+ dma-names = "tx";
+ power-domains = <&power RK3588_PD_VO1>;
+ resets = <&cru SRST_M_I2S5_8CH_TX>;
+ reset-names = "tx-m";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ i2s9_8ch: i2s@fddfc000 {
+ compatible = "rockchip,rk3588-i2s-tdm";
+ reg = <0x0 0xfddfc000 0x0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
+ assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ dmas = <&dmac2 23>;
+ dma-names = "rx";
+ power-domains = <&power RK3588_PD_VO1>;
+ resets = <&cru SRST_M_I2S9_8CH_RX>;
+ reset-names = "rx-m";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
qos_gpu_m0: qos@fdf35000 {
compatible = "rockchip,rk3588-qos", "syscon";
reg = <0x0 0xfdf35000 0x0 0x20>;
@@ -1070,6 +1227,108 @@
reg = <0x0 0xfdf82200 0x0 0x20>;
};
+ pcie2x1l1: pcie@fe180000 {
+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+ bus-range = <0x30 0x3f>;
+ clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
+ <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
+ <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+ device_type = "pci";
+ interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
+ <0 0 0 2 &pcie2x1l1_intc 1>,
+ <0 0 0 3 &pcie2x1l1_intc 2>,
+ <0 0 0 4 &pcie2x1l1_intc 3>;
+ linux,pci-domain = <3>;
+ max-link-speed = <2>;
+ msi-map = <0x3000 &its0 0x3000 0x1000>;
+ num-lanes = <1>;
+ phys = <&combphy2_psu PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3588_PD_PCIE>;
+ ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
+ <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
+ <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
+ reg = <0xa 0x40c00000 0x0 0x00400000>,
+ <0x0 0xfe180000 0x0 0x00010000>,
+ <0x0 0xf3000000 0x0 0x00100000>;
+ reg-names = "dbi", "apb", "config";
+ resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
+ reset-names = "pwr", "pipe";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ pcie2x1l1_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>;
+ };
+ };
+
+ pcie2x1l2: pcie@fe190000 {
+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+ bus-range = <0x40 0x4f>;
+ clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
+ <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
+ <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+ device_type = "pci";
+ interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
+ <0 0 0 2 &pcie2x1l2_intc 1>,
+ <0 0 0 3 &pcie2x1l2_intc 2>,
+ <0 0 0 4 &pcie2x1l2_intc 3>;
+ linux,pci-domain = <4>;
+ max-link-speed = <2>;
+ msi-map = <0x4000 &its0 0x4000 0x1000>;
+ num-lanes = <1>;
+ phys = <&combphy0_ps PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3588_PD_PCIE>;
+ ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
+ <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
+ <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
+ reg = <0xa 0x41000000 0x0 0x00400000>,
+ <0x0 0xfe190000 0x0 0x00010000>,
+ <0x0 0xf4000000 0x0 0x00100000>;
+ reg-names = "dbi", "apb", "config";
+ resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
+ reset-names = "pwr", "pipe";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ pcie2x1l2_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
+ };
+ };
+
gmac1: ethernet@fe1c0000 {
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe1c0000 0x0 0x10000>;
@@ -1119,6 +1378,63 @@
};
};
+ sata0: sata@fe210000 {
+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
+ reg = <0 0xfe210000 0 0x1000>;
+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
+ <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
+ <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
+ ports-implemented = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata-port@0 {
+ reg = <0>;
+ hba-port-cap = <HBA_PORT_FBSCP>;
+ phys = <&combphy0_ps PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ snps,rx-ts-max = <32>;
+ snps,tx-ts-max = <32>;
+ };
+ };
+
+ sata2: sata@fe230000 {
+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
+ reg = <0 0xfe230000 0 0x1000>;
+ interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
+ <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
+ <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
+ ports-implemented = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata-port@0 {
+ reg = <0>;
+ hba-port-cap = <HBA_PORT_FBSCP>;
+ phys = <&combphy2_psu PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ snps,rx-ts-max = <32>;
+ snps,tx-ts-max = <32>;
+ };
+ };
+
+ sfc: spi@fe2b0000 {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0xfe2b0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
sdmmc: mmc@fe2c0000 {
compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe2c0000 0x0 0x4000>;
@@ -1134,6 +1450,21 @@
status = "disabled";
};
+ sdio: mmc@fe2d0000 {
+ compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x00 0xfe2d0000 0x00 0x4000>;
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdiom1_pins>;
+ power-domains = <&power RK3588_PD_SDIO>;
+ status = "disabled";
+ };
+
sdhci: mmc@fe2e0000 {
compatible = "rockchip,rk3588-dwcmshc";
reg = <0x0 0xfe2e0000 0x0 0x10000>;
@@ -1145,6 +1476,9 @@
<&cru TMCLK_EMMC>;
clock-names = "core", "bus", "axi", "block", "timer";
max-frequency = <200000000>;
+ pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
+ <&emmc_cmd>, <&emmc_data_strobe>;
+ pinctrl-names = "default";
resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
<&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
<&cru SRST_T_EMMC>;
@@ -1742,6 +2076,18 @@
status = "disabled";
};
+ saradc: adc@fec10000 {
+ compatible = "rockchip,rk3588-saradc";
+ reg = <0x0 0xfec10000 0x0 0x10000>;
+ interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
+ #io-channel-cells = <1>;
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_P_SARADC>;
+ reset-names = "saradc-apb";
+ status = "disabled";
+ };
+
i2c6: i2c@fec80000 {
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xfec80000 0x0 0x1000>;
@@ -1862,6 +2208,38 @@
#dma-cells = <1>;
};
+ combphy0_ps: phy@fee00000 {
+ compatible = "rockchip,rk3588-naneng-combphy";
+ reg = <0x0 0xfee00000 0x0 0x100>;
+ clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
+ <&cru PCLK_PHP_ROOT>;
+ clock-names = "ref", "apb", "pipe";
+ assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
+ assigned-clock-rates = <100000000>;
+ #phy-cells = <1>;
+ resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
+ reset-names = "phy", "apb";
+ rockchip,pipe-grf = <&php_grf>;
+ rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
+ status = "disabled";
+ };
+
+ combphy2_psu: phy@fee20000 {
+ compatible = "rockchip,rk3588-naneng-combphy";
+ reg = <0x0 0xfee20000 0x0 0x100>;
+ clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
+ <&cru PCLK_PHP_ROOT>;
+ clock-names = "ref", "apb", "pipe";
+ assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
+ assigned-clock-rates = <100000000>;
+ #phy-cells = <1>;
+ resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
+ reset-names = "phy", "apb";
+ rockchip,pipe-grf = <&php_grf>;
+ rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
+ status = "disabled";
+ };
+
system_sram2: sram@ff001000 {
compatible = "mmio-sram";
reg = <0x0 0xff001000 0x0 0xef000>;
@@ -1937,6 +2315,19 @@
#interrupt-cells = <2>;
};
};
+
+ av1d: video-codec@fdc70000 {
+ compatible = "rockchip,rk3588-av1-vpu";
+ reg = <0x0 0xfdc70000 0x0 0x800>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vdpu";
+ assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
+ assigned-clock-rates = <400000000>, <400000000>;
+ clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3588_PD_AV1>;
+ resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
+ };
};
#include "rk3588s-pinctrl.dtsi"
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi
index be2658e..c8c928c 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -56,10 +56,21 @@
#else
arch = "arm";
#endif
+#if defined(CONFIG_SPL_GZIP)
+ compression = "gzip";
+#elif defined(CONFIG_SPL_LZMA)
+ compression = "lzma";
+#else
compression = "none";
+#endif
load = <CONFIG_TEXT_BASE>;
entry = <CONFIG_TEXT_BASE>;
u-boot-nodtb {
+#if defined(CONFIG_SPL_GZIP)
+ compress = "gzip";
+#elif defined(CONFIG_SPL_LZMA)
+ compress = "lzma";
+#endif
};
#ifdef CONFIG_SPL_FIT_SIGNATURE
hash {
diff --git a/arch/arm/dts/rv1126-u-boot.dtsi b/arch/arm/dts/rv1126-u-boot.dtsi
index 5e34827..4485980 100644
--- a/arch/arm/dts/rv1126-u-boot.dtsi
+++ b/arch/arm/dts/rv1126-u-boot.dtsi
@@ -15,6 +15,18 @@
compatible = "rockchip,rv1126-dmc";
bootph-all;
};
+
+ otp: otp@ff5c0000 {
+ compatible = "rockchip,rv1126-otp";
+ reg = <0xff5c0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "okay";
+
+ cpu_id: id@7 {
+ reg = <0x07 0x10>;
+ };
+ };
};
&gpio0 {
@@ -26,15 +38,15 @@
};
&grf {
- bootph-pre-ram;
+ bootph-all;
};
&pmu {
- bootph-pre-ram;
+ bootph-all;
};
&pmugrf {
- bootph-pre-ram;
+ bootph-all;
};
&xin24m {
diff --git a/arch/arm/dts/rz-smarc-common.dtsi b/arch/arm/dts/rz-smarc-common.dtsi
new file mode 100644
index 0000000..3962d47
--- /dev/null
+++ b/arch/arm/dts/rz-smarc-common.dtsi
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/{G2L,G2LC,V2L} SMARC EVK common parts
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/*
+ * SSI-WM8978
+ *
+ * This command is required when Playback/Capture
+ *
+ * amixer cset name='Left Input Mixer L2 Switch' on
+ * amixer cset name='Right Input Mixer R2 Switch' on
+ * amixer cset name='Headphone Playback Volume' 100
+ * amixer cset name='PCM Volume' 100%
+ * amixer cset name='Input PGA Volume' 25
+ *
+ */
+
+/ {
+ aliases {
+ serial0 = &scif0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ audio_mclock: audio_mclock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <11289600>;
+ };
+
+ snd_rzg2l: sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&cpu_dai>;
+ simple-audio-card,frame-master = <&cpu_dai>;
+ simple-audio-card,mclk-fs = <256>;
+
+ simple-audio-card,widgets = "Microphone", "Microphone Jack";
+ simple-audio-card,routing =
+ "L2", "Mic Bias",
+ "R2", "Mic Bias",
+ "Mic Bias", "Microphone Jack";
+
+ cpu_dai: simple-audio-card,cpu {
+ };
+
+ codec_dai: simple-audio-card,codec {
+ clocks = <&audio_mclock>;
+ sound-dai = <&wm8978>;
+ };
+ };
+
+ usb0_vbus_otg: regulator-usb0-vbus-otg {
+ compatible = "regulator-fixed";
+
+ regulator-name = "USB0_VBUS_OTG";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vccq_sdhi1: regulator-vccq-sdhi1 {
+ compatible = "regulator-gpio";
+ regulator-name = "SDHI1 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios-states = <1>;
+ states = <3300000 1>, <1800000 0>;
+ };
+};
+
+&audio_clk1{
+ clock-frequency = <11289600>;
+};
+
+&audio_clk2{
+ clock-frequency = <12288000>;
+};
+
+&canfd {
+ pinctrl-0 = <&can0_pins &can1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ channel0 {
+ status = "okay";
+ };
+
+ channel1 {
+ status = "okay";
+ };
+};
+
+&ehci0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&hsusb {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&ohci0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&phyrst {
+ status = "okay";
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sdhi1 {
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-1 = <&sdhi1_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <&vccq_sdhi1>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&spi1 {
+ pinctrl-0 = <&spi1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&usb2_phy0 {
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+
+ vbus-supply = <&usb0_vbus_otg>;
+ status = "okay";
+};
+
+&usb2_phy1 {
+ pinctrl-0 = <&usb1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
diff --git a/arch/arm/dts/rzg2l-smarc-pinfunction.dtsi b/arch/arm/dts/rzg2l-smarc-pinfunction.dtsi
new file mode 100644
index 0000000..9085d8c
--- /dev/null
+++ b/arch/arm/dts/rzg2l-smarc-pinfunction.dtsi
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/{G2L,V2L} SMARC pincontrol parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+&pinctrl {
+ pinctrl-0 = <&sound_clk_pins>;
+ pinctrl-names = "default";
+
+ can0_pins: can0 {
+ pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */
+ <RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */
+ };
+
+ /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
+ can0-stb-hog {
+ gpio-hog;
+ gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "can0_stb";
+ };
+
+ can1_pins: can1 {
+ pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */
+ <RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */
+ };
+
+ /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
+ can1-stb-hog {
+ gpio-hog;
+ gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "can1_stb";
+ };
+
+ i2c0_pins: i2c0 {
+ pins = "RIIC0_SDA", "RIIC0_SCL";
+ input-enable;
+ };
+
+ i2c1_pins: i2c1 {
+ pins = "RIIC1_SDA", "RIIC1_SCL";
+ input-enable;
+ };
+
+ i2c3_pins: i2c3 {
+ pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
+ <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
+ };
+
+ scif0_pins: scif0 {
+ pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
+ <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
+ };
+
+ scif2_pins: scif2 {
+ pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */
+ <RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */
+ <RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */
+ <RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */
+ };
+
+ sd1-pwr-en-hog {
+ gpio-hog;
+ gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "sd1_pwr_en";
+ };
+
+ sdhi1_pins: sd1 {
+ sd1_data {
+ pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
+ power-source = <3300>;
+ };
+
+ sd1_ctrl {
+ pins = "SD1_CLK", "SD1_CMD";
+ power-source = <3300>;
+ };
+
+ sd1_mux {
+ pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
+ };
+ };
+
+ sdhi1_pins_uhs: sd1_uhs {
+ sd1_data_uhs {
+ pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
+ power-source = <1800>;
+ };
+
+ sd1_ctrl_uhs {
+ pins = "SD1_CLK", "SD1_CMD";
+ power-source = <1800>;
+ };
+
+ sd1_mux_uhs {
+ pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
+ };
+ };
+
+ sound_clk_pins: sound_clk {
+ pins = "AUDIO_CLK1", "AUDIO_CLK2";
+ input-enable;
+ };
+
+ spi1_pins: spi1 {
+ pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
+ <RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
+ <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
+ <RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
+ };
+
+ ssi0_pins: ssi0 {
+ pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
+ <RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
+ <RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */
+ <RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
+ };
+
+ usb0_pins: usb0 {
+ pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
+ <RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
+ <RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */
+ };
+
+ usb1_pins: usb1 {
+ pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
+ <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */
+ };
+};
+
diff --git a/arch/arm/dts/rzg2l-smarc-som.dtsi b/arch/arm/dts/rzg2l-smarc-som.dtsi
new file mode 100644
index 0000000..fbbb4f0
--- /dev/null
+++ b/arch/arm/dts/rzg2l-smarc-som.dtsi
@@ -0,0 +1,353 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/{G2L,V2L} SMARC SOM common parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
+#define EMMC 1
+
+/*
+ * To enable uSD card on CN3,
+ * SW1[2] should be at position 3/ON.
+ * Disable eMMC by setting "#define EMMC 0" above.
+ */
+#define SDHI (!EMMC)
+
+/ {
+ aliases {
+ ethernet0 = ð0;
+ ethernet1 = ð1;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
+ };
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_1p1v: regulator-vdd-core {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.1V";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vccq_sdhi0: regulator-vccq-sdhi0 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ states = <3300000 1>, <1800000 0>;
+ regulator-boot-on;
+ gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ };
+};
+
+&adc {
+ pinctrl-0 = <&adc_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /delete-node/ channel@6;
+ /delete-node/ channel@7;
+};
+
+ð0 {
+ pinctrl-0 = <ð0_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ phy0: ethernet-phy@7 {
+ compatible = "ethernet-phy-id0022.1640",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ interrupt-parent = <&irqc>;
+ interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
+ rxc-skew-psec = <2400>;
+ txc-skew-psec = <2400>;
+ rxdv-skew-psec = <0>;
+ txdv-skew-psec = <0>;
+ rxd0-skew-psec = <0>;
+ rxd1-skew-psec = <0>;
+ rxd2-skew-psec = <0>;
+ rxd3-skew-psec = <0>;
+ txd0-skew-psec = <0>;
+ txd1-skew-psec = <0>;
+ txd2-skew-psec = <0>;
+ txd3-skew-psec = <0>;
+ };
+};
+
+ð1 {
+ pinctrl-0 = <ð1_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ phy1: ethernet-phy@7 {
+ compatible = "ethernet-phy-id0022.1640",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ interrupt-parent = <&irqc>;
+ interrupts = <RZG2L_IRQ3 IRQ_TYPE_LEVEL_LOW>;
+ rxc-skew-psec = <2400>;
+ txc-skew-psec = <2400>;
+ rxdv-skew-psec = <0>;
+ txdv-skew-psec = <0>;
+ rxd0-skew-psec = <0>;
+ rxd1-skew-psec = <0>;
+ rxd2-skew-psec = <0>;
+ rxd3-skew-psec = <0>;
+ txd0-skew-psec = <0>;
+ txd1-skew-psec = <0>;
+ txd2-skew-psec = <0>;
+ txd3-skew-psec = <0>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <24000000>;
+};
+
+&gpu {
+ mali-supply = <®_1p1v>;
+};
+
+&ostm1 {
+ status = "okay";
+};
+
+&ostm2 {
+ status = "okay";
+};
+
+&pinctrl {
+ adc_pins: adc {
+ pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */
+ };
+
+ eth0_pins: eth0 {
+ pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
+ <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
+ <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
+ <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
+ <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
+ <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
+ <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
+ <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
+ <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
+ <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
+ <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
+ <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
+ <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
+ <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
+ <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
+ <RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */
+ };
+
+ eth1_pins: eth1 {
+ pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
+ <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
+ <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
+ <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
+ <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
+ <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
+ <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
+ <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
+ <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
+ <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
+ <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
+ <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
+ <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
+ <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
+ <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */
+ <RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */
+ };
+
+ gpio-sd0-pwr-en-hog {
+ gpio-hog;
+ gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "gpio_sd0_pwr_en";
+ };
+
+ qspi0_pins: qspi0 {
+ qspi0-data {
+ pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
+ power-source = <1800>;
+ };
+
+ qspi0-ctrl {
+ pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
+ power-source = <1800>;
+ };
+ };
+
+ /*
+ * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
+ * The below switch logic can be used to select the device between
+ * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
+ * SW1[2] should be at position 2/OFF to enable 64 GB eMMC
+ * SW1[2] should be at position 3/ON to enable uSD card CN3
+ */
+ sd0-dev-sel-hog {
+ gpio-hog;
+ gpios = <RZG2L_GPIO(41, 1) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "sd0_dev_sel";
+ };
+
+ sdhi0_emmc_pins: sd0emmc {
+ sd0_emmc_data {
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
+ "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
+ power-source = <1800>;
+ };
+
+ sd0_emmc_ctrl {
+ pins = "SD0_CLK", "SD0_CMD";
+ power-source = <1800>;
+ };
+
+ sd0_emmc_rst {
+ pins = "SD0_RST#";
+ power-source = <1800>;
+ };
+ };
+
+ sdhi0_pins: sd0 {
+ sd0_data {
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
+ power-source = <3300>;
+ };
+
+ sd0_ctrl {
+ pins = "SD0_CLK", "SD0_CMD";
+ power-source = <3300>;
+ };
+
+ sd0_mux {
+ pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
+ };
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ sd0_data_uhs {
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
+ power-source = <1800>;
+ };
+
+ sd0_ctrl_uhs {
+ pins = "SD0_CLK", "SD0_CMD";
+ power-source = <1800>;
+ };
+
+ sd0_mux_uhs {
+ pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
+ };
+ };
+};
+
+&sbc {
+ pinctrl-0 = <&qspi0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ flash@0 {
+ compatible = "micron,mt25qu512a", "jedec,spi-nor";
+ reg = <0>;
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ boot@0 {
+ reg = <0x00000000 0x2000000>;
+ read-only;
+ };
+ user@2000000 {
+ reg = <0x2000000 0x2000000>;
+ };
+ };
+ };
+};
+
+#if SDHI
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_pins>;
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <&vccq_sdhi0>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+#endif
+
+#if EMMC
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_emmc_pins>;
+ pinctrl-1 = <&sdhi0_emmc_pins>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ fixed-emmc-driver-type = <1>;
+ status = "okay";
+};
+#endif
+
+&wdt0 {
+ status = "okay";
+ timeout-sec = <60>;
+};
+
+&wdt1 {
+ status = "okay";
+ timeout-sec = <60>;
+};
diff --git a/arch/arm/dts/rzg2l-smarc.dtsi b/arch/arm/dts/rzg2l-smarc.dtsi
new file mode 100644
index 0000000..2a158a9
--- /dev/null
+++ b/arch/arm/dts/rzg2l-smarc.dtsi
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */
+#define PMOD1_SER0 1
+
+/ {
+ aliases {
+ serial1 = &scif2;
+ i2c3 = &i2c3;
+ };
+
+ osc1: cec-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12000000>;
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "d";
+
+ port {
+ hdmi_con_out: endpoint {
+ remote-endpoint = <&adv7535_out>;
+ };
+ };
+ };
+};
+
+&cpu_dai {
+ sound-dai = <&ssi0>;
+};
+
+&dsi {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&adv7535_in>;
+ };
+ };
+ };
+};
+
+&i2c1 {
+ adv7535: hdmi@3d {
+ compatible = "adi,adv7535";
+ reg = <0x3d>;
+
+ interrupt-parent = <&pinctrl>;
+ interrupts = <RZG2L_GPIO(2, 1) IRQ_TYPE_EDGE_FALLING>;
+ clocks = <&osc1>;
+ clock-names = "cec";
+ avdd-supply = <®_1p8v>;
+ dvdd-supply = <®_1p8v>;
+ pvdd-supply = <®_1p8v>;
+ a2vdd-supply = <®_1p8v>;
+ v3p3-supply = <®_3p3v>;
+ v1p2-supply = <®_1p8v>;
+
+ adi,dsi-lanes = <4>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7535_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7535_out: endpoint {
+ remote-endpoint = <&hdmi_con_out>;
+ };
+ };
+ };
+ };
+};
+
+&i2c3 {
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-names = "default";
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ wm8978: codec@1a {
+ compatible = "wlf,wm8978";
+ #sound-dai-cells = <0>;
+ reg = <0x1a>;
+ };
+};
+
+/*
+ * To enable SCIF2 (SER0) on PMOD1 (CN7)
+ * SW1 should be at position 2->3 so that SER0_CTS# line is activated
+ * SW2 should be at position 2->3 so that SER0_TX line is activated
+ * SW3 should be at position 2->3 so that SER0_RX line is activated
+ * SW4 should be at position 2->3 so that SER0_RTS# line is activated
+ */
+#if PMOD1_SER0
+&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+
+ uart-has-rtscts;
+ status = "okay";
+};
+#endif
+
+&ssi0 {
+ pinctrl-0 = <&ssi0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&vccq_sdhi1 {
+ gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
+};
diff --git a/arch/arm/dts/salvator-common.dtsi b/arch/arm/dts/salvator-common.dtsi
index 23fdd11..4a3d503 100644
--- a/arch/arm/dts/salvator-common.dtsi
+++ b/arch/arm/dts/salvator-common.dtsi
@@ -33,9 +33,20 @@
/ {
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c_dvfs;
serial0 = &scif2;
serial1 = &hscif1;
ethernet0 = &avb;
+ mmc0 = &sdhi2;
+ mmc1 = &sdhi0;
+ mmc2 = &sdhi3;
};
chosen {
@@ -94,6 +105,7 @@
port {
hdmi0_con: endpoint {
+ remote-endpoint = <&rcar_dw_hdmi0_out>;
};
};
};
@@ -166,7 +178,7 @@
};
};
- reg_1p8v: regulator0 {
+ reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
@@ -175,7 +187,7 @@
regulator-always-on;
};
- reg_3p3v: regulator1 {
+ reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
@@ -184,7 +196,7 @@
regulator-always-on;
};
- reg_12v: regulator2 {
+ reg_12v: regulator-12v {
compatible = "regulator-fixed";
regulator-name = "fixed-12V";
regulator-min-microvolt = <12000000>;
@@ -198,7 +210,12 @@
label = "rcar-sound";
- dais = <&rsnd_port0>;
+ dais = <&rsnd_port0 /* ak4613 */
+ &rsnd_port1 /* HDMI0 */
+#ifdef SOC_HAS_HDMI1
+ &rsnd_port2 /* HDMI1 */
+#endif
+ >;
};
vbus0_usb2: regulator-vbus0-usb2 {
@@ -316,6 +333,10 @@
};
};
+&a57_0 {
+ cpu-supply = <&dvfs>;
+};
+
&audio_clk_a {
clock-frequency = <22579200>;
};
@@ -324,7 +345,7 @@
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
- phy-mode = "rgmii-txid";
+ tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {
@@ -343,7 +364,6 @@
ports {
port@0 {
- reg = <0>;
csi20_in: endpoint {
clock-lanes = <0>;
data-lanes = <1>;
@@ -358,8 +378,6 @@
ports {
port@0 {
- reg = <0>;
-
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
@@ -376,7 +394,7 @@
ports {
port@0 {
- endpoint {
+ du_out_rgb: endpoint {
remote-endpoint = <&adv7123_in>;
};
};
@@ -396,6 +414,50 @@
clock-frequency = <32768>;
};
+&hdmi0 {
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+ rcar_dw_hdmi0_out: endpoint {
+ remote-endpoint = <&hdmi0_con>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+ dw_hdmi0_snd_in: endpoint {
+ remote-endpoint = <&rsnd_endpoint1>;
+ };
+ };
+ };
+};
+
+#ifdef SOC_HAS_HDMI1
+&hdmi1 {
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+ rcar_dw_hdmi1_out: endpoint {
+ remote-endpoint = <&hdmi1_con>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+ dw_hdmi1_snd_in: endpoint {
+ remote-endpoint = <&rsnd_endpoint2>;
+ };
+ };
+ };
+};
+
+&hdmi1_con {
+ remote-endpoint = <&rcar_dw_hdmi1_out>;
+};
+#endif /* SOC_HAS_HDMI1 */
+
&hscif1 {
pinctrl-0 = <&hscif1_pins>;
pinctrl-names = "default";
@@ -469,47 +531,49 @@
reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
"infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
- #address-cells = <1>;
- #size-cells = <0>;
-
interrupt-parent = <&gpio6>;
interrupt-names = "intrq1", "intrq2";
interrupts = <30 IRQ_TYPE_LEVEL_LOW>,
<31 IRQ_TYPE_LEVEL_LOW>;
- port@7 {
- reg = <7>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
- adv7482_ain7: endpoint {
- remote-endpoint = <&cvbs_con>;
+ port@7 {
+ reg = <7>;
+
+ adv7482_ain7: endpoint {
+ remote-endpoint = <&cvbs_con>;
+ };
};
- };
- port@8 {
- reg = <8>;
+ port@8 {
+ reg = <8>;
- adv7482_hdmi: endpoint {
- remote-endpoint = <&hdmi_in_con>;
+ adv7482_hdmi: endpoint {
+ remote-endpoint = <&hdmi_in_con>;
+ };
};
- };
- port@a {
- reg = <10>;
+ port@a {
+ reg = <10>;
- adv7482_txa: endpoint {
- clock-lanes = <0>;
- data-lanes = <1 2 3 4>;
- remote-endpoint = <&csi40_in>;
+ adv7482_txa: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&csi40_in>;
+ };
};
- };
- port@b {
- reg = <11>;
+ port@b {
+ reg = <11>;
- adv7482_txb: endpoint {
- clock-lanes = <0>;
- data-lanes = <1>;
- remote-endpoint = <&csi20_in>;
+ adv7482_txb: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1>;
+ remote-endpoint = <&csi20_in>;
+ };
};
};
};
@@ -732,12 +796,9 @@
};
&rcar_sound {
- pinctrl-0 = <&sound_pins &sound_clk_pins>;
+ pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
- /* Single DAI */
- #sound-dai-cells = <0>;
-
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <12288000 11289600>;
@@ -775,8 +836,85 @@
bitclock-master = <&rsnd_endpoint0>;
frame-master = <&rsnd_endpoint0>;
- playback = <&ssi0 &src0 &dvc0>;
- capture = <&ssi1 &src1 &dvc1>;
+ playback = <&ssi0>, <&src0>, <&dvc0>;
+ capture = <&ssi1>, <&src1>, <&dvc1>;
+ };
+ };
+
+ rsnd_port1: port@1 {
+ reg = <1>;
+ rsnd_endpoint1: endpoint {
+ remote-endpoint = <&dw_hdmi0_snd_in>;
+
+ dai-format = "i2s";
+ bitclock-master = <&rsnd_endpoint1>;
+ frame-master = <&rsnd_endpoint1>;
+
+ playback = <&ssi2>;
+ };
+ };
+
+#ifdef SOC_HAS_HDMI1
+ rsnd_port2: port@2 {
+ reg = <2>;
+ rsnd_endpoint2: endpoint {
+ remote-endpoint = <&dw_hdmi1_snd_in>;
+
+ dai-format = "i2s";
+ bitclock-master = <&rsnd_endpoint2>;
+ frame-master = <&rsnd_endpoint2>;
+
+ playback = <&ssi3>;
+ };
+ };
+#endif /* SOC_HAS_HDMI1 */
+ };
+};
+
+&rpc {
+ /* Left disabled. To be enabled by firmware when unlocked. */
+
+ flash@0 {
+ compatible = "cypress,hyperflash", "cfi-flash";
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootparam@0 {
+ reg = <0x00000000 0x040000>;
+ read-only;
+ };
+ bl2@40000 {
+ reg = <0x00040000 0x140000>;
+ read-only;
+ };
+ cert_header_sa6@180000 {
+ reg = <0x00180000 0x040000>;
+ read-only;
+ };
+ bl31@1c0000 {
+ reg = <0x001c0000 0x040000>;
+ read-only;
+ };
+ tee@200000 {
+ reg = <0x00200000 0x440000>;
+ read-only;
+ };
+ uboot@640000 {
+ reg = <0x00640000 0x100000>;
+ read-only;
+ };
+ dtb@740000 {
+ reg = <0x00740000 0x080000>;
+ };
+ kernel@7c0000 {
+ reg = <0x007c0000 0x1400000>;
+ };
+ user@1bc0000 {
+ reg = <0x01bc0000 0x2440000>;
};
};
};
@@ -787,6 +925,12 @@
status = "okay";
};
+#ifdef SOC_HAS_SATA
+&sata {
+ status = "okay";
+};
+#endif /* SOC_HAS_SATA */
+
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
@@ -833,8 +977,11 @@
bus-width = <8>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
+ no-sd;
+ no-sdio;
non-removable;
fixed-emmc-driver-type = <1>;
+ full-pwr-cycle-in-suspend;
status = "okay";
};
@@ -931,3 +1078,27 @@
status = "okay";
};
+
+#ifdef SOC_HAS_USB2_CH2
+&ehci2 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&pfc {
+ usb2_pins: usb2 {
+ groups = "usb2";
+ function = "usb2";
+ };
+};
+
+&usb2_phy2 {
+ pinctrl-0 = <&usb2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+#endif /* SOC_HAS_USB2_CH2 */
diff --git a/arch/arm/dts/salvator-xs.dtsi b/arch/arm/dts/salvator-xs.dtsi
index 717d427..08b9256 100644
--- a/arch/arm/dts/salvator-xs.dtsi
+++ b/arch/arm/dts/salvator-xs.dtsi
@@ -27,3 +27,59 @@
clock-names = "xin";
};
};
+
+#ifdef SOC_HAS_SATA
+&pca9654 {
+ pcie-sata-switch-hog {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ output-low; /* enable SATA by default */
+ line-name = "PCIE/SATA switch";
+ };
+};
+
+/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */
+#endif /* SOC_HAS_SATA */
+
+#ifdef SOC_HAS_USB2_CH3
+&ehci3 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&hsusb3 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&ohci3 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&pfc {
+ /*
+ * - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins
+ * (when SW31 is the default setting on Salvator-XS).
+ * - If SW31 is the default setting, you cannot use USB2.0 ch3 on
+ * r8a77951 with Salvator-XS.
+ * Hence the SW31 setting must be changed like 2) below.
+ * 1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF:
+ * - Connect GP6_3[01] to ADV7842.
+ * 2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON:
+ * - Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power).
+ * - Connect GP6_{04,21} to ADV7842.
+ */
+ usb2_ch3_pins: usb2_ch3 {
+ groups = "usb2_ch3";
+ function = "usb2_ch3";
+ };
+};
+
+&usb2_phy3 {
+ pinctrl-0 = <&usb2_ch3_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+#endif /* SOC_HAS_USB2_CH3 */
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
index 2b93d08..3b684fc 100644
--- a/arch/arm/dts/sam9x60.dtsi
+++ b/arch/arm/dts/sam9x60.dtsi
@@ -27,6 +27,18 @@
spi0 = &qspi;
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ARM9260_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,arm926ej-s";
+ clocks = <&pmc PMC_TYPE_CORE 19>, <&pmc PMC_TYPE_CORE 11>, <&main_xtal>;
+ clock-names = "cpu", "master", "xtal";
+ };
+ };
+
clocks {
slow_rc_osc: slow_rc_osc {
compatible = "fixed-clock";
@@ -51,18 +63,6 @@
};
};
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ARM9260_0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,arm926ej-s";
- clocks = <&pmc PMC_TYPE_CORE 19>, <&pmc PMC_TYPE_CORE 11>, <&main_xtal>;
- clock-names = "cpu", "master", "xtal";
- };
- };
-
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -149,13 +149,20 @@
compatible = "microchip,sam9x60-qspi";
reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
reg-names = "qspi_base", "qspi_mmap";
- clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 18>; /* ID_QSPI */
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 18>; /* ID_QSPI */
clock-names = "pclk", "qspick";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
+ pit64b0: timer@f0028000 {
+ compatible = "microchip,sam9x60-pit64b";
+ reg = <0xf0028000 0xec>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
+ clock-names = "pclk", "gclk";
+ };
+
flx0: flexcom@f801c600 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf801c000 0x200>;
@@ -181,6 +188,17 @@
reg = <0xf8050000 0x100>;
};
+ pmecc: ecc-engine@ffffe000 {
+ compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
+ reg = <0xffffe000 0x300>,
+ <0xffffe600 0x100>;
+ };
+
+ smc: smc@ffffea00 {
+ compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
+ reg = <0xffffea00 0x100>;
+ };
+
dbgu: serial@fffff200 {
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
@@ -190,7 +208,7 @@
clock-names = "usart";
};
- pinctrl {
+ pinctrl: pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "microchip,sam9x60-pinctrl", "simple-bus";
@@ -205,7 +223,7 @@
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
- AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
@@ -256,17 +274,6 @@
};
};
- pmecc: ecc-engine@ffffe000 {
- compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
- reg = <0xffffe000 0x300>,
- <0xffffe600 0x100>;
- };
-
- smc: smc@ffffea00 {
- compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
- reg = <0xffffea00 0x100>;
- };
-
pioA: gpio@fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
@@ -320,13 +327,6 @@
clocks = <&pmc PMC_TYPE_CORE 11>; /* ID_MCK. */
};
- pit64b0: timer@f0028000 {
- compatible = "microchip,sam9x60-pit64b";
- reg = <0xf0028000 0xec>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
- clock-names = "pclk", "gclk";
- };
-
clk32: sckc@fffffe50 {
compatible = "microchip,sam9x60-sckc";
reg = <0xfffffe50 0x4>;
diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts
index 45e2f4c..74016f5 100644
--- a/arch/arm/dts/sam9x60ek.dts
+++ b/arch/arm/dts/sam9x60ek.dts
@@ -62,7 +62,7 @@
status = "okay";
i2c@600 {
- compatible = "atmel,sama5d2-i2c";
+ compatible = "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx0>;
diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi
index dd6468e..819564f 100644
--- a/arch/arm/dts/sama5d2.dtsi
+++ b/arch/arm/dts/sama5d2.dtsi
@@ -781,6 +781,26 @@
status = "disabled";
};
+ flx4: flexcom@fc018000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xfc018000 0x200>;
+ clocks = <&flx4_clk>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xfc018000 0x800>;
+ status = "disabled";
+
+ i2c6: i2c@600 {
+ compatible = "atmel,sama5d2-i2c";
+ reg = <0x600 0x200>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&flx4_clk>;
+ clock-names = "i2c6_clk";
+ status = "disabled";
+ };
+ };
+
aic: interrupt-controller@fc020000 {
#interrupt-cells = <3>;
compatible = "atmel,sama5d2-aic";
diff --git a/arch/arm/dts/stm32f4-pinctrl.dtsi b/arch/arm/dts/stm32f4-pinctrl.dtsi
index 46815c9..0adc41b 100644
--- a/arch/arm/dts/stm32f4-pinctrl.dtsi
+++ b/arch/arm/dts/stm32f4-pinctrl.dtsi
@@ -412,6 +412,36 @@
slew-rate = <2>;
};
};
+
+ can1_pins_a: can1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
+ bias-pull-up;
+ };
+ };
+
+ can2_pins_a: can2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
+ bias-pull-up;
+ };
+ };
+
+ can2_pins_b: can2-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
+ bias-pull-up;
+ };
+ };
};
};
};
diff --git a/arch/arm/dts/stm32f429.dtsi b/arch/arm/dts/stm32f429.dtsi
index e5b13ac..8133ea1 100644
--- a/arch/arm/dts/stm32f429.dtsi
+++ b/arch/arm/dts/stm32f429.dtsi
@@ -321,6 +321,36 @@
status = "disabled";
};
+ can1: can@40006400 {
+ compatible = "st,stm32f4-bxcan";
+ reg = <0x40006400 0x200>;
+ interrupts = <19>, <20>, <21>, <22>;
+ interrupt-names = "tx", "rx0", "rx1", "sce";
+ resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
+ st,can-primary;
+ st,gcan = <&gcan>;
+ status = "disabled";
+ };
+
+ gcan: gcan@40006600 {
+ compatible = "st,stm32f4-gcan", "syscon";
+ reg = <0x40006600 0x200>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
+ };
+
+ can2: can@40006800 {
+ compatible = "st,stm32f4-bxcan";
+ reg = <0x40006800 0x200>;
+ interrupts = <63>, <64>, <65>, <66>;
+ interrupt-names = "tx", "rx0", "rx1", "sce";
+ resets = <&rcc STM32F4_APB1_RESET(CAN2)>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>;
+ st,can-secondary;
+ st,gcan = <&gcan>;
+ status = "disabled";
+ };
+
dac: dac@40007400 {
compatible = "st,stm32f4-dac-core";
reg = <0x40007400 0x400>;
diff --git a/arch/arm/dts/stm32f7-pinctrl.dtsi b/arch/arm/dts/stm32f7-pinctrl.dtsi
index 8f37aef..d3706ee 100644
--- a/arch/arm/dts/stm32f7-pinctrl.dtsi
+++ b/arch/arm/dts/stm32f7-pinctrl.dtsi
@@ -172,6 +172,16 @@
};
};
+ i2c3_pins_a: i2c3-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 8, AF4)>, /* I2C3_SDA */
+ <STM32_PINMUX('H', 7, AF4)>; /* I2C3_SCL */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
@@ -284,6 +294,122 @@
slew-rate = <2>;
};
};
+
+ can1_pins_a: can1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
+ bias-pull-up;
+ };
+ };
+
+ can1_pins_b: can1-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
+ bias-pull-up;
+ };
+ };
+
+ can1_pins_c: can1-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 1, AF9)>; /* CAN1_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
+ bias-pull-up;
+
+ };
+ };
+
+ can1_pins_d: can1-3 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */
+ bias-pull-up;
+
+ };
+ };
+
+ can2_pins_a: can2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 6, AF9)>; /* CAN2_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
+ bias-pull-up;
+ };
+ };
+
+ can2_pins_b: can2-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
+ bias-pull-up;
+ };
+ };
+
+ can3_pins_a: can3-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 15, AF11)>; /* CAN3_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 8, AF11)>; /* CAN3_RX */
+ bias-pull-up;
+ };
+ };
+
+ can3_pins_b: can3-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 4, AF11)>; /* CAN3_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 3, AF11)>; /* CAN3_RX */
+ bias-pull-up;
+ };
+ };
+
+ ltdc_pins_a: ltdc-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 4, AF14)>, /* LCD_B0 */
+ <STM32_PINMUX('G',12, AF9)>, /* LCD_B4 */
+ <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
+ <STM32_PINMUX('I',10, AF14)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I',14, AF14)>, /* LCD_CLK */
+ <STM32_PINMUX('I',15, AF14)>, /* LCD_R0 */
+ <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
+ <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
+ <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
+ <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
+ <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
+ <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
+ <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
+ <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
+ <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
+ <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
+ <STM32_PINMUX('J',10, AF14)>, /* LCD_G3 */
+ <STM32_PINMUX('J',11, AF14)>, /* LCD_G4 */
+ <STM32_PINMUX('J',13, AF14)>, /* LCD_B1 */
+ <STM32_PINMUX('J',14, AF14)>, /* LCD_B2 */
+ <STM32_PINMUX('J',15, AF14)>, /* LCD_B3 */
+ <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
+ <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
+ <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
+ <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
+ <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
+ <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
+ <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
+ slew-rate = <2>;
+ };
+ };
};
};
};
diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
index 522cffb..1b42d6c 100644
--- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
@@ -23,12 +23,6 @@
spi0 = &qspi;
};
- backlight: backlight {
- compatible = "gpio-backlight";
- gpios = <&gpiok 3 0>;
- status = "okay";
- };
-
button1 {
compatible = "st,button1";
button-gpio = <&gpioi 11 0>;
@@ -38,44 +32,11 @@
compatible = "st,led1";
led-gpio = <&gpioi 1 0>;
};
+};
- panel-rgb@0 {
- compatible = "simple-panel";
- backlight = <&backlight>;
- enable-gpios = <&gpioi 12 0>;
- status = "okay";
-
- display-timings {
- timing@0 {
- clock-frequency = <9000000>;
- hactive = <480>;
- vactive = <272>;
- hfront-porch = <2>;
- hback-porch = <2>;
- hsync-len = <41>;
- vfront-porch = <2>;
- vback-porch = <2>;
- vsync-len = <10>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <1>;
- };
- };
- };
-
- soc {
- ltdc: display-controller@40016800 {
- compatible = "st,stm32-ltdc";
- reg = <0x40016800 0x200>;
- resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
- pinctrl-0 = <<dc_pins>;
-
- status = "okay";
- bootph-all;
- };
- };
+<dc {
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
+ bootph-all;
};
&fmc {
@@ -102,6 +63,28 @@
};
};
+&panel_rgb {
+ compatible = "simple-panel";
+
+ display-timings {
+ timing@0 {
+ clock-frequency = <9000000>;
+ hactive = <480>;
+ vactive = <272>;
+ hfront-porch = <2>;
+ hback-porch = <2>;
+ hsync-len = <41>;
+ vfront-porch = <2>;
+ vback-porch = <2>;
+ vsync-len = <10>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+ };
+};
+
&pinctrl {
ethernet_mii: mii@0 {
pins {
@@ -166,40 +149,6 @@
};
};
- ltdc_pins: ltdc@0 {
- pins {
- pinmux = <STM32_PINMUX('E', 4, AF14)>, /* B0 */
- <STM32_PINMUX('G',12, AF9)>, /* B4 */
- <STM32_PINMUX('I', 9, AF14)>, /* VSYNC */
- <STM32_PINMUX('I',10, AF14)>, /* HSYNC */
- <STM32_PINMUX('I',14, AF14)>, /* CLK */
- <STM32_PINMUX('I',15, AF14)>, /* R0 */
- <STM32_PINMUX('J', 0, AF14)>, /* R1 */
- <STM32_PINMUX('J', 1, AF14)>, /* R2 */
- <STM32_PINMUX('J', 2, AF14)>, /* R3 */
- <STM32_PINMUX('J', 3, AF14)>, /* R4 */
- <STM32_PINMUX('J', 4, AF14)>, /* R5 */
- <STM32_PINMUX('J', 5, AF14)>, /* R6 */
- <STM32_PINMUX('J', 6, AF14)>, /* R7 */
- <STM32_PINMUX('J', 7, AF14)>, /* G0 */
- <STM32_PINMUX('J', 8, AF14)>, /* G1 */
- <STM32_PINMUX('J', 9, AF14)>, /* G2 */
- <STM32_PINMUX('J',10, AF14)>, /* G3 */
- <STM32_PINMUX('J',11, AF14)>, /* G4 */
- <STM32_PINMUX('J',13, AF14)>, /* B1 */
- <STM32_PINMUX('J',14, AF14)>, /* B2 */
- <STM32_PINMUX('J',15, AF14)>, /* B3 */
- <STM32_PINMUX('K', 0, AF14)>, /* G5 */
- <STM32_PINMUX('K', 1, AF14)>, /* G6 */
- <STM32_PINMUX('K', 2, AF14)>, /* G7 */
- <STM32_PINMUX('K', 4, AF14)>, /* B5 */
- <STM32_PINMUX('K', 5, AF14)>, /* B6 */
- <STM32_PINMUX('K', 6, AF14)>, /* B7 */
- <STM32_PINMUX('K', 7, AF14)>; /* DE */
- slew-rate = <2>;
- };
- };
-
qspi_pins: qspi@0 {
pins {
pinmux = <STM32_PINMUX('B', 2, AF9)>, /* CLK */
diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts
index 1ed58f2..4312751 100644
--- a/arch/arm/dts/stm32f746-disco.dts
+++ b/arch/arm/dts/stm32f746-disco.dts
@@ -7,8 +7,9 @@
/dts-v1/;
#include "stm32f746.dtsi"
#include "stm32f746-pinctrl.dtsi"
-#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "STMicroelectronics STM32F746-DISCO board";
@@ -24,6 +25,19 @@
reg = <0xC0000000 0x800000>;
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ no-map;
+ size = <0x80000>;
+ linux,dma-default;
+ };
+ };
+
aliases {
serial0 = &usart1;
};
@@ -43,12 +57,31 @@
regulator-always-on;
};
- mmc_vcard: mmc_vcard {
+ vcc_3v3: vcc-3v3 {
compatible = "regulator-fixed";
- regulator-name = "mmc_vcard";
+ regulator-name = "vcc_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ backlight: backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpiok 3 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ panel_rgb: panel-rgb {
+ compatible = "rocktech,rk043fn48h";
+ power-supply = <&vcc_3v3>;
+ backlight = <&backlight>;
+ enable-gpios = <&gpioi 12 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ port {
+ panel_in_rgb: endpoint {
+ remote-endpoint = <<dc_out_rgb>;
+ };
+ };
+ };
};
&clk_hse {
@@ -63,9 +96,37 @@
status = "okay";
};
+&i2c3 {
+ pinctrl-0 = <&i2c3_pins_a>;
+ pinctrl-names = "default";
+ clock-frequency = <400000>;
+ status = "okay";
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5306";
+ reg = <0x38>;
+ interrupt-parent = <&gpioi>;
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+ touchscreen-size-x = <480>;
+ touchscreen-size-y = <272>;
+ };
+};
+
+<dc {
+ pinctrl-0 = <<dc_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ port {
+ ltdc_out_rgb: endpoint {
+ remote-endpoint = <&panel_in_rgb>;
+ };
+ };
+};
+
&sdio1 {
status = "okay";
- vmmc-supply = <&mmc_vcard>;
+ vmmc-supply = <&vcc_3v3>;
cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "opendrain";
pinctrl-0 = <&sdio_pins_a>;
diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index c97b3d0..79dad31 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -221,6 +221,23 @@
status = "disabled";
};
+ can3: can@40003400 {
+ compatible = "st,stm32f4-bxcan";
+ reg = <0x40003400 0x200>;
+ interrupts = <104>, <105>, <106>, <107>;
+ interrupt-names = "tx", "rx0", "rx1", "sce";
+ resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
+ st,gcan = <&gcan3>;
+ status = "disabled";
+ };
+
+ gcan3: gcan@40003600 {
+ compatible = "st,stm32f4-gcan", "syscon";
+ reg = <0x40003600 0x200>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
+ };
+
usart2: serial@40004400 {
compatible = "st,stm32f7-uart";
reg = <0x40004400 0x400>;
@@ -301,6 +318,36 @@
status = "disabled";
};
+ can1: can@40006400 {
+ compatible = "st,stm32f4-bxcan";
+ reg = <0x40006400 0x200>;
+ interrupts = <19>, <20>, <21>, <22>;
+ interrupt-names = "tx", "rx0", "rx1", "sce";
+ resets = <&rcc STM32F7_APB1_RESET(CAN1)>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
+ st,can-primary;
+ st,gcan = <&gcan1>;
+ status = "disabled";
+ };
+
+ gcan1: gcan@40006600 {
+ compatible = "st,stm32f4-gcan", "syscon";
+ reg = <0x40006600 0x200>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
+ };
+
+ can2: can@40006800 {
+ compatible = "st,stm32f4-bxcan";
+ reg = <0x40006800 0x200>;
+ interrupts = <63>, <64>, <65>, <66>;
+ interrupt-names = "tx", "rx0", "rx1", "sce";
+ resets = <&rcc STM32F7_APB1_RESET(CAN2)>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
+ st,can-secondary;
+ st,gcan = <&gcan1>;
+ status = "disabled";
+ };
+
cec: cec@40006c00 {
compatible = "st,stm32-cec";
reg = <0x40006C00 0x400>;
@@ -471,6 +518,16 @@
};
};
+ ltdc: display-controller@40016800 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x40016800 0x200>;
+ interrupts = <88>, <89>;
+ resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
+ clocks = <&rcc 1 CLK_LCD>;
+ clock-names = "lcd";
+ status = "disabled";
+ };
+
pwrcfg: power-config@40007000 {
compatible = "st,stm32-power-config", "syscon";
reg = <0x40007000 0x400>;
@@ -479,7 +536,7 @@
crc: crc@40023000 {
compatible = "st,stm32f7-crc";
reg = <0x40023000 0x400>;
- clocks = <&rcc 0 12>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>;
status = "disabled";
};
diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi
index d23bbc3..215ad92 100644
--- a/arch/arm/dts/stm32mp131.dtsi
+++ b/arch/arm/dts/stm32mp131.dtsi
@@ -33,6 +33,8 @@
optee {
method = "smc";
compatible = "linaro,optee-tz";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
scmi: scmi {
@@ -50,6 +52,28 @@
reg = <0x16>;
#reset-cells = <1>;
};
+
+ scmi_voltd: protocol@17 {
+ reg = <0x17>;
+
+ scmi_regu: regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_reg11: regulator@0 {
+ reg = <VOLTD_SCMI_REG11>;
+ regulator-name = "reg11";
+ };
+ scmi_reg18: regulator@1 {
+ reg = <VOLTD_SCMI_REG18>;
+ regulator-name = "reg18";
+ };
+ scmi_usb33: regulator@2 {
+ reg = <VOLTD_SCMI_USB33>;
+ regulator-name = "usb33";
+ };
+ };
+ };
};
};
@@ -76,28 +100,6 @@
always-on;
};
- /* PWR 1v1, 1v8 and 3v3 regulators defined as fixed, waiting for SCMI */
- reg11: reg11 {
- compatible = "regulator-fixed";
- regulator-name = "reg11";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- };
-
- reg18: reg18 {
- compatible = "regulator-fixed";
- regulator-name = "reg18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- usb33: usb33 {
- compatible = "regulator-fixed";
- regulator-name = "usb33";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -799,7 +801,7 @@
g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
dr_mode = "otg";
otg-rev = <0x200>;
- usb33d-supply = <&usb33>;
+ usb33d-supply = <&scmi_usb33>;
status = "disabled";
};
@@ -1208,6 +1210,14 @@
};
};
+ rng: rng@54004000 {
+ compatible = "st,stm32mp13-rng";
+ reg = <0x54004000 0x400>;
+ clocks = <&rcc RNG1_K>;
+ resets = <&rcc RNG1_R>;
+ status = "disabled";
+ };
+
mdma: dma-controller@58000000 {
compatible = "st,stm32h7-mdma";
reg = <0x58000000 0x1000>;
@@ -1329,8 +1339,8 @@
reg = <0x5a006000 0x1000>;
clocks = <&rcc USBPHY_K>;
resets = <&rcc USBPHY_R>;
- vdda1v1-supply = <®11>;
- vdda1v8-supply = <®18>;
+ vdda1v1-supply = <&scmi_reg11>;
+ vdda1v8-supply = <&scmi_reg18>;
status = "disabled";
usbphyc_port0: usb-phy@0 {
diff --git a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi
index 48605ff..ba0c024 100644
--- a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi
@@ -38,3 +38,7 @@
bootph-all;
};
};
+
+&usbotg_hs {
+ u-boot,force-b-session-valid;
+};
diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts
index f0900ca..eea740d 100644
--- a/arch/arm/dts/stm32mp135f-dk.dts
+++ b/arch/arm/dts/stm32mp135f-dk.dts
@@ -9,6 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
#include "stm32mp135.dtsi"
#include "stm32mp13xf.dtsi"
#include "stm32mp13-pinctrl.dtsi"
@@ -65,45 +66,13 @@
default-state = "off";
};
};
-
- v3v3_sw: v3v3-sw {
- compatible = "regulator-fixed";
- regulator-name = "v3v3_sw";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vdd_adc: vdd-adc {
- compatible = "regulator-fixed";
- regulator-name = "vdd_adc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vdd_sd: vdd-sd {
- compatible = "regulator-fixed";
- regulator-name = "vdd_sd";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- regulator-always-on;
- };
-
- vdd_usb: vdd-usb {
- compatible = "regulator-fixed";
- regulator-name = "vdd_usb";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
};
&adc_1 {
pinctrl-names = "default";
pinctrl-0 = <&adc1_usb_cc_pins_a>;
- vdda-supply = <&vdd_adc>;
- vref-supply = <&vdd_adc>;
+ vdda-supply = <&scmi_vdd_adc>;
+ vref-supply = <&scmi_vdd_adc>;
status = "okay";
adc1: adc@0 {
status = "okay";
@@ -195,6 +164,29 @@
status = "okay";
};
+&scmi_regu {
+ scmi_vdd_adc: regulator@10 {
+ reg = <VOLTD_SCMI_STPMIC1_LDO1>;
+ regulator-name = "vdd_adc";
+ };
+ scmi_vdd_usb: regulator@13 {
+ reg = <VOLTD_SCMI_STPMIC1_LDO4>;
+ regulator-name = "vdd_usb";
+ };
+ scmi_vdd_sd: regulator@14 {
+ reg = <VOLTD_SCMI_STPMIC1_LDO5>;
+ regulator-name = "vdd_sd";
+ };
+ scmi_v1v8_periph: regulator@15 {
+ reg = <VOLTD_SCMI_STPMIC1_LDO6>;
+ regulator-name = "v1v8_periph";
+ };
+ scmi_v3v3_sw: regulator@19 {
+ reg = <VOLTD_SCMI_STPMIC1_PWR_SW2>;
+ regulator-name = "v3v3_sw";
+ };
+};
+
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
@@ -204,7 +196,7 @@
disable-wp;
st,neg-edge;
bus-width = <4>;
- vmmc-supply = <&vdd_sd>;
+ vmmc-supply = <&scmi_vdd_sd>;
status = "okay";
};
@@ -321,7 +313,7 @@
hub@1 {
compatible = "usb424,2514";
reg = <1>;
- vdd-supply = <&v3v3_sw>;
+ vdd-supply = <&scmi_v3v3_sw>;
};
};
@@ -342,7 +334,7 @@
};
&usbphyc_port0 {
- phy-supply = <&vdd_usb>;
+ phy-supply = <&scmi_vdd_usb>;
st,current-boost-microamp = <1000>;
st,decrease-hs-slew-rate;
st,tune-hs-dc-level = <2>;
@@ -356,7 +348,7 @@
};
&usbphyc_port1 {
- phy-supply = <&vdd_usb>;
+ phy-supply = <&scmi_vdd_usb>;
st,current-boost-microamp = <1000>;
st,decrease-hs-slew-rate;
st,tune-hs-dc-level = <2>;
diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
index e86d989..098153e 100644
--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi
@@ -6,6 +6,17 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
+ adc1_ain_pins_a: adc1-ain-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* ADC1_INP2 */
+ <STM32_PINMUX('B', 1, ANALOG)>, /* ADC1_INP5 */
+ <STM32_PINMUX('B', 0, ANALOG)>, /* ADC1_INP9 */
+ <STM32_PINMUX('C', 0, ANALOG)>, /* ADC1_INP10 */
+ <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1_INP13 */
+ <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1_INP15 */
+ };
+ };
+
adc1_in6_pins_a: adc1-in6-0 {
pins {
pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
@@ -341,6 +352,96 @@
};
};
+ ethernet0_rgmii_pins_d: rgmii-3 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
+ <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
+ <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
+ bias-disable;
+ };
+ };
+
+ ethernet0_rgmii_sleep_pins_d: rgmii-sleep-3 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
+ <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
+ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
+ <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
+ };
+ };
+
+ ethernet0_rgmii_pins_e: rgmii-4 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('B', 11, AF11)>; /* ETH_RGMII_TX_CTL */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
+ <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
+ bias-disable;
+ };
+ };
+
+ ethernet0_rgmii_sleep_pins_e: rgmii-sleep-4 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
+ <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
+ };
+ };
+
ethernet0_rmii_pins_a: rmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
@@ -1104,6 +1205,20 @@
};
};
+ pwm1_pins_c: pwm1-2 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 11, AF1)>; /* TIM1_CH2 */
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm1_sleep_pins_c: pwm1-sleep-2 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 11, ANALOG)>; /* TIM1_CH2 */
+ };
+ };
+
pwm2_pins_a: pwm2-0 {
pins {
pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
@@ -1230,6 +1345,26 @@
};
};
+ pwm8_pins_b: pwm8-1 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 5, AF3)>, /* TIM8_CH1 */
+ <STM32_PINMUX('I', 6, AF3)>, /* TIM8_CH2 */
+ <STM32_PINMUX('I', 7, AF3)>, /* TIM8_CH3 */
+ <STM32_PINMUX('C', 9, AF3)>; /* TIM8_CH4 */
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm8_sleep_pins_b: pwm8-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* TIM8_CH1 */
+ <STM32_PINMUX('I', 6, ANALOG)>, /* TIM8_CH2 */
+ <STM32_PINMUX('I', 7, ANALOG)>, /* TIM8_CH3 */
+ <STM32_PINMUX('C', 9, ANALOG)>; /* TIM8_CH4 */
+ };
+ };
+
pwm12_pins_a: pwm12-0 {
pins {
pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
@@ -1441,6 +1576,30 @@
};
};
+ sai2b_pins_d: sai2b-3 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 2, AF10)>, /* SAI2_SCK_B */
+ <STM32_PINMUX('C', 0, AF8)>, /* SAI2_FS_B */
+ <STM32_PINMUX('H', 3, AF10)>; /* SAI2_MCLK_B */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
+ bias-disable;
+ };
+ };
+
+ sai2b_sleep_pins_d: sai2b-sleep-3 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* SAI2_SCK_B */
+ <STM32_PINMUX('C', 0, ANALOG)>, /* SAI2_FS_B */
+ <STM32_PINMUX('H', 3, ANALOG)>, /* SAI2_MCLK_B */
+ <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
+ };
+ };
+
sai4a_pins_a: sai4a-0 {
pins {
pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
@@ -1522,6 +1681,60 @@
};
};
+ sdmmc1_b4_pins_b: sdmmc1-b4-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sdmmc1_b4_od_pins_b: sdmmc1-b4-od-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-disable;
+ };
+ };
+
+ sdmmc1_b4_sleep_pins_b: sdmmc1-b4-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('E', 6, ANALOG)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
+ };
+ };
+
sdmmc1_dir_pins_a: sdmmc1-dir-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
@@ -1531,7 +1744,7 @@
drive-push-pull;
bias-pull-up;
};
- pins2{
+ pins2 {
pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
bias-pull-up;
};
@@ -1566,7 +1779,7 @@
drive-push-pull;
bias-pull-up;
};
- pins2{
+ pins2 {
pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
bias-pull-up;
};
@@ -1759,6 +1972,27 @@
};
};
+ sdmmc2_d47_pins_e: sdmmc2-d47-4 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_d47_sleep_pins_e: sdmmc2-d47-sleep-4 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
+ };
+ };
+
sdmmc3_b4_pins_a: sdmmc3-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
@@ -1925,6 +2159,20 @@
};
};
+ spi2_pins_c: spi2-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */
+ <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
+ bias-disable;
+ drive-push-pull;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
+ bias-pull-down;
+ };
+ };
+
spi4_pins_a: spi4-0 {
pins {
pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
@@ -1939,6 +2187,21 @@
};
};
+ spi5_pins_a: spi5-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 7, AF5)>, /* SPI5_SCK */
+ <STM32_PINMUX('F', 9, AF5)>; /* SPI5_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 8, AF5)>; /* SPI5_MISO */
+ bias-disable;
+ };
+ };
+
stusb1600_pins_a: stusb1600-0 {
pins {
pinmux = <STM32_PINMUX('I', 11, GPIO)>;
@@ -2124,6 +2387,33 @@
};
};
+ usart1_pins_a: usart1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 12, AF7)>; /* USART1_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 11, AF7)>; /* USART1_CTS_NSS */
+ bias-disable;
+ };
+ };
+
+ usart1_idle_pins_a: usart1-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */
+ <STM32_PINMUX('A', 11, AF7)>; /* USART1_CTS_NSS */
+ };
+ };
+
+ usart1_sleep_pins_a: usart1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */
+ <STM32_PINMUX('A', 11, ANALOG)>; /* USART1_CTS_NSS */
+ };
+ };
+
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
@@ -2226,6 +2516,23 @@
};
};
+ usart3_idle_pins_a: usart3-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>; /* USART3_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
+ bias-disable;
+ };
+ };
+
+ usart3_sleep_pins_a: usart3-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
+ <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
+ };
+ };
+
usart3_pins_b: usart3-1 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
@@ -2385,6 +2692,21 @@
};
};
+ usart3_pins_f: usart3-5 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
+ <STM32_PINMUX('D', 12, AF7)>; /* USART3_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
+ <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
+ bias-disable;
+ };
+ };
+
usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
@@ -2463,4 +2785,42 @@
bias-disable;
};
};
+
+ spi1_sleep_pins_a: spi1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI1_SCK */
+ <STM32_PINMUX('Z', 1, ANALOG)>, /* SPI1_MISO */
+ <STM32_PINMUX('Z', 2, ANALOG)>; /* SPI1_MOSI */
+ };
+ };
+
+ usart1_pins_b: usart1-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('Z', 7, AF7)>; /* USART1_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */
+ bias-disable;
+ };
+ };
+
+ usart1_idle_pins_b: usart1-idle-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('Z', 7, ANALOG)>; /* USART1_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */
+ bias-disable;
+ };
+ };
+
+ usart1_sleep_pins_b: usart1-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 7, ANALOG)>, /* USART1_TX */
+ <STM32_PINMUX('Z', 6, ANALOG)>; /* USART1_RX */
+ };
+ };
};
diff --git a/arch/arm/dts/stm32mp15-scmi.dtsi b/arch/arm/dts/stm32mp15-scmi.dtsi
index ad25842..dc3b09f 100644
--- a/arch/arm/dts/stm32mp15-scmi.dtsi
+++ b/arch/arm/dts/stm32mp15-scmi.dtsi
@@ -34,22 +34,21 @@
#address-cells = <1>;
#size-cells = <0>;
- scmi_reg11: reg11@0 {
+ scmi_reg11: regulator@0 {
reg = <0>;
regulator-name = "reg11";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
};
- scmi_reg18: reg18@1 {
- voltd-name = "reg18";
+ scmi_reg18: regulator@1 {
reg = <1>;
regulator-name = "reg18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- scmi_usb33: usb33@2 {
+ scmi_usb33: regulator@2 {
reg = <2>;
regulator-name = "usb33";
regulator-min-microvolt = <3300000>;
diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
index 21d11be..e277140 100644
--- a/arch/arm/dts/stm32mp151.dtsi
+++ b/arch/arm/dts/stm32mp151.dtsi
@@ -1111,6 +1111,8 @@
adc1: adc@0 {
compatible = "st,stm32mp1-adc";
#io-channel-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x0>;
interrupt-parent = <&adc>;
interrupts = <0>;
@@ -1122,12 +1124,24 @@
adc2: adc@100 {
compatible = "st,stm32mp1-adc";
#io-channel-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x100>;
interrupt-parent = <&adc>;
interrupts = <1>;
dmas = <&dmamux1 10 0x400 0x01>;
dma-names = "rx";
+ nvmem-cells = <&vrefint>;
+ nvmem-cell-names = "vrefint";
status = "disabled";
+ channel@13 {
+ reg = <13>;
+ label = "vrefint";
+ };
+ channel@14 {
+ reg = <14>;
+ label = "vddcore";
+ };
};
};
@@ -1162,14 +1176,6 @@
status = "disabled";
};
- hwspinlock: hwspinlock@4c000000 {
- compatible = "st,stm32-hwspinlock";
- #hwlock-cells = <1>;
- reg = <0x4c000000 0x400>;
- clocks = <&rcc HSEM>;
- clock-names = "hwspinlock";
- };
-
ipcc: mailbox@4c001000 {
compatible = "st,stm32mp1-ipcc";
#mbox-cells = <1>;
@@ -1559,11 +1565,6 @@
clock-names = "lcd";
resets = <&rcc LTDC_R>;
status = "disabled";
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
- };
};
iwdg2: watchdog@5a002000 {
@@ -1650,9 +1651,12 @@
reg = <0x5c005000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
- part_number_otp: part_number_otp@4 {
+ part_number_otp: part-number-otp@4 {
reg = <0x4 0x1>;
};
+ vrefint: vrefin-cal@52 {
+ reg = <0x52 0x2>;
+ };
ts_cal1: calib@5c {
reg = <0x5c 0x2>;
};
@@ -1853,8 +1857,8 @@
<0x30000000 0x40000>,
<0x38000000 0x10000>;
resets = <&rcc MCU_R>;
+ reset-names = "mcu_rst";
st,syscfg-holdboot = <&rcc 0x10C 0x1>;
- st,syscfg-tz = <&rcc 0x000 0x1>;
st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi
index 54e73cc..6197d87 100644
--- a/arch/arm/dts/stm32mp157.dtsi
+++ b/arch/arm/dts/stm32mp157.dtsi
@@ -22,15 +22,26 @@
reg = <0x5a000000 0x800>;
clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
clock-names = "pclk", "ref", "px_clk";
+ phy-dsi-supply = <®18>;
resets = <&rcc DSI_R>;
reset-names = "apb";
- #address-cells = <1>;
- #size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ };
+ };
};
};
};
diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/dts/stm32mp157a-dk1-scmi.dts
index e539cc8..afcd628 100644
--- a/arch/arm/dts/stm32mp157a-dk1-scmi.dts
+++ b/arch/arm/dts/stm32mp157a-dk1-scmi.dts
@@ -55,8 +55,11 @@
resets = <&scmi_reset RST_SCMI_MDMA>;
};
-&mlahb {
- resets = <&scmi_reset RST_SCMI_MCU>;
+&m4_rproc {
+ /delete-property/ st,syscfg-holdboot;
+ resets = <&scmi_reset RST_SCMI_MCU>,
+ <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
+ reset-names = "mcu_rst", "hold_boot";
};
&rcc {
diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
index fae656e..f4a4942 100644
--- a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
+++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
@@ -81,6 +81,9 @@
status = "okay";
port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
ltdc_ep0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_in>;
diff --git a/arch/arm/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/dts/stm32mp157c-dk2-scmi.dts
index 97e4f94..39358d9 100644
--- a/arch/arm/dts/stm32mp157c-dk2-scmi.dts
+++ b/arch/arm/dts/stm32mp157c-dk2-scmi.dts
@@ -61,8 +61,11 @@
resets = <&scmi_reset RST_SCMI_MDMA>;
};
-&mlahb {
- resets = <&scmi_reset RST_SCMI_MCU>;
+&m4_rproc {
+ /delete-property/ st,syscfg-holdboot;
+ resets = <&scmi_reset RST_SCMI_MCU>,
+ <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
+ reset-names = "mcu_rst", "hold_boot";
};
&rcc {
diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts
index ab13e34..510cca5 100644
--- a/arch/arm/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/dts/stm32mp157c-dk2.dts
@@ -31,24 +31,9 @@
};
&dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "okay";
- phy-dsi-supply = <®18>;
-
- ports {
- port@0 {
- reg = <0>;
- dsi_in: endpoint {
- remote-endpoint = <<dc_ep1_out>;
- };
- };
-
- port@1 {
- reg = <1>;
- dsi_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
- };
panel@0 {
compatible = "orisetech,otm8009a";
@@ -65,6 +50,14 @@
};
};
+&dsi_in {
+ remote-endpoint = <<dc_ep1_out>;
+};
+
+&dsi_out {
+ remote-endpoint = <&panel_in>;
+};
+
&i2c1 {
touchscreen@38 {
compatible = "focaltech,ft6236";
@@ -82,6 +75,9 @@
status = "okay";
port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
ltdc_ep1_out: endpoint@1 {
reg = <1>;
remote-endpoint = <&dsi_in>;
diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/dts/stm32mp157c-ed1-scmi.dts
index 9cf0a44..07ea765 100644
--- a/arch/arm/dts/stm32mp157c-ed1-scmi.dts
+++ b/arch/arm/dts/stm32mp157c-ed1-scmi.dts
@@ -60,8 +60,11 @@
resets = <&scmi_reset RST_SCMI_MDMA>;
};
-&mlahb {
- resets = <&scmi_reset RST_SCMI_MCU>;
+&m4_rproc {
+ /delete-property/ st,syscfg-holdboot;
+ resets = <&scmi_reset RST_SCMI_MCU>,
+ <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
+ reset-names = "mcu_rst", "hold_boot";
};
&rcc {
diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
index 3541a17..66ed5f9 100644
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -103,21 +103,23 @@
vref-supply = <&vdda>;
status = "disabled";
adc1: adc@0 {
- st,adc-channels = <0 1 6>;
- /* 16.5 ck_cycles sampling time */
- st,min-sample-time-nsecs = <400>;
status = "okay";
+ channel@0 {
+ reg = <0>;
+ /* 16.5 ck_cycles sampling time */
+ st,min-sample-time-ns = <400>;
+ };
+ channel@1 {
+ reg = <1>;
+ st,min-sample-time-ns = <400>;
+ };
+ channel@6 {
+ reg = <6>;
+ st,min-sample-time-ns = <400>;
+ };
};
};
-&cpu0{
- cpu-supply = <&vddcore>;
-};
-
-&cpu1{
- cpu-supply = <&vddcore>;
-};
-
&crc1 {
status = "okay";
};
diff --git a/arch/arm/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/dts/stm32mp157c-ev1-scmi.dts
index 3b9dd6f..813086e 100644
--- a/arch/arm/dts/stm32mp157c-ev1-scmi.dts
+++ b/arch/arm/dts/stm32mp157c-ev1-scmi.dts
@@ -66,8 +66,11 @@
resets = <&scmi_reset RST_SCMI_MDMA>;
};
-&mlahb {
- resets = <&scmi_reset RST_SCMI_MCU>;
+&m4_rproc {
+ /delete-property/ st,syscfg-holdboot;
+ resets = <&scmi_reset RST_SCMI_MCU>,
+ <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
+ reset-names = "mcu_rst", "hold_boot";
};
&rcc {
diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
index 1f7fdbc..eb283ca 100644
--- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
@@ -135,20 +135,28 @@
&qspi_bk1_pins_a {
bootph-pre-ram;
- pins1 {
+ pins {
bootph-pre-ram;
};
- pins2 {
+};
+
+&qspi_cs1_pins_a {
+ bootph-pre-ram;
+ pins {
bootph-pre-ram;
};
};
&qspi_bk2_pins_a {
bootph-pre-ram;
- pins1 {
+ pins {
bootph-pre-ram;
};
- pins2 {
+};
+
+&qspi_cs2_pins_a {
+ bootph-pre-ram;
+ pins {
bootph-pre-ram;
};
};
diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts
index ba8e9d9..cd9c3ff 100644
--- a/arch/arm/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/dts/stm32mp157c-ev1.dts
@@ -100,26 +100,11 @@
};
&dsi {
- phy-dsi-supply = <®18>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "okay";
- ports {
- port@0 {
- reg = <0>;
- dsi_in: endpoint {
- remote-endpoint = <<dc_ep0_out>;
- };
- };
-
- port@1 {
- reg = <1>;
- dsi_out: endpoint {
- remote-endpoint = <&dsi_panel_in>;
- };
- };
- };
-
- panel-dsi@0 {
+ panel@0 {
compatible = "raydium,rm68200";
reg = <0>;
reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
@@ -135,6 +120,14 @@
};
};
+&dsi_in {
+ remote-endpoint = <<dc_ep0_out>;
+};
+
+&dsi_out {
+ remote-endpoint = <&dsi_panel_in>;
+};
+
ðernet0 {
status = "okay";
pinctrl-0 = <ðernet0_rgmii_pins_a>;
@@ -185,7 +178,9 @@
reg = <0x3c>;
clocks = <&clk_ext_camera>;
clock-names = "xclk";
+ AVDD-supply = <&v2v8>;
DOVDD-supply = <&v2v8>;
+ DVDD-supply = <&v2v8>;
powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
rotation = <180>;
@@ -239,8 +234,7 @@
status = "okay";
port {
- ltdc_ep0_out: endpoint@0 {
- reg = <0>;
+ ltdc_ep0_out: endpoint {
remote-endpoint = <&dsi_in>;
};
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index f12941b..2f70b06 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -134,20 +134,14 @@
&qspi_bk1_pins_a {
bootph-pre-ram;
- pins1 {
- bootph-pre-ram;
- };
- pins2 {
+ pins {
bootph-pre-ram;
};
};
-&qspi_bk2_pins_a {
+&qspi_cs1_pins_a {
bootph-pre-ram;
- pins1 {
- bootph-pre-ram;
- };
- pins2 {
+ pins {
bootph-pre-ram;
};
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
index eb905ad..552b35d 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
@@ -98,10 +98,14 @@
&qspi_bk1_pins_a {
bootph-pre-ram;
- pins1 {
+ pins {
bootph-pre-ram;
};
- pins2 {
+};
+
+&qspi_cs1_pins_a {
+ bootph-pre-ram;
+ pins {
bootph-pre-ram;
};
};
diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi
index f4de6c0..511113f 100644
--- a/arch/arm/dts/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi
@@ -93,28 +93,39 @@
&adc {
pinctrl-names = "default";
- pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>;
+ pinctrl-0 = <&adc12_usb_cc_pins_a>;
vdd-supply = <&vdd>;
vdda-supply = <&vdd>;
vref-supply = <&vrefbuf>;
- status = "disabled";
+ status = "okay";
adc1: adc@0 {
+ status = "okay";
/*
* Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
* Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
* 5 * (56 + 47kOhms) * 5pF => 2.5us.
* Use arbitrary margin here (e.g. 5us).
*/
- st,min-sample-time-nsecs = <5000>;
- /* AIN connector, USB Type-C CC1 & CC2 */
- st,adc-channels = <0 1 6 13 18 19>;
- status = "okay";
+ channel@18 {
+ reg = <18>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@19 {
+ reg = <19>;
+ st,min-sample-time-ns = <5000>;
+ };
};
adc2: adc@100 {
- /* AIN connector, USB Type-C CC1 & CC2 */
- st,adc-channels = <0 1 2 6 18 19>;
- st,min-sample-time-nsecs = <5000>;
status = "okay";
+ /* USB Type-C CC1 & CC2 */
+ channel@18 {
+ reg = <18>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@19 {
+ reg = <19>;
+ st,min-sample-time-ns = <5000>;
+ };
};
};
@@ -133,14 +144,6 @@
status = "okay";
};
-&cpu0{
- cpu-supply = <&vddcore>;
-};
-
-&cpu1{
- cpu-supply = <&vddcore>;
-};
-
ðernet0 {
status = "okay";
pinctrl-0 = <ðernet0_rgmii_pins_a>;
@@ -443,7 +446,7 @@
i2s2_port: port {
i2s2_endpoint: endpoint {
remote-endpoint = <&sii9022_tx_endpoint>;
- format = "i2s";
+ dai-format = "i2s";
mclk-fs = <256>;
};
};
@@ -465,8 +468,7 @@
status = "okay";
port {
- ltdc_ep0_out: endpoint@0 {
- reg = <0>;
+ ltdc_ep0_out: endpoint {
remote-endpoint = <&sii9022_in>;
};
};
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
index 135762b..2240eae 100644
--- a/arch/arm/dts/sun50i-a64.dtsi
+++ b/arch/arm/dts/sun50i-a64.dtsi
@@ -93,6 +93,7 @@
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
};
};
@@ -407,7 +408,7 @@
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
clock-names = "ahb", "tcon-ch0";
- clock-output-names = "tcon-pixel-clock";
+ clock-output-names = "tcon-data-clock";
#clock-cells = <0>;
resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
reset-names = "lcd", "lvds";
diff --git a/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts b/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts
index 686f58e..b710f1a 100644
--- a/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts
+++ b/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 Corentin LABBE <clabbe@baylibre.com>
*/
diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi b/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi
new file mode 100644
index 0000000..fc7315b
--- /dev/null
+++ b/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Arm Ltd.
+ *
+ * DT nodes common between Orange Pi Zero 2 and Orange Pi Zero 3.
+ * Excludes PMIC nodes and properties, since they are different between the two.
+ */
+
+#include "sun50i-h616.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ aliases {
+ ethernet0 = &emac0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
+ default-state = "on";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
+ };
+ };
+
+ reg_vcc5v: vcc5v {
+ /* board wide 5V supply directly from the USB-C socket */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ reg_usb1_vbus: regulator-usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_vcc5v>;
+ enable-active-high;
+ gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+/* USB 2 & 3 are on headers only. */
+
+&emac0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ext_rgmii_pins>;
+ phy-handle = <&ext_rgmii_phy>;
+ status = "okay";
+};
+
+&mdio0 {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ bus-width = <4>;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph_pins>;
+ status = "okay";
+};
+
+&usbotg {
+ /*
+ * PHY0 pins are connected to a USB-C socket, but a role switch
+ * is not implemented: both CC pins are pulled to GND.
+ * The VBUS pins power the device, so a fixed peripheral mode
+ * is the best choice.
+ * The board can be powered via GPIOs, in this case port0 *can*
+ * act as a host (with a cable/adapter ignoring CC), as VBUS is
+ * then provided by the GPIOs. Any user of this setup would
+ * need to adjust the DT accordingly: dr_mode set to "host",
+ * enabling OHCI0 and EHCI0.
+ */
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts
index cb8600d..b5d7139 100644
--- a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts
+++ b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts
@@ -1,99 +1,26 @@
-// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2020 Arm Ltd.
*/
/dts-v1/;
-#include "sun50i-h616.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/leds/common.h>
+#include "sun50i-h616-orangepi-zero.dtsi"
/ {
model = "OrangePi Zero2";
compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
-
- aliases {
- ethernet0 = &emac0;
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-0 {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_RED>;
- gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
- default-state = "on";
- };
-
- led-1 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
- };
- };
-
- reg_vcc5v: vcc5v {
- /* board wide 5V supply directly from the USB-C socket */
- compatible = "regulator-fixed";
- regulator-name = "vcc-5v";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- reg_usb1_vbus: regulator-usb1-vbus {
- compatible = "regulator-fixed";
- regulator-name = "usb1-vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <®_vcc5v>;
- enable-active-high;
- gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
- };
};
-&ehci1 {
- status = "okay";
-};
-
-/* USB 2 & 3 are on headers only. */
-
&emac0 {
- pinctrl-names = "default";
- pinctrl-0 = <&ext_rgmii_pins>;
- phy-mode = "rgmii";
- phy-handle = <&ext_rgmii_phy>;
- phy-supply = <®_dcdce>;
allwinner,rx-delay-ps = <3100>;
allwinner,tx-delay-ps = <700>;
- status = "okay";
-};
-
-&mdio0 {
- ext_rgmii_phy: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- };
+ phy-mode = "rgmii";
+ phy-supply = <®_dcdce>;
};
&mmc0 {
vmmc-supply = <®_dcdce>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- bus-width = <4>;
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
};
&r_rsb {
@@ -211,44 +138,3 @@
vcc-ph-supply = <®_aldo1>;
vcc-pi-supply = <®_aldo1>;
};
-
-&spi0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <40000000>;
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_ph_pins>;
- status = "okay";
-};
-
-&usbotg {
- /*
- * PHY0 pins are connected to a USB-C socket, but a role switch
- * is not implemented: both CC pins are pulled to GND.
- * The VBUS pins power the device, so a fixed peripheral mode
- * is the best choice.
- * The board can be powered via GPIOs, in this case port0 *can*
- * act as a host (with a cable/adapter ignoring CC), as VBUS is
- * then provided by the GPIOs. Any user of this setup would
- * need to adjust the DT accordingly: dr_mode set to "host",
- * enabling OHCI0 and EHCI0.
- */
- dr_mode = "peripheral";
- status = "okay";
-};
-
-&usbphy {
- usb1_vbus-supply = <®_usb1_vbus>;
- status = "okay";
-};
diff --git a/arch/arm/dts/sun50i-h616-x96-mate.dts b/arch/arm/dts/sun50i-h616-x96-mate.dts
index 07424c2..959b6fd 100644
--- a/arch/arm/dts/sun50i-h616-x96-mate.dts
+++ b/arch/arm/dts/sun50i-h616-x96-mate.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2021 Arm Ltd.
*/
diff --git a/arch/arm/dts/sun50i-h618-orangepi-zero3.dts b/arch/arm/dts/sun50i-h618-orangepi-zero3.dts
new file mode 100644
index 0000000..b3b1b86
--- /dev/null
+++ b/arch/arm/dts/sun50i-h618-orangepi-zero3.dts
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 Arm Ltd.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h616-orangepi-zero.dtsi"
+
+/ {
+ model = "OrangePi Zero3";
+ compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618";
+};
+
+&emac0 {
+ allwinner,tx-delay-ps = <700>;
+ phy-mode = "rgmii-rxid";
+ phy-supply = <®_dldo1>;
+};
+
+&ext_rgmii_phy {
+ motorcomm,clk-out-frequency-hz = <125000000>;
+};
+
+&mmc0 {
+ /*
+ * The schematic shows the card detect pin wired up to PF6, via an
+ * inverter, but it just doesn't work.
+ */
+ broken-cd;
+ vmmc-supply = <®_dldo1>;
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp313: pmic@36 {
+ compatible = "x-powers,axp313a";
+ reg = <0x36>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&pio>;
+ interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */
+
+ vin1-supply = <®_vcc5v>;
+ vin2-supply = <®_vcc5v>;
+ vin3-supply = <®_vcc5v>;
+
+ regulators {
+ /* Supplies VCC-PLL, so needs to be always on. */
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8";
+ };
+
+ /* Supplies VCC-IO, so needs to be always on. */
+ reg_dldo1: dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3";
+ };
+
+ reg_dcdc1: dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <990000>;
+ regulator-name = "vdd-gpu-sys";
+ };
+
+ reg_dcdc2: dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ reg_dcdc3: dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-dram";
+ };
+ };
+ };
+};
+
+&pio {
+ vcc-pc-supply = <®_dldo1>;
+ vcc-pf-supply = <®_dldo1>;
+ vcc-pg-supply = <®_aldo1>;
+ vcc-ph-supply = <®_dldo1>;
+ vcc-pi-supply = <®_dldo1>;
+};
diff --git a/arch/arm/dts/sun5i-r8-chip.dts b/arch/arm/dts/sun5i-r8-chip.dts
index fd37bd1..4192c23 100644
--- a/arch/arm/dts/sun5i-r8-chip.dts
+++ b/arch/arm/dts/sun5i-r8-chip.dts
@@ -255,6 +255,12 @@
pinctrl-0 = <&uart3_pg_pins>,
<&uart3_cts_rts_pg_pins>;
status = "okay";
+
+ bluetooth {
+ compatible = "realtek,rtl8723bs-bt";
+ device-wake-gpios = <&axp_gpio 3 GPIO_ACTIVE_HIGH>;
+ host-wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
+ };
};
&usb_otg {
diff --git a/arch/arm/dts/sun5i.dtsi b/arch/arm/dts/sun5i.dtsi
index 250d6b8..d7c7b45 100644
--- a/arch/arm/dts/sun5i.dtsi
+++ b/arch/arm/dts/sun5i.dtsi
@@ -286,7 +286,7 @@
clock-names = "ahb",
"tcon-ch0",
"tcon-ch1";
- clock-output-names = "tcon-pixel-clock";
+ clock-output-names = "tcon-data-clock";
#clock-cells = <0>;
status = "disabled";
@@ -517,6 +517,15 @@
bias-pull-up;
};
+ /omit-if-no-ref/
+ mmc2_4bit_pe_pins: mmc2-4bit-pe-pins {
+ pins = "PE4", "PE5", "PE6", "PE7",
+ "PE8", "PE9";
+ function = "mmc2";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
mmc2_8bit_pins: mmc2-8bit-pins {
pins = "PC6", "PC7", "PC8", "PC9",
"PC10", "PC11", "PC12", "PC13",
diff --git a/arch/arm/dts/sun7i-a20-icnova-a20-adb4006.dts b/arch/arm/dts/sun7i-a20-icnova-a20-adb4006.dts
new file mode 100644
index 0000000..577ead1
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-icnova-a20-adb4006.dts
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// Copyright (C) 2023 In-Circuit GmbH
+
+/dts-v1/;
+
+#include "sun7i-a20-icnova-a20.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "In-Circuit ICnova A20 ADB4006";
+ compatible = "incircuit,icnova-a20-adb4006", "incircuit,icnova-a20",
+ "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_YELLOW>;
+ gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* PH21 */
+ default-state = "on";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* PH20 */
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&ahci {
+ target-supply = <®_ahci_5v>;
+ status = "okay";
+};
+
+&codec {
+ status = "okay";
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+®_ahci_5v {
+ status = "okay";
+};
+
+&ac_power_supply {
+ status = "okay";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pb_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun7i-a20-icnova-a20.dtsi b/arch/arm/dts/sun7i-a20-icnova-a20.dtsi
new file mode 100644
index 0000000..46616c6
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-icnova-a20.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// Copyright (C) 2023 In-Circuit GmbH
+
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_mii_pins>;
+ phy-handle = <&phy1>;
+ phy-mode = "mii";
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+#include "axp209.dtsi"
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
diff --git a/arch/arm/dts/sun8i-a23-a33.dtsi b/arch/arm/dts/sun8i-a23-a33.dtsi
index 84c6d93..a0cac96 100644
--- a/arch/arm/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/dts/sun8i-a23-a33.dtsi
@@ -190,7 +190,7 @@
clock-names = "ahb",
"tcon-ch0",
"lvds-alt";
- clock-output-names = "tcon-pixel-clock";
+ clock-output-names = "tcon-data-clock";
#clock-cells = <0>;
resets = <&ccu RST_BUS_LCD>,
<&ccu RST_BUS_LVDS>;
diff --git a/arch/arm/dts/sun8i-a83t.dtsi b/arch/arm/dts/sun8i-a83t.dtsi
index 9c07660..cc40622 100644
--- a/arch/arm/dts/sun8i-a83t.dtsi
+++ b/arch/arm/dts/sun8i-a83t.dtsi
@@ -456,7 +456,7 @@
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
clock-names = "ahb", "tcon-ch0";
- clock-output-names = "tcon-pixel-clock";
+ clock-output-names = "tcon-data-clock";
#clock-cells = <0>;
resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
reset-names = "lcd", "lvds";
diff --git a/arch/arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts b/arch/arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts
new file mode 100644
index 0000000..8b3a753
--- /dev/null
+++ b/arch/arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2022 Arm Ltd.
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/dts-v1/;
+
+#include "sun8i-t113s.dtsi"
+#include "sunxi-d1s-t113-mangopi-mq-r.dtsi"
+
+/ {
+ model = "MangoPi MQ-R-T113";
+ compatible = "widora,mangopi-mq-r-t113", "allwinner,sun8i-t113s";
+
+ aliases {
+ ethernet0 = &rtl8189ftv;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_vcc_core>;
+};
+
+&cpu1 {
+ cpu-supply = <®_vcc_core>;
+};
+
+&mmc1 {
+ rtl8189ftv: wifi@1 {
+ reg = <1>;
+ interrupt-parent = <&pio>;
+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 = WL_WAKE_AP */
+ interrupt-names = "host-wake";
+ };
+};
diff --git a/arch/arm/dts/sun8i-t113s.dtsi b/arch/arm/dts/sun8i-t113s.dtsi
new file mode 100644
index 0000000..b94b691
--- /dev/null
+++ b/arch/arm/dts/sun8i-t113s.dtsi
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2022 Arm Ltd.
+
+#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <../../riscv/dts/sunxi-d1s-t113.dtsi>
+#include <../../riscv/dts/sunxi-d1-t113.dtsi>
+
+/ {
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&ccu CLK_CPUX>;
+ clock-names = "cpu";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ clocks = <&ccu CLK_CPUX>;
+ clock-names = "cpu";
+ };
+ };
+
+ gic: interrupt-controller@1c81000 {
+ compatible = "arm,gic-400";
+ reg = <0x03021000 0x1000>,
+ <0x03022000 0x2000>,
+ <0x03024000 0x2000>,
+ <0x03026000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ };
+};
diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi
index b001251..3b9a282 100644
--- a/arch/arm/dts/sun8i-v3s.dtsi
+++ b/arch/arm/dts/sun8i-v3s.dtsi
@@ -191,7 +191,7 @@
<&ccu CLK_TCON0>;
clock-names = "ahb",
"tcon-ch0";
- clock-output-names = "tcon-pixel-clock";
+ clock-output-names = "tcon-data-clock";
#clock-cells = <0>;
resets = <&ccu RST_BUS_TCON0>;
reset-names = "lcd";
diff --git a/arch/arm/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi b/arch/arm/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi
new file mode 100644
index 0000000..a415c4a
--- /dev/null
+++ b/arch/arm/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2022 Arm Ltd.
+/*
+ * Common peripherals and configurations for MangoPi MQ-R boards.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ aliases {
+ serial3 = &uart3;
+ };
+
+ chosen {
+ stdout-path = "serial3:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&pio 3 22 GPIO_ACTIVE_LOW>; /* PD22 */
+ };
+ };
+
+ /* board wide 5V supply directly from the USB-C socket */
+ reg_vcc5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ /* SY8008 DC/DC regulator on the board */
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <®_vcc5v>;
+ };
+
+ /* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */
+ reg_vcc_core: regulator-core {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-core";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ vin-supply = <®_vcc5v>;
+ };
+
+ /* XC6206 LDO on the board */
+ reg_avdd2v8: regulator-avdd {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd2v8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ vin-supply = <®_3v3>;
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
+ };
+};
+
+&dcxo {
+ clock-frequency = <24000000>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-0 = <&mmc0_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <®_3v3>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-0 = <&mmc1_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <®_3v3>;
+ non-removable;
+ bus-width = <4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ vcc-pb-supply = <®_3v3>;
+ vcc-pd-supply = <®_3v3>;
+ vcc-pe-supply = <®_avdd2v8>;
+ vcc-pf-supply = <®_3v3>;
+ vcc-pg-supply = <®_3v3>;
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pb_pins>;
+ status = "okay";
+};
+
+/* The USB-C socket has its CC pins pulled to GND, so is hardwired as a UFP. */
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_vcc5v>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
index af419c7..a0c8abb 100644
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -23,6 +23,13 @@
};
};
+/* Let U-Boot be the firmware layer that controls the watchdog. */
+#ifdef CONFIG_MACH_SUN8I_R528
+&wdt {
+ status = "okay";
+};
+#endif
+
&binman {
u-boot-sunxi-with-spl {
filename = "u-boot-sunxi-with-spl.bin";
diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi
index a521a43..28ecd2b 100644
--- a/arch/arm/dts/tegra210.dtsi
+++ b/arch/arm/dts/tegra210.dtsi
@@ -704,6 +704,8 @@
clock-names = "sdhci";
resets = <&tegra_car 14>;
reset-names = "sdhci";
+ nvidia,default-tap = <0x2>;
+ nvidia,default-trim = <0x4>;
status = "disabled";
};
@@ -715,6 +717,8 @@
clock-names = "sdhci";
resets = <&tegra_car 9>;
reset-names = "sdhci";
+ nvidia,default-tap = <0x8>;
+ nvidia,default-trim = <0x0>;
status = "disabled";
};
@@ -726,6 +730,8 @@
clock-names = "sdhci";
resets = <&tegra_car 69>;
reset-names = "sdhci";
+ nvidia,default-tap = <0x3>;
+ nvidia,default-trim = <0x3>;
status = "disabled";
};
@@ -737,6 +743,8 @@
clock-names = "sdhci";
resets = <&tegra_car 15>;
reset-names = "sdhci";
+ nvidia,default-tap = <0x8>;
+ nvidia,default-trim = <0x0>;
status = "disabled";
};
diff --git a/arch/arm/dts/tegra30-asus-grouper-common.dtsi b/arch/arm/dts/tegra30-asus-grouper-common.dtsi
index 4fa980f..fcf31e2 100644
--- a/arch/arm/dts/tegra30-asus-grouper-common.dtsi
+++ b/arch/arm/dts/tegra30-asus-grouper-common.dtsi
@@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/input/input.h>
-
#include "tegra30.dtsi"
/ {
@@ -62,6 +61,9 @@
status = "okay";
bus-width = <8>;
non-removable;
+
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vdd_1v8_vio>;
};
usb1: usb@7d000000 {
@@ -150,7 +152,6 @@
regulator-name = "vdd_5v0_bl";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- regulator-boot-on;
gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
diff --git a/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts b/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts
index a98d3e2..945ae40 100644
--- a/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts
+++ b/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts
@@ -22,7 +22,7 @@
gpio-controller;
regulators {
- vdd_1v8: sd2 {
+ vdd_1v8_vio: sd2 {
regulator-name = "vdd_1v8_gen";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -34,8 +34,7 @@
vcore_emmc: ldo3 {
regulator-name = "vcore_emmc";
regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <3100000>;
- regulator-always-on;
+ regulator-max-microvolt = <2850000>;
};
};
};
diff --git a/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts b/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts
index 44ea218..4363bfc 100644
--- a/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts
+++ b/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts
@@ -23,12 +23,19 @@
gpio-controller;
regulators {
+ vdd_1v8_vio: vddio {
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
/* eMMC VDD */
vcore_emmc: ldo1 {
regulator-name = "vdd_emmc_core";
- regulator-min-microvolt = <1000000>;
+ regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-always-on;
};
};
};
diff --git a/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts b/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts
index 812d5a1..89348fd 100644
--- a/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts
+++ b/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts
@@ -22,7 +22,7 @@
gpio-controller;
regulators {
- vdd_1v8: sd2 {
+ vdd_1v8_vio: sd2 {
regulator-name = "vdd_1v8_gen";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -34,8 +34,7 @@
vcore_emmc: ldo3 {
regulator-name = "vcore_emmc";
regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <3100000>;
- regulator-always-on;
+ regulator-max-microvolt = <2850000>;
};
};
};
diff --git a/arch/arm/dts/tegra30-asus-p1801-t.dts b/arch/arm/dts/tegra30-asus-p1801-t.dts
index 4b2dc61..39f7caf 100644
--- a/arch/arm/dts/tegra30-asus-p1801-t.dts
+++ b/arch/arm/dts/tegra30-asus-p1801-t.dts
@@ -1,18 +1,209 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
-#include "tegra30-asus-transformer.dtsi"
+#include <dt-bindings/input/input.h>
+#include "tegra30.dtsi"
/ {
model = "ASUS Portable AiO P1801-T";
compatible = "asus,p1801-t", "nvidia,tegra30";
- /delete-node/ host1x@50000000;
- /delete-node/ pwm@7000a000;
+ chosen {
+ stdout-path = &uarta;
+ };
- /delete-node/ backlight;
- /delete-node/ panel;
+ aliases {
+ i2c0 = &pwr_i2c;
+ i2c1 = &hdmi_ddc;
- /delete-node/ regulator-pnl;
- /delete-node/ regulator-bl;
+ mmc0 = &sdmmc4; /* eMMC */
+ mmc1 = &sdmmc1; /* uSD slot */
+
+ rtc0 = &pmic;
+ rtc1 = "/rtc@7000e000";
+
+ usb0 = &usb1;
+ usb1 = &usb2; /* Mini USB */
+ usb2 = &usb3; /* Dock USB */
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ host1x@50000000 {
+ dc@54200000 {
+ clocks = <&tegra_car TEGRA30_CLK_DISP1>,
+ <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
+
+ rgb {
+ status = "okay";
+
+ nvidia,panel = <&hdmi>;
+ };
+ };
+
+ hdmi: hdmi@54280000 {
+ clocks = <&tegra_car TEGRA30_CLK_HDMI>,
+ <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
+
+ status = "okay";
+
+ hdmi-supply = <&hdmi_5v0_sys>;
+ pll-supply = <&vdd_1v8_vio>;
+ vdd-supply = <&hdmi_3v3_vdd>;
+
+ /* low: tablet, high: dock */
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(H, 4) GPIO_ACTIVE_LOW>;
+ nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+ };
+ };
+
+ uarta: serial@70006000 {
+ status = "okay";
+ };
+
+ hdmi_ddc: i2c@7000c700 {
+ status = "okay";
+ clock-frequency = <33000>;
+ };
+
+ pwr_i2c: i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Texas Instruments TPS659110 PMIC */
+ pmic: tps65911@2d {
+ compatible = "ti,tps65911";
+ reg = <0x2d>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ regulators {
+ vdd_1v8_vio: vddio {
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* eMMC VDD */
+ vcore_emmc: ldo1 {
+ regulator-name = "vdd_emmc_core";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ /* uSD slot VDD */
+ vdd_usd: ldo2 {
+ regulator-name = "vdd_usd";
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3100000>;
+ };
+
+ /* uSD slot VDDIO */
+ vddio_usd: ldo3 {
+ regulator-name = "vddio_usd";
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+ };
+
+ sdmmc1: sdhci@78000000 {
+ status = "okay";
+ bus-width = <4>;
+
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+ power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
+
+ vmmc-supply = <&vdd_usd>;
+ vqmmc-supply = <&vddio_usd>;
+ };
+
+ sdmmc4: sdhci@78000600 {
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vdd_1v8_vio>;
+ };
+
+ /* USB via ASUS connector */
+ usb1: usb@7d000000 {
+ status = "okay";
+ dr_mode = "otg";
+ };
+
+ /* Mini USB port */
+ usb2: usb@7d004000 {
+ status = "okay";
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
+ };
+
+ /* Dock's USB port */
+ usb3: usb@7d008000 {
+ status = "okay";
+ };
+
+ /* PMIC has a built-in 32KHz oscillator which is used by PMC */
+ clk32k_in: clock-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "pmic-oscillator";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_ENTER>;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_UP>;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_DOWN>;
+ };
+ };
+
+ hdmi_3v3_vdd: regulator-vdd {
+ compatible = "regulator-fixed";
+ regulator-name = "hdmi_3v3_vdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ hdmi_5v0_sys: regulator-hdmi {
+ compatible = "regulator-fixed";
+ regulator-name = "hdmi_5v0_sys";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
};
diff --git a/arch/arm/dts/tegra30-asus-tf201.dts b/arch/arm/dts/tegra30-asus-tf201.dts
index 54f359e..59e19f9 100644
--- a/arch/arm/dts/tegra30-asus-tf201.dts
+++ b/arch/arm/dts/tegra30-asus-tf201.dts
@@ -6,4 +6,9 @@
/ {
model = "ASUS Transformer Prime TF201";
compatible = "asus,tf201", "nvidia,tegra30";
+
+ usb-phy@7d008000 {
+ /delete-property/ nvidia,xcvr-setup-use-fuses;
+ nvidia,xcvr-setup = <5>; /* Based on TF201 fuse value - 48 */
+ };
};
diff --git a/arch/arm/dts/tegra30-asus-tf600t.dts b/arch/arm/dts/tegra30-asus-tf600t.dts
index c9b8f4f..fd9d11c 100644
--- a/arch/arm/dts/tegra30-asus-tf600t.dts
+++ b/arch/arm/dts/tegra30-asus-tf600t.dts
@@ -1,38 +1,116 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
-#include "tegra30-asus-transformer.dtsi"
+#include <dt-bindings/input/input.h>
+#include "tegra30.dtsi"
/ {
model = "ASUS VivoTab RT TF600T";
compatible = "asus,tf600t", "nvidia,tegra30";
- aliases {
- spi0 = &spi4;
+ chosen {
+ stdout-path = &uarta;
};
- /delete-node/ host1x@50000000;
+ aliases {
+ i2c0 = &pwr_i2c;
- pmic_i2c: i2c@7000d000 {
+ mmc0 = &sdmmc4; /* eMMC */
+ mmc1 = &sdmmc1; /* uSD slot */
+
+ rtc0 = &pmic;
+ rtc1 = "/rtc@7000e000";
+
+ spi0 = &spi4;
+
+ usb0 = &usb1;
+ usb1 = &usb3; /* Dock USB */
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ host1x@50000000 {
+ dc@54200000 {
+ clocks = <&tegra_car TEGRA30_CLK_DISP1>,
+ <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
+
+ rgb {
+ status = "okay";
+
+ nvidia,panel = <&dsia>;
+ };
+ };
+
+ dsia: dsi@54300000 {
+ status = "okay";
+
+ avdd-dsi-csi-supply = <&avdd_dsi_csi>;
+
+ panel = <&panel>;
+ };
+ };
+
+ uarta: serial@70006000 {
+ status = "okay";
+ };
+
+ pwm: pwm@7000a000 {
+ status = "okay";
+ };
+
+ pwr_i2c: i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
/* Texas Instruments TPS659110 PMIC */
pmic: tps65911@2d {
+ compatible = "ti,tps65911";
+ reg = <0x2d>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
regulators {
vdd_1v2_bl: vdd1 {
regulator-name = "vdd_1v2_backlight";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
- regulator-always-on;
- regulator-boot-on;
- ti,regulator-ext-sleep-control = <8>;
};
- /delete-node/ ldo2;
- /delete-node/ ldo3;
+ vcore_lcd: vdd2 {
+ regulator-name = "vcore_lcd";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ };
+
+ vdd_1v8_vio: vddio {
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* eMMC VDD */
+ vcore_emmc: ldo1 {
+ regulator-name = "vdd_emmc_core";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
/* uSD slot VDDIO */
vddio_usd: ldo5 {
regulator-name = "vddio_sdmmc";
- regulator-min-microvolt = <1800000>;
+ regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
@@ -57,11 +135,65 @@
};
};
- backlight {
+ sdmmc1: sdhci@78000000 {
+ status = "okay";
+ bus-width = <4>;
+
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+ power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
+
+ vmmc-supply = <&vdd_usd>;
+ vqmmc-supply = <&vddio_usd>;
+ };
+
+ sdmmc4: sdhci@78000600 {
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vdd_1v8_vio>;
+ };
+
+ /* USB via ASUS connector */
+ usb1: usb@7d000000 {
+ status = "okay";
+ dr_mode = "otg";
+ };
+
+ /* Dock's USB port */
+ usb3: usb@7d008000 {
+ status = "okay";
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
power-supply = <&vdd_1v2_bl>;
+ pwms = <&pwm 0 71428>;
+
+ brightness-levels = <1 35 70 105 140 175 210 255>;
+ default-brightness-level = <5>;
+ };
+
+ /* PMIC has a built-in 32KHz oscillator which is used by PMC */
+ clk32k_in: clock-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "pmic-oscillator";
};
gpio-keys {
+ compatible = "gpio-keys";
+
+ key-power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_ENTER>;
+ };
+
key-volume-up {
label = "Volume Up";
gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
@@ -75,7 +207,14 @@
};
};
- /delete-node/ panel;
+ panel: panel {
+ compatible = "hydis,hv101hd1";
+
+ vdd-supply = <&vcore_lcd>;
+ enable-gpios = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
+
+ backlight = <&backlight>;
+ };
vdd_usd: regulator-usd {
compatible = "regulator-fixed";
@@ -83,7 +222,4 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
-
- /delete-node/ regulator-pnl;
- /delete-node/ regulator-bl;
};
diff --git a/arch/arm/dts/tegra30-asus-transformer.dtsi b/arch/arm/dts/tegra30-asus-transformer.dtsi
index 4eee1df..888f9ca 100644
--- a/arch/arm/dts/tegra30-asus-transformer.dtsi
+++ b/arch/arm/dts/tegra30-asus-transformer.dtsi
@@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/input/input.h>
-
#include "tegra30.dtsi"
/ {
@@ -70,12 +69,19 @@
gpio-controller;
regulators {
+ vdd_1v8_vio: vddio {
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
/* eMMC VDD */
vcore_emmc: ldo1 {
regulator-name = "vdd_emmc_core";
- regulator-min-microvolt = <1000000>;
+ regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-always-on;
};
/* uSD slot VDD */
@@ -88,8 +94,10 @@
/* uSD slot VDDIO */
vddio_usd: ldo3 {
regulator-name = "vddio_usd";
- regulator-min-microvolt = <1800000>;
+ regulator-min-microvolt = <3100000>;
regulator-max-microvolt = <3100000>;
+ regulator-always-on;
+ regulator-boot-on;
};
};
};
@@ -110,6 +118,9 @@
status = "okay";
bus-width = <8>;
non-removable;
+
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vdd_1v8_vio>;
};
/* USB via ASUS connector */
@@ -123,6 +134,10 @@
status = "okay";
};
+ usb-phy@7d008000 {
+ status = "okay";
+ };
+
backlight: backlight {
compatible = "pwm-backlight";
@@ -204,7 +219,6 @@
regulator-name = "vdd_5v0_bl";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- regulator-boot-on;
gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
diff --git a/arch/arm/dts/tegra30-htc-endeavoru.dts b/arch/arm/dts/tegra30-htc-endeavoru.dts
index c55e193..5c7b2de 100644
--- a/arch/arm/dts/tegra30-htc-endeavoru.dts
+++ b/arch/arm/dts/tegra30-htc-endeavoru.dts
@@ -5,7 +5,6 @@
/* CPU Speedo ID 4, Soc Speedo ID 1, CPU Process: 1, Core Process: 0 */
#include <dt-bindings/input/input.h>
-
#include "tegra30.dtsi"
/ {
@@ -66,13 +65,22 @@
compatible = "ti,tps80032";
reg = <0x48>;
+ ti,system-power-controller;
+
regulators {
+ vdd_1v8_vio: smps5 {
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
/* DSI VDD */
avdd_dsi_csi: ldo1 {
regulator-name = "avdd_dsi_csi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
- regulator-always-on;
};
};
};
@@ -82,6 +90,9 @@
status = "okay";
bus-width = <8>;
non-removable;
+
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vdd_1v8_vio>;
};
micro_usb: usb@7d000000 {
diff --git a/arch/arm/dts/tegra30-lg-x3.dtsi b/arch/arm/dts/tegra30-lg-x3.dtsi
index 922e399..6e52fc5 100644
--- a/arch/arm/dts/tegra30-lg-x3.dtsi
+++ b/arch/arm/dts/tegra30-lg-x3.dtsi
@@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/input/input.h>
-
#include "tegra30.dtsi"
/ {
@@ -91,6 +90,14 @@
regulator-boot-on;
};
+ avdd_3v3_periph: ldo2 {
+ regulator-name = "avdd_usb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
vdd_usd: ldo3 {
regulator-name = "vdd_sdmmc3";
regulator-min-microvolt = <3000000>;
@@ -103,8 +110,6 @@
regulator-name = "vdd_ddr_rx";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
- regulator-always-on;
- regulator-boot-on;
};
};
};
diff --git a/arch/arm/dts/tps6507x.dtsi b/arch/arm/dts/tps6507x.dtsi
index db4809d..6749d3f 100644
--- a/arch/arm/dts/tps6507x.dtsi
+++ b/arch/arm/dts/tps6507x.dtsi
@@ -1,11 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
/*
* Integrated Power Management Chip
- * http://www.ti.com/lit/ds/symlink/tps65070.pdf
+ * https://www.ti.com/lit/ds/symlink/tps65070.pdf
*/
&tps {
diff --git a/arch/arm/dts/tps65217.dtsi b/arch/arm/dts/tps65217.dtsi
index 0d463de..262e0bb 100644
--- a/arch/arm/dts/tps65217.dtsi
+++ b/arch/arm/dts/tps65217.dtsi
@@ -1,11 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/*
* Integrated Power Management Chip
- * http://www.ti.com/lit/ds/symlink/tps65217.pdf
+ * https://www.ti.com/lit/ds/symlink/tps65217.pdf
*/
&tps {
diff --git a/arch/arm/dts/tps65910.dtsi b/arch/arm/dts/tps65910.dtsi
index a941d1e..ab3a4ff 100644
--- a/arch/arm/dts/tps65910.dtsi
+++ b/arch/arm/dts/tps65910.dtsi
@@ -1,11 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/*
* Integrated Power Management Chip
- * http://www.ti.com/lit/ds/symlink/tps65910.pdf
+ * https://www.ti.com/lit/ds/symlink/tps65910.pdf
*/
&tps {
diff --git a/arch/arm/dts/twl4030.dtsi b/arch/arm/dts/twl4030.dtsi
index 6cb0a01..f87cea1 100644
--- a/arch/arm/dts/twl4030.dtsi
+++ b/arch/arm/dts/twl4030.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/dts/twl6030.dtsi b/arch/arm/dts/twl6030.dtsi
index 9d588cf..8da9690 100644
--- a/arch/arm/dts/twl6030.dtsi
+++ b/arch/arm/dts/twl6030.dtsi
@@ -1,11 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
/*
* Integrated Power Management Chip
- * http://www.ti.com/lit/ds/symlink/twl6030.pdf
+ * https://www.ti.com/lit/ds/symlink/twl6030.pdf
*/
&twl {
compatible = "ti,twl6030";
diff --git a/arch/arm/dts/twl6030_omap4.dtsi b/arch/arm/dts/twl6030_omap4.dtsi
index fc498d0..5730e46 100644
--- a/arch/arm/dts/twl6030_omap4.dtsi
+++ b/arch/arm/dts/twl6030_omap4.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
&twl {
diff --git a/arch/arm/dts/ulcb-audio-graph-card.dtsi b/arch/arm/dts/ulcb-audio-graph-card.dtsi
new file mode 100644
index 0000000..3be54df
--- /dev/null
+++ b/arch/arm/dts/ulcb-audio-graph-card.dtsi
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree for ULCB + Audio Graph Card
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+/*
+ * (A) CPU0 <-----> ak4613
+ * (B) CPU1 -----> HDMI
+ *
+ * (A) aplay -D plughw:0,0 xxx.wav
+ * (B) aplay -D plughw:0,1 xxx.wav
+ *
+ * (A) arecord -D plughw:0,0 xxx.wav
+ */
+
+/ {
+ sound_card: sound {
+ compatible = "audio-graph-card";
+ label = "rcar-sound";
+
+ dais = <&rsnd_port0 /* (A) CPU0 <-> ak4613 */
+ &rsnd_port1 /* (B) CPU1 -> HDMI */
+ >;
+ };
+};
+
+&ak4613 {
+ #sound-dai-cells = <0>;
+
+ port {
+ /*
+ * (A) CPU0 <-> ak4613
+ */
+ ak4613_endpoint: endpoint {
+ remote-endpoint = <&rsnd_for_ak4613>;
+ };
+ };
+};
+
+&hdmi0 {
+ ports {
+ port@2 {
+ /*
+ * (B) CPU1 -> HDMI
+ */
+ dw_hdmi0_snd_in: endpoint {
+ remote-endpoint = <&rsnd_for_hdmi>;
+ };
+ };
+ };
+};
+
+&rcar_sound {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rsnd_port0: port@0 {
+ /*
+ * (A) CPU0 <-> ak4613
+ */
+ reg = <0>;
+ rsnd_for_ak4613: endpoint {
+ remote-endpoint = <&ak4613_endpoint>;
+ bitclock-master;
+ frame-master;
+ playback = <&ssi0>, <&src0>, <&dvc0>;
+ capture = <&ssi1>, <&src1>, <&dvc1>;
+ };
+ };
+ rsnd_port1: port@1 {
+ /*
+ * (B) CPU1 -> HDMI
+ */
+ reg = <1>;
+ rsnd_for_hdmi: endpoint {
+ remote-endpoint = <&dw_hdmi0_snd_in>;
+ bitclock-master;
+ frame-master;
+ playback = <&ssi2>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/ulcb-audio-graph-card2.dtsi b/arch/arm/dts/ulcb-audio-graph-card2.dtsi
new file mode 100644
index 0000000..5ebec12
--- /dev/null
+++ b/arch/arm/dts/ulcb-audio-graph-card2.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree for ULCB + Audio Graph Card2
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+/*
+ * (A) CPU0 <----> ak4613
+ * (B) CPU1 ----> HDMI
+ *
+ * (A) aplay -D plughw:0,0 xxx.wav
+ * (B) aplay -D plughw:0,1 xxx.wav
+ *
+ * (A) arecord -D plughw:0,0 xxx.wav
+ */
+#include "ulcb-audio-graph-card.dtsi"
+
+&sound_card {
+ compatible = "audio-graph-card2";
+
+ /delete-property/ dais;
+ links = <&rsnd_port0 /* (A) CPU0 <-> ak4613 */
+ &rsnd_port1 /* (B) CPU1 -> HDMI */
+ >;
+};
diff --git a/arch/arm/dts/ulcb.dtsi b/arch/arm/dts/ulcb.dtsi
index 29cedf4..0be2716 100644
--- a/arch/arm/dts/ulcb.dtsi
+++ b/arch/arm/dts/ulcb.dtsi
@@ -6,14 +6,6 @@
* Copyright (C) 2016 Cogent Embedded, Inc.
*/
-/*
- * SSI-AK4613
- * aplay -D plughw:0,0 xxx.wav
- * arecord -D plughw:0,0 xxx.wav
- * SSI-HDMI
- * aplay -D plughw:0,1 xxx.wav
- */
-
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@@ -102,15 +94,6 @@
regulator-always-on;
};
- sound_card: sound {
- compatible = "audio-graph-card2";
- label = "rcar-sound";
-
- links = <&rsnd_port0 /* ak4613 */
- &rsnd_port1 /* HDMI0 */
- >;
- };
-
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
@@ -201,9 +184,6 @@
};
port@2 {
reg = <2>;
- dw_hdmi0_snd_in: endpoint {
- remote-endpoint = <&rsnd_for_hdmi>;
- };
};
};
};
@@ -218,7 +198,6 @@
ak4613: codec@10 {
compatible = "asahi-kasei,ak4613";
- #sound-dai-cells = <0>;
reg = <0x10>;
clocks = <&rcar_sound 3>;
@@ -230,12 +209,6 @@
asahi-kasei,out4-single-end;
asahi-kasei,out5-single-end;
asahi-kasei,out6-single-end;
-
- port {
- ak4613_endpoint: endpoint {
- remote-endpoint = <&rsnd_for_ak4613>;
- };
- };
};
cs2000: clk-multiplier@4f {
@@ -294,6 +267,12 @@
};
};
};
+
+ eeprom@50 {
+ compatible = "rohm,br24t01", "atmel,24c01";
+ reg = <0x50>;
+ pagesize = <8>;
+ };
};
&ohci1 {
@@ -381,9 +360,6 @@
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
- /* Single DAI */
- #sound-dai-cells = <0>;
-
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <12288000 11289600>;
@@ -408,30 +384,6 @@
<&audio_clk_a>, <&cs2000>,
<&audio_clk_c>,
<&cpg CPG_CORE CPG_AUDIO_CLK_I>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- rsnd_port0: port@0 {
- reg = <0>;
- rsnd_for_ak4613: endpoint {
- remote-endpoint = <&ak4613_endpoint>;
- bitclock-master;
- frame-master;
- playback = <&ssi0>, <&src0>, <&dvc0>;
- capture = <&ssi1>, <&src1>, <&dvc1>;
- };
- };
- rsnd_port1: port@1 {
- reg = <1>;
- rsnd_for_hdmi: endpoint {
- remote-endpoint = <&dw_hdmi0_snd_in>;
- bitclock-master;
- frame-master;
- playback = <&ssi2>;
- };
- };
- };
};
&rpc {
@@ -541,3 +493,17 @@
status = "okay";
};
+
+
+/*
+ * For sound-test.
+ *
+ * We can switch Audio Card for testing
+ *
+ * #include "ulcb-simple-audio-card.dtsi"
+ * #include "ulcb-simple-audio-card-mix+split.dtsi"
+ * #include "ulcb-audio-graph-card.dtsi"
+ * #include "ulcb-audio-graph-card-mix+split.dtsi"
+ * #include "ulcb-audio-graph-card2-mix+split.dtsi"
+ */
+#include "ulcb-audio-graph-card2.dtsi"
diff --git a/arch/arm/dts/versal-mini-emmc0.dts b/arch/arm/dts/versal-mini-emmc0.dts
index bd685dd..60b1c0e 100644
--- a/arch/arm/dts/versal-mini-emmc0.dts
+++ b/arch/arm/dts/versal-mini-emmc0.dts
@@ -4,7 +4,7 @@
*
* (C) Copyright 2018-2019, Xilinx, Inc.
*
- * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
* Michal Simek <michal.simek@amd.com>
*/
diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts
index fbdcf5d..751cc38 100644
--- a/arch/arm/dts/versal-mini-emmc1.dts
+++ b/arch/arm/dts/versal-mini-emmc1.dts
@@ -4,7 +4,7 @@
*
* (C) Copyright 2018-2019, Xilinx, Inc.
*
- * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
* Michal Simek <michal.simek@amd.com>
*/
diff --git a/arch/arm/dts/versal-mini-ospi-stacked.dts b/arch/arm/dts/versal-mini-ospi-stacked.dts
new file mode 100644
index 0000000..f46125d
--- /dev/null
+++ b/arch/arm/dts/versal-mini-ospi-stacked.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI Quad Stacked DTS
+ *
+ * Copyright (C) 2018-2020 Xilinx, Inc.
+ */
+
+#include "versal-mini-ospi.dtsi"
+
+/ {
+ model = "Xilinx Versal MINI OSPI STACKED";
+};
+
+&ospi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
+ spi-rx-bus-width = <8>;
+};
diff --git a/arch/arm/dts/versal-mini-ospi.dtsi b/arch/arm/dts/versal-mini-ospi.dtsi
index 19caea7..1abe44f 100644
--- a/arch/arm/dts/versal-mini-ospi.dtsi
+++ b/arch/arm/dts/versal-mini-ospi.dtsi
@@ -4,7 +4,7 @@
*
* (C) Copyright 2018-2019, Xilinx, Inc.
*
- * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
* Michal Simek <michal.simek@amd.com>
*/
@@ -57,6 +57,7 @@
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <20000000>;
+ no-wp;
};
};
};
diff --git a/arch/arm/dts/versal-mini-qspi-parallel.dts b/arch/arm/dts/versal-mini-qspi-parallel.dts
new file mode 100644
index 0000000..8485cda
--- /dev/null
+++ b/arch/arm/dts/versal-mini-qspi-parallel.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI Quad Parallel DTS
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include "versal-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal MINI QSPI PARALLEL";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
+ spi-rx-bus-width = <4>;
+};
diff --git a/arch/arm/dts/versal-mini-qspi-stacked.dts b/arch/arm/dts/versal-mini-qspi-stacked.dts
new file mode 100644
index 0000000..54d4277
--- /dev/null
+++ b/arch/arm/dts/versal-mini-qspi-stacked.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI Quad Stacked DTS
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include "versal-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal MINI QSPI STACKED";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
+ spi-rx-bus-width = <4>;
+};
diff --git a/arch/arm/dts/versal-mini-qspi-x1-single.dts b/arch/arm/dts/versal-mini-qspi-x1-single.dts
new file mode 100644
index 0000000..4d459a1
--- /dev/null
+++ b/arch/arm/dts/versal-mini-qspi-x1-single.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI x1 Single DTS
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include "versal-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal MINI QSPI X1 SINGLE";
+};
+
+&flash0 {
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+};
diff --git a/arch/arm/dts/versal-mini-qspi-x1-stacked.dts b/arch/arm/dts/versal-mini-qspi-x1-stacked.dts
new file mode 100644
index 0000000..905dc77
--- /dev/null
+++ b/arch/arm/dts/versal-mini-qspi-x1-stacked.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI x1 Stacked DTS
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include "versal-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal MINI QSPI X1 STACKED";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+};
diff --git a/arch/arm/dts/versal-mini-qspi-x2-single.dts b/arch/arm/dts/versal-mini-qspi-x2-single.dts
new file mode 100644
index 0000000..d25ad7c
--- /dev/null
+++ b/arch/arm/dts/versal-mini-qspi-x2-single.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI x2 Single DTS
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include "versal-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal MINI QSPI X2 SINGLE";
+};
+
+&flash0 {
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+};
diff --git a/arch/arm/dts/versal-mini-qspi-x2-stacked.dts b/arch/arm/dts/versal-mini-qspi-x2-stacked.dts
new file mode 100644
index 0000000..0c9e740
--- /dev/null
+++ b/arch/arm/dts/versal-mini-qspi-x2-stacked.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI x2 Stacked DTS
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include "versal-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal MINI QSPI X2 STACKED";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+};
diff --git a/arch/arm/dts/versal-mini-qspi.dtsi b/arch/arm/dts/versal-mini-qspi.dtsi
index 2fec92c..9347ea3 100644
--- a/arch/arm/dts/versal-mini-qspi.dtsi
+++ b/arch/arm/dts/versal-mini-qspi.dtsi
@@ -4,7 +4,7 @@
*
* (C) Copyright 2018-2019, Xilinx, Inc.
*
- * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
* Michal Simek <michal.simek@amd.com>
*/
diff --git a/arch/arm/dts/versal-mini.dts b/arch/arm/dts/versal-mini.dts
index a213b74..844e384 100644
--- a/arch/arm/dts/versal-mini.dts
+++ b/arch/arm/dts/versal-mini.dts
@@ -4,7 +4,7 @@
*
* (C) Copyright 2019, Xilinx, Inc.
*
- * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
*/
/dts-v1/;
diff --git a/arch/arm/dts/versal-net-mini-ospi-stacked.dts b/arch/arm/dts/versal-net-mini-ospi-stacked.dts
new file mode 100644
index 0000000..4bc954a
--- /dev/null
+++ b/arch/arm/dts/versal-net-mini-ospi-stacked.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal NET OSPI Quad Stacked DTS
+ *
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ */
+
+#include "versal-net-mini-ospi.dtsi"
+
+/ {
+ model = "Xilinx Versal NET MINI OSPI STACKED";
+};
+
+&ospi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
+ spi-rx-bus-width = <8>;
+};
diff --git a/arch/arm/dts/versal-net-mini-ospi.dtsi b/arch/arm/dts/versal-net-mini-ospi.dtsi
index ce8e215..5d188db 100644
--- a/arch/arm/dts/versal-net-mini-ospi.dtsi
+++ b/arch/arm/dts/versal-net-mini-ospi.dtsi
@@ -72,6 +72,7 @@
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <20000000>;
+ no-wp;
};
};
};
diff --git a/arch/arm/dts/versal-net-mini-qspi-parallel.dts b/arch/arm/dts/versal-net-mini-qspi-parallel.dts
new file mode 100644
index 0000000..edc2311
--- /dev/null
+++ b/arch/arm/dts/versal-net-mini-qspi-parallel.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal NET QSPI Quad Parallel DTS
+ *
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ */
+
+#include "versal-net-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal NET MINI QSPI PARALLEL";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
+ spi-rx-bus-width = <4>;
+};
diff --git a/arch/arm/dts/versal-net-mini-qspi-stacked.dts b/arch/arm/dts/versal-net-mini-qspi-stacked.dts
new file mode 100644
index 0000000..920eed2
--- /dev/null
+++ b/arch/arm/dts/versal-net-mini-qspi-stacked.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal NET QSPI Quad Stacked DTS
+ *
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ */
+
+#include "versal-net-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal NET MINI QSPI STACKED";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
+ spi-rx-bus-width = <4>;
+};
diff --git a/arch/arm/dts/versal-net-mini-qspi-x1-single.dts b/arch/arm/dts/versal-net-mini-qspi-x1-single.dts
new file mode 100644
index 0000000..856c79c
--- /dev/null
+++ b/arch/arm/dts/versal-net-mini-qspi-x1-single.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal NET QSPI x1 Single DTS
+ *
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ */
+
+#include "versal-net-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal NET MINI QSPI X1 SINGLE";
+};
+
+&flash0 {
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+};
diff --git a/arch/arm/dts/versal-net-mini-qspi-x1-stacked.dts b/arch/arm/dts/versal-net-mini-qspi-x1-stacked.dts
new file mode 100644
index 0000000..5f74d98
--- /dev/null
+++ b/arch/arm/dts/versal-net-mini-qspi-x1-stacked.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal NET QSPI x1 Stacked DTS
+ *
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ */
+
+#include "versal-net-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal NET MINI QSPI X1 STACKED";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+};
diff --git a/arch/arm/dts/versal-net-mini-qspi-x2-single.dts b/arch/arm/dts/versal-net-mini-qspi-x2-single.dts
new file mode 100644
index 0000000..6ceaa24
--- /dev/null
+++ b/arch/arm/dts/versal-net-mini-qspi-x2-single.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal NET QSPI x2 Single DTS
+ *
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ */
+
+#include "versal-net-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal NET MINI QSPI X2 SINGLE";
+};
+
+&flash0 {
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+};
diff --git a/arch/arm/dts/versal-net-mini-qspi-x2-stacked.dts b/arch/arm/dts/versal-net-mini-qspi-x2-stacked.dts
new file mode 100644
index 0000000..5f4d0b5
--- /dev/null
+++ b/arch/arm/dts/versal-net-mini-qspi-x2-stacked.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal NET QSPI x2 Stacked DTS
+ *
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ */
+
+#include "versal-net-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal NET MINI QSPI X2 STACKED";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+};
diff --git a/arch/arm/dts/xilinx-versal-net-virt.dts b/arch/arm/dts/xilinx-versal-net-virt.dts
index c99257c..f5eca84 100644
--- a/arch/arm/dts/xilinx-versal-net-virt.dts
+++ b/arch/arm/dts/xilinx-versal-net-virt.dts
@@ -8,4 +8,10 @@
/dts-v1/;
/ {
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ bootscr-address = /bits/ 64 <0x20000000>;
+ };
+ };
};
diff --git a/arch/arm/dts/xilinx-versal-virt.dts b/arch/arm/dts/xilinx-versal-virt.dts
index 733e532..3ea3cb1 100644
--- a/arch/arm/dts/xilinx-versal-virt.dts
+++ b/arch/arm/dts/xilinx-versal-virt.dts
@@ -8,4 +8,10 @@
/dts-v1/;
/ {
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ bootscr-address = /bits/ 64 <0x20000000>;
+ };
+ };
};
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 8c6eafe..f8c786a 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -11,6 +11,13 @@
#size-cells = <1>;
compatible = "xlnx,zynq-7000";
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ bootscr-address = /bits/ 64 <0x3000000>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -299,15 +306,11 @@
compatible = "arm,pl353-nand-r2p1";
reg = <0 0 0x1000000>;
status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
};
nor0: flash@1,0 {
status = "disabled";
compatible = "cfi-flash";
reg = <1 0 0x2000000>;
- #address-cells = <1>;
- #size-cells = <1>;
};
};
diff --git a/arch/arm/dts/zynq-cc108.dts b/arch/arm/dts/zynq-cc108.dts
index dc942b0..593ca4a 100644
--- a/arch/arm/dts/zynq-cc108.dts
+++ b/arch/arm/dts/zynq-cc108.dts
@@ -55,7 +55,6 @@
&qspi {
status = "okay";
- is-dual = <0>;
num-cs = <1>;
flash@0 { /* 16 MB */
compatible = "n25q128a11", "jedec,spi-nor";
diff --git a/arch/arm/dts/zynq-cse-qspi-parallel.dts b/arch/arm/dts/zynq-cse-qspi-parallel.dts
new file mode 100644
index 0000000..afa6348
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-parallel.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE QSPI Quad Parallel DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+/ {
+ model = "Zynq CSE QSPI PARALLEL Board";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
+ spi-rx-bus-width = <4>;
+};
diff --git a/arch/arm/dts/zynq-cse-qspi-stacked.dts b/arch/arm/dts/zynq-cse-qspi-stacked.dts
new file mode 100644
index 0000000..47859f7
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-stacked.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE QSPI Quad Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+/ {
+ model = "Zynq CSE QSPI STACKED Board";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
+ spi-rx-bus-width = <4>;
+};
diff --git a/arch/arm/dts/zynq-cse-qspi-x1-single.dts b/arch/arm/dts/zynq-cse-qspi-x1-single.dts
new file mode 100644
index 0000000..c14fb42
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-x1-single.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE QSPI x1 Single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+/ {
+ model = "Zynq CSE QSPI X1 SINGLE Board";
+};
+
+&flash0 {
+ spi-rx-bus-width = <1>;
+};
diff --git a/arch/arm/dts/zynq-cse-qspi-x1-stacked.dts b/arch/arm/dts/zynq-cse-qspi-x1-stacked.dts
new file mode 100644
index 0000000..0f4d414
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-x1-stacked.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE QSPI x1 Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+/ {
+ model = "Zynq CSE QSPI X1 STACKED Board";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
+ spi-rx-bus-width = <1>;
+};
diff --git a/arch/arm/dts/zynq-cse-qspi-x2-single.dts b/arch/arm/dts/zynq-cse-qspi-x2-single.dts
new file mode 100644
index 0000000..11be063
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-x2-single.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE QSPI x2 Single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+/ {
+ model = "Zynq CSE QSPI X2 SINGLE Board";
+};
+
+&flash0 {
+ spi-rx-bus-width = <2>;
+};
diff --git a/arch/arm/dts/zynq-cse-qspi-x2-stacked.dts b/arch/arm/dts/zynq-cse-qspi-x2-stacked.dts
new file mode 100644
index 0000000..d1b42e9
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-x2-stacked.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE QSPI x2 Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+/ {
+ model = "Zynq CSE QSPI X2 STACKED Board";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
+ spi-rx-bus-width = <2>;
+};
diff --git a/arch/arm/dts/zynq-dlc20-rev1.0.dts b/arch/arm/dts/zynq-dlc20-rev1.0.dts
index d06838c..8d00737 100644
--- a/arch/arm/dts/zynq-dlc20-rev1.0.dts
+++ b/arch/arm/dts/zynq-dlc20-rev1.0.dts
@@ -66,7 +66,6 @@
&qspi {
bootph-all;
status = "okay";
- is-dual = <0>;
num-cs = <1>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
diff --git a/arch/arm/dts/zynq-minized.dts b/arch/arm/dts/zynq-minized.dts
index 3214ee4..96d2937 100644
--- a/arch/arm/dts/zynq-minized.dts
+++ b/arch/arm/dts/zynq-minized.dts
@@ -39,7 +39,6 @@
&qspi {
status = "okay";
- is-dual = <0>;
num-cs = <1>;
flash@0 {
compatible = "micron,m25p128";
diff --git a/arch/arm/dts/zynq-topic-miami.dts b/arch/arm/dts/zynq-topic-miami.dts
index 57cb86a..8307a2ef 100644
--- a/arch/arm/dts/zynq-topic-miami.dts
+++ b/arch/arm/dts/zynq-topic-miami.dts
@@ -33,7 +33,6 @@
&qspi {
bootph-all;
status = "okay";
- is-dual = <0>;
num-cs = <1>;
flash@0 {
compatible = "st,m25p80", "n25q256a", "jedec,spi-nor";
diff --git a/arch/arm/dts/zynq-topic-miamilite.dts b/arch/arm/dts/zynq-topic-miamilite.dts
index 366fd5b..af0bc7e 100644
--- a/arch/arm/dts/zynq-topic-miamilite.dts
+++ b/arch/arm/dts/zynq-topic-miamilite.dts
@@ -12,5 +12,4 @@
};
&qspi {
- is-dual = <1>;
};
diff --git a/arch/arm/dts/zynq-topic-miamiplus.dts b/arch/arm/dts/zynq-topic-miamiplus.dts
index df53886..36a7db3 100644
--- a/arch/arm/dts/zynq-topic-miamiplus.dts
+++ b/arch/arm/dts/zynq-topic-miamiplus.dts
@@ -21,5 +21,4 @@
};
&qspi {
- is-dual = <1>;
};
diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index 8d47f24..0106d7b 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -406,6 +406,31 @@
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 {
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 {
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 {
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
+ partition@c00000 {
+ label = "qspi-bitstream";
+ reg = <0xc00000 0x400000>;
+ };
+ };
};
};
diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts
index 03eb016..ceea982 100644
--- a/arch/arm/dts/zynq-zc706.dts
+++ b/arch/arm/dts/zynq-zc706.dts
@@ -309,13 +309,39 @@
&qspi {
bootph-all;
status = "okay";
- num-cs = <1>;
+ num-cs = <2>;
flash@0 {
compatible = "n25q128a11", "jedec,spi-nor";
- reg = <0x0>;
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 {
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 {
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 {
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
+ partition@c00000 {
+ label = "qspi-bitstream";
+ reg = <0xc00000 0x400000>;
+ };
+ };
};
};
diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts
index 17680d7..199384b 100644
--- a/arch/arm/dts/zynq-zc770-xm010.dts
+++ b/arch/arm/dts/zynq-zc770-xm010.dts
@@ -69,6 +69,31 @@
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 {
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 {
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 {
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
+ partition@c00000 {
+ label = "qspi-bitstream";
+ reg = <0xc00000 0x400000>;
+ };
+ };
};
};
diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts
index 0221434..f9a086f 100644
--- a/arch/arm/dts/zynq-zc770-xm011.dts
+++ b/arch/arm/dts/zynq-zc770-xm011.dts
@@ -49,6 +49,28 @@
&nfc0 {
status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nand@0 {
+ reg = <0>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "nand-fsbl-uboot";
+ reg = <0x0 0x1000000>;
+ };
+ partition@1000000 {
+ label = "nand-linux";
+ reg = <0x1000000 0x2000000>;
+ };
+ partition@3000000 {
+ label = "nand-rootfs";
+ reg = <0x3000000 0x200000>;
+ };
+ };
+ };
};
&smcc {
diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts
index 6e36634..24520e7 100644
--- a/arch/arm/dts/zynq-zc770-xm012.dts
+++ b/arch/arm/dts/zynq-zc770-xm012.dts
@@ -56,6 +56,31 @@
&nor0 {
status = "okay";
bank-width = <1>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "nor-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 {
+ label = "nor-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 {
+ label = "nor-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 {
+ label = "nor-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
+ partition@c00000 {
+ label = "nor-bitstream";
+ reg = <0xc00000 0x400000>;
+ };
+ };
};
&smcc {
diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts
index 21902fb..add7599 100644
--- a/arch/arm/dts/zynq-zc770-xm013.dts
+++ b/arch/arm/dts/zynq-zc770-xm013.dts
@@ -61,13 +61,39 @@
&qspi {
status = "okay";
- num-cs = <1>;
+ num-cs = <2>;
flash@0 {
compatible = "n25q128a11", "jedec,spi-nor";
- reg = <0x0>;
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 {
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 {
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 {
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
+ partition@c00000 {
+ label = "qspi-bitstream";
+ reg = <0xc00000 0x400000>;
+ };
+ };
};
};
diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
index 5320b4b..70bc418 100644
--- a/arch/arm/dts/zynq-zed.dts
+++ b/arch/arm/dts/zynq-zed.dts
@@ -55,8 +55,35 @@
flash@0 {
compatible = "spansion,s25fl256s1", "jedec,spi-nor";
reg = <0>;
- spi-max-frequency = <30000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <50000000>;
m25p,fast-read;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 {
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 {
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 {
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
+ partition@c00000 {
+ label = "qspi-bitstream";
+ reg = <0xc00000 0x400000>;
+ };
+ };
};
};
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 1ae8ea2..dd4569e 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -2,37 +2,14 @@
/*
* Clock specification for Xilinx ZynqMP
*
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
/ {
- fclk0: fclk0 {
- status = "okay";
- compatible = "xlnx,fclk";
- clocks = <&zynqmp_clk PL0_REF>;
- };
-
- fclk1: fclk1 {
- status = "okay";
- compatible = "xlnx,fclk";
- clocks = <&zynqmp_clk PL1_REF>;
- };
-
- fclk2: fclk2 {
- status = "okay";
- compatible = "xlnx,fclk";
- clocks = <&zynqmp_clk PL2_REF>;
- };
-
- fclk3: fclk3 {
- status = "okay";
- compatible = "xlnx,fclk";
- clocks = <&zynqmp_clk PL3_REF>;
- };
-
pss_ref_clk: pss_ref_clk {
bootph-all;
compatible = "fixed-clock";
@@ -253,10 +230,12 @@
&uart0 {
clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
+ assigned-clocks = <&zynqmp_clk UART0_REF>;
};
&uart1 {
clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
+ assigned-clocks = <&zynqmp_clk UART1_REF>;
};
&usb0 {
diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts
index 1b247bf..f737004 100644
--- a/arch/arm/dts/zynqmp-dlc21-revA.dts
+++ b/arch/arm/dts/zynqmp-dlc21-revA.dts
@@ -61,14 +61,14 @@
non-removable;
disable-wp;
bus-width = <8>;
- xlnx,mio_bank = <0>;
+ xlnx,mio-bank = <0>;
};
&sdhci1 { /* sd1 MIO45-51 cd in place */
status = "okay";
no-1-8-v;
disable-wp;
- xlnx,mio_bank = <1>;
+ xlnx,mio-bank = <1>;
};
&psgtr {
@@ -88,9 +88,13 @@
phy-handle = <&phy0>;
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
is-internal-pcspma;
- /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
- phy0: ethernet-phy@0 {
- reg = <0>;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
};
};
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index bf6ffb7..bf7569c 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -2,7 +2,8 @@
/*
* dts file for Xilinx Versal a2197 RevA System Controller
*
- * (C) Copyright 2019 - 2021, Xilinx, Inc.
+ * (C) Copyright 2019 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -460,10 +461,10 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
- si570_user1: clock-generator@5d { /* u205 */
+ si570_user1: clock-generator@5f { /* u205 */
#clock-cells = <0>;
compatible = "silabs,si570";
- reg = <0x5d>;
+ reg = <0x5f>;
temperature-stability = <50>;
factory-fout = <100000000>;
clock-frequency = <100000000>;
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revB.dts b/arch/arm/dts/zynqmp-e-a2197-00-revB.dts
new file mode 100644
index 0000000..8310df9
--- /dev/null
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revB.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal a2197 RevB System Controller
+ *
+ * (C) Copyright 2019 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include "zynqmp-e-a2197-00-revA.dts"
+
+/ {
+ model = "Versal System Controller on a2197 Eval board RevB"; /* VCK190/VMK180 */
+ compatible = "xlnx,zynqmp-e-a2197-00-revB", "xlnx,zynqmp-a2197-revB",
+ "xlnx,zynqmp-a2197", "xlnx,zynqmp";
+
+ /delete-node/ ina226-vcco-500;
+ /delete-node/ ina226-vcco-501;
+ /delete-node/ ina226-vcco-502;
+};
+
+&i2c0 {
+ i2c-mux@74 { /* u33 */
+ i2c@2 { /* PCIE_CLK */
+ /delete-node/ clock-generator@6c;
+ };
+ i2c@3 { /* PMBUS2_INA226 */
+ /delete-node/ ina226@42;
+ /delete-node/ ina226@43;
+ /delete-node/ ina226@44;
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
index d5cfc61..36a0db4 100644
--- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
@@ -81,10 +81,14 @@
phy-handle = <&phy0>;
phy-mode = "sgmii";
is-internal-pcspma;
- phy0: ethernet-phy@0 { /* marwell m88e1512 */
- reg = <0>;
- reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@0 { /* marwell m88e1512 */
+ reg = <0>;
+ reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
+ };
};
};
diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
index 97500b1..83b8a98 100644
--- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
@@ -71,12 +71,13 @@
&qspi {
status = "okay";
- is-dual = <1>;
+ num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
#address-cells = <1>;
#size-cells = <1>;
- reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
@@ -110,10 +111,14 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
- phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
- phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
- reg = <0>;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
+ phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
+ reg = <0>;
/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
+ };
};
};
@@ -360,25 +365,25 @@
#gpio-cells = <2>;
gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
"", "", "", "";
- gtr_sel0 {
+ gtr-sel0 {
gpio-hog;
gpios = <0 0>;
input; /* FIXME add meaning */
line-name = "sw4_1";
};
- gtr_sel1 {
+ gtr-sel1 {
gpio-hog;
gpios = <1 0>;
input; /* FIXME add meaning */
line-name = "sw4_2";
};
- gtr_sel2 {
+ gtr-sel2 {
gpio-hog;
gpios = <2 0>;
input; /* FIXME add meaning */
line-name = "sw4_3";
};
- gtr_sel3 {
+ gtr-sel3 {
gpio-hog;
gpios = <3 0>;
input; /* FIXME add meaning */
diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
index 3bdcf05..dd37b72 100644
--- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
@@ -67,12 +67,13 @@
&qspi {
status = "okay";
- is-dual = <1>;
+ num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
#address-cells = <1>;
#size-cells = <1>;
- reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
@@ -106,9 +107,13 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "sgmii";
- phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
- phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
- reg = <0>;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
+ phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
+ reg = <0>;
+ };
};
};
@@ -362,25 +367,25 @@
#gpio-cells = <2>;
gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
"", "", "", "";
- gtr_sel0 {
+ gtr-sel0 {
gpio-hog;
gpios = <0 0>;
input; /* FIXME add meaning */
line-name = "sw4_1";
};
- gtr_sel1 {
+ gtr-sel1 {
gpio-hog;
gpios = <1 0>;
input; /* FIXME add meaning */
line-name = "sw4_2";
};
- gtr_sel2 {
+ gtr-sel2 {
gpio-hog;
gpios = <2 0>;
input; /* FIXME add meaning */
line-name = "sw4_3";
};
- gtr_sel3 {
+ gtr-sel3 {
gpio-hog;
gpios = <3 0>;
input; /* FIXME add meaning */
diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
index 9a693a5..811ceba 100644
--- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
@@ -67,12 +67,13 @@
&qspi {
status = "okay";
- is-dual = <1>;
+ num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
#address-cells = <1>;
#size-cells = <1>;
- reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
@@ -106,9 +107,13 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "sgmii";
- phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
- phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
- reg = <0>;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
+ phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
+ reg = <0>;
+ };
};
};
@@ -356,25 +361,25 @@
#gpio-cells = <2>;
gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
"", "", "", "";
- gtr_sel0 {
+ gtr-sel0 {
gpio-hog;
gpios = <0 0>;
input; /* FIXME add meaning */
line-name = "sw4_1";
};
- gtr_sel1 {
+ gtr-sel1 {
gpio-hog;
gpios = <1 0>;
input; /* FIXME add meaning */
line-name = "sw4_2";
};
- gtr_sel2 {
+ gtr-sel2 {
gpio-hog;
gpios = <2 0>;
input; /* FIXME add meaning */
line-name = "sw4_3";
};
- gtr_sel3 {
+ gtr-sel3 {
gpio-hog;
gpios = <3 0>;
input; /* FIXME add meaning */
diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts
index 08ec2f7..02e80bd 100644
--- a/arch/arm/dts/zynqmp-mini-emmc0.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc0.dts
@@ -4,7 +4,7 @@
*
* (C) Copyright 2018, Xilinx, Inc.
*
- * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
*/
/dts-v1/;
diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts
index 905de08..ce1cdb2 100644
--- a/arch/arm/dts/zynqmp-mini-emmc1.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc1.dts
@@ -4,7 +4,7 @@
*
* (C) Copyright 2018, Xilinx, Inc.
*
- * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
*/
/dts-v1/;
diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts
index e5688fd..e0517cf 100644
--- a/arch/arm/dts/zynqmp-mini-nand.dts
+++ b/arch/arm/dts/zynqmp-mini-nand.dts
@@ -4,7 +4,7 @@
*
* (C) Copyright 2018, Xilinx, Inc.
*
- * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
* Michal Simek <michal.simek@amd.com>
*/
diff --git a/arch/arm/dts/zynqmp-mini-qspi-parallel.dts b/arch/arm/dts/zynqmp-mini-qspi-parallel.dts
new file mode 100644
index 0000000..728e822
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi-parallel.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZynqMP QSPI Quad Parallel DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynqmp-mini-qspi.dts"
+
+/ {
+ model = "ZynqMP MINI QSPI PARALLEL";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
+};
diff --git a/arch/arm/dts/zynqmp-mini-qspi-single.dts b/arch/arm/dts/zynqmp-mini-qspi-single.dts
new file mode 100644
index 0000000..0f9306e
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi-single.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZynqMP QSPI single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynqmp-mini-qspi.dts"
+
+/ {
+ model = "ZynqMP MINI QSPI SINGLE";
+};
diff --git a/arch/arm/dts/zynqmp-mini-qspi-stacked.dts b/arch/arm/dts/zynqmp-mini-qspi-stacked.dts
new file mode 100644
index 0000000..9a9541b
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi-stacked.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZynqMP QSPI Quad Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynqmp-mini-qspi.dts"
+
+/ {
+ model = "ZynqMP MINI QSPI STACKED";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
+};
diff --git a/arch/arm/dts/zynqmp-mini-qspi-x1-single.dts b/arch/arm/dts/zynqmp-mini-qspi-x1-single.dts
new file mode 100644
index 0000000..5af875c
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi-x1-single.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZynqMP QSPI x1 Single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynqmp-mini-qspi.dts"
+
+/ {
+ model = "ZynqMP MINI QSPI X1 SINGLE";
+};
+
+&flash0 {
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+};
diff --git a/arch/arm/dts/zynqmp-mini-qspi-x1-stacked.dts b/arch/arm/dts/zynqmp-mini-qspi-x1-stacked.dts
new file mode 100644
index 0000000..ebf890e
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi-x1-stacked.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZynqMP QSPI x1 Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynqmp-mini-qspi.dts"
+
+/ {
+ model = "ZynqMP MINI QSPI X1 STACKED";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+};
diff --git a/arch/arm/dts/zynqmp-mini-qspi-x2-single.dts b/arch/arm/dts/zynqmp-mini-qspi-x2-single.dts
new file mode 100644
index 0000000..a5ab315
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi-x2-single.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE QSPI x2 Single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynqmp-mini-qspi.dts"
+
+/ {
+ model = "ZynqMP MINI QSPI X2 SINGLE";
+};
+
+&flash0 {
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+};
diff --git a/arch/arm/dts/zynqmp-mini-qspi-x2-stacked.dts b/arch/arm/dts/zynqmp-mini-qspi-x2-stacked.dts
new file mode 100644
index 0000000..e234b76
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi-x2-stacked.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZynqMP QSPI x2 Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynqmp-mini-qspi.dts"
+
+/ {
+ model = "ZynqMP MINI QSPI X2 STACKED";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+};
diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts
index fc0a2e8..ee8be53 100644
--- a/arch/arm/dts/zynqmp-mini-qspi.dts
+++ b/arch/arm/dts/zynqmp-mini-qspi.dts
@@ -4,7 +4,7 @@
*
* (C) Copyright 2015 - 2020, Xilinx, Inc.
*
- * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
* Michal Simek <michal.simek@amd.com>
*/
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso
new file mode 100644
index 0000000..197dc25
--- /dev/null
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP System Controller X-PRC-01 revA (SE1)
+ *
+ * (C) Copyright 2019 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/{
+ compatible = "xlnx,zynqmp-x-prc-01-revA", "xlnx,zynqmp-x-prc-01";
+
+ fragment@0 {
+ target = <&dc_i2c>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ x_prc_eeprom: eeprom@52 { /* u120 */
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+
+ x_prc_tca9534: gpio@22 { /* u121 tca9534 */
+ compatible = "nxp,pca9534";
+ reg = <0x22>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
+ "", "", "", "";
+ gtr-sel0 {
+ gpio-hog;
+ gpios = <0 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_1";
+ };
+ gtr-sel1 {
+ gpio-hog;
+ gpios = <1 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_2";
+ };
+ gtr-sel2 {
+ gpio-hog;
+ gpios = <2 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_3";
+ };
+ gtr-sel3 {
+ gpio-hog;
+ gpios = <3 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_4";
+ };
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&i2c1>; /* Must be enabled via J242 */
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom_versal: eeprom@51 { /* u116 */
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso
new file mode 100644
index 0000000..8eb6e40
--- /dev/null
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2)
+ *
+ * (C) Copyright 2019 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/{
+ compatible = "xlnx,zynqmp-x-prc-02-revA", "xlnx,zynqmp-x-prc-02";
+
+ fragment@0 {
+ target = <&dc_i2c>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ x_prc_eeprom: eeprom@52 { /* u16 */
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+
+ x_prc_tca9534: gpio@22 { /* u17 tca9534 */
+ compatible = "nxp,pca9534";
+ reg = <0x22>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
+ "", "", "", "";
+ gtr-sel0 {
+ gpio-hog;
+ gpios = <0 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_1";
+ };
+ gtr-sel1 {
+ gpio-hog;
+ gpios = <1 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_2";
+ };
+ gtr-sel2 {
+ gpio-hog;
+ gpios = <2 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_3";
+ };
+ gtr-sel3 {
+ gpio-hog;
+ gpios = <3 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_4";
+ };
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&i2c1>; /* Must be enabled via J242 */
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom_versal: eeprom@51 { /* u12 */
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso
new file mode 100644
index 0000000..af7a3ce
--- /dev/null
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3)
+ *
+ * (C) Copyright 2019 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/{
+ compatible = "xlnx,zynqmp-x-prc-03-revA", "xlnx,zynqmp-x-prc-03";
+
+ fragment@0 {
+ target = <&dc_i2c>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ x_prc_eeprom: eeprom@52 { /* u1 */
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+
+ x_prc_tca9534: gpio@22 { /* u3 tca9534 */
+ compatible = "nxp,pca9534";
+ reg = <0x22>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
+ "", "", "", "";
+ gtr-sel0 {
+ gpio-hog;
+ gpios = <0 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_1";
+ };
+ gtr-sel1 {
+ gpio-hog;
+ gpios = <1 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_2";
+ };
+ gtr-sel2 {
+ gpio-hog;
+ gpios = <2 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_3";
+ };
+ gtr-sel3 {
+ gpio-hog;
+ gpios = <3 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_4";
+ };
+ };
+ x_prc_si5338: clock-generator@70 { /* U9 */
+ compatible = "silabs,si5338";
+ reg = <0x70>; /* FIXME */
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&i2c1>; /* Must be enabled via J90/J91 */
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom_versal: eeprom@51 { /* u2 */
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso
new file mode 100644
index 0000000..29a6c2a
--- /dev/null
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4)
+ *
+ * (C) Copyright 2019 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/{
+ compatible = "xlnx,zynqmp-x-prc-04-revA", "xlnx,zynqmp-x-prc-04";
+
+ fragment@0 {
+ target = <&dc_i2c>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ x_prc_eeprom: eeprom@52 { /* u120 */
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+
+ x_prc_tca9534: gpio@22 { /* u121 tca9534 */
+ compatible = "nxp,pca9534";
+ reg = <0x22>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
+ "", "", "", "";
+ gtr-sel0 {
+ gpio-hog;
+ gpios = <0 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_1";
+ };
+ gtr-sel1 {
+ gpio-hog;
+ gpios = <1 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_2";
+ };
+ gtr-sel2 {
+ gpio-hog;
+ gpios = <2 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_3";
+ };
+ gtr-sel3 {
+ gpio-hog;
+ gpios = <3 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_4";
+ };
+ };
+
+ si570_gem_tsu: clock-generator@5d { /* u164 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>; /* FIXME */
+ clock-frequency = <300000000>;
+ clock-output-names = "si570_gem_tsu_clk";
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&i2c1>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom_versal: eeprom@51 { /* u153 */
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso
new file mode 100644
index 0000000..6ddf18c
--- /dev/null
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5)
+ *
+ * (C) Copyright 2019 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/{
+ compatible = "xlnx,zynqmp-x-prc-05-revA", "xlnx,zynqmp-x-prc-05";
+
+ fragment@0 {
+ target = <&dc_i2c>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ x_prc_eeprom: eeprom@52 { /* u120 */
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+
+ x_prc_tca9534: gpio@22 { /* u121 tca9534 */
+ compatible = "nxp,pca9534";
+ reg = <0x22>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
+ "", "", "", "";
+ gtr-sel0 {
+ gpio-hog;
+ gpios = <0 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_1";
+ };
+ gtr-sel1 {
+ gpio-hog;
+ gpios = <1 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_2";
+ };
+ gtr-sel2 {
+ gpio-hog;
+ gpios = <2 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_3";
+ };
+ gtr-sel3 {
+ gpio-hog;
+ gpios = <3 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_4";
+ };
+ };
+
+ si570_gem_tsu: clock-generator@5d { /* u164 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>; /* FIXME */
+ clock-frequency = <300000000>;
+ clock-output-names = "si570_gem_tsu_clk";
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&i2c1>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom_versal: eeprom@51 { /* u153 */
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
index 16691a8..c456c37 100644
--- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
@@ -91,9 +91,13 @@
phy-handle = <&phy0>;
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
is-internal-pcspma;
- /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
- phy0: ethernet-phy@0 {
- reg = <0>;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
};
};
@@ -423,25 +427,25 @@
#gpio-cells = <2>;
gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
"", "", "", "";
- gtr_sel0 {
+ gtr-sel0 {
gpio-hog;
gpios = <0 0>;
input; /* FIXME add meaning */
line-name = "sw4_1";
};
- gtr_sel1 {
+ gtr-sel1 {
gpio-hog;
gpios = <1 0>;
input; /* FIXME add meaning */
line-name = "sw4_2";
};
- gtr_sel2 {
+ gtr-sel2 {
gpio-hog;
gpios = <2 0>;
input; /* FIXME add meaning */
line-name = "sw4_3";
};
- gtr_sel3 {
+ gtr-sel3 {
gpio-hog;
gpios = <3 0>;
input; /* FIXME add meaning */
diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts
new file mode 100644
index 0000000..e0b554c
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-revB.dts
@@ -0,0 +1,430 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP Generic System Controller
+ *
+ * (C) Copyright 2021 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "ZynqMP Generic System Controller";
+ compatible = "xlnx,zynqmp-sc-revB", "xlnx,zynqmp-sc", "xlnx,zynqmp";
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ nvmem0 = &eeprom;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ spi0 = &qspi;
+ spi1 = &spi0;
+ spi2 = &spi1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ fwuen {
+ label = "sw16";
+ gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_MISC>;
+ wakeup-source;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ ds40-led {
+ label = "heartbeat";
+ gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ ds44-led {
+ label = "status";
+ gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ si5332_2: si5332_2 { /* u42 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ pwm-fan {
+ compatible = "pwm-fan";
+ status = "okay";
+ pwms = <&ttc0 2 40000 1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
+ "QSPI_CS_B", "", "LED1", "LED2", "", /* 5 - 9 */
+ "", "ZU4_TRIGGER", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
+ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
+ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "I2C1_SCL", /* 20 - 24 */
+ "I2C1_SDA", "UART0_RXD", "UART0_TXD", "", "", /* 25 - 29 */
+ "", "", "", "", "I2C0_SCL", /* 30 - 34 */
+ "I2C0_SDA", "UART1_TXD", "UART1_RXD", "GEM_TX_CLK", "GEM_TX_D0", /* 35 - 39 */
+ "GEM_TX_D1", "GEM_TX_D2", "GEM_TX_D3", "GEM_TX_CTL", "GEM_RX_CLK", /* 40 - 44 */
+ "GEM_RX_D0", "GEM_RX_D1", "GEM_RX_D2", "GEM_RX_D3", "GEM_RX_CTL", /* 45 - 49 */
+ "GEM_MDC", "GEM_MDIO", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
+ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
+ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
+ "", "", "", "", "", /* 65 - 69 */
+ "", "", "", "", "", /* 70 - 74 */
+ "", "", "ETH_RESET_B", /* 75 - 77, MIO end and EMIO start */
+ "", "", /* 78 - 79 */
+ "", "", "", "", "", /* 80 - 84 */
+ "", "", "", "", "", /* 85 -89 */
+ "", "", "", "", "", /* 90 - 94 */
+ "", "", "", "", "", /* 95 - 99 */
+ "", "", "", "", "", /* 100 - 104 */
+ "", "", "", "", "", /* 105 - 109 */
+ "", "", "", "", "", /* 110 - 114 */
+ "", "", "", "", "", /* 115 - 119 */
+ "", "", "", "", "", /* 120 - 124 */
+ "", "", "", "", "", /* 125 - 129 */
+ "", "", "", "", "", /* 130 - 134 */
+ "", "", "", "", "", /* 135 - 139 */
+ "", "", "", "", "", /* 140 - 144 */
+ "", "", "", "", "", /* 145 - 149 */
+ "", "", "", "", "", /* 150 - 154 */
+ "", "", "", "", "", /* 155 - 159 */
+ "", "", "", "", "", /* 160 - 164 */
+ "", "", "", "", "", /* 165 - 169 */
+ "", "", "", ""; /* 170 - 173 */
+};
+
+&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem1_default>;
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@1 {
+ #phy-cells = <1>;
+ compatible = "ethernet-phy-id2000.a231";
+ reg = <1>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <100>;
+ reset-deassert-us = <280>;
+ };
+ };
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+&i2c1 { /* i2c1 MIO 24-25 */
+ status = "okay";
+ bootph-all;
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ /* Use for storing information about SC board */
+ eeprom: eeprom@54 { /* u34 - m24128 16kB */
+ compatible = "st,24c128", "atmel,24c128";
+ reg = <0x54>; /* & 0x5c */
+ bootph-all;
+ };
+};
+
+/* USB 3.0 only */
+&psgtr {
+ status = "okay";
+ /* nc, nc, usb3 */
+ clocks = <&si5332_2>;
+ clock-names = "ref2";
+};
+
+&qspi { /* MIO 0-5 */
+ status = "okay";
+ /* QSPI should also have PINCTRL setup */
+ flash@0 {
+ compatible = "mt25qu512a", "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <40000000>; /* 40MHz */
+ partition@0 {
+ label = "Image Selector";
+ reg = <0x0 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition@80000 {
+ label = "Image Selector Golden";
+ reg = <0x80000 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition@100000 {
+ label = "Persistent Register";
+ reg = <0x100000 0x20000>; /* 128KB */
+ };
+ partition@120000 {
+ label = "Persistent Register Backup";
+ reg = <0x120000 0x20000>; /* 128KB */
+ };
+ partition@140000 {
+ label = "Open_1";
+ reg = <0x140000 0xC0000>; /* 768KB */
+ };
+ partition@200000 {
+ label = "Image A (FSBL, PMU, ATF, U-Boot)";
+ reg = <0x200000 0xD00000>; /* 13MB */
+ };
+ partition@f00000 {
+ label = "ImgSel Image A Catch";
+ reg = <0xF00000 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition@f80000 {
+ label = "Image B (FSBL, PMU, ATF, U-Boot)";
+ reg = <0xF80000 0xD00000>; /* 13MB */
+ };
+ partition@1c80000 {
+ label = "ImgSel Image B Catch";
+ reg = <0x1C80000 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition@1d00000 {
+ label = "Open_2";
+ reg = <0x1D00000 0x100000>; /* 1MB */
+ };
+ partition@1e00000 {
+ label = "Recovery Image";
+ reg = <0x1E00000 0x200000>; /* 2MB */
+ read-only;
+ lock;
+ };
+ partition@2000000 {
+ label = "Recovery Image Backup";
+ reg = <0x2000000 0x200000>; /* 2MB */
+ read-only;
+ lock;
+ };
+ partition@2200000 {
+ label = "U-Boot storage variables";
+ reg = <0x2200000 0x20000>; /* 128KB */
+ };
+ partition@2220000 {
+ label = "U-Boot storage variables backup";
+ reg = <0x2220000 0x20000>; /* 128KB */
+ };
+ partition@2240000 {
+ label = "SHA256";
+ reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
+ read-only;
+ lock;
+ };
+ partition@2280000 {
+ label = "Secure OS Storage";
+ reg = <0x2280000 0x20000>; /* 128KB */
+ };
+ partition@22A0000 {
+ label = "User";
+ reg = <0x22A0000 0x1d60000>; /* 29.375 MB */
+ };
+ };
+};
+
+&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */
+ status = "okay";
+ non-removable;
+ disable-wp;
+ bus-width = <8>;
+ xlnx,mio-bank = <0>;
+};
+
+&ttc0 {
+ status = "okay";
+ #pwm-cells = <3>;
+};
+
+&uart1 { /* uart0 MIO36-37 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+};
+
+&pinctrl0 { /* required by spec */
+ status = "okay";
+
+ pinctrl_uart1_default: uart1-default {
+ conf {
+ groups = "uart1_9_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO37";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO36";
+ bias-disable;
+ };
+
+ mux {
+ groups = "uart1_9_grp";
+ function = "uart1";
+ };
+ };
+
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_8_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_8_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_34_grp", "gpio0_35_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_34_grp", "gpio0_35_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ conf {
+ groups = "i2c1_6_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "i2c1_6_grp";
+ function = "i2c1";
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ conf {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ function = "gpio0";
+ };
+ };
+
+ pinctrl_gem1_default: gem1-default {
+ conf {
+ groups = "ethernet1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO44", "MIO46", "MIO48";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-bootstrap {
+ pins = "MIO45", "MIO47", "MIO49";
+ bias-disable;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO38", "MIO39", "MIO40",
+ "MIO41", "MIO42", "MIO43";
+ bias-disable;
+ low-power-enable;
+ };
+
+ conf-mdio {
+ groups = "mdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-mdio {
+ function = "mdio1";
+ groups = "mdio1_0_grp";
+ };
+
+ mux {
+ function = "ethernet1";
+ groups = "ethernet1_0_grp";
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-sc-revC.dts b/arch/arm/dts/zynqmp-sc-revC.dts
new file mode 100644
index 0000000..530a4a5
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-revC.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP Generic System Controller
+ *
+ * Copyright (C) 2021 - 2022, Xilinx, Inc.
+ * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include "zynqmp-sc-revB.dts"
+
+/ {
+ model = "ZynqMP Generic System Controller";
+ compatible = "xlnx,zynqmp-sc-revC", "xlnx,zynqmp-sc", "xlnx,zynqmp";
+};
+
+&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */
+ /delete-node/ mdio;
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@1 { /* ADI1300 */
+ #phy-cells = <1>;
+ compatible = "ethernet-phy-id0283.bc30";
+ reg = <1>;
+ adi,rx-internal-delay-ps = <2400>;
+ adi,tx-internal-delay-ps = <2400>;
+ adi,fifo-depth-bits = <8>;
+ reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10>;
+ reset-deassert-us = <5000>;
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-sc-vek280-revA.dtso b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso
new file mode 100644
index 0000000..3320bbc
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VEK280 revA
+ *
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-vek280-revA",
+ "xlnx,zynqmp-vek280", "xlnx,zynqmp";
+
+ vc7_xin: vc7-xin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6416_u233: gpio@20 { /* u233 */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "", "", "SFP_MOD_ABS", "SFP_TX_DISABLE", /* 0 - 3 */
+ "PMBUS2_INA226_ALERT", "", "", "", /* 4 - 7 */
+ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */
+ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@74 { /* u33 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ pmbus_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* On connector J325 */
+ ir35215_46: pmic@46 { /* IR35215 - u152 */
+ compatible = "infineon,ir35215";
+ reg = <0x46>; /* i2c addr - 0x16 */
+ };
+ irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
+ compatible = "infineon,irps5401";
+ reg = <0x47>; /* i2c addr 0x17 */
+ };
+ irps5401_48: pmic@48 { /* IRPS5401 - u279 */
+ compatible = "infineon,irps5401";
+ reg = <0x48>; /* i2c addr 0x18 */
+ };
+ ir38064_49: regulator@49 { /* IR38064 - u295 */
+ compatible = "infineon,ir38064";
+ reg = <0x49>; /* i2c addr 0x19 */
+ };
+ irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
+ compatible = "infineon,irps5401";
+ reg = <0x4c>; /* i2c addr 0x1c */
+ };
+ irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
+ compatible = "infineon,irps5401";
+ reg = <0x4d>; /* i2c addr 0x1d */
+ };
+ ir38060_4e: regulator@4e { /* IR38060 - u282 */
+ compatible = "infineon,ir38060";
+ reg = <0x4e>; /* i2c addr 0x1e */
+ };
+ };
+ pmbus1_ina226_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* alerts coming to u233 and SC */
+ vccint: ina226@40 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <500>; /* r440 */
+ };
+ vcc_soc: ina226@41 { /* u161 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <500>; /* r1702 */
+ };
+ vcc_pmc: ina226@42 { /* u163 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>; /* r382 */
+ };
+ vcc_ram: ina226@43 { /* u355 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>; /* r2417 */
+ };
+ vcc_pslp: ina226@44 { /* u165 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>; /* r1830 */
+ };
+ vcc_psfp: ina226@45 { /* u260 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>; /* r2386 */
+ };
+ vcco_hdio: ina226@46 { /* u356 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>; /* r2392 */
+ };
+ };
+ i2c@2 { /* NC */ /* FIXME maybe remove */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ pmbus2_ina226_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* alerts coming to u233 and SC */
+ vccaux: ina226@40 { /* u166 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>; /* r2384 */
+ };
+ vccaux_pmc: ina226@41 { /* u168 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>; /* r2000 */
+ };
+ mgtavcc: ina226@42 { /* u265 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>; /* r1829 */
+ };
+ vcc1v5: ina226@43 { /* u264 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>; /* r2397 */
+ };
+ vcco_mio: ina226@45 { /* u172 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>; /* r2401 */
+ };
+ mgtavtt: ina226@46 { /* u188 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <500>; /* r1384 */
+ };
+ vcco_502: ina226@47 { /* u174 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>; /* r1994 */
+ };
+ mgtvccaux: ina226@48 { /* u176 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>; /* r2384 */
+ };
+ vcc1v1_lp4: ina226@49 { /* u306 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <500>; /* r2064 */
+ };
+ vadj_fmc: ina226@4a { /* u281 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <5000>; /* r2031 */
+ };
+ lpdmgtyavcc: ina226@4b { /* u177 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>; /* r2004 */
+ };
+ lpdmgtyavtt: ina226@4c { /* u309 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <5000>; /* r1229 */
+ };
+ lpdmgtyvccaux: ina226@4d { /* u234 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <5000>; /* r1679 */
+ };
+ };
+ i2c@4 { /* NC */ /* FIXME maybe remove */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ rc21008a_gtclk1: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* connector j374 */
+ /* rc21008a at 0x9 u299 */
+ vc7: clock-generator@9 {
+ compatible = "renesas,rc21008a";
+ reg = <0x9>;
+ #clock-cells = <1>;
+ clocks = <&vc7_xin>;
+ clock-names = "xin";
+ };
+ };
+ fmcp1_iic: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* to j51c */
+ };
+ sfp: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* sfp+ connector J376 */
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-sc-vek280-revB.dtso b/arch/arm/dts/zynqmp-sc-vek280-revB.dtso
new file mode 100644
index 0000000..a3983f3
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-vek280-revB.dtso
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VEK280 revB
+ *
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include "zynqmp-sc-vek280-revA.dtso"
+
+&{/} {
+ compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB",
+ "xlnx,zynqmp-vek280", "xlnx,zynqmp";
+};
diff --git a/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso b/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso
new file mode 100644
index 0000000..2ce6937
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VHK158 revA
+ *
+ * (C) Copyright 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "xlnx,zynqmp-sc-vhk158-revA", "xlnx,zynqmp-vhk158-revA",
+ "xlnx,zynqmp-vhk158", "xlnx,zynqmp";
+
+ vc7_xin: vc7-xin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6416_u233: gpio@20 { /* u233 */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "", "", "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", /* 0 - 3 */
+ "PMBUS2_INA226_ALERT", "", "", "", /* 4 - 7 */
+ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */
+ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@74 { /* u33 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ pmbus_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* On connector J325 */
+ ir38064_41: regulator@41 { /* IR38064 - u294 */
+ compatible = "infineon,ir38064";
+ reg = <0x41>; /* i2c addr 0x11 */
+ };
+ irps5401_45: pmic5401@45 { /* IRPS5401 - u280 */
+ compatible = "infineon,irps5401";
+ reg = <0x45>; /* i2c addr 0x15 */
+ };
+ ir35221_46: pmic@46 { /* IR35221 - u152 */
+ compatible = "infineon,ir35221";
+ reg = <0x46>; /* i2c addr - 0x16 */
+ };
+ irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
+ compatible = "infineon,irps5401";
+ reg = <0x47>; /* i2c addr 0x17 */
+ };
+ irps5401_48: regulator@48 { /* IRPS5401 - u279 */
+ compatible = "infineon,irps5401";
+ reg = <0x48>; /* i2c addr 0x18 */
+ };
+ ir38164_49: regulator@49 { /* IR38164 - u295 */
+ compatible = "infineon,ir38164";
+ reg = <0x49>; /* i2c addr 0x19 */
+ };
+ ir38060_4a: regulator@4a { /* IR38060 - u259 */
+ compatible = "infineon,ir38164";
+ reg = <0x4a>; /* i2c addr 0x1a */
+ };
+ irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
+ compatible = "infineon,irps5401";
+ reg = <0x4c>; /* i2c addr 0x1c */
+ };
+ irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
+ compatible = "infineon,irps5401";
+ reg = <0x4d>; /* i2c addr 0x1d */
+ };
+ ir38060_4e: regulator@4e { /* IR38060 - u282 */
+ compatible = "infineon,ir38164";
+ reg = <0x4e>; /* i2c addr 0x1e */
+ };
+ };
+ pmbus1_ina226_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME check alerts coming to SC */
+ vccint: ina226@40 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <500>; /* R440 */
+ };
+ vcc_soc: ina226@41 { /* u161 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <500>; /* R1702 */
+ };
+ vcc_pmc: ina226@42 { /* u163 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>; /* R382 */
+ };
+ vcc_ram: ina226@43 { /* u5 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <500>; /* R121 */
+ };
+ vcc_pslp: ina226@44 { /* u165 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>; /* R1830 */
+ };
+ vcc_psfp: ina226@45 { /* u260 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>; /* R1834 */
+ };
+ vcco_hbm: ina226@46 { /* u164 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <500>; /* R2056 */
+ };
+ vcc_hbm: ina226@47 { /* u307 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <500>; /* R2068 */
+ };
+ vccaux_hbm: ina226@48 { /* u308 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>; /* R2019 */
+ };
+ };
+ i2c@2 { /* NC */ /* FIXME maybe remove */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ pmbus2_ina226_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* FIXME check alerts coming to SC */
+ vccaux: ina226@40 { /* u166 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>; /* R2060 */
+ };
+ vccaux_pmc: ina226@41 { /* u168 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <500>; /* R2000 */
+ };
+ mgtavcc: ina226@42 { /* u265 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <500>; /* R1829 */
+ };
+ vcc1v5: ina226@43 { /* u264 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <500>; /* R1221 */
+ };
+ vcco_mio: ina226@45 { /* u172 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <500>; /* R2015 */
+ };
+ mgtavtt: ina226@46 { /* u188 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <500>; /* R1384 */
+ };
+ vcco_502: ina226@47 { /* u174 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <500>; /* R1994 */
+ };
+ mgtvccaux: ina226@48 { /* u176 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <500>; /* R1232 */
+ };
+ vcc1v2_rdimm: ina226@49 { /* u306 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <500>; /* R2064 */
+ };
+ vadj_fmc: ina226@4a { /* u281 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <5000>; /* R2031 */
+ };
+ lpdmgtyavcc: ina226@4b { /* u177 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <500>; /* R2004 */
+ };
+ lpdmgtyavtt: ina226@4c { /* u309 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <500>; /* R1229 */
+ };
+ lpdmgtyvccaux: ina226@4d { /* u234 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <500>; /* R1679 */
+ };
+ };
+ i2c@4 { /* NC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ rc21008a_gtclk1: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ vc7_1: clock-generator@9 {
+ compatible = "renesas,rc21008a";
+ clock-output-names = "rc21008a-0";
+ reg = <0x9>;
+ #clock-cells = <1>;
+ clocks = <&vc7_xin>;
+ clock-names = "xin";
+ };
+ /* i2c@9 - U299 */
+ };
+ rc21008a_gtclk2: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ vc7_2: clock-generator@9 {
+ compatible = "renesas,rc21008a";
+ clock-output-names = "rc21008a-1";
+ reg = <0x9>;
+ #clock-cells = <1>;
+ clocks = <&vc7_xin>;
+ clock-names = "xin";
+ };
+ /* i2c@9 - U300 */
+ };
+ sync_8a34001: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* U219 - i2c address UNKNOWN */
+ };
+ };
+};
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-mux@74 { /* u35 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ ddr4_dimm0: i2c@0 { /* wired but NC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ fmcp1_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME connection to Samtec J51C */
+ /* expected eeprom 0x50 SE cards */
+ };
+ qsfp1_i2c: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* J350 connector */
+ };
+ qsfp2_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* J351 connector */
+ };
+ qsfp3_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* J352 connector */
+ };
+ qsfp4_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* J353 connector */
+ };
+ qsfpdd_i2c: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* J1/J2 connectors */
+ };
+ ddr4_dimm1: i2c@7 { /* wired but NC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso
new file mode 100644
index 0000000..5333767
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso
@@ -0,0 +1,460 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2)
+ *
+ * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ compatible = "xlnx,zynqmp-sc-vn-p-b2197-revA",
+ "xlnx,zynqmp-sc-vn-p-b2197", "xlnx,zynqmp";
+
+ aliases {
+ nvmem1 = &x_prc_eeprom;
+ };
+
+ ina226-u1700 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcc_ram_ina 0>, <&vcc_ram_ina 1>, <&vcc_ram_ina 2>;
+ };
+ ina226-u1732 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcc_lpd_ina 0>, <&vcc_lpd_ina 1>, <&vcc_lpd_ina 2>;
+ };
+ ina226-u1733 {
+ compatible = "iio-hwmon";
+ io-channels = <&vccaux_ina 0>, <&vccaux_ina 1>, <&vccaux_ina 2>;
+ };
+ ina226-u1736 {
+ compatible = "iio-hwmon";
+ io-channels = <&vccaux_lpd_ina 0>, <&vccaux_lpd_ina 1>, <&vccaux_lpd_ina 2>;
+ };
+ ina226-u1737 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcco_500_ina 0>, <&vcco_500_ina 1>, <&vcco_500_ina 2>;
+ };
+ ina226-u1739 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcco_501_ina 0>, <&vcco_501_ina 1>, <&vcco_501_ina 2>;
+ };
+ ina226-u1741 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcco_502_ina 0>, <&vcco_502_ina 1>, <&vcco_502_ina 2>;
+ };
+ ina226-u1743 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcco_503_ina 0>, <&vcco_503_ina 1>, <&vcco_503_ina 2>;
+ };
+ ina226-u1745 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcco_700_ina 0>, <&vcco_700_ina 1>, <&vcco_700_ina 2>;
+ };
+ ina226-u1747 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcco_706_ina 0>, <&vcco_706_ina 1>, <&vcco_706_ina 2>;
+ };
+ ina226-u1750 {
+ compatible = "iio-hwmon";
+ io-channels = <>yp_avcc_ina 0>, <>yp_avcc_ina 1>, <>yp_avcc_ina 2>;
+ };
+ ina226-u1752 {
+ compatible = "iio-hwmon";
+ io-channels = <>yp_avtt_ina 0>, <>yp_avtt_ina 1>, <>yp_avtt_ina 2>;
+ };
+ ina226-u1754 {
+ compatible = "iio-hwmon";
+ io-channels = <>yp_avccaux_ina 0>, <>yp_avccaux_ina 1>, <>yp_avccaux_ina 2>;
+ };
+ ina226-u1756 {
+ compatible = "iio-hwmon";
+ io-channels = <>m_avcc_ina 0>, <>m_avcc_ina 1>, <>m_avcc_ina 2>;
+ };
+ ina226-u1758 {
+ compatible = "iio-hwmon";
+ io-channels = <>m_avtt_ina 0>, <>m_avtt_ina 1>, <>m_avtt_ina 2>;
+ };
+ ina226-u1760 {
+ compatible = "iio-hwmon";
+ io-channels = <>m_avccaux_ina 0>, <>m_avccaux_ina 1>, <>m_avccaux_ina 2>;
+ };
+
+ /* sc_vpk180_axi_iic_0_0: i2c@80050000 - UNUSED NOW */ /* SI5332 */
+
+ /* Connect to J212G pin G29/G30 - sysmon connector */
+ /* sc_vpk180_axi_iic_1_0: i2c@80060000 */ /* SYSMON */
+
+ /* FIXME Fan control via u1702 - max6643 and mux via J1703 - not SW controllable - via EMIO */
+};
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* u97 eeprom at 0x54 described in sc-revB - WP protection via BOARD_EEPROM_WP - J1801 */
+ /* DC/SE eeprom at 0x52 */
+ x_prc_eeprom: eeprom@52 { /* u4 - DC card identification - possible WP */
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ bootph-all;
+ };
+
+ x_prc_tca9534: gpio@22 { /* u5 */
+ compatible = "nxp,pca9534";
+ reg = <0x22>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "xprc_sw_1", "xprc_sw_2", "xprc_sw_3", "xprc_sw_4",
+ "", "", "", "";
+ gtr-sel0 {
+ gpio-hog;
+ gpios = <0 0>;
+ input; /* FIXME add meaning */
+ line-name = "xprc_sw_1";
+ };
+ gtr-sel1 {
+ gpio-hog;
+ gpios = <1 0>;
+ input; /* FIXME add meaning */
+ line-name = "xprc_sw_1";
+ };
+ gtr-sel2 {
+ gpio-hog;
+ gpios = <2 0>;
+ input; /* FIXME add meaning */
+ line-name = "xprc_sw_1";
+ };
+ gtr-sel3 {
+ gpio-hog;
+ gpios = <3 0>;
+ input; /* FIXME add meaning */
+ line-name = "xprc_sw_1";
+ };
+ };
+
+ /* FMC eeproms at 0x50/0x51 */
+ /* via j3/j5 to 0x68 to u32/9FGV1006C
+
+ /* i2c_main_1 - u147 - j157 - disable translation, add 8 */
+ /* J1 - OE for u43@55 + 8 - 161,132813MHz - QSFP56G_0 */
+ qsfp56g_0_clk: clock-controller@5d {
+ compatible = "renesas,proxo-xp";
+ reg = <0x5d>;
+ #clock-cells = <0>;
+ clock-output-names = "qsfp56g_0_clk";
+ };
+
+ /* J2 - OE for u41@57 + 8 - 322,265625MHz - QSFP56G_1 */
+ qsfp56g_1_clk: clock-controller@5f {
+ compatible = "renesas,proxo-xp";
+ reg = <0x5f>;
+ #clock-cells = <0>;
+ clock-output-names = "qsfp56g_1_clk";
+ };
+
+ /* J81 - OE for u115@50 + 8 - 320MHz - LPDDR5_C0 */
+ lpddr5_c0_clk: clock-controller@58 {
+ compatible = "renesas,proxo-xp";
+ reg = <0x58>;
+ #clock-cells = <0>;
+ clock-output-names = "lpddr5_c0_clk";
+ };
+
+ /* i2c_main_2 - u148 - j122 - disable translation, add 9 */
+ /* J112 - OE for u63@50 + 9 - 320MHz - LPDDR5_C2 */
+ lpddr5_c2_clk: clock-controller@59 {
+ compatible = "renesas,proxo-xp";
+ reg = <0x59>;
+ #clock-cells = <0>;
+ clock-output-names = "lpddr5_c2_clk";
+ };
+
+ /* i2c_main_3 - u149 - j154 - disable translation, add 6 */
+ /* J78 - OE for u116@50 + 6 - 320MHz - DDR5_UDIMM */
+ ddr5_udimm_clk: clock-controller@56 {
+ compatible = "renesas,proxo-xp";
+ reg = <0x56>;
+ #clock-cells = <0>;
+ clock-output-names = "ddr5_udimm_clk";
+ };
+
+ /* i2c_main_4 - u150 - j146 - disable translation, add 5 */
+ /* J107 - OE for u39@50 + 5 - 33,3333MHz - PS_REFCLK */
+ ps_refclk: clock-controller@55 {
+ compatible = "renesas,proxo-xp";
+ reg = <0x55>;
+ #clock-cells = <0>;
+ clock-output-names = "ps_refclk";
+ };
+
+ /* i2c_main_5 - u1782 - j1798 - disable translation, add 7 */
+ /* J77 - OE for u1783@50 + 7 - 320MHz - DDR4 */
+ ddr4_clk: clock-controller@57 {
+ compatible = "renesas,proxo-xp";
+ reg = <0x57>;
+ #clock-cells = <0>;
+ clock-output-names = "ddr4_clk";
+ };
+
+ /* LTC4316 - not wired XORH/XORL - FIXME */
+ /* J3 gate - FIXME should be connected for SW handling */
+ /* i2c_main_1 bus */
+ i2c1_u32: clock-controller@68 {
+ compatible = "renesas,9fgv1006";
+ reg = <0x68>;
+ };
+
+ /* J71 - selection to LP_I2C_SCL_J or LP_I2C_PMC_SCL_J */
+ /* J70 - selection to LP_I2C_SDA_J or LP_I2C_PMC_SDA_J */
+ /* this should be SW controlable too */
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Via j11/j12 can also go to u17/IML3112 - 1:2 multiplexer - also accessed from Versal NET */
+ /* Connection DDR5_UDIMM - SPD can be from 0x50-0x57 */
+ /* FIXME gpio should handle SYSCTLR_PMBUS_ALERT and also INA226_PMBUS_ALERT */
+
+ /* ina226_pmbus - J55 - disable INA226_PMBUS */
+ vcc_ram_ina: power-monitor@40 { /* u1700 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x40>;
+ shunt-resistor = <1000>; /* R1996 */
+ };
+
+ vcc_lpd_ina: power-monitor@41 { /* u1732 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x41>;
+ shunt-resistor = <1000>; /* R2017 */
+ };
+
+ vccaux_ina: power-monitor@42 { /* u1733 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x42>;
+ shunt-resistor = <1000>; /* R2037 */
+ };
+
+ vccaux_lpd_ina: power-monitor@43 { /* u1736 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x43>;
+ shunt-resistor = <1000>; /* R2057 */
+ };
+
+ vcco_500_ina: power-monitor@44 { /* u1737 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x44>;
+ shunt-resistor = <1000>; /* R2069 */
+ };
+
+ vcco_501_ina: power-monitor@45 { /* u1739 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x45>;
+ shunt-resistor = <1000>; /* R2089 */
+ };
+
+ vcco_502_ina: power-monitor@46 { /* u1741 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x46>;
+ shunt-resistor = <1000>; /* R2108 */
+ };
+
+ vcco_503_ina: power-monitor@47 { /* u1743 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x47>;
+ shunt-resistor = <1000>; /* R2127 */
+ };
+
+ vcco_700_ina: power-monitor@48 { /* u1745 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x48>;
+ shunt-resistor = <1000>; /* R2154 */
+ };
+
+ vcco_706_ina: power-monitor@49 { /* u1747 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x49>;
+ shunt-resistor = <1000>; /* R2175 */
+ };
+
+ gtyp_avcc_ina: power-monitor@4a { /* u1750 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4a>;
+ shunt-resistor = <1000>; /* R2195 */
+ };
+
+ gtyp_avtt_ina: power-monitor@4b { /* u1752 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4b>;
+ shunt-resistor = <1000>; /* R2215 */
+ };
+
+ gtyp_avccaux_ina: power-monitor@4c { /* u1754 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4c>;
+ shunt-resistor = <5000>; /* R2235 */
+ };
+
+ gtm_avcc_ina: power-monitor@4d { /* u1756 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4d>;
+ shunt-resistor = <1000>; /* R2256 */
+ };
+
+ gtm_avtt_ina: power-monitor@4e { /* u1758 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4e>;
+ shunt-resistor = <1000>; /* R2276 */
+ };
+
+ gtm_avccaux_ina: power-monitor@4f { /* u1760 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4f>;
+ shunt-resistor = <5000>; /* R2296 */
+ };
+
+ /* pmbus - J50 - disable main PMBUS - also going to j132 */
+ vcc_ram: regulator@a { /* u1730 */
+ compatible = "ti,tps544b25";
+ reg = <0xa>;
+ };
+
+ vcc_lpd: regulator@b { /* u1731 */
+ compatible = "ti,tps544b25";
+ reg = <0xb>;
+ };
+
+ vccaux: regulator@1a { /* u1734 */
+ compatible = "ti,tps544b25";
+ reg = <0x1a>;
+ };
+
+ vcco_503: regulator@12 { /* u1744 */
+ compatible = "ti,tps546b24a";
+ reg = <0x12>;
+ };
+
+ vcco_700: regulator@16 { /* u1746 */
+ compatible = "ti,tps544b25";
+ reg = <0x16>;
+ };
+
+ vcco_706: regulator@17 { /* u1748 */
+ compatible = "ti,tps544b25";
+ reg = <0x17>;
+ };
+
+ gtm_avcc: regulator@23 { /* u1755 */
+ compatible = "ti,tps544b25";
+ reg = <0x23>;
+ };
+
+ gtm_avtt: regulator@24 { /* u1757 */
+ compatible = "ti,tps544b25";
+ reg = <0x24>;
+ };
+
+ gtm_avccaux: regulator@25 { /* u1759 */
+ compatible = "ti,tps544b25";
+ reg = <0x25>;
+ };
+
+ util_1v8: regulator@15 { /* u1765 */
+ compatible = "ti,tps544b25";
+ reg = <0x15>;
+ };
+
+ ucd90320: power-sequencer@73 { /* u1768 */
+ compatible = "ti,ucd90320";
+ reg = <0x73>;
+ };
+
+ /* EXT_PMBUS main - J10 - disable extended PMBUS */
+ vccint: tps53681@60 { /* u1712 - J1770 reset jumper */
+ compatible = "ti,tps53681", "ti,tps53679";
+ reg = <0x60>;
+ /* vccint, vcc_cpm5n */
+ };
+
+ vcc_io_soc: tps53681@61 { /* u1721 - J1772 reset jumper */
+ compatible = "ti,tps53681", "ti,tps53679";
+ reg = <0x61>;
+ /* vcc_io_soc, vcc_fpd */
+ };
+
+ vccaux_lpd: regulator@d { /* u1735 */
+ compatible = "ti,tps544b25";
+ reg = <0xd>;
+ };
+
+ vcco_500: regulator@13 { /* u1738 */
+ compatible = "ti,tps546b24a";
+ reg = <0x13>;
+ };
+
+ vcco_501: regulator@10 { /* u1740 */
+ compatible = "ti,tps546b24a";
+ reg = <0x10>;
+ };
+
+ vcco_502: regulator@11 { /* u1742 */
+ compatible = "ti,tps546b24a";
+ reg = <0x11>;
+ };
+
+ gtyp_avcc: regulator@20 { /* u1749 */
+ compatible = "ti,tps544b25";
+ reg = <0x20>;
+ };
+
+ gtyp_avtt: regulator@21 { /* u1751 */
+ compatible = "ti,tps544b25";
+ reg = <0x21>;
+ };
+
+ gtyp_avccaux: regulator@22 { /* u1753 */
+ compatible = "ti,tps544b25";
+ reg = <0x22>;
+ };
+
+ lp5_vdd1_1v8: regulator@e { /* u1761 - FIXME no ina226 */
+ compatible = "ti,tps544b25";
+ reg = <0xe>;
+ };
+
+ lp5_vdd2_1v05: regulator@f { /* u1762 - FIXME no ina226 */
+ compatible = "ti,tps544b25";
+ reg = <0xf>;
+ };
+
+ lp5_vddq_0v5: regulator@14 { /* u1763 - FIXME no ina226 */
+ compatible = "ti,tps546b24a";
+ reg = <0x14>;
+ };
+};
diff --git a/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso
new file mode 100644
index 0000000..750bc39
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso
@@ -0,0 +1,326 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VPK120 revB
+ *
+ * (C) Copyright 2021 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+
+&{/} {
+ compatible = "xlnx,zynqmp-sc-vpk120-revB", "xlnx,zynqmp-vpk120-revB",
+ "xlnx,zynqmp-vpk120", "xlnx,zynqmp";
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6416_u233: gpio@20 { /* u233 */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "", "", "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", /* 0 - 3 */
+ "PMBUS2_INA226_ALERT", "", "", "", /* 4 - 7 */
+ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */
+ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@74 { /* u33 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ pmbus_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* On connector J325 */
+ ir38060_41: regulator@41 { /* IR38060 - u259 */
+ compatible = "infineon,ir38060", "infineon,ir38064";
+ reg = <0x41>; /* i2c addr 0x11 */
+ };
+ ir38164_43: regulator@43 { /* IR38164 - u13 */
+ compatible = "infineon,ir38164";
+ reg = <0x43>; /* i2c addr 0x13 */
+ };
+ ir35221_46: pmic@46 { /* IR35221 - u152 */
+ compatible = "infineon,ir35221";
+ reg = <0x46>; /* i2c addr - 0x16 */
+ };
+ irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
+ compatible = "infineon,irps5401";
+ reg = <0x47>; /* i2c addr 0x17 */
+ };
+ ir38164_49: regulator@49 { /* IR38164 - u189 */
+ compatible = "infineon,ir38164";
+ reg = <0x49>; /* i2c addr 0x19 */
+ };
+ irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
+ compatible = "infineon,irps5401";
+ reg = <0x4c>; /* i2c addr 0x1c */
+ };
+ irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
+ compatible = "infineon,irps5401";
+ reg = <0x4d>; /* i2c addr 0x1d */
+ };
+ ir38164_4e: regulator@4e { /* IR38164 - u185 */
+ compatible = "infineon,ir38164";
+ reg = <0x4e>; /* i2c addr 0x1e */
+ };
+ ir38164_4f: regulator@4f { /* IR38164 - u187 */
+ compatible = "infineon,ir38164";
+ reg = <0x4f>; /* i2c addr 0x1f */
+ };
+ };
+ pmbus1_ina226_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME check alerts coming to SC */
+ vccint: ina226@40 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ vcc_soc: ina226@41 { /* u161 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ vcc_pmc: ina226@42 { /* u163 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ vcc_ram: ina226@43 { /* u5 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ vcc_pslp: ina226@44 { /* u165 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ vcc_psfp: ina226@45 { /* u164 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@2 { /* NC */ /* FIXME maybe remove */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ pmbus2_ina226_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* FIXME check alerts coming to SC */
+ vccaux: ina226@40 { /* u166 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ vccaux_pmc: ina226@41 { /* u168 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ mgtavcc: ina226@42 { /* u265 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ vcc1v5: ina226@43 { /* u264 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ vcco_mio: ina226@45 { /* u172 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ mgtavtt: ina226@46 { /* u188 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <2000>;
+ };
+ vcco_502: ina226@47 { /* u174 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ mgtvccaux: ina226@48 { /* u176 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>;
+ };
+ vcc1v1_lp4: ina226@49 { /* u186 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <2000>;
+ };
+ vadj_fmc: ina226@4a { /* u184 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <2000>;
+ };
+ lpdmgtyavcc: ina226@4b { /* u177 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ lpdmgtyavtt: ina226@4c { /* u260 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <2000>;
+ };
+ lpdmgtyvccaux: ina226@4d { /* u234 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@4 { /* NC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ i2c@5 { /* NC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ user_si570: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ user_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5f>;
+ temperature-stability = <50>;
+ factory-fout = <100000000>;
+ clock-frequency = <100000000>;
+ clock-output-names = "fmc_si570";
+ silabs,skip-recall;
+ };
+
+ };
+ /* 7 unused */
+ };
+};
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-mux@74 { /* u35 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ ref_clk_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ ref_clk: clock-generator@5d { /* u32 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <33333333>;
+ clock-frequency = <33333333>;
+ clock-output-names = "ref_clk";
+ silabs,skip-recall;
+ };
+ };
+ fmcp1_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME connection to Samtec J51C */
+ /* expected eeprom 0x50 SE cards */
+ };
+ i2c@2 { /* NC - FIXME */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ lpddr4_si570_clk3_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ lpddr4_clk3: clock-generator@60 { /* u4 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk3";
+ silabs,skip-recall;
+ };
+ };
+ lpddr4_si570_clk2_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ lpddr4_clk2: clock-generator@60 { /* u3 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk2";
+ silabs,skip-recall;
+ };
+ };
+ lpddr4_si570_clk1_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ lpddr4_clk1: clock-generator@60 { /* u248 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk1";
+ silabs,skip-recall;
+ };
+ };
+ qsfpdd_i2c: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* J1/J2 connectors */
+ };
+ idt8a34001_i2c: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* Via J310 connector */
+ idt_8a34001: phc@5b {
+ compatible = "idt,8a34001"; /* u219B */
+ reg = <0x5b>; /* FIXME not in schematics */
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso
new file mode 100644
index 0000000..551341f
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VPK180 revA
+ *
+ * (C) Copyright 2021 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+
+&{/} {
+ compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-vpk180-revA",
+ "xlnx,zynqmp-vpk180", "xlnx,zynqmp";
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6416_u233: gpio@20 { /* u233 */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", "QSFPDD3_MODSELL", "QSFPDD4_MODSELL", /* 0 - 3 */
+ "PMBUS2_INA226_ALERT", "QSFPDD5_MODSELL", "QSFPDD6_MODSELL", "", /* 4 - 7 */
+ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "UTIL_3V3_VRHOT_B", /* 10 - 13 */
+ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@74 { /* u33 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ pmbus_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* On connector J325 */
+ ir38060_41: regulator@41 { /* IR38060 - u259 */
+ compatible = "infineon,ir38060", "infineon,ir38064";
+ reg = <0x41>; /* i2c addr 0x11 */
+ };
+ ir35221_45: pmic@45 { /* IR35221 - u291 */
+ compatible = "infineon,ir35221";
+ reg = <0x45>; /* i2c addr - 0x15 */
+ };
+ ir35221_46: pmic@46 { /* IR35221 - u152 */
+ compatible = "infineon,ir35221";
+ reg = <0x46>; /* i2c addr - 0x16 */
+ };
+ irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
+ compatible = "infineon,irps5401";
+ reg = <0x47>; /* i2c addr 0x17 */
+ };
+ irps5401_48: pmic@48 { /* IRPS5401 - u295 */
+ compatible = "infineon,irps5401";
+ reg = <0x48>; /* i2c addr 0x18 */
+ };
+ ir38164_49: regulator@49 { /* IR38164 - u189 */
+ compatible = "infineon,ir38164";
+ reg = <0x49>; /* i2c addr 0x19 */
+ };
+ irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
+ compatible = "infineon,irps5401";
+ reg = <0x4c>; /* i2c addr 0x1c */
+ };
+ irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
+ compatible = "infineon,irps5401";
+ reg = <0x4d>; /* i2c addr 0x1d */
+ };
+ ir38164_4e: regulator@4e { /* IR38164 - u185 */
+ compatible = "infineon,ir38164";
+ reg = <0x4e>; /* i2c addr 0x1e */
+ };
+ ir38164_4f: regulator@4f { /* IR38164 - u187 */
+ compatible = "infineon,ir38164";
+ reg = <0x4f>; /* i2c addr 0x1f */
+ };
+ };
+ pmbus1_ina226_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME check alerts coming to SC */
+ vccint: ina226@40 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>; /* r440 */
+ };
+ vcc_soc: ina226@41 { /* u161 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>; /* r2174 */
+ };
+ vcc_pmc: ina226@42 { /* u163 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>; /* r1214 */
+ };
+ vcc_ram: ina226@43 { /* u5 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>; /* r2108 */
+ };
+ vcc_pslp: ina226@44 { /* u165 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>; /* r1830 */
+ };
+ vcc_psfp: ina226@45 { /* u164 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>; /* r2086 */
+ };
+ };
+ i2c@2 { /* NC */ /* FIXME maybe remove */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ pmbus2_ina226_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* FIXME check alerts coming to SC */
+ vccaux: ina226@40 { /* u166 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <2000>; /* r2109 */
+ };
+ vccaux_pmc: ina226@41 { /* u168 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>; /* r1246 */
+ };
+ mgtavcc: ina226@42 { /* u265 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>; /* r1829 */
+ };
+ vcc1v5: ina226@43 { /* u264 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>; /* r1221 */
+ };
+ vcco_mio: ina226@45 { /* u172 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>; /* r1219 */
+ };
+ mgtavtt: ina226@46 { /* u188 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <2000>; /* r1384 */
+ };
+ vcco_502: ina226@47 { /* u174 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>; /* r1825 */
+ };
+ mgtvccaux: ina226@48 { /* u176 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>; /* r1232 */
+ };
+ vcc1v1_lp4: ina226@49 { /* u186 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <2000>; /* r1367 */
+ };
+ vadj_fmc: ina226@4a { /* u184 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <2000>; /* r1350 */
+ };
+ lpdmgtyavcc: ina226@4b { /* u177 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>; /* r2097 */
+ };
+ lpdmgtyavtt: ina226@4c { /* u260 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <2000>; /* r1834 */
+ };
+ lpdmgtyvccaux: ina226@4d { /* u234 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <5000>; /* r1679 */
+ };
+ };
+ /* 4 - 7 unused */
+ };
+};
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-mux@74 { /* u35 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c-mux-idle-disconnect;
+ /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ ref_clk_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ ref_clk: clock-generator@5d { /* u32 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <33333333>;
+ clock-frequency = <33333333>;
+ clock-output-names = "ref_clk";
+ silabs,skip-recall;
+ };
+ };
+ fmcp1_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* connection to Samtec J51C */
+ /* expected eeprom 0x50 SE cards */
+ };
+ osfp_i2c: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* J362 connector */
+ };
+ lpddr4_si570_clk3_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ lpddr4_clk3: clock-generator@60 { /* u4 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk3";
+ silabs,skip-recall;
+ };
+ /* alternative option DNP - u305 at 0x50 */
+ };
+ lpddr4_si570_clk2_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ lpddr4_clk2: clock-generator@60 { /* u3 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk2";
+ silabs,skip-recall;
+ };
+ /* alternative option DNP - u303 at 0x50 */
+ };
+ lpddr4_si570_clk1_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ lpddr4_clk1: clock-generator@60 { /* u248 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk1";
+ silabs,skip-recall;
+ };
+ /* alternative option DNP - u301 at 0x50 */
+ };
+ qsfpdd_i2c: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* J1/J2/J355/J354/J359/J358 connectors */
+ };
+ idt8a34001_i2c: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* Via J310 connector */
+ idt_8a34001: phc@5b { /* u219B */
+ compatible = "idt,8a34001";
+ reg = <0x5b>;
+ };
+ };
+ };
+ i2c-mux@75 { /* u322 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c-mux-idle-disconnect;
+ /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ sfpdd1_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* J350 sfp-dd at 0x50 */
+ };
+ sfpdd2_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* J352 sfp-dd at 0x50 */
+ };
+ sfpdd3_i2c: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* J385 sfp-dd at 0x50 */
+ };
+ sfpdd4_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* J387 sfp-dd at 0x50 */
+ };
+ rc21008a_gtclk1_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ vc7_1: clock-generator@9 {
+ compatible = "renesas,rc21008a";
+ clock-output-names = "rc21008a-0";
+ reg = <0x9>;
+ #clock-cells = <1>;
+ clocks = <&vc7_xin>;
+ clock-names = "xin";
+ };
+ /* u298 - rc21008a at 0x9 */
+ /* connector J370 */
+ };
+ rc21008a_gtclk2_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ vc7_2: clock-generator@9 {
+ compatible = "renesas,rc21008a";
+ clock-output-names = "rc21008a-1";
+ reg = <0x9>;
+ #clock-cells = <1>;
+ clocks = <&vc7_xin>;
+ clock-names = "xin";
+ };
+ /* u299 - rc21008a at 0x9 */
+ /* connector J371 */
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso
new file mode 100644
index 0000000..e70eb4d
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso
@@ -0,0 +1,337 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VPK180 revA
+ *
+ * (C) Copyright 2021 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+
+&{/} {
+ compatible = "xlnx,zynqmp-sc-vpk180-revB", "xlnx,zynqmp-vpk180-revB",
+ "xlnx,zynqmp-vpk180", "xlnx,zynqmp";
+
+ vc7_xin: vc7-xin {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <50000000>;
+ };
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6416_u233: gpio@20 { /* u233 */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", "QSFPDD3_MODSELL", "QSFPDD4_MODSELL", /* 0 - 3 */
+ "PMBUS2_INA226_ALERT", "QSFPDD5_MODSELL", "QSFPDD6_MODSELL", "", /* 4 - 7 */
+ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "UTIL_3V3_VRHOT_B", /* 10 - 13 */
+ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@74 { /* u33 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ pmbus_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* On connector J325 */
+ ir38060_41: regulator@41 { /* IR38060 - u259 */
+ compatible = "infineon,ir38060", "infineon,ir38064";
+ reg = <0x41>; /* i2c addr 0x11 */
+ };
+ ir35221_45: pmic@45 { /* IR35221 - u291 */
+ compatible = "infineon,ir35221";
+ reg = <0x45>; /* i2c addr - 0x15 */
+ };
+ ir35221_46: pmic@46 { /* IR35221 - u152 */
+ compatible = "infineon,ir35221";
+ reg = <0x46>; /* i2c addr - 0x16 */
+ };
+ irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
+ compatible = "infineon,irps5401";
+ reg = <0x47>; /* i2c addr 0x17 */
+ };
+ irps5401_48: pmic@48 { /* IRPS5401 - u295 */
+ compatible = "infineon,irps5401";
+ reg = <0x48>; /* i2c addr 0x18 */
+ };
+ ir38164_49: regulator@49 { /* IR38164 - u189 */
+ compatible = "infineon,ir38164";
+ reg = <0x49>; /* i2c addr 0x19 */
+ };
+ irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
+ compatible = "infineon,irps5401";
+ reg = <0x4c>; /* i2c addr 0x1c */
+ };
+ irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
+ compatible = "infineon,irps5401";
+ reg = <0x4d>; /* i2c addr 0x1d */
+ };
+ ir38164_4e: regulator@4e { /* IR38164 - u185 */
+ compatible = "infineon,ir38164";
+ reg = <0x4e>; /* i2c addr 0x1e */
+ };
+ ir38164_4f: regulator@4f { /* IR38164 - u187 */
+ compatible = "infineon,ir38164";
+ reg = <0x4f>; /* i2c addr 0x1f */
+ };
+ };
+ pmbus1_ina226_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME check alerts coming to SC */
+ vccint: ina226@40 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>; /* r440 */
+ };
+ vcc_soc: ina226@41 { /* u161 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>; /* r2174 */
+ };
+ vcc_pmc: ina226@42 { /* u163 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>; /* r1214 */
+ };
+ vcc_ram: ina226@43 { /* u5 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>; /* r2108 */
+ };
+ vcc_pslp: ina226@44 { /* u165 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>; /* r1830 */
+ };
+ vcc_psfp: ina226@45 { /* u164 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>; /* r2086 */
+ };
+ };
+ i2c@2 { /* NC */ /* FIXME maybe remove */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ pmbus2_ina226_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* FIXME check alerts coming to SC */
+ vccaux: ina226@40 { /* u166 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <2000>; /* r2109 */
+ };
+ vccaux_pmc: ina226@41 { /* u168 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>; /* r1246 */
+ };
+ mgtavcc: ina226@42 { /* u265 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>; /* r1829 */
+ };
+ vcc1v5: ina226@43 { /* u264 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>; /* r1221 */
+ };
+ vcco_mio: ina226@45 { /* u172 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>; /* r1219 */
+ };
+ mgtavtt: ina226@46 { /* u188 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <2000>; /* r1384 */
+ };
+ vcco_502: ina226@47 { /* u174 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>; /* r1825 */
+ };
+ mgtvccaux: ina226@48 { /* u176 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>; /* r1232 */
+ };
+ vcc1v1_lp4: ina226@49 { /* u186 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <2000>; /* r1367 */
+ };
+ vadj_fmc: ina226@4a { /* u184 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <2000>; /* r1350 */
+ };
+ lpdmgtyavcc: ina226@4b { /* u177 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>; /* r2097 */
+ };
+ lpdmgtyavtt: ina226@4c { /* u260 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <2000>; /* r1834 */
+ };
+ lpdmgtyvccaux: ina226@4d { /* u234 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <5000>; /* r1679 */
+ };
+ };
+ /* 4 - 7 unused */
+ };
+};
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-mux@74 { /* u35 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c-mux-idle-disconnect;
+ /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ fmcp1_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* connection to Samtec J51C */
+ /* expected eeprom 0x50 SE cards */
+ };
+ osfp_i2c: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* J362 connector */
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* alternative option DNP - u305 at 0x50 */
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* alternative option DNP - u303 at 0x50 */
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* alternative option DNP - u301 at 0x50 */
+ };
+ qsfpdd_i2c: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* J1/J2/J355/J354/J359/J358 connectors */
+ };
+ idt8a34001_i2c: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* Via J310 connector */
+ idt_8a34001: phc@5b { /* u219B */
+ compatible = "idt,8a34001";
+ reg = <0x5b>;
+ };
+ };
+ };
+ i2c-mux@75 { /* u322 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c-mux-idle-disconnect;
+ /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ sfpdd1_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* J350 sfp-dd at 0x50 */
+ };
+ sfpdd2_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* J352 sfp-dd at 0x50 */
+ };
+ sfpdd3_i2c: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* J385 sfp-dd at 0x50 */
+ };
+ sfpdd4_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* J387 sfp-dd at 0x50 */
+ };
+ rc21008a_gtclk1_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ vc7_1: clock-generator@9 {
+ compatible = "renesas,rc21008a";
+ clock-output-names = "rc21008a-0";
+ reg = <0x9>;
+ #clock-cells = <1>;
+ clocks = <&vc7_xin>;
+ clock-names = "xin";
+ };
+ /* u298 - rc21008a at 0x9 */
+ /* connector J370 */
+ };
+ rc21008a_gtclk2_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ vc7_2: clock-generator@9 {
+ compatible = "renesas,rc21008a";
+ clock-output-names = "rc21008a-1";
+ reg = <0x9>;
+ #clock-cells = <1>;
+ clocks = <&vc7_xin>;
+ clock-names = "xin";
+ };
+ /* u299 - rc21008a at 0x9 */
+ /* connector J371 */
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
new file mode 100644
index 0000000..5a5c1ef
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
@@ -0,0 +1,353 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for KD240 revA Carrier Card
+ *
+ * Copyright (C) 2021 - 2022, Xilinx, Inc.
+ * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "xlnx,zynqmp-sk-kd240-rev1",
+ "xlnx,zynqmp-sk-kd240-revB",
+ "xlnx,zynqmp-sk-kd240-revA",
+ "xlnx,zynqmp-sk-kd240", "xlnx,zynqmp";
+ model = "ZynqMP KD240 revA/B/1";
+
+ ina260-u3 {
+ compatible = "iio-hwmon";
+ io-channels = <&u3 0>, <&u3 1>, <&u3 2>;
+ };
+
+ clk_26: clock2 { /* u17 - USB */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+};
+
+&can0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can0_default>;
+};
+
+&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ u3: ina260@40 { /* u3 */
+ compatible = "ti,ina260";
+ #io-channel-cells = <1>;
+ label = "ina260-u14";
+ reg = <0x40>;
+ };
+
+ slg7xl45106: gpio@11 { /* u13 - reset logic */
+ compatible = "dlg,slg7xl45106";
+ reg = <0x11>;
+ label = "resetchip";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "USB0_PHY_RESET_B", "",
+ "SD_RESET_B", "USB0_HUB_RESET_B",
+ "", "PS_GEM0_RESET_B",
+ "", "";
+ };
+
+ /* usb5744@2d */
+};
+
+/* USB 3.0 */
+&psgtr {
+ status = "okay";
+ /* usb */
+ clocks = <&clk_26>;
+ clock-names = "ref2";
+};
+
+&usb0 { /* mio52 - mio63 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+ reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
+ assigned-clock-rates = <250000000>, <20000000>;
+
+ usbhub0: usb-hub { /* u36 */
+ i2c-bus = <&i2c1>;
+ compatible = "microchip,usb5744";
+ reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
+ };
+
+ usb2244: usb-sd { /* u41 */
+ compatible = "microchip,usb2244";
+ reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+ maximum-speed = "super-speed";
+};
+
+&gem1 { /* mdio mio50/51 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem1_default>;
+ assigned-clock-rates = <250000000>;
+
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@8 { /* Adin u31 */
+ reg = <8>;
+ adi,rx-internal-delay-ps = <2000>;
+ adi,tx-internal-delay-ps = <2000>;
+ adi,fifo-depth-bits = <8>;
+ reset-assert-us = <10>;
+ reset-deassert-us = <5000>;
+ reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+/* 2 more ethernet phys u32@2 and u34@3 */
+
+&pinctrl0 { /* required by spec */
+ status = "okay";
+
+ pinctrl_can0_default: can0-default {
+ mux {
+ function = "can0";
+ groups = "can0_16_grp";
+ };
+
+ conf {
+ groups = "can0_16_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO66";
+ bias-pull-up;
+ };
+
+ conf-tx {
+ pins = "MIO67";
+ bias-pull-up;
+ drive-strength = <4>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ conf {
+ groups = "uart0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO70";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO71";
+ bias-disable;
+ };
+
+ mux {
+ groups = "uart0_17_grp";
+ function = "uart0";
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ conf {
+ groups = "uart1_9_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO37";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO36";
+ bias-disable;
+ output-enable;
+ };
+
+ mux {
+ groups = "uart1_9_grp";
+ function = "uart1";
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ conf {
+ groups = "i2c1_6_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "i2c1_6_grp";
+ function = "i2c1";
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ conf {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ function = "gpio0";
+ };
+ };
+
+ pinctrl_gem1_default: gem1-default {
+ conf {
+ groups = "ethernet1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO45", "MIO46", "MIO47", "MIO48";
+ bias-disable;
+ low-power-disable;
+ };
+
+ conf-bootstrap {
+ pins = "MIO44", "MIO49";
+ bias-disable;
+ output-enable;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO38", "MIO39", "MIO40",
+ "MIO41", "MIO42", "MIO43";
+ bias-disable;
+ output-enable;
+ low-power-enable;
+ };
+
+ conf-mdio {
+ groups = "mdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ output-enable;
+ };
+
+ mux-mdio {
+ function = "mdio1";
+ groups = "mdio1_0_grp";
+ };
+
+ mux {
+ function = "ethernet1";
+ groups = "ethernet1_0_grp";
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ conf {
+ groups = "usb0_0_grp";
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ drive-strength = <12>;
+ slew-rate = <SLEW_RATE_FAST>;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ output-enable;
+ drive-strength = <4>;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+ };
+
+ pinctrl_usb1_default: usb1-default {
+ conf {
+ groups = "usb1_0_grp";
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO64", "MIO65", "MIO67";
+ bias-high-impedance;
+ drive-strength = <12>;
+ slew-rate = <SLEW_RATE_FAST>;
+ };
+
+ conf-tx {
+ pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
+ "MIO72", "MIO73", "MIO74", "MIO75";
+ bias-disable;
+ output-enable;
+ drive-strength = <4>;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+
+ mux {
+ groups = "usb1_0_grp";
+ function = "usb1";
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
+ assigned-clock-rates = <100000000>;
+};
+
+&uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+};
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
similarity index 98%
rename from arch/arm/dts/zynqmp-sck-kr-g-revA.dts
rename to arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
index d318773..30a0230 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
@@ -250,6 +250,7 @@
conf-tx {
pins = "MIO36";
bias-disable;
+ output-enable;
};
mux {
@@ -301,6 +302,7 @@
conf-bootstrap {
pins = "MIO45", "MIO47", "MIO49";
bias-disable;
+ output-enable;
low-power-disable;
};
@@ -308,6 +310,7 @@
pins = "MIO38", "MIO39", "MIO40",
"MIO41", "MIO42", "MIO43";
bias-disable;
+ output-enable;
low-power-enable;
};
@@ -316,6 +319,7 @@
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
+ output-enable;
};
mux-mdio {
@@ -346,6 +350,7 @@
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
+ output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
@@ -373,6 +378,7 @@
pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
"MIO72", "MIO73", "MIO74", "MIO75";
bias-disable;
+ output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
similarity index 98%
rename from arch/arm/dts/zynqmp-sck-kr-g-revB.dts
rename to arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
index 69dba07..8f4c52d 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
@@ -250,6 +250,7 @@
conf-tx {
pins = "MIO36";
bias-disable;
+ output-enable;
};
mux {
@@ -301,6 +302,7 @@
conf-bootstrap {
pins = "MIO45", "MIO47", "MIO49";
bias-disable;
+ output-enable;
low-power-disable;
};
@@ -308,6 +310,7 @@
pins = "MIO38", "MIO39", "MIO40",
"MIO41", "MIO42", "MIO43";
bias-disable;
+ output-enable;
low-power-enable;
};
@@ -316,6 +319,7 @@
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
+ output-enable;
};
mux-mdio {
@@ -346,6 +350,7 @@
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
+ output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
@@ -373,6 +378,7 @@
pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
"MIO72", "MIO73", "MIO74", "MIO75";
bias-disable;
+ output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
similarity index 86%
rename from arch/arm/dts/zynqmp-sck-kv-g-revA.dts
rename to arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
index a81b3f6..c4f1da9 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
@@ -2,12 +2,13 @@
/*
* dts file for KV260 revA Carrier Card
*
- * (C) Copyright 2020 - 2021, Xilinx, Inc.
+ * (C) Copyright 2020 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* SD level shifter:
- * "A" – A01 board un-modified (NXP)
- * "Y" – A01 board modified with legacy interposer (Nexperia)
- * "Z" – A01 board modified with Diode interposer
+ * "A" - A01 board un-modified (NXP)
+ * "Y" - A01 board modified with legacy interposer (Nexperia)
+ * "Z" - A01 board modified with Diode interposer
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -156,7 +157,7 @@
disable-wp;
xlnx,mio-bank = <1>;
assigned-clock-rates = <187498123>;
- bus-width = <8>;
+ bus-width = <4>;
};
&gem3 {
@@ -189,6 +190,25 @@
&pinctrl0 {
status = "okay";
+ pinctrl_gpio0_default: gpio0-default {
+ conf {
+ groups = "gpio0_38_grp";
+ bias-pull-up;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "gpio0_38_grp";
+ function = "gpio0";
+ };
+
+ conf-tx {
+ pins = "MIO38";
+ bias-disable;
+ output-enable;
+ };
+ };
+
pinctrl_uart1_default: uart1-default {
conf {
groups = "uart1_9_grp";
@@ -205,6 +225,7 @@
conf-tx {
pins = "MIO36";
bias-disable;
+ output-enable;
};
mux {
@@ -256,6 +277,7 @@
conf-bootstrap {
pins = "MIO71", "MIO73", "MIO75";
bias-disable;
+ output-enable;
low-power-disable;
};
@@ -263,6 +285,7 @@
pins = "MIO64", "MIO65", "MIO66",
"MIO67", "MIO68", "MIO69";
bias-disable;
+ output-enable;
low-power-enable;
};
@@ -271,6 +294,7 @@
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
+ output-enable;
};
mux-mdio {
@@ -301,6 +325,7 @@
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
+ output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
@@ -339,6 +364,12 @@
};
};
+&gpio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio0_default>;
+};
+
&uart1 {
status = "okay";
pinctrl-names = "default";
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
similarity index 91%
rename from arch/arm/dts/zynqmp-sck-kv-g-revB.dts
rename to arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
index f935f25..6c5e0e5 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
@@ -2,7 +2,8 @@
/*
* dts file for KV260 revA Carrier Card
*
- * (C) Copyright 2020 - 2021, Xilinx, Inc.
+ * (C) Copyright 2020 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -144,7 +145,7 @@
clk-phase-uhs-sdr25 = <120>, <60>;
clk-phase-uhs-ddr50 = <126>, <48>;
assigned-clock-rates = <187498123>;
- bus-width = <8>;
+ bus-width = <4>;
};
&gem3 {
@@ -177,6 +178,25 @@
&pinctrl0 {
status = "okay";
+ pinctrl_gpio0_default: gpio0-default {
+ conf {
+ groups = "gpio0_38_grp";
+ bias-pull-up;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "gpio0_38_grp";
+ function = "gpio0";
+ };
+
+ conf-tx {
+ pins = "MIO38";
+ bias-disable;
+ output-enable;
+ };
+ };
+
pinctrl_uart1_default: uart1-default {
conf {
groups = "uart1_9_grp";
@@ -193,6 +213,7 @@
conf-tx {
pins = "MIO36";
bias-disable;
+ output-enable;
};
mux {
@@ -244,6 +265,7 @@
conf-bootstrap {
pins = "MIO71", "MIO73", "MIO75";
bias-disable;
+ output-enable;
low-power-disable;
};
@@ -251,6 +273,7 @@
pins = "MIO64", "MIO65", "MIO66",
"MIO67", "MIO68", "MIO69";
bias-disable;
+ output-enable;
low-power-enable;
};
@@ -259,6 +282,7 @@
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
+ output-enable;
};
mux-mdio {
@@ -289,6 +313,7 @@
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
+ output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
@@ -327,6 +352,12 @@
};
};
+&gpio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio0_default>;
+};
+
&uart1 {
status = "okay";
pinctrl-names = "default";
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index d718fec..1d62c48 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -1,8 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
+ * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -17,8 +18,9 @@
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/ {
- model = "ZynqMP SM-K26 Rev1/B/A";
- compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
+ model = "ZynqMP SM-K26 Rev2/1/B/A";
+ compatible = "xlnx,zynqmp-sm-k26-rev2",
+ "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
"xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
"xlnx,zynqmp";
@@ -143,8 +145,6 @@
status = "okay";
spi_flash: flash@0 { /* MT25QU512A */
compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
- #address-cells = <1>;
- #size-cells = <1>;
reg = <0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
@@ -233,9 +233,9 @@
label = "Secure OS Storage";
reg = <0x2280000 0x20000>; /* 128KB */
};
- partition@22A0000 {
+ partition@22a0000 {
label = "User";
- reg = <0x22A0000 0x1d60000>; /* 29.375 MB */
+ reg = <0x22a0000 0x1d60000>; /* 29.375 MB */
};
};
};
diff --git a/arch/arm/dts/zynqmp-smk-k26-revA.dts b/arch/arm/dts/zynqmp-smk-k26-revA.dts
index 85b0d16..719a4e4 100644
--- a/arch/arm/dts/zynqmp-smk-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-smk-k26-revA.dts
@@ -1,8 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A
+ * dts file for Xilinx ZynqMP SMK-K26 rev2/1/B/A
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -10,8 +11,9 @@
#include "zynqmp-sm-k26-revA.dts"
/ {
- model = "ZynqMP SMK-K26 Rev1/B/A";
- compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB",
+ model = "ZynqMP SMK-K26 Rev2/1/B/A";
+ compatible = "xlnx,zynqmp-smk-k26-rev2",
+ "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB",
"xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26",
"xlnx,zynqmp";
};
diff --git a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
index 3750bb3..0d96c6f 100644
--- a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
+++ b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
@@ -56,7 +56,6 @@
&qspi {
status = "okay";
- is-dual = <1>;
flash@0 {
compatible = "st,m25p80", "n25q256a", "jedec,spi-nor";
m25p,fast-read;
@@ -66,7 +65,6 @@
spi-max-frequency = <166000000>;
#address-cells = <1>;
#size-cells = <1>;
- is-dual = <1>;
partition@0 {
label = "qspi-boot-bin";
reg = <0x00000 0x60000>;
diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
new file mode 100644
index 0000000..9ab8f5b
--- /dev/null
+++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
@@ -0,0 +1,442 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller
+ *
+ * (C) Copyright 2021 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "ZynqMP System Controller on vp-x-a2785-00 board RevA";
+ compatible = "xlnx,zynqmp-vp-x-a2785-00-revA",
+ "xlnx,zynqmp-vp-x-a2785-00", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci0;
+ serial0 = &uart0;
+ serial1 = &dcc;
+ spi0 = &qspi;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ nvmem0 = &eeprom;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0 0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ j383 {
+ label = "j383";
+ gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
+ linux,code = <BTN_MISC>;
+ wakeup-source;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat-led { /* ds52 */
+ label = "heartbeat";
+ gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ si5332_0: si5332_0 { /* ps_ref_clk - u142 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <33333333>;
+ };
+
+ si5332_1: si5332_1 { /* clk0_sgmii - u142 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <33333333>; /* FIXME */
+ };
+
+ si5332_2: si5332_2 { /* clk1_usb - u142 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+};
+
+&qspi { /* MIO 0-5 */
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-tx-bus-width = <4>; /* maybe 4 here */
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ partition@0 { /* for testing purpose */
+ label = "qspi";
+ reg = <0 0x4000000>;
+ };
+ };
+};
+
+&sdhci1 { /* sd MIO 45-51 */
+ status = "okay";
+ no-1-8-v;
+ disable-wp;
+ xlnx,mio-bank = <1>;
+};
+
+&uart0 { /* uart0 MIO38-39 */
+ status = "okay";
+ bootph-all;
+};
+
+&gem0 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "sgmii"; /* DTG generates this properly 1512 */
+ is-internal-pcspma;
+ /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
+ phy0: ethernet-phy@0 { /* u131 - M88e1512 */
+ reg = <0>;
+ };
+ };
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
+ "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */
+ "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "", "", /* 10 - 14 */
+ "", "", "", "", "", /* 15 - 19 */
+ "", "", "", "", "", /* 20 - 24 */
+ "", "", "", "", "", /* 25 - 29 */
+ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
+ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
+ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
+ "SD1_CD", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
+ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
+ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
+ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
+ "", "", "", "", "", /* 65 - 69 */
+ "", "", "", "", "", /* 70 - 74 */
+ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
+ "", "", /* 78 - 79 */
+ "", "", "", "", "", /* 80 - 84 */
+ "", "", "", "", "", /* 85 - 89 */
+ "", "", "", "", "", /* 90 - 94 */
+ "", "", "", "", "", /* 95 - 99 */
+ "", "", "", "", "", /* 100 - 104 */
+ "", "", "", "", "", /* 105 - 109 */
+ "", "", "", "", "", /* 110 - 114 */
+ "", "", "", "", "", /* 115 - 119 */
+ "", "", "", "", "", /* 120 - 124 */
+ "", "", "", "", "", /* 125 - 129 */
+ "", "", "", "", "", /* 130 - 134 */
+ "", "", "", "", "", /* 135 - 139 */
+ "", "", "", "", "", /* 140 - 144 */
+ "", "", "", "", "", /* 145 - 149 */
+ "", "", "", "", "", /* 150 - 154 */
+ "", "", "", "", "", /* 155 - 159 */
+ "", "", "", "", "", /* 160 - 164 */
+ "", "", "", "", "", /* 165 - 169 */
+ "", "", "", ""; /* 170 - 173 */
+};
+
+&i2c0 { /* MIO 34-35 - can't stay here */
+ status = "okay";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */
+ "", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */
+ "", "", "", "VCCINT_FAULT_B", /* 10 - 13 */
+ "VCCINT_VRHOT_B", "", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@74 { /* u33 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ pmbus_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* On connector J325 */
+ reg_vccint: tps53681@60 { /* u266 - 0xc0 */
+ compatible = "ti,tps53681", "ti,tps53679";
+ reg = <0x60>;
+ };
+ reg_vcc1v1_lp4: tps544@d { /* u85 */
+ compatible = "ti,tps544b25";
+ reg = <0xd>;
+ };
+ reg_mgtyavcc: tps544@10 { /* u274 */
+ compatible = "ti,tps544b25";
+ reg = <0x10>;
+ };
+ reg_mgtyavtt: tps544@11 { /* u275 */
+ compatible = "ti,tps544b25";
+ reg = <0x11>;
+ };
+ reg_vccaux: tps544@12 { /* u276 */
+ compatible = "ti,tps544b25";
+ reg = <0x12>;
+ };
+ reg_vcc_cpm: tps544@14 { /* u272 */
+ compatible = "ti,tps544b25";
+ reg = <0x14>;
+ };
+ reg_util_3v3: tps544@1d { /* u278 */
+ compatible = "ti,tps544b25";
+ reg = <0x1d>;
+ };
+ };
+ pmbus1_ina226_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME check alerts coming to SC */
+ vcc_cpm: ina226@44 { /* u273 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <1000>;
+ };
+ };
+ i2c@2 { /* NC */ /* FIXME maybe remove */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ pcie_smbus: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ pcie2_smbus: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ i2c@5 { /* NC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ user_si570: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ /* 7 unused */
+ };
+};
+
+&i2c1 { /* i2c1 MIO 36-37 */
+ status = "okay";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ i2c-mux@74 { /* u35 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ dc_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* Use for storing information about SC board */
+ eeprom: eeprom@54 { /* u34 - m24128 16kB */
+ compatible = "st,24c128", "atmel,24c128";
+ reg = <0x54>; /* & 0x5c */
+ };
+ si570_ref_clk: clock-generator@5d { /* u32 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <33333333>;
+ clock-frequency = <33333333>;
+ clock-output-names = "ref_clk";
+ silabs,skip-recall;
+ };
+ };
+ i2c@1 { /* NC - FIXME */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ i2c@2 { /* NC - FIXME */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ i2c@3 { /* NC - FIXME */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ lpddr4_si570_clk2_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ lpddr4_clk2: clock-generator@60 { /* u3 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk2";
+ };
+ };
+ lpddr4_si570_clk1_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ lpddr4_clk1: clock-generator@60 { /* u248 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk1";
+ };
+ };
+ /* 6-7 unused */
+ };
+};
+
+&usb0 { /* MIO52 - MIO63 */
+ status = "okay";
+ phy-names = "usb3-phy";
+ phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
+};
+
+&psgtr {
+ status = "okay";
+ /* sgmii, usb3 */
+ clocks = <&si5332_1>, <&si5332_2>;
+ clock-names = "ref0", "ref1";
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "peripheral";
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ maximum-speed = "super-speed";
+};
+
+&xilinx_ams {
+ status = "okay";
+};
+
+&ams_ps {
+ status = "okay";
+};
+
+&ams_pl {
+ status = "okay";
+};
+
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_8_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_8_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_34_grp", "gpio0_35_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_34_grp", "gpio0_35_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_9_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_9_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_36_grp", "gpio0_37_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_36_grp", "gpio0_37_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts
new file mode 100644
index 0000000..ce76e0b
--- /dev/null
+++ b/arch/arm/dts/zynqmp-vpk120-revA.dts
@@ -0,0 +1,578 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VPK120 RevA System Controller
+ *
+ * (C) Copyright 2021 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "ZynqMP System Controller on VPK120 board RevA";
+ compatible = "xlnx,zynqmp-vpk120-revA",
+ "xlnx,zynqmp-vpk120", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci0;
+ serial0 = &uart0;
+ serial1 = &dcc;
+ spi0 = &qspi;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ nvmem0 = &eeprom;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ sw16 {
+ label = "sw16";
+ gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
+ linux,code = <BTN_MISC>;
+ wakeup-source;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat-led { /* ds40 */
+ label = "heartbeat";
+ gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ si5332_0: si5332_0 { /* ps_ref_clk */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <33333333>;
+ };
+
+ si5332_1: si5332_1 { /* clk0_sgmii */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <33333333>; /* FIXME */
+ };
+
+ si5332_2: si5332_2 { /* clk1_usb */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+};
+
+&qspi { /* MIO 0-5 */
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ partition@0 { /* for testing purpose */
+ label = "qspi";
+ reg = <0 0x4000000>;
+ };
+ };
+};
+
+&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */
+ status = "okay";
+ non-removable;
+ disable-wp;
+ bus-width = <8>;
+ xlnx,mio-bank = <0>;
+};
+
+&uart0 { /* uart0 MIO38-39 */
+ status = "okay";
+ bootph-all;
+};
+
+&gem0 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "sgmii"; /* DTG generates this properly 1512 */
+ is-internal-pcspma;
+ /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
+ "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */
+ "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
+ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
+ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
+ "", "", "", "", "", /* 25 - 29 */
+ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
+ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
+ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
+ "", "", "", "", "", /* 45 - 49 */
+ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
+ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
+ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
+ "", "", "", "", "", /* 65 - 69 */
+ "", "", "", "", "", /* 70 - 74 */
+ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
+ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
+ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */
+ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */
+ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
+ "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */
+ "", "", "", "", "", /* 100 - 104 */
+ "", "", "", "", "", /* 105 - 109 */
+ "", "", "", "", "", /* 110 - 114 */
+ "", "", "", "", "", /* 115 - 119 */
+ "", "", "", "", "", /* 120 - 124 */
+ "", "", "", "", "", /* 125 - 129 */
+ "", "", "", "", "", /* 130 - 134 */
+ "", "", "", "", "", /* 135 - 139 */
+ "", "", "", "", "", /* 140 - 144 */
+ "", "", "", "", "", /* 145 - 149 */
+ "", "", "", "", "", /* 150 - 154 */
+ "", "", "", "", "", /* 155 - 159 */
+ "", "", "", "", "", /* 160 - 164 */
+ "", "", "", "", "", /* 165 - 169 */
+ "", "", "", ""; /* 170 - 173 */
+};
+
+&i2c0 { /* MIO 34-35 - can't stay here */
+ status = "okay";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "QSFPDD1_MODSELL", "QSFPDD1_MODSELL", /* 0 - 3 */
+ "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */
+ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */
+ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@74 { /* u33 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ pmbus_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* On connector J325 */
+ ir38060_41: regulator@41 { /* IR38060 - u259 */
+ compatible = "infineon,ir38060", "infineon,ir38064";
+ reg = <0x41>; /* i2c addr 0x11 */
+ };
+ ir38164_43: regulator@43 { /* IR38164 - u13 */
+ compatible = "infineon,ir38164";
+ reg = <0x43>; /* i2c addr 0x13 */
+ };
+ ir35221_45: pmic@46 { /* IR35221 - u152 */
+ compatible = "infineon,ir35221";
+ reg = <0x46>; /* PMBUS - 0x16 */
+ };
+ irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
+ compatible = "infineon,irps5401";
+ reg = <0x47>; /* i2c addr 0x17 */
+ };
+ ir38164_49: regulator@49 { /* IR38164 - u189 */
+ compatible = "infineon,ir38164";
+ reg = <0x49>; /* i2c addr 0x19 */
+ };
+ irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
+ compatible = "infineon,irps5401";
+ reg = <0x4c>; /* i2c addr 0x1c */
+ };
+ irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
+ compatible = "infineon,irps5401";
+ reg = <0x4d>; /* i2c addr 0x1c */
+ };
+ ir38164_4e: regulator@4e { /* IR38164 - u184 */
+ compatible = "infineon,ir38164";
+ reg = <0x4e>; /* i2c addr 0x1e */
+ };
+ ir38164_4f: regulator@4f { /* IR38164 - u187 */
+ compatible = "infineon,ir38164";
+ reg = <0x4f>; /* i2c addr 0x1f */
+ };
+ };
+ pmbus1_ina226_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME check alerts coming to SC */
+ vccint: ina226@40 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ vcc_soc: ina226@41 { /* u161 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ vcc_pmc: ina226@42 { /* u163 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ vcc_ram: ina226@43 { /* u5 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ vcc_pslp: ina226@44 { /* u165 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ vcc_psfp: ina226@45 { /* u164 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@2 { /* NC */ /* FIXME maybe remove */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ pmbus2_ina226_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* FIXME check alerts coming to SC */
+ vccaux: ina226@40 { /* u166 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ vccaux_pmc: ina226@41 { /* u168 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ mgtavcc: ina226@42 { /* u265 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ vcc1v5: ina226@43 { /* u264 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ vcco_mio: ina226@45 { /* u172 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ mgtavtt: ina226@46 { /* u188 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <2000>;
+ };
+ vcco_502: ina226@47 { /* u174 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ mgtvccaux: ina226@48 { /* u176 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>;
+ };
+ vcc1v1_lp4: ina226@49 { /* u186 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <2000>;
+ };
+ vadj_fmc: ina226@4a { /* u184 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <2000>;
+ };
+ lpdmgtyavcc: ina226@4b { /* u177 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ lpdmgtyavtt: ina226@4c { /* u260 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <2000>;
+ };
+ lpdmgtyvccaux: ina226@4d { /* u234 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@4 { /* NC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ i2c@5 { /* NC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ user_si570: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ user_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5f>;
+ temperature-stability = <50>;
+ factory-fout = <100000000>;
+ clock-frequency = <100000000>;
+ clock-output-names = "fmc_si570";
+ };
+
+ };
+ /* 7 unused */
+ };
+};
+
+&i2c1 { /* i2c1 MIO 36-37 */
+ status = "okay";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ i2c-mux@74 { /* u35 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ ref_clk_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* Use for storing information about SC board */
+ eeprom: eeprom@54 { /* u34 - m24128 16kB */
+ compatible = "st,24c128", "atmel,24c128";
+ reg = <0x54>; /* & 0x5c */
+ };
+ ref_clk: clock-generator@5d { /* u32 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <33333333>;
+ clock-frequency = <33333333>;
+ clock-output-names = "ref_clk";
+ silabs,skip-recall;
+ };
+ };
+ fmcp1_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME connection to Samtec J51C */
+ /* expected eeprom 0x50 SE cards */
+ };
+ i2c@2 { /* NC - FIXME */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ lpddr4_si570_clk3_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ lpddr4_clk3: clock-generator@60 { /* u4 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk3";
+ };
+ };
+ lpddr4_si570_clk2_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ lpddr4_clk2: clock-generator@60 { /* u3 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk2";
+ };
+ };
+ lpddr4_si570_clk1_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ lpddr4_clk1: clock-generator@60 { /* u248 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk1";
+ };
+ };
+ qsfpdd_i2c: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* J1/J2 connectors */
+ };
+ idt8a34001_i2c: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* Via J310 connector */
+ idt_8a34001: phc@5b {
+ compatible = "idt,8a34001"; /* u219B */
+ reg = <0x5b>; /* FIXME not in schematics */
+ };
+ };
+ };
+};
+
+&usb0 { /* MIO52 - MIO63 */
+ status = "okay";
+ phy-names = "usb3-phy";
+ phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
+};
+
+&psgtr {
+ status = "okay";
+ /* sgmii, usb3 */
+ clocks = <&si5332_1>, <&si5332_2>;
+ clock-names = "ref0", "ref1";
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "peripheral";
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ maximum-speed = "super-speed";
+};
+
+&xilinx_ams {
+ status = "okay";
+};
+
+&ams_ps {
+ status = "okay";
+};
+
+&ams_pl {
+ status = "okay";
+};
+
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_8_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_8_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_34_grp", "gpio0_35_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_34_grp", "gpio0_35_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_9_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_9_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_36_grp", "gpio0_37_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_36_grp", "gpio0_37_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts
index 5c4acd17..cb9ef37 100644
--- a/arch/arm/dts/zynqmp-zc1254-revA.dts
+++ b/arch/arm/dts/zynqmp-zc1254-revA.dts
@@ -2,10 +2,10 @@
/*
* dts file for Xilinx ZynqMP ZC1254
*
- * (C) Copyright 2015 - 2020, Xilinx, Inc.
+ * (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
- * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
*/
/dts-v1/;
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index cffad44..e72ed50 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm015-dc1
*
- * (C) Copyright 2015 - 2021, Xilinx, Inc.
+ * (C) Copyright 2015 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -97,8 +98,12 @@
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
- phy0: ethernet-phy@0 {
- reg = <0>;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
};
};
@@ -349,11 +354,13 @@
&qspi {
status = "okay";
+ num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
#address-cells = <1>;
#size-cells = <1>;
- reg = <0x0>;
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index bb04778..160c6c5 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm016-dc2
*
- * (C) Copyright 2015 - 2021, Xilinx, Inc.
+ * (C) Copyright 2015 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -90,12 +91,16 @@
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem2_default>;
- phy0: ethernet-phy@5 {
- reg = <5>;
- ti,rx-internal-delay = <0x8>;
- ti,tx-internal-delay = <0xa>;
- ti,fifo-depth = <0x1>;
- ti,dp83867-rxctrl-strap-quirk;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@5 {
+ reg = <5>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ ti,dp83867-rxctrl-strap-quirk;
+ };
};
};
@@ -136,8 +141,7 @@
reg = <0x0>;
#address-cells = <0x2>;
#size-cells = <0x1>;
- nand-ecc-mode = "soft";
- nand-ecc-algo = "bch";
+ nand-ecc-mode = "hw";
nand-rb = <0>;
label = "main-storage-0";
nand-ecc-step-size = <1024>;
@@ -173,8 +177,7 @@
reg = <0x1>;
#address-cells = <0x2>;
#size-cells = <0x1>;
- nand-ecc-mode = "soft";
- nand-ecc-algo = "bch";
+ nand-ecc-mode = "hw";
nand-rb = <0>;
label = "main-storage-1";
nand-ecc-step-size = <1024>;
diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
index 69ad580..b97f7ee 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
@@ -88,8 +88,12 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
- phy0: ethernet-phy@0 { /* VSC8211 */
- reg = <0>;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@0 { /* VSC8211 */
+ reg = <0>;
+ };
};
};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
index 3017c9b..2b66abc 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@@ -116,17 +116,21 @@
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <ðernet_phy0>;
- ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
- reg = <0>;
- };
- ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
- reg = <7>;
- };
- ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
- reg = <3>;
- };
- ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
- reg = <8>;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
+ reg = <0>;
+ };
+ ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
+ reg = <7>;
+ };
+ ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
+ reg = <3>;
+ };
+ ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
+ reg = <8>;
+ };
};
};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index 74a5b02..b1857e1 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -4,7 +4,7 @@
*
* (C) Copyright 2015 - 2021, Xilinx, Inc.
*
- * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
* Michal Simek <michal.simek@amd.com>
*/
@@ -77,8 +77,12 @@
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem1_default>;
- phy0: ethernet-phy@0 {
- reg = <0>;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
};
};
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
index a84cd86..44d1b24 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP ZCU100 revC
*
- * (C) Copyright 2016 - 2021, Xilinx, Inc.
+ * (C) Copyright 2016 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Nathalie Chan King Choy
@@ -131,13 +132,13 @@
io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
};
- si5335_0: si5335_0 { /* clk0_usb - u23 */
+ si5335_0: si5335-0 { /* clk0_usb - u23 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
- si5335_1: si5335_1 { /* clk1_dp - u23 */
+ si5335_1: si5335-1 { /* clk1_dp - u23 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
index c0a4d91..c8f71a1 100644
--- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
+++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU102 Rev1.0
*
- * (C) Copyright 2016 - 2020, Xilinx, Inc.
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 79d67c4..e166c95 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP ZCU102 RevA
*
- * (C) Copyright 2015 - 2021, Xilinx, Inc.
+ * (C) Copyright 2015 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -602,7 +603,7 @@
reg = <0x5d>;
temperature-stability = <50>; /* copy from zc702 */
factory-fout = <156250000>;
- clock-frequency = <148500000>;
+ clock-frequency = <156250000>;
clock-output-names = "si570_mgt";
};
};
@@ -970,12 +971,13 @@
&qspi {
status = "okay";
- is-dual = <1>;
+ num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
- reg = <0x0>;
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts
index ce0a6e5..3c28130 100644
--- a/arch/arm/dts/zynqmp-zcu102-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revB.dts
@@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP ZCU102 RevB
*
- * (C) Copyright 2016 - 2020, Xilinx, Inc.
+ * (C) Copyright 2016 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts
index 90fbfca..cdfeea2 100644
--- a/arch/arm/dts/zynqmp-zcu104-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
@@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP ZCU104
*
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts
index 69470f8..4b942ac 100644
--- a/arch/arm/dts/zynqmp-zcu104-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revC.dts
@@ -1,8 +1,9 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx ZynqMP ZCU104
*
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index 7a8094a..b90ff61 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP ZCU106
*
- * (C) Copyright 2016 - 2021, Xilinx, Inc.
+ * (C) Copyright 2016 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -150,6 +151,18 @@
#clock-cells = <0>;
clock-frequency = <114285000>;
};
+
+ dpcon {
+ compatible = "dp-connector";
+ label = "P11";
+ type = "full-size";
+
+ port {
+ dpcon_in: endpoint {
+ remote-endpoint = <&dpsub_dp_out>;
+ };
+ };
+ };
};
&can1 {
@@ -592,7 +605,7 @@
reg = <0x5d>;
temperature-stability = <50>; /* copy from zc702 */
factory-fout = <156250000>;
- clock-frequency = <148500000>;
+ clock-frequency = <156250000>;
clock-output-names = "si570_mgt";
};
};
@@ -965,12 +978,13 @@
&qspi {
status = "okay";
- is-dual = <1>;
+ num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
- reg = <0x0>;
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
@@ -1065,4 +1079,12 @@
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
<&psgtr 0 PHY_TYPE_DP 1 3>;
+
+ ports {
+ port@5 {
+ dpsub_dp_out: endpoint {
+ remote-endpoint = <&dpcon_in>;
+ };
+ };
+ };
};
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
index c9ff99f..ba9e489 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP ZCU111
*
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -788,12 +789,13 @@
&qspi {
status = "okay";
- is-dual = <1>;
+ num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
- reg = <0x0>;
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts
index 9404c13..095c972 100644
--- a/arch/arm/dts/zynqmp-zcu1275-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts
@@ -5,7 +5,7 @@
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
- * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
*/
/dts-v1/;
diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts
index c06d262..4060dc3 100644
--- a/arch/arm/dts/zynqmp-zcu1275-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts
@@ -5,7 +5,7 @@
* (C) Copyright 2018 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
- * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
*/
/dts-v1/;
diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts
index 99ea143..4f85837 100644
--- a/arch/arm/dts/zynqmp-zcu1285-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts
@@ -5,7 +5,7 @@
* (C) Copyright 2018 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
- * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
*/
/dts-v1/;
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts
index 9b3ae67..22ad8d3 100644
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -57,7 +57,7 @@
leds {
compatible = "gpio-leds";
- heartbeat_led {
+ heartbeat-led {
label = "heartbeat";
gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
@@ -489,7 +489,7 @@
reg = <0x5d>;
temperature-stability = <50>;
factory-fout = <156250000>;
- clock-frequency = <148500000>;
+ clock-frequency = <156250000>;
clock-output-names = "si570_mgt";
};
};
@@ -643,12 +643,13 @@
&qspi {
status = "okay";
- is-dual = <1>;
+ num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */
#address-cells = <1>;
#size-cells = <1>;
- reg = <0>;
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts
index 43eeaec..575ff5b 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -57,7 +57,7 @@
leds {
compatible = "gpio-leds";
- heartbeat_led {
+ heartbeat-led {
label = "heartbeat";
gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
@@ -499,7 +499,7 @@
reg = <0x5d>;
temperature-stability = <50>;
factory-fout = <156250000>;
- clock-frequency = <148500000>;
+ clock-frequency = <156250000>;
clock-output-names = "si570_mgt";
};
};
@@ -653,12 +653,13 @@
&qspi {
status = "okay";
- is-dual = <1>;
+ num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */
#address-cells = <1>;
#size-cells = <1>;
- reg = <0x0>;
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
diff --git a/arch/arm/dts/zynqmp-zcu670-revA.dts b/arch/arm/dts/zynqmp-zcu670-revA.dts
new file mode 100644
index 0000000..edbbf0b
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu670-revA.dts
@@ -0,0 +1,669 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP ZCU670 (67DR)
+ *
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "ZynqMP ZCU670 RevA";
+ compatible = "xlnx,zynqmp-zcu670-revA", "xlnx,zynqmp-zcu670",
+ "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ nvmem0 = &eeprom;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &dcc;
+ spi0 = &qspi;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0 0 0x80000000>, <0x8 0x0 0x0 0x80000000>;
+ /* Another 4GB connected to PL */
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ sw1 {
+ label = "sw1";
+ gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <BTN_MISC>;
+ wakeup-source;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat-led {
+ label = "heartbeat"; /* DS1 */
+ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ ina226-vccint {
+ compatible = "iio-hwmon";
+ io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
+ };
+ ina226-vccint-io-bram-ps {
+ compatible = "iio-hwmon";
+ io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
+ };
+ ina226-vcc1v8 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
+ };
+ ina226-vcc1v2 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
+ };
+ ina226-vadj-fmc {
+ compatible = "iio-hwmon";
+ io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
+ };
+ ina226-mgtavcc {
+ compatible = "iio-hwmon";
+ io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
+ };
+ ina226-mgt1v2 {
+ compatible = "iio-hwmon";
+ io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
+ };
+ ina226-mgt1v8 {
+ compatible = "iio-hwmon";
+ io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
+ };
+ ina226-vccint-ams {
+ compatible = "iio-hwmon";
+ io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
+ };
+ ina226-dac-avtt {
+ compatible = "iio-hwmon";
+ io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
+ };
+ ina226-dac-avccaux {
+ compatible = "iio-hwmon";
+ io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;
+ };
+ ina226-adc-avcc {
+ compatible = "iio-hwmon";
+ io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
+ };
+ ina226-adc-avccaux {
+ compatible = "iio-hwmon";
+ io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;
+ };
+ ina226-dac-avcc {
+ compatible = "iio-hwmon";
+ io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
+ };
+
+ /* 48MHz reference crystal */
+ ref48: ref48M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ si5381_6: si5381_6 { /* refclk_usb3 - u43 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@c {
+ #phy-cells = <1>;
+ compatible = "ethernet-phy-id2000.a231";
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ ti,dp83867-rxctrl-strap-quirk;
+ reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */
+ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */
+ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */
+ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */
+ "", "", "BUTTON", "LED", "", /* 20 - 24 */
+ "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */
+ "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */
+ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */
+ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */
+ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */
+ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */
+ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */
+ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */
+ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */
+ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */
+ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */
+ "", "", /* 78 - 79 */
+ "", "", "", "", "", /* 80 - 84 */
+ "", "", "", "", "", /* 85 - 89 */
+ "", "", "", "", "", /* 90 - 94 */
+ "", "", "", "", "", /* 95 - 99 */
+ "", "", "", "", "", /* 100 - 104 */
+ "", "", "", "", "", /* 105 - 109 */
+ "", "", "", "", "", /* 110 - 114 */
+ "", "", "", "", "", /* 115 - 119 */
+ "", "", "", "", "", /* 120 - 124 */
+ "", "", "", "", "", /* 125 - 129 */
+ "", "", "", "", "", /* 130 - 134 */
+ "", "", "", "", "", /* 135 - 139 */
+ "", "", "", "", "", /* 140 - 144 */
+ "", "", "", "", "", /* 145 - 149 */
+ "", "", "", "", "", /* 150 - 154 */
+ "", "", "", "", "", /* 155 - 159 */
+ "", "", "", "", "", /* 160 - 164 */
+ "", "", "", "", "", /* 165 - 169 */
+ "", "", "", ""; /* 170 - 173 */
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ tca6416_u15: gpio@20 { /* u15 */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */
+ "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */
+ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */
+ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@75 { /* u17 */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* PS_PMBUS */
+ /* PMBUS_ALERT done via pca9544 */
+ vccint: ina226@40 { /* u65 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vccint";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ vccint_io_bram_ps: ina226@41 { /* u57 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vccint-io-bram-ps";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ vcc1v8: ina226@42 { /* u60 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vcc1v8";
+ reg = <0x42>;
+ shunt-resistor = <2000>;
+ };
+ vcc1v2: ina226@43 { /* u58 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vcc1v2";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ vadj_fmc: ina226@45 { /* u62 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vadj-fmc";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ mgtavcc: ina226@46 { /* u67 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-mgtavcc";
+ reg = <0x46>;
+ shunt-resistor = <2000>;
+ };
+ mgt1v2: ina226@47 { /* u63 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-mgt1v2";
+ reg = <0x47>;
+ shunt-resistor = <5000>; /* Not in schematics */
+ };
+ mgt1v8: ina226@48 { /* u64 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-mgt1v8";
+ reg = <0x48>;
+ shunt-resistor = <5000>;
+ };
+ vccint_ams: ina226@49 { /* u61 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vccint-ams";
+ reg = <0x49>;
+ shunt-resistor = <5000>;
+ };
+ dac_avtt: ina226@4a { /* u59 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-dac-avtt";
+ reg = <0x4a>;
+ shunt-resistor = <5000>;
+ };
+ dac_avccaux: ina226@4b { /* u124 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-dac-avccaux";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ adc_avcc: ina226@4c { /* u75 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-adc-avcc";
+ reg = <0x4c>;
+ shunt-resistor = <5000>;
+ };
+ adc_avccaux: ina226@4d { /* u71 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-adc-avccaux";
+ reg = <0x4d>;
+ shunt-resistor = <5000>;
+ };
+ dac_avcc: ina226@4e { /* u77 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-dac-avcc";
+ reg = <0x4e>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* NC */
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* u104 - ir35215 0x10/0x40 */
+ /* u127 - ir38164 0x1b/0x4b */
+ /* u112 - ir38164 0x13/0x43 */
+ /* u123 - ir38164 0x1c/0x4c */
+
+ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */
+ compatible = "infineon,irps5401";
+ reg = <0x44>; /* i2c addr 0x14 */
+ };
+ irps5401_45: irps5401@45 { /* IRPS5401 - u55 */
+ compatible = "infineon,irps5401";
+ reg = <0x45>; /* i2c addr 0x15 */
+ };
+ /* J21 header too */
+
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* SYSMON */
+ };
+ };
+ /* u38 MPS430 */
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ i2c-mux@74 {
+ compatible = "nxp,pca9548"; /* u20 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ i2c_eeprom: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom: eeprom@54 { /* u21 */
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+ i2c_si5381: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* SI5381 - u43 */
+ /* si5381: clock-generator@68 {
+ reg = <0x68>;
+ };*/
+ };
+ i2c_si570_user_c0: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>;
+ clock-frequency = <300000000>;
+ clock-output-names = "si570_user_c0";
+ };
+ };
+ i2c_si570_mgt: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <156250000>;
+ clock-frequency = <156250000>;
+ clock-output-names = "si570_mgt";
+ };
+ };
+ i2c_8a34001: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* U409B - 8a34001 */
+ };
+ i2c_clk104: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* CLK104_SDA */
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* RFMCP connector */
+ };
+ /* 7 NC */
+ };
+
+ i2c-mux@75 {
+ compatible = "nxp,pca9548"; /* u22 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* FMCP_HSPC_IIC */
+ };
+ i2c_si570_psrefclk: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <33333333>;
+ clock-frequency = <33333333>;
+ clock-output-names = "si570_ps_ref_clk";
+ silabs,skip-recall;
+ };
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* SYSMON */
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* DDR4 SODIMM */
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* SFP3 */
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* SFP2 */
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* SFP1 */
+ };
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* SFP0 */
+ };
+ };
+ /* u38 MPS430 */
+};
+
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_3_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_3_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+};
+
+&qspi {
+ status = "okay";
+ num-cs = <2>;
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ disable-wp;
+ /*
+ * This property should be removed for supporting UHS mode
+ */
+ no-1-8-v;
+ xlnx,mio-bank = <1>;
+};
+
+&psgtr {
+ status = "okay";
+ /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */
+ clocks = <&si5381_6>;
+ clock-names = "ref2";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+};
diff --git a/arch/arm/dts/zynqmp-zcu670-revB.dts b/arch/arm/dts/zynqmp-zcu670-revB.dts
new file mode 100644
index 0000000..97599c5
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu670-revB.dts
@@ -0,0 +1,672 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP ZCU670 (67DR) revB
+ *
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "ZynqMP ZCU670 RevB";
+ compatible = "xlnx,zynqmp-zcu670-revB", "xlnx,zynqmp-zcu670",
+ "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ nvmem0 = &eeprom;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &dcc;
+ spi0 = &qspi;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0 0 0x80000000>, <0x8 0x0 0x0 0x80000000>;
+ /* Another 4GB connected to PL */
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ sw1 {
+ label = "sw1";
+ gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <BTN_MISC>;
+ wakeup-source;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat-led {
+ label = "heartbeat"; /* DS1 */
+ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ ina226-vccint {
+ compatible = "iio-hwmon";
+ io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
+ };
+ ina226-vccint-io-bram-ps {
+ compatible = "iio-hwmon";
+ io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
+ };
+ ina226-vcc1v8 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
+ };
+ ina226-vcc1v2 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
+ };
+ ina226-vadj-fmc {
+ compatible = "iio-hwmon";
+ io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
+ };
+ ina226-mgtavcc {
+ compatible = "iio-hwmon";
+ io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
+ };
+ ina226-mgt1v2 {
+ compatible = "iio-hwmon";
+ io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
+ };
+ ina226-mgt1v8 {
+ compatible = "iio-hwmon";
+ io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
+ };
+ ina226-vccint-ams {
+ compatible = "iio-hwmon";
+ io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
+ };
+ ina226-dac-avtt {
+ compatible = "iio-hwmon";
+ io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
+ };
+ ina226-dac-avccaux {
+ compatible = "iio-hwmon";
+ io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;
+ };
+ ina226-adc-avcc {
+ compatible = "iio-hwmon";
+ io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
+ };
+ ina226-adc-avccaux {
+ compatible = "iio-hwmon";
+ io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;
+ };
+ ina226-dac-avcc {
+ compatible = "iio-hwmon";
+ io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
+ };
+
+ /* 48MHz reference crystal */
+ ref48: ref48M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ si5381_6: si5381_6 { /* refclk_usb3 - u43 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@c {
+ #phy-cells = <1>;
+ compatible = "ethernet-phy-id2000.a231";
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ ti,dp83867-rxctrl-strap-quirk;
+ reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */
+ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */
+ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */
+ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */
+ "", "", "BUTTON", "LED", "", /* 20 - 24 */
+ "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */
+ "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */
+ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */
+ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */
+ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */
+ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */
+ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */
+ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */
+ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */
+ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */
+ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */
+ "", "", /* 78 - 79 */
+ "", "", "", "", "", /* 80 - 84 */
+ "", "", "", "", "", /* 85 - 89 */
+ "", "", "", "", "", /* 90 - 94 */
+ "", "", "", "", "", /* 95 - 99 */
+ "", "", "", "", "", /* 100 - 104 */
+ "", "", "", "", "", /* 105 - 109 */
+ "", "", "", "", "", /* 110 - 114 */
+ "", "", "", "", "", /* 115 - 119 */
+ "", "", "", "", "", /* 120 - 124 */
+ "", "", "", "", "", /* 125 - 129 */
+ "", "", "", "", "", /* 130 - 134 */
+ "", "", "", "", "", /* 135 - 139 */
+ "", "", "", "", "", /* 140 - 144 */
+ "", "", "", "", "", /* 145 - 149 */
+ "", "", "", "", "", /* 150 - 154 */
+ "", "", "", "", "", /* 155 - 159 */
+ "", "", "", "", "", /* 160 - 164 */
+ "", "", "", "", "", /* 165 - 169 */
+ "", "", "", ""; /* 170 - 173 */
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ tca6416_u15: gpio@20 { /* u15 */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */
+ "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */
+ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */
+ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@75 { /* u17 */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* PS_PMBUS */
+ /* PMBUS_ALERT done via pca9544 */
+ vccint: ina226@40 { /* u65 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vccint";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ vccint_io_bram_ps: ina226@41 { /* u57 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vccint-io-bram-ps";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ vcc1v8: ina226@42 { /* u60 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vcc1v8";
+ reg = <0x42>;
+ shunt-resistor = <2000>;
+ };
+ vcc1v2: ina226@43 { /* u58 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vcc1v2";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ vadj_fmc: ina226@45 { /* u62 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vadj-fmc";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ mgtavcc: ina226@46 { /* u67 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-mgtavcc";
+ reg = <0x46>;
+ shunt-resistor = <2000>;
+ };
+ mgt1v2: ina226@47 { /* u63 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-mgt1v2";
+ reg = <0x47>;
+ shunt-resistor = <5000>; /* Not in schematics */
+ };
+ mgt1v8: ina226@48 { /* u64 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-mgt1v8";
+ reg = <0x48>;
+ shunt-resistor = <5000>;
+ };
+ vccint_ams: ina226@49 { /* u61 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vccint-ams";
+ reg = <0x49>;
+ shunt-resistor = <5000>;
+ };
+ dac_avtt: ina226@4a { /* u59 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-dac-avtt";
+ reg = <0x4a>;
+ shunt-resistor = <5000>;
+ };
+ dac_avccaux: ina226@4b { /* u124 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-dac-avccaux";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ adc_avcc: ina226@4c { /* u75 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-adc-avcc";
+ reg = <0x4c>;
+ shunt-resistor = <5000>;
+ };
+ adc_avccaux: ina226@4d { /* u71 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-adc-avccaux";
+ reg = <0x4d>;
+ shunt-resistor = <5000>;
+ };
+ dac_avcc: ina226@4e { /* u77 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-dac-avcc";
+ reg = <0x4e>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* NC */
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* u104 - ir35215 0x10/0x40 */
+ /* u127 - ir38164 0x1b/0x4b */
+ /* u112 - ir38164 0x13/0x43 */
+ /* u123 - ir38164 0x1c/0x4c */
+
+ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */
+ compatible = "infineon,irps5401";
+ reg = <0x44>; /* i2c addr 0x14 */
+ };
+ irps5401_45: irps5401@45 { /* IRPS5401 - u55 */
+ compatible = "infineon,irps5401";
+ reg = <0x45>; /* i2c addr 0x15 */
+ };
+ /* J21 header too */
+
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* SYSMON */
+ };
+ };
+ /* u38 MPS430 */
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ i2c-mux@74 {
+ compatible = "nxp,pca9548"; /* u20 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ i2c_eeprom: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom: eeprom@54 { /* u21 */
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+ i2c_si5381: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* SI5381 - u43 */
+ /* si5381: clock-generator@68 {
+ reg = <0x68>;
+ };*/
+ };
+ i2c_si570_user_c0: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>;
+ clock-frequency = <300000000>;
+ clock-output-names = "si570_user_c0";
+ };
+ };
+ i2c_si570_mgt: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <156250000>;
+ clock-frequency = <156250000>;
+ clock-output-names = "si570_mgt";
+ };
+ };
+ i2c_8a34001: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* U409B - 8a34001 */
+ };
+ i2c_clk104: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* CLK104_SDA */
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* RFMCP connector */
+ };
+ /* 7 NC */
+ };
+
+ i2c-mux@75 {
+ compatible = "nxp,pca9548"; /* u22 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* FMCP_HSPC_IIC */
+ };
+ i2c_si570_psrefclk: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <33333333>;
+ clock-frequency = <33333333>;
+ clock-output-names = "si570_ps_ref_clk";
+ silabs,skip-recall;
+ };
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* SYSMON */
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* DDR4 SODIMM */
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* SFP3 */
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* SFP2 */
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* SFP1 */
+ };
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* SFP0 */
+ };
+ };
+ /* u38 MPS430 */
+};
+
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_3_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_3_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+};
+
+&qspi {
+ status = "okay";
+ num-cs = <2>;
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ disable-wp;
+ /*
+ * This property should be removed for supporting UHS mode
+ */
+ no-1-8-v;
+ xlnx,mio-bank = <1>;
+ clk-phase-sd-hs = <120>, <60>;
+ clk-phase-uhs-sdr25 = <132>, <60>;
+ clk-phase-uhs-ddr50 = <153>, <48>;
+};
+
+&psgtr {
+ status = "okay";
+ /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */
+ clocks = <&si5381_6>;
+ clock-names = "ref2";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+};
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 1632be8..58a56bc 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -14,6 +14,8 @@
#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/xlnx-zynqmp-power.h>
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
@@ -22,6 +24,13 @@
#address-cells = <2>;
#size-cells = <2>;
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ bootscr-address = /bits/ 64 <0x20000000>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -111,11 +120,27 @@
};
};
- zynqmp_ipi: zynqmp_ipi {
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ rproc_0_fw_image: memory@3ed00000 {
+ no-map;
+ reg = <0x0 0x3ed00000 0x0 0x40000>;
+ };
+
+ rproc_1_fw_image: memory@3ef00000 {
+ no-map;
+ reg = <0x0 0x3ef00000 0x0 0x40000>;
+ };
+ };
+
+ zynqmp_ipi: zynqmp-ipi {
bootph-all;
compatible = "xlnx,zynqmp-ipi-mailbox";
interrupt-parent = <&gic>;
- interrupts = <0 35 4>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
xlnx,ipi-id = <0>;
#address-cells = <2>;
#size-cells = <2>;
@@ -145,10 +170,10 @@
pmu {
compatible = "arm,armv8-pmuv3";
interrupt-parent = <&gic>;
- interrupts = <0 143 4>,
- <0 144 4>,
- <0 145 4>,
- <0 146 4>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>,
<&cpu1>,
<&cpu2>,
@@ -176,29 +201,74 @@
bootph-all;
compatible = "xlnx,zynqmp-power";
interrupt-parent = <&gic>;
- interrupts = <0 35 4>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
mbox-names = "tx", "rx";
};
- nvmem_firmware {
+ nvmem-firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;
#size-cells = <1>;
- soc_revision: soc_revision@0 {
+ soc_revision: soc-revision@0 {
reg = <0x0 0x4>;
};
+ /* efuse access */
+ efuse_dna: efuse-dna@c {
+ reg = <0xc 0xc>;
+ };
+ efuse_usr0: efuse-usr0@20 {
+ reg = <0x20 0x4>;
+ };
+ efuse_usr1: efuse-usr1@24 {
+ reg = <0x24 0x4>;
+ };
+ efuse_usr2: efuse-usr2@28 {
+ reg = <0x28 0x4>;
+ };
+ efuse_usr3: efuse-usr3@2c {
+ reg = <0x2c 0x4>;
+ };
+ efuse_usr4: efuse-usr4@30 {
+ reg = <0x30 0x4>;
+ };
+ efuse_usr5: efuse-usr5@34 {
+ reg = <0x34 0x4>;
+ };
+ efuse_usr6: efuse-usr6@38 {
+ reg = <0x38 0x4>;
+ };
+ efuse_usr7: efuse-usr7@3c {
+ reg = <0x3c 0x4>;
+ };
+ efuse_miscusr: efuse-miscusr@40 {
+ reg = <0x40 0x4>;
+ };
+ efuse_chash: efuse-chash@50 {
+ reg = <0x50 0x4>;
+ };
+ efuse_pufmisc: efuse-pufmisc@54 {
+ reg = <0x54 0x4>;
+ };
+ efuse_sec: efuse-sec@58 {
+ reg = <0x58 0x4>;
+ };
+ efuse_spkid: efuse-spkid@5c {
+ reg = <0x5c 0x4>;
+ };
+ efuse_ppk0hash: efuse-ppk0hash@a0 {
+ reg = <0xa0 0x30>;
+ };
+ efuse_ppk1hash: efuse-ppk1hash@d0 {
+ reg = <0xd0 0x30>;
+ };
};
zynqmp_pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
};
- xlnx_aes: zynqmp-aes {
- compatible = "xlnx,zynqmp-aes";
- };
-
zynqmp_reset: reset-controller {
compatible = "xlnx,zynqmp-reset";
#reset-cells = <1>;
@@ -220,10 +290,10 @@
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
- interrupts = <1 13 0xf08>,
- <1 14 0xf08>,
- <1 11 0xf08>,
- <1 10 0xf08>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
edac {
@@ -236,7 +306,23 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
- power-domains = <&zynqmp_firmware PD_PL>;
+ };
+
+ remoteproc {
+ compatible = "xlnx,zynqmp-r5fss";
+ xlnx,cluster-mode = <1>;
+
+ r5f-0 {
+ compatible = "xlnx,zynqmp-r5f";
+ power-domains = <&zynqmp_firmware PD_RPU_0>;
+ memory-region = <&rproc_0_fw_image>;
+ };
+
+ r5f-1 {
+ compatible = "xlnx,zynqmp-r5f";
+ power-domains = <&zynqmp_firmware PD_RPU_1>;
+ memory-region = <&rproc_1_fw_image>;
+ };
};
amba: axi {
@@ -251,10 +337,11 @@
status = "disabled";
clock-names = "can_clk", "pclk";
reg = <0x0 0xff060000 0x0 0x1000>;
- interrupts = <0 23 4>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_CAN0>;
power-domains = <&zynqmp_firmware PD_CAN_0>;
};
@@ -263,10 +350,11 @@
status = "disabled";
clock-names = "can_clk", "pclk";
reg = <0x0 0xff070000 0x0 0x1000>;
- interrupts = <0 24 4>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_CAN1>;
power-domains = <&zynqmp_firmware PD_CAN_1>;
};
@@ -282,11 +370,11 @@
compatible = "arm,cci-400-pmu,r1";
reg = <0x9000 0x5000>;
interrupt-parent = <&gic>;
- interrupts = <0 123 4>,
- <0 123 4>,
- <0 123 4>,
- <0 123 4>,
- <0 123 4>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -296,11 +384,11 @@
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd500000 0x0 0x1000>;
interrupt-parent = <&gic>;
- interrupts = <0 124 4>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14e8>;
+ /* iommus = <&smmu 0x14e8>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@@ -309,11 +397,11 @@
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd510000 0x0 0x1000>;
interrupt-parent = <&gic>;
- interrupts = <0 125 4>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14e9>;
+ /* iommus = <&smmu 0x14e9>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@@ -322,11 +410,11 @@
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd520000 0x0 0x1000>;
interrupt-parent = <&gic>;
- interrupts = <0 126 4>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14ea>;
+ /* iommus = <&smmu 0x14ea>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@@ -335,11 +423,11 @@
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd530000 0x0 0x1000>;
interrupt-parent = <&gic>;
- interrupts = <0 127 4>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14eb>;
+ /* iommus = <&smmu 0x14eb>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@@ -348,11 +436,11 @@
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd540000 0x0 0x1000>;
interrupt-parent = <&gic>;
- interrupts = <0 128 4>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14ec>;
+ /* iommus = <&smmu 0x14ec>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@@ -361,11 +449,11 @@
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd550000 0x0 0x1000>;
interrupt-parent = <&gic>;
- interrupts = <0 129 4>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14ed>;
+ /* iommus = <&smmu 0x14ed>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@@ -374,11 +462,11 @@
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd560000 0x0 0x1000>;
interrupt-parent = <&gic>;
- interrupts = <0 130 4>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14ee>;
+ /* iommus = <&smmu 0x14ee>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@@ -387,11 +475,11 @@
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd570000 0x0 0x1000>;
interrupt-parent = <&gic>;
- interrupts = <0 131 4>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14ef>;
+ /* iommus = <&smmu 0x14ef>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@@ -404,7 +492,7 @@
<0x0 0xf9060000 0x0 0x20000>;
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <1 9 0xf04>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
gpu: gpu@fd4b0000 {
@@ -412,7 +500,12 @@
compatible = "xlnx,zynqmp-mali", "arm,mali-400";
reg = <0x0 0xfd4b0000 0x0 0x10000>;
interrupt-parent = <&gic>;
- interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1";
clock-names = "bus", "core";
power-domains = <&zynqmp_firmware PD_GPU>;
@@ -427,11 +520,11 @@
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffa80000 0x0 0x1000>;
interrupt-parent = <&gic>;
- interrupts = <0 77 4>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x868>;
+ /* iommus = <&smmu 0x868>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@@ -440,11 +533,11 @@
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffa90000 0x0 0x1000>;
interrupt-parent = <&gic>;
- interrupts = <0 78 4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x869>;
+ /* iommus = <&smmu 0x869>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@@ -453,11 +546,11 @@
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffaa0000 0x0 0x1000>;
interrupt-parent = <&gic>;
- interrupts = <0 79 4>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x86a>;
+ /* iommus = <&smmu 0x86a>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@@ -466,11 +559,11 @@
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffab0000 0x0 0x1000>;
interrupt-parent = <&gic>;
- interrupts = <0 80 4>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x86b>;
+ /* iommus = <&smmu 0x86b>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@@ -479,11 +572,11 @@
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffac0000 0x0 0x1000>;
interrupt-parent = <&gic>;
- interrupts = <0 81 4>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x86c>;
+ /* iommus = <&smmu 0x86c>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@@ -492,11 +585,11 @@
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffad0000 0x0 0x1000>;
interrupt-parent = <&gic>;
- interrupts = <0 82 4>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x86d>;
+ /* iommus = <&smmu 0x86d>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@@ -505,11 +598,11 @@
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffae0000 0x0 0x1000>;
interrupt-parent = <&gic>;
- interrupts = <0 83 4>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x86e>;
+ /* iommus = <&smmu 0x86e>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@@ -518,11 +611,11 @@
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffaf0000 0x0 0x1000>;
interrupt-parent = <&gic>;
- interrupts = <0 84 4>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x86f>;
+ /* iommus = <&smmu 0x86f>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@@ -530,7 +623,7 @@
compatible = "xlnx,zynqmp-ddrc-2.40a";
reg = <0x0 0xfd070000 0x0 0x30000>;
interrupt-parent = <&gic>;
- interrupts = <0 112 4>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
};
nand0: nand-controller@ff100000 {
@@ -539,10 +632,10 @@
reg = <0x0 0xff100000 0x0 0x1000>;
clock-names = "controller", "bus";
interrupt-parent = <&gic>;
- interrupts = <0 14 4>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- iommus = <&smmu 0x872>;
+ /* iommus = <&smmu 0x872>; */
power-domains = <&zynqmp_firmware PD_NAND>;
};
@@ -550,12 +643,11 @@
compatible = "xlnx,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
- interrupts = <0 57 4>, <0 57 4>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0b0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
- #address-cells = <1>;
- #size-cells = <0>;
- iommus = <&smmu 0x874>;
+ /* iommus = <&smmu 0x874>; */
power-domains = <&zynqmp_firmware PD_ETH_0>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
reset-names = "gem0_rst";
@@ -565,12 +657,11 @@
compatible = "xlnx,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
- interrupts = <0 59 4>, <0 59 4>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0c0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
- #address-cells = <1>;
- #size-cells = <0>;
- iommus = <&smmu 0x875>;
+ /* iommus = <&smmu 0x875>; */
power-domains = <&zynqmp_firmware PD_ETH_1>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
reset-names = "gem1_rst";
@@ -580,12 +671,11 @@
compatible = "xlnx,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
- interrupts = <0 61 4>, <0 61 4>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0d0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
- #address-cells = <1>;
- #size-cells = <0>;
- iommus = <&smmu 0x876>;
+ /* iommus = <&smmu 0x876>; */
power-domains = <&zynqmp_firmware PD_ETH_2>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
reset-names = "gem2_rst";
@@ -595,12 +685,11 @@
compatible = "xlnx,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
- interrupts = <0 63 4>, <0 63 4>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0e0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
- #address-cells = <1>;
- #size-cells = <0>;
- iommus = <&smmu 0x877>;
+ /* iommus = <&smmu 0x877>; */
power-domains = <&zynqmp_firmware PD_ETH_3>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
reset-names = "gem3_rst";
@@ -612,7 +701,7 @@
#gpio-cells = <0x2>;
gpio-controller;
interrupt-parent = <&gic>;
- interrupts = <0 16 4>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0xff0a0000 0x0 0x1000>;
@@ -623,7 +712,7 @@
compatible = "cdns,i2c-r1p14";
status = "disabled";
interrupt-parent = <&gic>;
- interrupts = <0 17 4>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
reg = <0x0 0xff020000 0x0 0x1000>;
#address-cells = <1>;
@@ -635,7 +724,7 @@
compatible = "cdns,i2c-r1p14";
status = "disabled";
interrupt-parent = <&gic>;
- interrupts = <0 18 4>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
reg = <0x0 0xff030000 0x0 0x1000>;
#address-cells = <1>;
@@ -659,17 +748,17 @@
msi-controller;
device_type = "pci";
interrupt-parent = <&gic>;
- interrupts = <0 118 4>,
- <0 117 4>,
- <0 116 4>,
- <0 115 4>, /* MSI_1 [63...32] */
- <0 114 4>; /* MSI_0 [31...0] */
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, /* MSI_1 [63...32] */
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; /* MSI_0 [31...0] */
interrupt-names = "misc", "dummy", "intx",
"msi1", "msi0";
msi-parent = <&pcie>;
reg = <0x0 0xfd0e0000 0x0 0x1000>,
<0x0 0xfd480000 0x0 0x1000>,
- <0x80 0x00000000 0x0 0x1000000>;
+ <0x80 0x00000000 0x0 0x10000000>;
reg-names = "breg", "pcireg", "cfg";
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */
<0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
@@ -679,7 +768,7 @@
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
- iommus = <&smmu 0x4d0>;
+ /* iommus = <&smmu 0x4d0>; */
power-domains = <&zynqmp_firmware PD_PCIE>;
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
@@ -693,14 +782,14 @@
compatible = "xlnx,zynqmp-qspi-1.0";
status = "disabled";
clock-names = "ref_clk", "pclk";
- interrupts = <0 15 4>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
num-cs = <1>;
reg = <0x0 0xff0f0000 0x0 0x1000>,
<0x0 0xc0000000 0x0 0x8000000>;
#address-cells = <1>;
#size-cells = <0>;
- iommus = <&smmu 0x873>;
+ /* iommus = <&smmu 0x873>; */
power-domains = <&zynqmp_firmware PD_QSPI>;
};
@@ -718,7 +807,8 @@
status = "disabled";
reg = <0x0 0xffa60000 0x0 0x100>;
interrupt-parent = <&gic>;
- interrupts = <0 26 4>, <0 27 4>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "alarm", "sec";
calibration = <0x7FFF>;
};
@@ -728,11 +818,10 @@
status = "disabled";
reg = <0x0 0xfd0c0000 0x0 0x2000>;
interrupt-parent = <&gic>;
- interrupts = <0 133 4>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&zynqmp_firmware PD_SATA>;
resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
- iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
- <&smmu 0x4c2>, <&smmu 0x4c3>;
+ /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */
/* dma-coherent; */
};
@@ -741,10 +830,10 @@
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
interrupt-parent = <&gic>;
- interrupts = <0 48 4>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff160000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
- iommus = <&smmu 0x870>;
+ /* iommus = <&smmu 0x870>; */
#clock-cells = <1>;
clock-output-names = "clk_out_sd0", "clk_in_sd0";
power-domains = <&zynqmp_firmware PD_SD_0>;
@@ -756,10 +845,10 @@
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
interrupt-parent = <&gic>;
- interrupts = <0 49 4>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff170000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
- iommus = <&smmu 0x871>;
+ /* iommus = <&smmu 0x871>; */
#clock-cells = <1>;
clock-output-names = "clk_out_sd1", "clk_in_sd1";
power-domains = <&zynqmp_firmware PD_SD_1>;
@@ -773,18 +862,30 @@
status = "disabled";
#global-interrupts = <1>;
interrupt-parent = <&gic>;
- interrupts = <0 155 4>,
- <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
- <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
- <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
- <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
};
spi0: spi@ff040000 {
compatible = "cdns,spi-r1p6";
status = "disabled";
interrupt-parent = <&gic>;
- interrupts = <0 19 4>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff040000 0x0 0x1000>;
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
@@ -796,7 +897,7 @@
compatible = "cdns,spi-r1p6";
status = "disabled";
interrupt-parent = <&gic>;
- interrupts = <0 20 4>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff050000 0x0 0x1000>;
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
@@ -808,7 +909,9 @@
compatible = "cdns,ttc";
status = "disabled";
interrupt-parent = <&gic>;
- interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff110000 0x0 0x1000>;
timer-width = <32>;
power-domains = <&zynqmp_firmware PD_TTC_0>;
@@ -818,7 +921,9 @@
compatible = "cdns,ttc";
status = "disabled";
interrupt-parent = <&gic>;
- interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff120000 0x0 0x1000>;
timer-width = <32>;
power-domains = <&zynqmp_firmware PD_TTC_1>;
@@ -828,7 +933,9 @@
compatible = "cdns,ttc";
status = "disabled";
interrupt-parent = <&gic>;
- interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff130000 0x0 0x1000>;
timer-width = <32>;
power-domains = <&zynqmp_firmware PD_TTC_2>;
@@ -838,7 +945,9 @@
compatible = "cdns,ttc";
status = "disabled";
interrupt-parent = <&gic>;
- interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff140000 0x0 0x1000>;
timer-width = <32>;
power-domains = <&zynqmp_firmware PD_TTC_3>;
@@ -849,7 +958,7 @@
compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
status = "disabled";
interrupt-parent = <&gic>;
- interrupts = <0 21 4>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff000000 0x0 0x1000>;
clock-names = "uart_clk", "pclk";
power-domains = <&zynqmp_firmware PD_UART_0>;
@@ -860,7 +969,7 @@
compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
status = "disabled";
interrupt-parent = <&gic>;
- interrupts = <0 22 4>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff010000 0x0 0x1000>;
clock-names = "uart_clk", "pclk";
power-domains = <&zynqmp_firmware PD_UART_1>;
@@ -887,12 +996,13 @@
reg = <0x0 0xfe200000 0x0 0x40000>;
interrupt-parent = <&gic>;
interrupt-names = "dwc_usb3", "otg", "hiber";
- interrupts = <0 65 4>, <0 69 4>, <0 75 4>;
- iommus = <&smmu 0x860>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ /* iommus = <&smmu 0x860>; */
snps,quirk-frame-length-adjustment = <0x20>;
clock-names = "ref";
snps,enable_guctl1_ipd_quirk;
- snps,xhci-stream-quirk;
snps,resume-hs-terminations;
/* dma-coherent; */
};
@@ -918,12 +1028,13 @@
reg = <0x0 0xfe300000 0x0 0x40000>;
interrupt-parent = <&gic>;
interrupt-names = "dwc_usb3", "otg", "hiber";
- interrupts = <0 70 4>, <0 74 4>, <0 76 4>;
- iommus = <&smmu 0x861>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ /* iommus = <&smmu 0x861>; */
snps,quirk-frame-length-adjustment = <0x20>;
clock-names = "ref";
snps,enable_guctl1_ipd_quirk;
- snps,xhci-stream-quirk;
snps,resume-hs-terminations;
/* dma-coherent; */
};
@@ -933,7 +1044,7 @@
compatible = "cdns,wdt-r1p2";
status = "disabled";
interrupt-parent = <&gic>;
- interrupts = <0 113 1>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
reg = <0x0 0xfd4d0000 0x0 0x1000>;
timeout-sec = <60>;
reset-on-timeout;
@@ -943,7 +1054,7 @@
compatible = "cdns,wdt-r1p2";
status = "disabled";
interrupt-parent = <&gic>;
- interrupts = <0 52 1>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>;
reg = <0x0 0xff150000 0x0 0x1000>;
timeout-sec = <10>;
};
@@ -952,7 +1063,7 @@
compatible = "xlnx,zynqmp-ams";
status = "disabled";
interrupt-parent = <&gic>;
- interrupts = <0 56 4>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xffa50000 0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
@@ -969,8 +1080,6 @@
compatible = "xlnx,zynqmp-ams-pl";
status = "disabled";
reg = <0x400 0x400>;
- #address-cells = <1>;
- #size-cells = <0>;
};
};
@@ -978,10 +1087,11 @@
compatible = "xlnx,zynqmp-dpdma";
status = "disabled";
reg = <0x0 0xfd4c0000 0x0 0x1000>;
- interrupts = <0 122 4>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clock-names = "axi_clk";
power-domains = <&zynqmp_firmware PD_DP>;
+ /* iommus = <&smmu 0xce4>; */
#dma-cells = <1>;
};
@@ -994,8 +1104,9 @@
<0x0 0xfd4ab000 0x0 0x1000>,
<0x0 0xfd4ac000 0x0 0x1000>;
reg-names = "dp", "blend", "av_buf", "aud";
- interrupts = <0 119 4>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
+ /* iommus = <&smmu 0xce3>; */
clock-names = "dp_apb_clk", "dp_aud_clk",
"dp_vtc_pixel_clk_in";
power-domains = <&zynqmp_firmware PD_DP>;
@@ -1005,6 +1116,30 @@
<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
<&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+ port@1 {
+ reg = <1>;
+ };
+ port@2 {
+ reg = <2>;
+ };
+ port@3 {
+ reg = <3>;
+ };
+ port@4 {
+ reg = <4>;
+ };
+ port@5 {
+ reg = <5>;
+ };
+ };
};
};
};
diff --git a/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h
index 7bcafba..8e3d55f 100644
--- a/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h
+++ b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h
@@ -4,7 +4,7 @@
*
* Clock synthesizer header
*
- * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2016, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef __CLK_SYNTHESIZER_H
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index 67400c2..13960db 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -4,7 +4,7 @@
*
* clock header
*
- * Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef _CLOCKS_H_
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index e5ad507..adb574e 100644
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -4,7 +4,7 @@
*
* AM33xx clock define
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef _CLOCKS_AM33XX_H_
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index b33e6f7..8ec2585 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -4,7 +4,7 @@
*
* AM33xx specific header file
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _AM33XX_CPU_H
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 1a03107..6e7a62b 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -4,7 +4,7 @@
*
* ddr specific header
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _DDR_DEFS_H
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index 387f053..33ee915 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -4,7 +4,7 @@
*
* hardware specific header
*
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef __AM33XX_HARDWARE_H
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
index 878ef3e..de597c2 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
@@ -4,7 +4,7 @@
*
* AM33xx hardware specific header
*
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef __AM33XX_HARDWARE_AM33XX_H
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
index 0b73ebd..8786d8c 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
@@ -4,7 +4,7 @@
*
* AM43xx hardware specific header
*
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef __AM43XX_HARDWARE_AM43XX_H
diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
index b1b1896..ed60abf 100644
--- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
@@ -1,7 +1,7 @@
/*
* mmc_host_def.h
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h
index ebb2d30..f704afa 100644
--- a/arch/arm/include/asm/arch-am33xx/mux.h
+++ b/arch/arm/include/asm/arch-am33xx/mux.h
@@ -1,7 +1,7 @@
/*
* mux.h
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/include/asm/arch-am33xx/mux_am33xx.h b/arch/arm/include/asm/arch-am33xx/mux_am33xx.h
index 26bd4b4..c702e4a 100644
--- a/arch/arm/include/asm/arch-am33xx/mux_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/mux_am33xx.h
@@ -1,7 +1,7 @@
/*
* mux_am33xx.h
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
index f74ae74..24f0041 100644
--- a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
@@ -2,7 +2,7 @@
/*
* mux_am43xx.h
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef _MUX_AM43XX_H_
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h
index 53046de..71a84fe 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -2,7 +2,7 @@
/*
* omap.h
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*
* Author:
* Chandan Nath <chandan.nath@ti.com>
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index be17aad..513cdac 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -4,7 +4,7 @@
*
* System information header
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _SYS_PROTO_H_
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ppa.h b/arch/arm/include/asm/arch-fsl-layerscape/ppa.h
deleted file mode 100644
index f0c4a84..0000000
--- a/arch/arm/include/asm/arch-fsl-layerscape/ppa.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2016 NXP Semiconductor, Inc.
- */
-
-#ifndef __FSL_PPA_H_
-#define __FSL_PPA_H_
-
-#ifdef CONFIG_FSL_LS_PPA
-int ppa_init(void);
-#endif
-#endif
diff --git a/arch/arm/include/asm/arch-meson/clock-a1.h b/arch/arm/include/asm/arch-meson/clock-a1.h
new file mode 100644
index 0000000..f6795f5
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/clock-a1.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 - AmLogic, Inc.
+ * Copyright 2023 (C) SberDevices, Inc.
+ */
+
+#ifndef _ARCH_MESON_CLOCK_A1_H_
+#define _ARCH_MESON_CLOCK_A1_H_
+
+/*
+ * Clock controller register offsets
+ */
+#define A1_SYS_OSCIN_CTRL 0x0
+#define A1_SYS_CLK_CTRL0 0x10
+#define A1_SYS_CLK_EN0 0x1c
+#define A1_SAR_ADC_CLK_CTR 0xc0
+#define A1_SPIFC_CLK_CTRL 0xd8
+#define A1_USB_BUSCLK_CTRL 0xdc
+#define A1_SD_EMMC_CLK_CTRL 0xe0
+
+#define A1_ANACTRL_FIXPLL_CTRL0 0x0
+
+#endif /* _ARCH_MESON_CLOCK_A1_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/emif4.h b/arch/arm/include/asm/arch-omap3/emif4.h
index bac43b2..397bb47 100644
--- a/arch/arm/include/asm/arch-omap3/emif4.h
+++ b/arch/arm/include/asm/arch-omap3/emif4.h
@@ -4,7 +4,7 @@
* Vaibhav Hiremath <hvaibhav@ti.com>
*
* Copyright (C) 2010
- * Texas Instruments Incorporated - http://www.ti.com/
+ * Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef _EMIF_H_
diff --git a/arch/arm/include/asm/arch-omap4/ehci.h b/arch/arm/include/asm/arch-omap4/ehci.h
index 30bdaad..e8fe88f 100644
--- a/arch/arm/include/asm/arch-omap4/ehci.h
+++ b/arch/arm/include/asm/arch-omap4/ehci.h
@@ -4,7 +4,7 @@
* Based on LINUX KERNEL
* drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com
* Author: Govindraj R <govindraj.raja@ti.com>
*/
diff --git a/arch/arm/include/asm/arch-omap4/hardware.h b/arch/arm/include/asm/arch-omap4/hardware.h
index 48dc809..67e3dae 100644
--- a/arch/arm/include/asm/arch-omap4/hardware.h
+++ b/arch/arm/include/asm/arch-omap4/hardware.h
@@ -4,7 +4,7 @@
*
* hardware specific header
*
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef __OMAP_HARDWARE_H
diff --git a/arch/arm/include/asm/arch-omap5/ehci.h b/arch/arm/include/asm/arch-omap5/ehci.h
index 1790b92..3c52a76 100644
--- a/arch/arm/include/asm/arch-omap5/ehci.h
+++ b/arch/arm/include/asm/arch-omap5/ehci.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com*
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com*
* Author: Govindraj R <govindraj.raja@ti.com>
*/
diff --git a/arch/arm/include/asm/arch-omap5/hardware.h b/arch/arm/include/asm/arch-omap5/hardware.h
index b6d26e9..c948c0e 100644
--- a/arch/arm/include/asm/arch-omap5/hardware.h
+++ b/arch/arm/include/asm/arch-omap5/hardware.h
@@ -4,7 +4,7 @@
*
* hardware specific header
*
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef __OMAP_HARDWARE_H
diff --git a/arch/arm/include/asm/arch-rk3066/boot0.h b/arch/arm/include/asm/arch-rk3066/boot0.h
index 28c0fb9..6bf3828 100644
--- a/arch/arm/include/asm/arch-rk3066/boot0.h
+++ b/arch/arm/include/asm/arch-rk3066/boot0.h
@@ -3,6 +3,81 @@
#ifndef __ASM_ARCH_BOOT0_H__
#define __ASM_ARCH_BOOT0_H__
-#include <asm/arch-rockchip/boot0.h>
+#include <asm/arch-rockchip/boot_mode.h>
+/*
+ * Execution starts on the instruction following this 4-byte header
+ * (containing the magic 'RK30'). This magic constant will be written into
+ * the final image by the rkimage tool, but we need to reserve space for it here.
+ */
+#ifdef CONFIG_SPL_BUILD
+ b 1f /* if overwritten, entry-address is at the next word */
+1:
+#endif
+
+#if CONFIG_IS_ENABLED(ROCKCHIP_EARLYRETURN_TO_BROM)
+/*
+ * Keep track of the re-entries with help of the lr register.
+ * This binary can be re-used and called from various BROM functions.
+ * Only when it's called from the part that handles SPI, NAND or EMMC
+ * hardware it needs to early return to BROM ones.
+ * In download mode when it handles data on USB OTG and UART0
+ * this section must be skipped.
+ */
+ ldr r3, =CONFIG_ROCKCHIP_BOOT_LR_REG
+ cmp lr, r3 /* if (LR != CONFIG_ROCKCHIP_BOOT_LR_REG) */
+ bne reset /* goto reset; */
+/*
+ * Unlike newer Rockchip SoC models the rk3066 BROM code does not have built-in
+ * support to enter download mode on return to BROM. This binary must check
+ * the boot mode register for the BOOT_BROM_DOWNLOAD flag and reset if it's set.
+ * It then returns to BROM to the end of the function that reads boot blocks.
+ * From there the BROM code goes into a download mode and waits for data
+ * on USB OTG and UART0.
+ */
+ ldr r2, =BOOT_BROM_DOWNLOAD
+ ldr r3, =CONFIG_ROCKCHIP_BOOT_MODE_REG
+ ldr r0, [r3] /* if (readl(CONFIG_ROCKCHIP_BOOT_MODE_REG) != */
+ cmp r0, r2 /* BOOT_BROM_DOWNLOAD) { */
+ bne early_return /* goto early_return; */
+ /* } else { */
+ mov r0, #0
+ str r0, [r3] /* writel(0, CONFIG_ROCKCHIP_BOOT_MODE_REG); */
+
+ ldr r3, =CONFIG_ROCKCHIP_BOOT_RETURN_REG
+ bx r3 /* return to CONFIG_ROCKCHIP_BOOT_RETURN_REG;*/
+ /* } */
+early_return:
+ bx lr /* return to LR in BROM */
+
+SAVE_SP_ADDR:
+ .word 0
+
+ .globl save_boot_params
+save_boot_params:
+ push {r1-r12, lr}
+ ldr r0, =SAVE_SP_ADDR
+ str sp, [r0]
+ b save_boot_params_ret
+
+ .globl back_to_bootrom
+back_to_bootrom:
+ ldr r0, =SAVE_SP_ADDR
+ ldr sp, [r0]
+ mov r0, #0
+ pop {r1-r12, pc}
+#endif
+
+#if (defined(CONFIG_SPL_BUILD))
+/* U-Boot proper of armv7 does not need this */
+ b reset
+#endif
+
+/*
+ * For armv7, the addr '_start' will be used as vector start address
+ * and is written to the VBAR register, which needs to aligned to 0x20.
+ */
+ .align(5), 0x0
+_start:
+ ARM_VECTORS
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h
index 30f5680..cad25c5 100644
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -3,6 +3,8 @@
* Configuration settings for the Allwinner A64 (sun50i) CPU
*/
+#include <asm/arch/cpu.h>
+
#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_SPL_BUILD)
/* reserve space for BOOT0 header information */
b reset
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
index 2cfd540..fcc8966 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -9,6 +9,7 @@
#define _SUNXI_CLOCK_H
#include <linux/types.h>
+#include <asm/arch/cpu.h>
#define CLK_GATE_OPEN 0x1
#define CLK_GATE_CLOSE 0x0
@@ -16,7 +17,7 @@
/* clock control module regs definition */
#if defined(CONFIG_MACH_SUN8I_A83T)
#include <asm/arch/clock_sun8i_a83t.h>
-#elif defined(CONFIG_SUN50I_GEN_H6)
+#elif defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
#include <asm/arch/clock_sun50i_h6.h>
#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNIV)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
index 37df441..a84a57e 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -228,6 +228,7 @@
/* pll1 bit field */
#define CCM_PLL1_CTRL_EN BIT(31)
+#define CCM_PLL1_LDO_EN BIT(30)
#define CCM_PLL1_LOCK_EN BIT(29)
#define CCM_PLL1_LOCK BIT(28)
#define CCM_PLL1_OUT_EN BIT(27)
@@ -248,6 +249,8 @@
#define CCM_PLL6_CTRL_EN BIT(31)
#define CCM_PLL6_LOCK_EN BIT(29)
#define CCM_PLL6_LOCK BIT(28)
+#define CCM_PLL6_CTRL_P0_SHIFT 16
+#define CCM_PLL6_CTRL_P0_MASK (0x7 << CCM_PLL6_CTRL_P0_SHIFT)
#define CCM_PLL6_CTRL_N_SHIFT 8
#define CCM_PLL6_CTRL_N_MASK (0xff << CCM_PLL6_CTRL_N_SHIFT)
#define CCM_PLL6_CTRL_DIV1_SHIFT 0
@@ -263,7 +266,7 @@
#define CCM_CPU_AXI_AXI_MASK 0x3
#define CCM_CPU_AXI_DEFAULT_FACTORS 0x301
-#ifdef CONFIG_MACH_SUN50I_H6
+#ifdef CONFIG_MACH_SUN50I_H6 /* H6 */
#define CCM_PLL6_DEFAULT 0xa0006300
/* psi_ahb1_ahb2 bit field */
@@ -274,7 +277,7 @@
/* apb1 bit field */
#define CCM_APB1_DEFAULT 0x03000102
-#elif CONFIG_MACH_SUN50I_H616
+#elif CONFIG_MACH_SUN50I_H616 /* H616 */
#define CCM_PLL6_DEFAULT 0xa8003100
/* psi_ahb1_ahb2 bit field */
@@ -285,6 +288,11 @@
/* apb1 bit field */
#define CCM_APB1_DEFAULT 0x03000102
+#elif CONFIG_MACH_SUN8I_R528 /* R528 */
+#define CCM_PLL6_DEFAULT 0xe8216300
+#define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000002
+//#define CCM_AHB3_DEFAULT 0x03000002
+#define CCM_APB1_DEFAULT 0x03000102
#endif
/* apb2 bit field */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
index b08f202..768c657 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -10,6 +10,8 @@
#include <asm/arch/cpu_sun9i.h>
#elif defined(CONFIG_SUN50I_GEN_H6)
#include <asm/arch/cpu_sun50i_h6.h>
+#elif defined(CONFIG_SUNXI_GEN_NCAT2)
+#include <asm/arch/cpu_sunxi_ncat2.h>
#else
#include <asm/arch/cpu_sun4i.h>
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index f7ecc79..3daee2f 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -91,7 +91,6 @@
#define SUNXI_CCM_BASE 0x01c20000
#define SUNXI_INTC_BASE 0x01c20400
-#define SUNXI_PIO_BASE 0x01c20800
#define SUNXI_TIMER_BASE 0x01c20c00
#ifndef CONFIG_SUNXI_GEN_SUN6I
#define SUNXI_PWM_BASE 0x01c20e00
@@ -129,20 +128,6 @@
#define SUNXI_CPUCFG_BASE 0x01c25c00
#endif
-#ifdef CONFIG_MACH_SUNIV
-#define SUNXI_UART0_BASE 0x01c25000
-#define SUNXI_UART1_BASE 0x01c25400
-#define SUNXI_UART2_BASE 0x01c25800
-#else
-#define SUNXI_UART0_BASE 0x01c28000
-#define SUNXI_UART1_BASE 0x01c28400
-#define SUNXI_UART2_BASE 0x01c28800
-#endif
-#define SUNXI_UART3_BASE 0x01c28c00
-#define SUNXI_UART4_BASE 0x01c29000
-#define SUNXI_UART5_BASE 0x01c29400
-#define SUNXI_UART6_BASE 0x01c29800
-#define SUNXI_UART7_BASE 0x01c29c00
#define SUNXI_PS2_0_BASE 0x01c2a000
#define SUNXI_PS2_1_BASE 0x01c2a400
@@ -209,8 +194,6 @@
#endif
#define SUNXI_R_TWI_BASE 0x01f02400
-#define SUNXI_R_UART_BASE 0x01f02800
-#define SUNXI_R_PIO_BASE 0x01f02c00
#define SUN6I_P2WI_BASE 0x01f03400
#define SUNXI_RSB_BASE 0x01f03400
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
index d9cf8ae..15ee092 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
@@ -22,7 +22,6 @@
#define SUNXI_SIDC_BASE 0x03006000
#define SUNXI_SID_BASE 0x03006200
#define SUNXI_TIMER_BASE 0x03009000
-#define SUNXI_PIO_BASE 0x0300B000
#define SUNXI_PSI_BASE 0x0300C000
#define SUNXI_GIC400_BASE 0x03020000
@@ -43,10 +42,6 @@
#define SUNXI_DRAM_PHY0_BASE 0x04800000
#endif
-#define SUNXI_UART0_BASE 0x05000000
-#define SUNXI_UART1_BASE 0x05000400
-#define SUNXI_UART2_BASE 0x05000800
-#define SUNXI_UART3_BASE 0x05000C00
#define SUNXI_TWI0_BASE 0x05002000
#define SUNXI_TWI1_BASE 0x05002400
#define SUNXI_TWI2_BASE 0x05002800
@@ -68,8 +63,6 @@
#define SUNXI_R_CPUCFG_BASE 0x07000400
#define SUNXI_PRCM_BASE 0x07010000
#define SUNXI_R_WDOG_BASE 0x07020400
-#define SUNXI_R_PIO_BASE 0x07022000
-#define SUNXI_R_UART_BASE 0x07080000
#define SUNXI_R_TWI_BASE 0x07081400
#ifndef __ASSEMBLY__
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
index 9c2d11b..2bf2675 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -81,18 +81,11 @@
/* APB0 Module */
#define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000)
#define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400)
-#define SUNXI_PIO_BASE (REGS_APB0_BASE + 0x0800)
#define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00)
#define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400)
#define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800)
/* APB1 Module */
-#define SUNXI_UART0_BASE (REGS_APB1_BASE + 0x0000)
-#define SUNXI_UART1_BASE (REGS_APB1_BASE + 0x0400)
-#define SUNXI_UART2_BASE (REGS_APB1_BASE + 0x0800)
-#define SUNXI_UART3_BASE (REGS_APB1_BASE + 0x0C00)
-#define SUNXI_UART4_BASE (REGS_APB1_BASE + 0x1000)
-#define SUNXI_UART5_BASE (REGS_APB1_BASE + 0x1400)
#define SUNXI_TWI0_BASE (REGS_APB1_BASE + 0x2800)
#define SUNXI_TWI1_BASE (REGS_APB1_BASE + 0x2C00)
#define SUNXI_TWI2_BASE (REGS_APB1_BASE + 0x3000)
@@ -101,8 +94,6 @@
/* RCPUS Module */
#define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400)
-#define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800)
-#define SUNXI_R_PIO_BASE (REGS_RCPUS_BASE + 0x2c00)
#define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400)
/* Misc. */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h
new file mode 100644
index 0000000..908a582
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2022 Arm Limited
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_CPU_SUNXI_NCAT2_H
+#define _SUNXI_CPU_SUNXI_NCAT2_H
+
+#define SUNXI_CCM_BASE 0x02001000
+#define SUNXI_TIMER_BASE 0x02050000
+
+#define SUNXI_TWI0_BASE 0x02502000
+#define SUNXI_TWI1_BASE 0x02502400
+#define SUNXI_TWI2_BASE 0x02502800
+#define SUNXI_TWI3_BASE 0x02502C00
+
+#define SUNXI_SRAMC_BASE 0x03000000
+/* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */
+#define SUNXI_SIDC_BASE 0x03006000
+#define SUNXI_SID_BASE 0x03006200
+#define SUNXI_GIC400_BASE 0x03020000
+
+#define SUNXI_MMC0_BASE 0x04020000
+#define SUNXI_MMC1_BASE 0x04021000
+#define SUNXI_MMC2_BASE 0x04022000
+
+#define SUNXI_R_CPUCFG_BASE 0x07000400
+#define SUNXI_PRCM_BASE 0x07010000
+
+#define SUNXI_CPUCFG_BASE 0x09010000
+
+#ifndef __ASSEMBLY__
+void sunxi_board_init(void);
+void sunxi_reset(void);
+int sunxi_get_sid(unsigned int *sid);
+#endif
+
+#endif /* _SUNXI_CPU_SUNXI_NCAT2_H */
diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg.h b/arch/arm/include/asm/arch-sunxi/cpucfg.h
deleted file mode 100644
index 4aaebe0..0000000
--- a/arch/arm/include/asm/arch-sunxi/cpucfg.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Sunxi A31 CPUCFG register definition.
- *
- * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com
- */
-
-#ifndef _SUNXI_CPUCFG_H
-#define _SUNXI_CPUCFG_H
-
-#include <linux/compiler.h>
-#include <linux/types.h>
-
-#ifndef __ASSEMBLY__
-
-struct __packed sunxi_cpucfg_cpu {
- u32 rst; /* base + 0x0 */
- u32 ctrl; /* base + 0x4 */
- u32 status; /* base + 0x8 */
- u8 res[0x34]; /* base + 0xc */
-};
-
-struct __packed sunxi_cpucfg_reg {
- u8 res0[0x40]; /* 0x000 */
- struct sunxi_cpucfg_cpu cpu[4]; /* 0x040 */
- u8 res1[0x44]; /* 0x140 */
- u32 gen_ctrl; /* 0x184 */
- u32 l2_status; /* 0x188 */
- u8 res2[0x4]; /* 0x18c */
- u32 event_in; /* 0x190 */
- u8 res3[0xc]; /* 0x194 */
- u32 super_standy_flag; /* 0x1a0 */
- u32 priv0; /* 0x1a4 */
- u32 priv1; /* 0x1a8 */
- u8 res4[0x4]; /* 0x1ac */
- u32 cpu1_pwr_clamp; /* 0x1b0 sun7i only */
- u32 cpu1_pwroff; /* 0x1b4 sun7i only */
- u8 res5[0x2c]; /* 0x1b8 */
- u32 dbg_ctrl1; /* 0x1e4 */
- u8 res6[0x18]; /* 0x1e8 */
- u32 idle_cnt0_low; /* 0x200 */
- u32 idle_cnt0_high; /* 0x204 */
- u32 idle_cnt0_ctrl; /* 0x208 */
- u8 res8[0x4]; /* 0x20c */
- u32 idle_cnt1_low; /* 0x210 */
- u32 idle_cnt1_high; /* 0x214 */
- u32 idle_cnt1_ctrl; /* 0x218 */
- u8 res9[0x4]; /* 0x21c */
- u32 idle_cnt2_low; /* 0x220 */
- u32 idle_cnt2_high; /* 0x224 */
- u32 idle_cnt2_ctrl; /* 0x228 */
- u8 res10[0x4]; /* 0x22c */
- u32 idle_cnt3_low; /* 0x230 */
- u32 idle_cnt3_high; /* 0x234 */
- u32 idle_cnt3_ctrl; /* 0x238 */
- u8 res11[0x4]; /* 0x23c */
- u32 idle_cnt4_low; /* 0x240 */
- u32 idle_cnt4_high; /* 0x244 */
- u32 idle_cnt4_ctrl; /* 0x248 */
- u8 res12[0x34]; /* 0x24c */
- u32 cnt64_ctrl; /* 0x280 */
- u32 cnt64_low; /* 0x284 */
- u32 cnt64_high; /* 0x288 */
-};
-
-#endif /* __ASSEMBLY__ */
-#endif /* _SUNXI_CPUCFG_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
index 11774de..a8fdda1 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
@@ -130,6 +130,7 @@
#define MSTR_DEVICETYPE_LPDDR2 BIT(2)
#define MSTR_DEVICETYPE_LPDDR3 BIT(3)
#define MSTR_DEVICETYPE_DDR4 BIT(4)
+#define MSTR_DEVICETYPE_LPDDR4 BIT(5)
#define MSTR_DEVICETYPE_MASK GENMASK(5, 0)
#define MSTR_2TMODE BIT(10)
#define MSTR_BUSWIDTH_FULL (0 << 12)
@@ -154,6 +155,7 @@
u32 odt_en;
u32 tpr0;
u32 tpr2;
+ u32 tpr6;
u32 tpr10;
u32 tpr11;
u32 tpr12;
diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
index 5daacf1..b8d91b5 100644
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -1,139 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2007-2011
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Aaron <leafy.myeh@allwinnertech.com>
- *
- * MMC register definition for allwinner sunxi platform.
- */
-#ifndef _SUNXI_MMC_H
-#define _SUNXI_MMC_H
-
-#include <linux/types.h>
-
-struct sunxi_mmc {
- u32 gctrl; /* 0x00 global control */
- u32 clkcr; /* 0x04 clock control */
- u32 timeout; /* 0x08 time out */
- u32 width; /* 0x0c bus width */
- u32 blksz; /* 0x10 block size */
- u32 bytecnt; /* 0x14 byte count */
- u32 cmd; /* 0x18 command */
- u32 arg; /* 0x1c argument */
- u32 resp0; /* 0x20 response 0 */
- u32 resp1; /* 0x24 response 1 */
- u32 resp2; /* 0x28 response 2 */
- u32 resp3; /* 0x2c response 3 */
- u32 imask; /* 0x30 interrupt mask */
- u32 mint; /* 0x34 masked interrupt status */
- u32 rint; /* 0x38 raw interrupt status */
- u32 status; /* 0x3c status */
- u32 ftrglevel; /* 0x40 FIFO threshold watermark*/
- u32 funcsel; /* 0x44 function select */
- u32 cbcr; /* 0x48 CIU byte count */
- u32 bbcr; /* 0x4c BIU byte count */
- u32 dbgc; /* 0x50 debug enable */
- u32 res0; /* 0x54 reserved */
- u32 a12a; /* 0x58 Auto command 12 argument */
- u32 ntsr; /* 0x5c New timing set register */
- u32 res1[8];
- u32 dmac; /* 0x80 internal DMA control */
- u32 dlba; /* 0x84 internal DMA descr list base address */
- u32 idst; /* 0x88 internal DMA status */
- u32 idie; /* 0x8c internal DMA interrupt enable */
- u32 chda; /* 0x90 */
- u32 cbda; /* 0x94 */
- u32 res2[26];
-#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
- u32 res3[17];
- u32 samp_dl;
- u32 res4[46];
-#endif
- u32 fifo; /* 0x100 / 0x200 FIFO access address */
-};
-
-#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17)
-#define SUNXI_MMC_CLK_ENABLE (0x1 << 16)
-#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff)
-
-#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0)
-#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1)
-#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2)
-#define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\
- SUNXI_MMC_GCTRL_FIFO_RESET|\
- SUNXI_MMC_GCTRL_DMA_RESET)
-#define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5)
-#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31)
-
-#define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6)
-#define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7)
-#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8)
-#define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9)
-#define SUNXI_MMC_CMD_WRITE (0x1 << 10)
-#define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12)
-#define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13)
-#define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15)
-#define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21)
-#define SUNXI_MMC_CMD_START (0x1 << 31)
-
-#define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1)
-#define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2)
-#define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3)
-#define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4)
-#define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5)
-#define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6)
-#define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7)
-#define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8)
-#define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9)
-#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10)
-#define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11)
-#define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12)
-#define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13)
-#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14)
-#define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15)
-#define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16)
-#define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30)
-#define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31)
-#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \
- (SUNXI_MMC_RINT_RESP_ERROR | \
- SUNXI_MMC_RINT_RESP_CRC_ERROR | \
- SUNXI_MMC_RINT_DATA_CRC_ERROR | \
- SUNXI_MMC_RINT_RESP_TIMEOUT | \
- SUNXI_MMC_RINT_DATA_TIMEOUT | \
- SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \
- SUNXI_MMC_RINT_FIFO_RUN_ERROR | \
- SUNXI_MMC_RINT_HARD_WARE_LOCKED | \
- SUNXI_MMC_RINT_START_BIT_ERROR | \
- SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */
-#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \
- (SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \
- SUNXI_MMC_RINT_DATA_OVER | \
- SUNXI_MMC_RINT_COMMAND_DONE | \
- SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE)
-
-#define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0)
-#define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1)
-#define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2)
-#define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3)
-#define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8)
-#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9)
-#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10)
-#define SUNXI_MMC_STATUS_FIFO_LEVEL(reg) (((reg) >> 17) & 0x3fff)
-
-#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31)
-
-#define SUNXI_MMC_IDMAC_RESET (0x1 << 0)
-#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1)
-#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7)
-
-#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0)
-#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1)
-
-#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
-#define SUNXI_MMC_COMMON_RESET (1 << 18)
-
-#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
+#ifndef _ASM_ARCH_MMC_H_
+#define _ASM_ARCH_MMC_H_
struct mmc *sunxi_mmc_init(int sdc_no);
-#endif /* _SUNXI_MMC_H */
+
+#endif /* _ASM_ARCH_MMC_H_ */
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h
index 5106076..c5418cf 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -9,7 +9,7 @@
#define _SUNXI_PRCM_H
/* prcm regs definition */
-#if defined(CONFIG_SUN50I_GEN_H6)
+#if defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
#include <asm/arch/prcm_sun50i.h>
#else
#include <asm/arch/prcm_sun6i.h>
diff --git a/arch/arm/include/asm/arch-sunxi/serial.h b/arch/arm/include/asm/arch-sunxi/serial.h
new file mode 100644
index 0000000..9386287
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/serial.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * hardcoded UART base addresses for early SPL use
+ *
+ * Copyright (c) 2022 Arm Ltd.
+ */
+
+#ifndef SUNXI_SERIAL_MEMMAP_H
+#define SUNXI_SERIAL_MEMMAP_H
+
+#if defined(CONFIG_MACH_SUN9I)
+#define SUNXI_UART0_BASE 0x07000000
+#define SUNXI_R_UART_BASE 0x08002800
+#elif defined(CONFIG_SUN50I_GEN_H6)
+#define SUNXI_UART0_BASE 0x05000000
+#define SUNXI_R_UART_BASE 0x07080000
+#elif defined(CONFIG_MACH_SUNIV)
+#define SUNXI_UART0_BASE 0x01c25000
+#define SUNXI_R_UART_BASE 0
+#elif defined(CONFIG_SUNXI_GEN_NCAT2)
+#define SUNXI_UART0_BASE 0x02500000
+#define SUNXI_R_UART_BASE 0 // 0x07080000 (?>
+#else
+#define SUNXI_UART0_BASE 0x01c28000
+#define SUNXI_R_UART_BASE 0x01f02800
+#endif
+
+#define SUNXI_UART1_BASE (SUNXI_UART0_BASE + 0x400)
+#define SUNXI_UART2_BASE (SUNXI_UART0_BASE + 0x800)
+#define SUNXI_UART3_BASE (SUNXI_UART0_BASE + 0xc00)
+
+#endif /* SUNXI_SERIAL_MEMMAP_H */
diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h
index bb5626d..e17db85 100644
--- a/arch/arm/include/asm/arch-sunxi/timer.h
+++ b/arch/arm/include/asm/arch-sunxi/timer.h
@@ -76,7 +76,7 @@
struct sunxi_tgp tgp[4];
u8 res5[8];
u32 cpu_cfg;
-#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
+#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
u8 res3[16];
struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */
#endif
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
index d6a5576..750c7d8 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -128,21 +128,22 @@
/* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */
#define MEMCOMP_PADCTRL_VREF 7
-#define AUTO_CAL_ENABLE (1 << 29)
-#define AUTO_CAL_ACTIVE (1 << 31)
-#define AUTO_CAL_START (1 << 31)
+#define AUTO_CAL_ENABLE BIT(29)
+#define AUTO_CAL_ACTIVE BIT(31)
+#define AUTO_CAL_START BIT(31)
+
#if defined(CONFIG_TEGRA210)
#define AUTO_CAL_PD_OFFSET (0x7D << 8)
#define AUTO_CAL_PU_OFFSET (0 << 0)
-#define IO_TRIM_BYPASS_MASK (1 << 2)
-#define TRIM_VAL_SHIFT 24
-#define TRIM_VAL_MASK (0x1F << TRIM_VAL_SHIFT)
-#define TAP_VAL_SHIFT 16
-#define TAP_VAL_MASK (0xFF << TAP_VAL_SHIFT)
#else
#define AUTO_CAL_PD_OFFSET (0x70 << 8)
#define AUTO_CAL_PU_OFFSET (0x62 << 0)
#endif
+#define TRIM_VAL_SHIFT 24
+#define TRIM_VAL_MASK (0x1F << TRIM_VAL_SHIFT)
+#define TAP_VAL_SHIFT 16
+#define TAP_VAL_MASK (0xFF << TAP_VAL_SHIFT)
+
#endif /* __ASSEMBLY__ */
#endif /* __TEGRA_MMC_H_ */
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 5c57004..befa7c9 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -49,13 +49,10 @@
#define PTE_TYPE_BLOCK (1 << 0)
#define PTE_TYPE_VALID (1 << 0)
-#define PTE_RDONLY BIT(7)
-#define PTE_DBM BIT(51)
-
-#define PTE_TABLE_PXN BIT(59)
-#define PTE_TABLE_XN BIT(60)
-#define PTE_TABLE_AP BIT(61)
-#define PTE_TABLE_NS BIT(63)
+#define PTE_TABLE_PXN (1UL << 59)
+#define PTE_TABLE_XN (1UL << 60)
+#define PTE_TABLE_AP (1UL << 61)
+#define PTE_TABLE_NS (1UL << 63)
/*
* Block
@@ -102,15 +99,6 @@
#define TCR_TG0_16K (2 << 14)
#define TCR_EPD1_DISABLE (1 << 23)
-#define TCR_EL1_HA BIT(39)
-#define TCR_EL1_HD BIT(40)
-
-#define TCR_EL2_HA BIT(21)
-#define TCR_EL2_HD BIT(22)
-
-#define TCR_EL3_HA BIT(21)
-#define TCR_EL3_HD BIT(22)
-
#define TCR_EL1_RSVD (1U << 31)
#define TCR_EL2_RSVD (1U << 31 | 1 << 23)
#define TCR_EL3_RSVD (1U << 31 | 1 << 23)
@@ -118,7 +106,6 @@
#define HCR_EL2_E2H_BIT 34
#ifndef __ASSEMBLY__
-
#include <linux/types.h>
static inline void set_ttbr_tcr(int el, u64 table, u64 tcr)
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index fa85486..8e89783 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -15,9 +15,34 @@
#ifndef __ASM_ARM_BITOPS_H
#define __ASM_ARM_BITOPS_H
+#if __LINUX_ARM_ARCH__ < 5
+
#include <asm-generic/bitops/__ffs.h>
#include <asm-generic/bitops/__fls.h>
#include <asm-generic/bitops/fls.h>
+
+#else
+
+#define PLATFORM_FFS
+#define PLATFORM_FLS
+
+#if !IS_ENABLED(CONFIG_HAS_THUMB2) && CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
+
+unsigned long __fls(unsigned long word);
+unsigned long __ffs(unsigned long word);
+int fls(unsigned int x);
+int ffs(int x);
+
+#else
+
+#include <asm-generic/bitops/builtin-__fls.h>
+#include <asm-generic/bitops/builtin-__ffs.h>
+#include <asm-generic/bitops/builtin-fls.h>
+#include <asm-generic/bitops/builtin-ffs.h>
+
+#endif
+#endif
+
#include <asm-generic/bitops/fls64.h>
#ifdef __KERNEL__
@@ -113,7 +138,7 @@
static inline int __ilog2(unsigned int x)
{
- return generic_fls(x) - 1;
+ return fls(x) - 1;
}
#define ffz(x) __ffs(~(x))
diff --git a/arch/arm/include/asm/ehci-omap.h b/arch/arm/include/asm/ehci-omap.h
index 2b51b5e..662b62c 100644
--- a/arch/arm/include/asm/ehci-omap.h
+++ b/arch/arm/include/asm/ehci-omap.h
@@ -4,7 +4,7 @@
* Based on LINUX KERNEL
* drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com*
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com*
* Author: Govindraj R <govindraj.raja@ti.com>
*/
diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
index 6a9d198..15627c9 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -9,15 +9,6 @@
#ifdef CONFIG_CHAIN_OF_TRUST
#ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_FSL_LS_PPA
-/* Define the key hash here if SRK used for signing PPA image is
- * different from SRK hash put in SFP used for U-Boot.
- * Example
- * #define PPA_KEY_HASH \
- * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
- */
-#define PPA_KEY_HASH NULL
-#endif /* ifdef CONFIG_FSL_LS_PPA */
#endif /* #ifndef CONFIG_SPL_BUILD */
#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 2a222c5..75bd9d5 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -52,8 +52,6 @@
#if defined(CONFIG_ARM64)
unsigned long tlb_fillptr;
unsigned long tlb_emerg;
- unsigned int first_block_level;
- bool has_hafdbs;
#endif
#endif
#ifdef CFG_SYS_MEM_RESERVE_SECURE
@@ -102,6 +100,9 @@
#ifdef CONFIG_ARCH_IMX8ULP
bool m33_handshake_done;
#endif
+#ifdef CONFIG_SMBIOS
+ ulong smbios_start; /* Start address of SMBIOS table */
+#endif
};
#include <asm-generic/global_data.h>
diff --git a/arch/arm/include/asm/mach-imx/ahab.h b/arch/arm/include/asm/mach-imx/ahab.h
index 4222e3d..4884f05 100644
--- a/arch/arm/include/asm/mach-imx/ahab.h
+++ b/arch/arm/include/asm/mach-imx/ahab.h
@@ -6,7 +6,7 @@
#ifndef __IMX_AHAB_H__
#define __IMX_AHAB_H__
-#include <asm/mach-imx/image.h>
+#include <imx_container.h>
int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length);
int ahab_auth_release(void);
diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
index 0ece4b0..ee79a19 100644
--- a/arch/arm/include/asm/spl.h
+++ b/arch/arm/include/asm/spl.h
@@ -34,9 +34,6 @@
};
#endif
-/* Linker symbols. */
-extern char __bss_start[], __bss_end[];
-
#ifndef CONFIG_DM
extern gd_t gdata;
#endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 87d1c77..0eae857 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -84,6 +84,7 @@
#define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */
#define HCR_EL2_AMO_EL2 (1 << 5) /* Route SErrors to EL2 */
+#define ID_AA64ISAR0_EL1_RNDR (0xFUL << 60) /* RNDR random registers */
/*
* ID_AA64ISAR1_EL1 bits definitions
*/
diff --git a/arch/arm/include/asm/ti-common/omap_wdt.h b/arch/arm/include/asm/ti-common/omap_wdt.h
index 42d7e4c..855f889 100644
--- a/arch/arm/include/asm/ti-common/omap_wdt.h
+++ b/arch/arm/include/asm/ti-common/omap_wdt.h
@@ -4,7 +4,7 @@
*
* OMAP Watchdog header file
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef __OMAP_WDT_H__
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 62cf80f..b1bcd37 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -113,6 +113,11 @@
AFLAGS_REMOVE_memcpy.o := -mthumb -mthumb-interwork
AFLAGS_memset.o := -DMEMSET_NO_THUMB_BUILD
AFLAGS_memcpy.o := -DMEMCPY_NO_THUMB_BUILD
+
+# This is only necessary to force ARM mode on THUMB1 targets.
+ifneq ($(CONFIG_SYS_ARM_ARCH),4)
+obj-y += bitops.o
+endif
endif
endif
diff --git a/arch/arm/lib/bdinfo.c b/arch/arm/lib/bdinfo.c
index 5e6eaad..b88b01e 100644
--- a/arch/arm/lib/bdinfo.c
+++ b/arch/arm/lib/bdinfo.c
@@ -57,7 +57,7 @@
#ifdef CONFIG_BOARD_TYPES
printf("Board Type = %ld\n", gd->board_type);
#endif
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
printf("Early malloc usage: %lx / %x\n", gd->malloc_ptr,
CONFIG_VAL(SYS_MALLOC_F_LEN));
#endif
diff --git a/arch/arm/lib/bitops.S b/arch/arm/lib/bitops.S
new file mode 100644
index 0000000..29d1524
--- /dev/null
+++ b/arch/arm/lib/bitops.S
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 Sean Anderson <sean.anderson@seco.com>
+ *
+ * ARM bitops to call when using THUMB1, which doesn't have these instructions.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+.pushsection .text.__fls
+ENTRY(__fls)
+ clz r0, r0
+ rsb r0, r0, #31
+ ret lr
+ENDPROC(__fls)
+.popsection
+
+.pushsection .text.__ffs
+ENTRY(__ffs)
+ rsb r3, r0, #0
+ and r0, r0, r3
+ clz r0, r0
+ rsb r0, r0, #31
+ ret lr
+ENDPROC(__ffs)
+.popsection
+
+.pushsection .text.fls
+ENTRY(fls)
+ cmp r0, #0
+ clzne r0, r0
+ rsbne r0, r0, #32
+ ret lr
+ENDPROC(fls)
+.popsection
+
+.pushsection .text.ffs
+ENTRY(ffs)
+ rsb r3, r0, #0
+ and r0, r0, r3
+ clz r0, r0
+ rsb r0, r0, #32
+ ret lr
+ENDPROC(ffs)
+.popsection
diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
index f6211a2..f4bbd21 100644
--- a/arch/arm/lib/gic-v3-its.c
+++ b/arch/arm/lib/gic-v3-its.c
@@ -9,6 +9,7 @@
#include <asm/gic-v3.h>
#include <asm/io.h>
#include <linux/bitops.h>
+#include <linux/printk.h>
#include <linux/sizes.h>
static u32 lpi_id_bits;
diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c
index d501948..7a6151a 100644
--- a/arch/arm/mach-apple/board.c
+++ b/arch/arm/mach-apple/board.c
@@ -372,6 +372,22 @@
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
+ .virt = 0x400000000,
+ .phys = 0x400000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x480000000,
+ .phys = 0x480000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
.virt = 0x580000000,
.phys = 0x580000000,
.size = SZ_512M,
@@ -444,6 +460,219 @@
}
};
+/* Apple M2 Ultra */
+
+static struct mm_region t6022_mem_map[] = {
+ {
+ /* I/O */
+ .virt = 0x280000000,
+ .phys = 0x280000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x340000000,
+ .phys = 0x340000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x380000000,
+ .phys = 0x380000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x400000000,
+ .phys = 0x400000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x480000000,
+ .phys = 0x480000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x580000000,
+ .phys = 0x580000000,
+ .size = SZ_512M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PCIE */
+ .virt = 0x5a0000000,
+ .phys = 0x5a0000000,
+ .size = SZ_512M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PCIE */
+ .virt = 0x5c0000000,
+ .phys = 0x5c0000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x700000000,
+ .phys = 0x700000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0xb00000000,
+ .phys = 0xb00000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0xf00000000,
+ .phys = 0xf00000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x1300000000,
+ .phys = 0x1300000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2280000000,
+ .phys = 0x2280000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2340000000,
+ .phys = 0x2340000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2380000000,
+ .phys = 0x2380000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2400000000,
+ .phys = 0x2400000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2480000000,
+ .phys = 0x2480000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2580000000,
+ .phys = 0x2580000000,
+ .size = SZ_512M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PCIE */
+ .virt = 0x25a0000000,
+ .phys = 0x25a0000000,
+ .size = SZ_512M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PCIE */
+ .virt = 0x25c0000000,
+ .phys = 0x25c0000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2700000000,
+ .phys = 0x2700000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2b00000000,
+ .phys = 0x2b00000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2f00000000,
+ .phys = 0x2f00000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x3300000000,
+ .phys = 0x3300000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* RAM */
+ .virt = 0x10000000000,
+ .phys = 0x10000000000,
+ .size = 16UL * SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* Framebuffer */
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
struct mm_region *mem_map;
int board_init(void)
@@ -488,6 +717,8 @@
else if (of_machine_is_compatible("apple,t6020") ||
of_machine_is_compatible("apple,t6021"))
mem_map = t6020_mem_map;
+ else if (of_machine_is_compatible("apple,t6022"))
+ mem_map = t6022_mem_map;
else
panic("Unsupported SoC\n");
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 7c2e4eb..37ef2d6 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -204,6 +204,17 @@
processor-based SAMA5D2 MPU with 2 Gbit LPDDR2-SDRAM
in a single package.
+config TARGET_KSTR_SAMA5D27
+ bool "Conclusive KSTR-SAMA5D27 board"
+ select BOARD_EARLY_INIT_F
+ select SAMA5D2
+ help
+ The KSTR-SAMA5D27 embeds SAMA5D27 SoC, together with
+ 256 MiB SDRAM, 10/100 Mbit/s Ethernet, 96 Mbit/s Wi-Fi b/g/n,
+ Bluetooth 4.1 LE, USB OTG controller w/ type-C USB connector
+ and stackable GPIO headers in an all-in-one SBC form factor:
+ https://conclusive.pl/products/kstr-sama5d27-sbc/
+
config TARGET_SAMA5D2_ICP
bool "SAMA5D2 Industrial Connectivity Platform (ICP)"
select SAMA5D2
@@ -215,6 +226,17 @@
a 64Mbit QSPI flash, 3xMikrobus connectors, 4xUSB ,
EtherCat and WILC3000 devices on board.
+config TARGET_SAMA5D29_CURIOSITY
+ bool "SAMA5D29 CURIOSITY board"
+ select SAMA5D2
+ select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+ select CPU_V7A
+ help
+ The SAMA5D29 Curiosity embeds SAMA5D29 SoC with 4 Gbit LPDDR2-SDRAM,
+ a 64Mbit QSPI flash with Mac-address, MCP16502 PMIC, RGB LCD connector,
+ 2 x Mikrobus connectors, 2 x SD-Card connectors, 2 x USB
+
config TARGET_SAMA5D3_XPLAINED
bool "SAMA5D3 Xplained board"
select BOARD_EARLY_INIT_F
@@ -346,12 +368,14 @@
source "board/atmel/sama5d27_som1_ek/Kconfig"
source "board/atmel/sama5d27_wlsom1_ek/Kconfig"
source "board/atmel/sama5d2_icp/Kconfig"
+source "board/atmel/sama5d29_curiosity/Kconfig"
source "board/atmel/sama5d3_xplained/Kconfig"
source "board/atmel/sama5d3xek/Kconfig"
source "board/atmel/sama5d4_xplained/Kconfig"
source "board/atmel/sama5d4ek/Kconfig"
source "board/bluewater/gurnard/Kconfig"
source "board/calao/usb_a9263/Kconfig"
+source "board/conclusive/kstr-sama5d27/Kconfig"
source "board/egnite/ethernut5/Kconfig"
source "board/esd/meesc/Kconfig"
source "board/gardena/smart-gateway-at91sam/Kconfig"
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 183650a..7265faf 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -146,6 +146,14 @@
return 0;
}
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ printf("CPU: BCM283x\n");
+ return 0;
+}
+#endif
+
#ifdef CONFIG_ARMV7_LPAE
#ifdef CONFIG_TARGET_RPI_4_32B
#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xffc00000UL
diff --git a/arch/arm/mach-davinci/config.mk b/arch/arm/mach-davinci/config.mk
index 4674cae..edbac8e 100644
--- a/arch/arm/mach-davinci/config.mk
+++ b/arch/arm/mach-davinci/config.mk
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2012, Texas Instruments, Incorporated - http://www.ti.com/
+# Copyright (C) 2012, Texas Instruments, Incorporated - https://www.ti.com/
ifndef CONFIG_SPL_BUILD
INPUTS-$(CONFIG_SPL_FRAMEWORK) += u-boot.ais
endif
diff --git a/arch/arm/mach-exynos/include/mach/board.h b/arch/arm/mach-exynos/include/mach/board.h
index 44ebdb8..a167f96 100644
--- a/arch/arm/mach-exynos/include/mach/board.h
+++ b/arch/arm/mach-exynos/include/mach/board.h
@@ -11,7 +11,7 @@
* Exynos baord specific changes for
* board_init
*/
-int exynos_init(void);
+void exynos_init(void);
/*
* Exynos board specific changes for
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
index f9975d7..9eeeb76 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -8,6 +8,9 @@
#define __ASM_ARCH_GPIO_H
#ifndef __ASSEMBLY__
+
+#include <asm/arch/cpu.h>
+
struct s5p_gpio_bank {
unsigned int con;
unsigned int dat;
diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c
index a07c87a..aff2b5e 100644
--- a/arch/arm/mach-exynos/soc.c
+++ b/arch/arm/mach-exynos/soc.c
@@ -9,6 +9,7 @@
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/system.h>
+#include <asm/arch/cpu.h>
#ifdef CONFIG_TARGET_ESPRESSO7420
/*
@@ -20,12 +21,14 @@
void *secondary_boot_addr = (void *)_main;
#endif /* CONFIG_TARGET_ESPRESSO7420 */
+#if !CONFIG_IS_ENABLED(SYSRESET)
void reset_cpu(void)
{
#ifdef CONFIG_CPU_V7A
writel(0x1, samsung_get_base_swreset());
#endif
}
+#endif
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index fda7624..abd48d4 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -71,7 +71,7 @@
config CMD_BMODE
bool "Support the 'bmode' command"
default y
- depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5
+ depends on ARCH_IMX8M || ARCH_MX7 || ARCH_MX6 || ARCH_MX5
help
This enables the 'bmode' (bootmode) command for forcing
a boot from specific media.
@@ -182,7 +182,7 @@
config SPL_IMX_ROMAPI_LOADADDR
hex "Default load address to load image through ROM API"
depends on IMX8_ROMAPI || SPL_BOOTROM_SUPPORT
- default 0
+ default 0x0
config IMX_DCD_ADDR
hex "DCD Blocks location on the image"
@@ -194,19 +194,6 @@
This information is shared with the user via mkimage -l just so the
image can be signed.
-config SPL_LOAD_IMX_CONTAINER
- bool "Enable SPL loading U-Boot as a i.MX Container image"
- depends on SPL
- help
- This is to let SPL could load i.MX Container image
-
-config IMX_CONTAINER_CFG
- string "i.MX Container config file"
- depends on SPL
- help
- This is to specific the cfg file for generating container
- image which will be loaded by SPL.
-
config IOMUX_LPSR
bool
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index aebfa65..a3b44c9 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -79,7 +79,7 @@
endif
ifeq ($(CONFIG_SPL_BUILD),y)
-obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image-container.o parse-container.o
+obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image-container.o
endif
ifeq ($(SOC),$(filter $(SOC),imx8ulp imx9))
@@ -142,7 +142,9 @@
$(call if_changed,mkimage)
quiet_cmd_u-boot-nand_imx = GEN $@
-cmd_u-boot-nand_imx = (dd bs=1024 count=1 if=/dev/zero 2>/dev/null) | cat - $< > $@
+cmd_u-boot-nand_imx = (dd bs=1024 count=1 if=/dev/zero 2>/dev/null) | cat - $< > $@.zero-padded ; \
+ (dd bs=10k count=1 if=/dev/zero 2>/dev/null) | cat $@.zero-padded - > $@ ; \
+ rm -f $@.zero-padded
u-boot-nand.imx: u-boot.imx FORCE
$(call if_changed,u-boot-nand_imx)
diff --git a/arch/arm/mach-imx/cmd_bmode.c b/arch/arm/mach-imx/cmd_bmode.c
index cb31749..5b2f468 100644
--- a/arch/arm/mach-imx/cmd_bmode.c
+++ b/arch/arm/mach-imx/cmd_bmode.c
@@ -83,7 +83,11 @@
reset_requested = 0;
}
+/* No longer applicable to i.MX8M */
+#if IS_ENABLED(CONFIG_MX53) || IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7)
boot_mode_apply(p->cfg_val);
+#endif
+
if (reset_requested && p->cfg_val)
do_reset(NULL, 0, 0, NULL);
return 0;
diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c
index 6fa5b41..2f389db 100644
--- a/arch/arm/mach-imx/cmd_dek.c
+++ b/arch/arm/mach-imx/cmd_dek.c
@@ -18,12 +18,12 @@
#include <mapmem.h>
#include <tee.h>
#ifdef CONFIG_IMX_SECO_DEK_ENCAP
+#include <imx_container.h>
#include <firmware/imx/sci/sci.h>
-#include <asm/mach-imx/image.h>
#endif
#ifdef CONFIG_IMX_ELE_DEK_ENCAP
+#include <imx_container.h>
#include <asm/mach-imx/ele_api.h>
-#include <asm/mach-imx/image.h>
#endif
#include <cpu_func.h>
diff --git a/arch/arm/mach-imx/cmd_nandbcb.c b/arch/arm/mach-imx/cmd_nandbcb.c
index c54f52b..70a213a 100644
--- a/arch/arm/mach-imx/cmd_nandbcb.c
+++ b/arch/arm/mach-imx/cmd_nandbcb.c
@@ -1561,8 +1561,7 @@
return CMD_RET_USAGE;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char nandbcb_help_text[] =
+U_BOOT_LONGHELP(nandbcb,
"init addr off|partition len - update 'len' bytes starting at\n"
" 'off|part' to memory address 'addr', skipping bad blocks\n"
"nandbcb bcbonly off|partition fw1-off fw1-size [fw2-off fw2-size]\n"
@@ -1572,8 +1571,7 @@
" FIY, BCB isn't erased automatically, so mtd erase should\n"
" be called in advance before writing new BCB:\n"
" > mtd erase mx7-bcb\n"
- "nandbcb dump off|partition - dump/verify boot structures\n";
-#endif
+ "nandbcb dump off|partition - dump/verify boot structures\n");
U_BOOT_CMD(nandbcb, 7, 1, do_nandbcb,
"i.MX NAND Boot Control Blocks write",
diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c
index 785b0d6..295c055 100644
--- a/arch/arm/mach-imx/ele_ahab.c
+++ b/arch/arm/mach-imx/ele_ahab.c
@@ -6,12 +6,12 @@
#include <common.h>
#include <command.h>
#include <errno.h>
+#include <imx_container.h>
#include <asm/io.h>
#include <asm/mach-imx/ele_api.h>
#include <asm/mach-imx/sys_proto.h>
#include <asm/arch-imx/cpu.h>
#include <asm/arch/sys_proto.h>
-#include <asm/mach-imx/image.h>
#include <console.h>
#include <cpu_func.h>
#include <asm/global_data.h>
@@ -343,7 +343,7 @@
}
phdr = (struct container_hdr *)addr;
- if (phdr->tag != 0x87 || phdr->version != 0x0) {
+ if (!valid_container_hdr(phdr)) {
printf("Error: Wrong container header\n");
return -EFAULT;
}
diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c
index 5f188ab..c9455fe 100644
--- a/arch/arm/mach-imx/image-container.c
+++ b/arch/arm/mach-imx/image-container.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <errno.h>
+#include <imx_container.h>
#include <log.h>
#include <malloc.h>
#include <asm/io.h>
@@ -12,7 +13,6 @@
#include <spi_flash.h>
#include <spl.h>
#include <nand.h>
-#include <asm/mach-imx/image.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
@@ -50,7 +50,7 @@
u32 max_offset = 0, img_end;
phdr = (struct container_hdr *)addr;
- if (phdr->tag != 0x87 || phdr->version != 0x0) {
+ if (!valid_container_hdr(phdr)) {
debug("Wrong container header\n");
return -EFAULT;
}
@@ -276,8 +276,8 @@
#endif
#ifdef CONFIG_SPL_MMC
-unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
- unsigned long raw_sect)
+unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
+ unsigned long raw_sect)
{
int end;
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index 15f844f..59d11b3 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -34,11 +34,11 @@
config BOOTAUX_RESERVED_MEM_BASE
hex "i.MX auxiliary core dram memory base"
- default 0
+ default 0x0
config BOOTAUX_RESERVED_MEM_SIZE
hex "i.MX auxiliary core dram memory size"
- default 0
+ default 0x0
choice
prompt "i.MX8 board select"
diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c
index b58b14c..994becc 100644
--- a/arch/arm/mach-imx/imx8/ahab.c
+++ b/arch/arm/mach-imx/imx8/ahab.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <command.h>
#include <errno.h>
+#include <imx_container.h>
#include <log.h>
#include <asm/global_data.h>
#include <asm/io.h>
@@ -13,7 +14,6 @@
#include <asm/mach-imx/sys_proto.h>
#include <asm/arch-imx/cpu.h>
#include <asm/arch/sys_proto.h>
-#include <asm/mach-imx/image.h>
#include <console.h>
#include <cpu_func.h>
#include "u-boot/sha256.h"
@@ -146,7 +146,7 @@
}
phdr = (struct container_hdr *)addr;
- if (phdr->tag != 0x87 && phdr->version != 0x0) {
+ if (!valid_container_hdr(phdr)) {
printf("Error: Wrong container header\n");
return -EFAULT;
}
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index c623570..39ac0bc 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -69,7 +69,7 @@
return 0;
}
-static int imx8_init_mu(void *ctx, struct event *event)
+static int imx8_init_mu(void)
{
struct udevice *devp;
int node, ret;
@@ -91,7 +91,7 @@
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, imx8_init_mu);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx8_init_mu);
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
diff --git a/arch/arm/mach-imx/imx8/fdt.c b/arch/arm/mach-imx/imx8/fdt.c
index 491c8bb..c2bed3e 100644
--- a/arch/arm/mach-imx/imx8/fdt.c
+++ b/arch/arm/mach-imx/imx8/fdt.c
@@ -11,6 +11,7 @@
#include <dm/ofnode.h>
#include <fdt_support.h>
#include <linux/libfdt.h>
+#include <linux/printk.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 9868707..a24eb74 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -56,6 +56,7 @@
static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
PLL_1443X_RATE(933000000U, 311, 4, 1, 0),
+ PLL_1443X_RATE(900000000U, 300, 8, 0, 0),
PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 0ae93bb..39802d6 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -28,8 +28,10 @@
#include <errno.h>
#include <fdt_support.h>
#include <fsl_wdog.h>
+#include <fuse.h>
#include <imx_sip.h>
#include <linux/bitops.h>
+#include <linux/bitfield.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -533,7 +535,7 @@
writew(enable, &wdog3->wmcr);
}
-static int imx8m_check_clock(void *ctx, struct event *event)
+static int imx8m_check_clock(void)
{
struct udevice *dev;
int ret;
@@ -550,7 +552,7 @@
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, imx8m_check_clock);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx8m_check_clock);
static void imx8m_setup_snvs(void)
{
@@ -648,19 +650,17 @@
#if defined(CONFIG_IMX8M)
#include <spl.h>
-int spl_mmc_emmc_boot_partition(struct mmc *mmc)
+int imx8m_detect_secondary_image_boot(void)
{
u32 *rom_log_addr = (u32 *)0x9e0;
u32 *rom_log;
u8 event_id;
- int i, part;
-
- part = default_spl_mmc_emmc_boot_partition(mmc);
+ int i, boot_secondary = 0;
/* If the ROM event log pointer is not valid. */
if (*rom_log_addr < 0x900000 || *rom_log_addr >= 0xb00000 ||
*rom_log_addr & 0x3)
- return part;
+ return -EINVAL;
/* Parse the ROM event ID version 2 log */
rom_log = (u32 *)(uintptr_t)(*rom_log_addr);
@@ -668,7 +668,7 @@
event_id = rom_log[i] >> 24;
switch (event_id) {
case 0x00: /* End of list */
- return part;
+ return boot_secondary;
/* Log entries with 1 parameter, skip 1 */
case 0x80: /* Start to perform the device initialization */
case 0x81: /* The boot device initialization completes */
@@ -686,26 +686,89 @@
continue;
/* Boot from the secondary boot image */
case 0x51:
- /*
- * Swap the eMMC boot partitions in case there was a
- * fallback event (i.e. primary image was corrupted
- * and that corruption was recognized by the BootROM),
- * so the SPL loads the rest of the U-Boot from the
- * correct eMMC boot partition, since the BootROM
- * leaves the boot partition set to the corrupted one.
- */
- if (part == 1)
- part = 2;
- else if (part == 2)
- part = 1;
+ boot_secondary = 1;
continue;
default:
continue;
}
}
+ return boot_secondary;
+}
+
+int spl_mmc_emmc_boot_partition(struct mmc *mmc)
+{
+ int part, ret;
+
+ part = default_spl_mmc_emmc_boot_partition(mmc);
+ if (part == 0)
+ return part;
+
+ ret = imx8m_detect_secondary_image_boot();
+ if (ret < 0) {
+ printf("Could not get boot partition! Using %d\n", part);
+ return part;
+ }
+
+ if (ret == 1) {
+ /*
+ * Swap the eMMC boot partitions in case there was a
+ * fallback event (i.e. primary image was corrupted
+ * and that corruption was recognized by the BootROM),
+ * so the SPL loads the rest of the U-Boot from the
+ * correct eMMC boot partition, since the BootROM
+ * leaves the boot partition set to the corrupted one.
+ */
+ if (part == 1)
+ part = 2;
+ else if (part == 2)
+ part = 1;
+ }
+
return part;
}
+
+int boot_mode_getprisec(void)
+{
+ return !!imx8m_detect_secondary_image_boot();
+}
+#endif
+
+#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
+#define IMG_CNTN_SET1_OFFSET GENMASK(22, 19)
+unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
+ unsigned long raw_sect)
+{
+ u32 val, offset;
+
+ if (fuse_read(2, 1, &val)) {
+ debug("Error reading fuse!\n");
+ return raw_sect;
+ }
+
+ val = FIELD_GET(IMG_CNTN_SET1_OFFSET, val);
+ if (val > 10) {
+ debug("Secondary image boot disabled!\n");
+ return raw_sect;
+ }
+
+ if (val == 0)
+ offset = SZ_4M;
+ else if (val == 1)
+ offset = SZ_2M;
+ else if (val == 2)
+ offset = SZ_1M;
+ else /* flash.bin offset = 1 MiB * 2^n */
+ offset = SZ_1M << val;
+
+ offset /= 512;
+ offset -= CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET;
+
+ if (imx8m_detect_secondary_image_boot())
+ raw_sect += offset;
+
+ return raw_sect;
+}
#endif
bool is_usb_boot(void)
@@ -1246,6 +1309,82 @@
return 0;
}
+#define OPTEE_SHM_SIZE 0x00400000
+static int ft_add_optee_node(void *fdt, struct bd_info *bd)
+{
+ struct fdt_memory carveout;
+ const char *path, *subpath;
+ phys_addr_t optee_start;
+ size_t optee_size;
+ int offs;
+ int ret;
+
+ /*
+ * No TEE space allocated indicating no TEE running, so no
+ * need to add optee node in dts
+ */
+ if (!rom_pointer[1])
+ return 0;
+
+ optee_start = (phys_addr_t)rom_pointer[0];
+ optee_size = rom_pointer[1] - OPTEE_SHM_SIZE;
+
+ offs = fdt_increase_size(fdt, 512);
+ if (offs) {
+ printf("No Space for dtb\n");
+ return 1;
+ }
+
+ path = "/firmware";
+ offs = fdt_path_offset(fdt, path);
+ if (offs < 0) {
+ path = "/";
+ offs = fdt_path_offset(fdt, path);
+
+ if (offs < 0) {
+ printf("Could not find root node.\n");
+ return offs;
+ }
+
+ subpath = "firmware";
+ offs = fdt_add_subnode(fdt, offs, subpath);
+ if (offs < 0) {
+ printf("Could not create %s node.\n", subpath);
+ return offs;
+ }
+ }
+
+ subpath = "optee";
+ offs = fdt_add_subnode(fdt, offs, subpath);
+ if (offs < 0) {
+ printf("Could not create %s node.\n", subpath);
+ return offs;
+ }
+
+ fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz");
+ fdt_setprop_string(fdt, offs, "method", "smc");
+
+ carveout.start = optee_start,
+ carveout.end = optee_start + optee_size - 1,
+ ret = fdtdec_add_reserved_memory(fdt, "optee_core", &carveout, NULL, 0,
+ NULL, FDTDEC_RESERVED_MEMORY_NO_MAP);
+ if (ret < 0) {
+ printf("Could not create optee_core node.\n");
+ return ret;
+ }
+
+ carveout.start = optee_start + optee_size;
+ carveout.end = optee_start + optee_size + OPTEE_SHM_SIZE - 1;
+ ret = fdtdec_add_reserved_memory(fdt, "optee_shm", &carveout, NULL, 0,
+ NULL, FDTDEC_RESERVED_MEMORY_NO_MAP);
+ if (ret < 0) {
+ printf("Could not create optee_shm node.\n");
+ return ret;
+ }
+
+ return 0;
+}
+
int ft_system_setup(void *blob, struct bd_info *bd)
{
#ifdef CONFIG_IMX8MQ
@@ -1395,7 +1534,7 @@
fixup_thermal_trips(blob, "soc-thermal"))
printf("Failed to update soc-thermal trip(s)");
- return 0;
+ return ft_add_optee_node(blob, bd);
}
#endif
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index e23cf60..fd436dd 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -803,12 +803,7 @@
return 0;
}
-
-static int imx8ulp_evt_dm_post_init(void *ctx, struct event *event)
-{
- return imx8ulp_dm_post_init();
-}
-EVENT_SPY(EVT_DM_POST_INIT_F, imx8ulp_evt_dm_post_init);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx8ulp_dm_post_init);
#if defined(CONFIG_SPL_BUILD)
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 55c2801..86b45be 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -552,7 +552,7 @@
return 0;
}
-int imx9_probe_mu(void *ctx, struct event *event)
+int imx9_probe_mu(void)
{
struct udevice *devp;
int node, ret;
@@ -576,7 +576,7 @@
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, imx9_probe_mu);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx9_probe_mu);
int timer_init(void)
{
diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig
index d3233d8..d2e4205 100644
--- a/arch/arm/mach-imx/mxs/Kconfig
+++ b/arch/arm/mach-imx/mxs/Kconfig
@@ -18,9 +18,6 @@
select PL01X_SERIAL
select BOARD_EARLY_INIT_F
-config TARGET_XFI3
- bool "Support xfi3"
-
endchoice
config SYS_SOC
@@ -57,7 +54,6 @@
config SPL_MXS_PMU_MINIMAL_VDD5V_CURRENT
bool "Force minimal current draw from VDD5V by MX28 PMU"
- default n
help
After setting this option, the current drawn from VDD5V
by the PMU is reduced to zero - the DCDC_BATT is used as
@@ -65,7 +61,6 @@
config SPL_MXS_PMU_DISABLE_BATT_CHARGE
bool "Disable Battery Charging in MX28 PMU"
- default n
config SPL_MXS_PMU_ENABLE_4P2_LINEAR_REGULATOR
bool "Enable the 4P2 linear regulator in MX28 PMU"
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index 6c13b00..b30cd96 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -353,7 +353,7 @@
debug("%s: ivt: %p offset: %lx size: %lx\n", __func__, ivt, offset, size);
debug("%s: ivt self: %x\n", __func__, ivt->self);
- if (imx_hab_authenticate_image((uintptr_t)fit, (uintptr_t)ivt, offset))
+ if (imx_hab_authenticate_image((uintptr_t)fit, (uintptr_t)size, offset))
panic("spl: ERROR: image authentication unsuccessful\n");
return (void *)fit;
diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c
index 4af4169..5eb5a3d 100644
--- a/arch/arm/mach-imx/spl_imx_romapi.c
+++ b/arch/arm/mach-imx/spl_imx_romapi.c
@@ -6,11 +6,11 @@
#include <common.h>
#include <errno.h>
#include <image.h>
+#include <imx_container.h>
#include <log.h>
#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <spl.h>
-#include <asm/mach-imx/image.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -111,7 +111,8 @@
load.read = spl_romapi_read_seekable;
load.priv = &pagesize;
return spl_load_simple_fit(spl_image, &load, offset / pagesize, header);
- } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) {
+ } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) &&
+ valid_container_hdr((void *)header)) {
struct spl_load_info load;
memset(&load, 0, sizeof(load));
@@ -133,6 +134,41 @@
return -1;
}
+struct stream_state {
+ u8 *base;
+ u8 *end;
+ u32 pagesize;
+};
+
+static ulong spl_romapi_read_stream(struct spl_load_info *load, ulong sector,
+ ulong count, void *buf)
+{
+ struct stream_state *ss = load->priv;
+ u8 *end = (u8*)(sector + count);
+ u32 bytes;
+ int ret;
+
+ if (end > ss->end) {
+ bytes = end - ss->end;
+ bytes += ss->pagesize - 1;
+ bytes /= ss->pagesize;
+ bytes *= ss->pagesize;
+
+ debug("downloading another 0x%x bytes\n", bytes);
+ ret = rom_api_download_image(ss->end, 0, bytes);
+
+ if (ret != ROM_API_OKAY) {
+ printf("Failure download %d\n", bytes);
+ return 0;
+ }
+
+ ss->end += bytes;
+ }
+
+ memcpy(buf, (void *)(sector), count);
+ return count;
+}
+
static ulong spl_ram_load_read(struct spl_load_info *load, ulong sector,
ulong count, void *buf)
{
@@ -149,23 +185,6 @@
return count;
}
-static ulong get_fit_image_size(void *fit)
-{
- struct spl_image_info spl_image;
- struct spl_load_info spl_load_info;
- ulong last = (ulong)fit;
-
- memset(&spl_load_info, 0, sizeof(spl_load_info));
- spl_load_info.bl_len = 1;
- spl_load_info.read = spl_ram_load_read;
- spl_load_info.priv = &last;
-
- spl_load_simple_fit(&spl_image, &spl_load_info,
- (uintptr_t)fit, fit);
-
- return last - (ulong)fit;
-}
-
static u8 *search_fit_header(u8 *p, int size)
{
int i;
@@ -184,7 +203,8 @@
for (i = 0; i < size; i += 4) {
hdr = p + i;
- if (*(hdr + 3) == 0x87 && *hdr == 0 && (*(hdr + 1) != 0 || *(hdr + 2) != 0))
+ if (valid_container_hdr((void *)hdr) &&
+ (*(hdr + 1) != 0 || *(hdr + 2) != 0))
return p + i;
}
@@ -226,9 +246,7 @@
static int img_total_size(void *img_hdr)
{
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) {
- return get_fit_image_size(img_hdr);
- } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) {
+ if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) {
int total = get_container_size((ulong)img_hdr, NULL);
if (total < 0) {
@@ -267,7 +285,7 @@
ret = rom_api_download_image(p, 0, pg);
if (ret != ROM_API_OKAY) {
- puts("Steam(USB) download failure\n");
+ puts("Stream(USB) download failure\n");
return -1;
}
@@ -287,7 +305,7 @@
ret = rom_api_download_image(p, 0, pg);
if (ret != ROM_API_OKAY) {
- puts("Steam(USB) download failure\n");
+ puts("Stream(USB) download failure\n");
return -1;
}
@@ -316,6 +334,21 @@
}
}
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) {
+ struct stream_state ss;
+
+ ss.base = phdr;
+ ss.end = p;
+ ss.pagesize = pagesize;
+
+ memset(&load, 0, sizeof(load));
+ load.bl_len = 1;
+ load.read = spl_romapi_read_stream;
+ load.priv = &ss;
+
+ return spl_load_simple_fit(spl_image, &load, (ulong)phdr, phdr);
+ }
+
total = img_total_size(phdr);
total += 3;
total &= ~0x3;
@@ -336,9 +369,7 @@
load.bl_len = 1;
load.read = spl_ram_load_read;
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT))
- return spl_load_simple_fit(spl_image, &load, (ulong)phdr, phdr);
- else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER))
+ if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER))
return spl_load_imx_container(spl_image, &load, (ulong)phdr);
return -1;
diff --git a/arch/arm/mach-imx/syscounter.c b/arch/arm/mach-imx/syscounter.c
index 129efac..16df118 100644
--- a/arch/arm/mach-imx/syscounter.c
+++ b/arch/arm/mach-imx/syscounter.c
@@ -59,7 +59,7 @@
return usec;
}
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || IS_ENABLED(CONFIG_SPL_BUILD)
int timer_init(void)
{
struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index fd77b8b..c7ca0fd 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
# Lokesh Vutla <lokeshvutla@ti.com>
obj-$(CONFIG_SOC_K3_J721E) += j721e/ j7200/
diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c
index 0e5d442..8fa36f7 100644
--- a/arch/arm/mach-k3/am625_init.c
+++ b/arch/arm/mach-k3/am625_init.c
@@ -80,8 +80,6 @@
writel(stat, CTRLMMR_MCU_RST_CTRL);
}
-#if defined(CONFIG_CPU_V7R)
-
/*
* RTC Erratum i2327 Workaround for Silicon Revision 1
*
@@ -94,7 +92,7 @@
*
* https://www.ti.com/lit/er/sprz487c/sprz487c.pdf
*/
-void rtc_erratumi2327_init(void)
+static __maybe_unused void rtc_erratumi2327_init(void)
{
u32 counter;
@@ -112,19 +110,17 @@
*/
writel(K3RTC_KICK0_UNLOCK_VALUE, REG_K3RTC_KICK0);
writel(K3RTC_KICK1_UNLOCK_VALUE, REG_K3RTC_KICK1);
- return;
}
-#endif
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
-#if defined(CONFIG_CPU_V7R)
- setup_k3_mpu_regions();
- rtc_erratumi2327_init();
-#endif
+ if (IS_ENABLED(CONFIG_CPU_V7R)) {
+ setup_k3_mpu_regions();
+ rtc_erratumi2327_init();
+ }
/*
* Cannot delay this further as there is a chance that
@@ -156,29 +152,28 @@
preloader_console_init();
-#ifdef CONFIG_K3_EARLY_CONS
/*
* Allow establishing an early console as required for example when
* doing a UART-based boot. Note that this console may not "survive"
* through a SYSFW PM-init step and will need a re-init in some way
* due to changing module clock frequencies.
*/
- early_console_init();
-#endif
+ if (IS_ENABLED(CONFIG_K3_EARLY_CONS))
+ early_console_init();
-#if defined(CONFIG_K3_LOAD_SYSFW)
/*
* Configure and start up system controller firmware. Provide
* the U-Boot console init function to the SYSFW post-PM configuration
* callback hook, effectively switching on (or over) the console
* output.
*/
- ret = is_rom_loaded_sysfw(&bootdata);
- if (!ret)
- panic("ROM has not loaded TIFS firmware\n");
+ if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
+ ret = is_rom_loaded_sysfw(&bootdata);
+ if (!ret)
+ panic("ROM has not loaded TIFS firmware\n");
- k3_sysfw_loader(true, NULL, NULL);
-#endif
+ k3_sysfw_loader(true, NULL, NULL);
+ }
/*
* Force probe of clk_k3 driver here to ensure basic default clock
@@ -209,11 +204,11 @@
enable_mcu_esm_reset();
}
-#if defined(CONFIG_K3_AM64_DDRSS)
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret)
- panic("DRAM init failed: %d\n", ret);
-#endif
+ if (IS_ENABLED(CONFIG_K3_AM64_DDRSS)) {
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret)
+ panic("DRAM init failed: %d\n", ret);
+ }
spl_enable_dcache();
}
@@ -225,9 +220,15 @@
u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
-
switch (bootmode) {
case BOOT_DEVICE_EMMC:
+ if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) {
+ if (spl_mmc_emmc_boot_partition(mmc))
+ return MMCSD_MODE_EMMCBOOT;
+ return MMCSD_MODE_FS;
+ }
+ if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4))
+ return MMCSD_MODE_FS;
return MMCSD_MODE_EMMCBOOT;
case BOOT_DEVICE_MMC:
if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK)
diff --git a/arch/arm/mach-k3/am62ax/dev-data.c b/arch/arm/mach-k3/am62ax/dev-data.c
index abf5d8e..6cced9e 100644
--- a/arch/arm/mach-k3/am62ax/dev-data.c
+++ b/arch/arm/mach-k3/am62ax/dev-data.c
@@ -52,6 +52,7 @@
PSC_DEV(161, &soc_lpsc_list[5]),
PSC_DEV(162, &soc_lpsc_list[6]),
PSC_DEV(75, &soc_lpsc_list[7]),
+ PSC_DEV(36, &soc_lpsc_list[8]),
PSC_DEV(102, &soc_lpsc_list[8]),
PSC_DEV(146, &soc_lpsc_list[8]),
PSC_DEV(166, &soc_lpsc_list[9]),
diff --git a/arch/arm/mach-k3/am654_init.c b/arch/arm/mach-k3/am654_init.c
index 0d3889c..9353a47 100644
--- a/arch/arm/mach-k3/am654_init.c
+++ b/arch/arm/mach-k3/am654_init.c
@@ -2,7 +2,7 @@
/*
* AM6: SoC specific initialization
*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
diff --git a/arch/arm/mach-k3/cache.S b/arch/arm/mach-k3/cache.S
index a5717ea..17cfb12 100644
--- a/arch/arm/mach-k3/cache.S
+++ b/arch/arm/mach-k3/cache.S
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
* Andrew F. Davis <afd@ti.com>
*/
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index a351104..d8974d6 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -2,7 +2,7 @@
/*
* K3: Common Architecture initialization
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
@@ -13,6 +13,7 @@
#include <log.h>
#include <spl.h>
#include <asm/global_data.h>
+#include <linux/printk.h>
#include "common.h"
#include <dm.h>
#include <remoteproc.h>
@@ -83,10 +84,10 @@
ti_sci->version.firmware_revision, fw_desc);
}
-void mmr_unlock(phys_addr_t base, u32 partition)
+void mmr_unlock(uintptr_t base, u32 partition)
{
/* Translate the base address */
- phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
+ uintptr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
/* Unlock the requested partition if locked using two-step sequence */
writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index 9bd9ad6..04f3c0b 100644
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -2,7 +2,7 @@
/*
* K3: Architecture common definitions
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
@@ -38,7 +38,7 @@
int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr);
void k3_sysfw_print_ver(void);
void spl_enable_dcache(void);
-void mmr_unlock(phys_addr_t base, u32 partition);
+void mmr_unlock(uintptr_t base, u32 partition);
bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data);
enum k3_device_type get_device_type(void);
void ti_secure_image_post_process(void **p_image, size_t *p_size);
diff --git a/arch/arm/mach-k3/config_secure.mk b/arch/arm/mach-k3/config_secure.mk
deleted file mode 100644
index 7bc8af8..0000000
--- a/arch/arm/mach-k3/config_secure.mk
+++ /dev/null
@@ -1,44 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Copyright (C) 2018 Texas Instruments, Incorporated - http://www.ti.com/
-# Andrew F. Davis <afd@ti.com>
-
-quiet_cmd_k3secureimg = SECURE $@
-ifneq ($(TI_SECURE_DEV_PKG),)
-ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh),)
-cmd_k3secureimg = $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh \
- $< $@ \
- $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-else
-cmd_k3secureimg = echo "WARNING:" \
- "$(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh not found." \
- "$@ was NOT secured!"; cp $< $@
-endif
-else
-cmd_k3secureimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \
- "variable must be defined for TI secure devices." \
- "$@ was NOT secured!"; cp $< $@
-endif
-
-%.dtb_HS: %.dtb FORCE
- $(call if_changed,k3secureimg)
-
-$(obj)/u-boot-spl-nodtb.bin_HS: $(obj)/u-boot-spl-nodtb.bin FORCE
- $(call if_changed,k3secureimg)
-
-tispl.bin_HS: $(obj)/u-boot-spl-nodtb.bin_HS $(patsubst %,$(obj)/dts/%.dtb_HS,$(subst ",,$(CONFIG_SPL_OF_LIST))) $(SPL_ITS) FORCE
- $(call if_changed,mkfitimage)
-
-MKIMAGEFLAGS_u-boot.img_HS = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
- -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
- $(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST)))
-
-OF_LIST_TARGETS = $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
-$(OF_LIST_TARGETS): dtbs
-
-u-boot-nodtb.bin_HS: u-boot-nodtb.bin FORCE
- $(call if_changed,k3secureimg)
-
-u-boot.img_HS: u-boot-nodtb.bin_HS u-boot.img $(patsubst %.dtb,%.dtb_HS,$(OF_LIST_TARGETS)) FORCE
- $(call if_changed,mkimage)
diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h
index 029041f..9913964 100644
--- a/arch/arm/mach-k3/include/mach/am6_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am6_hardware.h
@@ -2,7 +2,7 @@
/*
* K3: AM6 SoC definitions, structures etc.
*
- * (C) Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * (C) Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __ASM_ARCH_AM6_HARDWARE_H
#define __ASM_ARCH_AM6_HARDWARE_H
diff --git a/arch/arm/mach-k3/include/mach/am6_spl.h b/arch/arm/mach-k3/include/mach/am6_spl.h
index 61e0380..4c6950f 100644
--- a/arch/arm/mach-k3/include/mach/am6_spl.h
+++ b/arch/arm/mach-k3/include/mach/am6_spl.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
#ifndef _ASM_ARCH_AM6_SPL_H_
diff --git a/arch/arm/mach-k3/include/mach/clock.h b/arch/arm/mach-k3/include/mach/clock.h
index e3adbcd..32368ce 100644
--- a/arch/arm/mach-k3/include/mach/clock.h
+++ b/arch/arm/mach-k3/include/mach/clock.h
@@ -2,7 +2,7 @@
/*
* K3: Common SoC clock definitions.
*
- * (C) Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * (C) Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
index 65742c4..a1a9dfb 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
#ifndef _ASM_ARCH_HARDWARE_H_
diff --git a/arch/arm/mach-k3/include/mach/j721e_hardware.h b/arch/arm/mach-k3/include/mach/j721e_hardware.h
index 376db38..7803411 100644
--- a/arch/arm/mach-k3/include/mach/j721e_hardware.h
+++ b/arch/arm/mach-k3/include/mach/j721e_hardware.h
@@ -2,7 +2,7 @@
/*
* K3: J721E SoC definitions, structures etc.
*
- * (C) Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * (C) Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __ASM_ARCH_J721E_HARDWARE_H
#define __ASM_ARCH_J721E_HARDWARE_H
diff --git a/arch/arm/mach-k3/include/mach/j721e_spl.h b/arch/arm/mach-k3/include/mach/j721e_spl.h
index e894791..ed3d733 100644
--- a/arch/arm/mach-k3/include/mach/j721e_spl.h
+++ b/arch/arm/mach-k3/include/mach/j721e_spl.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
#ifndef _ASM_ARCH_J721E_SPL_H_
diff --git a/arch/arm/mach-k3/include/mach/j721s2_hardware.h b/arch/arm/mach-k3/include/mach/j721s2_hardware.h
index 7948bcf..ad4fcdd 100644
--- a/arch/arm/mach-k3/include/mach/j721s2_hardware.h
+++ b/arch/arm/mach-k3/include/mach/j721s2_hardware.h
@@ -2,7 +2,7 @@
/*
* K3: J721S2 SoC definitions, structures etc.
*
- * (C) Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ * (C) Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __ASM_ARCH_J721S2_HARDWARE_H
#define __ASM_ARCH_J721S2_HARDWARE_H
diff --git a/arch/arm/mach-k3/include/mach/j721s2_spl.h b/arch/arm/mach-k3/include/mach/j721s2_spl.h
index 94b6c13..d8fae2c 100644
--- a/arch/arm/mach-k3/include/mach/j721s2_spl.h
+++ b/arch/arm/mach-k3/include/mach/j721s2_spl.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
* David Huang <d-huang@ti.com>
*/
#ifndef _ASM_ARCH_J721S2_SPL_H_
diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h
index 356cd89..3ddc7eb 100644
--- a/arch/arm/mach-k3/include/mach/spl.h
+++ b/arch/arm/mach-k3/include/mach/spl.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
#ifndef _ASM_ARCH_SPL_H_
diff --git a/arch/arm/mach-k3/j7200/Makefile b/arch/arm/mach-k3/j7200/Makefile
index ff9abd7..0f91cf4 100644
--- a/arch/arm/mach-k3/j7200/Makefile
+++ b/arch/arm/mach-k3/j7200/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
obj-y += clk-data.o
obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/j7200/dev-data.c b/arch/arm/mach-k3/j7200/dev-data.c
index 4ddc342..8ce6796 100644
--- a/arch/arm/mach-k3/j7200/dev-data.c
+++ b/arch/arm/mach-k3/j7200/dev-data.c
@@ -46,6 +46,7 @@
static struct ti_dev soc_dev_list[] = {
PSC_DEV(30, &soc_lpsc_list[0]),
+ PSC_DEV(35, &soc_lpsc_list[0]),
PSC_DEV(61, &soc_lpsc_list[1]),
PSC_DEV(90, &soc_lpsc_list[2]),
PSC_DEV(8, &soc_lpsc_list[3]),
diff --git a/arch/arm/mach-k3/j721e/Makefile b/arch/arm/mach-k3/j721e/Makefile
index ff9abd7..0f91cf4 100644
--- a/arch/arm/mach-k3/j721e/Makefile
+++ b/arch/arm/mach-k3/j721e/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
obj-y += clk-data.o
obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/j721e/dev-data.c b/arch/arm/mach-k3/j721e/dev-data.c
index 97f017f..b0adb18 100644
--- a/arch/arm/mach-k3/j721e/dev-data.c
+++ b/arch/arm/mach-k3/j721e/dev-data.c
@@ -56,6 +56,7 @@
PSC_DEV(4, &soc_lpsc_list[8]),
PSC_DEV(202, &soc_lpsc_list[9]),
PSC_DEV(203, &soc_lpsc_list[10]),
+ PSC_DEV(35, &soc_lpsc_list[11]),
PSC_DEV(102, &soc_lpsc_list[11]),
PSC_DEV(103, &soc_lpsc_list[11]),
PSC_DEV(104, &soc_lpsc_list[11]),
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index b616457..18814c3 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -2,7 +2,7 @@
/*
* J721E: SoC specific initialization
*
- * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
@@ -229,6 +229,18 @@
pinctrl_select_state(dev, "default");
/*
+ * Force probe of clk_k3 driver here to ensure basic default clock
+ * configuration is always done.
+ */
+ if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(ti_clk),
+ &dev);
+ if (ret)
+ panic("Failed to initialize clk-k3!\n");
+ }
+
+ /*
* Load, start up, and configure system controller firmware. Provide
* the U-Boot console init function to the SYSFW post-PM configuration
* callback hook, effectively switching on (or over) the console
@@ -241,18 +253,6 @@
do_dt_magic();
#endif
- /*
- * Force probe of clk_k3 driver here to ensure basic default clock
- * configuration is always done.
- */
- if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
- ret = uclass_get_device_by_driver(UCLASS_CLK,
- DM_DRIVER_GET(ti_clk),
- &dev);
- if (ret)
- panic("Failed to initialize clk-k3!\n");
- }
-
/* Prepare console output */
preloader_console_init();
diff --git a/arch/arm/mach-k3/j721s2/Makefile b/arch/arm/mach-k3/j721s2/Makefile
index 7bcd490..e794bff 100644
--- a/arch/arm/mach-k3/j721s2/Makefile
+++ b/arch/arm/mach-k3/j721s2/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
obj-y += clk-data.o
obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/j721s2/dev-data.c b/arch/arm/mach-k3/j721s2/dev-data.c
index 8c999a3..df70c5e 100644
--- a/arch/arm/mach-k3/j721s2/dev-data.c
+++ b/arch/arm/mach-k3/j721s2/dev-data.c
@@ -47,6 +47,7 @@
};
static struct ti_dev soc_dev_list[] = {
+ PSC_DEV(35, &soc_lpsc_list[0]),
PSC_DEV(108, &soc_lpsc_list[0]),
PSC_DEV(109, &soc_lpsc_list[0]),
PSC_DEV(110, &soc_lpsc_list[0]),
diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c
index 712a7e2..7170a80 100644
--- a/arch/arm/mach-k3/j721s2_init.c
+++ b/arch/arm/mach-k3/j721s2_init.c
@@ -2,7 +2,7 @@
/*
* J721E: SoC specific initialization
*
- * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
* David Huang <d-huang@ti.com>
*/
@@ -219,7 +219,7 @@
struct udevice *dev;
int ret;
- if (IS_ENABLED(CONFIG_TARGET_J721S2_R5_EVM)) {
+ if (IS_ENABLED(CONFIG_K3_J721E_DDRSS)) {
ret = uclass_get_device_by_name(UCLASS_MISC, "msmc", &dev);
if (ret)
panic("Probe of msmc failed: %d\n", ret);
diff --git a/arch/arm/mach-k3/lowlevel_init.S b/arch/arm/mach-k3/lowlevel_init.S
index 70c5d1c..463ab0d 100644
--- a/arch/arm/mach-k3/lowlevel_init.S
+++ b/arch/arm/mach-k3/lowlevel_init.S
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
diff --git a/arch/arm/mach-k3/r5_mpu.c b/arch/arm/mach-k3/r5_mpu.c
index 2aec962..605f793 100644
--- a/arch/arm/mach-k3/r5_mpu.c
+++ b/arch/arm/mach-k3/r5_mpu.c
@@ -2,7 +2,7 @@
/*
* K3: R5 MPU region definitions
*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c
index 89659f4..ebc9704 100644
--- a/arch/arm/mach-k3/security.c
+++ b/arch/arm/mach-k3/security.c
@@ -2,7 +2,7 @@
/*
* K3: Security functions
*
- * Copyright (C) 2018-2022 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
* Andrew F. Davis <afd@ti.com>
*/
diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index 9be2d9e..73a1727 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -2,7 +2,7 @@
/*
* K3: System Firmware Loader
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* Andreas Dannenberg <dannenberg@ti.com>
*/
@@ -321,7 +321,7 @@
static void *k3_sysfw_get_spi_addr(void)
{
struct udevice *dev;
- fdt_addr_t addr;
+ void *addr;
int ret;
unsigned int sf_bus = spl_spi_boot_bus();
@@ -329,11 +329,11 @@
if (ret)
return NULL;
- addr = dev_read_addr_index(dev, 1);
- if (addr == FDT_ADDR_T_NONE)
+ addr = dev_read_addr_index_ptr(dev, 1);
+ if (!addr)
return NULL;
- return (void *)(addr + CONFIG_K3_SYSFW_IMAGE_SPI_OFFS);
+ return addr + CONFIG_K3_SYSFW_IMAGE_SPI_OFFS;
}
static void k3_sysfw_spi_copy(u32 *dst, u32 *src, size_t len)
@@ -349,18 +349,18 @@
static void *get_sysfw_hf_addr(void)
{
struct udevice *dev;
- fdt_addr_t addr;
+ void *addr;
int ret;
ret = uclass_find_first_device(UCLASS_MTD, &dev);
if (ret)
return NULL;
- addr = dev_read_addr_index(dev, 1);
- if (addr == FDT_ADDR_T_NONE)
+ addr = dev_read_addr_index_ptr(dev, 1);
+ if (!addr)
return NULL;
- return (void *)(addr + CONFIG_K3_SYSFW_IMAGE_SPI_OFFS);
+ return addr + CONFIG_K3_SYSFW_IMAGE_SPI_OFFS;
}
#endif
diff --git a/arch/arm/mach-k3/sysfw-loader.h b/arch/arm/mach-k3/sysfw-loader.h
index b23a9e8..e48c834 100644
--- a/arch/arm/mach-k3/sysfw-loader.h
+++ b/arch/arm/mach-k3/sysfw-loader.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* Andreas Dannenberg <dannenberg@ti.com>
*/
diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c
index b863bab..e91b0d6 100644
--- a/arch/arm/mach-keystone/mon.c
+++ b/arch/arm/mach-keystone/mon.c
@@ -2,7 +2,7 @@
/*
* K2x: Secure commands file
*
- * Copyright (C) 2012-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012-2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <hang.h>
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 54027cc..c2fff84 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -133,6 +133,12 @@
select KW88F6192
select KIRKWOOD_COMMON
+config TARGET_NSA325
+ bool "ZyXEL NSA325"
+ select FEROCEON_88FR131
+ select KW88F6281
+ select KIRKWOOD_COMMON
+
config TARGET_SBx81LIFKW
bool "Allied Telesis SBx81GS24/SBx81GT40/SBx81XS6/SBx81XS16"
select FEROCEON_88FR131
@@ -177,6 +183,7 @@
source "board/Seagate/goflexhome/Kconfig"
source "board/Seagate/nas220/Kconfig"
source "board/zyxel/nsa310s/Kconfig"
+source "board/zyxel/nsa325/Kconfig"
source "board/alliedtelesis/SBx81LIFKW/Kconfig"
source "board/alliedtelesis/SBx81LIFXCAT/Kconfig"
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 669ca09..d6c8905 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -11,6 +11,7 @@
select PWRSEQ
select MMC_PWRSEQ
select BOARD_LATE_INIT
+ select MESON_SM
imply CMD_DM
config MESON_GX
diff --git a/arch/arm/mach-meson/board-gx.c b/arch/arm/mach-meson/board-gx.c
index f28f84d..c3fbdff 100644
--- a/arch/arm/mach-meson/board-gx.c
+++ b/arch/arm/mach-meson/board-gx.c
@@ -15,6 +15,7 @@
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/armv8/mmu.h>
+#include <linux/printk.h>
#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c
index d600c64d..914fd11 100644
--- a/arch/arm/mach-meson/sm.c
+++ b/arch/arm/mach-meson/sm.c
@@ -6,7 +6,11 @@
*/
#include <common.h>
+#include <dm.h>
#include <log.h>
+#include <regmap.h>
+#include <sm.h>
+#include <syscon.h>
#include <asm/arch/sm.h>
#include <asm/cache.h>
#include <asm/global_data.h>
@@ -14,74 +18,63 @@
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/kernel.h>
-#include <dm.h>
#include <linux/bitfield.h>
-#include <regmap.h>
-#include <syscon.h>
+#include <meson/sm.h>
-#define FN_GET_SHARE_MEM_INPUT_BASE 0x82000020
-#define FN_GET_SHARE_MEM_OUTPUT_BASE 0x82000021
-#define FN_EFUSE_READ 0x82000030
-#define FN_EFUSE_WRITE 0x82000031
-#define FN_CHIP_ID 0x82000044
-#define FN_PWRDM_SET 0x82000093
-
-static void *shmem_input;
-static void *shmem_output;
-
-static void meson_init_shmem(void)
+static inline struct udevice *meson_get_sm_device(void)
{
- struct pt_regs regs;
+ struct udevice *dev;
+ int err;
- if (shmem_input && shmem_output)
- return;
+ err = uclass_first_device_err(UCLASS_SM, &dev);
+ if (err) {
+ pr_err("Mesom SM device not found\n");
+ return ERR_PTR(err);
+ }
- regs.regs[0] = FN_GET_SHARE_MEM_INPUT_BASE;
- smc_call(®s);
- shmem_input = (void *)regs.regs[0];
-
- regs.regs[0] = FN_GET_SHARE_MEM_OUTPUT_BASE;
- smc_call(®s);
- shmem_output = (void *)regs.regs[0];
-
- debug("Secure Monitor shmem: 0x%p 0x%p\n", shmem_input, shmem_output);
+ return dev;
}
ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size)
{
- struct pt_regs regs;
+ struct udevice *dev;
+ struct pt_regs regs = { 0 };
+ int err;
- meson_init_shmem();
+ dev = meson_get_sm_device();
+ if (IS_ERR(dev))
+ return PTR_ERR(dev);
- regs.regs[0] = FN_EFUSE_READ;
regs.regs[1] = offset;
regs.regs[2] = size;
- smc_call(®s);
+ err = sm_call_read(dev, buffer, size,
+ MESON_SMC_CMD_EFUSE_READ, ®s);
+ if (err < 0)
+ pr_err("Failed to read efuse memory (%d)\n", err);
- if (regs.regs[0] == 0)
- return -1;
-
- memcpy(buffer, shmem_output, min(size, regs.regs[0]));
-
- return regs.regs[0];
+ return err;
}
ssize_t meson_sm_write_efuse(uintptr_t offset, void *buffer, size_t size)
{
- struct pt_regs regs;
+ struct udevice *dev;
+ struct pt_regs regs = { 0 };
+ int err;
- meson_init_shmem();
+ dev = meson_get_sm_device();
+ if (IS_ERR(dev))
+ return PTR_ERR(dev);
- memcpy(shmem_input, buffer, size);
-
- regs.regs[0] = FN_EFUSE_WRITE;
regs.regs[1] = offset;
regs.regs[2] = size;
- smc_call(®s);
+ err = sm_call_write(dev, buffer, size,
+ MESON_SMC_CMD_EFUSE_WRITE, ®s);
+ if (err < 0)
+ pr_err("Failed to write efuse memory (%d)\n", err);
- return regs.regs[0];
+ return err;
}
#define SM_CHIP_ID_LENGTH 119
@@ -90,18 +83,21 @@
int meson_sm_get_serial(void *buffer, size_t size)
{
- struct pt_regs regs;
+ struct udevice *dev;
+ struct pt_regs regs = { 0 };
+ u8 id_buffer[SM_CHIP_ID_LENGTH];
+ int err;
- meson_init_shmem();
+ dev = meson_get_sm_device();
+ if (IS_ERR(dev))
+ return PTR_ERR(dev);
- regs.regs[0] = FN_CHIP_ID;
- regs.regs[1] = 0;
- regs.regs[2] = 0;
+ err = sm_call_read(dev, id_buffer, SM_CHIP_ID_LENGTH,
+ MESON_SMC_CMD_CHIP_ID_GET, ®s);
+ if (err < 0)
+ pr_err("Failed to read serial number (%d)\n", err);
- smc_call(®s);
-
- memcpy(buffer, shmem_output + SM_CHIP_ID_OFFSET,
- min_t(size_t, size, SM_CHIP_ID_SIZE));
+ memcpy(buffer, id_buffer + SM_CHIP_ID_OFFSET, size);
return 0;
}
@@ -141,13 +137,21 @@
int meson_sm_pwrdm_set(size_t index, int cmd)
{
- struct pt_regs regs;
+ struct udevice *dev;
+ struct pt_regs regs = { 0 };
+ int err;
- regs.regs[0] = FN_PWRDM_SET;
+ dev = meson_get_sm_device();
+ if (IS_ERR(dev))
+ return PTR_ERR(dev);
+
regs.regs[1] = index;
regs.regs[2] = cmd;
- smc_call(®s);
+ err = sm_call(dev, MESON_SMC_CMD_PWRDM_SET, NULL, ®s);
+ if (err)
+ pr_err("Failed to %s power domain ind=%zu (%d)\n", cmd == PWRDM_ON ?
+ "enable" : "disable", index, err);
- return regs.regs[0];
+ return err;
}
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 5c7f4bf..c80d858 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -144,8 +144,12 @@
select ATSHA204A
config TARGET_TURRIS_MOX
- bool "Support Turris Mox"
+ bool "Support CZ.NIC's Turris Mox / RIPE Atlas Probe"
select ARMADA_3700
+ select BOARD_TYPES
+ select ENV_IS_IN_MMC
+ select ENV_IS_IN_SPI_FLASH
+ select MULTI_DTB_FIT
config TARGET_MVEBU_ARMADA_8K
bool "Support Armada 7k/8k platforms"
diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c
index 379daa8..79f8877 100644
--- a/arch/arm/mach-mvebu/spl.c
+++ b/arch/arm/mach-mvebu/spl.c
@@ -71,8 +71,9 @@
#error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR must be set to 0
#endif
#if !defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET) || \
- CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET != 0
-#error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET must be set to 0
+ (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET != 0 && \
+ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET != 4096)
+#error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET must be set to either 0 or 4096
#endif
#endif
@@ -123,8 +124,8 @@
{
return IS_SD(mmc) ? MMCSD_MODE_RAW : MMCSD_MODE_EMMCBOOT;
}
-unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
- unsigned long raw_sect)
+unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
+ unsigned long raw_sect)
{
return IS_SD(mmc) ? 1 : 0;
}
diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile
index 2aa8013..3f1af7f 100644
--- a/arch/arm/mach-omap2/am33xx/Makefile
+++ b/arch/arm/mach-omap2/am33xx/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+# Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
obj-$(CONFIG_AM33XX) += clock_am33xx.o
obj-$(CONFIG_AM43XX) += clock_am43xx.o
diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
index ecc0a59..09659da 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -4,7 +4,7 @@
*
* Common board functions for AM33XX based boards
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
@@ -42,6 +42,7 @@
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/compiler.h>
+#include <linux/printk.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/musb.h>
@@ -270,11 +271,7 @@
return ret;
#if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
- ret = usb_ether_init();
- if (ret) {
- pr_err("USB ether init failed\n");
- return ret;
- }
+ usb_ether_init();
#endif
return 0;
@@ -527,7 +524,7 @@
#endif
-static int am33xx_dm_post_init(void *ctx, struct event *event)
+static int am33xx_dm_post_init(void)
{
hw_data_init();
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
@@ -535,4 +532,4 @@
#endif
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, am33xx_dm_post_init);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, am33xx_dm_post_init);
diff --git a/arch/arm/mach-omap2/am33xx/chilisom.c b/arch/arm/mach-omap2/am33xx/chilisom.c
index 459bac1..d4f2abe 100644
--- a/arch/arm/mach-omap2/am33xx/chilisom.c
+++ b/arch/arm/mach-omap2/am33xx/chilisom.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
* Copyright (C) 2017, Grinn - http://grinn-global.com/
*/
diff --git a/arch/arm/mach-omap2/am33xx/clk_synthesizer.c b/arch/arm/mach-omap2/am33xx/clk_synthesizer.c
index c9b9502..0969a40 100644
--- a/arch/arm/mach-omap2/am33xx/clk_synthesizer.c
+++ b/arch/arm/mach-omap2/am33xx/clk_synthesizer.c
@@ -4,7 +4,7 @@
*
* Clock synthesizer apis
*
- * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2016, Texas Instruments, Incorporated - https://www.ti.com/
*/
diff --git a/arch/arm/mach-omap2/am33xx/clock.c b/arch/arm/mach-omap2/am33xx/clock.c
index 130ee6c..3273632 100644
--- a/arch/arm/mach-omap2/am33xx/clock.c
+++ b/arch/arm/mach-omap2/am33xx/clock.c
@@ -5,7 +5,7 @@
* Clock initialization for AM33XX boards.
* Derived from OMAP4 boards
*
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
#include <hang.h>
diff --git a/arch/arm/mach-omap2/am33xx/clock_am33xx.c b/arch/arm/mach-omap2/am33xx/clock_am33xx.c
index cd3b34b..d39e7e4 100644
--- a/arch/arm/mach-omap2/am33xx/clock_am33xx.c
+++ b/arch/arm/mach-omap2/am33xx/clock_am33xx.c
@@ -4,7 +4,7 @@
*
* clocks for AM33XX based boards
*
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/arch/arm/mach-omap2/am33xx/clock_am43xx.c b/arch/arm/mach-omap2/am33xx/clock_am43xx.c
index b98bb99..8039bc2 100644
--- a/arch/arm/mach-omap2/am33xx/clock_am43xx.c
+++ b/arch/arm/mach-omap2/am33xx/clock_am43xx.c
@@ -5,7 +5,7 @@
* clocks for AM43XX based boards
* Derived from AM33XX based boards
*
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c
index 5f970d9..61b95c9 100644
--- a/arch/arm/mach-omap2/am33xx/ddr.c
+++ b/arch/arm/mach-omap2/am33xx/ddr.c
@@ -2,7 +2,7 @@
/*
* DDR Configuration for AM33xx devices.
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/arch/arm/mach-omap2/am33xx/emif4.c b/arch/arm/mach-omap2/am33xx/emif4.c
index bf3da43..b29250b 100644
--- a/arch/arm/mach-omap2/am33xx/emif4.c
+++ b/arch/arm/mach-omap2/am33xx/emif4.c
@@ -4,7 +4,7 @@
*
* AM33XX emif4 configuration file
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/arch/arm/mach-omap2/am33xx/mux.c b/arch/arm/mach-omap2/am33xx/mux.c
index aad3ec8..4960559 100644
--- a/arch/arm/mach-omap2/am33xx/mux.c
+++ b/arch/arm/mach-omap2/am33xx/mux.c
@@ -1,7 +1,7 @@
/*
* mux.c
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/mach-omap2/am33xx/sys_info.c b/arch/arm/mach-omap2/am33xx/sys_info.c
index 338f6af..390d540 100644
--- a/arch/arm/mach-omap2/am33xx/sys_info.c
+++ b/arch/arm/mach-omap2/am33xx/sys_info.c
@@ -4,7 +4,7 @@
*
* System information functions
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*
* Derived from Beagle Board and 3430 SDP code by
* Richard Woodruff <r-woodruff2@ti.com>
diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c
index a2dd5f6..a68b21a 100644
--- a/arch/arm/mach-omap2/boot-common.c
+++ b/arch/arm/mach-omap2/boot-common.c
@@ -4,7 +4,7 @@
*
* Common bootmode functions for omap based boards
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/arch/arm/mach-omap2/config.mk b/arch/arm/mach-omap2/config.mk
index 4f0d259..30d8fb1 100644
--- a/arch/arm/mach-omap2/config.mk
+++ b/arch/arm/mach-omap2/config.mk
@@ -1,5 +1,5 @@
#
-# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+# Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
#
# SPDX-License-Identifier: GPL-2.0+
diff --git a/arch/arm/mach-omap2/config_secure.mk b/arch/arm/mach-omap2/config_secure.mk
index 24ddcdb..40db1ae 100644
--- a/arch/arm/mach-omap2/config_secure.mk
+++ b/arch/arm/mach-omap2/config_secure.mk
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
+# Copyright (C) 2016, Texas Instruments, Incorporated - https://www.ti.com/
quiet_cmd_mkomapsecimg = SECURE $@
ifneq ($(TI_SECURE_DEV_PKG),)
ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh),)
@@ -102,7 +102,7 @@
ifdef CONFIG_SPL_LOAD_FIT
MKIMAGEFLAGS_u-boot_HS.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST)))
diff --git a/arch/arm/mach-omap2/hwinit-common.c b/arch/arm/mach-omap2/hwinit-common.c
index 7715333..0e4572c 100644
--- a/arch/arm/mach-omap2/hwinit-common.c
+++ b/arch/arm/mach-omap2/hwinit-common.c
@@ -174,7 +174,7 @@
* done in each of these cases
* This function is called with SRAM stack.
*/
-void early_system_init(void)
+int early_system_init(void)
{
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT)
int ret;
@@ -225,6 +225,8 @@
debug_uart_init();
#endif
prcm_init();
+
+ return 0;
}
#ifdef CONFIG_SPL_BUILD
@@ -240,13 +242,7 @@
}
#endif
-static int omap2_system_init(void *ctx, struct event *event)
-{
- early_system_init();
-
- return 0;
-}
-EVENT_SPY(EVT_DM_POST_INIT_F, omap2_system_init);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, early_system_init);
/*
* Routine: wait_for_command_complete
diff --git a/arch/arm/mach-omap2/omap3/emif4.c b/arch/arm/mach-omap2/omap3/emif4.c
index 491e7c2..7e5a281 100644
--- a/arch/arm/mach-omap2/omap3/emif4.c
+++ b/arch/arm/mach-omap2/omap3/emif4.c
@@ -6,7 +6,7 @@
* Based on mem.c and sdrc.c
*
* Copyright (C) 2010
- * Texas Instruments Incorporated - http://www.ti.com/
+ * Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/arch/arm/mach-omap2/omap3/sdrc.c b/arch/arm/mach-omap2/omap3/sdrc.c
index 07f534a..5d43e7c 100644
--- a/arch/arm/mach-omap2/omap3/sdrc.c
+++ b/arch/arm/mach-omap2/omap3/sdrc.c
@@ -7,7 +7,7 @@
* generic init function (mem_init).
*
* Copyright (C) 2004-2010
- * Texas Instruments Incorporated - http://www.ti.com/
+ * Texas Instruments Incorporated - https://www.ti.com/
*
* Copyright (C) 2011
* Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
diff --git a/arch/arm/mach-omap2/utils.c b/arch/arm/mach-omap2/utils.c
index 7d93872..0623281 100644
--- a/arch/arm/mach-omap2/utils.c
+++ b/arch/arm/mach-omap2/utils.c
@@ -9,6 +9,7 @@
#include <asm/setup.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
+#include <linux/printk.h>
static void do_cancel_out(u32 *num, u32 *den, u32 factor)
{
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index b7f7980..054782e 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -1,7 +1,7 @@
/*
* Voltage Controller implementation for OMAP
*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
* Nishanth Menon
*
* This program is free software; you can redistribute it and/or modify
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index 3061ccd..2bb9674 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -9,7 +9,6 @@
select PHY
select PINCONF
select PINCTRL
- select PINCTRL_PFC
select POSITION_INDEPENDENT
imply CMD_FS_UUID
imply CMD_GPT
@@ -29,6 +28,7 @@
bool "Renesas ARM SoCs R-Car Gen3 (64bit)"
select RCAR_64
select SUPPORT_SPL
+ select PINCTRL_PFC
imply SPL
imply SPL_BOARD_INIT
imply SPL_GZIP
@@ -43,6 +43,7 @@
config RCAR_GEN4
bool "Renesas ARM SoCs R-Car Gen4 (64bit)"
select RCAR_64
+ select PINCTRL_PFC
config RZA1
prompt "Renesas ARM SoCs RZ/A1 (32bit)"
@@ -66,6 +67,24 @@
select SYSRESET_SYSCON
imply CMD_DM
+config RZG2L
+ prompt "Renesas RZ/G2L Family ARM SoCs"
+ select GICV3
+ select RCAR_64
+ imply CLK_RZG2L
+ imply MULTI_DTB_FIT
+ imply MULTI_DTB_FIT_USER_DEFINED_AREA
+ imply PINCTRL_RZG2L
+ imply RENESAS_SDHI
+ imply RZG2L_GPIO
+ imply SCIF_CONSOLE
+ imply SYS_MALLOC_F
+ help
+ Enable support for the Renesas RZ/G2L family of SoCs. Currently
+ support is only included for the RZ/G2L itself (based on the R9A07G044
+ SoC). Support for additional SoCs in this family (RZ/G2LC, RZ/G2UL,
+ RZ/V2L & RZ/Five) is not yet available.
+
endchoice
config SYS_SOC
@@ -75,5 +94,6 @@
source "arch/arm/mach-rmobile/Kconfig.64"
source "arch/arm/mach-rmobile/Kconfig.rza1"
source "arch/arm/mach-rmobile/Kconfig.rzn1"
+source "arch/arm/mach-rmobile/Kconfig.rzg2l"
endif
diff --git a/arch/arm/mach-rmobile/Kconfig.rzg2l b/arch/arm/mach-rmobile/Kconfig.rzg2l
new file mode 100644
index 0000000..dc30bdf
--- /dev/null
+++ b/arch/arm/mach-rmobile/Kconfig.rzg2l
@@ -0,0 +1,32 @@
+# Copyright (C) 2023 Renesas Electronics Corporation
+# SPDX-License-Identifier: GPL-2.0+
+
+if RZG2L
+
+config R9A07G044L
+ bool "Renesas R9A07G044L SoC"
+ imply CLK_R9A07G044
+ help
+ Enable support for the Renesas R9A07G044L (RZ/G2L) SoC.
+
+choice
+ prompt "Renesas RZ/G2L Family Board selection"
+ default TARGET_RZG2L_SMARC_EVK
+
+config TARGET_RZG2L_SMARC_EVK
+ bool "Renesas RZ/G2L SMARC EVK"
+ imply R9A07G044L
+ help
+ Enable support for the RZ/G2L SMARC evaluation board.
+
+source "board/renesas/rzg2l/Kconfig"
+
+endchoice
+
+config MULTI_DTB_FIT_UNCOMPRESS_SZ
+ default 0x80000 if TARGET_RZG2L_SMARC_EVK
+
+config MULTI_DTB_FIT_USER_DEF_ADDR
+ default 0x49000000 if TARGET_RZG2L_SMARC_EVK
+
+endif
diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index 4eddba5..ff8b0c7 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -10,8 +10,11 @@
obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
-obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
+obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o
+obj-$(CONFIG_RCAR_GEN3) += cpu_info-rcar.o memmap-gen3.o
+obj-$(CONFIG_RCAR_GEN4) += cpu_info-rcar.o memmap-gen3.o
obj-$(CONFIG_RZ_G2) += cpu_info-rzg.o
+obj-$(CONFIG_RZG2L) += cpu_info-rzg2l.o memmap-rzg2l.o
ifneq ($(CONFIG_R8A779A0),)
obj-$(CONFIG_ARMV8_PSCI) += psci-r8a779a0.o
diff --git a/arch/arm/mach-rmobile/board.c b/arch/arm/mach-rmobile/board.c
index a10371f..79c7e02 100644
--- a/arch/arm/mach-rmobile/board.c
+++ b/arch/arm/mach-rmobile/board.c
@@ -3,7 +3,7 @@
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* (C) Copyright 2012 Renesas Solutions Corp.
*/
-#include <common.h>
+
#include <init.h>
#include <asm/io.h>
diff --git a/arch/arm/mach-rmobile/cpu_info-r8a7740.c b/arch/arm/mach-rmobile/cpu_info-r8a7740.c
index dcbe25f..5a94235 100644
--- a/arch/arm/mach-rmobile/cpu_info-r8a7740.c
+++ b/arch/arm/mach-rmobile/cpu_info-r8a7740.c
@@ -3,7 +3,7 @@
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* (C) Copyright 2012 Renesas Solutions Corp.
*/
-#include <common.h>
+
#include <asm/io.h>
u32 rmobile_get_cpu_type(void)
diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c b/arch/arm/mach-rmobile/cpu_info-rcar.c
index 8fc4cd7..b9d8b5e 100644
--- a/arch/arm/mach-rmobile/cpu_info-rcar.c
+++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
@@ -4,7 +4,7 @@
*
* Copyright (C) 2013,2014 Renesas Electronics Corporation
*/
-#include <common.h>
+
#include <asm/io.h>
#define PRR_MASK 0x7fff
diff --git a/arch/arm/mach-rmobile/cpu_info-rzg.c b/arch/arm/mach-rmobile/cpu_info-rzg.c
index 1c18fd0..4ade4bc 100644
--- a/arch/arm/mach-rmobile/cpu_info-rzg.c
+++ b/arch/arm/mach-rmobile/cpu_info-rzg.c
@@ -3,7 +3,7 @@
* Copyright (C) 2021 Renesas Electronics Corporation
*
*/
-#include <common.h>
+
#include <linux/libfdt.h>
/* If the firmware passed a device tree, use it for soc identification. */
diff --git a/arch/arm/mach-rmobile/cpu_info-rzg2l.c b/arch/arm/mach-rmobile/cpu_info-rzg2l.c
new file mode 100644
index 0000000..f69649d
--- /dev/null
+++ b/arch/arm/mach-rmobile/cpu_info-rzg2l.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021,2023 Renesas Electronics Corporation
+ *
+ */
+
+#include <asm/io.h>
+#include <linux/libfdt.h>
+
+#define SYSC_LSI_DEVID 0x11020A04
+
+/* If the firmware passed a device tree, use it for soc identification. */
+extern u64 rcar_atf_boot_args[];
+
+/* CPU information table */
+struct tfa_info {
+ const char *soc_name;
+ const char *cpu_name;
+ u32 cpu_type;
+};
+
+static const struct tfa_info tfa_info[] = {
+ { "renesas,r9a07g044l2", "R9A07G044L", RMOBILE_CPU_TYPE_R9A07G044L },
+};
+
+static const struct tfa_info invalid_tfa_info = { NULL, "(invalid)", 0 };
+
+static const struct tfa_info *get_tfa_info(void)
+{
+ void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
+
+ if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) {
+ unsigned int i;
+ for (i = 0; i < ARRAY_SIZE(tfa_info); i++) {
+ if (!fdt_node_check_compatible(atf_fdt_blob, 0,
+ tfa_info[i].soc_name))
+ return &tfa_info[i];
+ }
+ }
+
+ return &invalid_tfa_info;
+}
+
+const u8 *rzg_get_cpu_name(void)
+{
+ return get_tfa_info()->cpu_name;
+}
+
+u32 rmobile_get_cpu_type(void)
+{
+ return get_tfa_info()->cpu_type;
+}
+
+u32 rmobile_get_cpu_rev_integer(void)
+{
+ return (readl(SYSC_LSI_DEVID) >> 28) + 1;
+}
+
+u32 rmobile_get_cpu_rev_fraction(void)
+{
+ return 0;
+}
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index 7651e43..895c0f5 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -3,7 +3,7 @@
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* (C) Copyright 2012-2021 Renesas Solutions Corp.
*/
-#include <common.h>
+
#include <cpu_func.h>
#include <asm/cache.h>
#include <init.h>
@@ -83,14 +83,15 @@
static int rmobile_cpuinfo_idx(void)
{
- int i = 0;
u32 cpu_type = rmobile_get_cpu_type();
+ int i;
- for (; i < ARRAY_SIZE(rmobile_cpuinfo) - 1; i++)
+ for (i = 0; i < ARRAY_SIZE(rmobile_cpuinfo) - 1; i++)
if (rmobile_cpuinfo[i].cpu_type == cpu_type)
- break;
+ return i;
- return i;
+ /* Unknown "CPU" entry */
+ return ARRAY_SIZE(rmobile_cpuinfo) - 1;
}
static const u8 *get_cpu_name(int idx)
diff --git a/arch/arm/mach-rmobile/emac.c b/arch/arm/mach-rmobile/emac.c
index cb9bce0..9565162 100644
--- a/arch/arm/mach-rmobile/emac.c
+++ b/arch/arm/mach-rmobile/emac.c
@@ -6,7 +6,6 @@
* Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
*/
-#include <common.h>
#include <net.h>
#include <linux/errno.h>
#include <netdev.h>
diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h
index a14c2aa..88b8b78 100644
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -19,6 +19,8 @@
#elif defined(CONFIG_RCAR_GEN4)
#include <asm/arch/rcar-gen4-base.h>
#elif defined(CONFIG_R7S72100)
+#elif defined(CONFIG_RZG2L)
+#include <asm/arch/rzg2l.h>
#else
#error "SOC Name not defined"
#endif
@@ -41,8 +43,11 @@
#define RMOBILE_CPU_TYPE_R8A779A0 0x59
#define RMOBILE_CPU_TYPE_R8A779F0 0x5A
#define RMOBILE_CPU_TYPE_R8A779G0 0x5C
+#define RMOBILE_CPU_TYPE_R9A07G044L 0x9A070440
#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
const u8 *rzg_get_cpu_name(void);
u32 rmobile_get_cpu_type(void);
u32 rmobile_get_cpu_rev_integer(void);
diff --git a/arch/arm/mach-rmobile/include/mach/rzg2l.h b/arch/arm/mach-rmobile/include/mach/rzg2l.h
new file mode 100644
index 0000000..057df5c
--- /dev/null
+++ b/arch/arm/mach-rmobile/include/mach/rzg2l.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * RZ/G2L SoC Family support.
+ * Copyright (C) 2023 Renesas Electronics Corporation
+ */
+
+#ifndef __ASM_ARCH_RZG2L_H
+#define __ASM_ARCH_RZG2L_H
+
+#define GICD_BASE 0x11900000
+#define GICR_BASE 0x11960000
+
+#endif /* __ASM_ARCH_RZG2L_H */
diff --git a/arch/arm/mach-rmobile/memmap-gen3.c b/arch/arm/mach-rmobile/memmap-gen3.c
index a68eb80..4dff9e0 100644
--- a/arch/arm/mach-rmobile/memmap-gen3.c
+++ b/arch/arm/mach-rmobile/memmap-gen3.c
@@ -5,10 +5,10 @@
* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
*/
-#include <common.h>
-#include <cpu_func.h>
#include <asm/armv8/mmu.h>
#include <asm/global_data.h>
+#include <asm/u-boot.h>
+#include <cpu_func.h>
#define GEN3_NR_REGIONS 16
diff --git a/arch/arm/mach-rmobile/memmap-rzg2l.c b/arch/arm/mach-rmobile/memmap-rzg2l.c
new file mode 100644
index 0000000..9934a77
--- /dev/null
+++ b/arch/arm/mach-rmobile/memmap-rzg2l.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Renesas RZ/G2L family memory map tables
+ *
+ * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2023 Renesas Electronics Corp.
+ */
+
+#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
+#include <asm/u-boot.h>
+#include <cpu_func.h>
+
+#define RZG2L_NR_REGIONS 16
+
+/*
+ * RZ/G2L supports up to 4 GiB RAM starting at 0x40000000, of
+ * which the first 128 MiB is reserved by TF-A.
+ */
+static struct mm_region rzg2l_mem_map[RZG2L_NR_REGIONS] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x03F00000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x47E00000UL,
+ .phys = 0x47E00000UL,
+ .size = 0xF8200000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = rzg2l_mem_map;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define debug_memmap(i, map) \
+ debug("memmap %d: virt 0x%llx -> phys 0x%llx, size=0x%llx, attrs=0x%llx\n", \
+ i, map[i].virt, map[i].phys, map[i].size, map[i].attrs)
+
+void enable_caches(void)
+{
+ unsigned int bank, i = 0;
+ u64 start, size;
+
+ /* Create map for register access */
+ rzg2l_mem_map[i].virt = 0x0ULL;
+ rzg2l_mem_map[i].phys = 0x0ULL;
+ rzg2l_mem_map[i].size = 0x40000000ULL;
+ rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN;
+ debug_memmap(i, rzg2l_mem_map);
+ i++;
+
+ /* Generate entries for DRAM in 32bit address space */
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ start = gd->bd->bi_dram[bank].start;
+ size = gd->bd->bi_dram[bank].size;
+
+ /* Skip empty DRAM banks */
+ if (!size)
+ continue;
+
+ /* Mark memory reserved by ATF as cacheable too. */
+ if (start == 0x48000000) {
+ /* Unmark protection area (0x43F00000 to 0x47DFFFFF) */
+ rzg2l_mem_map[i].virt = 0x40000000ULL;
+ rzg2l_mem_map[i].phys = 0x40000000ULL;
+ rzg2l_mem_map[i].size = 0x03F00000ULL;
+ rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE;
+ debug_memmap(i, rzg2l_mem_map);
+ i++;
+
+ start = 0x47E00000ULL;
+ size += 0x00200000ULL;
+ }
+
+ rzg2l_mem_map[i].virt = start;
+ rzg2l_mem_map[i].phys = start;
+ rzg2l_mem_map[i].size = size;
+ rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE;
+ debug_memmap(i, rzg2l_mem_map);
+ i++;
+ }
+
+ /* Zero out the remaining regions. */
+ for (; i < RZG2L_NR_REGIONS; i++) {
+ rzg2l_mem_map[i].virt = 0;
+ rzg2l_mem_map[i].phys = 0;
+ rzg2l_mem_map[i].size = 0;
+ rzg2l_mem_map[i].attrs = 0;
+ debug_memmap(i, rzg2l_mem_map);
+ }
+
+ if (!icache_status())
+ icache_enable();
+
+ dcache_enable();
+}
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
+
+ return 0;
+}
diff --git a/arch/arm/mach-rmobile/pfc-r8a7740.c b/arch/arm/mach-rmobile/pfc-r8a7740.c
index 5d42a68..4f48476 100644
--- a/arch/arm/mach-rmobile/pfc-r8a7740.c
+++ b/arch/arm/mach-rmobile/pfc-r8a7740.c
@@ -18,7 +18,7 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <common.h>
+
#include <sh_pfc.h>
#include <asm/gpio.h>
#include <asm/arch/irqs.h>
diff --git a/arch/arm/mach-rmobile/psci-r8a779a0.c b/arch/arm/mach-rmobile/psci-r8a779a0.c
index 6a85eb2..b6c49e7 100644
--- a/arch/arm/mach-rmobile/psci-r8a779a0.c
+++ b/arch/arm/mach-rmobile/psci-r8a779a0.c
@@ -6,7 +6,6 @@
*
*/
-#include <common.h>
#include <asm/io.h>
#include <asm/psci.h>
#include <asm/secure.h>
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index a279582..b577a91 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -166,7 +166,6 @@
imply SPL_SYSCON
imply SPL_RAM
imply SPL_SERIAL
- imply TPL_SERIAL
imply SPL_SEPARATE_BSS
help
The Rockchip RK3308 is a ARM-based Soc which embedded with quad
@@ -360,6 +359,8 @@
select BOARD_LATE_INIT
imply ROCKCHIP_COMMON_BOARD
imply OF_LIBFDT_OVERLAY
+ imply ROCKCHIP_OTP
+ imply MISC_INIT_R
imply TPL_DM
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
@@ -402,7 +403,7 @@
config TPL_ROCKCHIP_BACK_TO_BROM
bool "TPL returns to bootrom"
default y
- select ROCKCHIP_BROM_HELPER
+ select ROCKCHIP_BROM_HELPER if !ROCKCHIP_RK3066
select TPL_BOOTROM_SUPPORT
depends on TPL
help
@@ -436,7 +437,7 @@
config ROCKCHIP_EXTERNAL_TPL
bool "Use external TPL binary"
- default y if ROCKCHIP_RK3568 || ROCKCHIP_RK3588
+ default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3588
help
Some Rockchip SoCs require an external TPL to initialize DRAM.
Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
@@ -451,7 +452,6 @@
config ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON
bool "Disable device boot on power plug-in"
depends on PMIC_RK8XX
- default n
---help---
Say Y here to prevent the device from booting up because of a plug-in
event. When set, the device will boot briefly to determine why it was
@@ -470,7 +470,7 @@
config ROCKCHIP_SPL_RESERVE_IRAM
hex "Size of IRAM reserved in SPL"
- default 0
+ default 0x0
help
SPL may need reserve memory for firmware loaded by SPL, whose load
address is in IRAM and may overlay with SPL text area if not
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index 8d7b39b..57f08e0 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -299,9 +299,9 @@
.hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
};
-int usb_gadget_handle_interrupts(int index)
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
{
- dwc3_uboot_handle_interrupt(0);
+ dwc3_uboot_handle_interrupt(dev);
return 0;
}
diff --git a/arch/arm/mach-rockchip/boot_mode.c b/arch/arm/mach-rockchip/boot_mode.c
index 1a1a887..eb8f65a 100644
--- a/arch/arm/mach-rockchip/boot_mode.c
+++ b/arch/arm/mach-rockchip/boot_mode.c
@@ -12,6 +12,7 @@
#include <asm/arch-rockchip/boot_mode.h>
#include <dm/device.h>
#include <dm/uclass.h>
+#include <linux/printk.h>
#if (CONFIG_ROCKCHIP_BOOT_MODE_REG == 0)
diff --git a/arch/arm/mach-rockchip/rk3066/Kconfig b/arch/arm/mach-rockchip/rk3066/Kconfig
index 95d7fc8..4a79a82 100644
--- a/arch/arm/mach-rockchip/rk3066/Kconfig
+++ b/arch/arm/mach-rockchip/rk3066/Kconfig
@@ -10,6 +10,14 @@
config ROCKCHIP_BOOT_MODE_REG
default 0x20004040
+config ROCKCHIP_BOOT_LR_REG
+ hex
+ default 0x00001058
+
+config ROCKCHIP_BOOT_RETURN_REG
+ hex
+ default 0x00001100
+
config SYS_SOC
default "rk3066"
diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c
index df8fa15..c807221 100644
--- a/arch/arm/mach-rockchip/rk3188/rk3188.c
+++ b/arch/arm/mach-rockchip/rk3188/rk3188.c
@@ -17,6 +17,7 @@
#include <asm/arch-rockchip/hardware.h>
#include <dm/ofnode.h>
#include <linux/err.h>
+#include <linux/printk.h>
#define GRF_BASE 0x20008000
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
index cbd2ea0..14565d2 100644
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -20,6 +20,7 @@
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/hardware.h>
#include <linux/bitops.h>
+#include <linux/printk.h>
#include <power/regulator.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig
index 79fcc99..e5282dd 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -6,6 +6,51 @@
help
RK3588 EVB is a evaluation board for Rockchp RK3588.
+config TARGET_NANOPCT6_RK3588
+ bool "FriendlyElec NanoPC-T6 RK3588 board"
+ select BOARD_LATE_INIT
+ help
+ The NanoPC-T6 is a Rockchip RK3588 based SBC by FriendlyElec.
+
+ There are four variants depending on the DRAM size: 4G/32GB eMMC,
+ 8G/64GB eMMC, 16G/16MB SPI NOR, and 16G/256GB eMMC/16MB SPI NOR
+
+ Specifications:
+
+ CPU: Rockchip RK3588, 4x Cortex-A76 (up to 2.4GHz)
+ + 4x Cortex-A55 (up to 1.8GHz)
+ GPU: Mali-G610 MP4
+ VPU: 8K@60fps H.265 and VP9 decoder, 8K@30fps H.264 decoder,
+ 4K@60fps AV1 decoder, 8K@30fps H.264 and H.265 encoder
+ NPU: 6TOPs, supports INT4/INT8/INT16/FP16
+ RAM: 64-bit 4GB/8GB/16GB LPDDR4X at 2133MHz
+ eMMC: 0GB/32GB/64GB/256GB HS400
+ MicroSD Slot: MicroSD SDR104
+ PCIe 3.0: M.2 M-Key x1, PCIe 3.0 x4 for NVMe SSDs up to 2,500 MB/s
+ Ethernet: PCIe 2.5G 2x Ethernet (RTL8125BG)
+ PCIe 2.1: M.2 E-Key x1, PCIe 2.1 x1 and USB2.0 Host,
+ supports M.2 WiFi and Bluetooth
+ 4G Module: MiniPCIe x1, MicroSIM Card Slot x1
+ Audio Out: 3.5mm jack for stereo headphone output
+ Audio In: 2.0mm PH-2A connector for analog microphone input
+ Video Input: standard HDMI input port, up to 4Kp60
+ 2x 4-lane MIPI-CSI, compatible with MIPI V1.2
+ Video Output: 2x standard HDMI output ports compatible with HDMI2.1,
+ HDMI2.0, and HDMI1.4
+ 2x 4-lane MIPI-DSI, compatible with MIPI DPHY 2.0 or CPHY 1.1
+ USB-A: USB 3.0, Type A
+ USB-C: Full function USB Type‑C port, DP display up to 4Kp60, USB 3.0
+ 40-pin 2.54mm header connector: up to 2x SPIs, 6x UARTs, 1x I2Cs,
+ 8x PWMs, 2x I2Ss, 28x GPIOs
+ Debug UART: 3 Pin 2.54mm header, 3V level, 1500000bps
+ Onboard IR receiver: 38KHz carrier frequency
+ RTC Battery: 2 Pin 1.27/1.25mm RTC battery connector for low power
+ RTC IC HYM8563TS
+ 5V Fan connector
+ Working Temperature: 0C to 70C
+ Power: 5.5*2.1mm DC Jack, 12VDC input
+ Dimensions: 110x80x1.6mm (without case) / 86x114.5x30mm (with case)
+
config TARGET_RK3588_NEU6
bool "Edgeble Neural Compute Module 6(Neu6) SoM"
select BOARD_LATE_INIT
@@ -80,6 +125,13 @@
USB PD over USB Type-C
Size: 100mm x 72mm (Pico-ITX form factor)
+config TARGET_QUARTZPRO64_RK3588
+ bool "Pine64 QuartzPro64 RK3588 board"
+ select BOARD_LATE_INIT
+ help
+ Pine64 QuartzPro64 is a Rockchip RK3588 based SBC (Single Board
+ Computer) by Pine64.
+
config ROCKCHIP_BOOT_MODE_REG
default 0xfd588080
@@ -93,6 +145,8 @@
default 0x80000
source board/edgeble/neural-compute-module-6/Kconfig
+source board/friendlyelec/nanopc-t6-rk3588/Kconfig
+source board/pine64/quartzpro64-rk3588/Kconfig
source board/rockchip/evb_rk3588/Kconfig
source board/radxa/rock5a-rk3588s/Kconfig
source board/radxa/rock5b-rk3588/Kconfig
diff --git a/arch/arm/mach-rockchip/rv1126/Kconfig b/arch/arm/mach-rockchip/rv1126/Kconfig
index 7382c55..a6e2b59 100644
--- a/arch/arm/mach-rockchip/rv1126/Kconfig
+++ b/arch/arm/mach-rockchip/rv1126/Kconfig
@@ -42,6 +42,9 @@
config TPL_STACK
default 0xff718000
+config TPL_SYS_MALLOC_F
+ default y
+
config TPL_SYS_MALLOC_F_LEN
default 0x2000
diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
index 914f4d9..2fc1521 100644
--- a/arch/arm/mach-snapdragon/Kconfig
+++ b/arch/arm/mach-snapdragon/Kconfig
@@ -6,12 +6,14 @@
config SYS_MALLOC_F_LEN
default 0x2000
+config SPL_SYS_MALLOC_F
+ default y
+
config SPL_SYS_MALLOC_F_LEN
default 0x2000
config SDM845
bool "Qualcomm Snapdragon 845 SoC"
- default n
select LINUX_KERNEL_IMAGE_HEADER
config LNX_KRNL_IMG_TEXT_OFFSET_BASE
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 503c82d..114d243 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -30,6 +30,9 @@
config SPL_STACK_R_ADDR
default 0x00800000 if TARGET_SOCFPGA_GEN5
+config SPL_SYS_MALLOC_F
+ default y if TARGET_SOCFPGA_GEN5
+
config SPL_SYS_MALLOC_F_LEN
default 0x800 if TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 5b5a81a..80ad087 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -25,6 +25,7 @@
#include <asm/arch/nic301.h>
#include <asm/arch/scu.h>
#include <asm/pl310.h>
+#include <linux/printk.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-stm32mp/boot_params.c b/arch/arm/mach-stm32mp/boot_params.c
index 24d04dc..158bf40 100644
--- a/arch/arm/mach-stm32mp/boot_params.c
+++ b/arch/arm/mach-stm32mp/boot_params.c
@@ -29,7 +29,7 @@
return (void *)nt_fw_dtb;
log_debug("%s: DTB not found.\n", __func__);
}
- log_debug("%s: fall back to builtin DTB, %p\n", __func__, &_end);
+ log_debug("%s: fall back to builtin DTB, %p\n", __func__, _end);
- return (void *)&_end;
+ return (void *)_end;
}
diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c
index 0dc1e5c..599e63a 100644
--- a/arch/arm/mach-stm32mp/bsec.c
+++ b/arch/arm/mach-stm32mp/bsec.c
@@ -18,6 +18,7 @@
#include <dm/device_compat.h>
#include <linux/arm-smccc.h>
#include <linux/iopoll.h>
+#include <linux/printk.h>
#define BSEC_OTP_MAX_VALUE 95
#define BSEC_OTP_UPPER_START 32
diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c
index 85be8e2..e16fcf4 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32key.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32key.c
@@ -11,6 +11,7 @@
#include <asm/arch/bsec.h>
#include <dm/device.h>
#include <dm/uclass.h>
+#include <linux/printk.h>
/*
* Closed device: OTP0
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
index c695cc1..2411bcf 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
@@ -8,6 +8,7 @@
#include <dfu.h>
#include <image.h>
#include <asm/arch/stm32prog.h>
+#include <linux/printk.h>
#include "stm32prog.h"
struct stm32prog_data *stm32prog_data;
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
index 9ba94be..393f9a1 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
@@ -20,6 +20,7 @@
#include <linux/list.h>
#include <linux/list_sort.h>
#include <linux/mtd/mtd.h>
+#include <linux/printk.h>
#include <linux/sizes.h>
#include "stm32prog.h"
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
index feba295..ae4bd88 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
@@ -6,6 +6,8 @@
#ifndef _STM32PROG_H_
#define _STM32PROG_H_
+#include <linux/printk.h>
+
/* - phase defines ------------------------------------------------*/
#define PHASE_FLASHLAYOUT 0x00
#define PHASE_FIRST_USER 0x10
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
index f1bed7d..35bed31 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
@@ -14,6 +14,7 @@
#include <dm/lists.h>
#include <dm/device-internal.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <asm/global_data.h>
#include "stm32prog.h"
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c
index be38ff2..d18455b 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c
@@ -9,6 +9,7 @@
#include <usb.h>
#include <asm/arch/stm32prog.h>
#include <asm/arch/sys_proto.h>
+#include <linux/printk.h>
#include "stm32prog.h"
static int stm32prog_set_phase(struct stm32prog_data *data, u8 phase,
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index e2f67fc..55574fd 100644
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -15,6 +15,7 @@
#include <lmb.h>
#include <misc.h>
#include <net.h>
+#include <spl.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <asm/arch/sys_proto.h>
@@ -22,7 +23,7 @@
#include <dm/device.h>
#include <dm/uclass.h>
#include <linux/bitops.h>
-#include <spl.h>
+#include <linux/printk.h>
/*
* early TLB into the .data section so that it not get cleared
@@ -39,6 +40,13 @@
TAMP_BOOT_MODE_SHIFT;
}
+u32 get_bootauth(void)
+{
+ /* read boot auth status and partition from TAMP backup register */
+ return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_AUTH_MASK) >>
+ TAMP_BOOT_AUTH_SHIFT;
+}
+
/*
* weak function overidde: set the DDR/SYSRAM executable before to enable the
* MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc)
@@ -90,10 +98,10 @@
if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
return;
- if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
gd->arch.tlb_size = PGTABLE_SIZE;
gd->arch.tlb_addr = (unsigned long)&early_tlb;
- }
+#endif
/* enable MMU (default configuration) */
dcache_enable();
@@ -370,8 +378,24 @@
{
}
+static int setup_boot_auth_info(void)
+{
+ char buf[10];
+ u32 bootauth = get_bootauth();
+
+ snprintf(buf, sizeof(buf), "%d", bootauth >> 4);
+ env_set("boot_auth", buf);
+
+ snprintf(buf, sizeof(buf), "%d", bootauth &
+ (u32)TAMP_BOOT_PARTITION_MASK);
+ env_set("boot_part", buf);
+
+ return 0;
+}
+
int arch_misc_init(void)
{
+ setup_boot_auth_info();
setup_boot_mode();
setup_mac_address();
setup_serial_number();
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
index 1cdc5e3..ac0dece 100644
--- a/arch/arm/mach-stm32mp/include/mach/stm32.h
+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
@@ -139,8 +139,12 @@
#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
#define TAMP_BOOT_MODE_SHIFT 8
+#define TAMP_BOOT_AUTH_MASK GENMASK(23, 16)
+#define TAMP_BOOT_AUTH_SHIFT 16
#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
+#define TAMP_BOOT_AUTH_ST_MASK GENMASK(7, 4)
+#define TAMP_BOOT_PARTITION_MASK GENMASK(3, 0)
#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0)
enum forced_boot_mode {
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h b/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h
index 4ad14f9..1b2bba3 100644
--- a/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h
+++ b/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h
@@ -7,6 +7,7 @@
#define __STM32MP1_SMC_H__
#include <linux/arm-smccc.h>
+#include <linux/printk.h>
/*
* SMC function IDs for STM32 Service queries
diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
index 83fb32a..52aca1e 100644
--- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h
+++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
@@ -66,6 +66,9 @@
/* return boot mode */
u32 get_bootmode(void);
+/* return auth status and partition */
+u32 get_bootauth(void);
+
int get_eth_nb(void);
int setup_mac_address(void);
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index e20c3a3..a4a8d8e 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -85,6 +85,12 @@
help
TPR2 value from vendor DRAM settings.
+config DRAM_SUN50I_H616_TPR6
+ hex "H616 DRAM TPR6 parameter"
+ default 0x3300c080
+ help
+ TPR6 value from vendor DRAM settings.
+
config DRAM_SUN50I_H616_TPR10
hex "H616 DRAM TPR10 parameter"
help
@@ -121,7 +127,7 @@
config SUNXI_SRAM_ADDRESS
hex
default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
- default 0x20000 if SUN50I_GEN_H6
+ default 0x20000 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2
default 0x0
---help---
Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
@@ -183,6 +189,14 @@
Select this for sunxi SoCs which have H6 like peripherals, clocks
and memory map.
+config SUNXI_GEN_NCAT2
+ bool
+ select MMC_SUNXI_HAS_NEW_MODE
+ select SUPPORT_SPL
+ ---help---
+ Select this for sunxi SoCs which have D1 like peripherals, clocks
+ and memory map.
+
config SUNXI_DRAM_DW
bool
---help---
@@ -338,6 +352,19 @@
select SUNXI_DRAM_DW_32BIT
imply SPL_SYS_I2C_LEGACY
+config MACH_SUN8I_R528
+ bool "sun8i (Allwinner R528)"
+ select CPU_V7A
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
+ select ARCH_SUPPORT_PSCI
+ select SPL_ARMV7_SET_CORTEX_SMPEN
+ select SUNXI_GEN_NCAT2
+ select SUNXI_NEW_PINCTRL
+ select MMC_SUNXI_HAS_NEW_MODE
+ select SUPPORT_SPL
+ select DRAM_SUN20I_D1
+
config MACH_SUN8I_V3S
bool "sun8i (Allwinner V3/V3s/S3/S3L)"
select CPU_V7A
@@ -441,6 +468,9 @@
config SUNXI_DRAM_LPDDR3
bool
+config SUNXI_DRAM_LPDDR4
+ bool
+
choice
prompt "DRAM Type and Timing"
default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
@@ -484,6 +514,14 @@
This option is the LPDDR3 timing used by the stock boot0 by
Allwinner.
+config SUNXI_DRAM_H616_LPDDR4
+ bool "LPDDR4 DRAM chips on the H616 DRAM controller"
+ select SUNXI_DRAM_LPDDR4
+ depends on DRAM_SUN50I_H616
+ help
+ This option is the LPDDR4 timing used by the stock boot0 by
+ Allwinner.
+
config SUNXI_DRAM_H616_DDR3_1333
bool "DDR3-1333 boot0 timings on the H616 DRAM controller"
select SUNXI_DRAM_DDR3
@@ -568,7 +606,7 @@
config DRAM_TPR3
hex "sunxi dram tpr3 value"
- default 0
+ default 0x0
---help---
Set the dram controller tpr3 parameter. This parameter configures
the delay on the command lane and also phase shifts, which are
@@ -579,7 +617,7 @@
config DRAM_DQS_GATING_DELAY
hex "sunxi dram dqs_gating_delay value"
- default 0
+ default 0x0
---help---
Set the dram controller dqs_gating_delay parmeter. Each byte
encodes the DQS gating delay for each byte lane. The delay
@@ -648,6 +686,7 @@
default 1008000000 if MACH_SUN9I
default 888000000 if MACH_SUN50I_H6
default 1008000000 if MACH_SUN50I_H616
+ default 1008000000 if MACH_SUN8I_R528
config SYS_CONFIG_NAME
default "suniv" if MACH_SUNIV
@@ -656,6 +695,7 @@
default "sun6i" if MACH_SUN6I
default "sun7i" if MACH_SUN7I
default "sun8i" if MACH_SUN8I
+ default "sun8i" if MACH_SUN8I_R528
default "sun9i" if MACH_SUN9I
default "sun50i" if MACH_SUN50I
default "sun50i" if MACH_SUN50I_H6
@@ -695,13 +735,6 @@
Set this to enable various workarounds for old kernels, this results in
sub-optimal settings for newer kernels, only enable if needed.
-config MACPWR
- string "MAC power pin"
- default ""
- help
- Set the pin used to power the MAC. This takes a string in the format
- understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
config MMC1_PINS_PH
bool "Pins for mmc1 are on Port H"
depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40
@@ -795,7 +828,6 @@
config AXP_DISABLE_BOOT_ON_POWERON
bool "Disable device boot on power plug-in"
depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
- default n
---help---
Say Y here to prevent the device from booting up because of a plug-in
event. When set, the device will boot into the SPL briefly to
@@ -811,6 +843,7 @@
depends on !MACH_SUN9I
depends on !MACH_SUN50I
depends on !SUN50I_GEN_H6
+ depends on !SUNXI_GEN_NCAT2
select VIDEO
select DISPLAY
imply VIDEO_DT_SIMPLEFB
@@ -1008,14 +1041,6 @@
endchoice
-config SATAPWR
- string "SATA power pin"
- default ""
- help
- Set the pins used to power the SATA. This takes a string in the
- format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
- port H.
-
config GMAC_TX_DELAY
int "GMAC Transmit Clock Delay Chain"
default 0
@@ -1032,6 +1057,7 @@
default 0x2fe00000 if MACH_SUN9I
default 0x4fe00000 if MACH_SUN50I
default 0x4fe00000 if SUN50I_GEN_H6
+ default 0x4fe00000 if SUNXI_GEN_NCAT2
config SPL_SPI_SUNXI
bool "Support for SPI Flash on Allwinner SoCs in SPL"
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 58f807c..1d4c70e 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -10,7 +10,6 @@
obj-y += clock.o
obj-y += cpu_info.o
obj-y += dram_helpers.o
-obj-y += pinmux.o
obj-$(CONFIG_SUN6I_PRCM) += prcm.o
obj-$(CONFIG_AXP_PMIC_BUS) += pmic_bus.o
obj-$(CONFIG_MACH_SUNIV) += clock_sun6i.o
@@ -26,6 +25,7 @@
endif
obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o gtbus_sun9i.o
obj-$(CONFIG_SUN50I_GEN_H6) += clock_sun50i_h6.o
+obj-$(CONFIG_SUNXI_GEN_NCAT2) += clock_sun50i_h6.o
ifndef CONFIG_ARM64
obj-y += timer.o
endif
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 78597ad..11a4941 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -17,6 +17,7 @@
#include <i2c.h>
#include <serial.h>
#include <spl.h>
+#include <sunxi_gpio.h>
#include <asm/cache.h>
#include <asm/gpio.h>
#include <asm/io.h>
@@ -146,6 +147,10 @@
sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_R528)
+ sunxi_gpio_set_cfgpin(SUNXI_GPE(2), 6);
+ sunxi_gpio_set_cfgpin(SUNXI_GPE(3), 6);
+ sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV)
sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0);
@@ -162,6 +167,10 @@
sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 4 && defined(CONFIG_MACH_SUN8I_R528)
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(6), 7);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(7), 7);
+ sunxi_gpio_set_pull(SUNXI_GPB(7), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
@@ -175,13 +184,19 @@
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif
-#ifdef CONFIG_SUN50I_GEN_H6
- /* Update PIO power bias configuration by copy hardware detected value */
- val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
- writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
- val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
- writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
-#endif
+ /*
+ * Update PIO power bias configuration by copying the hardware
+ * detected value.
+ */
+ if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
+ IS_ENABLED(CONFIG_SUN50I_GEN_NCAT2)) {
+ val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
+ writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
+ }
+ if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) {
+ val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
+ writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
+ }
return 0;
}
@@ -323,8 +338,8 @@
* Also U-Boot proper is located at least 32KB after the SPL, but will
* immediately follow the SPL if that is bigger than that.
*/
-unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
- unsigned long raw_sect)
+unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
+ unsigned long raw_sect)
{
unsigned long spl_size = sunxi_get_spl_size();
unsigned long sector;
@@ -480,7 +495,7 @@
/* sun5i sometimes gets stuck without this */
writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
}
-#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
+#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
#if defined(CONFIG_MACH_SUN50I_H6)
/* WDOG is broken for some H6 rev. use the R_WDOG instead */
static const struct sunxi_wdog *wdog =
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index 7926394..bea91c7 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -18,8 +18,11 @@
setbits_le32(&prcm->res_cal_ctrl, 2);
}
- clrbits_le32(&prcm->res_cal_ctrl, 1);
- setbits_le32(&prcm->res_cal_ctrl, 1);
+ if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) ||
+ IS_ENABLED(CONFIG_MACH_SUN50I_H6)) {
+ clrbits_le32(&prcm->res_cal_ctrl, 1);
+ setbits_le32(&prcm->res_cal_ctrl, 1);
+ }
if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) {
/* set key field for ldo enable */
@@ -38,7 +41,9 @@
CCM_CPU_AXI_DEFAULT_FACTORS);
writel(CCM_PSI_AHB1_AHB2_DEFAULT, &ccm->psi_ahb1_ahb2_cfg);
+#ifdef CCM_AHB3_DEFAULT
writel(CCM_AHB3_DEFAULT, &ccm->ahb3_cfg);
+#endif
writel(CCM_APB1_DEFAULT, &ccm->apb1_cfg);
/*
@@ -86,11 +91,13 @@
writel(val, &ccm->cpu_axi_cfg);
/* clk = 24*n/p, p is ignored if clock is >288MHz */
- writel(CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2 |
-#ifdef CONFIG_MACH_SUN50I_H616
- CCM_PLL1_OUT_EN |
-#endif
- CCM_PLL1_CTRL_N(clk / 24000000), &ccm->pll1_cfg);
+ val = CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2;
+ val |= CCM_PLL1_CTRL_N(clk / 24000000);
+ if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
+ val |= CCM_PLL1_OUT_EN;
+ if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
+ val |= CCM_PLL1_OUT_EN | CCM_PLL1_LDO_EN;
+ writel(val, &ccm->pll1_cfg);
while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {}
/* Switch CPU to PLL1 */
@@ -105,16 +112,26 @@
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- int m = IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? 4 : 2;
-
uint32_t rval = readl(&ccm->pll6_cfg);
int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
- int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
- CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
- CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
- /* The register defines PLL6-2X or PLL6-4X, not plain PLL6 */
- return 24000000 / m * n / div1 / div2;
+ CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
+ int div1, m;
+
+ if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
+ div1 = ((rval & CCM_PLL6_CTRL_P0_MASK) >>
+ CCM_PLL6_CTRL_P0_SHIFT) + 1;
+ m = 1;
+ } else {
+ div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
+ CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
+ if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
+ m = 4;
+ else
+ m = 2;
+ }
+
+ return 24000000U * n / m / div1 / div2;
}
int clock_twi_onoff(int port, int state)
diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
index 7eef178..7fecc3b 100644
--- a/arch/arm/mach-sunxi/cpu_info.c
+++ b/arch/arm/mach-sunxi/cpu_info.c
@@ -93,6 +93,8 @@
printf("CPU: Allwinner R40 (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN8I_V3S
printf("CPU: Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id());
+#elif defined CONFIG_MACH_SUN8I_R528
+ puts("CPU: Allwinner R528 (SUN8I)\n");
#elif defined CONFIG_MACH_SUN9I
puts("CPU: Allwinner A80 (SUN9I)\n");
#elif defined CONFIG_MACH_SUN50I
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 7e580b6..c5c1331 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -6,8 +6,8 @@
* unknown. That's why this driver has plenty of magic numbers. Some
* meaning was nevertheless deduced from strings found in boot0 and
* known meaning of some dram parameters.
- * This driver only supports DDR3 memory and omits logic for all
- * other supported types supported by hardware.
+ * This driver supports DDR3, LPDDR3 and LPDDR4 memory. There is no
+ * DDR4 support yet.
*
* (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net>
*
@@ -238,64 +238,59 @@
0x08, 0x01, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x07,
0x17, 0x19, 0x1a
+#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR4)
+ 0x02, 0x00, 0x17, 0x05, 0x04, 0x19, 0x06, 0x07,
+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x01,
+ 0x18, 0x03, 0x1a
#endif
};
+#define MASK_BYTE(reg, nr) (((reg) >> ((nr) * 8)) & 0x1f)
static void mctl_phy_configure_odt(const struct dram_para *para)
{
- unsigned int val;
+ uint32_t val_lo, val_hi;
- val = para->dx_dri & 0x1f;
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x388);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x38c);
+ /*
+ * This part should be applicable to all memory types, but is
+ * usually found in LPDDR4 bootloaders. Therefore, we will leave
+ * only for this type of memory.
+ */
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR4) {
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x390, BIT(5), BIT(4));
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x3d0, BIT(5), BIT(4));
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x410, BIT(5), BIT(4));
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x450, BIT(5), BIT(4));
+ }
- val = (para->dx_dri >> 8) & 0x1f;
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c8);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3cc);
+ val_lo = para->dx_dri;
+ val_hi = (para->type == SUNXI_DRAM_TYPE_LPDDR4) ? 0x04040404 : para->dx_dri;
+ writel_relaxed(MASK_BYTE(val_lo, 0), SUNXI_DRAM_PHY0_BASE + 0x388);
+ writel_relaxed(MASK_BYTE(val_hi, 0), SUNXI_DRAM_PHY0_BASE + 0x38c);
+ writel_relaxed(MASK_BYTE(val_lo, 1), SUNXI_DRAM_PHY0_BASE + 0x3c8);
+ writel_relaxed(MASK_BYTE(val_hi, 1), SUNXI_DRAM_PHY0_BASE + 0x3cc);
+ writel_relaxed(MASK_BYTE(val_lo, 2), SUNXI_DRAM_PHY0_BASE + 0x408);
+ writel_relaxed(MASK_BYTE(val_hi, 2), SUNXI_DRAM_PHY0_BASE + 0x40c);
+ writel_relaxed(MASK_BYTE(val_lo, 3), SUNXI_DRAM_PHY0_BASE + 0x448);
+ writel_relaxed(MASK_BYTE(val_hi, 3), SUNXI_DRAM_PHY0_BASE + 0x44c);
- val = (para->dx_dri >> 16) & 0x1f;
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x408);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x40c);
+ val_lo = para->ca_dri;
+ val_hi = para->ca_dri;
+ writel_relaxed(MASK_BYTE(val_lo, 0), SUNXI_DRAM_PHY0_BASE + 0x340);
+ writel_relaxed(MASK_BYTE(val_hi, 0), SUNXI_DRAM_PHY0_BASE + 0x344);
+ writel_relaxed(MASK_BYTE(val_lo, 1), SUNXI_DRAM_PHY0_BASE + 0x348);
+ writel_relaxed(MASK_BYTE(val_hi, 1), SUNXI_DRAM_PHY0_BASE + 0x34c);
- val = (para->dx_dri >> 24) & 0x1f;
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x448);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x44c);
-
- val = para->ca_dri & 0x1f;
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x340);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x344);
-
- val = (para->ca_dri >> 8) & 0x1f;
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x348);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x34c);
-
- val = para->dx_odt & 0x1f;
- if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
- writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x380);
- else
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x380);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x384);
-
- val = (para->dx_odt >> 8) & 0x1f;
- if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
- writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x3c0);
- else
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c0);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c4);
-
- val = (para->dx_odt >> 16) & 0x1f;
- if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
- writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x400);
- else
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x400);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x404);
-
- val = (para->dx_odt >> 24) & 0x1f;
- if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
- writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x440);
- else
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x440);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x444);
+ val_lo = (para->type == SUNXI_DRAM_TYPE_LPDDR3) ? 0 : para->dx_odt;
+ val_hi = (para->type == SUNXI_DRAM_TYPE_LPDDR4) ? 0 : para->dx_odt;
+ writel_relaxed(MASK_BYTE(val_lo, 0), SUNXI_DRAM_PHY0_BASE + 0x380);
+ writel_relaxed(MASK_BYTE(val_hi, 0), SUNXI_DRAM_PHY0_BASE + 0x384);
+ writel_relaxed(MASK_BYTE(val_lo, 1), SUNXI_DRAM_PHY0_BASE + 0x3c0);
+ writel_relaxed(MASK_BYTE(val_hi, 1), SUNXI_DRAM_PHY0_BASE + 0x3c4);
+ writel_relaxed(MASK_BYTE(val_lo, 2), SUNXI_DRAM_PHY0_BASE + 0x400);
+ writel_relaxed(MASK_BYTE(val_hi, 2), SUNXI_DRAM_PHY0_BASE + 0x404);
+ writel_relaxed(MASK_BYTE(val_lo, 3), SUNXI_DRAM_PHY0_BASE + 0x440);
+ writel_relaxed(MASK_BYTE(val_hi, 3), SUNXI_DRAM_PHY0_BASE + 0x444);
dmb();
}
@@ -414,12 +409,18 @@
return result;
}
-static bool mctl_phy_read_training(const struct dram_config *config)
+static bool mctl_phy_read_training(const struct dram_para *para,
+ const struct dram_config *config)
{
u32 val1, val2, *ptr1, *ptr2;
bool result = true;
int i;
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR4) {
+ writel(0, SUNXI_DRAM_PHY0_BASE + 0x800);
+ writel(0, SUNXI_DRAM_PHY0_BASE + 0x81c);
+ }
+
clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x198, 3, 2);
clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x804, 0x3f, 0xf);
clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x808, 0x3f, 0xf);
@@ -600,6 +601,8 @@
clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1);
setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 8);
clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR4)
+ clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x4, 0x80);
if (para->tpr10 & BIT(30))
val = para->tpr11 & 0x3f;
@@ -813,8 +816,9 @@
writel(val, SUNXI_DRAM_PHY0_BASE + 0x7e0);
writel(val, SUNXI_DRAM_PHY0_BASE + 0x7f4);
- if (para->type == SUNXI_DRAM_TYPE_DDR3) {
- val = (para->tpr10 >> 7) & 0x1e;
+ val = (para->tpr10 >> 7) & 0x1e;
+ switch (para->type) {
+ case SUNXI_DRAM_TYPE_DDR3:
if (para->tpr2 & 1) {
writel(val, SUNXI_DRAM_PHY0_BASE + 0x794);
if (config->ranks == 2) {
@@ -840,8 +844,8 @@
writel(val, SUNXI_DRAM_PHY0_BASE + 0x7b8);
}
}
- } else if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
- val = (para->tpr10 >> 7) & 0x1e;
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR3:
if (para->tpr2 & 1) {
writel(val, SUNXI_DRAM_PHY0_BASE + 0x7a0);
if (config->ranks == 2) {
@@ -855,7 +859,18 @@
writel(val, SUNXI_DRAM_PHY0_BASE + 0x7f8);
}
}
- }
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR4:
+ if (para->tpr2 & 1) {
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x788);
+ } else {
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x794);
+ };
+ break;
+ case SUNXI_DRAM_TYPE_DDR4:
+ default:
+ panic("This DRAM setup is currently not supported.\n");
+ };
}
static bool mctl_phy_init(const struct dram_para *para,
@@ -868,30 +883,42 @@
u32 val, val2, *ptr, mr0, mr2;
int i;
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR4)
+ clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x4,0x80);
+
if (config->bus_full_width)
val = 0xf;
else
val = 3;
clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x3c, 0xf, val);
- if (para->tpr2 & 0x100) {
- if (para->type == SUNXI_DRAM_TYPE_DDR3) {
+ switch (para->type) {
+ case SUNXI_DRAM_TYPE_DDR3:
+ if (para->tpr2 & 0x100) {
val = 9;
val2 = 7;
- } else if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
- // untested setup: use some values for now
- val = 14;
- val2 = 8;
- }
- } else {
- if (para->type == SUNXI_DRAM_TYPE_DDR3) {
+ } else {
val = 13;
val2 = 9;
- } else if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
+ }
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR3:
+ if (para->tpr2 & 0x100) {
+ val = 12;
+ val2 = 6;
+ } else {
val = 14;
val2 = 8;
}
- }
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR4:
+ val = 20;
+ val2 = 10;
+ break;
+ case SUNXI_DRAM_TYPE_DDR4:
+ default:
+ panic("This DRAM setup is currently not supported.\n");
+ };
writel(val, SUNXI_DRAM_PHY0_BASE + 0x14);
writel(val, SUNXI_DRAM_PHY0_BASE + 0x35c);
@@ -915,19 +942,40 @@
if (para->tpr10 & TPR10_CA_BIT_DELAY)
mctl_phy_ca_bit_delay_compensation(para, config);
- if (para->type == SUNXI_DRAM_TYPE_DDR3)
- val = 0x80;
- else if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
- val = 0xc0;
+ switch (para->type) {
+ case SUNXI_DRAM_TYPE_DDR3:
+ val = para->tpr6 & 0xff;
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR3:
+ val = para->tpr6 >> 8 & 0xff;
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR4:
+ val = para->tpr6 >> 24 & 0xff;
+ break;
+ case SUNXI_DRAM_TYPE_DDR4:
+ default:
+ panic("This DRAM setup is currently not supported.\n");
+ };
+
writel(val, SUNXI_DRAM_PHY0_BASE + 0x3dc);
writel(val, SUNXI_DRAM_PHY0_BASE + 0x45c);
mctl_phy_configure_odt(para);
- if (para->type == SUNXI_DRAM_TYPE_DDR3)
+ switch (para->type) {
+ case SUNXI_DRAM_TYPE_DDR3:
val = 0x0a;
- else if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR3:
val = 0x0b;
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR4:
+ val = 0x0d;
+ break;
+ case SUNXI_DRAM_TYPE_DDR4:
+ default:
+ panic("This DRAM setup is currently not supported.\n");
+ };
clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 0x7, val);
if (para->clk <= 672)
@@ -977,8 +1025,8 @@
mr0 = 0x1f14;
mr2 = 0x20;
}
-
- if (para->type == SUNXI_DRAM_TYPE_DDR3) {
+ switch (para->type) {
+ case SUNXI_DRAM_TYPE_DDR3:
writel(mr0, &mctl_ctl->mrctrl1);
writel(0x80000030, &mctl_ctl->mrctrl0);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
@@ -994,7 +1042,8 @@
writel(0, &mctl_ctl->mrctrl1);
writel(0x80003030, &mctl_ctl->mrctrl0);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
- } else if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR3:
writel(mr0, &mctl_ctl->mrctrl1);
writel(0x800000f0, &mctl_ctl->mrctrl0);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
@@ -1010,7 +1059,48 @@
writel(0x301, &mctl_ctl->mrctrl1);
writel(0x800000f0, &mctl_ctl->mrctrl0);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
- }
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR4:
+ writel(0x0, &mctl_ctl->mrctrl1);
+ writel(0x80000030, &mctl_ctl->mrctrl0);
+ mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+
+ writel(0x134, &mctl_ctl->mrctrl1);
+ writel(0x80000030, &mctl_ctl->mrctrl0);
+ mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+
+ writel(0x21b, &mctl_ctl->mrctrl1);
+ writel(0x80000030, &mctl_ctl->mrctrl0);
+ mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+
+ writel(0x333, &mctl_ctl->mrctrl1);
+ writel(0x80000030, &mctl_ctl->mrctrl0);
+ mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+
+ writel(0x403, &mctl_ctl->mrctrl1);
+ writel(0x80000030, &mctl_ctl->mrctrl0);
+ mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+
+ writel(0xb04, &mctl_ctl->mrctrl1);
+ writel(0x80000030, &mctl_ctl->mrctrl0);
+ mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+
+ writel(0xc72, &mctl_ctl->mrctrl1);
+ writel(0x80000030, &mctl_ctl->mrctrl0);
+ mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+
+ writel(0xe09, &mctl_ctl->mrctrl1);
+ writel(0x80000030, &mctl_ctl->mrctrl0);
+ mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+
+ writel(0x1624, &mctl_ctl->mrctrl1);
+ writel(0x80000030, &mctl_ctl->mrctrl0);
+ mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+ break;
+ case SUNXI_DRAM_TYPE_DDR4:
+ default:
+ panic("This DRAM setup is currently not supported.\n");
+ };
writel(0, SUNXI_DRAM_PHY0_BASE + 0x54);
@@ -1040,7 +1130,7 @@
if (para->tpr10 & TPR10_READ_TRAINING) {
for (i = 0; i < 5; i++)
- if (mctl_phy_read_training(config))
+ if (mctl_phy_read_training(para, config))
break;
if (i == 5) {
debug("read training failed!\n");
@@ -1079,17 +1169,29 @@
setbits_le32(&mctl_com->unk_0x008, 0xff00);
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR4)
+ writel(1, SUNXI_DRAM_COM_BASE + 0x50);
clrsetbits_le32(&mctl_ctl->sched[0], 0xff00, 0x3000);
writel(0, &mctl_ctl->hwlpctl);
setbits_le32(&mctl_com->unk_0x008, 0xff00);
- reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(config->ranks);
- if (para->type == SUNXI_DRAM_TYPE_DDR3)
- reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE;
- else if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
- reg_val |= MSTR_DEVICETYPE_LPDDR3;
+ reg_val = MSTR_ACTIVE_RANKS(config->ranks);
+ switch (para->type) {
+ case SUNXI_DRAM_TYPE_DDR3:
+ reg_val |= MSTR_BURST_LENGTH(8) | MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE;
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR3:
+ reg_val |= MSTR_BURST_LENGTH(8) | MSTR_DEVICETYPE_LPDDR3;
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR4:
+ reg_val |= MSTR_BURST_LENGTH(16) | MSTR_DEVICETYPE_LPDDR4;
+ break;
+ case SUNXI_DRAM_TYPE_DDR4:
+ default:
+ panic("This DRAM setup is currently not supported.\n");
+ };
if (config->bus_full_width)
reg_val |= MSTR_BUSWIDTH_FULL;
else
@@ -1101,10 +1203,20 @@
else
writel(0x0201, &mctl_ctl->odtmap);
- if (para->type == SUNXI_DRAM_TYPE_DDR3)
+ switch (para->type) {
+ case SUNXI_DRAM_TYPE_DDR3:
reg_val = 0x06000400;
- else if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR3:
reg_val = 0x09020400;
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR4:
+ reg_val = 0x04000400;
+ break;
+ case SUNXI_DRAM_TYPE_DDR4:
+ default:
+ panic("This DRAM setup is currently not supported.\n");
+ };
writel(reg_val, &mctl_ctl->odtcfg);
writel(reg_val, &mctl_ctl->unk_0x2240);
writel(reg_val, &mctl_ctl->unk_0x3240);
@@ -1124,6 +1236,9 @@
setbits_le32(&mctl_ctl->unk_0x3180, BIT(31) | BIT(30));
setbits_le32(&mctl_ctl->unk_0x4180, BIT(31) | BIT(30));
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR4)
+ setbits_le32(&mctl_ctl->dbictl, 0x1);
+
setbits_le32(&mctl_ctl->rfshctl3, BIT(0));
clrbits_le32(&mctl_ctl->dfimisc, BIT(0));
@@ -1246,6 +1361,8 @@
.type = SUNXI_DRAM_TYPE_DDR3,
#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR3)
.type = SUNXI_DRAM_TYPE_LPDDR3,
+#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR4)
+ .type = SUNXI_DRAM_TYPE_LPDDR4,
#endif
.dx_odt = CONFIG_DRAM_SUN50I_H616_DX_ODT,
.dx_dri = CONFIG_DRAM_SUN50I_H616_DX_DRI,
@@ -1253,6 +1370,7 @@
.odt_en = CONFIG_DRAM_SUN50I_H616_ODT_EN,
.tpr0 = CONFIG_DRAM_SUN50I_H616_TPR0,
.tpr2 = CONFIG_DRAM_SUN50I_H616_TPR2,
+ .tpr6 = CONFIG_DRAM_SUN50I_H616_TPR6,
.tpr10 = CONFIG_DRAM_SUN50I_H616_TPR10,
.tpr11 = CONFIG_DRAM_SUN50I_H616_TPR11,
.tpr12 = CONFIG_DRAM_SUN50I_H616_TPR12,
diff --git a/arch/arm/mach-sunxi/dram_sun8i_a23.c b/arch/arm/mach-sunxi/dram_sun8i_a23.c
index 3ed97b5..056cb03 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_a23.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_a23.c
@@ -14,7 +14,7 @@
*
* The register-layout of the sunxi_mctl_phy_reg-s looks a lot like the one
* found in the TI Keystone2 documentation:
- * http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf
+ * https://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf
* "Table4-2 DDR3 PHY Registers"
* This may be used as a (possible) reference for future work / cleanups.
*/
diff --git a/arch/arm/mach-sunxi/dram_suniv.c b/arch/arm/mach-sunxi/dram_suniv.c
index 3aa3ce7..9e583e1 100644
--- a/arch/arm/mach-sunxi/dram_suniv.c
+++ b/arch/arm/mach-sunxi/dram_suniv.c
@@ -13,10 +13,10 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/dram.h>
-#include <asm/arch/gpio.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <hang.h>
+#include <sunxi_gpio.h>
#define SDR_T_CAS (0x2)
#define SDR_T_RAS (0x8)
diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile b/arch/arm/mach-sunxi/dram_timings/Makefile
index 8bfd994..5f20341 100644
--- a/arch/arm/mach-sunxi/dram_timings/Makefile
+++ b/arch/arm/mach-sunxi/dram_timings/Makefile
@@ -5,3 +5,4 @@
obj-$(CONFIG_SUNXI_DRAM_H6_DDR3_1333) += h6_ddr3_1333.o
obj-$(CONFIG_SUNXI_DRAM_H616_DDR3_1333) += h616_ddr3_1333.o
obj-$(CONFIG_SUNXI_DRAM_H616_LPDDR3) += h616_lpddr3.o
+obj-$(CONFIG_SUNXI_DRAM_H616_LPDDR4) += h616_lpddr4_2133.o
diff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c
new file mode 100644
index 0000000..c11cb86
--- /dev/null
+++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c
@@ -0,0 +1,95 @@
+/*
+ * sun50i H616 LPDDR4-2133 timings, as programmed by Allwinner's boot0
+ * for orangepi zero3 with the H618 and LPDDR4 memory.
+ *
+ * (C) Copyright 2023 Mikhail Kalashnikov <iuncuim@gmail.com>
+ * Based on H6 DDR3 timings:
+ * (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/cpu.h>
+
+void mctl_set_timing_params(const struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ u8 tccd = 4;
+ u8 tfaw = ns_to_t(40);
+ u8 trrd = max(ns_to_t(10), 2);
+ u8 trcd = max(ns_to_t(18), 2);
+ u8 trc = ns_to_t(65);
+ u8 txp = max(ns_to_t(8), 2);
+ u8 trtp = max(ns_to_t(8), 4);
+ u8 trp = ns_to_t(21);
+ u8 tras = ns_to_t(42);
+ u16 trefi = ns_to_t(3904) / 32;
+ u16 trfc = ns_to_t(280);
+ u16 txsr = ns_to_t(190);
+
+ u8 tmrw = max(ns_to_t(14), 5);
+ u8 tmrd = tmrw;
+ u8 tmod = 12;
+ u8 tcke = max(ns_to_t(15), 2);
+ u8 tcksrx = max(ns_to_t(2), 2);
+ u8 tcksre = max(ns_to_t(5), 2);
+ u8 tckesr = tcke;
+ u8 trasmax = (trefi * 9) / 32;
+ u8 txs = 4;
+ u8 txsdll = 16;
+ u8 txsabort = 4;
+ u8 txsfast = 4;
+ u8 tcl = 10;
+ u8 tcwl = 5;
+ u8 t_rdata_en = 17;
+ u8 tphy_wrlat = 5;
+
+ u8 twtp = 24;
+ u8 twr2rd = max(trrd, (u8)4) + 14;
+ u8 trd2wr = (ns_to_t(4) + 17) - ns_to_t(1);
+
+ /* set DRAM timing */
+ writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras,
+ &mctl_ctl->dramtmg[0]);
+ writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]);
+ writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd,
+ &mctl_ctl->dramtmg[2]);
+ writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]);
+ writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp,
+ &mctl_ctl->dramtmg[4]);
+ writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke,
+ &mctl_ctl->dramtmg[5]);
+ /* Value suggested by ZynqMP manual and used by libdram */
+ writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]);
+ writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs,
+ &mctl_ctl->dramtmg[8]);
+ writel(0x00020208, &mctl_ctl->dramtmg[9]);
+ writel(0xE0C05, &mctl_ctl->dramtmg[10]);
+ writel(0x440C021C, &mctl_ctl->dramtmg[11]);
+ writel(8, &mctl_ctl->dramtmg[12]);
+ writel(0xA100002, &mctl_ctl->dramtmg[13]);
+ writel(txsr, &mctl_ctl->dramtmg[14]);
+
+ clrsetbits_le32(&mctl_ctl->init[0], 0xC0000FFF, 0x3f0);
+ writel(0x01f20000, &mctl_ctl->init[1]);
+ writel(0x00000d05, &mctl_ctl->init[2]);
+ writel(0, &mctl_ctl->dfimisc);
+ writel(0x0034001b, &mctl_ctl->init[3]);
+ writel(0x00330000, &mctl_ctl->init[4]);
+ writel(0x00040072, &mctl_ctl->init[6]);
+ writel(0x00240009, &mctl_ctl->init[7]);
+
+ clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660);
+
+ /* Configure DFI timing */
+ writel(tphy_wrlat | 0x2000000 | (t_rdata_en << 16) | 0x808000,
+ &mctl_ctl->dfitmg0);
+ writel(0x100202, &mctl_ctl->dfitmg1);
+
+ /* set refresh timing */
+ writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg);
+}
diff --git a/arch/arm/mach-sunxi/gtbus_sun9i.c b/arch/arm/mach-sunxi/gtbus_sun9i.c
index cf011c4..5624621 100644
--- a/arch/arm/mach-sunxi/gtbus_sun9i.c
+++ b/arch/arm/mach-sunxi/gtbus_sun9i.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <asm/io.h>
+#include <asm/arch/cpu.h>
#include <asm/arch/gtbus_sun9i.h>
#include <asm/arch/sys_proto.h>
diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c
deleted file mode 100644
index c95fcee..0000000
--- a/arch/arm/mach-sunxi/pinmux.c
+++ /dev/null
@@ -1,78 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007-2011
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/gpio.h>
-
-void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
-{
- u32 index = GPIO_CFG_INDEX(bank_offset);
- u32 offset = GPIO_CFG_OFFSET(bank_offset);
-
- clrsetbits_le32(&pio->cfg[index], 0xf << offset, val << offset);
-}
-
-void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
-{
- u32 bank = GPIO_BANK(pin);
- struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
-
- sunxi_gpio_set_cfgbank(pio, pin, val);
-}
-
-int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
-{
- u32 index = GPIO_CFG_INDEX(bank_offset);
- u32 offset = GPIO_CFG_OFFSET(bank_offset);
- u32 cfg;
-
- cfg = readl(&pio->cfg[index]);
- cfg >>= offset;
-
- return cfg & 0xf;
-}
-
-int sunxi_gpio_get_cfgpin(u32 pin)
-{
- u32 bank = GPIO_BANK(pin);
- struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
-
- return sunxi_gpio_get_cfgbank(pio, pin);
-}
-
-void sunxi_gpio_set_drv(u32 pin, u32 val)
-{
- u32 bank = GPIO_BANK(pin);
- struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
-
- sunxi_gpio_set_drv_bank(pio, pin, val);
-}
-
-void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val)
-{
- u32 index = GPIO_DRV_INDEX(bank_offset);
- u32 offset = GPIO_DRV_OFFSET(bank_offset);
-
- clrsetbits_le32(&pio->drv[index], 0x3 << offset, val << offset);
-}
-
-void sunxi_gpio_set_pull(u32 pin, u32 val)
-{
- u32 bank = GPIO_BANK(pin);
- struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
-
- sunxi_gpio_set_pull_bank(pio, pin, val);
-}
-
-void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val)
-{
- u32 index = GPIO_PULL_INDEX(bank_offset);
- u32 offset = GPIO_PULL_OFFSET(bank_offset);
-
- clrsetbits_le32(&pio->pull[index], 0x3 << offset, val << offset);
-}
diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c
index c090840..8e7625f 100644
--- a/arch/arm/mach-sunxi/pmic_bus.c
+++ b/arch/arm/mach-sunxi/pmic_bus.c
@@ -22,6 +22,7 @@
#define AXP209_I2C_ADDR 0x34
#define AXP305_I2C_ADDR 0x36
+#define AXP313_I2C_ADDR 0x36
#define AXP221_CHIP_ADDR 0x68
@@ -34,6 +35,8 @@
return AXP152_I2C_ADDR;
if (IS_ENABLED(CONFIG_AXP305_POWER))
return AXP305_I2C_ADDR;
+ if (IS_ENABLED(CONFIG_AXP313_POWER))
+ return AXP313_I2C_ADDR;
/* Other AXP2xx and AXP8xx variants */
return AXP209_I2C_ADDR;
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index 81159cf..c2410dd 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -13,6 +13,7 @@
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
+#include <sunxi_gpio.h>
#ifdef CONFIG_SPL_OS_BOOT
#error CONFIG_SPL_OS_BOOT is not supported yet
diff --git a/arch/arm/mach-sunxi/timer.c b/arch/arm/mach-sunxi/timer.c
index fc9d419..9a6f6c0 100644
--- a/arch/arm/mach-sunxi/timer.c
+++ b/arch/arm/mach-sunxi/timer.c
@@ -10,6 +10,7 @@
#include <time.h>
#include <asm/global_data.h>
#include <asm/io.h>
+#include <asm/arch/cpu.h>
#include <asm/arch/timer.h>
#include <linux/delay.h>
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 464bd07..f273778 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -18,7 +18,6 @@
config TEGRA_CRYPTO
bool "Tegra AES128 crypto module"
select AES
- default n
config TEGRA_GP_PADCTRL
bool
@@ -61,6 +60,9 @@
select MISC
select OF_CONTROL
select SPI
+ select SYSRESET
+ select SPL_SYSRESET if SPL
+ select SYSRESET_TEGRA
imply CMD_DM
imply CRC32_VERIFY
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 981768b..cd40587 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -26,6 +26,10 @@
#include <asm/arch-tegra/gpu.h>
#include <asm/arch-tegra/usb.h>
#include <asm/arch-tegra/xusb-padctl.h>
+#ifndef CONFIG_TEGRA186
+#include <asm/arch-tegra/fuse.h>
+#include <asm/arch/gp_padctrl.h>
+#endif
#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
#include <asm/arch/clock.h>
#endif
@@ -256,6 +260,37 @@
}
#endif /* EARLY_INIT */
+#ifndef CONFIG_TEGRA186
+static void nvidia_board_late_init_generic(void)
+{
+ char serialno_str[17];
+
+ /* Set chip id as serialno */
+ sprintf(serialno_str, "%016llx", tegra_chip_uid());
+ env_set("serial#", serialno_str);
+
+ switch (tegra_get_chip()) {
+ case CHIPID_TEGRA20:
+ env_set("platform", "tegra20");
+ break;
+ case CHIPID_TEGRA30:
+ env_set("platform", "tegra30");
+ break;
+ case CHIPID_TEGRA114:
+ env_set("platform", "tegra114");
+ break;
+ case CHIPID_TEGRA124:
+ env_set("platform", "tegra124");
+ break;
+ case CHIPID_TEGRA210:
+ env_set("platform", "tegra210");
+ break;
+ default:
+ return;
+ }
+}
+#endif
+
int board_late_init(void)
{
#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
@@ -268,6 +303,14 @@
#endif
start_cpu_fan();
cboot_late_init();
+
+ /*
+ * Perform generic env setup in case
+ * vendor does not provide it.
+ */
+#ifndef CONFIG_TEGRA186
+ nvidia_board_late_init_generic();
+#endif
nvidia_board_late_init();
return 0;
diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c
index 55eb819..8f5bb2f 100644
--- a/arch/arm/mach-tegra/cboot.c
+++ b/arch/arm/mach-tegra/cboot.c
@@ -15,6 +15,7 @@
#include <stdlib.h>
#include <string.h>
#include <asm/global_data.h>
+#include <linux/printk.h>
#include <linux/ctype.h>
#include <linux/sizes.h>
diff --git a/arch/arm/mach-tegra/ivc.c b/arch/arm/mach-tegra/ivc.c
index b69a458..66c1276 100644
--- a/arch/arm/mach-tegra/ivc.c
+++ b/arch/arm/mach-tegra/ivc.c
@@ -8,6 +8,7 @@
#include <asm/io.h>
#include <asm/arch-tegra/ivc.h>
#include <linux/bug.h>
+#include <linux/printk.h>
#define TEGRA_IVC_ALIGN 64
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index 8d617be..c4f5106 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -84,12 +84,3 @@
writel(value, NV_PA_PMC_BASE + offset);
}
-
-void reset_cpu(void)
-{
- u32 value;
-
- value = tegra_pmc_readl(PMC_CNTRL);
- value |= PMC_CNTRL_MAIN_RST;
- tegra_pmc_writel(value, PMC_CNTRL);
-}
diff --git a/arch/arm/mach-tegra/tegra114/cpu.c b/arch/arm/mach-tegra/tegra114/cpu.c
index 62c1053..7d8f080 100644
--- a/arch/arm/mach-tegra/tegra114/cpu.c
+++ b/arch/arm/mach-tegra/tegra114/cpu.c
@@ -13,9 +13,13 @@
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/tegra_i2c.h>
#include <linux/delay.h>
#include "../cpu.h"
+/* In case this function is not defined */
+__weak void pmic_enable_cpu_vdd(void) {}
+
/* Tegra114-specific CPU init code */
static void enable_cpu_power_rail(void)
{
@@ -254,6 +258,7 @@
/* Enable VDD_CPU */
enable_cpu_power_rail();
+ pmic_enable_cpu_vdd();
/* Get the CPU(s) running */
enable_cpu_clocks();
diff --git a/arch/arm/mach-tegra/tegra124/xusb-padctl.c b/arch/arm/mach-tegra/tegra124/xusb-padctl.c
index d3c7719c..69736aa 100644
--- a/arch/arm/mach-tegra/tegra124/xusb-padctl.c
+++ b/arch/arm/mach-tegra/tegra124/xusb-padctl.c
@@ -11,6 +11,7 @@
#include <dm/of_access.h>
#include <dm/ofnode.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <asm/global_data.h>
#include "../xusb-padctl-common.h"
diff --git a/arch/arm/mach-tegra/tegra20/bct.c b/arch/arm/mach-tegra/tegra20/bct.c
index 5eb4899..b2c44f3 100644
--- a/arch/arm/mach-tegra/tegra20/bct.c
+++ b/arch/arm/mach-tegra/tegra20/bct.c
@@ -11,6 +11,9 @@
#include "bct.h"
#include "uboot_aes.h"
+/* Device with "sbk burned: false" will expose zero key */
+const u8 nosbk[AES128_KEY_LENGTH] = { 0 };
+
/*
* @param bct boot config table start in RAM
* @param ect bootloader start in RAM
@@ -23,22 +26,27 @@
u8 ebt_hash[AES128_KEY_LENGTH] = { 0 };
u8 sbk[AES128_KEY_LENGTH] = { 0 };
u8 *bct_hash = bct;
+ bool encrypted;
int ret;
bct += BCT_HASH;
+ ebt_size = roundup(ebt_size, EBT_ALIGNMENT);
+
memcpy(sbk, (u8 *)(bct + BCT_LENGTH),
NVBOOT_CMAC_AES_HASH_LENGTH * 4);
- ret = decrypt_data_block(bct, BCT_LENGTH, sbk);
- if (ret)
- return 1;
+ encrypted = memcmp(&sbk, &nosbk, AES128_KEY_LENGTH);
- ebt_size = roundup(ebt_size, EBT_ALIGNMENT);
+ if (encrypted) {
+ ret = decrypt_data_block(bct, BCT_LENGTH, sbk);
+ if (ret)
+ return 1;
- ret = encrypt_data_block(ebt, ebt_size, sbk);
- if (ret)
- return 1;
+ ret = encrypt_data_block(ebt, ebt_size, sbk);
+ if (ret)
+ return 1;
+ }
ret = sign_enc_data_block(ebt, ebt_size, ebt_hash, sbk);
if (ret)
@@ -52,9 +60,11 @@
bct_tbl->bootloader[0].load_addr = CONFIG_SPL_TEXT_BASE;
bct_tbl->bootloader[0].length = ebt_size;
- ret = encrypt_data_block(bct, BCT_LENGTH, sbk);
- if (ret)
- return 1;
+ if (encrypted) {
+ ret = encrypt_data_block(bct, BCT_LENGTH, sbk);
+ if (ret)
+ return 1;
+ }
ret = sign_enc_data_block(bct, BCT_LENGTH, bct_hash, sbk);
if (ret)
diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c
index 067a9f1..abd6e39 100644
--- a/arch/arm/mach-tegra/tegra20/clock.c
+++ b/arch/arm/mach-tegra/tegra20/clock.c
@@ -19,6 +19,7 @@
#include <div64.h>
#include <fdtdec.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <dt-bindings/clock/tegra20-car.h>
diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
index c414dfd..30d0395 100644
--- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c
+++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
@@ -12,6 +12,7 @@
#include <dm/of_access.h>
#include <dm/ofnode.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include "../xusb-padctl-common.h"
diff --git a/arch/arm/mach-tegra/tegra30/bct.c b/arch/arm/mach-tegra/tegra30/bct.c
index c56958d..cff1a3e 100644
--- a/arch/arm/mach-tegra/tegra30/bct.c
+++ b/arch/arm/mach-tegra/tegra30/bct.c
@@ -11,6 +11,9 @@
#include "bct.h"
#include "uboot_aes.h"
+/* Device with "sbk burned: false" will expose zero key */
+const u8 nosbk[AES128_KEY_LENGTH] = { 0 };
+
/*
* @param bct boot config table start in RAM
* @param ect bootloader start in RAM
@@ -23,22 +26,27 @@
u8 ebt_hash[AES128_KEY_LENGTH] = { 0 };
u8 sbk[AES128_KEY_LENGTH] = { 0 };
u8 *bct_hash = bct;
+ bool encrypted;
int ret;
bct += BCT_HASH;
+ ebt_size = roundup(ebt_size, EBT_ALIGNMENT);
+
memcpy(sbk, (u8 *)(bct + BCT_LENGTH),
NVBOOT_CMAC_AES_HASH_LENGTH * 4);
- ret = decrypt_data_block(bct, BCT_LENGTH, sbk);
- if (ret)
- return 1;
+ encrypted = memcmp(&sbk, &nosbk, AES128_KEY_LENGTH);
- ebt_size = roundup(ebt_size, EBT_ALIGNMENT);
+ if (encrypted) {
+ ret = decrypt_data_block(bct, BCT_LENGTH, sbk);
+ if (ret)
+ return 1;
- ret = encrypt_data_block(ebt, ebt_size, sbk);
- if (ret)
- return 1;
+ ret = encrypt_data_block(ebt, ebt_size, sbk);
+ if (ret)
+ return 1;
+ }
ret = sign_enc_data_block(ebt, ebt_size, ebt_hash, sbk);
if (ret)
@@ -52,9 +60,11 @@
bct_tbl->bootloader[0].load_addr = CONFIG_SPL_TEXT_BASE;
bct_tbl->bootloader[0].length = ebt_size;
- ret = encrypt_data_block(bct, BCT_LENGTH, sbk);
- if (ret)
- return 1;
+ if (encrypted) {
+ ret = encrypt_data_block(bct, BCT_LENGTH, sbk);
+ if (ret)
+ return 1;
+ }
ret = sign_enc_data_block(bct, BCT_LENGTH, bct_hash, sbk);
if (ret)
diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c
index 1dc9d09..698c7ab 100644
--- a/arch/arm/mach-tegra/tegra30/clock.c
+++ b/arch/arm/mach-tegra/tegra30/clock.c
@@ -18,6 +18,7 @@
#include <div64.h>
#include <fdtdec.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <dt-bindings/clock/tegra30-car.h>
diff --git a/arch/arm/mach-tegra/xusb-padctl-common.c b/arch/arm/mach-tegra/xusb-padctl-common.c
index 388ec49..28fdebe 100644
--- a/arch/arm/mach-tegra/xusb-padctl-common.c
+++ b/arch/arm/mach-tegra/xusb-padctl-common.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <errno.h>
#include <log.h>
+#include <linux/printk.h>
#include "xusb-padctl-common.h"
diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c b/arch/arm/mach-uniphier/boot-device/boot-device.c
index 98ff34c..1e6bc84 100644
--- a/arch/arm/mach-uniphier/boot-device/boot-device.c
+++ b/arch/arm/mach-uniphier/boot-device/boot-device.c
@@ -12,6 +12,7 @@
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/log2.h>
+#include <linux/printk.h>
#include "../init.h"
#include "../sg-regs.h"
diff --git a/arch/arm/mach-uniphier/clk/dpll-ld4.c b/arch/arm/mach-uniphier/clk/dpll-ld4.c
index 3ccaf02..f24a0eb 100644
--- a/arch/arm/mach-uniphier/clk/dpll-ld4.c
+++ b/arch/arm/mach-uniphier/clk/dpll-ld4.c
@@ -7,6 +7,7 @@
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/io.h>
+#include <linux/printk.h>
#include "../init.h"
#include "../sc-regs.h"
diff --git a/arch/arm/mach-uniphier/clk/dpll-pro4.c b/arch/arm/mach-uniphier/clk/dpll-pro4.c
index 44006ae..204aee1 100644
--- a/arch/arm/mach-uniphier/clk/dpll-pro4.c
+++ b/arch/arm/mach-uniphier/clk/dpll-pro4.c
@@ -7,6 +7,7 @@
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/io.h>
+#include <linux/printk.h>
#include "../init.h"
#include "../sc-regs.h"
diff --git a/arch/arm/mach-uniphier/dram/umc-ld4.c b/arch/arm/mach-uniphier/dram/umc-ld4.c
index 96acca2..1eb15b6 100644
--- a/arch/arm/mach-uniphier/dram/umc-ld4.c
+++ b/arch/arm/mach-uniphier/dram/umc-ld4.c
@@ -7,6 +7,7 @@
#include <linux/errno.h>
#include <linux/io.h>
+#include <linux/printk.h>
#include <linux/sizes.h>
#include <asm/processor.h>
diff --git a/arch/arm/mach-uniphier/dram/umc-pro4.c b/arch/arm/mach-uniphier/dram/umc-pro4.c
index cde39b4..0114df7 100644
--- a/arch/arm/mach-uniphier/dram/umc-pro4.c
+++ b/arch/arm/mach-uniphier/dram/umc-pro4.c
@@ -7,6 +7,7 @@
#include <linux/errno.h>
#include <linux/io.h>
+#include <linux/printk.h>
#include <linux/sizes.h>
#include <asm/processor.h>
diff --git a/arch/arm/mach-uniphier/dram/umc-sld8.c b/arch/arm/mach-uniphier/dram/umc-sld8.c
index a115869..583a1ba 100644
--- a/arch/arm/mach-uniphier/dram/umc-sld8.c
+++ b/arch/arm/mach-uniphier/dram/umc-sld8.c
@@ -7,6 +7,7 @@
#include <linux/errno.h>
#include <linux/io.h>
+#include <linux/printk.h>
#include <linux/sizes.h>
#include <asm/processor.h>
diff --git a/arch/arm/mach-uniphier/memconf.c b/arch/arm/mach-uniphier/memconf.c
index 57192f0..ab0d187 100644
--- a/arch/arm/mach-uniphier/memconf.c
+++ b/arch/arm/mach-uniphier/memconf.c
@@ -7,6 +7,7 @@
#include <linux/errno.h>
#include <linux/io.h>
+#include <linux/printk.h>
#include <linux/sizes.h>
#include "sg-regs.h"
diff --git a/arch/arm/mach-uniphier/spl_board_init.c b/arch/arm/mach-uniphier/spl_board_init.c
index a93b8cd..0f2e350 100644
--- a/arch/arm/mach-uniphier/spl_board_init.c
+++ b/arch/arm/mach-uniphier/spl_board_init.c
@@ -7,6 +7,7 @@
#include <debug_uart.h>
#include <hang.h>
#include <spl.h>
+#include <linux/printk.h>
#include "init.h"
#include "micro-support-card.h"
diff --git a/arch/arm/mach-versal-net/include/mach/hardware.h b/arch/arm/mach-versal-net/include/mach/hardware.h
index 9bddb8b..767cdd3 100644
--- a/arch/arm/mach-versal-net/include/mach/hardware.h
+++ b/arch/arm/mach-versal-net/include/mach/hardware.h
@@ -66,6 +66,7 @@
#define EMMC_MODE 0x00000006
#define USB_MODE 0x00000007
#define OSPI_MODE 0x00000008
+#define SELECTMAP_MODE 0x0000000A
#define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */
#define JTAG_MODE 0x00000000
#define BOOT_MODE_USE_ALT 0x100
diff --git a/arch/arm/mach-versal/include/mach/hardware.h b/arch/arm/mach-versal/include/mach/hardware.h
index 000af97..9d1c2f0 100644
--- a/arch/arm/mach-versal/include/mach/hardware.h
+++ b/arch/arm/mach-versal/include/mach/hardware.h
@@ -82,6 +82,7 @@
#define EMMC_MODE 0x00000006
#define USB_MODE 0x00000007
#define OSPI_MODE 0x00000008
+#define SELECTMAP_MODE 0x0000000A
#define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */
#define JTAG_MODE 0x00000000
#define BOOT_MODE_USE_ALT 0x100
diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c
index 7bd3928..2487b48 100644
--- a/arch/arm/mach-versal/mp.c
+++ b/arch/arm/mach-versal/mp.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* (C) Copyright 2019 Xilinx, Inc.
- * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
*/
#include <common.h>
diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig
index fd6f077..7e7c87d 100644
--- a/arch/arm/mach-zynqmp/Kconfig
+++ b/arch/arm/mach-zynqmp/Kconfig
@@ -84,9 +84,6 @@
Leave this option empty if your PMU firmware has a hard-coded
configuration object or you are loading it by any other means.
-config ZYNQMP_USB
- bool "Configure ZynqMP USB"
-
config ZYNQMP_NO_DDR
bool "Disable DDR MMU mapping"
help
@@ -103,30 +100,30 @@
config SPL_ZYNQMP_DRAM_BANK1_BASE
depends on SPL_ZYNQMP_DRAM_ECC_INIT
hex "DRAM Bank1 address"
- default 0x00000000
- help
- Start address of DRAM ECC bank1
+ default 0x00000000
+ help
+ Start address of DRAM ECC bank1
config SPL_ZYNQMP_DRAM_BANK1_LEN
depends on SPL_ZYNQMP_DRAM_ECC_INIT
hex "DRAM Bank1 size"
- default 0x80000000
- help
- Size in bytes of the DRAM ECC bank1
+ default 0x80000000
+ help
+ Size in bytes of the DRAM ECC bank1
config SPL_ZYNQMP_DRAM_BANK2_BASE
depends on SPL_ZYNQMP_DRAM_ECC_INIT
hex "DRAM Bank2 address"
- default 0x800000000
- help
- Start address of DRAM ECC bank2
+ default 0x800000000
+ help
+ Start address of DRAM ECC bank2
config SPL_ZYNQMP_DRAM_BANK2_LEN
depends on SPL_ZYNQMP_DRAM_ECC_INIT
hex "DRAM Bank2 size"
- default 0x0
- help
- Size in bytes of the DRAM ECC bank2. A null size takes no action.
+ default 0x0
+ help
+ Size in bytes of the DRAM ECC bank2. A null size takes no action.
config SYS_MALLOC_F_LEN
default 0x600
diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile
index 3f25554..8f897a3 100644
--- a/arch/arm/mach-zynqmp/Makefile
+++ b/arch/arm/mach-zynqmp/Makefile
@@ -3,8 +3,7 @@
# (C) Copyright 2014 - 2015 Xilinx, Inc.
# Michal Simek <michal.simek@amd.com>
-obj-y += clk.o
-obj-y += cpu.o
+obj-y += aes.o clk.o cpu.o
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o psu_spl_init.o
obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o
diff --git a/arch/arm/mach-zynqmp/aes.c b/arch/arm/mach-zynqmp/aes.c
new file mode 100644
index 0000000..8a2b7fd
--- /dev/null
+++ b/arch/arm/mach-zynqmp/aes.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2018 Xilinx, Inc.
+ * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ *
+ * Copyright (C) 2023 Weidmueller Interface GmbH & Co. KG <oss@weidmueller.com>
+ * Christian Taedcke <christian.taedcke@weidmueller.com>
+ */
+
+#include <common.h>
+#include <mach/zynqmp_aes.h>
+
+#include <asm/arch/sys_proto.h>
+#include <cpu_func.h>
+#include <memalign.h>
+#include <zynqmp_firmware.h>
+
+int zynqmp_aes_operation(struct zynqmp_aes *aes)
+{
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ int ret;
+
+ if (zynqmp_firmware_version() <= PMUFW_V1_0)
+ return -ENOENT;
+
+ if (aes->srcaddr && aes->ivaddr && aes->dstaddr) {
+ flush_dcache_range(aes->srcaddr,
+ aes->srcaddr +
+ roundup(aes->len, ARCH_DMA_MINALIGN));
+ flush_dcache_range(aes->ivaddr,
+ aes->ivaddr +
+ roundup(IV_SIZE, ARCH_DMA_MINALIGN));
+ flush_dcache_range(aes->dstaddr,
+ aes->dstaddr +
+ roundup(aes->len, ARCH_DMA_MINALIGN));
+ }
+
+ if (aes->keysrc == 0) {
+ if (aes->keyaddr == 0)
+ return -EINVAL;
+
+ flush_dcache_range(aes->keyaddr,
+ aes->keyaddr +
+ roundup(KEY_PTR_LEN, ARCH_DMA_MINALIGN));
+ }
+
+ flush_dcache_range((ulong)aes, (ulong)(aes) +
+ roundup(sizeof(struct zynqmp_aes), ARCH_DMA_MINALIGN));
+
+ ret = xilinx_pm_request(PM_SECURE_AES, upper_32_bits((ulong)aes),
+ lower_32_bits((ulong)aes), 0, 0, ret_payload);
+ if (ret || ret_payload[1]) {
+ printf("Failed: AES op status:0x%x, errcode:0x%x\n",
+ ret, ret_payload[1]);
+ return -EIO;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h
index 634bf16..8cb6494 100644
--- a/arch/arm/mach-zynqmp/include/mach/hardware.h
+++ b/arch/arm/mach-zynqmp/include/mach/hardware.h
@@ -166,7 +166,7 @@
u32 jtag_dap_cfg;
u32 idcode;
u32 version;
- u32 reserved2[3055];
+ u32 reserved2[3054];
u32 pcap_prog;
};
diff --git a/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h b/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h
new file mode 100644
index 0000000..2a9cffb
--- /dev/null
+++ b/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 Weidmueller Interface GmbH & Co. KG <oss@weidmueller.com>
+ * Christian Taedcke <christian.taedcke@weidmueller.com>
+ *
+ * Declaration of AES operation functionality for ZynqMP.
+ */
+
+#ifndef ZYNQMP_AES_H
+#define ZYNQMP_AES_H
+
+struct zynqmp_aes {
+ u64 srcaddr;
+ u64 ivaddr;
+ u64 keyaddr;
+ u64 dstaddr;
+ u64 len;
+ u64 op;
+ u64 keysrc;
+};
+
+/**
+ * zynqmp_aes_operation() - Performs an aes operation using the pmu firmware
+ *
+ * @aes: The aes operation buffer that must have been allocated using
+ * ALLOC_CACHE_ALIGN_BUFFER(struct zynqmp_aes, aes, 1)
+ *
+ * Return: 0 in case of success, in case of an error any other value
+ */
+int zynqmp_aes_operation(struct zynqmp_aes *aes);
+
+#endif /* ZYNQMP_AES_H */
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 1911563..b288c65 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -4,8 +4,8 @@
config SYS_ARCH
default "m68k"
-config NEEDS_MANUAL_RELOC
- def_bool y
+config STATIC_RELA
+ default y
# processor family
config MCF520x
@@ -200,7 +200,6 @@
config M68K_QEMU
bool "Build with workarounds for incomplete QEMU emulation"
- default n
help
QEMU 8.x currently does not implement RAMBAR accesses and
DMA timers. Enable this option for U-Boot CI purposes only
diff --git a/arch/m68k/config.mk b/arch/m68k/config.mk
index 3ccbe49..643b7d1 100644
--- a/arch/m68k/config.mk
+++ b/arch/m68k/config.mk
@@ -3,8 +3,8 @@
# (C) Copyright 2000-2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-PLATFORM_CPPFLAGS += -D__M68K__
-KBUILD_LDFLAGS += -n
+PLATFORM_CPPFLAGS += -D__M68K__ -fPIC
+KBUILD_LDFLAGS += -n -pie
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
-LDFLAGS_FINAL += --gc-sections
+LDFLAGS_FINAL += --gc-sections -pie
diff --git a/arch/m68k/cpu/mcf523x/cpu.c b/arch/m68k/cpu/mcf523x/cpu.c
index bef6776..c843a38 100644
--- a/arch/m68k/cpu/mcf523x/cpu.c
+++ b/arch/m68k/cpu/mcf523x/cpu.c
@@ -8,7 +8,6 @@
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
-#include <common.h>
#include <init.h>
#include <net.h>
#include <vsprintf.h>
diff --git a/arch/m68k/cpu/mcf523x/cpu_init.c b/arch/m68k/cpu/mcf523x/cpu_init.c
index 10be738..a05cbdc 100644
--- a/arch/m68k/cpu/mcf523x/cpu_init.c
+++ b/arch/m68k/cpu/mcf523x/cpu_init.c
@@ -8,7 +8,6 @@
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
-#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <watchdog.h>
diff --git a/arch/m68k/cpu/mcf523x/interrupts.c b/arch/m68k/cpu/mcf523x/interrupts.c
index 09c7f9e..46c9207 100644
--- a/arch/m68k/cpu/mcf523x/interrupts.c
+++ b/arch/m68k/cpu/mcf523x/interrupts.c
@@ -6,7 +6,6 @@
*/
/* CPU specific interrupt routine */
-#include <common.h>
#include <irq_func.h>
#include <asm/immap.h>
#include <asm/io.h>
diff --git a/arch/m68k/cpu/mcf523x/speed.c b/arch/m68k/cpu/mcf523x/speed.c
index 6b08a12..2eb43cc 100644
--- a/arch/m68k/cpu/mcf523x/speed.c
+++ b/arch/m68k/cpu/mcf523x/speed.c
@@ -8,7 +8,6 @@
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
-#include <common.h>
#include <clock_legacy.h>
#include <asm/global_data.h>
#include <asm/processor.h>
diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S
index d2a21c3..c609e82 100644
--- a/arch/m68k/cpu/mcf523x/start.S
+++ b/arch/m68k/cpu/mcf523x/start.S
@@ -177,6 +177,39 @@
cmp.l %a1,%a2
bgt.s 1b
+#define R_68K_32 1
+#define R_68K_RELATIVE 22
+
+ move.l #(__rel_dyn_start), %a1
+ move.l #(__rel_dyn_end), %a2
+
+fixloop:
+ move.l (%a1)+, %d1 /* Elf32_Rela r_offset */
+ move.l (%a1)+, %d2 /* Elf32_Rela r_info */
+ move.l (%a1)+, %d3 /* Elf32_Rela r_addend */
+
+ andi.l #0xff, %d2
+ cmp.l #R_68K_32, %d2
+ beq.s fixup
+ cmp.l #R_68K_RELATIVE, %d2
+ beq.s fixup
+
+ bra fixnext
+
+fixup:
+ /* relative fix: store addend plus offset at dest location */
+ move.l %a0, %a3
+ add.l %d1, %a3
+ sub.l #CONFIG_SYS_MONITOR_BASE, %a3
+ move.l (%a3), %d4
+ add.l %a0, %d4
+ sub.l #CONFIG_SYS_MONITOR_BASE, %d4
+ move.l %d4, (%a3)
+
+fixnext:
+ cmp.l %a1, %a2
+ bge.s fixloop
+
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
@@ -191,10 +224,8 @@
/*
* Now clear BSS segment
*/
- move.l %a0, %a1
- add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
- move.l %a0, %d1
- add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
+ move.l #(_sbss), %a1
+ move.l #(_ebss), %d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
@@ -203,24 +234,10 @@
/*
* fix got table in RAM
*/
- move.l %a0, %a1
- add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
- move.l %a1,%a5 /* * fix got pointer register a5 */
-
- move.l %a0, %a2
- add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
-
-7:
- move.l (%a1),%d1
- sub.l #_start,%d1
- add.l %a0,%d1
- move.l %d1,(%a1)+
- cmp.l %a2, %a1
- bne 7b
+ move.l #(__got_start), %a5 /* fix got pointer register a5 */
/* calculate relative jump to board_init_r in ram */
- move.l %a0, %a1
- add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+ move.l #(board_init_r), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
diff --git a/arch/m68k/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c
index 5042a38..6bfde5e 100644
--- a/arch/m68k/cpu/mcf52x2/cpu.c
+++ b/arch/m68k/cpu/mcf52x2/cpu.c
@@ -13,7 +13,6 @@
* Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
*/
-#include <common.h>
#include <init.h>
#include <net.h>
#include <vsprintf.h>
diff --git a/arch/m68k/cpu/mcf52x2/cpu_init.c b/arch/m68k/cpu/mcf52x2/cpu_init.c
index 99eb61f..4506eb3 100644
--- a/arch/m68k/cpu/mcf52x2/cpu_init.c
+++ b/arch/m68k/cpu/mcf52x2/cpu_init.c
@@ -17,7 +17,7 @@
* Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
*/
-#include <common.h>
+#include <config.h>
#include <cpu_func.h>
#include <init.h>
#include <watchdog.h>
@@ -25,7 +25,6 @@
#include <asm/io.h>
#if defined(CONFIG_CMD_NET)
-#include <config.h>
#include <net.h>
#include <asm/fec.h>
#endif
diff --git a/arch/m68k/cpu/mcf52x2/interrupts.c b/arch/m68k/cpu/mcf52x2/interrupts.c
index c5ed060..264bdc7 100644
--- a/arch/m68k/cpu/mcf52x2/interrupts.c
+++ b/arch/m68k/cpu/mcf52x2/interrupts.c
@@ -7,7 +7,6 @@
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
-#include <common.h>
#include <irq_func.h>
#include <watchdog.h>
#include <asm/processor.h>
diff --git a/arch/m68k/cpu/mcf52x2/speed.c b/arch/m68k/cpu/mcf52x2/speed.c
index 6c76282..538e4c6 100644
--- a/arch/m68k/cpu/mcf52x2/speed.c
+++ b/arch/m68k/cpu/mcf52x2/speed.c
@@ -7,7 +7,6 @@
* Hayden Fraser (Hayden.Fraser@freescale.com)
*/
-#include <common.h>
#include <clock_legacy.h>
#include <asm/global_data.h>
#include <asm/processor.h>
diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S
index 51d2e23..3a27602 100644
--- a/arch/m68k/cpu/mcf52x2/start.S
+++ b/arch/m68k/cpu/mcf52x2/start.S
@@ -255,6 +255,39 @@
cmp.l %a1,%a2
bgt.s 1b
+#define R_68K_32 1
+#define R_68K_RELATIVE 22
+
+ move.l #(__rel_dyn_start), %a1
+ move.l #(__rel_dyn_end), %a2
+
+fixloop:
+ move.l (%a1)+, %d1 /* Elf32_Rela r_offset */
+ move.l (%a1)+, %d2 /* Elf32_Rela r_info */
+ move.l (%a1)+, %d3 /* Elf32_Rela r_addend */
+
+ andi.l #0xff, %d2
+ cmp.l #R_68K_32, %d2
+ beq.s fixup
+ cmp.l #R_68K_RELATIVE, %d2
+ beq.s fixup
+
+ bra fixnext
+
+fixup:
+ /* relative fix: store addend plus offset at dest location */
+ move.l %a0, %a3
+ add.l %d1, %a3
+ sub.l #CONFIG_SYS_MONITOR_BASE, %a3
+ move.l (%a3), %d4
+ add.l %a0, %d4
+ sub.l #CONFIG_SYS_MONITOR_BASE, %d4
+ move.l %d4, (%a3)
+
+fixnext:
+ cmp.l %a1, %a2
+ bge.s fixloop
+
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
@@ -269,10 +302,8 @@
/*
* Now clear BSS segment
*/
- move.l %a0, %a1
- add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
- move.l %a0, %d1
- add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
+ move.l #(_sbss), %a1
+ move.l #(_ebss), %d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
@@ -281,24 +312,10 @@
/*
* fix got table in RAM
*/
- move.l %a0, %a1
- add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
- move.l %a1,%a5 /* fix got pointer register a5 */
-
- move.l %a0, %a2
- add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
-
-7:
- move.l (%a1),%d1
- sub.l #_start,%d1
- add.l %a0,%d1
- move.l %d1,(%a1)+
- cmp.l %a2, %a1
- bne 7b
+ move.l #(__got_start), %a5 /* fix got pointer register a5 */
/* calculate relative jump to board_init_r in ram */
- move.l %a0, %a1
- add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+ move.l #(board_init_r), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
diff --git a/arch/m68k/cpu/mcf530x/cpu.c b/arch/m68k/cpu/mcf530x/cpu.c
index 53a25d8..92a0ef7 100644
--- a/arch/m68k/cpu/mcf530x/cpu.c
+++ b/arch/m68k/cpu/mcf530x/cpu.c
@@ -4,7 +4,6 @@
*
*/
-#include <common.h>
#include <command.h>
#include <init.h>
#include <vsprintf.h>
diff --git a/arch/m68k/cpu/mcf530x/cpu_init.c b/arch/m68k/cpu/mcf530x/cpu_init.c
index dad47d8..8f6e668 100644
--- a/arch/m68k/cpu/mcf530x/cpu_init.c
+++ b/arch/m68k/cpu/mcf530x/cpu_init.c
@@ -4,7 +4,6 @@
*
*/
-#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <watchdog.h>
diff --git a/arch/m68k/cpu/mcf530x/interrupts.c b/arch/m68k/cpu/mcf530x/interrupts.c
index 1168620..99cf863 100644
--- a/arch/m68k/cpu/mcf530x/interrupts.c
+++ b/arch/m68k/cpu/mcf530x/interrupts.c
@@ -4,7 +4,6 @@
*
*/
-#include <common.h>
#include <irq_func.h>
#include <asm/immap.h>
#include <asm/io.h>
diff --git a/arch/m68k/cpu/mcf530x/speed.c b/arch/m68k/cpu/mcf530x/speed.c
index c8d0790..6542fc4 100644
--- a/arch/m68k/cpu/mcf530x/speed.c
+++ b/arch/m68k/cpu/mcf530x/speed.c
@@ -4,7 +4,6 @@
*
*/
-#include <common.h>
#include <clock_legacy.h>
#include <asm/global_data.h>
#include <asm/processor.h>
diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S
index cef8d79..552e020 100644
--- a/arch/m68k/cpu/mcf530x/start.S
+++ b/arch/m68k/cpu/mcf530x/start.S
@@ -180,6 +180,39 @@
cmp.l %a1,%a2
bgt.s 1b
+#define R_68K_32 1
+#define R_68K_RELATIVE 22
+
+ move.l #(__rel_dyn_start), %a1
+ move.l #(__rel_dyn_end), %a2
+
+fixloop:
+ move.l (%a1)+, %d1 /* Elf32_Rela r_offset */
+ move.l (%a1)+, %d2 /* Elf32_Rela r_info */
+ move.l (%a1)+, %d3 /* Elf32_Rela r_addend */
+
+ andi.l #0xff, %d2
+ cmp.l #R_68K_32, %d2
+ beq.s fixup
+ cmp.l #R_68K_RELATIVE, %d2
+ beq.s fixup
+
+ bra fixnext
+
+fixup:
+ /* relative fix: store addend plus offset at dest location */
+ move.l %a0, %a3
+ add.l %d1, %a3
+ sub.l #CONFIG_SYS_MONITOR_BASE, %a3
+ move.l (%a3), %d4
+ add.l %a0, %d4
+ sub.l #CONFIG_SYS_MONITOR_BASE, %d4
+ move.l %d4, (%a3)
+
+fixnext:
+ cmp.l %a1, %a2
+ bge.s fixloop
+
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
@@ -194,10 +227,8 @@
/*
* Now clear BSS segment
*/
- move.l %a0, %a1
- add.l #(_sbss - CONFIG_SYS_MONITOR_BASE), %a1
- move.l %a0, %d1
- add.l #(_ebss - CONFIG_SYS_MONITOR_BASE), %d1
+ move.l #(_sbss), %a1
+ move.l #(_ebss), %d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
@@ -206,26 +237,10 @@
/*
* fix got table in RAM
*/
- move.l %a0, %a1
- add.l #(__got_start - CONFIG_SYS_MONITOR_BASE), %a1
-
- /* fix got pointer register a5 */
- move.l %a1,%a5
-
- move.l %a0, %a2
- add.l #(__got_end - CONFIG_SYS_MONITOR_BASE), %a2
-
-7:
- move.l (%a1),%d1
- sub.l #_start, %d1
- add.l %a0,%d1
- move.l %d1,(%a1)+
- cmp.l %a2, %a1
- bne 7b
+ move.l #(__got_start), %a5 /* fix got pointer register a5 */
/* calculate relative jump to board_init_r in ram */
- move.l %a0, %a1
- add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+ move.l #(board_init_r), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
diff --git a/arch/m68k/cpu/mcf532x/cpu.c b/arch/m68k/cpu/mcf532x/cpu.c
index 18d20a8..6973af9 100644
--- a/arch/m68k/cpu/mcf532x/cpu.c
+++ b/arch/m68k/cpu/mcf532x/cpu.c
@@ -8,7 +8,6 @@
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
-#include <common.h>
#include <init.h>
#include <net.h>
#include <vsprintf.h>
diff --git a/arch/m68k/cpu/mcf532x/cpu_init.c b/arch/m68k/cpu/mcf532x/cpu_init.c
index 844d2cd..62a45f9 100644
--- a/arch/m68k/cpu/mcf532x/cpu_init.c
+++ b/arch/m68k/cpu/mcf532x/cpu_init.c
@@ -8,7 +8,6 @@
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
-#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <watchdog.h>
diff --git a/arch/m68k/cpu/mcf532x/interrupts.c b/arch/m68k/cpu/mcf532x/interrupts.c
index 4f72fa8..e37893c 100644
--- a/arch/m68k/cpu/mcf532x/interrupts.c
+++ b/arch/m68k/cpu/mcf532x/interrupts.c
@@ -6,7 +6,6 @@
*/
/* CPU specific interrupt routine */
-#include <common.h>
#include <irq_func.h>
#include <asm/immap.h>
#include <asm/io.h>
diff --git a/arch/m68k/cpu/mcf532x/speed.c b/arch/m68k/cpu/mcf532x/speed.c
index 32ffac08..1669165 100644
--- a/arch/m68k/cpu/mcf532x/speed.c
+++ b/arch/m68k/cpu/mcf532x/speed.c
@@ -8,7 +8,6 @@
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
-#include <common.h>
#include <clock_legacy.h>
#include <asm/global_data.h>
#include <asm/processor.h>
diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S
index 72a2f99..c3eae73 100644
--- a/arch/m68k/cpu/mcf532x/start.S
+++ b/arch/m68k/cpu/mcf532x/start.S
@@ -192,6 +192,39 @@
cmp.l %a1,%a2
bgt.s 1b
+#define R_68K_32 1
+#define R_68K_RELATIVE 22
+
+ move.l #(__rel_dyn_start), %a1
+ move.l #(__rel_dyn_end), %a2
+
+fixloop:
+ move.l (%a1)+, %d1 /* Elf32_Rela r_offset */
+ move.l (%a1)+, %d2 /* Elf32_Rela r_info */
+ move.l (%a1)+, %d3 /* Elf32_Rela r_addend */
+
+ andi.l #0xff, %d2
+ cmp.l #R_68K_32, %d2
+ beq.s fixup
+ cmp.l #R_68K_RELATIVE, %d2
+ beq.s fixup
+
+ bra fixnext
+
+fixup:
+ /* relative fix: store addend plus offset at dest location */
+ move.l %a0, %a3
+ add.l %d1, %a3
+ sub.l #CONFIG_SYS_MONITOR_BASE, %a3
+ move.l (%a3), %d4
+ add.l %a0, %d4
+ sub.l #CONFIG_SYS_MONITOR_BASE, %d4
+ move.l %d4, (%a3)
+
+fixnext:
+ cmp.l %a1, %a2
+ bge.s fixloop
+
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
@@ -206,10 +239,8 @@
/*
* Now clear BSS segment
*/
- move.l %a0, %a1
- add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
- move.l %a0, %d1
- add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
+ move.l #(_sbss), %a1
+ move.l #(_ebss), %d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
@@ -218,24 +249,10 @@
/*
* fix got table in RAM
*/
- move.l %a0, %a1
- add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
- move.l %a1,%a5 /* fix got pointer register a5 */
-
- move.l %a0, %a2
- add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
-
-7:
- move.l (%a1),%d1
- sub.l #_start,%d1
- add.l %a0,%d1
- move.l %d1,(%a1)+
- cmp.l %a2, %a1
- bne 7b
+ move.l #(__got_start), %a5 /* fix got pointer register a5 */
/* calculate relative jump to board_init_r in ram */
- move.l %a0, %a1
- add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+ move.l #(board_init_r), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
diff --git a/arch/m68k/cpu/mcf5445x/cpu.c b/arch/m68k/cpu/mcf5445x/cpu.c
index d9a71c6..b811ac3 100644
--- a/arch/m68k/cpu/mcf5445x/cpu.c
+++ b/arch/m68k/cpu/mcf5445x/cpu.c
@@ -8,7 +8,6 @@
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
-#include <common.h>
#include <init.h>
#include <net.h>
#include <vsprintf.h>
diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c
index bc3a2f3..3277617 100644
--- a/arch/m68k/cpu/mcf5445x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5445x/cpu_init.c
@@ -8,7 +8,6 @@
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
-#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <watchdog.h>
diff --git a/arch/m68k/cpu/mcf5445x/dspi.c b/arch/m68k/cpu/mcf5445x/dspi.c
index 456af17..13eb6ec 100644
--- a/arch/m68k/cpu/mcf5445x/dspi.c
+++ b/arch/m68k/cpu/mcf5445x/dspi.c
@@ -6,7 +6,6 @@
* CPU specific dspi routines
*/
-#include <common.h>
#include <asm/immap.h>
#include <asm/io.h>
diff --git a/arch/m68k/cpu/mcf5445x/interrupts.c b/arch/m68k/cpu/mcf5445x/interrupts.c
index 400f3de..9132900 100644
--- a/arch/m68k/cpu/mcf5445x/interrupts.c
+++ b/arch/m68k/cpu/mcf5445x/interrupts.c
@@ -9,7 +9,6 @@
*/
/* CPU specific interrupt routine */
-#include <common.h>
#include <irq_func.h>
#include <asm/immap.h>
#include <asm/io.h>
diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c
index 5c78eb9..41cb9e9 100644
--- a/arch/m68k/cpu/mcf5445x/speed.c
+++ b/arch/m68k/cpu/mcf5445x/speed.c
@@ -5,7 +5,6 @@
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
-#include <common.h>
#include <clock_legacy.h>
#include <asm/global_data.h>
#include <asm/processor.h>
diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S
index a083c3d..f026467 100644
--- a/arch/m68k/cpu/mcf5445x/start.S
+++ b/arch/m68k/cpu/mcf5445x/start.S
@@ -7,7 +7,6 @@
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
-#include <common.h>
#include <asm-offsets.h>
#include <config.h>
#include <asm/cache.h>
@@ -533,6 +532,39 @@
cmp.l %a1,%a2
bgt.s 1b
+#define R_68K_32 1
+#define R_68K_RELATIVE 22
+
+ move.l #(__rel_dyn_start), %a1
+ move.l #(__rel_dyn_end), %a2
+
+fixloop:
+ move.l (%a1)+, %d1 /* Elf32_Rela r_offset */
+ move.l (%a1)+, %d2 /* Elf32_Rela r_info */
+ move.l (%a1)+, %d3 /* Elf32_Rela r_addend */
+
+ andi.l #0xff, %d2
+ cmp.l #R_68K_32, %d2
+ beq.s fixup
+ cmp.l #R_68K_RELATIVE, %d2
+ beq.s fixup
+
+ bra fixnext
+
+fixup:
+ /* relative fix: store addend plus offset at dest location */
+ move.l %a0, %a3
+ add.l %d1, %a3
+ sub.l #CONFIG_SYS_MONITOR_BASE, %a3
+ move.l (%a3), %d4
+ add.l %a0, %d4
+ sub.l #CONFIG_SYS_MONITOR_BASE, %d4
+ move.l %d4, (%a3)
+
+fixnext:
+ cmp.l %a1, %a2
+ bge.s fixloop
+
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
@@ -547,10 +579,8 @@
/*
* Now clear BSS segment
*/
- move.l %a0, %a1
- add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
- move.l %a0, %d1
- add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
+ move.l #(_sbss), %a1
+ move.l #(_ebss), %d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
@@ -559,24 +589,10 @@
/*
* fix got table in RAM
*/
- move.l %a0, %a1
- add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
- move.l %a1,%a5 /* fix got pointer register a5 */
-
- move.l %a0, %a2
- add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
-
-7:
- move.l (%a1),%d1
- sub.l #_start,%d1
- add.l %a0,%d1
- move.l %d1,(%a1)+
- cmp.l %a2, %a1
- bne 7b
+ move.l #(__got_start), %a5 /* fix got pointer register a5 */
/* calculate relative jump to board_init_r in ram */
- move.l %a0, %a1
- add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+ move.l #(board_init_r), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
diff --git a/arch/m68k/cpu/u-boot.lds b/arch/m68k/cpu/u-boot.lds
index 133f791..03d427c 100644
--- a/arch/m68k/cpu/u-boot.lds
+++ b/arch/m68k/cpu/u-boot.lds
@@ -76,6 +76,20 @@
. = ALIGN(4);
__init_end = .;
+ . = ALIGN(4);
+ __rel_dyn_start = .;
+ .rela.dyn : {
+ *(.rela.dyn)
+ }
+ __rel_dyn_end = .;
+
+ . = ALIGN(4);
+ __dyn_sym_start = .;
+ .dynsym : {
+ *(.dynsym)
+ }
+ __dyn_sym_end = .;
+
_end = .;
__bss_start = .;
diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
index aafa4f4..411b008 100644
--- a/arch/m68k/include/asm/immap.h
+++ b/arch/m68k/include/asm/immap.h
@@ -9,6 +9,7 @@
#ifndef __IMMAP_H
#define __IMMAP_H
+#include <config.h>
#if defined(CONFIG_MCF520x)
#include <asm/immap_520x.h>
#include <asm/m520x.h>
diff --git a/arch/m68k/include/asm/immap_520x.h b/arch/m68k/include/asm/immap_520x.h
index 7c7443b..d3c2f4a 100644
--- a/arch/m68k/include/asm/immap_520x.h
+++ b/arch/m68k/include/asm/immap_520x.h
@@ -36,6 +36,7 @@
#define MMAP_GPIO (CFG_SYS_MBAR + 0x000A4000)
#define MMAP_SDRAM (CFG_SYS_MBAR + 0x000A8000)
+#include <linux/types.h>
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/eport.h>
diff --git a/arch/m68k/include/asm/immap_5235.h b/arch/m68k/include/asm/immap_5235.h
index a1825c2..d9b0be1 100644
--- a/arch/m68k/include/asm/immap_5235.h
+++ b/arch/m68k/include/asm/immap_5235.h
@@ -46,6 +46,7 @@
#define MMAP_ETPU (CFG_SYS_MBAR + 0x001D0000)
#define MMAP_CAN2 (CFG_SYS_MBAR + 0x001F0000)
+#include <linux/types.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
diff --git a/arch/m68k/include/asm/immap_5272.h b/arch/m68k/include/asm/immap_5272.h
index c5c3cc7..5378ed1 100644
--- a/arch/m68k/include/asm/immap_5272.h
+++ b/arch/m68k/include/asm/immap_5272.h
@@ -27,6 +27,7 @@
#define MMAP_FEC (CFG_SYS_MBAR + 0x00000840)
#define MMAP_USB (CFG_SYS_MBAR + 0x00001000)
+#include <linux/types.h>
#include <asm/coldfire/pwm.h>
/* System configuration registers */
diff --git a/arch/m68k/include/asm/immap_5275.h b/arch/m68k/include/asm/immap_5275.h
index 9b8d71d..c4cce3f 100644
--- a/arch/m68k/include/asm/immap_5275.h
+++ b/arch/m68k/include/asm/immap_5275.h
@@ -49,6 +49,7 @@
#define MMAP_USB (CFG_SYS_MBAR + 0x001C0000)
#define MMAP_PWM0 (CFG_SYS_MBAR + 0x001D0000)
+#include <linux/types.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/intctrl.h>
diff --git a/arch/m68k/include/asm/immap_5282.h b/arch/m68k/include/asm/immap_5282.h
index f810a4d..e5f400e 100644
--- a/arch/m68k/include/asm/immap_5282.h
+++ b/arch/m68k/include/asm/immap_5282.h
@@ -45,6 +45,7 @@
#define MMAP_CFMC (CFG_SYS_MBAR + 0x001D0000)
#define MMAP_CFMMEM (CFG_SYS_MBAR + 0x04000000)
+#include <linux/types.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
diff --git a/arch/m68k/include/asm/immap_5301x.h b/arch/m68k/include/asm/immap_5301x.h
index e1f7858..3ade4f0 100644
--- a/arch/m68k/include/asm/immap_5301x.h
+++ b/arch/m68k/include/asm/immap_5301x.h
@@ -50,6 +50,7 @@
#define MMAP_IIM (CFG_SYS_MBAR + 0x000C8000)
#define MMAP_ESDHC (CFG_SYS_MBAR + 0x000CC000)
+#include <linux/types.h>
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/edma.h>
diff --git a/arch/m68k/include/asm/immap_5307.h b/arch/m68k/include/asm/immap_5307.h
index d6442d9..d96dd14 100644
--- a/arch/m68k/include/asm/immap_5307.h
+++ b/arch/m68k/include/asm/immap_5307.h
@@ -17,6 +17,8 @@
#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000200)
#define MMAP_GPIO (CFG_SYS_MBAR + 0x00000244)
+#include <linux/types.h>
+
typedef struct sim {
u8 rsr;
u8 sypcr;
diff --git a/arch/m68k/include/asm/immap_5329.h b/arch/m68k/include/asm/immap_5329.h
index dbf3a22..6f1795a 100644
--- a/arch/m68k/include/asm/immap_5329.h
+++ b/arch/m68k/include/asm/immap_5329.h
@@ -51,6 +51,7 @@
#define MMAP_SSI 0xFC0BC000
#define MMAP_PLL 0xFC0C0000
+#include <linux/types.h>
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/eport.h>
diff --git a/arch/m68k/include/asm/immap_5441x.h b/arch/m68k/include/asm/immap_5441x.h
index 708d0db..c8f3eff 100644
--- a/arch/m68k/include/asm/immap_5441x.h
+++ b/arch/m68k/include/asm/immap_5441x.h
@@ -76,6 +76,7 @@
#define MMAP_CCM 0xEC090000
#define MMAP_GPIO 0xEC094000
+#include <linux/types.h>
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/edma.h>
diff --git a/arch/m68k/lib/bdinfo.c b/arch/m68k/lib/bdinfo.c
index 0b4629f..3719f11 100644
--- a/arch/m68k/lib/bdinfo.c
+++ b/arch/m68k/lib/bdinfo.c
@@ -6,8 +6,9 @@
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
+#include <config.h>
#include <init.h>
+#include <asm/u-boot.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/m68k/lib/bootm.c b/arch/m68k/lib/bootm.c
index f18bed2..79d8b34 100644
--- a/arch/m68k/lib/bootm.c
+++ b/arch/m68k/lib/bootm.c
@@ -4,7 +4,6 @@
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
#include <bootstage.h>
#include <command.h>
#include <env.h>
diff --git a/arch/m68k/lib/cache.c b/arch/m68k/lib/cache.c
index 57e5632..de04124 100644
--- a/arch/m68k/lib/cache.c
+++ b/arch/m68k/lib/cache.c
@@ -4,7 +4,7 @@
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
+#include <config.h>
#include <cpu_func.h>
#include <asm/immap.h>
#include <asm/cache.h>
diff --git a/arch/m68k/lib/fec.c b/arch/m68k/lib/fec.c
index eecea7a..d6f238e 100644
--- a/arch/m68k/lib/fec.c
+++ b/arch/m68k/lib/fec.c
@@ -3,8 +3,8 @@
* (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com>
*/
-#include <common.h>
#include <asm/global_data.h>
+#include <linux/errno.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
diff --git a/arch/m68k/lib/interrupts.c b/arch/m68k/lib/interrupts.c
index 799daab..175ec68 100644
--- a/arch/m68k/lib/interrupts.c
+++ b/arch/m68k/lib/interrupts.c
@@ -7,7 +7,7 @@
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
-#include <common.h>
+#include <stdio.h>
#include <irq_func.h>
#include <watchdog.h>
#include <asm/processor.h>
diff --git a/arch/m68k/lib/time.c b/arch/m68k/lib/time.c
index 61db1e6..4249488 100644
--- a/arch/m68k/lib/time.c
+++ b/arch/m68k/lib/time.c
@@ -6,7 +6,6 @@
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
#include <init.h>
#include <irq_func.h>
#include <time.h>
diff --git a/arch/m68k/lib/traps.c b/arch/m68k/lib/traps.c
index 28fe803..c283351 100644
--- a/arch/m68k/lib/traps.c
+++ b/arch/m68k/lib/traps.c
@@ -7,7 +7,6 @@
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
#include <init.h>
#include <watchdog.h>
#include <command.h>
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index 829e6c7..75ec0a8 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -5,7 +5,6 @@
* Michal SIMEK <monstr@monstr.eu>
*/
-#include <common.h>
#include <cpu_func.h>
#include <asm/asm.h>
#include <asm/cache.h>
diff --git a/arch/microblaze/cpu/cpuinfo.c b/arch/microblaze/cpu/cpuinfo.c
index 6b15d6c..2bfdf76 100644
--- a/arch/microblaze/cpu/cpuinfo.c
+++ b/arch/microblaze/cpu/cpuinfo.c
@@ -2,7 +2,6 @@
/*
* Copyright (C) 2022, Ovidiu Panait <ovpanait@gmail.com>
*/
-#include <common.h>
#include <asm/cpuinfo.h>
#include <asm/global_data.h>
diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c
index 9414776..6b329fc 100644
--- a/arch/microblaze/cpu/exception.c
+++ b/arch/microblaze/cpu/exception.c
@@ -5,8 +5,8 @@
* Michal SIMEK <monstr@monstr.eu>
*/
-#include <common.h>
#include <hang.h>
+#include <stdio.h>
#include <asm/asm.h>
void _hw_exception_handler (void)
diff --git a/arch/microblaze/cpu/interrupts.c b/arch/microblaze/cpu/interrupts.c
index ac53208..244f7fd 100644
--- a/arch/microblaze/cpu/interrupts.c
+++ b/arch/microblaze/cpu/interrupts.c
@@ -7,7 +7,8 @@
* Yasushi SHOJI <yashi@atmark-techno.com>
*/
-#include <common.h>
+#include <log.h>
+#include <vsprintf.h>
#include <asm/asm.h>
void enable_interrupts(void)
diff --git a/arch/microblaze/cpu/pvr.c b/arch/microblaze/cpu/pvr.c
index 23c0f91..71aea0b 100644
--- a/arch/microblaze/cpu/pvr.c
+++ b/arch/microblaze/cpu/pvr.c
@@ -2,7 +2,6 @@
/*
* Copyright (C) 2022, Ovidiu Panait <ovpanait@gmail.com>
*/
-#include <common.h>
#include <asm/asm.h>
#include <asm/pvr.h>
diff --git a/arch/microblaze/cpu/relocate.c b/arch/microblaze/cpu/relocate.c
index 7a15fb2..e46fe5b 100644
--- a/arch/microblaze/cpu/relocate.c
+++ b/arch/microblaze/cpu/relocate.c
@@ -4,8 +4,9 @@
* Michal Simek <michal.simek@amd.com>
*/
-#include <common.h>
#include <elf.h>
+#include <log.h>
+#include <linux/types.h>
#define R_MICROBLAZE_NONE 0
#define R_MICROBLAZE_32 1
diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c
index c21beaf..cb224bd 100644
--- a/arch/microblaze/cpu/spl.c
+++ b/arch/microblaze/cpu/spl.c
@@ -5,7 +5,6 @@
* Michal Simek <michal.simek@amd.com>
*/
-#include <common.h>
#include <command.h>
#include <image.h>
#include <log.h>
diff --git a/arch/microblaze/include/asm/cpuinfo.h b/arch/microblaze/include/asm/cpuinfo.h
index 3c58e52..fbd9418 100644
--- a/arch/microblaze/include/asm/cpuinfo.h
+++ b/arch/microblaze/include/asm/cpuinfo.h
@@ -6,6 +6,8 @@
#ifndef __ASM_MICROBLAZE_CPUINFO_H
#define __ASM_MICROBLAZE_CPUINFO_H
+#include <linux/types.h>
+
/**
* struct microblaze_cpuinfo - CPU info for microblaze processor core.
*
diff --git a/arch/microblaze/include/asm/processor.h b/arch/microblaze/include/asm/processor.h
index 958018c..c0423ea 100644
--- a/arch/microblaze/include/asm/processor.h
+++ b/arch/microblaze/include/asm/processor.h
@@ -6,11 +6,6 @@
#ifndef __ASM_MICROBLAZE_PROCESSOR_H
#define __ASM_MICROBLAZE_PROCESSOR_H
-/* References to section boundaries */
-
-extern char _end[];
-extern char __text_start[];
-
/* Microblaze board initialization function */
void board_init(void);
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index 930384f..f3ec4b7 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -7,7 +7,6 @@
* Yasushi SHOJI <yashi@atmark-techno.com>
*/
-#include <common.h>
#include <bootstage.h>
#include <command.h>
#include <cpu_func.h>
diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c
index f0e20da..acfc9dc 100644
--- a/arch/mips/cpu/cpu.c
+++ b/arch/mips/cpu/cpu.c
@@ -4,7 +4,6 @@
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*/
-#include <common.h>
#include <command.h>
#include <init.h>
#include <linux/compiler.h>
diff --git a/arch/mips/cpu/interrupts.c b/arch/mips/cpu/interrupts.c
index b3ba9aa..f7f9a18 100644
--- a/arch/mips/cpu/interrupts.c
+++ b/arch/mips/cpu/interrupts.c
@@ -4,7 +4,6 @@
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*/
-#include <common.h>
#include <irq_func.h>
int interrupt_init(void)
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index 2acc21d..a95c95b 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -46,7 +46,7 @@
sp, sp, GD_SIZE # reserve space for gd
and sp, sp, t0 # force 16 byte alignment
move k0, sp # save gd pointer
-#if CONFIG_VAL(SYS_MALLOC_F_LEN) && \
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F) && \
!CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
li t2, CONFIG_VAL(SYS_MALLOC_F_LEN)
PTR_SUBU \
@@ -63,7 +63,7 @@
blt t0, t1, 1b
nop
-#if CONFIG_VAL(SYS_MALLOC_F_LEN) && \
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F) && \
!CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
#endif
diff --git a/arch/mips/cpu/time.c b/arch/mips/cpu/time.c
index 5e7a714..210709d 100644
--- a/arch/mips/cpu/time.c
+++ b/arch/mips/cpu/time.c
@@ -4,7 +4,6 @@
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
#include <time.h>
#include <asm/mipsregs.h>
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 1b17911..14fbce5 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -14,6 +14,7 @@
dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
+dtb-$(CONFIG_BOARD_INTENO_XG6846) += inteno,xg6846.dtb
dtb-$(CONFIG_BOARD_MT7620_RFB) += mediatek,mt7620-rfb.dtb
dtb-$(CONFIG_BOARD_MT7620_MT7530_RFB) += mediatek,mt7620-mt7530-rfb.dtb
dtb-$(CONFIG_BOARD_MT7621_RFB) += mediatek,mt7621-rfb.dtb
diff --git a/arch/mips/dts/inteno,xg6846.dts b/arch/mips/dts/inteno,xg6846.dts
new file mode 100644
index 0000000..180cfdc
--- /dev/null
+++ b/arch/mips/dts/inteno,xg6846.dts
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Linus Walleij <linusw@kernel.org>
+ *
+ * This is a diet version of the device tree from Linux,
+ * suitable for U-Boot.
+ */
+
+/dts-v1/;
+
+#include "brcm,bcm6328.dtsi"
+
+/ {
+ model = "Inteno XG6846";
+ compatible = "inteno,xg6846", "brcm,bcm6328";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&leds {
+ status = "okay";
+
+ led@18 {
+ reg = <18>;
+ active-low;
+ label = "red:pwr";
+ };
+
+ led@20 {
+ reg = <20>;
+ active-low;
+ label = "green:pwr";
+ };
+};
+
+&spi {
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <33333334>;
+ };
+};
+
+&uart0 {
+ bootph-all;
+ status = "okay";
+};
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 641e2ad..c1015c8 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -11,6 +11,7 @@
#include <asm/cache.h>
#ifndef __ASSEMBLY__
+#include <linux/types.h>
static inline void mips_cache(int op, const volatile void *addr)
{
diff --git a/arch/mips/lib/boot.c b/arch/mips/lib/boot.c
index 1b29d63..749625a 100644
--- a/arch/mips/lib/boot.c
+++ b/arch/mips/lib/boot.c
@@ -3,7 +3,6 @@
* Copyright (C) 2020 Stefan Roese <sr@denx.de>
*/
-#include <common.h>
#include <command.h>
#include <cpu_func.h>
#include <asm/global_data.h>
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index ab92bd0..d6d2f7d 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -4,7 +4,6 @@
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
#include <bootstage.h>
#include <env.h>
#include <image.h>
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index d23b38d..d365578 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -4,7 +4,6 @@
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*/
-#include <common.h>
#include <cpu_func.h>
#include <malloc.h>
#include <asm/cache.h>
diff --git a/arch/mips/lib/reloc.c b/arch/mips/lib/reloc.c
index 67c8af2..69dd63a 100644
--- a/arch/mips/lib/reloc.c
+++ b/arch/mips/lib/reloc.c
@@ -26,7 +26,6 @@
* terminating R_MIPS_NONE reloc includes no offset.
*/
-#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <asm/relocs.h>
@@ -146,7 +145,7 @@
/* Clear the .bss section */
bss_start = (uint8_t *)((unsigned long)__bss_start + off);
- bss_len = (unsigned long)&__bss_end - (unsigned long)__bss_start;
+ bss_len = (unsigned long)__bss_end - (unsigned long)__bss_start;
memset(bss_start, 0, bss_len);
/* Jump to the relocated U-Boot */
diff --git a/arch/mips/lib/spl.c b/arch/mips/lib/spl.c
index f96fda5..b408754 100644
--- a/arch/mips/lib/spl.c
+++ b/arch/mips/lib/spl.c
@@ -3,7 +3,6 @@
* Copyright (C) 2020 Stefan Roese <sr@denx.de>
*/
-#include <common.h>
#include <cpu_func.h>
#include <log.h>
#include <spl.h>
diff --git a/arch/mips/lib/stack.c b/arch/mips/lib/stack.c
index 930d218..5797271 100644
--- a/arch/mips/lib/stack.c
+++ b/arch/mips/lib/stack.c
@@ -1,6 +1,5 @@
// SPDX-License-Identifier: GPL-2.0+
-#include <common.h>
#include <init.h>
#include <log.h>
#include <asm/global_data.h>
diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c
index 7a682f2..40469d1 100644
--- a/arch/mips/lib/traps.c
+++ b/arch/mips/lib/traps.c
@@ -10,9 +10,9 @@
* Copyright (C) 2014, Imagination Technologies Ltd.
*/
-#include <common.h>
#include <asm/global_data.h>
#include <asm/ptrace.h>
+#include <config.h>
#include <cpu_func.h>
#include <hang.h>
#include <init.h>
@@ -20,6 +20,7 @@
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/system.h>
+#include <asm/u-boot.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/mips/mach-ath79/ar933x/clk.c b/arch/mips/mach-ath79/ar933x/clk.c
index 68d4893..86fc40a 100644
--- a/arch/mips/mach-ath79/ar933x/clk.c
+++ b/arch/mips/mach-ath79/ar933x/clk.c
@@ -3,7 +3,6 @@
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
*/
-#include <common.h>
#include <clock_legacy.h>
#include <asm/global_data.h>
#include <asm/io.h>
diff --git a/arch/mips/mach-ath79/ar933x/ddr.c b/arch/mips/mach-ath79/ar933x/ddr.c
index 09166ec..a932efb 100644
--- a/arch/mips/mach-ath79/ar933x/ddr.c
+++ b/arch/mips/mach-ath79/ar933x/ddr.c
@@ -4,7 +4,6 @@
* Based on Atheros LSDK/QSDK
*/
-#include <common.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/types.h>
diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c
index 6ed4057..bdaa683 100644
--- a/arch/mips/mach-ath79/ar934x/clk.c
+++ b/arch/mips/mach-ath79/ar934x/clk.c
@@ -3,7 +3,6 @@
* Copyright (C) 2016 Marek Vasut <marex@denx.de>
*/
-#include <common.h>
#include <clock_legacy.h>
#include <command.h>
#include <hang.h>
diff --git a/arch/mips/mach-ath79/ar934x/cpu.c b/arch/mips/mach-ath79/ar934x/cpu.c
index 7daac03..f2e4ef1 100644
--- a/arch/mips/mach-ath79/ar934x/cpu.c
+++ b/arch/mips/mach-ath79/ar934x/cpu.c
@@ -3,7 +3,5 @@
* Copyright (C) 2016 Marek Vasut <marex@denx.de>
*/
-#include <common.h>
-
/* The lowlevel_init() is not needed on AR934x */
void lowlevel_init(void) {}
diff --git a/arch/mips/mach-ath79/ar934x/ddr.c b/arch/mips/mach-ath79/ar934x/ddr.c
index 9df48b9..e260783 100644
--- a/arch/mips/mach-ath79/ar934x/ddr.c
+++ b/arch/mips/mach-ath79/ar934x/ddr.c
@@ -5,7 +5,6 @@
* Based on RAM init sequence by Piotr Dymacz <pepe2k@gmail.com>
*/
-#include <common.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/addrspace.h>
diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c
index 79f4190..24160ef 100644
--- a/arch/mips/mach-ath79/cpu.c
+++ b/arch/mips/mach-ath79/cpu.c
@@ -3,7 +3,6 @@
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
*/
-#include <common.h>
#include <init.h>
#include <asm/io.h>
#include <asm/addrspace.h>
diff --git a/arch/mips/mach-ath79/dram.c b/arch/mips/mach-ath79/dram.c
index 545b119..247691d 100644
--- a/arch/mips/mach-ath79/dram.c
+++ b/arch/mips/mach-ath79/dram.c
@@ -3,7 +3,6 @@
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
*/
-#include <common.h>
#include <init.h>
#include <asm/global_data.h>
#include <linux/sizes.h>
diff --git a/arch/mips/mach-ath79/qca953x/clk.c b/arch/mips/mach-ath79/qca953x/clk.c
index f5438ef..379085f 100644
--- a/arch/mips/mach-ath79/qca953x/clk.c
+++ b/arch/mips/mach-ath79/qca953x/clk.c
@@ -3,7 +3,6 @@
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
*/
-#include <common.h>
#include <clock_legacy.h>
#include <asm/global_data.h>
#include <asm/io.h>
diff --git a/arch/mips/mach-ath79/qca953x/ddr.c b/arch/mips/mach-ath79/qca953x/ddr.c
index 78f2370..0eb69d3 100644
--- a/arch/mips/mach-ath79/qca953x/ddr.c
+++ b/arch/mips/mach-ath79/qca953x/ddr.c
@@ -4,7 +4,6 @@
* Based on Atheros LSDK/QSDK
*/
-#include <common.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/types.h>
diff --git a/arch/mips/mach-ath79/qca956x/clk.c b/arch/mips/mach-ath79/qca956x/clk.c
index 6a58dba..6138a91 100644
--- a/arch/mips/mach-ath79/qca956x/clk.c
+++ b/arch/mips/mach-ath79/qca956x/clk.c
@@ -3,7 +3,6 @@
* Copyright (C) 2019 Rosy Song <rosysong@rosinson.com>
*/
-#include <common.h>
#include <clock_legacy.h>
#include <log.h>
#include <asm/global_data.h>
diff --git a/arch/mips/mach-ath79/qca956x/cpu.c b/arch/mips/mach-ath79/qca956x/cpu.c
index 08a8c84..7da8d0e 100644
--- a/arch/mips/mach-ath79/qca956x/cpu.c
+++ b/arch/mips/mach-ath79/qca956x/cpu.c
@@ -3,7 +3,5 @@
* Copyright (C) 2019 Rosy Song <rosysong@rosinson.com>
*/
-#include <common.h>
-
/* The lowlevel_init() is not needed on QCA956X */
void lowlevel_init(void) {}
diff --git a/arch/mips/mach-ath79/qca956x/ddr.c b/arch/mips/mach-ath79/qca956x/ddr.c
index f9cf8da..2e46e24 100644
--- a/arch/mips/mach-ath79/qca956x/ddr.c
+++ b/arch/mips/mach-ath79/qca956x/ddr.c
@@ -5,7 +5,6 @@
* Based on QSDK
*/
-#include <common.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/addrspace.h>
diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
index 6cd5e77..62da8b9 100644
--- a/arch/mips/mach-ath79/reset.c
+++ b/arch/mips/mach-ath79/reset.c
@@ -4,7 +4,6 @@
* Copyright (C) 2018-2019 Rosy Song <rosysong@rosinson.com>
*/
-#include <common.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/errno.h>
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index 01d919f..eb9ea34 100644
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -203,6 +203,17 @@
ethernet ports, 3 USB ports, 1 UART, GPIO buttons and LEDs, and
a RT3062F/AR9223 (PCI).
+config BOARD_INTENO_XG6846
+ bool "Inteno XG6846"
+ depends on SOC_BMIPS_BCM6328
+ select BMIPS_SUPPORTS_BOOT_RAM
+ help
+ Inteno XG6846 boards have a BCM6328 SoC with 64 MB of RAM and 16
+ MB of flash (SPI).
+ Between its different peripherals there's an integrated switch with 4
+ ethernet ports, 1 UART, GPIO buttons and LEDs, and a Marvell
+ DSA switch connected to a fiber SFP.
+
config BOARD_NETGEAR_CG3100D
bool "Netgear CG3100D"
depends on SOC_BMIPS_BCM3380
@@ -272,6 +283,7 @@
source "board/comtrend/vr3032u/Kconfig"
source "board/comtrend/wap5813n/Kconfig"
source "board/huawei/hg556a/Kconfig"
+source "board/inteno/xg6846/Kconfig"
source "board/netgear/cg3100d/Kconfig"
source "board/netgear/dgnd3700v2/Kconfig"
source "board/sagem/f@st1704/Kconfig"
diff --git a/arch/mips/mach-bmips/dram.c b/arch/mips/mach-bmips/dram.c
index bba6cd6..eec8b44 100644
--- a/arch/mips/mach-bmips/dram.c
+++ b/arch/mips/mach-bmips/dram.c
@@ -4,7 +4,6 @@
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*/
-#include <common.h>
#include <init.h>
#include <log.h>
#include <ram.h>
diff --git a/arch/mips/mach-jz47xx/jz4780/gpio.c b/arch/mips/mach-jz47xx/jz4780/gpio.c
index d4884e7..7f6717e 100644
--- a/arch/mips/mach-jz47xx/jz4780/gpio.c
+++ b/arch/mips/mach-jz47xx/jz4780/gpio.c
@@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
#include <config.h>
-#include <common.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <mach/jz4780.h>
diff --git a/arch/mips/mach-jz47xx/jz4780/jz4780.c b/arch/mips/mach-jz47xx/jz4780/jz4780.c
index 676c305..1d6fb6a 100644
--- a/arch/mips/mach-jz47xx/jz4780/jz4780.c
+++ b/arch/mips/mach-jz47xx/jz4780/jz4780.c
@@ -7,7 +7,6 @@
*/
#include <config.h>
-#include <common.h>
#include <cpu_func.h>
#include <hang.h>
#include <image.h>
@@ -42,7 +41,7 @@
enable_caches();
/* Clear the BSS */
- memset(__bss_start, 0, (char *)&__bss_end - __bss_start);
+ memset(__bss_start, 0, (size_t)__bss_end - (size_t)__bss_start);
gd->flags |= GD_FLG_SPL_INIT;
diff --git a/arch/mips/mach-jz47xx/jz4780/pll.c b/arch/mips/mach-jz47xx/jz4780/pll.c
index 4519b47..8ef00f9 100644
--- a/arch/mips/mach-jz47xx/jz4780/pll.c
+++ b/arch/mips/mach-jz47xx/jz4780/pll.c
@@ -7,7 +7,6 @@
*/
#include <config.h>
-#include <common.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/delay.h>
diff --git a/arch/mips/mach-jz47xx/jz4780/reset.c b/arch/mips/mach-jz47xx/jz4780/reset.c
index bf6addc..d2e9eb7 100644
--- a/arch/mips/mach-jz47xx/jz4780/reset.c
+++ b/arch/mips/mach-jz47xx/jz4780/reset.c
@@ -7,7 +7,6 @@
*/
#include <config.h>
-#include <common.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <mach/jz4780.h>
diff --git a/arch/mips/mach-jz47xx/jz4780/sdram.c b/arch/mips/mach-jz47xx/jz4780/sdram.c
index 690f3c5..09296ee 100644
--- a/arch/mips/mach-jz47xx/jz4780/sdram.c
+++ b/arch/mips/mach-jz47xx/jz4780/sdram.c
@@ -9,7 +9,6 @@
* Copyright (c) 2006-2013 Ingenic Semiconductor
*/
-#include <common.h>
#include <hang.h>
#include <init.h>
#include <asm/io.h>
diff --git a/arch/mips/mach-jz47xx/jz4780/timer.c b/arch/mips/mach-jz47xx/jz4780/timer.c
index 82bb9e8..94ef505 100644
--- a/arch/mips/mach-jz47xx/jz4780/timer.c
+++ b/arch/mips/mach-jz47xx/jz4780/timer.c
@@ -7,7 +7,6 @@
*/
#include <config.h>
-#include <common.h>
#include <div64.h>
#include <init.h>
#include <irq_func.h>
diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c
index d484eb92..22b1b98 100644
--- a/arch/mips/mach-mscc/cpu.c
+++ b/arch/mips/mach-mscc/cpu.c
@@ -3,7 +3,6 @@
* Copyright (c) 2018 Microsemi Corporation
*/
-#include <common.h>
#include <init.h>
#include <asm/global_data.h>
#include <linux/bitops.h>
diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c
index f7fbd33..c7c2040 100644
--- a/arch/mips/mach-mscc/dram.c
+++ b/arch/mips/mach-mscc/dram.c
@@ -3,7 +3,6 @@
* Copyright (c) 2018 Microsemi Corporation
*/
-#include <common.h>
#include <init.h>
#include <asm/global_data.h>
diff --git a/arch/mips/mach-mscc/gpio.c b/arch/mips/mach-mscc/gpio.c
index d6b4c5d..6cd0e24 100644
--- a/arch/mips/mach-mscc/gpio.c
+++ b/arch/mips/mach-mscc/gpio.c
@@ -3,7 +3,6 @@
* Copyright (c) 2018 Microsemi Corporation
*/
-#include <common.h>
#include <asm/io.h>
#include <linux/bitops.h>
diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h
index 75fb3ca..3ba33d2 100644
--- a/arch/mips/mach-mscc/include/mach/ddr.h
+++ b/arch/mips/mach-mscc/include/mach/ddr.h
@@ -6,6 +6,7 @@
#ifndef __ASM_MACH_DDR_H
#define __ASM_MACH_DDR_H
+#include <config.h>
#include <asm/cacheops.h>
#include <asm/io.h>
#include <asm/reboot.h>
diff --git a/arch/mips/mach-mscc/phy.c b/arch/mips/mach-mscc/phy.c
index 83d3e5b..444d1f5 100644
--- a/arch/mips/mach-mscc/phy.c
+++ b/arch/mips/mach-mscc/phy.c
@@ -3,7 +3,6 @@
* Copyright (c) 2018 Microsemi Corporation
*/
-#include <common.h>
#include <log.h>
#include <asm/io.h>
diff --git a/arch/mips/mach-mscc/reset.c b/arch/mips/mach-mscc/reset.c
index a121457..ca9a7c6 100644
--- a/arch/mips/mach-mscc/reset.c
+++ b/arch/mips/mach-mscc/reset.c
@@ -3,8 +3,6 @@
* Copyright (c) 2018 Microsemi Corporation
*/
-#include <common.h>
-
#include <asm/sections.h>
#include <asm/io.h>
diff --git a/arch/mips/mach-mtmips/cpu.c b/arch/mips/mach-mtmips/cpu.c
index f1e9022..243938a 100644
--- a/arch/mips/mach-mtmips/cpu.c
+++ b/arch/mips/mach-mtmips/cpu.c
@@ -3,7 +3,7 @@
* Copyright (C) 2018 Stefan Roese <sr@denx.de>
*/
-#include <common.h>
+#include <event.h>
#include <init.h>
#include <malloc.h>
#include <asm/addrspace.h>
@@ -21,7 +21,8 @@
return 0;
}
-int last_stage_init(void)
+#ifndef CONFIG_SPL_BUILD
+static int last_stage_init(void)
{
void *src, *dst;
@@ -46,3 +47,5 @@
return 0;
}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
+#endif
diff --git a/arch/mips/mach-mtmips/ddr_cal.c b/arch/mips/mach-mtmips/ddr_cal.c
index 762619a..e2e1760 100644
--- a/arch/mips/mach-mtmips/ddr_cal.c
+++ b/arch/mips/mach-mtmips/ddr_cal.c
@@ -5,7 +5,6 @@
* Author: Weijie Gao <weijie.gao@mediatek.com>
*/
-#include <common.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
#include <asm/global_data.h>
diff --git a/arch/mips/mach-mtmips/ddr_init.c b/arch/mips/mach-mtmips/ddr_init.c
index 9c986da..cab5356 100644
--- a/arch/mips/mach-mtmips/ddr_init.c
+++ b/arch/mips/mach-mtmips/ddr_init.c
@@ -5,7 +5,6 @@
* Author: Weijie Gao <weijie.gao@mediatek.com>
*/
-#include <common.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/io.h>
diff --git a/arch/mips/mach-mtmips/mt7621/spl/launch.c b/arch/mips/mach-mtmips/mt7621/spl/launch.c
index 37c20a5..95dd659 100644
--- a/arch/mips/mach-mtmips/mt7621/spl/launch.c
+++ b/arch/mips/mach-mtmips/mt7621/spl/launch.c
@@ -70,7 +70,7 @@
cpumask = 0x0f;
/* Make BootROM/TPL redirect Core1's bootup flow to our entry point */
- writel((uintptr_t)&_start, sysc + BOOT_SRAM_BASE_REG);
+ writel((uintptr_t)_start, sysc + BOOT_SRAM_BASE_REG);
bootup_secondary_core();
}
diff --git a/arch/mips/mach-mtmips/mt7621/spl/spl.c b/arch/mips/mach-mtmips/mt7621/spl/spl.c
index aa5b267..25b409e 100644
--- a/arch/mips/mach-mtmips/mt7621/spl/spl.c
+++ b/arch/mips/mach-mtmips/mt7621/spl/spl.c
@@ -86,7 +86,7 @@
uint32_t spl_nand_get_uboot_raw_page(void)
{
- const struct stage_header *sh = (const struct stage_header *)&_start;
+ const struct stage_header *sh = (const struct stage_header *)_start;
u32 addr;
addr = image_get_header_size() + be32_to_cpu(sh->stage_size);
diff --git a/arch/mips/mach-mtmips/mt7621/spl/start.S b/arch/mips/mach-mtmips/mt7621/spl/start.S
index d2f9c03..d56e624 100644
--- a/arch/mips/mach-mtmips/mt7621/spl/start.S
+++ b/arch/mips/mach-mtmips/mt7621/spl/start.S
@@ -37,7 +37,7 @@
sp, sp, GD_SIZE # reserve space for gd
and sp, sp, t0 # force 16 byte alignment
move k0, sp # save gd pointer
-#if CONFIG_VAL(SYS_MALLOC_F_LEN) && \
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F) && \
!CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
li t2, CONFIG_VAL(SYS_MALLOC_F_LEN)
PTR_SUBU \
@@ -54,7 +54,7 @@
blt t0, t1, 1b
nop
-#if CONFIG_VAL(SYS_MALLOC_F_LEN) && \
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F) && \
!CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
#endif
diff --git a/arch/mips/mach-mtmips/mt7628/ddr.c b/arch/mips/mach-mtmips/mt7628/ddr.c
index 4e72459..198bf26 100644
--- a/arch/mips/mach-mtmips/mt7628/ddr.c
+++ b/arch/mips/mach-mtmips/mt7628/ddr.c
@@ -5,7 +5,6 @@
* Author: Weijie Gao <weijie.gao@mediatek.com>
*/
-#include <common.h>
#include <asm/addrspace.h>
#include <asm/global_data.h>
#include <linux/bitops.h>
diff --git a/arch/mips/mach-mtmips/mt7628/init.c b/arch/mips/mach-mtmips/mt7628/init.c
index 6b53512..2996fd9 100644
--- a/arch/mips/mach-mtmips/mt7628/init.c
+++ b/arch/mips/mach-mtmips/mt7628/init.c
@@ -5,7 +5,6 @@
* Author: Weijie Gao <weijie.gao@mediatek.com>
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <asm/global_data.h>
diff --git a/arch/mips/mach-mtmips/mt7628/serial.c b/arch/mips/mach-mtmips/mt7628/serial.c
index e5f3f87..11a2149 100644
--- a/arch/mips/mach-mtmips/mt7628/serial.c
+++ b/arch/mips/mach-mtmips/mt7628/serial.c
@@ -5,7 +5,6 @@
* Author: Weijie Gao <weijie.gao@mediatek.com>
*/
-#include <common.h>
#include <asm/io.h>
#include "mt7628.h"
diff --git a/arch/mips/mach-mtmips/spl.c b/arch/mips/mach-mtmips/spl.c
index fe5b49e..0208bc4 100644
--- a/arch/mips/mach-mtmips/spl.c
+++ b/arch/mips/mach-mtmips/spl.c
@@ -5,7 +5,6 @@
* Author: Weijie Gao <weijie.gao@mediatek.com>
*/
-#include <common.h>
#include <init.h>
#include <spl.h>
#include <asm/sections.h>
diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c
index ec3c250..dbf8c9c 100644
--- a/arch/mips/mach-pic32/cpu.c
+++ b/arch/mips/mach-pic32/cpu.c
@@ -4,7 +4,6 @@
* Purna Chandra Mandal <purna.mandal@microchip.com>
*
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <event.h>
@@ -57,7 +56,7 @@
}
/* initialize prefetch module related to cpu_clk */
-static void prefetch_init(void)
+static int prefetch_init(void)
{
struct pic32_reg_atomic *regs;
const void __iomem *base;
@@ -93,16 +92,12 @@
/* Enable prefetch for all */
writel(0x30, ®s->set);
iounmap(regs);
-}
-/* arch specific CPU init after DM */
-static int pic32_flash_prefetch(void *ctx, struct event *event)
-{
- /* flash prefetch */
- prefetch_init();
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, pic32_flash_prefetch);
+
+/* arch-specific CPU init after DM: flash prefetch */
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, prefetch_init);
/* Un-gate DDR2 modules (gated by default) */
static void ddr2_pmd_ungate(void)
diff --git a/arch/mips/mach-pic32/reset.c b/arch/mips/mach-pic32/reset.c
index 8071b13..efd6985 100644
--- a/arch/mips/mach-pic32/reset.c
+++ b/arch/mips/mach-pic32/reset.c
@@ -4,7 +4,6 @@
*
*/
-#include <common.h>
#include <asm/io.h>
#include <mach/pic32.h>
diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c
index da167f4..79a54d1 100644
--- a/arch/nios2/cpu/cpu.c
+++ b/arch/nios2/cpu/cpu.c
@@ -64,7 +64,7 @@
}
#endif
-static int nios_cpu_setup(void *ctx, struct event *event)
+static int nios_cpu_setup(void)
{
struct udevice *dev;
int ret;
@@ -80,7 +80,7 @@
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, nios_cpu_setup);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, nios_cpu_setup);
static int altera_nios2_get_desc(const struct udevice *dev, char *buf,
int size)
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index 6749263..d72d314 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -244,7 +244,7 @@
cmplw r3, r4
bne 1b
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CFG_SYS_INIT_RAM_SIZE
#error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 562b699..b737d5d 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1233,7 +1233,7 @@
lis r3,(CFG_SYS_INIT_RAM_ADDR)@h
ori r3,r3,((CFG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CFG_SYS_INIT_RAM_SIZE
#error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
#endif
@@ -1253,7 +1253,7 @@
cmplw r4,r3
bne 1b
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
lis r4,SYS_INIT_SP_ADDR@h
ori r4,r4,SYS_INIT_SP_ADDR@l
@@ -1617,7 +1617,7 @@
mr r10,r5 /* Save copy of Destination Address */
GET_GOT
-#ifndef CONFIG_SPL_SKIP_RELOCATE
+#if !defined(CONFIG_SPL_SKIP_RELOCATE) || !defined(CONFIG_SPL_BUILD)
mr r3,r5 /* Destination Address */
lis r4,CONFIG_VAL(SYS_MONITOR_BASE)@h /* Source Address */
ori r4,r4,CONFIG_VAL(SYS_MONITOR_BASE)@l
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index bd2af8d..1731c96 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -94,7 +94,7 @@
config SYS_SYPCR
hex "SYPCR register" if !WDT_MPC8xxx
- default 0
+ default 0x0
help
System Protection Control (11-9)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 1c62c23..6d0d812 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -8,12 +8,15 @@
prompt "Target select"
optional
-config TARGET_AE350
- bool "Support ae350"
+config TARGET_ANDES_AE350
+ bool "Support Andes ae350"
config TARGET_MICROCHIP_ICICLE
bool "Support Microchip PolarFire-SoC Icicle Board"
+config TARGET_OPENPITON_RISCV64
+ bool "Support RISC-V cores on OpenPiton SoC"
+
config TARGET_QEMU_VIRT
bool "Support QEMU Virt Board"
@@ -24,6 +27,10 @@
bool "Support SiFive Unmatched Board"
select SYS_CACHE_SHIFT_6
+config TARGET_SIPEED_MAIX
+ bool "Support Sipeed Maix Board"
+ select SYS_CACHE_SHIFT_6
+
config TARGET_STARFIVE_VISIONFIVE2
bool "Support StarFive VisionFive2 Board"
select BOARD_LATE_INIT
@@ -32,13 +39,6 @@
bool "Support Sipeed's TH1520 Lichee PI 4A Board"
select SYS_CACHE_SHIFT_6
-config TARGET_SIPEED_MAIX
- bool "Support Sipeed Maix Board"
- select SYS_CACHE_SHIFT_6
-
-config TARGET_OPENPITON_RISCV64
- bool "Support RISC-V cores on OpenPiton SoC"
-
endchoice
config SYS_ICACHE_OFF
@@ -68,7 +68,6 @@
config SPL_ZERO_MEM_BEFORE_USE
bool "Zero memory before use"
depends on SPL
- default n
help
Zero stack/GD/malloc area in SPL before using them, this is needed for
Sifive core devices that uses L2 cache to store SPL.
@@ -77,12 +76,12 @@
source "board/AndesTech/ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
+source "board/openpiton/riscv64/Kconfig"
source "board/sifive/unleashed/Kconfig"
source "board/sifive/unmatched/Kconfig"
-source "board/thead/th1520_lpi4a/Kconfig"
-source "board/openpiton/riscv64/Kconfig"
source "board/sipeed/maix/Kconfig"
source "board/starfive/visionfive2/Kconfig"
+source "board/thead/th1520_lpi4a/Kconfig"
# platform-specific options below
source "arch/riscv/cpu/andesv5/Kconfig"
@@ -141,6 +140,7 @@
config RISCV_SMODE
bool "Supervisor"
+ imply DEBUG_UART
help
Choose this option to build U-Boot for RISC-V S-Mode.
@@ -186,6 +186,97 @@
riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to
lp64d.
+config RISCV_ISA_ZBB
+ bool "Zbb extension support for bit manipulation instructions"
+ help
+ Adds ZBB extension (basic bit manipulation) to the ISA subsets
+ that the toolchain is allowed to emit when building U-Boot.
+ The Zbb extension provides instructions to accelerate a number
+ of bit-specific operations (count bit population, sign extending,
+ bitrotation, etc) and enables optimized string routines.
+
+menu "Use assembly optimized implementation of string routines"
+
+config USE_ARCH_STRLEN
+ bool "Use an assembly optimized implementation of strlen"
+ default y
+ depends on RISCV_ISA_ZBB
+ help
+ Enable the generation of an optimized version of strlen using
+ Zbb extension.
+
+config SPL_USE_ARCH_STRLEN
+ bool "Use an assembly optimized implementation of strlen for SPL"
+ default y if USE_ARCH_STRLEN
+ depends on RISCV_ISA_ZBB
+ depends on SPL
+ help
+ Enable the generation of an optimized version of strlen using
+ Zbb extension.
+
+config TPL_USE_ARCH_STRLEN
+ bool "Use an assembly optimized implementation of strlen for TPL"
+ default y if USE_ARCH_STRLEN
+ depends on RISCV_ISA_ZBB
+ depends on TPL
+ help
+ Enable the generation of an optimized version of strlen using
+ Zbb extension.
+
+config USE_ARCH_STRCMP
+ bool "Use an assembly optimized implementation of strcmp"
+ default y
+ depends on RISCV_ISA_ZBB
+ help
+ Enable the generation of an optimized version of strcmp using
+ Zbb extension.
+
+config SPL_USE_ARCH_STRCMP
+ bool "Use an assembly optimized implementation of strcmp for SPL"
+ default y if USE_ARCH_STRCMP
+ depends on RISCV_ISA_ZBB
+ depends on SPL
+ help
+ Enable the generation of an optimized version of strcmp using
+ Zbb extension.
+
+config TPL_USE_ARCH_STRCMP
+ bool "Use an assembly optimized implementation of strcmp for TPL"
+ default y if USE_ARCH_STRCMP
+ depends on RISCV_ISA_ZBB
+ depends on TPL
+ help
+ Enable the generation of an optimized version of strcmp using
+ Zbb extension.
+
+config USE_ARCH_STRNCMP
+ bool "Use an assembly optimized implementation of strncmp"
+ default y
+ depends on RISCV_ISA_ZBB
+ help
+ Enable the generation of an optimized version of strncmp using
+ Zbb extension.
+
+config SPL_USE_ARCH_STRNCMP
+ bool "Use an assembly optimized implementation of strncmp for SPL"
+ default y if USE_ARCH_STRNCMP
+ depends on RISCV_ISA_ZBB
+ depends on SPL
+ help
+ Enable the generation of an optimized version of strncmp using
+ Zbb extension.
+
+config TPL_USE_ARCH_STRNCMP
+ bool "Use an assembly optimized implementation of strncmp for TPL"
+ default y if USE_ARCH_STRNCMP
+ depends on RISCV_ISA_ZBB
+ depends on TPL
+ help
+ Enable the generation of an optimized version of strncmp using
+ Zbb extension.
+
+endmenu
+
config RISCV_ISA_A
def_bool y
@@ -423,4 +514,12 @@
endmenu
+config SPL_LOAD_FIT_OPENSBI_OS_BOOT
+ bool "Enable SPL (OpenSBI OS boot mode) applying linux from FIT"
+ depends on SPL_LOAD_FIT
+ help
+ Use fw_dynamic from the FIT image, and u-boot SPL will invoke it directly.
+ This is a shortcut boot flow, from u-boot SPL -> OpenSBI -> u-boot proper
+ -> linux to u-boot SPL -> OpenSBI -> linux.
+
endmenu
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 4963b51..b3ef870 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -24,6 +24,9 @@
ifeq ($(CONFIG_RISCV_ISA_C),y)
ARCH_C = c
endif
+ifeq ($(CONFIG_RISCV_ISA_ZBB),y)
+ ARCH_ZBB = _zbb
+endif
ifeq ($(CONFIG_CMODEL_MEDLOW),y)
CMODEL = medlow
endif
@@ -32,7 +35,7 @@
endif
-RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C)
+RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C)$(ARCH_ZBB)
ABI = $(ABI_BASE)$(ABI_D)
# Newer binutils versions default to ISA spec version 20191213 which moves some
diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andesv5/Kconfig
index 82bb5a2..f311291 100644
--- a/arch/riscv/cpu/andesv5/Kconfig
+++ b/arch/riscv/cpu/andesv5/Kconfig
@@ -4,8 +4,9 @@
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+ imply ANDES_PLMT_TIMER
+ imply SPL_ANDES_PLMT_TIMER
imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
- imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
imply V5L2_CACHE
imply SPL_CPU
imply SPL_OPENSBI
diff --git a/arch/riscv/cpu/andesv5/cache.c b/arch/riscv/cpu/andesv5/cache.c
index 40d77f6..269bb27 100644
--- a/arch/riscv/cpu/andesv5/cache.c
+++ b/arch/riscv/cpu/andesv5/cache.c
@@ -6,7 +6,6 @@
#include <asm/csr.h>
#include <asm/asm.h>
-#include <common.h>
#include <cache.h>
#include <cpu_func.h>
#include <dm.h>
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
index 06e379b..63bc24c 100644
--- a/arch/riscv/cpu/andesv5/cpu.c
+++ b/arch/riscv/cpu/andesv5/cpu.c
@@ -5,7 +5,6 @@
*/
/* CPU specific code */
-#include <common.h>
#include <cpu_func.h>
#include <irq_func.h>
#include <asm/cache.h>
diff --git a/arch/riscv/cpu/andesv5/spl.c b/arch/riscv/cpu/andesv5/spl.c
index 4138490..a13dc40 100644
--- a/arch/riscv/cpu/andesv5/spl.c
+++ b/arch/riscv/cpu/andesv5/spl.c
@@ -3,7 +3,6 @@
* Copyright (C) 2023 Andes Technology Corporation
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
*/
-#include <common.h>
#include <cpu_func.h>
#include <hang.h>
#include <init.h>
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 0975ff5..1b70aba 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -3,7 +3,6 @@
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
*/
-#include <common.h>
#include <cpu.h>
#include <dm.h>
#include <dm/lists.h>
@@ -72,7 +71,7 @@
#endif /* CONFIG_CPU */
}
-static int riscv_cpu_probe(void *ctx, struct event *event)
+static int riscv_cpu_probe(void)
{
#ifdef CONFIG_CPU
int ret;
@@ -85,7 +84,7 @@
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_R, riscv_cpu_probe);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_R, riscv_cpu_probe);
/*
* This is called on secondary harts just after the IPI is init'd. Currently
@@ -98,13 +97,9 @@
}
#endif
-int riscv_cpu_setup(void *ctx, struct event *event)
+int riscv_cpu_setup(void)
{
- int ret;
-
- ret = riscv_cpu_probe(ctx, event);
- if (ret)
- return ret;
+ int __maybe_unused ret;
/* Enable FPU */
if (supports_extension('d') || supports_extension('f')) {
@@ -152,7 +147,7 @@
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, riscv_cpu_setup);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, riscv_cpu_setup);
int arch_early_init_r(void)
{
diff --git a/arch/riscv/cpu/fu540/dram.c b/arch/riscv/cpu/fu540/dram.c
index 94d8018..7b5a347 100644
--- a/arch/riscv/cpu/fu540/dram.c
+++ b/arch/riscv/cpu/fu540/dram.c
@@ -3,7 +3,6 @@
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
*/
-#include <common.h>
#include <fdtdec.h>
#include <init.h>
#include <asm/global_data.h>
diff --git a/arch/riscv/cpu/fu740/dram.c b/arch/riscv/cpu/fu740/dram.c
index 8657fcd..61f5517 100644
--- a/arch/riscv/cpu/fu740/dram.c
+++ b/arch/riscv/cpu/fu740/dram.c
@@ -3,7 +3,6 @@
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
*/
-#include <common.h>
#include <fdtdec.h>
#include <init.h>
#include <linux/sizes.h>
diff --git a/arch/riscv/cpu/generic/cpu.c b/arch/riscv/cpu/generic/cpu.c
index d78e1a3..f13c189 100644
--- a/arch/riscv/cpu/generic/cpu.c
+++ b/arch/riscv/cpu/generic/cpu.c
@@ -3,7 +3,6 @@
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
*/
-#include <common.h>
#include <irq_func.h>
#include <asm/cache.h>
diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c
index 94d8018..91007c0 100644
--- a/arch/riscv/cpu/generic/dram.c
+++ b/arch/riscv/cpu/generic/dram.c
@@ -3,7 +3,6 @@
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
*/
-#include <common.h>
#include <fdtdec.h>
#include <init.h>
#include <asm/global_data.h>
@@ -20,19 +19,3 @@
{
return fdtdec_setup_memory_banksize();
}
-
-phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
-{
- /*
- * Ensure that we run from first 4GB so that all
- * addresses used by U-Boot are 32bit addresses.
- *
- * This in-turn ensures that 32bit DMA capable
- * devices work fine because DMA mapping APIs will
- * provide 32bit DMA addresses only.
- */
- if (gd->ram_top >= SZ_4G)
- return SZ_4G - 1;
-
- return gd->ram_top;
-}
diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c
index 1a9fa46..664b9b9 100644
--- a/arch/riscv/cpu/jh7110/dram.c
+++ b/arch/riscv/cpu/jh7110/dram.c
@@ -4,7 +4,6 @@
* Author: Yanhong Wang <yanhong.wang@starfivetech.com>
*/
-#include <common.h>
#include <fdtdec.h>
#include <init.h>
#include <linux/sizes.h>
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
index 4047b10..6bdf8b9 100644
--- a/arch/riscv/cpu/jh7110/spl.c
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -3,7 +3,6 @@
* Copyright (C) 2022 StarFive Technology Co., Ltd.
* Author: Yanhong Wang<yanhong.wang@starfivetech.com>
*/
-#include <common.h>
#include <asm/arch/eeprom.h>
#include <asm/csr.h>
#include <asm/sections.h>
diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S
index e40c7bd..5cad7b4 100644
--- a/arch/riscv/cpu/mtrap.S
+++ b/arch/riscv/cpu/mtrap.S
@@ -11,7 +11,6 @@
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
*/
-#include <common.h>
#include <asm/encoding.h>
#ifdef CONFIG_32BIT
@@ -27,7 +26,7 @@
.text
/* trap entry */
- .align 2
+ .align 6
.global trap_entry
trap_entry:
addi sp, sp, -32 * REGBYTES
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 30cf674..6cecadf 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -11,7 +11,6 @@
#include <asm-offsets.h>
#include <config.h>
-#include <common.h>
#include <elf.h>
#include <system-constants.h>
#include <asm/encoding.h>
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index f1525cb..be6c8a4 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
-dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb
+dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
index 156cb00..9271de0 100644
--- a/arch/riscv/dts/binman.dtsi
+++ b/arch/riscv/dts/binman.dtsi
@@ -13,26 +13,46 @@
&binman {
itb {
+
+#ifndef CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT
filename = "u-boot.itb";
+#else
+ filename = "linux.itb";
+#endif
fit {
description = "Configuration to load OpenSBI before U-Boot";
- #address-cells = <1>;
+ #address-cells = <2>;
fit,fdt-list = "of-list";
images {
+#ifndef CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT
uboot {
description = "U-Boot";
type = "standalone";
os = "U-Boot";
arch = "riscv";
compression = "none";
- load = <CONFIG_TEXT_BASE>;
+ load = /bits/ 64 <CONFIG_TEXT_BASE>;
uboot_blob: blob-ext {
filename = "u-boot-nodtb.bin";
};
};
+#else
+ linux {
+ description = "Linux";
+ type = "standalone";
+ os = "Linux";
+ arch = "riscv";
+ compression = "none";
+ load = /bits/ 64 <CONFIG_TEXT_BASE>;
+
+ linux_blob: blob-ext {
+ filename = "Image";
+ };
+ };
+#endif
opensbi {
description = "OpenSBI fw_dynamic Firmware";
@@ -40,8 +60,8 @@
os = "opensbi";
arch = "riscv";
compression = "none";
- load = <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
- entry = <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
+ load = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
+ entry = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
opensbi_blob: opensbi {
filename = "fw_dynamic.bin";
@@ -68,7 +88,11 @@
#endif
description = "NAME";
firmware = "opensbi";
+#ifndef CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT
loadables = "uboot";
+#else
+ loadables = "linux";
+#endif
#ifndef CONFIG_OF_BOARD
fdt = "fdt-SEQ";
#endif
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
index 13f69da..5518531 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
@@ -103,4 +103,15 @@
};
};
};
+
+ spl-img {
+ filename = "spl/u-boot-spl.bin.normal.out";
+
+ mkimage {
+ args = "-T sfspl";
+
+ u-boot-spl {
+ };
+ };
+};
};
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index ec237a4..6d2675d 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -533,6 +533,16 @@
#gpio-cells = <2>;
};
+ watchdog@13070000 {
+ compatible = "starfive,jh7110-wdt";
+ reg = <0x0 0x13070000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
+ <&syscrg JH7110_SYSCLK_WDT_CORE>;
+ clock-names = "apb", "core";
+ resets = <&syscrg JH7110_SYSRST_WDT_APB>,
+ <&syscrg JH7110_SYSRST_WDT_CORE>;
+ };
+
mmc0: mmc@16010000 {
compatible = "starfive,jh7110-mmc";
reg = <0x0 0x16010000 0x0 0x10000>;
@@ -627,6 +637,16 @@
status = "disabled";
};
+ rng: rng@1600c000 {
+ compatible = "starfive,jh7110-trng";
+ reg = <0x0 0x1600C000 0x0 0x4000>;
+ clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
+ <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
+ clock-names = "hclk", "ahb";
+ resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
+ interrupts = <30>;
+ };
+
aoncrg: clock-controller@17000000 {
compatible = "starfive,jh7110-aoncrg";
reg = <0x0 0x17000000 0x0 0x10000>;
diff --git a/arch/riscv/dts/sunxi-d1-t113.dtsi b/arch/riscv/dts/sunxi-d1-t113.dtsi
new file mode 100644
index 0000000..b715612
--- /dev/null
+++ b/arch/riscv/dts/sunxi-d1-t113.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
+
+/ {
+ soc {
+ dsp_wdt: watchdog@1700400 {
+ compatible = "allwinner,sun20i-d1-wdt";
+ reg = <0x1700400 0x20>;
+ interrupts = <SOC_PERIPHERAL_IRQ(122) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dcxo>, <&rtc CLK_OSC32K>;
+ clock-names = "hosc", "losc";
+ status = "reserved";
+ };
+ };
+};
diff --git a/arch/riscv/dts/sunxi-d1s-t113.dtsi b/arch/riscv/dts/sunxi-d1s-t113.dtsi
new file mode 100644
index 0000000..822f022
--- /dev/null
+++ b/arch/riscv/dts/sunxi-d1s-t113.dtsi
@@ -0,0 +1,927 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
+
+#include <dt-bindings/clock/sun6i-rtc.h>
+#include <dt-bindings/clock/sun8i-de2.h>
+#include <dt-bindings/clock/sun8i-tcon-top.h>
+#include <dt-bindings/clock/sun20i-d1-ccu.h>
+#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/reset/sun8i-de2.h>
+#include <dt-bindings/reset/sun20i-d1-ccu.h>
+#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ dcxo: dcxo-clk {
+ compatible = "fixed-clock";
+ clock-output-names = "dcxo";
+ #clock-cells = <0>;
+ };
+
+ de: display-engine {
+ compatible = "allwinner,sun20i-d1-display-engine";
+ allwinner,pipelines = <&mixer0>, <&mixer1>;
+ status = "disabled";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ ranges;
+ dma-noncoherent;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pio: pinctrl@2000000 {
+ compatible = "allwinner,sun20i-d1-pinctrl";
+ reg = <0x2000000 0x800>;
+ interrupts = <SOC_PERIPHERAL_IRQ(69) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(71) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(73) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(75) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(77) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(79) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_APB0>,
+ <&dcxo>,
+ <&rtc CLK_OSC32K>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ interrupt-controller;
+ #gpio-cells = <3>;
+ #interrupt-cells = <3>;
+
+ /omit-if-no-ref/
+ can0_pins: can0-pins {
+ pins = "PB2", "PB3";
+ function = "can0";
+ };
+
+ /omit-if-no-ref/
+ can1_pins: can1-pins {
+ pins = "PB4", "PB5";
+ function = "can1";
+ };
+
+ /omit-if-no-ref/
+ clk_pg11_pin: clk-pg11-pin {
+ pins = "PG11";
+ function = "clk";
+ };
+
+ /omit-if-no-ref/
+ dsi_4lane_pins: dsi-4lane-pins {
+ pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
+ "PD6", "PD7", "PD8", "PD9";
+ drive-strength = <30>;
+ function = "dsi";
+ };
+
+ /omit-if-no-ref/
+ lcd_rgb666_pins: lcd-rgb666-pins {
+ pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
+ "PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
+ "PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
+ "PD18", "PD19", "PD20", "PD21";
+ function = "lcd0";
+ };
+
+ /omit-if-no-ref/
+ mmc0_pins: mmc0-pins {
+ pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
+ function = "mmc0";
+ };
+
+ /omit-if-no-ref/
+ mmc1_pins: mmc1-pins {
+ pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
+ function = "mmc1";
+ };
+
+ /omit-if-no-ref/
+ mmc2_pins: mmc2-pins {
+ pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
+ function = "mmc2";
+ };
+
+ /omit-if-no-ref/
+ rgmii_pe_pins: rgmii-pe-pins {
+ pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+ "PE5", "PE6", "PE7", "PE8", "PE9",
+ "PE11", "PE12", "PE13", "PE14", "PE15";
+ function = "emac";
+ };
+
+ /omit-if-no-ref/
+ rmii_pe_pins: rmii-pe-pins {
+ pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+ "PE5", "PE6", "PE7", "PE8", "PE9";
+ function = "emac";
+ };
+
+ /omit-if-no-ref/
+ spi0_pins: spi0-pins {
+ pins = "PC2", "PC3", "PC4", "PC5";
+ function = "spi0";
+ };
+
+ /omit-if-no-ref/
+ uart1_pg6_pins: uart1-pg6-pins {
+ pins = "PG6", "PG7";
+ function = "uart1";
+ };
+
+ /omit-if-no-ref/
+ uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
+ pins = "PG8", "PG9";
+ function = "uart1";
+ };
+
+ /omit-if-no-ref/
+ uart3_pb_pins: uart3-pb-pins {
+ pins = "PB6", "PB7";
+ function = "uart3";
+ };
+ };
+
+ ccu: clock-controller@2001000 {
+ compatible = "allwinner,sun20i-d1-ccu";
+ reg = <0x2001000 0x1000>;
+ clocks = <&dcxo>,
+ <&rtc CLK_OSC32K>,
+ <&rtc CLK_IOSC>;
+ clock-names = "hosc", "losc", "iosc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ gpadc: adc@2009000 {
+ compatible = "allwinner,sun20i-d1-gpadc";
+ reg = <0x2009000 0x400>;
+ clocks = <&ccu CLK_BUS_GPADC>;
+ resets = <&ccu RST_BUS_GPADC>;
+ interrupts = <SOC_PERIPHERAL_IRQ(57) IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #io-channel-cells = <1>;
+ };
+
+ dmic: dmic@2031000 {
+ compatible = "allwinner,sun20i-d1-dmic",
+ "allwinner,sun50i-h6-dmic";
+ reg = <0x2031000 0x400>;
+ interrupts = <SOC_PERIPHERAL_IRQ(24) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DMIC>,
+ <&ccu CLK_DMIC>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_DMIC>;
+ dmas = <&dma 8>;
+ dma-names = "rx";
+ status = "disabled";
+ #sound-dai-cells = <0>;
+ };
+
+ i2s1: i2s@2033000 {
+ compatible = "allwinner,sun20i-d1-i2s",
+ "allwinner,sun50i-r329-i2s";
+ reg = <0x2033000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(27) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S1>,
+ <&ccu CLK_I2S1>;
+ clock-names = "apb", "mod";
+ resets = <&ccu RST_BUS_I2S1>;
+ dmas = <&dma 4>, <&dma 4>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #sound-dai-cells = <0>;
+ };
+
+ i2s2: i2s@2034000 {
+ compatible = "allwinner,sun20i-d1-i2s",
+ "allwinner,sun50i-r329-i2s";
+ reg = <0x2034000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S2>,
+ <&ccu CLK_I2S2>;
+ clock-names = "apb", "mod";
+ resets = <&ccu RST_BUS_I2S2>;
+ dmas = <&dma 5>, <&dma 5>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #sound-dai-cells = <0>;
+ };
+
+ timer: timer@2050000 {
+ compatible = "allwinner,sun20i-d1-timer",
+ "allwinner,sun8i-a23-timer";
+ reg = <0x2050000 0xa0>;
+ interrupts = <SOC_PERIPHERAL_IRQ(59) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(60) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dcxo>;
+ };
+
+ wdt: watchdog@20500a0 {
+ compatible = "allwinner,sun20i-d1-wdt-reset",
+ "allwinner,sun20i-d1-wdt";
+ reg = <0x20500a0 0x20>;
+ interrupts = <SOC_PERIPHERAL_IRQ(63) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dcxo>, <&rtc CLK_OSC32K>;
+ clock-names = "hosc", "losc";
+ status = "reserved";
+ };
+
+ uart0: serial@2500000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x2500000 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
+ dmas = <&dma 14>, <&dma 14>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart1: serial@2500400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x2500400 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
+ dmas = <&dma 15>, <&dma 15>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart2: serial@2500800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x2500800 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
+ dmas = <&dma 16>, <&dma 16>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart3: serial@2500c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x2500c00 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_UART3>;
+ resets = <&ccu RST_BUS_UART3>;
+ dmas = <&dma 17>, <&dma 17>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart4: serial@2501000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x2501000 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_UART4>;
+ resets = <&ccu RST_BUS_UART4>;
+ dmas = <&dma 18>, <&dma 18>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart5: serial@2501400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x2501400 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_UART5>;
+ resets = <&ccu RST_BUS_UART5>;
+ dmas = <&dma 19>, <&dma 19>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c0: i2c@2502000 {
+ compatible = "allwinner,sun20i-d1-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x2502000 0x400>;
+ interrupts = <SOC_PERIPHERAL_IRQ(9) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C0>;
+ resets = <&ccu RST_BUS_I2C0>;
+ dmas = <&dma 43>, <&dma 43>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@2502400 {
+ compatible = "allwinner,sun20i-d1-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x2502400 0x400>;
+ interrupts = <SOC_PERIPHERAL_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C1>;
+ resets = <&ccu RST_BUS_I2C1>;
+ dmas = <&dma 44>, <&dma 44>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@2502800 {
+ compatible = "allwinner,sun20i-d1-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x2502800 0x400>;
+ interrupts = <SOC_PERIPHERAL_IRQ(11) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C2>;
+ resets = <&ccu RST_BUS_I2C2>;
+ dmas = <&dma 45>, <&dma 45>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c@2502c00 {
+ compatible = "allwinner,sun20i-d1-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x2502c00 0x400>;
+ interrupts = <SOC_PERIPHERAL_IRQ(12) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C3>;
+ resets = <&ccu RST_BUS_I2C3>;
+ dmas = <&dma 46>, <&dma 46>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ can0: can@2504000 {
+ compatible = "allwinner,sun20i-d1-can";
+ reg = <0x02504000 0x400>;
+ interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CAN0>;
+ resets = <&ccu RST_BUS_CAN0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&can0_pins>;
+ status = "disabled";
+ };
+
+ can1: can@2504400 {
+ compatible = "allwinner,sun20i-d1-can";
+ reg = <0x02504400 0x400>;
+ interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CAN1>;
+ resets = <&ccu RST_BUS_CAN1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&can1_pins>;
+ status = "disabled";
+ };
+
+ syscon: syscon@3000000 {
+ compatible = "allwinner,sun20i-d1-system-control";
+ reg = <0x3000000 0x1000>;
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ dma: dma-controller@3002000 {
+ compatible = "allwinner,sun20i-d1-dma";
+ reg = <0x3002000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
+ clock-names = "bus", "mbus";
+ resets = <&ccu RST_BUS_DMA>;
+ dma-channels = <16>;
+ dma-requests = <48>;
+ #dma-cells = <1>;
+ };
+
+ sid: efuse@3006000 {
+ compatible = "allwinner,sun20i-d1-sid";
+ reg = <0x3006000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ crypto: crypto@3040000 {
+ compatible = "allwinner,sun20i-d1-crypto";
+ reg = <0x3040000 0x800>;
+ interrupts = <SOC_PERIPHERAL_IRQ(52) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CE>,
+ <&ccu CLK_CE>,
+ <&ccu CLK_MBUS_CE>,
+ <&rtc CLK_IOSC>;
+ clock-names = "bus", "mod", "ram", "trng";
+ resets = <&ccu RST_BUS_CE>;
+ };
+
+ mbus: dram-controller@3102000 {
+ compatible = "allwinner,sun20i-d1-mbus";
+ reg = <0x3102000 0x1000>,
+ <0x3103000 0x1000>;
+ reg-names = "mbus", "dram";
+ interrupts = <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_MBUS>,
+ <&ccu CLK_DRAM>,
+ <&ccu CLK_BUS_DRAM>;
+ clock-names = "mbus", "dram", "bus";
+ dma-ranges = <0 0x40000000 0x80000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interconnect-cells = <1>;
+ };
+
+ mmc0: mmc@4020000 {
+ compatible = "allwinner,sun20i-d1-mmc";
+ reg = <0x4020000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ cap-sd-highspeed;
+ max-frequency = <150000000>;
+ no-mmc;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@4021000 {
+ compatible = "allwinner,sun20i-d1-mmc";
+ reg = <0x4021000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ cap-sd-highspeed;
+ max-frequency = <150000000>;
+ no-mmc;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@4022000 {
+ compatible = "allwinner,sun20i-d1-emmc",
+ "allwinner,sun50i-a100-emmc";
+ reg = <0x4022000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC2>;
+ reset-names = "ahb";
+ cap-mmc-highspeed;
+ max-frequency = <150000000>;
+ mmc-ddr-1_8v;
+ mmc-ddr-3_3v;
+ no-sd;
+ no-sdio;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi0: spi@4025000 {
+ compatible = "allwinner,sun20i-d1-spi",
+ "allwinner,sun50i-r329-spi";
+ reg = <0x04025000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(15) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 22>, <&dma 22>;
+ dma-names = "rx", "tx";
+ resets = <&ccu RST_BUS_SPI0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@4026000 {
+ compatible = "allwinner,sun20i-d1-spi-dbi",
+ "allwinner,sun50i-r329-spi-dbi",
+ "allwinner,sun50i-r329-spi";
+ reg = <0x04026000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(16) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 23>, <&dma 23>;
+ dma-names = "rx", "tx";
+ resets = <&ccu RST_BUS_SPI1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ usb_otg: usb@4100000 {
+ compatible = "allwinner,sun20i-d1-musb",
+ "allwinner,sun8i-a33-musb";
+ reg = <0x4100000 0x400>;
+ interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc";
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ extcon = <&usbphy 0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usbphy: phy@4100400 {
+ compatible = "allwinner,sun20i-d1-usb-phy";
+ reg = <0x4100400 0x100>,
+ <0x4101800 0x100>,
+ <0x4200800 0x100>;
+ reg-names = "phy_ctrl",
+ "pmu0",
+ "pmu1";
+ clocks = <&dcxo>,
+ <&dcxo>;
+ clock-names = "usb0_phy",
+ "usb1_phy";
+ resets = <&ccu RST_USB_PHY0>,
+ <&ccu RST_USB_PHY1>;
+ reset-names = "usb0_reset",
+ "usb1_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci0: usb@4101000 {
+ compatible = "allwinner,sun20i-d1-ehci",
+ "generic-ehci";
+ reg = <0x4101000 0x100>;
+ interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_BUS_EHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>,
+ <&ccu RST_BUS_EHCI0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci0: usb@4101400 {
+ compatible = "allwinner,sun20i-d1-ohci",
+ "generic-ohci";
+ reg = <0x4101400 0x100>;
+ interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci1: usb@4200000 {
+ compatible = "allwinner,sun20i-d1-ehci",
+ "generic-ehci";
+ reg = <0x4200000 0x100>;
+ interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_BUS_EHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>,
+ <&ccu RST_BUS_EHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@4200400 {
+ compatible = "allwinner,sun20i-d1-ohci",
+ "generic-ohci";
+ reg = <0x4200400 0x100>;
+ interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ emac: ethernet@4500000 {
+ compatible = "allwinner,sun20i-d1-emac",
+ "allwinner,sun50i-a64-emac";
+ reg = <0x4500000 0x10000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ syscon = <&syscon>;
+ status = "disabled";
+
+ mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ display_clocks: clock-controller@5000000 {
+ compatible = "allwinner,sun20i-d1-de2-clk",
+ "allwinner,sun50i-h5-de2-clk";
+ reg = <0x5000000 0x10000>;
+ clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mixer0: mixer@5100000 {
+ compatible = "allwinner,sun20i-d1-de2-mixer-0";
+ reg = <0x5100000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER0>,
+ <&display_clocks CLK_MIXER0>;
+ clock-names = "bus", "mod";
+ resets = <&display_clocks RST_MIXER0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port@1 {
+ reg = <1>;
+
+ mixer0_out_tcon_top_mixer0: endpoint {
+ remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
+ };
+ };
+ };
+ };
+
+ mixer1: mixer@5200000 {
+ compatible = "allwinner,sun20i-d1-de2-mixer-1";
+ reg = <0x5200000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER1>,
+ <&display_clocks CLK_MIXER1>;
+ clock-names = "bus", "mod";
+ resets = <&display_clocks RST_MIXER1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer1_out: port@1 {
+ reg = <1>;
+
+ mixer1_out_tcon_top_mixer1: endpoint {
+ remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
+ };
+ };
+ };
+ };
+
+ dsi: dsi@5450000 {
+ compatible = "allwinner,sun20i-d1-mipi-dsi",
+ "allwinner,sun50i-a100-mipi-dsi";
+ reg = <0x5450000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_MIPI_DSI>,
+ <&tcon_top CLK_TCON_TOP_DSI>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_MIPI_DSI>;
+ phys = <&dphy>;
+ phy-names = "dphy";
+ status = "disabled";
+
+ port {
+ dsi_in_tcon_lcd0: endpoint {
+ remote-endpoint = <&tcon_lcd0_out_dsi>;
+ };
+ };
+ };
+
+ dphy: phy@5451000 {
+ compatible = "allwinner,sun20i-d1-mipi-dphy",
+ "allwinner,sun50i-a100-mipi-dphy";
+ reg = <0x5451000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_MIPI_DSI>,
+ <&ccu CLK_MIPI_DSI>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_MIPI_DSI>;
+ #phy-cells = <0>;
+ };
+
+ tcon_top: tcon-top@5460000 {
+ compatible = "allwinner,sun20i-d1-tcon-top";
+ reg = <0x5460000 0x1000>;
+ clocks = <&ccu CLK_BUS_DPSS_TOP>,
+ <&ccu CLK_TCON_TV>,
+ <&ccu CLK_TVE>,
+ <&ccu CLK_TCON_LCD0>;
+ clock-names = "bus", "tcon-tv0", "tve0", "dsi";
+ clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
+ resets = <&ccu RST_BUS_DPSS_TOP>;
+ #clock-cells = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_top_mixer0_in: port@0 {
+ reg = <0>;
+
+ tcon_top_mixer0_in_mixer0: endpoint {
+ remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
+ };
+ };
+
+ tcon_top_mixer0_out: port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
+ };
+
+ tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
+ };
+ };
+
+ tcon_top_mixer1_in: port@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_top_mixer1_in_mixer1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
+ };
+ };
+
+ tcon_top_mixer1_out: port@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
+ };
+
+ tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
+ };
+ };
+
+ tcon_top_hdmi_in: port@4 {
+ reg = <4>;
+
+ tcon_top_hdmi_in_tcon_tv0: endpoint {
+ remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
+ };
+ };
+
+ tcon_top_hdmi_out: port@5 {
+ reg = <5>;
+ };
+ };
+ };
+
+ tcon_lcd0: lcd-controller@5461000 {
+ compatible = "allwinner,sun20i-d1-tcon-lcd";
+ reg = <0x5461000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(90) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON_LCD0>,
+ <&ccu CLK_TCON_LCD0>;
+ clock-names = "ahb", "tcon-ch0";
+ clock-output-names = "tcon-pixel-clock";
+ resets = <&ccu RST_BUS_TCON_LCD0>,
+ <&ccu RST_BUS_LVDS0>;
+ reset-names = "lcd", "lvds";
+ #clock-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_lcd0_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
+ };
+
+ tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
+ };
+ };
+
+ tcon_lcd0_out: port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_lcd0_out_dsi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dsi_in_tcon_lcd0>;
+ };
+ };
+ };
+ };
+
+ tcon_tv0: lcd-controller@5470000 {
+ compatible = "allwinner,sun20i-d1-tcon-tv";
+ reg = <0x5470000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON_TV>,
+ <&tcon_top CLK_TCON_TOP_TV0>;
+ clock-names = "ahb", "tcon-ch1";
+ resets = <&ccu RST_BUS_TCON_TV>;
+ reset-names = "lcd";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_tv0_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
+ };
+
+ tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
+ };
+ };
+
+ tcon_tv0_out: port@1 {
+ reg = <1>;
+
+ tcon_tv0_out_tcon_top_hdmi: endpoint {
+ remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
+ };
+ };
+ };
+ };
+
+ ppu: power-controller@7001000 {
+ compatible = "allwinner,sun20i-d1-ppu";
+ reg = <0x7001000 0x1000>;
+ clocks = <&r_ccu CLK_BUS_R_PPU>;
+ resets = <&r_ccu RST_BUS_R_PPU>;
+ #power-domain-cells = <1>;
+ };
+
+ r_ccu: clock-controller@7010000 {
+ compatible = "allwinner,sun20i-d1-r-ccu";
+ reg = <0x7010000 0x400>;
+ clocks = <&dcxo>,
+ <&rtc CLK_OSC32K>,
+ <&rtc CLK_IOSC>,
+ <&ccu CLK_PLL_PERIPH0_DIV3>;
+ clock-names = "hosc", "losc", "iosc", "pll-periph";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ rtc: rtc@7090000 {
+ compatible = "allwinner,sun20i-d1-rtc",
+ "allwinner,sun50i-r329-rtc";
+ reg = <0x7090000 0x400>;
+ interrupts = <SOC_PERIPHERAL_IRQ(144) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_BUS_R_RTC>,
+ <&dcxo>,
+ <&r_ccu CLK_R_AHB>;
+ clock-names = "bus", "hosc", "ahb";
+ #clock-cells = <1>;
+ };
+ };
+};
diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h
index c7ed920..393d51c 100644
--- a/arch/riscv/include/asm/arch-andes/csr.h
+++ b/arch/riscv/include/asm/arch-andes/csr.h
@@ -7,6 +7,7 @@
#define _ASM_ANDES_CSR_H
#include <asm/asm.h>
+#include <linux/bitops.h>
#include <linux/const.h>
#define CSR_MCACHE_CTL 0x7ca
diff --git a/arch/riscv/include/asm/arch-jh7110/eeprom.h b/arch/riscv/include/asm/arch-jh7110/eeprom.h
index f354d5c..d2776d5 100644
--- a/arch/riscv/include/asm/arch-jh7110/eeprom.h
+++ b/arch/riscv/include/asm/arch-jh7110/eeprom.h
@@ -7,6 +7,8 @@
#ifndef _ASM_RISCV_EEPROM_H
#define _ASM_RISCV_EEPROM_H
+#include <linux/types.h>
+
u8 get_pcb_revision_from_eeprom(void);
u32 get_ddr_size_from_eeprom(void);
diff --git a/arch/riscv/include/asm/arch-jh7110/gpio.h b/arch/riscv/include/asm/arch-jh7110/gpio.h
new file mode 100644
index 0000000..90aa2f8
--- /dev/null
+++ b/arch/riscv/include/asm/arch-jh7110/gpio.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: yanhong <yanhong.wang@starfivetech.com>
+ *
+ */
+
+#ifndef _GPIO_STARFIVE_H_
+#define _GPIO_STARFIVE_H_
+
+#include <asm/arch/regs.h>
+
+#define GPIO_NUM_SHIFT 2 /*one dword include 4 gpios*/
+#define GPIO_BYTE_SHIFT 3
+
+#define GPIO_INDEX_MASK 0x3
+
+#define GPIO_DOEN_MASK 0x3f
+#define GPIO_DOUT_MASK 0x7f
+#define GPIO_DIN_MASK 0x7f
+#define GPIO_DS_MASK 0x06
+#define GPIO_DS_SHIFT 1
+#define GPIO_SLEW_MASK BIT(5)
+#define GPIO_SLEW_SHIFT 5
+#define GPIO_PULL_MASK 0x18
+#define GPIO_PULL_SHIFT 3
+#define GPIO_PULL_UP 1
+#define GPIO_PULL_DOWN 2
+
+#define NR_GPIOS 64
+
+#define GPIO_OFFSET(gpio) \
+ (((gpio) >> GPIO_NUM_SHIFT) << GPIO_NUM_SHIFT)
+
+#define GPIO_SHIFT(gpio) \
+ (((gpio) & GPIO_INDEX_MASK) << GPIO_BYTE_SHIFT)
+
+enum gpio_state {
+ LOW,
+ HIGH
+};
+
+#define GPIO_DOEN 0x0
+#define GPIO_DOUT 0x40
+#define GPIO_DIN 0x80
+#define GPIO_EN 0xdc
+#define GPIO_LOW_IE 0x100
+#define GPIO_HIGH_IE 0x104
+#define GPIO_CONFIG 0x120
+
+#define SYS_IOMUX_DOEN(gpio, oen) \
+ clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_OFFSET(gpio), \
+ GPIO_DOEN_MASK << GPIO_SHIFT(gpio), \
+ (oen) << GPIO_SHIFT(gpio))
+
+#define SYS_IOMUX_DOUT(gpio, gpo) \
+ clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DOUT + GPIO_OFFSET(gpio), \
+ GPIO_DOUT_MASK << GPIO_SHIFT(gpio), \
+ ((gpo) & GPIO_DOUT_MASK) << GPIO_SHIFT(gpio))
+
+#define SYS_IOMUX_DIN(gpio, gpi)\
+ clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DIN + GPIO_OFFSET(gpi), \
+ GPIO_DIN_MASK << GPIO_SHIFT(gpi), \
+ ((gpio + 2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi))
+
+#define SYS_IOMUX_SET_DS(gpio, ds) \
+ clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \
+ GPIO_DS_MASK, (ds) << GPIO_DS_SHIFT)
+
+#define SYS_IOMUX_SET_SLEW(gpio, slew) \
+ clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \
+ GPIO_SLEW_MASK, (slew) << GPIO_SLEW_SHIFT)
+
+#define SYS_IOMUX_SET_PULL(gpio, pull) \
+ clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \
+ GPIO_PULL_MASK, (pull) << GPIO_PULL_SHIFT)
+
+#define SYS_IOMUX_COMPLEX(gpio, gpi, gpo, oen) \
+ do { \
+ SYS_IOMUX_DOEN(gpio, oen); \
+ SYS_IOMUX_DOUT(gpio, gpo); \
+ SYS_IOMUX_DIN(gpio, gpi); \
+ } while (0)
+
+#endif /* _GPIO_STARFIVE_H_ */
diff --git a/arch/riscv/include/asm/dma-mapping.h b/arch/riscv/include/asm/dma-mapping.h
index 6ecadab..d0cc5d7 100644
--- a/arch/riscv/include/asm/dma-mapping.h
+++ b/arch/riscv/include/asm/dma-mapping.h
@@ -9,7 +9,6 @@
#ifndef __ASM_RISCV_DMA_MAPPING_H
#define __ASM_RISCV_DMA_MAPPING_H
-#include <common.h>
#include <linux/types.h>
#include <asm/cache.h>
#include <cpu_func.h>
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index 9d97517..937fa4d 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -32,6 +32,9 @@
ulong available_harts;
#endif
#endif
+#ifdef CONFIG_SMBIOS
+ ulong smbios_start; /* Start address of SMBIOS table */
+#endif
};
#include <asm-generic/global_data.h>
diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index b16e6df..4170877 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -323,6 +323,51 @@
#define insw_p(port, to, len) insw(port, to, len)
#define insl_p(port, to, len) insl(port, to, len)
+/*
+ * Unordered I/O memory access primitives. These are even more relaxed than
+ * the relaxed versions, as they don't even order accesses between successive
+ * operations to the I/O regions.
+ */
+#define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; })
+#define readw_cpu(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
+#define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
+
+#define writeb_cpu(v, c) ((void)__raw_writeb((v), (c)))
+#define writew_cpu(v, c) ((void)__raw_writew((__force u16)cpu_to_le16(v), (c)))
+#define writel_cpu(v, c) ((void)__raw_writel((__force u32)cpu_to_le32(v), (c)))
+
+#ifdef CONFIG_64BIT
+#define readq_cpu(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
+#define writeq_cpu(v, c) ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c)))
+#endif
+
+/*
+ * Relaxed I/O memory access primitives. These follow the Device memory
+ * ordering rules but do not guarantee any ordering relative to Normal memory
+ * accesses. These are defined to order the indicated access (either a read or
+ * write) with all other I/O memory accesses to the same peripheral. Since the
+ * platform specification defines that all I/O regions are strongly ordered on
+ * channel 0, no explicit fences are required to enforce this ordering.
+ */
+/* FIXME: These are now the same as asm-generic */
+#define __io_rbr() do {} while (0)
+#define __io_rar() do {} while (0)
+#define __io_rbw() do {} while (0)
+#define __io_raw() do {} while (0)
+
+#define readb_relaxed(c) ({ u8 __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; })
+#define readw_relaxed(c) ({ u16 __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; })
+#define readl_relaxed(c) ({ u32 __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; })
+
+#define writeb_relaxed(v, c) ({ __io_rbw(); writeb_cpu((v), (c)); __io_raw(); })
+#define writew_relaxed(v, c) ({ __io_rbw(); writew_cpu((v), (c)); __io_raw(); })
+#define writel_relaxed(v, c) ({ __io_rbw(); writel_cpu((v), (c)); __io_raw(); })
+
+#ifdef CONFIG_64BIT
+#define readq_relaxed(c) ({ u64 __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; })
+#define writeq_relaxed(v, c) ({ __io_rbw(); writeq_cpu((v), (c)); __io_raw(); })
+#endif
+
#include <asm-generic/io.h>
#endif /* __ASM_RISCV_IO_H */
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index 4284a33..ee749dd 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -7,6 +7,8 @@
#ifndef _ASM_RISCV_SMP_H
#define _ASM_RISCV_SMP_H
+#include <linux/types.h>
+
/**
* struct ipi_data - Inter-processor interrupt (IPI) data structure
*
diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h
index 7dee3e4..38ad85f 100644
--- a/arch/riscv/include/asm/string.h
+++ b/arch/riscv/include/asm/string.h
@@ -40,4 +40,22 @@
#endif
extern void *memset(void *, int, __kernel_size_t);
+#undef __HAVE_ARCH_STRLEN
+#if CONFIG_IS_ENABLED(USE_ARCH_STRLEN)
+#define __HAVE_ARCH_STRLEN
+#endif
+extern __kernel_size_t strlen(const char *);
+
+#undef __HAVE_ARCH_STRCMP
+#if CONFIG_IS_ENABLED(USE_ARCH_STRCMP)
+#define __HAVE_ARCH_STRCMP
+#endif
+extern int strcmp(const char *, const char *);
+
+#undef __HAVE_ARCH_STRNCMP
+#if CONFIG_IS_ENABLED(USE_ARCH_STRNCMP)
+#define __HAVE_ARCH_STRNCMP
+#endif
+extern int strncmp(const char *, const char *, size_t __kernel_size_t);
+
#endif /* __ASM_RISCV_STRING_H */
diff --git a/arch/riscv/include/asm/system.h b/arch/riscv/include/asm/system.h
index ffa7649..87a804b 100644
--- a/arch/riscv/include/asm/system.h
+++ b/arch/riscv/include/asm/system.h
@@ -26,6 +26,6 @@
} while (0)
/* Hook to set up the CPU (called from SPL too) */
-int riscv_cpu_setup(void *ctx, struct event *event);
+int riscv_cpu_setup(void);
#endif /* __ASM_RISCV_SYSTEM_H */
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 02c4d8f..9a05b66 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -42,5 +42,8 @@
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMMOVE) += memmove.o
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o
+obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_STRLEN) += strlen_zbb.o
+obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_STRCMP) += strcmp_zbb.o
+obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_STRNCMP) += strncmp_zbb.o
obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o
diff --git a/arch/riscv/lib/aclint_ipi.c b/arch/riscv/lib/aclint_ipi.c
index 90b8e12..dcd7e5e 100644
--- a/arch/riscv/lib/aclint_ipi.c
+++ b/arch/riscv/lib/aclint_ipi.c
@@ -8,7 +8,6 @@
* associated with software and timer interrupts.
*/
-#include <common.h>
#include <dm.h>
#include <regmap.h>
#include <syscon.h>
diff --git a/arch/riscv/lib/andes_plicsw.c b/arch/riscv/lib/andes_plicsw.c
index 7518408..c09e5c6 100644
--- a/arch/riscv/lib/andes_plicsw.c
+++ b/arch/riscv/lib/andes_plicsw.c
@@ -8,7 +8,6 @@
* similar to RISC-V PLIC.
*/
-#include <common.h>
#include <dm.h>
#include <asm/global_data.h>
#include <dm/device-internal.h>
@@ -22,41 +21,36 @@
#include <linux/err.h>
/* pending register */
-#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4)
+#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + 4 * (((hart) + 1) / 32))
/* enable register */
-#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
+#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80 + 4 * (((hart) + 1) / 32))
/* claim register */
#define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000)
/* priority register */
#define PRIORITY_REG(base) ((ulong)(base) + PLICSW_PRIORITY_BASE)
-#define ENABLE_HART_IPI (0x01010101)
-#define SEND_IPI_TO_HART(hart) (0x1 << (hart))
+/* Bit 0 of PLIC-SW pending array is hardwired to zero, so we start from bit 1 */
#define PLICSW_PRIORITY_BASE 0x4
-#define PLICSW_INTERRUPT_PER_HART 0x8
DECLARE_GLOBAL_DATA_PTR;
static int enable_ipi(int hart)
{
- unsigned int en;
+ u32 enable_bit = (hart + 1) % 32;
- en = ENABLE_HART_IPI << hart;
- writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart));
- writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw + 0x4, hart));
+ writel(BIT(enable_bit), (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart));
return 0;
}
static void init_priority_ipi(int hart_num)
{
- uint32_t *priority = (void *)PRIORITY_REG(gd->arch.plicsw);
+ u32 *priority = (void *)PRIORITY_REG(gd->arch.plicsw);
- for (int i = 0; i < hart_num * PLICSW_INTERRUPT_PER_HART; i++) {
- writel(1, &priority[i]);
- }
+ for (int i = 0; i < hart_num; i++)
+ writel(1, &priority[i]);
- return;
+ return;
}
int riscv_init_ipi(void)
@@ -75,7 +69,7 @@
ret = uclass_find_first_device(UCLASS_CPU, &dev);
if (ret)
return ret;
- else if (!dev)
+ if (!dev)
return -ENODEV;
ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
@@ -105,10 +99,10 @@
int riscv_send_ipi(int hart)
{
- unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
+ u32 interrupt_id = hart + 1;
+ u32 pending_bit = interrupt_id % 32;
- writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plicsw,
- gd->arch.boot_hart));
+ writel(BIT(pending_bit), (void __iomem *)PENDING_REG(gd->arch.plicsw, hart));
return 0;
}
@@ -125,11 +119,11 @@
int riscv_get_ipi(int hart, int *pending)
{
- unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
+ u32 interrupt_id = hart + 1;
+ u32 pending_bit = interrupt_id % 32;
- *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw,
- gd->arch.boot_hart));
- *pending = !!(*pending & ipi);
+ *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw, hart));
+ *pending = !!(*pending & BIT(pending_bit));
return 0;
}
diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
index 452dfce..875bb9a 100644
--- a/arch/riscv/lib/asm-offsets.c
+++ b/arch/riscv/lib/asm-offsets.c
@@ -8,7 +8,6 @@
* assembly language modules.
*/
-#include <common.h>
#include <asm/global_data.h>
#include <linux/kbuild.h>
diff --git a/arch/riscv/lib/boot.c b/arch/riscv/lib/boot.c
index 778d011..03014c5 100644
--- a/arch/riscv/lib/boot.c
+++ b/arch/riscv/lib/boot.c
@@ -4,8 +4,7 @@
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
*/
-#include <common.h>
-#include <command.h>
+#include <asm/u-boot.h>
unsigned long do_go_exec(ulong (*entry)(int, char * const []),
int argc, char *const argv[])
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index 276677a..f9e1e18 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -6,7 +6,6 @@
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
*/
-#include <common.h>
#include <bootstage.h>
#include <command.h>
#include <dm.h>
@@ -42,7 +41,7 @@
#ifdef CONFIG_BOOTSTAGE_FDT
bootstage_fdt_add_report();
#endif
-#ifdef CONFIG_BOOTSTAGE_REPORT
+#if CONFIG_IS_ENABLED(BOOTSTAGE_REPORT)
bootstage_report();
#endif
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
index 686e699..afad7e1 100644
--- a/arch/riscv/lib/cache.c
+++ b/arch/riscv/lib/cache.c
@@ -4,7 +4,6 @@
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
*/
-#include <common.h>
#include <cpu_func.h>
void invalidate_icache_all(void)
@@ -20,7 +19,7 @@
{
}
-void invalidate_icache_range(unsigned long start, unsigned long end)
+__weak void invalidate_icache_range(unsigned long start, unsigned long end)
{
/*
* RISC-V does not have an instruction for invalidating parts of the
diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c
index 36c16e9..c658e72 100644
--- a/arch/riscv/lib/fdt_fixup.c
+++ b/arch/riscv/lib/fdt_fixup.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY LOGC_ARCH
-#include <common.h>
#include <fdt_support.h>
#include <log.h>
#include <mapmem.h>
diff --git a/arch/riscv/lib/image.c b/arch/riscv/lib/image.c
index a65a5b8d..a82f48e 100644
--- a/arch/riscv/lib/image.c
+++ b/arch/riscv/lib/image.c
@@ -6,7 +6,6 @@
* Based on arm/lib/image.c
*/
-#include <common.h>
#include <image.h>
#include <mapmem.h>
#include <errno.h>
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index e966afa..a26ccc7 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -10,9 +10,9 @@
*/
#include <linux/compat.h>
-#include <common.h>
#include <efi_loader.h>
#include <hang.h>
+#include <interrupt.h>
#include <irq_func.h>
#include <asm/global_data.h>
#include <asm/ptrace.h>
@@ -22,6 +22,13 @@
DECLARE_GLOBAL_DATA_PTR;
+static struct resume_data *resume;
+
+void set_resume(struct resume_data *data)
+{
+ resume = data;
+}
+
static void show_efi_loaded_images(uintptr_t epc)
{
efi_print_image_infos((void *)epc);
@@ -106,6 +113,11 @@
"Store/AMO page fault",
};
+ if (resume) {
+ resume->code = code;
+ longjmp(resume->jump, 1);
+ }
+
if (code < ARRAY_SIZE(exception_code))
printf("Unhandled exception: %s\n", exception_code[code]);
else
diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c
index 8779c61..712e1bd 100644
--- a/arch/riscv/lib/reset.c
+++ b/arch/riscv/lib/reset.c
@@ -3,7 +3,6 @@
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
*/
-#include <common.h>
#include <command.h>
#include <hang.h>
diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c
index 55a3bc3..35a7d3b 100644
--- a/arch/riscv/lib/sbi.c
+++ b/arch/riscv/lib/sbi.c
@@ -7,7 +7,7 @@
* Taken from Linux arch/riscv/kernel/sbi.c
*/
-#include <common.h>
+#include <errno.h>
#include <asm/encoding.h>
#include <asm/sbi.h>
diff --git a/arch/riscv/lib/sbi_ipi.c b/arch/riscv/lib/sbi_ipi.c
index d02e2b4..511d381 100644
--- a/arch/riscv/lib/sbi_ipi.c
+++ b/arch/riscv/lib/sbi_ipi.c
@@ -4,7 +4,6 @@
* Lukas Auer <lukas.auer@aisec.fraunhofer.de>
*/
-#include <common.h>
#include <asm/encoding.h>
#include <asm/sbi.h>
diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c
index 2815487..39b0248 100644
--- a/arch/riscv/lib/sifive_cache.c
+++ b/arch/riscv/lib/sifive_cache.c
@@ -3,9 +3,9 @@
* Copyright (C) 2021 SiFive, Inc
*/
-#include <common.h>
#include <cache.h>
#include <cpu_func.h>
+#include <log.h>
#include <dm.h>
void enable_caches(void)
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index 4f073a0..a692f06 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -4,12 +4,12 @@
* Lukas Auer <lukas.auer@aisec.fraunhofer.de>
*/
-#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <asm/barrier.h>
#include <asm/global_data.h>
#include <asm/smp.h>
+#include <linux/printk.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c
index f4d3b67..9a7a4f6 100644
--- a/arch/riscv/lib/spl.c
+++ b/arch/riscv/lib/spl.c
@@ -3,7 +3,6 @@
* Copyright (C) 2019 Fraunhofer AISEC,
* Lukas Auer <lukas.auer@aisec.fraunhofer.de>
*/
-#include <common.h>
#include <cpu_func.h>
#include <hang.h>
#include <init.h>
@@ -28,7 +27,7 @@
if (ret)
panic("spl_early_init() failed: %d\n", ret);
- riscv_cpu_setup(NULL, NULL);
+ riscv_cpu_setup();
preloader_console_init();
diff --git a/arch/riscv/lib/strcmp_zbb.S b/arch/riscv/lib/strcmp_zbb.S
new file mode 100644
index 0000000..e5a367c
--- /dev/null
+++ b/arch/riscv/lib/strcmp_zbb.S
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Taken from Linux arch/riscv/lib/strcmp.S
+ */
+
+#include <linux/linkage.h>
+#include <asm/asm.h>
+
+ENTRY(__strcmp)
+WEAK(strcmp)
+.option push
+.option arch,+zbb
+ /*
+ * Returns
+ * a0 - comparison result, value like strcmp
+ *
+ * Parameters
+ * a0 - string1
+ * a1 - string2
+ *
+ * Clobbers
+ * t0, t1, t2, t3, t4
+ */
+
+ or t2, a0, a1
+ li t4, -1
+ and t2, t2, SZREG-1
+ bnez t2, 3f
+
+ /* Main loop for aligned string. */
+ .p2align 3
+1:
+ REG_L t0, 0(a0)
+ REG_L t1, 0(a1)
+ orc.b t3, t0
+ bne t3, t4, 2f
+ addi a0, a0, SZREG
+ addi a1, a1, SZREG
+ beq t0, t1, 1b
+
+ /*
+ * Words don't match, and no null byte in the first
+ * word. Get bytes in big-endian order and compare.
+ */
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+ rev8 t0, t0
+ rev8 t1, t1
+#endif
+
+ /* Synthesize (t0 >= t1) ? 1 : -1 in a branchless sequence. */
+ sltu a0, t0, t1
+ neg a0, a0
+ ori a0, a0, 1
+ ret
+
+2:
+ /*
+ * Found a null byte.
+ * If words don't match, fall back to simple loop.
+ */
+ bne t0, t1, 3f
+
+ /* Otherwise, strings are equal. */
+ li a0, 0
+ ret
+
+ /* Simple loop for misaligned strings. */
+ .p2align 3
+3:
+ lbu t0, 0(a0)
+ lbu t1, 0(a1)
+ addi a0, a0, 1
+ addi a1, a1, 1
+ bne t0, t1, 4f
+ bnez t0, 3b
+
+4:
+ sub a0, t0, t1
+ ret
+.option pop
+END(__strcmp)
diff --git a/arch/riscv/lib/strlen_zbb.S b/arch/riscv/lib/strlen_zbb.S
new file mode 100644
index 0000000..bd8fa4c
--- /dev/null
+++ b/arch/riscv/lib/strlen_zbb.S
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Taken from Linux arch/riscv/lib/strlen.S
+ */
+
+#include <linux/linkage.h>
+#include <asm/asm.h>
+
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+# define CZ ctz
+# define SHIFT srl
+#else
+# define CZ clz
+# define SHIFT sll
+#endif
+
+ENTRY(__strlen)
+WEAK(strlen)
+.option push
+.option arch,+zbb
+ /*
+ * Returns
+ * a0 - string length
+ *
+ * Parameters
+ * a0 - String to measure
+ *
+ * Clobbers
+ * t0, t1, t2, t3
+ */
+
+ /* Number of irrelevant bytes in the first word. */
+ andi t2, a0, SZREG-1
+
+ /* Align pointer. */
+ andi t0, a0, -SZREG
+
+ li t3, SZREG
+ sub t3, t3, t2
+ slli t2, t2, 3
+
+ /* Get the first word. */
+ REG_L t1, 0(t0)
+
+ /*
+ * Shift away the partial data we loaded to remove the irrelevant bytes
+ * preceding the string with the effect of adding NUL bytes at the
+ * end of the string's first word.
+ */
+ SHIFT t1, t1, t2
+
+ /* Convert non-NUL into 0xff and NUL into 0x00. */
+ orc.b t1, t1
+
+ /* Convert non-NUL into 0x00 and NUL into 0xff. */
+ not t1, t1
+
+ /*
+ * Search for the first set bit (corresponding to a NUL byte in the
+ * original chunk).
+ */
+ CZ t1, t1
+
+ /*
+ * The first chunk is special: compare against the number
+ * of valid bytes in this chunk.
+ */
+ srli a0, t1, 3
+ bgtu t3, a0, 2f
+
+ /* Prepare for the word comparison loop. */
+ addi t2, t0, SZREG
+ li t3, -1
+
+ /*
+ * Our critical loop is 4 instructions and processes data in
+ * 4 byte or 8 byte chunks.
+ */
+ .p2align 3
+1:
+ REG_L t1, SZREG(t0)
+ addi t0, t0, SZREG
+ orc.b t1, t1
+ beq t1, t3, 1b
+
+ not t1, t1
+ CZ t1, t1
+ srli t1, t1, 3
+
+ /* Get number of processed bytes. */
+ sub t2, t0, t2
+
+ /* Add number of characters in the first word. */
+ add a0, a0, t2
+
+ /* Add number of characters in the last word. */
+ add a0, a0, t1
+2:
+ ret
+.option pop
+END(__strlen)
diff --git a/arch/riscv/lib/strncmp_zbb.S b/arch/riscv/lib/strncmp_zbb.S
new file mode 100644
index 0000000..00e0fec
--- /dev/null
+++ b/arch/riscv/lib/strncmp_zbb.S
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Taken from Linux arch/riscv/lib/strncmp.S
+ */
+
+#include <linux/linkage.h>
+#include <asm/asm.h>
+
+ENTRY(__strncmp)
+WEAK(strncmp)
+.option push
+.option arch,+zbb
+ /*
+ * Returns
+ * a0 - comparison result, like strncmp
+ *
+ * Parameters
+ * a0 - string1
+ * a1 - string2
+ * a2 - number of characters to compare
+ *
+ * Clobbers
+ * t0, t1, t2, t3, t4, t5, t6
+ */
+
+ or t2, a0, a1
+ li t5, -1
+ and t2, t2, SZREG-1
+ add t4, a0, a2
+ bnez t2, 3f
+
+ /* Adjust limit for fast-path. */
+ andi t6, t4, -SZREG
+
+ /* Main loop for aligned string. */
+ .p2align 3
+1:
+ bge a0, t6, 3f
+ REG_L t0, 0(a0)
+ REG_L t1, 0(a1)
+ orc.b t3, t0
+ bne t3, t5, 2f
+ orc.b t3, t1
+ bne t3, t5, 2f
+ addi a0, a0, SZREG
+ addi a1, a1, SZREG
+ beq t0, t1, 1b
+
+ /*
+ * Words don't match, and no null byte in the first
+ * word. Get bytes in big-endian order and compare.
+ */
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+ rev8 t0, t0
+ rev8 t1, t1
+#endif
+
+ /* Synthesize (t0 >= t1) ? 1 : -1 in a branchless sequence. */
+ sltu a0, t0, t1
+ neg a0, a0
+ ori a0, a0, 1
+ ret
+
+2:
+ /*
+ * Found a null byte.
+ * If words don't match, fall back to simple loop.
+ */
+ bne t0, t1, 3f
+
+ /* Otherwise, strings are equal. */
+ li a0, 0
+ ret
+
+ /* Simple loop for misaligned strings. */
+ .p2align 3
+3:
+ bge a0, t4, 5f
+ lbu t0, 0(a0)
+ lbu t1, 0(a1)
+ addi a0, a0, 1
+ addi a1, a1, 1
+ bne t0, t1, 4f
+ bnez t0, 3b
+
+4:
+ sub a0, t0, t1
+ ret
+
+5:
+ li a0, 0
+ ret
+.option pop
+END(__strncmp)
diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk
index 2d184c5..1d50991 100644
--- a/arch/sandbox/config.mk
+++ b/arch/sandbox/config.mk
@@ -2,7 +2,7 @@
# Copyright (c) 2011 The Chromium OS Authors.
PLATFORM_CPPFLAGS += -D__SANDBOX__ -U_FORTIFY_SOURCE
-PLATFORM_CPPFLAGS += -fPIC
+PLATFORM_CPPFLAGS += -fPIC -ffunction-sections -fdata-sections
PLATFORM_LIBS += -lrt
SDL_CONFIG ?= sdl2-config
@@ -30,7 +30,7 @@
$(u-boot-main) \
$(u-boot-keep-syms-lto) \
-Wl,--no-whole-archive \
- $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map
+ $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map -Wl,--gc-sections
cmd_u-boot-spl = (cd $(obj) && $(CC) -o $(SPL_BIN) -Wl,-T u-boot-spl.lds \
$(KBUILD_LDFLAGS:%=-Wl,%) \
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 9e93a0f..95c26d8 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -219,7 +219,7 @@
{
void *ptr;
off_t size;
- int ifd;
+ int ifd, ret = 0;
ifd = os_open(pathname, os_flags);
if (ifd < 0) {
@@ -229,23 +229,28 @@
size = os_filesize(ifd);
if (size < 0) {
printf("Cannot get file size of '%s'\n", pathname);
- return -EIO;
+ ret = -EIO;
+ goto out;
}
if ((unsigned long long)size > (unsigned long long)SIZE_MAX) {
printf("File '%s' too large to map\n", pathname);
- return -EIO;
+ ret = -EIO;
+ goto out;
}
ptr = mmap(0, size, PROT_READ | PROT_WRITE, MAP_SHARED, ifd, 0);
if (ptr == MAP_FAILED) {
printf("Can't map file '%s': %s\n", pathname, strerror(errno));
- return -EPERM;
+ ret = -EPERM;
+ goto out;
}
*bufp = ptr;
*sizep = size;
- return 0;
+out:
+ os_close(ifd);
+ return ret;
}
int os_unmap(void *buf, int size)
@@ -258,6 +263,30 @@
return 0;
}
+int os_persistent_file(char *buf, int maxsize, const char *fname)
+{
+ const char *dirname = getenv("U_BOOT_PERSISTENT_DATA_DIR");
+ char *ptr;
+ int len;
+
+ len = strlen(fname) + (dirname ? strlen(dirname) + 1 : 0) + 1;
+ if (len > maxsize)
+ return -ENOSPC;
+
+ ptr = buf;
+ if (dirname) {
+ strcpy(ptr, dirname);
+ ptr += strlen(dirname);
+ *ptr++ = '/';
+ }
+ strcpy(ptr, fname);
+
+ if (access(buf, F_OK) == -1)
+ return -ENOENT;
+
+ return 0;
+}
+
/* Restore tty state when we exit */
static struct termios orig_term;
static bool term_setup;
diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c
index 09e3d10..16b7662 100644
--- a/arch/sandbox/cpu/spl.c
+++ b/arch/sandbox/cpu/spl.c
@@ -126,6 +126,13 @@
{
struct sandbox_state *state = state_get_current();
+ if (!CONFIG_IS_ENABLED(UNIT_TEST))
+ return;
+
+ /* These are necessary so TFTP can use LMBs to check its load address */
+ gd->bd->bi_dram[0].start = gd->ram_base;
+ gd->bd->bi_dram[0].size = get_effective_memsize();
+
if (state->run_unittests) {
struct unit_test *tests = UNIT_TEST_ALL_START();
const int count = UNIT_TEST_ALL_COUNT();
diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index 2346528..2589c2e 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -13,6 +13,7 @@
#include <log.h>
#include <os.h>
#include <sort.h>
+#include <spl.h>
#include <asm/getopt.h>
#include <asm/global_data.h>
#include <asm/io.h>
@@ -119,12 +120,7 @@
os_exit(0);
}
-
-static int sandbox_misc_init_f(void *ctx, struct event *event)
-{
- return sandbox_early_getopt_check();
-}
-EVENT_SPY(EVT_MISC_INIT_F, sandbox_misc_init_f);
+EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, sandbox_early_getopt_check);
static int sandbox_cmdline_cb_help(struct sandbox_state *state, const char *arg)
{
@@ -207,10 +203,14 @@
{
char buf[256];
char *fname;
+ char *relname;
int len;
- len = state_get_rel_filename("arch/sandbox/dts/test.dtb", buf,
- sizeof(buf));
+ if (spl_phase() <= PHASE_SPL)
+ relname = "../arch/sandbox/dts/test.dtb";
+ else
+ relname = "arch/sandbox/dts/test.dtb";
+ len = state_get_rel_filename(relname, buf, sizeof(buf));
if (len < 0)
return len;
@@ -277,17 +277,9 @@
static int sandbox_cmdline_cb_memory(struct sandbox_state *state,
const char *arg)
{
- int err;
-
/* For now assume we always want to write it */
state->write_ram_buf = true;
state->ram_buf_fname = arg;
-
- err = os_read_ram_buf(arg);
- if (err) {
- printf("Failed to read RAM buffer '%s': %d\n", arg, err);
- return err;
- }
state->ram_buf_read = true;
return 0;
@@ -517,6 +509,17 @@
if (os_parse_args(state, argc, argv))
return 1;
+ if (state->ram_buf_fname) {
+ ret = os_read_ram_buf(state->ram_buf_fname);
+ if (ret) {
+ printf("Failed to read RAM buffer '%s': %d\n",
+ state->ram_buf_fname, ret);
+ } else {
+ state->ram_buf_read = true;
+ log_debug("Read RAM buffer from '%s'\n", state->ram_buf_fname);
+ }
+ }
+
/* Remove old memory file if required */
if (state->ram_buf_rm && state->ram_buf_fname) {
os_unlink(state->ram_buf_fname);
@@ -524,9 +527,11 @@
state->ram_buf_fname = NULL;
}
- ret = sandbox_read_state(state, state->state_fname);
- if (ret)
- goto err;
+ if (state->read_state && state->state_fname) {
+ ret = sandbox_read_state(state, state->state_fname);
+ if (ret)
+ goto err;
+ }
if (state->handle_signals) {
ret = os_setup_signal_handlers();
@@ -534,7 +539,7 @@
goto err;
}
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
gd->malloc_base = CFG_MALLOC_F_ADDR;
#endif
#if CONFIG_IS_ENABLED(LOG)
diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c
index d678349..e38bb24 100644
--- a/arch/sandbox/cpu/state.c
+++ b/arch/sandbox/cpu/state.c
@@ -513,6 +513,7 @@
printf("Failed to write RAM buffer\n");
return err;
}
+ log_debug("Wrote RAM to file '%s'\n", state->ram_buf_fname);
}
if (state->write_state) {
@@ -520,6 +521,7 @@
printf("Failed to write sandbox state\n");
return -1;
}
+ log_debug("Wrote state to file '%s'\n", state->ram_buf_fname);
}
/* Delete this at the last moment so as not to upset gdb too much */
diff --git a/arch/sandbox/cpu/u-boot-spl.lds b/arch/sandbox/cpu/u-boot-spl.lds
index ef885fd..a81d66a 100644
--- a/arch/sandbox/cpu/u-boot-spl.lds
+++ b/arch/sandbox/cpu/u-boot-spl.lds
@@ -26,6 +26,8 @@
KEEP(*(_u_boot_sandbox_getopt))
*(_u_boot_sandbox_getopt_end)
}
+
+ _image_binary_end = .;
}
INSERT AFTER .data;
diff --git a/arch/sandbox/cpu/u-boot.lds b/arch/sandbox/cpu/u-boot.lds
index ba8dee5..52f13af 100644
--- a/arch/sandbox/cpu/u-boot.lds
+++ b/arch/sandbox/cpu/u-boot.lds
@@ -15,7 +15,7 @@
_u_boot_sandbox_getopt : {
*(_u_boot_sandbox_getopt_start)
- *(_u_boot_sandbox_getopt)
+ KEEP(*(_u_boot_sandbox_getopt))
*(_u_boot_sandbox_getopt_end)
}
diff --git a/arch/sandbox/dts/cedit.dtsi b/arch/sandbox/dts/cedit.dtsi
index a9eb4c2..9bd84e6 100644
--- a/arch/sandbox/dts/cedit.dtsi
+++ b/arch/sandbox/dts/cedit.dtsi
@@ -51,6 +51,14 @@
item-id = <ID_AC_OFF ID_AC_ON ID_AC_MEMORY>;
};
+
+ machine-name {
+ id = <ID_MACHINE_NAME>;
+ type = "textline";
+ max-chars = <20>;
+ title = "Machine name";
+ edit-id = <ID_MACHINE_NAME_EDIT>;
+ };
};
};
diff --git a/arch/sandbox/dts/overlay0.dts b/arch/sandbox/dts/overlay0.dtso
similarity index 100%
rename from arch/sandbox/dts/overlay0.dts
rename to arch/sandbox/dts/overlay0.dtso
diff --git a/arch/sandbox/dts/overlay1.dts b/arch/sandbox/dts/overlay1.dtso
similarity index 100%
rename from arch/sandbox/dts/overlay1.dts
rename to arch/sandbox/dts/overlay1.dtso
diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi
index 8aaf911..241f397 100644
--- a/arch/sandbox/dts/sandbox.dtsi
+++ b/arch/sandbox/dts/sandbox.dtsi
@@ -4,11 +4,23 @@
* and sandbox64 builds.
*/
+#include <config.h>
#include <dt-bindings/input/input.h>
#define USB_CLASS_HUB 9
/ {
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ event_log: tcg_event_log {
+ no-map;
+ reg = <(CFG_SYS_SDRAM_SIZE - 0x2000) 0x2000>;
+ };
+ };
+
binman {
};
@@ -16,12 +28,6 @@
stdout-path = "/serial";
};
- cedit-theme {
- font-size = <30>;
- menu-inset = <3>;
- menuitem-gap-y = <1>;
- };
-
alarm_wdt: alarm-wdt {
compatible = "sandbox,alarm-wdt";
timeout-sec = <5>;
@@ -36,6 +42,12 @@
bootstd {
compatible = "u-boot,boot-std";
filename-prefixes = "./";
+
+ cedit-theme {
+ font-size = <30>;
+ menu-inset = <3>;
+ menuitem-gap-y = <1>;
+ };
};
buttons {
@@ -342,6 +354,7 @@
tpm2 {
compatible = "sandbox,tpm2";
+ memory-region = <&event_log>;
};
triangle {
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 057e1ca..a3a865d 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -9,6 +9,7 @@
/dts-v1/;
+#include <config.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/sandbox-gpio.h>
#include <dt-bindings/input/input.h>
@@ -39,6 +40,9 @@
mmc1 = "/mmc1";
mmc2 = "/mmc2";
mmc3 = "/mmc3";
+ mmc4 = "/mmc4";
+ mmc5 = "/mmc5";
+ mmc6 = "/mmc6";
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
@@ -66,6 +70,17 @@
osd0 = "/osd";
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ event_log: tcg_event_log {
+ no-map;
+ reg = <(CFG_SYS_SDRAM_SIZE - 0x2000) 0x2000>;
+ };
+ };
+
binman: binman {
};
@@ -79,6 +94,15 @@
};
};
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ bootscr-ram-offset = /bits/ 64 <0x12345678>;
+ bootscr-flash-offset = /bits/ 64 <0>;
+ bootscr-flash-size = /bits/ 64 <0x2000>;
+ };
+ };
+
bootstd {
bootph-verify;
compatible = "u-boot,boot-std";
@@ -100,6 +124,12 @@
menuitem-gap-y = <1>;
};
+ cedit-theme {
+ font-size = <30>;
+ menu-inset = <3>;
+ menuitem-gap-y = <1>;
+ };
+
/*
* This is used for the VBE OS-request tests. A FAT filesystem
* created in a partition with the VBE information appearing
@@ -144,12 +174,6 @@
cedit: cedit {
};
- cedit-theme {
- font-size = <30>;
- menu-inset = <3>;
- menuitem-gap-y = <1>;
- };
-
fuzzing-engine {
compatible = "sandbox,fuzzing-engine";
};
@@ -299,6 +323,7 @@
uint-value = <(-1234)>;
int64-value = /bits/ 64 <0x1111222233334444>;
int-array = <5678 9123 4567>;
+ int64-array = /bits/ 64 <0x1111222233334444 0x4444333322221111>;
str-value = "test string";
interrupts-extended = <&irq 3 0>;
acpi,name = "GHIJ";
@@ -431,6 +456,11 @@
#phy-cells = <0>;
};
+ phy_provider3: gen_phy@3 {
+ compatible = "sandbox,phy";
+ #phy-cells = <2>;
+ };
+
gen_phy_user: gen_phy_user {
compatible = "simple-bus";
phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
@@ -443,6 +473,12 @@
phy-names = "phy1", "phy2";
};
+ gen_phy_user2: gen_phy_user2 {
+ compatible = "simple-bus";
+ phys = <&phy_provider3 0 0>;
+ phy-names = "phy1";
+ };
+
some-bus {
#address-cells = <1>;
#size-cells = <0>;
@@ -595,13 +631,31 @@
clocks = <&clk_fixed>,
<&clk_sandbox 1>,
<&clk_sandbox 0>,
+ <&ccf 11>,
<&clk_sandbox 3>,
<&clk_sandbox 2>;
- clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
+ clock-names = "fixed", "i2c", "spi", "i2c_root", "uart2", "uart1";
+ };
+
+ clk-test2 {
+ compatible = "sandbox,clk-test";
+ assigned-clock-rates = <321>;
+ };
+
+ clk-test3 {
+ compatible = "sandbox,clk-test";
+ assigned-clocks = <&clk_sandbox 1>;
+ };
+
+ clk-test4 {
+ compatible = "sandbox,clk-test";
+ assigned-clock-rates = <654>, <321>;
+ assigned-clocks = <&clk_sandbox 1>;
};
ccf: clk-ccf {
compatible = "sandbox,clk-ccf";
+ #clock-cells = <1>;
};
efi-media {
@@ -693,13 +747,15 @@
#address-cells = <1>;
#size-cells = <0>;
- protocol@10 {
- reg = <0x10>;
+ pwrdom_scmi: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
};
clk_scmi: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
+ linaro,sandbox-channel-id = <0x14>;
};
reset_scmi: protocol@16 {
@@ -728,6 +784,10 @@
};
};
};
+
+ sm: secure-monitor {
+ compatible = "sandbox,sm";
+ };
};
fpga {
@@ -935,7 +995,7 @@
};
wdt-gpio-toggle {
- gpios = <&gpio_a 7 0>;
+ gpios = <&gpio_a 8 0>;
compatible = "linux,wdt-gpio";
hw_margin_ms = <100>;
hw_algo = "toggle";
@@ -1055,6 +1115,20 @@
filename = "mmc4.img";
};
+ /* This is used for ChromiumOS tests */
+ mmc5 {
+ status = "disabled";
+ compatible = "sandbox,mmc";
+ filename = "mmc5.img";
+ };
+
+ /* This is used for mbr tests */
+ mmc6 {
+ status = "disabled";
+ compatible = "sandbox,mmc";
+ filename = "mmc6.img";
+ };
+
pch {
compatible = "sandbox,pch";
};
@@ -1077,8 +1151,8 @@
pci@1,0 {
compatible = "pci-generic";
/* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
- reg = <0x02000814 0 0 0 0
- 0x01000810 0 0 0 0>;
+ reg = <0x02000814 0 0 0x80 0
+ 0x01000810 0 0 0xc0 0>;
sandbox,emul = <&swap_case_emul0_1>;
};
p2sb-pci@2,0 {
@@ -1105,7 +1179,7 @@
pci@1f,0 {
compatible = "pci-generic";
/* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
- reg = <0x0100f810 0 0 0 0>;
+ reg = <0x0100f810 0 0 0x100 0>;
sandbox,emul = <&swap_case_emul0_1f>;
};
};
@@ -1376,6 +1450,7 @@
tpm2 {
compatible = "sandbox,tpm2";
+ memory-region = <&event_log>;
};
tpm {
@@ -1499,6 +1574,7 @@
other-node = "/some-bus/c-test@5";
int-values = <0x1937 72993>;
u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
+ stdout-path = "serial0:115200n8";
chosen-test {
compatible = "denx,u-boot-fdt-test";
reg = <9 1>;
@@ -1592,6 +1668,7 @@
sandbox_scmi {
compatible = "sandbox,scmi-devices";
+ power-domains = <&pwrdom_scmi 2>;
clocks = <&clk_scmi 2>, <&clk_scmi 0>;
resets = <&reset_scmi 3>;
regul0-supply = <®ul0_scmi>;
diff --git a/arch/sandbox/include/asm/clk.h b/arch/sandbox/include/asm/clk.h
index df7156f..1daf2e7 100644
--- a/arch/sandbox/include/asm/clk.h
+++ b/arch/sandbox/include/asm/clk.h
@@ -39,6 +39,7 @@
SANDBOX_CLK_TEST_ID_FIXED,
SANDBOX_CLK_TEST_ID_SPI,
SANDBOX_CLK_TEST_ID_I2C,
+ SANDBOX_CLK_TEST_ID_I2C_ROOT,
SANDBOX_CLK_TEST_ID_DEVM1,
SANDBOX_CLK_TEST_ID_DEVM2,
SANDBOX_CLK_TEST_ID_DEVM_NULL,
diff --git a/arch/sandbox/include/asm/global_data.h b/arch/sandbox/include/asm/global_data.h
index f0ab3ba..c697773 100644
--- a/arch/sandbox/include/asm/global_data.h
+++ b/arch/sandbox/include/asm/global_data.h
@@ -17,6 +17,7 @@
ulong table_end; /* End address of x86 tables */
ulong table_start_high; /* Start address of high x86 tables */
ulong table_end_high; /* End address of high x86 tables */
+ ulong smbios_start; /* Start address of SMBIOS table */
};
#include <asm-generic/global_data.h>
diff --git a/arch/sandbox/include/asm/scmi_test.h b/arch/sandbox/include/asm/scmi_test.h
index c72ec1e..619f8f5 100644
--- a/arch/sandbox/include/asm/scmi_test.h
+++ b/arch/sandbox/include/asm/scmi_test.h
@@ -6,11 +6,23 @@
#ifndef __SANDBOX_SCMI_TEST_H
#define __SANDBOX_SCMI_TEST_H
+#include <power-domain.h>
+
struct udevice;
struct sandbox_scmi_agent;
struct sandbox_scmi_service;
/**
+ * struct sandbox_scmi_pwd
+ * @id: Identifier of the power domain used in the SCMI protocol
+ * @pstate:: Power state of the domain
+ */
+struct sandbox_scmi_pwd {
+ uint id;
+ u32 pstate;
+};
+
+/**
* struct sandbox_scmi_clk - Simulated clock exposed by SCMI
* @id: Identifier of the clock used in the SCMI protocol
* @enabled: Clock state: true if enabled, false if disabled
@@ -45,6 +57,8 @@
/**
* struct sandbox_scmi_agent - Simulated SCMI service seen by SCMI agent
+ * @pwdom_version: Implemented power domain protocol version
+ * @pwdom_count: Simulated power domains array size
* @clk: Simulated clocks
* @clk_count: Simulated clocks array size
* @reset: Simulated reset domains
@@ -53,6 +67,9 @@
* @voltd_count: Simulated voltage domains array size
*/
struct sandbox_scmi_agent {
+ int pwdom_version;
+ struct sandbox_scmi_pwd *pwdom;
+ size_t pwdom_count;
struct sandbox_scmi_clk *clk;
size_t clk_count;
struct sandbox_scmi_reset *reset;
@@ -71,6 +88,8 @@
/**
* struct sandbox_scmi_devices - Reference to devices probed through SCMI
+ * @pwdom: Array of power domains
+ * @pwdom_count: Number of power domains probed
* @clk: Array the clock devices
* @clk_count: Number of clock devices probed
* @reset: Array the reset controller devices
@@ -79,6 +98,8 @@
* @regul_count: Number of regulator devices probed
*/
struct sandbox_scmi_devices {
+ struct power_domain *pwdom;
+ size_t pwdom_count;
struct clk *clk;
size_t clk_count;
struct reset_ctl *reset;
@@ -89,10 +110,20 @@
#ifdef CONFIG_SCMI_FIRMWARE
/**
+ * sandbox_scmi_channel_id - Get the channel id
+ * @dev: Reference to the SCMI protocol device
+ *
+ * Return: Channel id
+ */
+unsigned int sandbox_scmi_channel_id(struct udevice *dev);
+
+/**
* sandbox_scmi_service_ctx - Get the simulated SCMI services context
+ * sandbox_scmi_agent_ctx - Get the simulated SCMI agent context
+ * @dev: Reference to the test agent
* @return: Reference to backend simulated resources state
*/
-struct sandbox_scmi_service *sandbox_scmi_service_ctx(void);
+struct sandbox_scmi_agent *sandbox_scmi_agent_ctx(struct udevice *dev);
/**
* sandbox_scmi_devices_ctx - Get references to devices accessed through SCMI
@@ -101,7 +132,12 @@
*/
struct sandbox_scmi_devices *sandbox_scmi_devices_ctx(struct udevice *dev);
#else
-static inline struct sandbox_scmi_service *sandbox_scmi_service_ctx(void)
+inline unsigned int sandbox_scmi_channel_id(struct udevice *dev);
+{
+ return 0;
+}
+
+static struct sandbox_scmi_agent *sandbox_scmi_agent_ctx(struct udevice *dev)
{
return NULL;
}
diff --git a/arch/sandbox/include/asm/spl.h b/arch/sandbox/include/asm/spl.h
index 2f8b5fc..f349ea1 100644
--- a/arch/sandbox/include/asm/spl.h
+++ b/arch/sandbox/include/asm/spl.h
@@ -12,6 +12,9 @@
BOOT_DEVICE_MMC2_2,
BOOT_DEVICE_BOARD,
BOOT_DEVICE_VBE,
+ BOOT_DEVICE_CPGMAC,
+ BOOT_DEVICE_NOR,
+ BOOT_DEVICE_SPI,
};
/**
diff --git a/arch/sh/lib/start.S b/arch/sh/lib/start.S
index ddb9aa9..f0e1c80 100644
--- a/arch/sh/lib/start.S
+++ b/arch/sh/lib/start.S
@@ -53,7 +53,7 @@
mov.l ._gd_init, r13 /* global data */
mov.l ._stack_init, r15 /* stack */
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
mov.l ._gd_malloc_base, r14
mov.l r15, @r14
#endif
@@ -73,7 +73,7 @@
._bss_start: .long bss_start
._bss_end: .long bss_end
._gd_init: .long (_start - GENERATED_GBL_DATA_SIZE)
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
._gd_malloc_base: .long (_start - GENERATED_GBL_DATA_SIZE + GD_MALLOC_BASE)
#endif
._stack_init: .long (_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
diff --git a/arch/x86/cpu/apollolake/acpi.c b/arch/x86/cpu/apollolake/acpi.c
index fd21c0b..c610a7f 100644
--- a/arch/x86/cpu/apollolake/acpi.c
+++ b/arch/x86/cpu/apollolake/acpi.c
@@ -146,16 +146,21 @@
fadt->x_pm_tmr_blk.addrl = IOMAP_ACPI_BASE + PM1_TMR;
}
-void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
- void *dsdt)
+static int apl_write_fadt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
{
- struct acpi_table_header *header = &fadt->header;
+ struct acpi_table_header *header;
+ struct acpi_fadt *fadt;
- acpi_fadt_common(fadt, facs, dsdt);
+ fadt = ctx->current;
+ acpi_fadt_common(fadt, ctx->facs, ctx->dsdt);
intel_acpi_fill_fadt(fadt);
fill_fadt(fadt);
+ header = &fadt->header;
header->checksum = table_compute_checksum(fadt, header->length);
+
+ return acpi_add_fadt(ctx, fadt);
}
+ACPI_WRITER(5fadt, "FADT", apl_write_fadt, 0);
int apl_acpi_fill_dmar(struct acpi_ctx *ctx)
{
diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c
index 07757b8..4378846 100644
--- a/arch/x86/cpu/baytrail/acpi.c
+++ b/arch/x86/cpu/baytrail/acpi.c
@@ -15,20 +15,24 @@
#include <asm/arch/iomap.h>
#include <dm/uclass-internal.h>
-void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
- void *dsdt)
+static int baytrail_write_fadt(struct acpi_ctx *ctx,
+ const struct acpi_writer *entry)
{
- struct acpi_table_header *header = &(fadt->header);
+ struct acpi_table_header *header;
+ struct acpi_fadt *fadt;
+
+ fadt = ctx->current;
+ header = &fadt->header;
u16 pmbase = ACPI_BASE_ADDRESS;
- memset((void *)fadt, 0, sizeof(struct acpi_fadt));
+ memset(fadt, '\0', sizeof(struct acpi_fadt));
acpi_fill_header(header, "FACP");
header->length = sizeof(struct acpi_fadt);
header->revision = 4;
- fadt->firmware_ctrl = (u32)facs;
- fadt->dsdt = (u32)dsdt;
+ fadt->firmware_ctrl = (u32)ctx->facs;
+ fadt->dsdt = (u32)ctx->dsdt;
fadt->preferred_pm_profile = ACPI_PM_MOBILE;
fadt->sci_int = 9;
fadt->smi_cmd = 0;
@@ -75,9 +79,9 @@
fadt->reset_reg.addrh = 0;
fadt->reset_value = SYS_RST | RST_CPU | FULL_RST;
- fadt->x_firmware_ctl_l = (u32)facs;
+ fadt->x_firmware_ctl_l = (u32)ctx->facs;
fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (u32)dsdt;
+ fadt->x_dsdt_l = (u32)ctx->dsdt;
fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
@@ -137,7 +141,10 @@
fadt->x_gpe1_blk.addrh = 0x0;
header->checksum = table_compute_checksum(fadt, header->length);
+
+ return acpi_add_fadt(ctx, fadt);
}
+ACPI_WRITER(5fadt, "FADT", baytrail_write_fadt, 0);
int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
{
diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c
index 4a7b4f6..c270426 100644
--- a/arch/x86/cpu/baytrail/cpu.c
+++ b/arch/x86/cpu/baytrail/cpu.c
@@ -45,7 +45,7 @@
* Configure the internal clock of both SIO HS-UARTs, if they are enabled
* via FSP
*/
-static int baytrail_uart_init(void *ctx, struct event *event)
+static int baytrail_uart_init(void)
{
struct udevice *dev;
void *base;
@@ -64,7 +64,7 @@
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, baytrail_uart_init);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, baytrail_uart_init);
static void set_max_freq(void)
{
diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c
index f30aebf..cbd4a3b 100644
--- a/arch/x86/cpu/broadwell/cpu.c
+++ b/arch/x86/cpu/broadwell/cpu.c
@@ -11,6 +11,7 @@
#include <event.h>
#include <init.h>
#include <log.h>
+#include <spl.h>
#include <asm/cpu.h>
#include <asm/cpu_x86.h>
#include <asm/cpu_common.h>
@@ -25,7 +26,7 @@
#include <asm/arch/pch.h>
#include <asm/arch/rcb.h>
-static int broadwell_init_cpu(void *ctx, struct event *event)
+static int broadwell_init_cpu(void)
{
struct udevice *dev;
int ret;
@@ -40,7 +41,7 @@
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, broadwell_init_cpu);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, broadwell_init_cpu);
void set_max_freq(void)
{
@@ -67,12 +68,11 @@
{
post_code(POST_CPU_INIT);
-#ifdef CONFIG_TPL
/* Do a mini-init if TPL has already done the full init */
- return x86_cpu_reinit_f();
-#else
- return x86_cpu_init_f();
-#endif
+ if (IS_ENABLED(CONFIG_TPL) && spl_phase() != PHASE_TPL)
+ return x86_cpu_reinit_f();
+ else
+ return x86_cpu_init_f();
}
int checkcpu(void)
diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c
index f477d51..d30ebee 100644
--- a/arch/x86/cpu/broadwell/sdram.c
+++ b/arch/x86/cpu/broadwell/sdram.c
@@ -5,6 +5,8 @@
* From coreboot src/soc/intel/broadwell/romstage/raminit.c
*/
+#define LOG_CATEGORY UCLASS_RAM
+
#include <common.h>
#include <dm.h>
#include <init.h>
diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig
index b97c277..178f8ad 100644
--- a/arch/x86/cpu/coreboot/Kconfig
+++ b/arch/x86/cpu/coreboot/Kconfig
@@ -25,6 +25,7 @@
imply FS_CBFS
imply CBMEM_CONSOLE
imply X86_TSC_READ_BASE
+ imply USE_PREBOOT
select BINMAN if X86_64
endif
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index d7eedbd..82fe4c7 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <cpu_func.h>
+#include <event.h>
#include <fdtdec.h>
#include <init.h>
#include <usb.h>
@@ -20,7 +21,14 @@
int arch_cpu_init(void)
{
- int ret = get_coreboot_info(&lib_sysinfo);
+ int ret;
+
+ ret = IS_ENABLED(CONFIG_X86_RUN_64BIT) ? x86_cpu_reinit_f() :
+ x86_cpu_init_f();
+ if (ret)
+ return ret;
+
+ ret = get_coreboot_info(&lib_sysinfo);
if (ret != 0) {
printf("Failed to parse coreboot tables.\n");
return ret;
@@ -28,8 +36,7 @@
timestamp_init();
- return IS_ENABLED(CONFIG_X86_RUN_64BIT) ? x86_cpu_reinit_f() :
- x86_cpu_init_f();
+ return 0;
}
int checkcpu(void)
@@ -74,13 +81,13 @@
}
}
-int last_stage_init(void)
+static int last_stage_init(void)
{
- /* start usb so that usb keyboard can be used as input device */
- if (IS_ENABLED(CONFIG_USB_KEYBOARD))
- usb_init();
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ return 0;
board_final_init();
return 0;
}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index dddd281..ce55efc 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -26,6 +26,7 @@
#include <cpu_func.h>
#include <dm.h>
#include <errno.h>
+#include <event.h>
#include <init.h>
#include <irq.h>
#include <log.h>
@@ -185,7 +186,8 @@
}
#endif
-#if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB)
+#if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB) && \
+ !defined(CONFIG_SPL_BUILD)
/*
* Implement a weak default function for boards that need to do some final init
* before the system is ready.
@@ -202,7 +204,7 @@
{
}
-int last_stage_init(void)
+static int last_stage_init(void)
{
struct acpi_fadt __maybe_unused *fadt;
int ret;
@@ -245,7 +247,9 @@
return 0;
}
-#endif
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
+
+#endif /* !SYS_COREBOOT && !EFI_STUB && !SPL_BUILD */
static int x86_init_cpus(void)
{
diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c
index d8920ef..708bfbe 100644
--- a/arch/x86/cpu/efi/payload.c
+++ b/arch/x86/cpu/efi/payload.c
@@ -9,6 +9,7 @@
#include <efi.h>
#include <efi_api.h>
#include <errno.h>
+#include <event.h>
#include <init.h>
#include <log.h>
#include <usb.h>
@@ -168,7 +169,7 @@
return 0;
}
-int last_stage_init(void)
+static int last_stage_init(void)
{
/* start usb so that usb keyboard can be used as input device */
if (IS_ENABLED(CONFIG_USB_KEYBOARD))
@@ -176,6 +177,7 @@
return 0;
}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
unsigned int install_e820_map(unsigned int max_entries,
struct e820_entry *entries)
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index 91cd5d7..8882532 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -415,7 +415,7 @@
/* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
static void setup_pci_ram_top(void)
{
- gd->pci_ram_top = 0x80000000U;
+ gd_set_pci_ram_top(0x80000000U);
}
static void setup_mtrr(void)
diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c
index 56cc253..ff959d1 100644
--- a/arch/x86/cpu/intel_common/mrc.c
+++ b/arch/x86/cpu/intel_common/mrc.c
@@ -9,6 +9,7 @@
#include <dm.h>
#include <init.h>
#include <log.h>
+#include <spl.h>
#include <syscon.h>
#include <asm/cpu.h>
#include <asm/global_data.h>
@@ -251,13 +252,28 @@
int mrc_common_init(struct udevice *dev, void *pei_data, bool use_asm_linkage)
{
struct udevice *me_dev;
- int ret;
+ int ret, delay;
ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
if (ret)
return ret;
+ delay = dev_read_u32_default(dev, "fspm,training-delay", 0);
+ if (spl_phase() == PHASE_SPL) {
+ if (delay)
+ printf("SDRAM training (%d seconds)...", delay);
+ else
+ log_debug("SDRAM init...");
+ } else {
+ if (delay)
+ printf("(%d seconds)...", delay);
+ }
+
ret = sdram_initialise(dev, me_dev, pei_data, use_asm_linkage);
+ if (delay)
+ printf("done\n");
+ else
+ log_debug("done\n");
if (ret)
return ret;
quick_ram_check();
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index c988d7f..e71a10b 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -54,7 +54,7 @@
return x86_cpu_init_f();
}
-static int ivybridge_cpu_init(void *ctx, struct event *ev)
+static int ivybridge_cpu_init(void)
{
struct pci_controller *hose;
struct udevice *bus, *dev;
@@ -86,7 +86,7 @@
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, ivybridge_cpu_init);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, ivybridge_cpu_init);
#define PCH_EHCI0_TEMP_BAR0 0xe8000000
#define PCH_EHCI1_TEMP_BAR0 0xe8000400
diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c
index 82b776f..9a2d682 100644
--- a/arch/x86/cpu/quark/acpi.c
+++ b/arch/x86/cpu/quark/acpi.c
@@ -10,20 +10,24 @@
#include <asm/arch/global_nvs.h>
#include <asm/arch/iomap.h>
-void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
- void *dsdt)
+static int quark_write_fadt(struct acpi_ctx *ctx,
+ const struct acpi_writer *entry)
{
- struct acpi_table_header *header = &(fadt->header);
u16 pmbase = ACPI_PM1_BASE_ADDRESS;
+ struct acpi_table_header *header;
+ struct acpi_fadt *fadt;
- memset((void *)fadt, 0, sizeof(struct acpi_fadt));
+ fadt = ctx->current;
+ header = &fadt->header;
+
+ memset(fadt, '\0', sizeof(struct acpi_fadt));
acpi_fill_header(header, "FACP");
header->length = sizeof(struct acpi_fadt);
header->revision = 4;
- fadt->firmware_ctrl = (u32)facs;
- fadt->dsdt = (u32)dsdt;
+ fadt->firmware_ctrl = (u32)ctx->facs;
+ fadt->dsdt = (u32)ctx->dsdt;
fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED;
fadt->sci_int = 9;
fadt->smi_cmd = 0;
@@ -70,9 +74,9 @@
fadt->reset_reg.addrh = 0;
fadt->reset_value = SYS_RST | RST_CPU | FULL_RST;
- fadt->x_firmware_ctl_l = (u32)facs;
+ fadt->x_firmware_ctl_l = (u32)ctx->facs;
fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (u32)dsdt;
+ fadt->x_dsdt_l = (u32)ctx->dsdt;
fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
@@ -132,7 +136,10 @@
fadt->x_gpe1_blk.addrh = 0x0;
header->checksum = table_compute_checksum(fadt, header->length);
+
+ return acpi_add_fadt(ctx, fadt);
}
+ACPI_WRITER(5fadt, "FADT", quark_write_fadt, 0);
int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
{
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index 1be8e38..62b83c2 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -107,7 +107,7 @@
CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
}
-static void quark_pcie_early_init(void)
+static int quark_pcie_early_init(void)
{
/*
* Step1: Assert PCIe signal PERST#
@@ -146,6 +146,8 @@
/* Mixer Load Lane 1 */
msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1,
(1 << 6) | (1 << 7));
+
+ return 0;
}
static void quark_usb_early_init(void)
@@ -248,22 +250,16 @@
return 0;
}
-static int quark_init_pcie(void *ctx, struct event *event)
-{
- /*
- * Initialize PCIe controller
- *
- * Quark SoC holds the PCIe controller in reset following a power on.
- * U-Boot needs to release the PCIe controller from reset. The PCIe
- * controller (D23:F0/F1) will not be visible in PCI configuration
- * space and any access to its PCI configuration registers will cause
- * system hang while it is held in reset.
- */
- quark_pcie_early_init();
-
- return 0;
-}
-EVENT_SPY(EVT_DM_POST_INIT_F, quark_init_pcie);
+/*
+ * Initialize PCIe controller
+ *
+ * Quark SoC holds the PCIe controller in reset following a power on.
+ * U-Boot needs to release the PCIe controller from reset. The PCIe
+ * controller (D23:F0/F1) will not be visible in PCI configuration
+ * space and any access to its PCI configuration registers will cause
+ * system hang while it is held in reset.
+ */
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, quark_pcie_early_init);
int checkcpu(void)
{
diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c
index 3ffba38..1c667c7 100644
--- a/arch/x86/cpu/tangier/acpi.c
+++ b/arch/x86/cpu/tangier/acpi.c
@@ -16,19 +16,23 @@
#include <asm/arch/iomap.h>
#include <dm/uclass-internal.h>
-void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
- void *dsdt)
+static int tangier_write_fadt(struct acpi_ctx *ctx,
+ const struct acpi_writer *entry)
{
- struct acpi_table_header *header = &(fadt->header);
+ struct acpi_table_header *header;
+ struct acpi_fadt *fadt;
- memset((void *)fadt, 0, sizeof(struct acpi_fadt));
+ fadt = ctx->current;
+ header = &fadt->header;
+
+ memset(fadt, '\0', sizeof(struct acpi_fadt));
acpi_fill_header(header, "FACP");
header->length = sizeof(struct acpi_fadt);
header->revision = 6;
- fadt->firmware_ctrl = (u32)facs;
- fadt->dsdt = (u32)dsdt;
+ fadt->firmware_ctrl = (u32)ctx->facs;
+ fadt->dsdt = (u32)ctx->dsdt;
fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED;
fadt->iapc_boot_arch = ACPI_FADT_VGA_NOT_PRESENT |
@@ -41,13 +45,16 @@
fadt->minor_revision = 2;
- fadt->x_firmware_ctl_l = (u32)facs;
+ fadt->x_firmware_ctl_l = (u32)ctx->facs;
fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (u32)dsdt;
+ fadt->x_dsdt_l = (u32)ctx->dsdt;
fadt->x_dsdt_h = 0;
header->checksum = table_compute_checksum(fadt, header->length);
+
+ return acpi_add_fadt(ctx, fadt);
}
+ACPI_WRITER(5fadt, "FADT", tangier_write_fadt, 0);
u32 acpi_fill_madt(u32 current)
{
diff --git a/arch/x86/cpu/tangier/pinmux.c b/arch/x86/cpu/tangier/pinmux.c
index 7b2c35f..23bfa7c 100644
--- a/arch/x86/cpu/tangier/pinmux.c
+++ b/arch/x86/cpu/tangier/pinmux.c
@@ -13,6 +13,7 @@
#include <asm/cpu.h>
#include <asm/scu.h>
#include <linux/io.h>
+#include <linux/printk.h>
#define BUFCFG_OFFSET 0x100
diff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c
index ee74a1f..374b262 100644
--- a/arch/x86/cpu/tangier/sdram.c
+++ b/arch/x86/cpu/tangier/sdram.c
@@ -9,6 +9,7 @@
#include <asm/e820.h>
#include <asm/global_data.h>
#include <asm/sfi.h>
+#include <linux/printk.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
index d1c3873..2647bff 100644
--- a/arch/x86/cpu/x86_64/cpu.c
+++ b/arch/x86/cpu/x86_64/cpu.c
@@ -8,8 +8,11 @@
#include <cpu_func.h>
#include <debug_uart.h>
#include <init.h>
+#include <asm/cpu.h>
#include <asm/global_data.h>
+DECLARE_GLOBAL_DATA_PTR;
+
int cpu_has_64bit(void)
{
return true;
@@ -38,6 +41,10 @@
int x86_cpu_reinit_f(void)
{
+ /* set the vendor to Intel so that native_calibrate_tsc() works */
+ gd->arch.x86_vendor = X86_VENDOR_INTEL;
+ gd->arch.has_mtrr = true;
+
return 0;
}
diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts
index 96705ce..ddff277 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -266,6 +266,7 @@
board-id-gpios = <&gpio_c 5 0>, <&gpio_c 4 0>,
<&gpio_c 3 0>, <&gpio_c 1 0>;
bootph-all;
+ fspm,training-delay = <7>;
spd {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts
index f9ff534..0eb31ca 100644
--- a/arch/x86/dts/coreboot.dts
+++ b/arch/x86/dts/coreboot.dts
@@ -42,6 +42,7 @@
};
coreboot-fb {
+ bootph-some-ram;
compatible = "coreboot-fb";
};
};
diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index 72e1873..226753b 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -24,8 +24,6 @@
/* These can be used by the target port */
-void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
- void *dsdt);
int acpi_create_madt_lapics(u32 current);
int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
u32 addr, u32 gsi_base);
diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h
index 4de137f..0dfb64b 100644
--- a/arch/x86/include/asm/coreboot_tables.h
+++ b/arch/x86/include/asm/coreboot_tables.h
@@ -299,11 +299,24 @@
#define CB_TAG_TIMESTAMPS 0x0016
#define CB_TAG_CBMEM_CONSOLE 0x0017
+#define CBMC_CURSOR_MASK ((1 << 28) - 1)
+#define CBMC_OVERFLOW BIT(31)
+
+/*
+ * struct cbmem_console - In-memory console buffer for coreboot
+ *
+ * Structure describing console buffer. It is overlaid on a flat memory area,
+ * with body covering the extent of the memory. Once the buffer is full,
+ * output will wrap back around to the start of the buffer. The high bit of the
+ * cursor field gets set to indicate that this happened. If the underlying
+ * storage allows this, the buffer will persist across multiple boots and append
+ * to the previous log.
+ */
struct cbmem_console {
u32 size;
u32 cursor;
- char body[0];
-} __packed;
+ u8 body[0];
+};
#define CB_TAG_MRC_CACHE 0x0018
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index ea58259..6f4a713 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -127,6 +127,7 @@
ulong table_end; /* End address of x86 tables */
ulong table_start_high; /* Start address of high x86 tables */
ulong table_end_high; /* End address of high x86 tables */
+ ulong smbios_start; /* Start address of SMBIOS table */
};
#endif
diff --git a/arch/x86/include/asm/sections.h b/arch/x86/include/asm/sections.h
index a6be360..874a43d 100644
--- a/arch/x86/include/asm/sections.h
+++ b/arch/x86/include/asm/sections.h
@@ -8,4 +8,6 @@
#include <asm-generic/sections.h>
+extern char __data_end[];
+
#endif
diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h
index 79b90a2..e626800 100644
--- a/arch/x86/include/asm/zimage.h
+++ b/arch/x86/include/asm/zimage.h
@@ -61,41 +61,4 @@
int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
ulong initrd_addr, ulong initrd_size, ulong cmdline_force);
-/**
- * zimage_dump() - Dump the metadata of a zimage
- *
- * This shows all available information in a zimage that has been loaded.
- *
- * @base_ptr: Pointer to the boot parameters, typically at address
- * DEFAULT_SETUP_BASE
- */
-void zimage_dump(struct boot_params *base_ptr);
-
-/**
- * zboot_start() - Boot a zimage
- *
- * Boot a zimage, given the component parts
- *
- * @addr: Address where the bzImage is moved before booting, either
- * BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR
- * @base: Pointer to the boot parameters, typically at address
- * DEFAULT_SETUP_BASE
- * @initrd: Address of the initial ramdisk, or 0 if none
- * @initrd_size: Size of the initial ramdisk, or 0 if none
- * @cmdline: Command line to use for booting
- * Return: -EFAULT on error (normally it does not return)
- */
-int zboot_start(ulong addr, ulong size, ulong initrd, ulong initrd_size,
- ulong base, char *cmdline);
-
-/*
- * zimage_get_kernel_version() - Get the version string from a kernel
- *
- * @params: boot_params pointer
- * @kernel_base: base address of kernel
- * Return: Kernel version as a NUL-terminated string
- */
-const char *zimage_get_kernel_version(struct boot_params *params,
- void *kernel_base);
-
#endif
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index e3b7e9a..c5b33dc 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -458,21 +458,6 @@
}
ACPI_WRITER(4gnvs, "GNVS", acpi_write_gnvs, 0);
-static int acpi_write_fadt(struct acpi_ctx *ctx,
- const struct acpi_writer *entry)
-{
- struct acpi_fadt *fadt;
-
- fadt = ctx->current;
- acpi_create_fadt(fadt, ctx->facs, ctx->dsdt);
- acpi_add_table(ctx, fadt);
-
- acpi_inc(ctx, sizeof(struct acpi_fadt));
-
- return 0;
-}
-ACPI_WRITER(5fact, "FADT", acpi_write_fadt, 0);
-
/**
* acpi_write_hpet() - Write out a HPET table
*
diff --git a/arch/x86/lib/coreboot/cb_sysinfo.c b/arch/x86/lib/coreboot/cb_sysinfo.c
index dfbc80c..f7fd9ea 100644
--- a/arch/x86/lib/coreboot/cb_sysinfo.c
+++ b/arch/x86/lib/coreboot/cb_sysinfo.c
@@ -471,6 +471,7 @@
return -ENOENT;
gd->arch.coreboot_table = addr;
gd_set_acpi_start(map_to_sysmem(info->rsdp));
+ gd_set_smbios_start(info->smbios_start);
gd->flags |= GD_FLG_SKIP_LL_INIT;
return 0;
diff --git a/arch/x86/lib/fsp1/fsp_common.c b/arch/x86/lib/fsp1/fsp_common.c
index 2092617..df18f47 100644
--- a/arch/x86/lib/fsp1/fsp_common.c
+++ b/arch/x86/lib/fsp1/fsp_common.c
@@ -101,3 +101,4 @@
return 0;
}
+EVENT_SPY_SIMPLE(EVT_FSP_INIT_F, arch_fsp_init);
diff --git a/arch/x86/lib/fsp2/fsp_common.c b/arch/x86/lib/fsp2/fsp_common.c
index 20c3f64..d802a86 100644
--- a/arch/x86/lib/fsp2/fsp_common.c
+++ b/arch/x86/lib/fsp2/fsp_common.c
@@ -8,11 +8,6 @@
#include <init.h>
#include <asm/fsp/fsp_support.h>
-int arch_fsp_init(void)
-{
- return 0;
-}
-
void board_final_cleanup(void)
{
u32 status;
diff --git a/arch/x86/lib/fsp2/fsp_init.c b/arch/x86/lib/fsp2/fsp_init.c
index afec7d0..aadc08c 100644
--- a/arch/x86/lib/fsp2/fsp_init.c
+++ b/arch/x86/lib/fsp2/fsp_init.c
@@ -19,7 +19,7 @@
#include <dm/uclass-internal.h>
#include <asm/fsp2/fsp_internal.h>
-int fsp_setup_pinctrl(void *ctx, struct event *event)
+int fsp_setup_pinctrl(void)
{
struct udevice *dev;
ofnode node;
@@ -42,7 +42,7 @@
return ret;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, fsp_setup_pinctrl);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, fsp_setup_pinctrl);
#if !defined(CONFIG_TPL_BUILD)
binman_sym_declare(ulong, intel_fsp_m, image_pos);
diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c
index 60a2707..bf0c921 100644
--- a/arch/x86/lib/init_helpers.c
+++ b/arch/x86/lib/init_helpers.c
@@ -15,7 +15,8 @@
int init_cache_f_r(void)
{
bool do_mtrr = CONFIG_IS_ENABLED(X86_32BIT_INIT) ||
- IS_ENABLED(CONFIG_FSP_VERSION2);
+ IS_ENABLED(CONFIG_FSP_VERSION2) ||
+ (IS_ENABLED(CONFIG_TPL) && IS_ENABLED(CONFIG_HAVE_MRC));
int ret;
/*
@@ -23,11 +24,9 @@
*
* booting from slimbootloader - MTRRs are already set up
* booting with FSPv1 - MTRRs are already set up
- * booting with FSPv2 - MTRRs must be set here
+ * booting with FSPv2 or MRC - MTRRs must be set here
* booting from coreboot - in this case there is no SPL, so we set up
* the MTRRs here
- * Note: if there is an SPL, then it has already set up MTRRs so we
- * don't need to do that here
*/
do_mtrr &= !IS_ENABLED(CONFIG_FSP_VERSION1) &&
!IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER);
diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c
index 5b1b420..da819b9 100644
--- a/arch/x86/lib/relocate.c
+++ b/arch/x86/lib/relocate.c
@@ -26,11 +26,11 @@
int copy_uboot_to_ram(void)
{
- size_t len = (uintptr_t)&__data_end - (uintptr_t)&__text_start;
+ size_t len = (uintptr_t)__data_end - (uintptr_t)__text_start;
if (gd->flags & GD_FLG_SKIP_RELOC)
return 0;
- memcpy((void *)gd->relocaddr, (void *)&__text_start, len);
+ memcpy((void *)gd->relocaddr, (void *)__text_start, len);
return 0;
}
@@ -38,8 +38,8 @@
#ifndef CONFIG_EFI_APP
int clear_bss(void)
{
- ulong dst_addr = (ulong)&__bss_start + gd->reloc_off;
- size_t len = (uintptr_t)&__bss_end - (uintptr_t)&__bss_start;
+ ulong dst_addr = (ulong)__bss_start + gd->reloc_off;
+ size_t len = (uintptr_t)__bss_end - (uintptr_t)__bss_start;
if (gd->flags & GD_FLG_SKIP_RELOC)
return 0;
@@ -150,12 +150,12 @@
*/
int do_elf_reloc_fixups(void)
{
- void *re_src = (void *)(&__rel_dyn_start);
- void *re_end = (void *)(&__rel_dyn_end);
+ void *re_src = (void *)__rel_dyn_start;
+ void *re_end = (void *)__rel_dyn_end;
uint text_base;
/* The size of the region of u-boot that runs out of RAM. */
- uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start;
+ uintptr_t size = (uintptr_t)__bss_end - (uintptr_t)__text_start;
if (gd->flags & GD_FLG_SKIP_RELOC)
return 0;
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index f99df08..c15f11f 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -138,9 +138,9 @@
}
#ifndef CONFIG_SYS_COREBOOT
- debug("BSS clear from %lx to %lx len %lx\n", (ulong)&__bss_start,
- (ulong)&__bss_end, (ulong)&__bss_end - (ulong)&__bss_start);
- memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
+ debug("BSS clear from %lx to %lx len %lx\n", (ulong)__bss_start,
+ (ulong)__bss_end, (ulong)__bss_end - (ulong)__bss_start);
+ memset(__bss_start, 0, (ulong)__bss_end - (ulong)__bss_start);
# ifndef CONFIG_TPL
/* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */
@@ -230,6 +230,9 @@
mtrr_commit(false);
init_cache();
gd->flags &= ~GD_FLG_SERIAL_READY;
+
+ /* make sure driver model is not accessed from now on */
+ gd->flags |= GD_FLG_DM_DEAD;
debug("cache status %d\n", dcache_status());
board_init_r(gd, 0);
}
@@ -258,7 +261,7 @@
spl_image->os = IH_OS_U_BOOT;
spl_image->name = "U-Boot";
- if (!IS_ENABLED(CONFIG_SYS_COREBOOT)) {
+ if (spl_image->load_addr != spl_get_image_pos()) {
/* Copy U-Boot from ROM */
memcpy((void *)spl_image->load_addr,
(void *)spl_get_image_pos(), spl_get_image_size());
diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
index 67bc0a7..5b5070f 100644
--- a/arch/x86/lib/tables.c
+++ b/arch/x86/lib/tables.c
@@ -97,6 +97,9 @@
int size = table->size ? : CONFIG_ROM_TABLE_SIZE;
u32 rom_table_end;
+ if (!strcmp("smbios", table->name))
+ gd->arch.smbios_start = rom_addr;
+
if (IS_ENABLED(CONFIG_BLOBLIST_TABLES) && table->tag) {
if (!gd->arch.table_end)
gd->arch.table_end = rom_addr;
diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c
index 18b05b2..273e9c8 100644
--- a/arch/x86/lib/tpl.c
+++ b/arch/x86/lib/tpl.c
@@ -3,6 +3,8 @@
* Copyright (c) 2018 Google, Inc
*/
+#define LOG_CATEGORY LOGC_BOOT
+
#include <common.h>
#include <debug_uart.h>
#include <dm.h>
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index bd9553f..8097fee 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -688,7 +688,7 @@
printf("\n");
}
-void zimage_dump(struct boot_params *base_ptr)
+void zimage_dump(struct boot_params *base_ptr, bool show_cmdline)
{
struct setup_header *hdr;
const char *version;
@@ -699,7 +699,7 @@
printf("E820: %d entries\n", base_ptr->e820_entries);
if (base_ptr->e820_entries) {
- printf("%18s %16s %s\n", "Addr", "Size", "Type");
+ printf("%12s %10s %s\n", "Addr", "Size", "Type");
for (i = 0; i < base_ptr->e820_entries; i++) {
struct e820_entry *entry = &base_ptr->e820_map[i];
@@ -745,7 +745,7 @@
print_num("Ext loader ver", hdr->ext_loader_ver);
print_num("Ext loader type", hdr->ext_loader_type);
print_num("Command line ptr", hdr->cmd_line_ptr);
- if (hdr->cmd_line_ptr) {
+ if (show_cmdline && hdr->cmd_line_ptr) {
printf(" ");
/* Use puts() to avoid limits from CONFIG_SYS_PBSIZE */
puts((char *)(ulong)hdr->cmd_line_ptr);
@@ -783,7 +783,7 @@
printf("No zboot setup_base\n");
return CMD_RET_FAILURE;
}
- zimage_dump(base_ptr);
+ zimage_dump(base_ptr, true);
return 0;
}
diff --git a/arch/xtensa/lib/relocate.c b/arch/xtensa/lib/relocate.c
index 3dc8edc..a499590 100644
--- a/arch/xtensa/lib/relocate.c
+++ b/arch/xtensa/lib/relocate.c
@@ -9,8 +9,8 @@
int clear_bss(void)
{
- size_t len = (size_t)&__bss_end - (size_t)&__bss_start;
+ size_t len = (size_t)__bss_end - (size_t)__bss_start;
- memset((void *)&__bss_start, 0x00, len);
+ memset((void *)__bss_start, 0x00, len);
return 0;
}
diff --git a/board/AndesTech/ae350/Kconfig b/board/AndesTech/ae350/Kconfig
index 75815bf..a85e7d6 100644
--- a/board/AndesTech/ae350/Kconfig
+++ b/board/AndesTech/ae350/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_AE350
+if TARGET_ANDES_AE350
config SYS_CPU
default "andesv5"
diff --git a/board/AndesTech/ae350/MAINTAINERS b/board/AndesTech/ae350/MAINTAINERS
index ead8e0e..a6bc90b 100644
--- a/board/AndesTech/ae350/MAINTAINERS
+++ b/board/AndesTech/ae350/MAINTAINERS
@@ -4,10 +4,14 @@
F: board/AndesTech/ae350/
F: include/configs/ae350.h
F: configs/ae350_rv32_defconfig
-F: configs/ae350_rv64_defconfig
-F: configs/ae350_rv32_xip_defconfig
-F: configs/ae350_rv64_xip_defconfig
+F: configs/ae350_rv32_falcon_defconfig
+F: configs/ae350_rv32_falcon_xip_defconfig
F: configs/ae350_rv32_spl_defconfig
-F: configs/ae350_rv64_spl_defconfig
F: configs/ae350_rv32_spl_xip_defconfig
+F: configs/ae350_rv32_xip_defconfig
+F: configs/ae350_rv64_defconfig
+F: configs/ae350_rv64_falcon_defconfig
+F: configs/ae350_rv64_falcon_xip_defconfig
+F: configs/ae350_rv64_spl_defconfig
F: configs/ae350_rv64_spl_xip_defconfig
+F: configs/ae350_rv64_xip_defconfig
diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c
index 1c2288b..772c6bf 100644
--- a/board/AndesTech/ae350/ae350.c
+++ b/board/AndesTech/ae350/ae350.c
@@ -4,7 +4,7 @@
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
*/
-#include <common.h>
+#include <config.h>
#include <cpu_func.h>
#include <flash.h>
#include <image.h>
@@ -19,6 +19,8 @@
#include <fdtdec.h>
#include <dm.h>
#include <spl.h>
+#include <mapmem.h>
+#include <hang.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -26,6 +28,29 @@
* Miscellaneous platform dependent initializations
*/
+#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
+#define ANDES_SPL_FDT_ADDR (CONFIG_TEXT_BASE - 0x100000)
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+ /*
+ * Originally, u-boot-spl will place DTB directly after the kernel,
+ * but the size of the kernel did not include the BSS section, which
+ * means u-boot-spl will place the DTB in the kernel BSS section
+ * causing the DTB to be cleared by kernel BSS initializtion.
+ * Moving DTB in front of the kernel can avoid the error.
+ */
+ if (ANDES_SPL_FDT_ADDR < 0) {
+ printf("%s: CONFIG_TEXT_BASE needs to be larger than 0x100000\n",
+ __func__);
+ hang();
+ }
+
+ memcpy((void *)ANDES_SPL_FDT_ADDR, spl_image->fdt_addr,
+ fdt_totalsize(spl_image->fdt_addr));
+ spl_image->fdt_addr = map_sysmem(ANDES_SPL_FDT_ADDR, 0);
+}
+#endif
+
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
diff --git a/board/CZ.NIC/turris_mox/mox_sp.c b/board/CZ.NIC/turris_mox/mox_sp.c
index 87f6751..11d8756 100644
--- a/board/CZ.NIC/turris_mox/mox_sp.c
+++ b/board/CZ.NIC/turris_mox/mox_sp.c
@@ -10,6 +10,8 @@
#include <linux/delay.h>
#include <mach/mbox.h>
+#include "mox_sp.h"
+
const char *mox_sp_get_ecdsa_public_key(void)
{
static char public_key[135];
@@ -42,12 +44,13 @@
mac[5] = t2;
}
-int mbox_sp_get_board_info(u64 *sn, u8 *mac1, u8 *mac2, int *bv, int *ram)
+int mbox_sp_get_board_info(u64 *sn, u8 *mac1, u8 *mac2, int *bv, int *ram,
+ enum cznic_a3720_board *board)
{
- u32 out[8];
+ u32 out[9];
int res;
- res = mbox_do_cmd(MBOX_CMD_BOARD_INFO, NULL, 0, out, 8);
+ res = mbox_do_cmd(MBOX_CMD_BOARD_INFO, NULL, 0, out, 9);
if (res < 0)
return res;
@@ -69,5 +72,8 @@
if (mac2)
res_to_mac(mac2, out[6], out[7]);
+ if (board)
+ *board = out[8] + 1;
+
return 0;
}
diff --git a/board/CZ.NIC/turris_mox/mox_sp.h b/board/CZ.NIC/turris_mox/mox_sp.h
index 83b6037..720880d 100644
--- a/board/CZ.NIC/turris_mox/mox_sp.h
+++ b/board/CZ.NIC/turris_mox/mox_sp.h
@@ -8,8 +8,14 @@
#include <common.h>
+enum cznic_a3720_board {
+ BOARD_UNDEFINED = 0x0,
+ BOARD_TURRIS_MOX = 0x1,
+ BOARD_RIPE_ATLAS = 0x3,
+};
+
const char *mox_sp_get_ecdsa_public_key(void);
int mbox_sp_get_board_info(u64 *sn, u8 *mac1, u8 *mac2, int *bv,
- int *ram);
+ int *ram, enum cznic_a3720_board *board);
#endif /* _BOARD_CZNIC_TURRIS_MOX_MOX_SP_H_ */
diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c
index a52a032..63b8699 100644
--- a/board/CZ.NIC/turris_mox/turris_mox.c
+++ b/board/CZ.NIC/turris_mox/turris_mox.c
@@ -15,6 +15,8 @@
#include <dm.h>
#include <dm/of_extra.h>
#include <env.h>
+#include <env_internal.h>
+#include <event.h>
#include <fdt_support.h>
#include <init.h>
#include <led.h>
@@ -44,6 +46,26 @@
DECLARE_GLOBAL_DATA_PTR;
+int board_fit_config_name_match(const char *name)
+{
+ if (!gd->board_type) {
+ enum cznic_a3720_board board;
+
+ if (mbox_sp_get_board_info(NULL, NULL, NULL, NULL, NULL,
+ &board) < 0) {
+ printf("Cannot determine board, defaulting to Turris MOX!\n");
+ board = BOARD_TURRIS_MOX;
+ }
+
+ gd->board_type = board;
+ }
+
+ return !((gd->board_type == BOARD_TURRIS_MOX &&
+ !strcmp(name, "armada-3720-turris-mox")) ||
+ (gd->board_type == BOARD_RIPE_ATLAS &&
+ !strcmp(name, "armada-3720-ripe-atlas")));
+}
+
#if defined(CONFIG_OF_BOARD_FIXUP)
int board_fix_fdt(void *blob)
{
@@ -52,6 +74,9 @@
int i, size, ret;
bool eth1_sgmii;
+ if (gd->board_type != BOARD_TURRIS_MOX)
+ return 0;
+
/*
* SPI driver is not loaded in driver model yet, but we have to find out
* if pcie should be enabled in U-Boot's device tree. Therefore we have
@@ -387,16 +412,23 @@
int misc_init_r(void)
{
+ int i, ret, addrcnt;
u8 mac[2][6];
- int i, ret;
- ret = mbox_sp_get_board_info(NULL, mac[0], mac[1], NULL, NULL);
+ ret = mbox_sp_get_board_info(NULL, mac[0], mac[1], NULL, NULL, NULL);
if (ret < 0) {
printf("Cannot read data from OTP!\n");
return 0;
}
- for (i = 0; i < 2; ++i) {
+ if (gd->board_type == BOARD_TURRIS_MOX)
+ addrcnt = 2;
+ else if (gd->board_type == BOARD_RIPE_ATLAS)
+ addrcnt = 1;
+ else
+ addrcnt = 0;
+
+ for (i = 0; i < addrcnt; ++i) {
u8 oldmac[6];
if (is_valid_ethaddr(mac[i]) &&
@@ -404,7 +436,13 @@
eth_env_set_enetaddr_by_index("eth", i, mac[i]);
}
- load_spi_dtb();
+ if (gd->board_type == BOARD_RIPE_ATLAS) {
+ env_set("board", "ripe_atlas");
+ env_set("board_name", "ripe_atlas");
+ env_set("fdtfile", "marvell/armada-3720-ripe-atlas.dtb");
+ } else {
+ load_spi_dtb();
+ }
return 0;
}
@@ -527,14 +565,15 @@
int show_board_info(void)
{
int i, ret, board_version, ram_size, is_sd;
- const char *pub_key;
+ const char *pub_key, *model;
const u8 *topology;
u64 serial_number;
- printf("Model: CZ.NIC Turris Mox Board\n");
+ model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
+ printf("Model: %s\n", model);
ret = mbox_sp_get_board_info(&serial_number, NULL, NULL, &board_version,
- &ram_size);
+ &ram_size, NULL);
if (ret < 0) {
printf(" Cannot read board info: %i\n", ret);
} else {
@@ -549,6 +588,9 @@
else
printf(" Cannot read ECDSA Public Key\n");
+ if (gd->board_type != BOARD_TURRIS_MOX)
+ return 0;
+
ret = mox_get_topology(&topology, &module_count, &is_sd);
if (ret)
printf("Cannot read module topology!\n");
@@ -667,10 +709,24 @@
return NULL;
}
-int last_stage_init(void)
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ if (prio > 0)
+ return ENVL_UNKNOWN;
+
+ if (gd->board_type == BOARD_RIPE_ATLAS)
+ return ENVL_MMC;
+
+ return ENVL_SPI_FLASH;
+}
+
+static int last_stage_init(void)
{
struct gpio_desc reset_gpio = {};
+ if (gd->board_type != BOARD_TURRIS_MOX)
+ return 0;
+
/* configure modules */
if (get_reset_gpio(&reset_gpio) < 0)
goto handle_reset_btn;
@@ -712,6 +768,7 @@
return 0;
}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
#if defined(CONFIG_OF_BOARD_SETUP)
@@ -799,6 +856,9 @@
{
int res;
+ if (gd->board_type != BOARD_TURRIS_MOX)
+ return 0;
+
/*
* If MOX B (PCI), MOX F (USB) or MOX G (Passthrough PCI) modules are
* connected, enable the PCIe node.
diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c
index 3ab6e88..04124d8 100644
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -8,6 +8,7 @@
#include <dm/device-internal.h>
#include <env.h>
#include <env_internal.h>
+#include <event.h>
#include <i2c.h>
#include <init.h>
#include <mmc.h>
@@ -301,12 +302,13 @@
}
/* Bring-up board-specific network stuff */
-int last_stage_init(void)
+static int last_stage_init(void)
{
struct udevice *bus;
ofnode node;
- if (!of_machine_is_compatible("globalscale,espressobin"))
+ if (!CONFIG_IS_ENABLED(DM_MDIO) ||
+ !of_machine_is_compatible("globalscale,espressobin"))
return 0;
node = ofnode_by_compatible(ofnode_null(), "marvell,orion-mdio");
@@ -356,6 +358,8 @@
return 0;
}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
+
#endif
#ifdef CONFIG_OF_BOARD_SETUP
diff --git a/board/Marvell/octeon_nic23/board.c b/board/Marvell/octeon_nic23/board.c
index 08b1aa4..bc9332c 100644
--- a/board/Marvell/octeon_nic23/board.c
+++ b/board/Marvell/octeon_nic23/board.c
@@ -5,6 +5,7 @@
#include <cyclic.h>
#include <dm.h>
+#include <event.h>
#include <ram.h>
#include <time.h>
#include <asm/gpio.h>
@@ -364,7 +365,7 @@
return 0;
}
-int last_stage_init(void)
+static int last_stage_init(void)
{
struct gpio_desc gpio = {};
ofnode node;
@@ -386,3 +387,4 @@
return 0;
}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
diff --git a/board/Marvell/octeontx2/board.c b/board/Marvell/octeontx2/board.c
index e7899f4..974e9eb 100644
--- a/board/Marvell/octeontx2/board.c
+++ b/board/Marvell/octeontx2/board.c
@@ -12,6 +12,7 @@
#include <asm/global_data.h>
#include <dm/uclass-internal.h>
#include <env.h>
+#include <event.h>
#include <init.h>
#include <malloc.h>
#include <net.h>
@@ -213,11 +214,12 @@
}
}
-int last_stage_init(void)
+static int last_stage_init(void)
{
(void)smc_flsf_fw_booted();
return 0;
}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
static int do_go_uboot(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
diff --git a/board/abilis/tb100/tb100.c b/board/abilis/tb100/tb100.c
index 89e7322..3dc9e14 100644
--- a/board/abilis/tb100/tb100.c
+++ b/board/abilis/tb100/tb100.c
@@ -3,7 +3,6 @@
* (C) Copyright 2014 Pierrick Hascoet, Abilis Systems
*/
-#include <common.h>
#include <cpu_func.h>
#include <net.h>
#include <netdev.h>
diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
index b79a238..d87fe36 100644
--- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
+++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
@@ -193,7 +193,7 @@
#ifdef CONFIG_SPL_MMC
#define UBOOT_RAW_SECTOR_OFFSET 0x40
-unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
+unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
unsigned long raw_sector)
{
u32 boot_dev = spl_boot_device();
diff --git a/board/advantech/imx8qm_dmsse20_a1/spl.c b/board/advantech/imx8qm_dmsse20_a1/spl.c
index f36caec..e8959ed 100644
--- a/board/advantech/imx8qm_dmsse20_a1/spl.c
+++ b/board/advantech/imx8qm_dmsse20_a1/spl.c
@@ -14,6 +14,7 @@
#include <firmware/imx/sci/sci.h>
#include <asm/arch/imx8-pins.h>
#include <asm/arch/iomux.h>
+#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/advantech/imx8qm_rom7720_a1/spl.c b/board/advantech/imx8qm_rom7720_a1/spl.c
index 922bb0b..d324001 100644
--- a/board/advantech/imx8qm_rom7720_a1/spl.c
+++ b/board/advantech/imx8qm_rom7720_a1/spl.c
@@ -17,6 +17,7 @@
#include <firmware/imx/sci/sci.h>
#include <asm/arch/imx8-pins.h>
#include <asm/arch/iomux.h>
+#include <asm/sections.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/altera/arria10-socdk/Makefile b/board/altera/arria10-socdk/Makefile
deleted file mode 100644
index 80d0004..0000000
--- a/board/altera/arria10-socdk/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Copyright (C) 2015 Altera Corporation <www.altera.com>
-
-obj-y := socfpga.o
diff --git a/board/altera/arria10-socdk/socfpga.c b/board/altera/arria10-socdk/socfpga.c
deleted file mode 100644
index 4c466cb..0000000
--- a/board/altera/arria10-socdk/socfpga.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2015 Altera Corporation <www.altera.com>
- */
-
-#include <common.h>
diff --git a/board/altera/arria5-socdk/Makefile b/board/altera/arria5-socdk/Makefile
deleted file mode 100644
index e1c8a6b..0000000
--- a/board/altera/arria5-socdk/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
-
-obj-y := socfpga.o
diff --git a/board/altera/arria5-socdk/socfpga.c b/board/altera/arria5-socdk/socfpga.c
deleted file mode 100644
index 48bfe32..0000000
--- a/board/altera/arria5-socdk/socfpga.c
+++ /dev/null
@@ -1,5 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- */
-#include <common.h>
diff --git a/board/altera/cyclone5-socdk/Makefile b/board/altera/cyclone5-socdk/Makefile
deleted file mode 100644
index e1c8a6b..0000000
--- a/board/altera/cyclone5-socdk/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
-
-obj-y := socfpga.o
diff --git a/board/altera/cyclone5-socdk/socfpga.c b/board/altera/cyclone5-socdk/socfpga.c
deleted file mode 100644
index 48bfe32..0000000
--- a/board/altera/cyclone5-socdk/socfpga.c
+++ /dev/null
@@ -1,5 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- */
-#include <common.h>
diff --git a/board/altera/stratix10-socdk/Makefile b/board/altera/stratix10-socdk/Makefile
deleted file mode 100644
index 02a9cad..0000000
--- a/board/altera/stratix10-socdk/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
-#
-# SPDX-License-Identifier: GPL-2.0
-#
-
-obj-y := socfpga.o
diff --git a/board/altera/stratix10-socdk/socfpga.c b/board/altera/stratix10-socdk/socfpga.c
deleted file mode 100644
index 043fc54..0000000
--- a/board/altera/stratix10-socdk/socfpga.c
+++ /dev/null
@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
- *
- */
-
-#include <common.h>
diff --git a/board/amlogic/vim3/vim3.c b/board/amlogic/vim3/vim3.c
index fcd60ab..8bdfb30 100644
--- a/board/amlogic/vim3/vim3.c
+++ b/board/amlogic/vim3/vim3.c
@@ -104,8 +104,8 @@
}
/* Update PHY names (mandatory to disable USB3.0) */
- len = strlcpy(data, "usb2-phy0", 32);
- len += strlcpy(&data[len], "usb2-phy1", 32 - len);
+ len = strlcpy(data, "usb2-phy0", 32) + 1;
+ len += strlcpy(&data[len], "usb2-phy1", 32 - len) + 1;
ret = fdt_setprop(blob, node, "phy-names", data, len);
if (ret < 0) {
printf("vim3: failed to update usb phy names property (%d)\n", ret);
@@ -132,7 +132,7 @@
}
/* Enable PCIe */
- len = strlcpy(data, "okay", 32);
+ len = strlcpy(data, "okay", 32) + 1;
ret = fdt_setprop(blob, node, "status", data, len);
if (ret < 0) {
printf("vim3: failed to enable pcie node (%d)\n", ret);
diff --git a/board/aries/mcvevk/Makefile b/board/aries/mcvevk/Makefile
deleted file mode 100644
index e1c8a6b..0000000
--- a/board/aries/mcvevk/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
-
-obj-y := socfpga.o
diff --git a/board/aries/mcvevk/socfpga.c b/board/aries/mcvevk/socfpga.c
deleted file mode 100644
index f173bf8..0000000
--- a/board/aries/mcvevk/socfpga.c
+++ /dev/null
@@ -1,5 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015 Marek Vasut <marex@denx.de>
- */
-#include <common.h>
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
index 4dcf3f3..17f37ba 100644
--- a/board/aristainetos/aristainetos.c
+++ b/board/aristainetos/aristainetos.c
@@ -27,6 +27,7 @@
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
+#include <asm/sections.h>
#include <bmp_logo.h>
#include <dm/root.h>
#include <env.h>
@@ -216,7 +217,6 @@
&iomuxc_regs->gpr[12]);
}
-extern char __bss_start[], __bss_end[];
int board_early_init_f(void)
{
select_ldb_di_clock_source(MXC_PLL5_CLK);
diff --git a/board/aspeed/evb_ast2500/Makefile b/board/aspeed/evb_ast2500/Makefile
deleted file mode 100644
index 4564098..0000000
--- a/board/aspeed/evb_ast2500/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += evb_ast2500.o
diff --git a/board/aspeed/evb_ast2500/evb_ast2500.c b/board/aspeed/evb_ast2500/evb_ast2500.c
deleted file mode 100644
index ed162c4..0000000
--- a/board/aspeed/evb_ast2500/evb_ast2500.c
+++ /dev/null
@@ -1,5 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2016 Google, Inc
- */
-#include <common.h>
diff --git a/board/aspeed/evb_ast2600/Makefile b/board/aspeed/evb_ast2600/Makefile
deleted file mode 100644
index 9291db6..0000000
--- a/board/aspeed/evb_ast2600/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += evb_ast2600.o
diff --git a/board/aspeed/evb_ast2600/evb_ast2600.c b/board/aspeed/evb_ast2600/evb_ast2600.c
deleted file mode 100644
index e6dc8c7..0000000
--- a/board/aspeed/evb_ast2600/evb_ast2600.c
+++ /dev/null
@@ -1,5 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) Aspeed Technology Inc.
- */
-#include <common.h>
diff --git a/board/asus/grouper/Kconfig b/board/asus/grouper/Kconfig
index 912c6c5..47d9bae 100644
--- a/board/asus/grouper/Kconfig
+++ b/board/asus/grouper/Kconfig
@@ -12,11 +12,9 @@
config GROUPER_TPS65911
bool "Enable support TI TPS65911 PMIC"
select CMD_POWEROFF
- default n
config GROUPER_MAX77663
bool "Enable support MAXIM MAX77663 PMIC"
select CMD_POWEROFF
- default n
endif
diff --git a/board/asus/grouper/MAINTAINERS b/board/asus/grouper/MAINTAINERS
index 18b4f06..f4068d8 100644
--- a/board/asus/grouper/MAINTAINERS
+++ b/board/asus/grouper/MAINTAINERS
@@ -2,9 +2,6 @@
M: Svyatoslav Ryhel <clamor95@gmail.com>
S: Maintained
F: board/asus/grouper/
-F: configs/grouper_E1565.config
-F: configs/grouper_PM269.config
-F: configs/tilapia.config
F: configs/grouper_common_defconfig
F: doc/board/asus/grouper_common.rst
F: include/configs/grouper.h
diff --git a/configs/grouper_E1565.config b/board/asus/grouper/configs/grouper_E1565.config
similarity index 100%
rename from configs/grouper_E1565.config
rename to board/asus/grouper/configs/grouper_E1565.config
diff --git a/configs/grouper_PM269.config b/board/asus/grouper/configs/grouper_PM269.config
similarity index 100%
rename from configs/grouper_PM269.config
rename to board/asus/grouper/configs/grouper_PM269.config
diff --git a/configs/tilapia.config b/board/asus/grouper/configs/tilapia.config
similarity index 100%
rename from configs/tilapia.config
rename to board/asus/grouper/configs/tilapia.config
diff --git a/board/asus/grouper/grouper.c b/board/asus/grouper/grouper.c
index 2769313..5398ec8 100644
--- a/board/asus/grouper/grouper.c
+++ b/board/asus/grouper/grouper.c
@@ -9,14 +9,12 @@
#include <common.h>
#include <dm.h>
-#include <env.h>
#include <fdt_support.h>
#include <i2c.h>
#include <log.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch/gpio.h>
-#include <asm/arch-tegra/fuse.h>
#include <asm/gpio.h>
#include <linux/delay.h>
#include "pinmux-config-grouper.h"
@@ -190,13 +188,3 @@
return 0;
}
#endif
-
-void nvidia_board_late_init(void)
-{
- char serialno_str[17];
-
- /* Set chip id as serialno */
- sprintf(serialno_str, "%016llx", tegra_chip_uid());
- env_set("serial#", serialno_str);
- env_set("platform", "Tegra 3 T30");
-}
diff --git a/board/asus/transformer-t30/Kconfig b/board/asus/transformer-t30/Kconfig
index 3c36f4a..accc999 100644
--- a/board/asus/transformer-t30/Kconfig
+++ b/board/asus/transformer-t30/Kconfig
@@ -14,7 +14,6 @@
select TEGRA20_SLINK
select DM_SPI_FLASH
select SPI_FLASH_WINBOND
- default n
help
Tegra 3 based Transformers with Windows RT have core
boot sequence (BCT and EBT) on separate SPI FLASH
diff --git a/board/asus/transformer-t30/MAINTAINERS b/board/asus/transformer-t30/MAINTAINERS
index c6c1532..071a9c0 100644
--- a/board/asus/transformer-t30/MAINTAINERS
+++ b/board/asus/transformer-t30/MAINTAINERS
@@ -2,13 +2,6 @@
M: Svyatoslav Ryhel <clamor95@gmail.com>
S: Maintained
F: board/asus/transformer-t30/
-F: configs/p1801-t.config
-F: configs/tf201.config
-F: configs/tf300t.config
-F: configs/tf300tg.config
-F: configs/tf300tl.config
-F: configs/tf600t.config
-F: configs/tf700t.config
F: configs/transformer_t30_defconfig
F: doc/board/asus/transformer_t30.rst
F: include/configs/transformer-common.h
diff --git a/configs/p1801-t.config b/board/asus/transformer-t30/configs/p1801-t.config
similarity index 100%
rename from configs/p1801-t.config
rename to board/asus/transformer-t30/configs/p1801-t.config
diff --git a/configs/tf201.config b/board/asus/transformer-t30/configs/tf201.config
similarity index 100%
rename from configs/tf201.config
rename to board/asus/transformer-t30/configs/tf201.config
diff --git a/configs/tf300t.config b/board/asus/transformer-t30/configs/tf300t.config
similarity index 100%
rename from configs/tf300t.config
rename to board/asus/transformer-t30/configs/tf300t.config
diff --git a/configs/tf300tg.config b/board/asus/transformer-t30/configs/tf300tg.config
similarity index 100%
rename from configs/tf300tg.config
rename to board/asus/transformer-t30/configs/tf300tg.config
diff --git a/configs/tf300tl.config b/board/asus/transformer-t30/configs/tf300tl.config
similarity index 100%
rename from configs/tf300tl.config
rename to board/asus/transformer-t30/configs/tf300tl.config
diff --git a/configs/tf600t.config b/board/asus/transformer-t30/configs/tf600t.config
similarity index 82%
rename from configs/tf600t.config
rename to board/asus/transformer-t30/configs/tf600t.config
index 89d8db4..18ab4fb 100644
--- a/configs/tf600t.config
+++ b/board/asus/transformer-t30/configs/tf600t.config
@@ -1,4 +1,4 @@
CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf600t"
CONFIG_TRANSFORMER_SPI_BOOT=y
-CONFIG_BOOTCOMMAND="setenv gpio_button 222; if run check_button; then poweroff; fi; setenv gpio_button 132; if run check_button; then echo Starting SPI flash update ...; run update_spi; fi; run bootcmd_mmc1; run bootcmd_mmc0; poweroff;"
+CONFIG_BOOTCOMMAND="setenv gpio_button 222; if run check_button; then poweroff; fi; setenv gpio_button 132; if run check_button; then echo Starting SPI flash update ...; run update_spi; fi; run bootcmd_usb0; run bootcmd_mmc1; run bootcmd_mmc0; poweroff;"
CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00
diff --git a/configs/tf700t.config b/board/asus/transformer-t30/configs/tf700t.config
similarity index 100%
rename from configs/tf700t.config
rename to board/asus/transformer-t30/configs/tf700t.config
diff --git a/board/asus/transformer-t30/transformer-t30.c b/board/asus/transformer-t30/transformer-t30.c
index b6fd19d..ba795a8 100644
--- a/board/asus/transformer-t30/transformer-t30.c
+++ b/board/asus/transformer-t30/transformer-t30.c
@@ -11,14 +11,12 @@
#include <common.h>
#include <dm.h>
-#include <env.h>
#include <fdt_support.h>
#include <i2c.h>
#include <log.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch/gpio.h>
-#include <asm/arch-tegra/fuse.h>
#include <asm/gpio.h>
#include <linux/delay.h>
#include "pinmux-config-transformer.h"
@@ -33,11 +31,6 @@
#define TPS65911_LDO5 0x32
#define TPS65911_LDO6 0x35
-#define TPS65911_GPIO0 0x60
-#define TPS65911_GPIO6 0x66
-#define TPS65911_GPIO7 0x67
-#define TPS65911_GPIO8 0x68
-
#define TPS65911_DEVCTRL 0x3F
#define DEVCTRL_PWR_OFF_MASK BIT(7)
#define DEVCTRL_DEV_ON_MASK BIT(2)
@@ -146,26 +139,6 @@
if (ret)
log_debug("vddio_usd set failed: %d\n", ret);
}
-
- /* TPS659110: GPIO0_REG output high to VDD_5V0_SBY */
- ret = dm_i2c_reg_write(dev, TPS65911_GPIO0, 0x07);
- if (ret)
- log_debug("vdd_5v0_sby set failed: %d\n", ret);
-
- /* TPS659110: GPIO6_REG output high to VDD_3V3_SYS */
- ret = dm_i2c_reg_write(dev, TPS65911_GPIO6, 0x07);
- if (ret)
- log_debug("vdd_3v3_sys set failed: %d\n", ret);
-
- /* TPS659110: GPIO7_REG output high to VDD_1V5_DDR */
- ret = dm_i2c_reg_write(dev, TPS65911_GPIO7, 0x07);
- if (ret)
- log_debug("vdd_1v5_ddr set failed: %d\n", ret);
-
- /* TPS659110: GPIO8_REG pull_down output high to VDD_5V0_SYS */
- ret = dm_i2c_reg_write(dev, TPS65911_GPIO8, 0x0f);
- if (ret)
- log_debug("vdd_5v0_sys set failed: %d\n", ret);
}
/*
@@ -189,13 +162,3 @@
return 0;
}
#endif
-
-void nvidia_board_late_init(void)
-{
- char serialno_str[17];
-
- /* Set chip id as serialno */
- sprintf(serialno_str, "%016llx", tegra_chip_uid());
- env_set("serial#", serialno_str);
- env_set("platform", "Tegra 3 T30");
-}
diff --git a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c
index 0fe0de9..f53d359 100644
--- a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c
+++ b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c
@@ -9,6 +9,7 @@
#include <debug_uart.h>
#include <fdtdec.h>
#include <init.h>
+#include <led.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_sfr.h>
@@ -18,6 +19,7 @@
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-types.h>
+#include <dm/ofnode.h>
extern void at91_pda_detect(void);
@@ -27,9 +29,25 @@
static void board_leds_init(void)
{
+#if CONFIG_IS_ENABLED(LED)
+ const char *led_name;
+ struct udevice *dev;
+ int ret;
+
+ led_name = ofnode_conf_read_str("u-boot,boot-led");
+ if (!led_name)
+ return;
+
+ ret = led_get_by_label(led_name, &dev);
+ if (ret)
+ return;
+
+ led_set_state(dev, LEDST_ON);
+#else
at91_set_pio_output(AT91_PIO_PORTD, 17, 0); /* LED RED */
at91_set_pio_output(AT91_PIO_PORTD, 19, 0); /* LED GREEN */
at91_set_pio_output(AT91_PIO_PORTD, 21, 1); /* LED BLUE */
+#endif
}
int board_late_init(void)
diff --git a/board/atmel/sama5d29_curiosity/Kconfig b/board/atmel/sama5d29_curiosity/Kconfig
new file mode 100644
index 0000000..64ca237
--- /dev/null
+++ b/board/atmel/sama5d29_curiosity/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SAMA5D29_CURIOSITY
+
+config SYS_BOARD
+ default "sama5d29_curiosity"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "sama5d29_curiosity"
+
+endif
diff --git a/board/atmel/sama5d29_curiosity/MAINTAINERS b/board/atmel/sama5d29_curiosity/MAINTAINERS
new file mode 100644
index 0000000..54894d6
--- /dev/null
+++ b/board/atmel/sama5d29_curiosity/MAINTAINERS
@@ -0,0 +1,9 @@
+SAMA5D29 CURIOSITY BOARD
+M: Mihai Sain <mihai.sain@microchip.com>
+S: Maintained
+F: board/atmel/sama5d29_curiosity.c
+F: include/configs/sama5d29_curiosity.h
+F: configs/sama5d29_curiosity_mmc_defconfig
+F: configs/sama5d29_curiosity_mmc1_defconfig
+F: configs/sama5d29_curiosity_qspiflash_defconfig
+F: arch/arm/dts/at91-sama5d29_curiosity*
diff --git a/board/atmel/sama5d29_curiosity/Makefile b/board/atmel/sama5d29_curiosity/Makefile
new file mode 100644
index 0000000..848e1ce
--- /dev/null
+++ b/board/atmel/sama5d29_curiosity/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
+#
+# Author: Mihai Sain <mihai.sain@microchip.com>
+
+obj-y += sama5d29_curiosity.o
diff --git a/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c b/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c
new file mode 100644
index 0000000..d067931
--- /dev/null
+++ b/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Mihai Sain <mihai.sain@microchip.com>
+ *
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5d2.h>
+
+extern void at91_pda_detect(void);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void rgb_leds_init(void)
+{
+ atmel_pio4_set_pio_output(AT91_PIO_PORTA, 7, 0); /* LED RED */
+ atmel_pio4_set_pio_output(AT91_PIO_PORTA, 8, 0); /* LED GREEN */
+ atmel_pio4_set_pio_output(AT91_PIO_PORTA, 9, 1); /* LED BLUE */
+}
+
+static void board_usb_hw_init(void)
+{
+ atmel_pio4_set_pio_output(AT91_PIO_PORTA, 6, 1);
+}
+
+int board_late_init(void)
+{
+ at91_video_show_board_info();
+
+ at91_pda_detect();
+
+ return 0;
+}
+
+static void board_uart0_hw_init(void)
+{
+ atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */
+ atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
+
+ at91_periph_clk_enable(ATMEL_ID_UART0);
+}
+
+void board_debug_uart_init(void)
+{
+ board_uart0_hw_init();
+}
+
+int board_early_init_f(void)
+{
+ debug_uart_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+ rgb_leds_init();
+
+ board_usb_hw_init();
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c
index b2830c5..1632238 100644
--- a/board/beacon/imx8mm/spl.c
+++ b/board/beacon/imx8mm/spl.c
@@ -14,6 +14,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/ddr.h>
+#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c
index 9acd916..b4d46f1 100644
--- a/board/beacon/imx8mn/spl.c
+++ b/board/beacon/imx8mn/spl.c
@@ -20,6 +20,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <linux/delay.h>
diff --git a/board/bosch/acc/acc.c b/board/bosch/acc/acc.c
index 7c49b20..34088ad 100644
--- a/board/bosch/acc/acc.c
+++ b/board/bosch/acc/acc.c
@@ -27,6 +27,7 @@
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/iomux-v3.h>
+#include <asm/sections.h>
#include <usb.h>
#include <usb/ehci-ci.h>
#include <fuse.h>
diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c
index c31e2c8..ee9e6d6 100644
--- a/board/bosch/guardian/board.c
+++ b/board/bosch/guardian/board.c
@@ -4,7 +4,7 @@
*
* Board functions for Bosch Guardian
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
* Copyright (C) 2018 Robert Bosch Power Tools GmbH
*/
diff --git a/board/bosch/guardian/board.h b/board/bosch/guardian/board.h
index b301caf..e1e8c0c 100644
--- a/board/bosch/guardian/board.h
+++ b/board/bosch/guardian/board.h
@@ -4,7 +4,7 @@
*
* Board header for Bosch Guardian
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
* Copyright (C) 2018 Robert Bosch Power Tools GmbH
*/
diff --git a/board/bosch/guardian/mux.c b/board/bosch/guardian/mux.c
index 12c3eb6..53850ff 100644
--- a/board/bosch/guardian/mux.c
+++ b/board/bosch/guardian/mux.c
@@ -2,7 +2,7 @@
/*
* mux.c
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
* Copyright (C) 2018 Robert Bosch Power Tools GmbH
*/
diff --git a/board/bosch/shc/Makefile b/board/bosch/shc/Makefile
index 93f2df3..bac12ed 100644
--- a/board/bosch/shc/Makefile
+++ b/board/bosch/shc/Makefile
@@ -2,7 +2,7 @@
#
# Makefile
#
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
obj-y := mux.o
obj-y += board.o
diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c
index e3a9c00..962a485 100644
--- a/board/bosch/shc/board.c
+++ b/board/bosch/shc/board.c
@@ -8,7 +8,7 @@
* Based on:
* Board functions for TI AM335X based boards
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/bosch/shc/board.h b/board/bosch/shc/board.h
index 997595b..4cc02f9 100644
--- a/board/bosch/shc/board.h
+++ b/board/bosch/shc/board.h
@@ -8,7 +8,7 @@
* Based on:
* TI AM335x boards information header
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _BOARD_H_
diff --git a/board/bosch/shc/mux.c b/board/bosch/shc/mux.c
index 0a97eaf..f19d186 100644
--- a/board/bosch/shc/mux.c
+++ b/board/bosch/shc/mux.c
@@ -6,7 +6,7 @@
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/broadcom/bcm968380gerg/Makefile b/board/broadcom/bcm968380gerg/Makefile
deleted file mode 100644
index a525b7b..0000000
--- a/board/broadcom/bcm968380gerg/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += bcm968380gerg.o
diff --git a/board/broadcom/bcm968380gerg/bcm968380gerg.c b/board/broadcom/bcm968380gerg/bcm968380gerg.c
deleted file mode 100644
index 044b355..0000000
--- a/board/broadcom/bcm968380gerg/bcm968380gerg.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
- */
-
-#include <common.h>
diff --git a/board/broadcom/bcm968380gerg/board.c b/board/broadcom/bcm968380gerg/board.c
deleted file mode 100644
index 044b355..0000000
--- a/board/broadcom/bcm968380gerg/board.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
- */
-
-#include <common.h>
diff --git a/board/bsh/imx8mn_smm_s2/spl.c b/board/bsh/imx8mn_smm_s2/spl.c
index ce0504a..5a77d28 100644
--- a/board/bsh/imx8mn_smm_s2/spl.c
+++ b/board/bsh/imx8mn_smm_s2/spl.c
@@ -13,6 +13,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/gpio.h>
+#include <asm/sections.h>
#include <dm/device.h>
#include <dm/uclass.h>
diff --git a/board/cloos/imx8mm_phg/spl.c b/board/cloos/imx8mm_phg/spl.c
index e63904e..0c3a013 100644
--- a/board/cloos/imx8mm_phg/spl.c
+++ b/board/cloos/imx8mm_phg/spl.c
@@ -19,6 +19,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/ddr.h>
+#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
diff --git a/board/cobra5272/README b/board/cobra5272/README
index 11abcfa..0b07148 100644
--- a/board/cobra5272/README
+++ b/board/cobra5272/README
@@ -1,6 +1,6 @@
File: README.COBRA5272
Author: Florian Schlote for Sentec elektronik (linux@sentec-elektronik.de)
-Contents: This is the README of u-boot (Universal bootloader) for our
+Contents: This is the README of U-Boot (Universal bootloader) for our
COBRA5272 board.
Version: v01.00
Date: Tue Mar 30 00:28:33 CEST 2004
@@ -31,7 +31,7 @@
to u-boot-x-x-x/board/cobra5272/README and
to the comments in u-boot-x-x-x/include/configs/cobra5272.h
-Configuring u-boot is done by commenting/uncommenting preprocessor defines.
+Configuring U-Boot is done by commenting/uncommenting preprocessor defines.
Default configuration is
@@ -48,10 +48,10 @@
#-----------------------------------
-# u-boot FLASH version & RAM version
+# U-Boot FLASH version & RAM version
#-----------------------------------
-The u-boot bootloader for Coldfire processors can be configured
+The U-Boot bootloader for Coldfire processors can be configured
1. as a standalone bootloader residing in flash & relocating itself to RAM on
startup automatically => "FLASH version"
@@ -60,7 +60,7 @@
prestage bootloader ("chainloading") & is running only from the RAM address it
is linked to => "RAM version"
- This version may be very helpful when installing u-boot for the first time
+ This version may be very helpful when installing U-Boot for the first time
since it can be used to make available s. th. like a "bootstrap
mechanism".
@@ -71,7 +71,7 @@
Flash version
------------------------------
-Compile u-boot
+Compile U-Boot
in dir ./u-boot-x-x-x/
@@ -81,14 +81,14 @@
CONFIG_MONITOR_IS_IN_RAM has to be not present in the file
- => u-boot as single bootloader starting from flash
+ => U-Boot as single bootloader starting from flash
in configs/cobra5272_defconfig CONFIG_TEXT_BASE should be
CONFIG_TEXT_BASE=0xffe00000
- => linking address for u-boot as single bootloader stored in flash
+ => linking address for U-Boot as single bootloader stored in flash
then:
@@ -116,7 +116,7 @@
CONFIG_MONITOR_IS_IN_RAM=y
- => u-boot as RAM version, chainloaded by another bootloader or using bdm cable
+ => U-Boot as RAM version, chainloaded by another bootloader or using bdm cable
in configs/cobra5272_defconfig CONFIG_TEXT_BASE should be
diff --git a/board/compulab/cl-som-imx7/spl.c b/board/compulab/cl-som-imx7/spl.c
index 5d4c4d3..98c3b83 100644
--- a/board/compulab/cl-som-imx7/spl.c
+++ b/board/compulab/cl-som-imx7/spl.c
@@ -16,6 +16,7 @@
#include <asm/arch-mx7/mx7-pins.h>
#include <asm/arch-mx7/clock.h>
#include <asm/arch-mx7/mx7-ddr.h>
+#include <asm/sections.h>
#include "common.h"
#ifdef CONFIG_FSL_ESDHC_IMX
diff --git a/board/compulab/imx8mm-cl-iot-gate/spl.c b/board/compulab/imx8mm-cl-iot-gate/spl.c
index d2d2026..19c1acd 100644
--- a/board/compulab/imx8mm-cl-iot-gate/spl.c
+++ b/board/compulab/imx8mm-cl-iot-gate/spl.c
@@ -21,6 +21,7 @@
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/gpio.h>
#include <asm/arch/ddr.h>
+#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
diff --git a/board/comtrend/ar5315u/Makefile b/board/comtrend/ar5315u/Makefile
deleted file mode 100644
index 25656a8..0000000
--- a/board/comtrend/ar5315u/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += ar-5315u.o
diff --git a/board/comtrend/ar5315u/ar-5315u.c b/board/comtrend/ar5315u/ar-5315u.c
deleted file mode 100644
index 3437985..0000000
--- a/board/comtrend/ar5315u/ar-5315u.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
- */
-
-#include <common.h>
diff --git a/board/comtrend/ar5387un/Makefile b/board/comtrend/ar5387un/Makefile
deleted file mode 100644
index 572ae1f..0000000
--- a/board/comtrend/ar5387un/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += ar-5387un.o
diff --git a/board/comtrend/ar5387un/ar-5387un.c b/board/comtrend/ar5387un/ar-5387un.c
deleted file mode 100644
index 1e4b728..0000000
--- a/board/comtrend/ar5387un/ar-5387un.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- */
-
-#include <common.h>
diff --git a/board/comtrend/ct5361/Makefile b/board/comtrend/ct5361/Makefile
deleted file mode 100644
index 8b41c4a..0000000
--- a/board/comtrend/ct5361/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += ct-5361.o
diff --git a/board/comtrend/ct5361/ct-5361.c b/board/comtrend/ct5361/ct-5361.c
deleted file mode 100644
index 1e4b728..0000000
--- a/board/comtrend/ct5361/ct-5361.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- */
-
-#include <common.h>
diff --git a/board/comtrend/vr3032u/Makefile b/board/comtrend/vr3032u/Makefile
deleted file mode 100644
index 3542fea..0000000
--- a/board/comtrend/vr3032u/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += vr-3032u.o
diff --git a/board/comtrend/vr3032u/vr-3032u.c b/board/comtrend/vr3032u/vr-3032u.c
deleted file mode 100644
index 1e4b728..0000000
--- a/board/comtrend/vr3032u/vr-3032u.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- */
-
-#include <common.h>
diff --git a/board/comtrend/wap5813n/Makefile b/board/comtrend/wap5813n/Makefile
deleted file mode 100644
index b8d4a6d..0000000
--- a/board/comtrend/wap5813n/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += wap-5813n.o
diff --git a/board/comtrend/wap5813n/wap-5813n.c b/board/comtrend/wap5813n/wap-5813n.c
deleted file mode 100644
index 1e4b728..0000000
--- a/board/comtrend/wap5813n/wap-5813n.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- */
-
-#include <common.h>
diff --git a/board/conclusive/kstr-sama5d27/Kconfig b/board/conclusive/kstr-sama5d27/Kconfig
new file mode 100644
index 0000000..572551c
--- /dev/null
+++ b/board/conclusive/kstr-sama5d27/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_KSTR_SAMA5D27
+
+config SYS_BOARD
+ default "kstr-sama5d27"
+
+config SYS_VENDOR
+ default "conclusive"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "kstr-sama5d27"
+
+endif
diff --git a/board/conclusive/kstr-sama5d27/MAINTAINERS b/board/conclusive/kstr-sama5d27/MAINTAINERS
new file mode 100644
index 0000000..b788228
--- /dev/null
+++ b/board/conclusive/kstr-sama5d27/MAINTAINERS
@@ -0,0 +1,9 @@
+CONCLUSIVE KSTR-SAMA5D27 BOARD
+M: Jakub Klama <jakub@conclusive.pl>
+M: Artur Rojek <artur@conclusive.pl>
+S: Maintained
+F: board/conclusive/kstr-sama5d27
+F: include/configs/kstr-sama5d27.h
+F: configs/kstr_sama5d27_defconfig
+F: arch/arm/dts/at91-kstr-sama5d27.dts
+F: arch/arm/dts/at91-kstr-sama5d27-u-boot.dtsi
diff --git a/board/conclusive/kstr-sama5d27/Makefile b/board/conclusive/kstr-sama5d27/Makefile
new file mode 100644
index 0000000..edf7d1c
--- /dev/null
+++ b/board/conclusive/kstr-sama5d27/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019-2023 Conclusive Engineering Sp. z o. o.
+
+obj-y += kstr-sama5d27.o
diff --git a/board/conclusive/kstr-sama5d27/kstr-sama5d27.c b/board/conclusive/kstr-sama5d27/kstr-sama5d27.c
new file mode 100644
index 0000000..1b765b1
--- /dev/null
+++ b/board/conclusive/kstr-sama5d27/kstr-sama5d27.c
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * kstr-sama5d27.c - Board init file for Conclusive KSTR-SAMA5D27 board
+ * Copyright (C) 2021-2023 Conclusive Engineering Sp. z o. o.
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <init.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5d2.h>
+#include <linux/delay.h>
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+#include <asm/arch/atmel_usba_udc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+static void board_uart1_hw_init(void)
+{
+ /* URXD1 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, ATMEL_PIO_PUEN_MASK);
+ /* UTXD1 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0);
+ at91_periph_clk_enable(ATMEL_ID_UART1);
+}
+
+void board_debug_uart_init(void)
+{
+ board_uart1_hw_init();
+}
+#endif
+
+void board_lan8720a_init(void)
+{
+ /* LAN8720A_nRST */
+ atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, 0);
+ /*
+ * Force 0 on RXER/PHYAD0. LAN8720A chipset will latch with address 0 on
+ * MDIO bus.
+ */
+ atmel_pio4_set_pio_output(AT91_PIO_PORTB, 17, 0);
+ /* Minimal delay of reset signal is 25 ms */
+ mdelay(30);
+ /* LAN8720A_nRST */
+ atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, 1);
+}
+
+void board_usba_init(void)
+{
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+ /* USB device peripheral initialization: sama5d2_devices.c */
+ at91_udp_hw_init();
+ /* USB device controller drivers/usb/gadget/atmel_usba_udc.c */
+ usba_udc_probe(&pdata);
+#endif
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
+
+ return 0;
+}
+#endif
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ char *wlanaddr = env_get("eth1addr");
+
+ if (wlanaddr)
+ do_fixup_by_compat(blob, "brcm,bcm4329-fmac", "local-mac-address",
+ wlanaddr, strlen(wlanaddr), 1);
+ else
+ printf("Not setting WIFI mac address. Check if EEPROM TLV is correctly set up.\n");
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
+
+ board_usba_init();
+ board_lan8720a_init();
+
+ return 0;
+}
+
+static int settings_r(void)
+{
+ mac_read_from_eeprom();
+ serial_read_from_eeprom(0);
+
+ return 0;
+}
+EVENT_SPY_SIMPLE(EVT_SETTINGS_R, settings_r);
+
+#if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
+int checkboard(void)
+{
+ const char *serial_number;
+
+ serial_number = env_get("serial#");
+ if (!serial_number)
+ printf("Warning: unknown serial number.\n");
+ else
+ printf("S/N: %s\n", serial_number);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ return 0;
+}
+#endif
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+}
+
+static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
+{
+ ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+ ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+ ATMEL_MPDDRC_CR_NR_ROW_13 |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+ ATMEL_MPDDRC_CR_DIC_DS |
+ ATMEL_MPDDRC_CR_ZQ_LONG |
+ ATMEL_MPDDRC_CR_NB_8BANKS |
+ ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+ ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+ ddrc->rtr = 0x511;
+
+ ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
+ (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
+ (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
+ (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
+ (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
+ (2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
+
+ ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
+ (23 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
+ (200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
+ (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
+
+ ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
+ (8 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
+ (8 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
+}
+
+void mem_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+ struct atmel_mpddrc_config ddrc_config;
+ u32 reg;
+
+ ddrc_conf(&ddrc_config);
+
+ at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+ writel(AT91_PMC_DDR, &pmc->scer);
+
+ reg = readl(&mpddrc->io_calibr);
+ reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
+ reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
+ reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
+ reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(101);
+ writel(reg, &mpddrc->io_calibr);
+
+ writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
+ &mpddrc->rd_data_path);
+
+ ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
+
+ writel(0x3, &mpddrc->cal_mr4);
+ writel(64, &mpddrc->tim_cal);
+}
+
+void at91_pmc_init(void)
+{
+ u32 tmp;
+
+ /*
+ * While coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz,
+ * so we need to slow down and configure MCKR accordingly.
+ * This is why we have a special flavor of the switching function.
+ */
+ tmp = AT91_PMC_MCKR_PLLADIV_2 |
+ AT91_PMC_MCKR_MDIV_3 |
+ AT91_PMC_MCKR_CSS_MAIN;
+ at91_mck_init_down(tmp);
+
+ tmp = AT91_PMC_PLLAR_29 |
+ AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+ AT91_PMC_PLLXR_MUL(40) |
+ AT91_PMC_PLLXR_DIV(1);
+ at91_plla_init(tmp);
+
+ tmp = AT91_PMC_MCKR_H32MXDIV |
+ AT91_PMC_MCKR_PLLADIV_2 |
+ AT91_PMC_MCKR_MDIV_3 |
+ AT91_PMC_MCKR_CSS_PLLA;
+ at91_mck_init(tmp);
+}
+#endif
diff --git a/board/congatec/cgtqmx8/spl.c b/board/congatec/cgtqmx8/spl.c
index dea34e4..b432ce2 100644
--- a/board/congatec/cgtqmx8/spl.c
+++ b/board/congatec/cgtqmx8/spl.c
@@ -10,6 +10,7 @@
#include <init.h>
#include <log.h>
#include <spl.h>
+#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c
index 3b90ae7..db855c1 100644
--- a/board/coreboot/coreboot/coreboot.c
+++ b/board/coreboot/coreboot/coreboot.c
@@ -10,6 +10,8 @@
#include <asm/cb_sysinfo.h>
#include <asm/global_data.h>
+DECLARE_GLOBAL_DATA_PTR;
+
int board_early_init_r(void)
{
/*
@@ -54,14 +56,12 @@
return 0;
fallback:
-#ifdef CONFIG_OF_CONTROL
- DECLARE_GLOBAL_DATA_PTR;
+ if (IS_ENABLED(CONFIG_OF_CONTROL)) {
+ model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
- model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
-
- if (model)
- printf("Model: %s\n", model);
-#endif
+ if (model)
+ printf("Model: %s\n", model);
+ }
return checkboard();
}
diff --git a/board/cortina/presidio-asic/presidio.c b/board/cortina/presidio-asic/presidio.c
index aae0a5d..fdfa3af 100644
--- a/board/cortina/presidio-asic/presidio.c
+++ b/board/cortina/presidio-asic/presidio.c
@@ -4,6 +4,7 @@
*
*/
#include <common.h>
+#include <event.h>
#include <init.h>
#include <malloc.h>
#include <errno.h>
@@ -121,7 +122,7 @@
}
#ifdef CONFIG_LAST_STAGE_INIT
-int last_stage_init(void)
+static int last_stage_init(void)
{
u32 val;
@@ -134,4 +135,5 @@
return 0;
}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
#endif
diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dns325/dns325.c
index 055783f..8ebfe4c 100644
--- a/board/d-link/dns325/dns325.c
+++ b/board/d-link/dns325/dns325.c
@@ -89,6 +89,7 @@
kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1);
kw_gpio_set_value(DNS325_GPIO_SATA0_EN , 1);
+ kw_gpio_set_value(DNS325_GPIO_SATA1_EN , 1);
return 0;
}
diff --git a/board/data_modul/common/common.c b/board/data_modul/common/common.c
index bf9a114..a6761c2 100644
--- a/board/data_modul/common/common.c
+++ b/board/data_modul/common/common.c
@@ -30,6 +30,8 @@
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+#define DDRC_ECCCFG0_ECC_MODE_MASK 0x7
+
u8 dmo_get_memcfg(void)
{
struct gpio_desc gpio[4];
@@ -58,8 +60,16 @@
int board_phys_sdram_size(phys_size_t *size)
{
u8 memcfg = dmo_get_memcfg();
+ u8 ecc = 0;
- *size = (4ULL >> ((memcfg >> 1) & 0x3)) * SZ_1G;
+ *size = 4ULL >> ((memcfg >> 1) & 0x3);
+
+ if (IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)) {
+ /* 896 MiB, i.e. 1 GiB without 12.5% reserved for in-band ECC */
+ ecc = readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK;
+ }
+
+ *size *= SZ_1G - (ecc ? (SZ_1G / 8) : 0);
return 0;
}
@@ -100,6 +110,12 @@
}
ddr_init(dram_timing_info[memcfg]);
+
+ if (IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)) {
+ printf("DDR: Inline ECC %sabled\n",
+ (readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK) ?
+ "en" : "dis");
+ }
}
void dmo_board_init_f(const iomux_v3_cfg_t wdog_pad,
diff --git a/board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c b/board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c
index 04cef3a..0ad4000 100644
--- a/board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c
+++ b/board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c
@@ -19,47 +19,66 @@
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa3080020 },
{ 0x3d400020, 0x1303 },
- { 0x3d400024, 0x1c79100 },
+ { 0x3d400024, 0x1c7cf80 },
{ 0x3d400064, 0x710106 },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d400070, 0x7027fd4 },
+#else
{ 0x3d400070, 0x7027f90 },
+#endif
{ 0x3d400074, 0x790 },
- { 0x3d4000d0, 0xc0030720 },
+ { 0x3d4000d0, 0xc0030721 },
{ 0x3d4000d4, 0xb80000 },
- { 0x3d4000dc, 0xe40036 },
- { 0x3d4000e0, 0x330000 },
+ { 0x3d4000dc, 0xf4003f },
+ { 0x3d4000e0, 0xf30000 },
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
- { 0x3d400100, 0x1e262028 },
- { 0x3d400104, 0x7073b },
+ { 0x3d400100, 0x1f262028 },
+ { 0x3d400104, 0x8083b },
{ 0x3d40010c, 0xe0e000 },
{ 0x3d400110, 0x11040a11 },
- { 0x3d400114, 0x2050e0e },
- { 0x3d400118, 0x1010008 },
- { 0x3d40011c, 0x501 },
- { 0x3d400130, 0x20700 },
+ { 0x3d400114, 0x2050f0f },
+ { 0x3d400118, 0x1010009 },
+ { 0x3d40011c, 0x502 },
+ { 0x3d400130, 0x20800 },
{ 0x3d400134, 0xe100002 },
{ 0x3d400138, 0x10d },
{ 0x3d400144, 0xbb005e },
- { 0x3d400180, 0x3a5001c },
- { 0x3d400184, 0x2f071e5 },
+ { 0x3d400180, 0x3a6001d },
+ { 0x3d400184, 0x2f071f4 },
{ 0x3d400188, 0x0 },
- { 0x3d400190, 0x49b820c },
+ { 0x3d400190, 0x4a3820e },
{ 0x3d400194, 0x80303 },
- { 0x3d4001b4, 0x1b0c },
+ { 0x3d4001b4, 0x230e },
{ 0x3d4001a0, 0xe0400018 },
{ 0x3d4001a4, 0xdf00e4 },
{ 0x3d4001a8, 0x80000000 },
{ 0x3d4001b0, 0x11 },
- { 0x3d4001c0, 0x1 },
+ { 0x3d4001c0, 0x7 },
{ 0x3d4001c4, 0x1 },
- { 0x3d4000f4, 0xc99 },
- { 0x3d400108, 0x810191a },
+ { 0x3d4000f4, 0x799 },
+ { 0x3d400108, 0x9141c1c },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d400200, 0x14 },
+#else
{ 0x3d400200, 0x17 },
+#endif
+ { 0x3d400208, 0x0 },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d40020c, 0x14141400 },
+#else
{ 0x3d40020c, 0x0 },
+#endif
{ 0x3d400210, 0x1f1f },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d400204, 0x50505 },
+ { 0x3d400214, 0x4040404 },
+ { 0x3d400218, 0x4040404 },
+#else
{ 0x3d400204, 0x80808 },
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0x7070707 },
+#endif
{ 0x3d40021c, 0xf0f },
{ 0x3d400250, 0x1705 },
{ 0x3d400254, 0x2c },
@@ -78,7 +97,7 @@
{ 0x3d402050, 0x20d000 },
{ 0x3d402064, 0xc001c },
{ 0x3d4020dc, 0x840000 },
- { 0x3d4020e0, 0x330000 },
+ { 0x3d4020e0, 0xf30000 },
{ 0x3d4020e8, 0x660048 },
{ 0x3d4020ec, 0x160048 },
{ 0x3d402100, 0xa040305 },
@@ -88,7 +107,7 @@
{ 0x3d402110, 0x2040202 },
{ 0x3d402114, 0x2030202 },
{ 0x3d402118, 0x1010004 },
- { 0x3d40211c, 0x301 },
+ { 0x3d40211c, 0x302 },
{ 0x3d402130, 0x20300 },
{ 0x3d402134, 0xa100002 },
{ 0x3d402138, 0x1d },
@@ -97,13 +116,13 @@
{ 0x3d402190, 0x3818200 },
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
- { 0x3d4020f4, 0xc99 },
+ { 0x3d4020f4, 0x599 },
{ 0x3d403020, 0x1001 },
{ 0x3d403024, 0xc3500 },
{ 0x3d403050, 0x20d000 },
{ 0x3d403064, 0x30007 },
{ 0x3d4030dc, 0x840000 },
- { 0x3d4030e0, 0x330000 },
+ { 0x3d4030e0, 0xf30000 },
{ 0x3d4030e8, 0x660048 },
{ 0x3d4030ec, 0x160048 },
{ 0x3d403100, 0xa010102 },
@@ -113,7 +132,7 @@
{ 0x3d403110, 0x2040202 },
{ 0x3d403114, 0x2030202 },
{ 0x3d403118, 0x1010004 },
- { 0x3d40311c, 0x301 },
+ { 0x3d40311c, 0x302 },
{ 0x3d403130, 0x20300 },
{ 0x3d403134, 0xa100002 },
{ 0x3d403138, 0x8 },
@@ -122,7 +141,7 @@
{ 0x3d403190, 0x3818200 },
{ 0x3d403194, 0x80303 },
{ 0x3d4031b4, 0x100 },
- { 0x3d4030f4, 0xc99 },
+ { 0x3d4030f4, 0x599 },
{ 0x3d400028, 0x0 },
};
@@ -260,16 +279,16 @@
{ 0x212149, 0xeba },
{ 0x213049, 0xeba },
{ 0x213149, 0xeba },
- { 0x43, 0xe7 },
- { 0x1043, 0xe7 },
- { 0x2043, 0xe7 },
- { 0x3043, 0xe7 },
- { 0x4043, 0xe7 },
- { 0x5043, 0xe7 },
- { 0x6043, 0xe7 },
- { 0x7043, 0xe7 },
- { 0x8043, 0xe7 },
- { 0x9043, 0xe7 },
+ { 0x43, 0x3ff },
+ { 0x1043, 0x3ff },
+ { 0x2043, 0x3ff },
+ { 0x3043, 0x3ff },
+ { 0x4043, 0x3ff },
+ { 0x5043, 0x3ff },
+ { 0x6043, 0x3ff },
+ { 0x7043, 0x3ff },
+ { 0x8043, 0x3ff },
+ { 0x9043, 0x3ff },
{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
@@ -319,19 +338,15 @@
{ 0x200f6, 0x0 },
{ 0x200f7, 0xf000 },
{ 0x20025, 0x0 },
- { 0x2002d, 0x0 },
- { 0x12002d, 0x0 },
- { 0x22002d, 0x0 },
+ { 0x2002d, 0x1 },
+ { 0x12002d, 0x1 },
+ { 0x22002d, 0x1 },
{ 0x2007d, 0x212 },
{ 0x12007d, 0x212 },
{ 0x22007d, 0x212 },
{ 0x2007c, 0x61 },
{ 0x12007c, 0x61 },
{ 0x22007c, 0x61 },
- { 0x1004a, 0x500 },
- { 0x1104a, 0x500 },
- { 0x1204a, 0x500 },
- { 0x1304a, 0x500 },
{ 0x2002c, 0x0 },
};
@@ -1061,7 +1076,7 @@
/* P0 message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xe94 },
+ { 0x54003, 0xe96 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
@@ -1070,26 +1085,26 @@
{ 0x5400b, 0x2 },
{ 0x5400f, 0x100 },
{ 0x54012, 0x310 },
- { 0x54019, 0x36e4 },
- { 0x5401a, 0x33 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
- { 0x5401f, 0x36e4 },
- { 0x54020, 0x33 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
- { 0x54032, 0xe400 },
- { 0x54033, 0x3336 },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0xf33f },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
- { 0x54038, 0xe400 },
- { 0x54039, 0x3336 },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0xf33f },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1111,25 +1126,25 @@
{ 0x5400f, 0x100 },
{ 0x54012, 0x310 },
{ 0x54019, 0x84 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0x8400 },
- { 0x54033, 0x3300 },
+ { 0x54033, 0xf300 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
- { 0x54039, 0x3300 },
+ { 0x54039, 0xf300 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1151,25 +1166,25 @@
{ 0x5400f, 0x100 },
{ 0x54012, 0x310 },
{ 0x54019, 0x84 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0x8400 },
- { 0x54033, 0x3300 },
+ { 0x54033, 0xf300 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
- { 0x54039, 0x3300 },
+ { 0x54039, 0xf300 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1180,7 +1195,7 @@
/* P0 2D message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xe94 },
+ { 0x54003, 0xe96 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
@@ -1190,26 +1205,26 @@
{ 0x5400f, 0x100 },
{ 0x54010, 0x1f7f },
{ 0x54012, 0x310 },
- { 0x54019, 0x36e4 },
- { 0x5401a, 0x33 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
- { 0x5401f, 0x36e4 },
- { 0x54020, 0x33 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
- { 0x54032, 0xe400 },
- { 0x54033, 0x3336 },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0xf33f },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
- { 0x54038, 0xe400 },
- { 0x54039, 0x3336 },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0xf33f },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1699,9 +1714,9 @@
{ 0x400d7, 0x20b },
{ 0x2003a, 0x2 },
{ 0x200be, 0x3 },
- { 0x2000b, 0x419 },
+ { 0x2000b, 0x41a },
{ 0x2000c, 0xe9 },
- { 0x2000d, 0x91c },
+ { 0x2000d, 0x91d },
{ 0x2000e, 0x2c },
{ 0x12000b, 0x70 },
{ 0x12000c, 0x19 },
@@ -1804,8 +1819,8 @@
static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
{
- /* P0 3733mts 1D */
- .drate = 3733,
+ /* P0 3600mts 1D */
+ .drate = 3600,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
@@ -1825,8 +1840,8 @@
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
},
{
- /* P0 3733mts 2D */
- .drate = 3733,
+ /* P0 3600mts 2D */
+ .drate = 3600,
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
@@ -1845,5 +1860,19 @@
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 3733, 400, 100, },
+ .fsp_table = { 3600, 400, 100, },
};
+
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+void board_dram_ecc_scrub(void)
+{
+ ddrc_inline_ecc_scrub(0x0,0x7ffffff);
+ ddrc_inline_ecc_scrub(0x8000000,0xfffffff);
+ ddrc_inline_ecc_scrub(0x10000000,0x17ffffff);
+ ddrc_inline_ecc_scrub(0x18000000,0x1fffffff);
+ ddrc_inline_ecc_scrub(0x20000000,0x27ffffff);
+ ddrc_inline_ecc_scrub(0x28000000,0x2fffffff);
+ ddrc_inline_ecc_scrub(0x30000000,0x37ffffff);
+ ddrc_inline_ecc_scrub_end(0x0,0x3fffffff);
+}
+#endif
diff --git a/board/data_modul/imx8mp_edm_sbc/spl.c b/board/data_modul/imx8mp_edm_sbc/spl.c
index 2fdd95a..a3600c8 100644
--- a/board/data_modul/imx8mp_edm_sbc/spl.c
+++ b/board/data_modul/imx8mp_edm_sbc/spl.c
@@ -68,6 +68,11 @@
/* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */
pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c);
+ /* DRAM Vdd1 always FPWM */
+ pmic_reg_write(dev, PCA9450_BUCK5CTRL, 0x0d);
+ /* DRAM Vdd2/Vddq always FPWM */
+ pmic_reg_write(dev, PCA9450_BUCK6CTRL, 0x0d);
+
/* Set LDO4 and CONFIG2 to enable the I2C level translator. */
pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59);
pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
@@ -107,7 +112,7 @@
spl_boot_list[4] = BOOT_DEVICE_NONE;
}
-unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long sect)
+unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long sect)
{
const u32 boot_dev = spl_boot_device();
int part;
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index 474dca7..05053a8 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
*
* Based on da830evm.c. Original Copyrights follow:
*
diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c
index 5ffd420..9738e2b 100644
--- a/board/davinci/da8xxevm/omapl138_lcdk.c
+++ b/board/davinci/da8xxevm/omapl138_lcdk.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* Based on da850evm.c. Original Copyrights follow:
*
diff --git a/board/devboards/dbm-soc1/Makefile b/board/devboards/dbm-soc1/Makefile
deleted file mode 100644
index 88621b0..0000000
--- a/board/devboards/dbm-soc1/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2018 Marek Vasut <marex@denx.de>
-
-obj-y := socfpga.o
diff --git a/board/devboards/dbm-soc1/socfpga.c b/board/devboards/dbm-soc1/socfpga.c
deleted file mode 100644
index a907ee6..0000000
--- a/board/devboards/dbm-soc1/socfpga.c
+++ /dev/null
@@ -1,5 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Marek Vasut <marex@denx.de>
- */
-#include <common.h>
diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
index 20a330c..e6d5657 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
@@ -21,6 +21,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
+#include <asm/sections.h>
#include <asm/system.h>
#include <errno.h>
#include <fuse.h>
diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
index 760ea4b..5f12d78 100644
--- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
+++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
@@ -5,16 +5,13 @@
#include <common.h>
#include <asm/arch/clock.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/ddr.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <dm.h>
-#include <dt-bindings/clock/imx8mp-clock.h>
#include <env.h>
#include <env_internal.h>
#include <i2c_eeprom.h>
-#include <linux/bitfield.h>
#include <malloc.h>
#include <net.h>
#include <miiphy.h>
@@ -34,9 +31,11 @@
int board_phys_sdram_size(phys_size_t *size)
{
const u16 memsz[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 };
+ const u8 ecc = readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK;
u8 memcfg = dh_get_memcfg();
- *size = (u64)memsz[memcfg] << 20ULL;
+ /* 896 kiB, i.e. 1 MiB without 12.5% reserved for in-band ECC */
+ *size = (u64)memsz[memcfg] * (SZ_1M - (ecc ? (SZ_1M / 8) : 0));
return 0;
}
@@ -120,227 +119,3 @@
{
return prio ? ENVL_UNKNOWN : ENVL_SPI_FLASH;
}
-
-static const char *iomuxc_compat = "fsl,imx8mp-iomuxc";
-static const char *lan_compat = "ethernet-phy-id0007.c110";
-static const char *ksz_compat = "ethernet-phy-id0022.1642";
-
-static int dh_dt_patch_som_eqos(const void *fdt_blob)
-{
- const void __iomem *mux = (void __iomem *)IOMUXC_BASE_ADDR +
- FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_ENET_RX_CTL__GPIO1_IO24);
- int mac_node, mdio_node, iomuxc_node, ksz_node, lan_node, subnode;
- const char *mac_compat = "nxp,imx8mp-dwmac-eqos";
- void *blob = (void *)fdt_blob;
- const fdt32_t *clk_prop;
- bool is_gigabit;
- u32 handle;
- u32 clk[6];
-
- setbits_le32(mux, IOMUX_CONFIG_SION);
- is_gigabit = !(readl(GPIO1_BASE_ADDR) & BIT(24));
- clrbits_le32(mux, IOMUX_CONFIG_SION);
-
- /* Adjust EQoS node for Gigabit KSZ9131RNXI or Fast LAN8740Ai PHY */
- mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
- if (mac_node < 0)
- return 0;
-
- mdio_node = fdt_first_subnode(blob, mac_node);
- if (mdio_node < 0)
- return 0;
-
- /* KSZ9131RNXI */
- ksz_node = fdt_node_offset_by_compatible(blob, mdio_node, ksz_compat);
- if (ksz_node < 0)
- return 0;
-
- /* LAN8740Ai */
- lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat);
- if (lan_node < 0)
- return 0;
-
- iomuxc_node = fdt_node_offset_by_compatible(blob, -1, iomuxc_compat);
- if (iomuxc_node < 0)
- return 0;
-
- /*
- * The code below adjusts the following DT properties:
- * - assigned-clock-parents .. 125 MHz RGMII / 50 MHz RMII ref clock
- * - assigned-clock-rates .... 125 MHz RGMII / 50 MHz RMII ref clock
- * - phy-handle .............. KSZ9131RNXI RGMII / LAN8740Ai RMII
- * - phy-mode ................ RGMII / RMII
- * - pinctrl-0 ............... RGMII / RMII
- * - PHY subnode status ...... "disabled"/"okay" per RGMII / RMII
- */
-
- /* Perform all inplace changes first, string changes last. */
- clk_prop = fdt_getprop(blob, mac_node, "assigned-clock-parents", NULL);
- if (!clk_prop)
- return 0;
- clk[0] = clk_prop[0];
- clk[1] = cpu_to_fdt32(IMX8MP_SYS_PLL1_266M);
- clk[2] = clk_prop[2];
- clk[3] = cpu_to_fdt32(IMX8MP_SYS_PLL2_100M);
- clk[4] = clk_prop[4];
- clk[5] = is_gigabit ? cpu_to_fdt32(IMX8MP_SYS_PLL2_125M) :
- cpu_to_fdt32(IMX8MP_SYS_PLL2_50M);
- fdt_setprop_inplace(blob, mac_node, "assigned-clock-parents",
- clk, 6 * sizeof(u32));
-
- clk[0] = cpu_to_fdt32(0);
- clk[1] = cpu_to_fdt32(100000000);
- clk[2] = is_gigabit ? cpu_to_fdt32(125000000) :
- cpu_to_fdt32(50000000);
- fdt_setprop_inplace(blob, mac_node, "assigned-clock-rates",
- clk, 3 * sizeof(u32));
-
- handle = fdt_get_phandle(blob, is_gigabit ? ksz_node : lan_node);
- fdt_setprop_inplace_u32(blob, mac_node, "phy-handle", handle);
-
- fdt_for_each_subnode(subnode, blob, iomuxc_node) {
- if (!strstr(fdt_get_name(blob, subnode, NULL),
- is_gigabit ? "eqos-rgmii" : "eqos-rmii"))
- continue;
-
- handle = fdt_get_phandle(blob, subnode);
- fdt_setprop_inplace_u32(blob, mac_node, "pinctrl-0", handle);
- break;
- }
-
- fdt_setprop_string(blob, mac_node, "phy-mode",
- is_gigabit ? "rgmii-id" : "rmii");
-
- mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
- mdio_node = fdt_first_subnode(blob, mac_node);
- ksz_node = fdt_node_offset_by_compatible(blob, mdio_node, ksz_compat);
- fdt_setprop_string(blob, ksz_node, "status",
- is_gigabit ? "okay" : "disabled");
-
- mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
- mdio_node = fdt_first_subnode(blob, mac_node);
- lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat);
- fdt_setprop_string(blob, lan_node, "status",
- is_gigabit ? "disabled" : "okay");
-
- return 0;
-}
-
-static int dh_dt_patch_som_fec(const void *fdt_blob)
-{
- const void __iomem *mux = (void __iomem *)IOMUXC_BASE_ADDR +
- FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI1_TXFS__GPIO4_IO10);
- int mac_node, mdio_node, iomuxc_node, lan_node, phy_node, subnode;
- const char *mac_compat = "fsl,imx8mp-fec";
- void *blob = (void *)fdt_blob;
- const fdt32_t *clk_prop;
- bool is_gigabit;
- u32 handle;
- u32 clk[8];
-
- setbits_le32(mux, IOMUX_CONFIG_SION);
- is_gigabit = !(readl(GPIO4_BASE_ADDR) & BIT(10));
- clrbits_le32(mux, IOMUX_CONFIG_SION);
-
- /* Test for non-default SoM with 100/Full PHY attached to FEC */
- if (is_gigabit)
- return 0;
-
- /* Adjust FEC node for Fast LAN8740Ai PHY */
- mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
- if (mac_node < 0)
- return 0;
-
- /* Optional PHY pointed to by phy-handle, possibly on carrier board */
- phy_node = fdtdec_lookup_phandle(blob, mac_node, "phy-handle");
- if (phy_node > 0) {
- fdt_setprop_string(blob, phy_node, "status", "disabled");
- mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
- }
-
- mdio_node = fdt_first_subnode(blob, mac_node);
- if (mdio_node < 0)
- return 0;
-
- /* LAN8740Ai */
- lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat);
- if (lan_node < 0)
- return 0;
-
- iomuxc_node = fdt_node_offset_by_compatible(blob, -1, iomuxc_compat);
- if (iomuxc_node < 0)
- return 0;
-
- /*
- * The code below adjusts the following DT properties:
- * - assigned-clock-parents .. 50 MHz RMII ref clock
- * - assigned-clock-rates .... 50 MHz RMII ref clock
- * - phy-handle .............. LAN8740Ai RMII
- * - phy-mode ................ RMII
- * - pinctrl-0 ............... RMII
- * - PHY subnode status ...... "okay" for RMII PHY
- */
-
- /* Perform all inplace changes first, string changes last. */
- clk_prop = fdt_getprop(blob, mac_node, "assigned-clock-parents", NULL);
- if (!clk_prop)
- return 0;
- clk[0] = clk_prop[0];
- clk[1] = cpu_to_fdt32(IMX8MP_SYS_PLL1_266M);
- clk[2] = clk_prop[2];
- clk[3] = cpu_to_fdt32(IMX8MP_SYS_PLL2_100M);
- clk[4] = clk_prop[4];
- clk[5] = cpu_to_fdt32(IMX8MP_SYS_PLL2_50M);
- clk[6] = clk_prop[6];
- clk[7] = cpu_to_fdt32(IMX8MP_SYS_PLL2_50M);
- fdt_setprop_inplace(blob, mac_node, "assigned-clock-parents",
- clk, 8 * sizeof(u32));
-
- clk[0] = cpu_to_fdt32(0);
- clk[1] = cpu_to_fdt32(100000000);
- clk[2] = cpu_to_fdt32(50000000);
- clk[3] = cpu_to_fdt32(0);
- fdt_setprop_inplace(blob, mac_node, "assigned-clock-rates",
- clk, 4 * sizeof(u32));
-
- handle = fdt_get_phandle(blob, lan_node);
- fdt_setprop_inplace_u32(blob, mac_node, "phy-handle", handle);
-
- fdt_for_each_subnode(subnode, blob, iomuxc_node) {
- if (!strstr(fdt_get_name(blob, subnode, NULL), "fec-rmii"))
- continue;
-
- handle = fdt_get_phandle(blob, subnode);
- fdt_setprop_inplace_u32(blob, mac_node, "pinctrl-0", handle);
- break;
- }
-
- fdt_setprop_string(blob, mac_node, "phy-mode", "rmii");
- mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
- mdio_node = fdt_first_subnode(blob, mac_node);
- lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat);
- fdt_setprop_string(blob, lan_node, "status", "okay");
-
- return 0;
-}
-
-static int dh_dt_patch_som(const void *fdt_blob)
-{
- int ret;
-
- /* Do nothing if not i.MX8MP DHCOM SoM */
- ret = fdt_node_check_compatible(fdt_blob, 0, "dh,imx8mp-dhcom-som");
- if (ret)
- return 0;
-
- ret = dh_dt_patch_som_eqos(fdt_blob);
- if (ret)
- return ret;
-
- return dh_dt_patch_som_fec(fdt_blob);
-}
-
-int fdtdec_board_setup(const void *fdt_blob)
-{
- return dh_dt_patch_som(fdt_blob);
-}
diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h
index 7894da3..c4d5117 100644
--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h
+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h
@@ -9,6 +9,12 @@
extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32;
extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32;
+typedef void (*scrub_func_t)(void);
+extern void dh_imx8mp_dhcom_dram_scrub_16g_x32(void);
+extern void dh_imx8mp_dhcom_dram_scrub_32g_x32(void);
+
u8 dh_get_memcfg(void);
+#define DDRC_ECCCFG0_ECC_MODE_MASK 0x7
+
#endif /* __LPDDR4_TIMING_H__ */
diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c b/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c
index 51b8c4c..add7a0b 100644
--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c
+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c
@@ -14,48 +14,62 @@
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa1080020 },
{ 0x3d400020, 0x1323 },
- { 0x3d400024, 0x1c79100 },
- { 0x3d400064, 0x710106 },
+ { 0x3d400024, 0x1b77400 },
+ { 0x3d400064, 0x6d00fc },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d400070, 0x7027fd4 },
+#else
{ 0x3d400070, 0x7027f90 },
+#endif
{ 0x3d400074, 0x790 },
- { 0x3d4000d0, 0xc0030720 },
- { 0x3d4000d4, 0xb80000 },
+ { 0x3d4000d0, 0xc00306df },
+ { 0x3d4000d4, 0xb10000 },
{ 0x3d4000dc, 0xe40036 },
- { 0x3d4000e0, 0x330000 },
+ { 0x3d4000e0, 0xf30000 },
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
- { 0x3d400100, 0x1e262028 },
- { 0x3d400104, 0x7073b },
- { 0x3d40010c, 0xe0e000 },
- { 0x3d400110, 0x11040a11 },
+ { 0x3d400100, 0x1d241e26 },
+ { 0x3d400104, 0x70739 },
+ { 0x3d40010c, 0xd0d000 },
+ { 0x3d400110, 0x11040911 },
{ 0x3d400114, 0x2050e0e },
{ 0x3d400118, 0x1010008 },
{ 0x3d40011c, 0x502 },
{ 0x3d400130, 0x20700 },
{ 0x3d400134, 0xd100002 },
- { 0x3d400138, 0x10d },
- { 0x3d400144, 0xbb005e },
- { 0x3d400180, 0x3a5001c },
- { 0x3d400184, 0x2f071e5 },
+ { 0x3d400138, 0x103 },
+ { 0x3d400144, 0xb4005a },
+ { 0x3d400180, 0x384001b },
+ { 0x3d400184, 0x2d06ddd },
{ 0x3d400188, 0x0 },
- { 0x3d400190, 0x49b820c },
+ { 0x3d400190, 0x49f820c },
{ 0x3d400194, 0x80303 },
- { 0x3d4001b4, 0x1b0c },
+ { 0x3d4001b4, 0x1f0c },
{ 0x3d4001a0, 0xe0400018 },
{ 0x3d4001a4, 0xdf00e4 },
{ 0x3d4001a8, 0x80000000 },
{ 0x3d4001b0, 0x11 },
- { 0x3d4001c0, 0x1 },
+ { 0x3d4001c0, 0x7 },
{ 0x3d4001c4, 0x1 },
{ 0x3d4000f4, 0x799 },
- { 0x3d400108, 0x810191a },
+ { 0x3d400108, 0x8121b1a },
{ 0x3d400200, 0x1f },
{ 0x3d400208, 0x0 },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d40020c, 0x13131300 },
+#else
{ 0x3d40020c, 0x0 },
+#endif
{ 0x3d400210, 0x1f1f },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d400204, 0x50505 },
+ { 0x3d400214, 0x4040404 },
+ { 0x3d400218, 0x4040404 },
+#else
{ 0x3d400204, 0x80808 },
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0x7070707 },
+#endif
{ 0x3d40021c, 0xf0f },
{ 0x3d400250, 0x1705 },
{ 0x3d400254, 0x2c },
@@ -74,7 +88,7 @@
{ 0x3d402050, 0x20d000 },
{ 0x3d402064, 0xc001c },
{ 0x3d4020dc, 0x840000 },
- { 0x3d4020e0, 0x330000 },
+ { 0x3d4020e0, 0xf30000 },
{ 0x3d4020e8, 0x660048 },
{ 0x3d4020ec, 0x160048 },
{ 0x3d402100, 0xa040305 },
@@ -99,7 +113,7 @@
{ 0x3d403050, 0x20d000 },
{ 0x3d403064, 0x30007 },
{ 0x3d4030dc, 0x840000 },
- { 0x3d4030e0, 0x330000 },
+ { 0x3d4030e0, 0xf30000 },
{ 0x3d4030e8, 0x660048 },
{ 0x3d4030ec, 0x160048 },
{ 0x3d403100, 0xa010102 },
@@ -269,7 +283,7 @@
{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
- { 0x20008, 0x3a5 },
+ { 0x20008, 0x384 },
{ 0x120008, 0x64 },
{ 0x220008, 0x19 },
{ 0x20088, 0x9 },
@@ -315,19 +329,15 @@
{ 0x200f6, 0x0 },
{ 0x200f7, 0xf000 },
{ 0x20025, 0x0 },
- { 0x2002d, 0x0 },
- { 0x12002d, 0x0 },
- { 0x22002d, 0x0 },
+ { 0x2002d, 0x1 },
+ { 0x12002d, 0x1 },
+ { 0x22002d, 0x1 },
{ 0x2007d, 0x212 },
{ 0x12007d, 0x212 },
{ 0x22007d, 0x212 },
{ 0x2007c, 0x61 },
{ 0x12007c, 0x61 },
{ 0x22007c, 0x61 },
- { 0x1004a, 0x500 },
- { 0x1104a, 0x500 },
- { 0x1204a, 0x500 },
- { 0x1304a, 0x500 },
{ 0x2002c, 0x0 },
};
@@ -1057,7 +1067,7 @@
/* P0 message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xe94 },
+ { 0x54003, 0xe10 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
@@ -1067,25 +1077,25 @@
{ 0x5400f, 0x100 },
{ 0x54012, 0x110 },
{ 0x54019, 0x36e4 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x36e4 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
{ 0x54032, 0xe400 },
- { 0x54033, 0x3336 },
+ { 0x54033, 0xf336 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0xe400 },
- { 0x54039, 0x3336 },
+ { 0x54039, 0xf336 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1107,25 +1117,25 @@
{ 0x5400f, 0x100 },
{ 0x54012, 0x110 },
{ 0x54019, 0x84 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
{ 0x54032, 0x8400 },
- { 0x54033, 0x3300 },
+ { 0x54033, 0xf300 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
- { 0x54039, 0x3300 },
+ { 0x54039, 0xf300 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1147,25 +1157,25 @@
{ 0x5400f, 0x100 },
{ 0x54012, 0x110 },
{ 0x54019, 0x84 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
{ 0x54032, 0x8400 },
- { 0x54033, 0x3300 },
+ { 0x54033, 0xf300 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
- { 0x54039, 0x3300 },
+ { 0x54039, 0xf300 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1176,7 +1186,7 @@
/* P0 2D message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xe94 },
+ { 0x54003, 0xe10 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
@@ -1187,25 +1197,25 @@
{ 0x54010, 0x1f7f },
{ 0x54012, 0x110 },
{ 0x54019, 0x36e4 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x36e4 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
{ 0x54032, 0xe400 },
- { 0x54033, 0x3336 },
+ { 0x54033, 0xf336 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0xe400 },
- { 0x54039, 0x3336 },
+ { 0x54039, 0xf336 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1695,9 +1705,9 @@
{ 0x400d7, 0x20b },
{ 0x2003a, 0x2 },
{ 0x200be, 0x3 },
- { 0x2000b, 0x419 },
- { 0x2000c, 0xe9 },
- { 0x2000d, 0x91c },
+ { 0x2000b, 0x3f4 },
+ { 0x2000c, 0xe1 },
+ { 0x2000d, 0x8ca },
{ 0x2000e, 0x2c },
{ 0x12000b, 0x70 },
{ 0x12000c, 0x19 },
@@ -1800,8 +1810,8 @@
static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
{
- /* P0 3733mts 1D */
- .drate = 3733,
+ /* P0 3600mts 1D */
+ .drate = 3600,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
@@ -1821,8 +1831,8 @@
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
},
{
- /* P0 3733mts 2D */
- .drate = 3733,
+ /* P0 3600mts 2D */
+ .drate = 3600,
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
@@ -1841,5 +1851,19 @@
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 3733, 400, 100, },
+ .fsp_table = { 3600, 400, 100, },
};
+
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+void dh_imx8mp_dhcom_dram_scrub_16g_x32(void)
+{
+ ddrc_inline_ecc_scrub(0x0,0x3ffffff);
+ ddrc_inline_ecc_scrub(0x4000000,0x7ffffff);
+ ddrc_inline_ecc_scrub(0x8000000,0xbffffff);
+ ddrc_inline_ecc_scrub(0xc000000,0xfffffff);
+ ddrc_inline_ecc_scrub(0x10000000,0x13ffffff);
+ ddrc_inline_ecc_scrub(0x14000000,0x17ffffff);
+ ddrc_inline_ecc_scrub(0x18000000,0x1bffffff);
+ ddrc_inline_ecc_scrub_end(0x0,0x1fffffff);
+}
+#endif
diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c b/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c
index a4c1b12..41b078f 100644
--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c
+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c
@@ -14,47 +14,66 @@
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa3080020 },
{ 0x3d400020, 0x1323 },
- { 0x3d400024, 0x1c79100 },
- { 0x3d400064, 0x710106 },
+ { 0x3d400024, 0x1b77400 },
+ { 0x3d400064, 0x6d00fc },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d400070, 0x7027fd4 },
+#else
{ 0x3d400070, 0x7027f90 },
+#endif
{ 0x3d400074, 0x790 },
- { 0x3d4000d0, 0xc0030720 },
- { 0x3d4000d4, 0xb80000 },
+ { 0x3d4000d0, 0xc00306df },
+ { 0x3d4000d4, 0xb10000 },
{ 0x3d4000dc, 0xe40036 },
- { 0x3d4000e0, 0x330000 },
+ { 0x3d4000e0, 0xf30000 },
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
- { 0x3d400100, 0x1e262028 },
- { 0x3d400104, 0x7073b },
- { 0x3d40010c, 0xe0e000 },
- { 0x3d400110, 0x11040a11 },
+ { 0x3d400100, 0x1d241e26 },
+ { 0x3d400104, 0x70739 },
+ { 0x3d40010c, 0xd0d000 },
+ { 0x3d400110, 0x11040911 },
{ 0x3d400114, 0x2050e0e },
{ 0x3d400118, 0x1010008 },
- { 0x3d40011c, 0x501 },
+ { 0x3d40011c, 0x502 },
{ 0x3d400130, 0x20700 },
- { 0x3d400134, 0xe100002 },
- { 0x3d400138, 0x10d },
- { 0x3d400144, 0xbb005e },
- { 0x3d400180, 0x3a5001c },
- { 0x3d400184, 0x2f071e5 },
+ { 0x3d400134, 0xd100002 },
+ { 0x3d400138, 0x103 },
+ { 0x3d400144, 0xb4005a },
+ { 0x3d400180, 0x384001b },
+ { 0x3d400184, 0x2d06ddd },
{ 0x3d400188, 0x0 },
- { 0x3d400190, 0x49b820c },
+ { 0x3d400190, 0x49f820c },
{ 0x3d400194, 0x80303 },
- { 0x3d4001b4, 0x1b0c },
+ { 0x3d4001b4, 0x1f0c },
{ 0x3d4001a0, 0xe0400018 },
{ 0x3d4001a4, 0xdf00e4 },
{ 0x3d4001a8, 0x80000000 },
{ 0x3d4001b0, 0x11 },
- { 0x3d4001c0, 0x1 },
+ { 0x3d4001c0, 0x7 },
{ 0x3d4001c4, 0x1 },
- { 0x3d4000f4, 0xc99 },
- { 0x3d400108, 0x810191a },
+ { 0x3d4000f4, 0x799 },
+ { 0x3d400108, 0x8121b1a },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d400200, 0x14 },
+#else
{ 0x3d400200, 0x17 },
+#endif
+ { 0x3d400208, 0x0 },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d40020c, 0x14141400 },
+#else
{ 0x3d40020c, 0x0 },
+#endif
{ 0x3d400210, 0x1f1f },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d400204, 0x50505 },
+ { 0x3d400214, 0x4040404 },
+ { 0x3d400218, 0x4040404 },
+#else
{ 0x3d400204, 0x80808 },
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0x7070707 },
+#endif
{ 0x3d40021c, 0xf0f },
{ 0x3d400250, 0x1705 },
{ 0x3d400254, 0x2c },
@@ -73,7 +92,7 @@
{ 0x3d402050, 0x20d000 },
{ 0x3d402064, 0xc001c },
{ 0x3d4020dc, 0x840000 },
- { 0x3d4020e0, 0x330000 },
+ { 0x3d4020e0, 0xf30000 },
{ 0x3d4020e8, 0x660048 },
{ 0x3d4020ec, 0x160048 },
{ 0x3d402100, 0xa040305 },
@@ -83,7 +102,7 @@
{ 0x3d402110, 0x2040202 },
{ 0x3d402114, 0x2030202 },
{ 0x3d402118, 0x1010004 },
- { 0x3d40211c, 0x301 },
+ { 0x3d40211c, 0x302 },
{ 0x3d402130, 0x20300 },
{ 0x3d402134, 0xa100002 },
{ 0x3d402138, 0x1d },
@@ -92,13 +111,13 @@
{ 0x3d402190, 0x3818200 },
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
- { 0x3d4020f4, 0xc99 },
+ { 0x3d4020f4, 0x599 },
{ 0x3d403020, 0x1021 },
{ 0x3d403024, 0xc3500 },
{ 0x3d403050, 0x20d000 },
{ 0x3d403064, 0x30007 },
{ 0x3d4030dc, 0x840000 },
- { 0x3d4030e0, 0x330000 },
+ { 0x3d4030e0, 0xf30000 },
{ 0x3d4030e8, 0x660048 },
{ 0x3d4030ec, 0x160048 },
{ 0x3d403100, 0xa010102 },
@@ -108,7 +127,7 @@
{ 0x3d403110, 0x2040202 },
{ 0x3d403114, 0x2030202 },
{ 0x3d403118, 0x1010004 },
- { 0x3d40311c, 0x301 },
+ { 0x3d40311c, 0x302 },
{ 0x3d403130, 0x20300 },
{ 0x3d403134, 0xa100002 },
{ 0x3d403138, 0x8 },
@@ -117,7 +136,7 @@
{ 0x3d403190, 0x3818200 },
{ 0x3d403194, 0x80303 },
{ 0x3d4031b4, 0x100 },
- { 0x3d4030f4, 0xc99 },
+ { 0x3d4030f4, 0x599 },
{ 0x3d400028, 0x0 },
};
@@ -268,7 +287,7 @@
{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
- { 0x20008, 0x3a5 },
+ { 0x20008, 0x384 },
{ 0x120008, 0x64 },
{ 0x220008, 0x19 },
{ 0x20088, 0x9 },
@@ -314,19 +333,15 @@
{ 0x200f6, 0x0 },
{ 0x200f7, 0xf000 },
{ 0x20025, 0x0 },
- { 0x2002d, 0x0 },
- { 0x12002d, 0x0 },
- { 0x22002d, 0x0 },
+ { 0x2002d, 0x1 },
+ { 0x12002d, 0x1 },
+ { 0x22002d, 0x1 },
{ 0x2007d, 0x212 },
{ 0x12007d, 0x212 },
{ 0x22007d, 0x212 },
{ 0x2007c, 0x61 },
{ 0x12007c, 0x61 },
{ 0x22007c, 0x61 },
- { 0x1004a, 0x500 },
- { 0x1104a, 0x500 },
- { 0x1204a, 0x500 },
- { 0x1304a, 0x500 },
{ 0x2002c, 0x0 },
};
@@ -1056,7 +1071,7 @@
/* P0 message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xe94 },
+ { 0x54003, 0xe10 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
@@ -1066,25 +1081,25 @@
{ 0x5400f, 0x100 },
{ 0x54012, 0x310 },
{ 0x54019, 0x36e4 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x36e4 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0xe400 },
- { 0x54033, 0x3336 },
+ { 0x54033, 0xf336 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0xe400 },
- { 0x54039, 0x3336 },
+ { 0x54039, 0xf336 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1106,25 +1121,25 @@
{ 0x5400f, 0x100 },
{ 0x54012, 0x310 },
{ 0x54019, 0x84 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0x8400 },
- { 0x54033, 0x3300 },
+ { 0x54033, 0xf300 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
- { 0x54039, 0x3300 },
+ { 0x54039, 0xf300 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1146,25 +1161,25 @@
{ 0x5400f, 0x100 },
{ 0x54012, 0x310 },
{ 0x54019, 0x84 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0x8400 },
- { 0x54033, 0x3300 },
+ { 0x54033, 0xf300 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
- { 0x54039, 0x3300 },
+ { 0x54039, 0xf300 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1175,7 +1190,7 @@
/* P0 2D message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xe94 },
+ { 0x54003, 0xe10 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
@@ -1186,25 +1201,25 @@
{ 0x54010, 0x1f7f },
{ 0x54012, 0x310 },
{ 0x54019, 0x36e4 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x36e4 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0xe400 },
- { 0x54033, 0x3336 },
+ { 0x54033, 0xf336 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0xe400 },
- { 0x54039, 0x3336 },
+ { 0x54039, 0xf336 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1694,9 +1709,9 @@
{ 0x400d7, 0x20b },
{ 0x2003a, 0x2 },
{ 0x200be, 0x3 },
- { 0x2000b, 0x419 },
- { 0x2000c, 0xe9 },
- { 0x2000d, 0x91c },
+ { 0x2000b, 0x3f4 },
+ { 0x2000c, 0xe1 },
+ { 0x2000d, 0x8ca },
{ 0x2000e, 0x2c },
{ 0x12000b, 0x70 },
{ 0x12000c, 0x19 },
@@ -1799,8 +1814,8 @@
static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
{
- /* P0 3733mts 1D */
- .drate = 3733,
+ /* P0 3600mts 1D */
+ .drate = 3600,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
@@ -1820,8 +1835,8 @@
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
},
{
- /* P0 3733mts 2D */
- .drate = 3733,
+ /* P0 3600mts 2D */
+ .drate = 3600,
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
@@ -1840,5 +1855,19 @@
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 3733, 400, 100, },
+ .fsp_table = { 3600, 400, 100, },
};
+
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+void dh_imx8mp_dhcom_dram_scrub_32g_x32(void)
+{
+ ddrc_inline_ecc_scrub(0x0,0x7ffffff);
+ ddrc_inline_ecc_scrub(0x8000000,0xfffffff);
+ ddrc_inline_ecc_scrub(0x10000000,0x17ffffff);
+ ddrc_inline_ecc_scrub(0x18000000,0x1fffffff);
+ ddrc_inline_ecc_scrub(0x20000000,0x27ffffff);
+ ddrc_inline_ecc_scrub(0x28000000,0x2fffffff);
+ ddrc_inline_ecc_scrub(0x30000000,0x37ffffff);
+ ddrc_inline_ecc_scrub_end(0x0,0x3fffffff);
+}
+#endif
diff --git a/board/dhelectronics/dh_imx8mp/spl.c b/board/dhelectronics/dh_imx8mp/spl.c
index e2aa874..7d228da 100644
--- a/board/dhelectronics/dh_imx8mp/spl.c
+++ b/board/dhelectronics/dh_imx8mp/spl.c
@@ -11,16 +11,20 @@
#include <asm/io.h>
#include <asm-generic/gpio.h>
#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
#include <asm/arch/imx8mp_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/ddr.h>
+#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
+#include <linux/bitfield.h>
+
#include <power/pmic.h>
#include <power/pca9450.h>
@@ -40,6 +44,9 @@
MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
+static bool dh_gigabit_eqos, dh_gigabit_fec;
+static u8 dh_som_rev;
+
static void dh_imx8mp_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
@@ -88,6 +95,11 @@
/* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */
pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c);
+ /* DRAM Vdd1 always FPWM */
+ pmic_reg_write(dev, PCA9450_BUCK5CTRL, 0x0d);
+ /* DRAM Vdd2/Vddq always FPWM */
+ pmic_reg_write(dev, PCA9450_BUCK6CTRL, 0x0d);
+
/* Set LDO4 and CONFIG2 to enable the I2C level translator. */
pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59);
pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
@@ -123,8 +135,35 @@
}
ddr_init(dram_timing_info[memcfg]);
+
+ printf("DDR: Inline ECC %sabled\n",
+ (readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK) ?
+ "en" : "dis");
}
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+static const scrub_func_t dram_scrub_fn[8] = {
+ NULL, /* 512 MiB */
+ NULL, /* 1024 MiB */
+ NULL, /* 1536 MiB */
+ dh_imx8mp_dhcom_dram_scrub_16g_x32, /* 2048 MiB */
+ NULL, /* 3072 MiB */
+ dh_imx8mp_dhcom_dram_scrub_32g_x32, /* 4096 MiB */
+ NULL, /* 6144 MiB */
+ NULL, /* 8192 MiB */
+};
+
+void board_dram_ecc_scrub(void)
+{
+ u8 memcfg = dh_get_memcfg();
+
+ if (!dram_scrub_fn[memcfg])
+ return;
+
+ dram_scrub_fn[memcfg]();
+}
+#endif
+
void spl_board_init(void)
{
/*
@@ -143,6 +182,61 @@
return BOOT_DEVICE_BOOTROM;
}
+int board_spl_fit_append_fdt_skip(const char *name)
+{
+ if (!dh_gigabit_eqos) { /* 1x or 2x RMII PHY SoM */
+ if (dh_gigabit_fec) { /* 1x RMII PHY SoM */
+ if (!strcmp(name, "fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast"))
+ return 0;
+ } else { /* 2x RMII PHY SoM */
+ if (!strcmp(name, "fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast"))
+ return 0;
+ if (!strcmp(name, "fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast")) {
+ /* 2x RMII PHY SoM on PDK2 or PDK3 */
+ if (of_machine_is_compatible("dh,imx8mp-dhcom-pdk2") ||
+ of_machine_is_compatible("dh,imx8mp-dhcom-pdk3"))
+ return 0;
+ }
+ }
+ }
+
+ if (dh_som_rev == 0x0) { /* Prototype SoM rev.100 */
+ if (!strcmp(name, "fdt-dto-imx8mp-dhcom-som-overlay-rev100"))
+ return 0;
+
+ if (!strcmp(name, "fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100") &&
+ of_machine_is_compatible("dh,imx8mp-dhcom-pdk3"))
+ return 0;
+ }
+
+ return 1; /* Skip this DTO */
+}
+
+static void dh_imx8mp_board_cache_config(void)
+{
+ const void __iomem *mux_base = (void __iomem *)IOMUXC_BASE_ADDR;
+ const u32 mux_sion[] = {
+ FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_ENET_RX_CTL__GPIO1_IO24),
+ FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI1_TXFS__GPIO4_IO10),
+ FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_NAND_DQS__GPIO3_IO14),
+ FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI1_TXD7__GPIO4_IO19),
+ FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI5_MCLK__GPIO3_IO25),
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(mux_sion); i++)
+ setbits_le32(mux_base + mux_sion[i], IOMUX_CONFIG_SION);
+
+ dh_gigabit_eqos = !(readl(GPIO1_BASE_ADDR) & BIT(24));
+ dh_gigabit_fec = !(readl(GPIO4_BASE_ADDR) & BIT(10));
+ dh_som_rev = !!(readl(GPIO3_BASE_ADDR) & BIT(14));
+ dh_som_rev |= !!(readl(GPIO4_BASE_ADDR) & BIT(19)) << 1;
+ dh_som_rev |= !!(readl(GPIO3_BASE_ADDR) & BIT(25)) << 2;
+
+ for (i = 0; i < ARRAY_SIZE(mux_sion); i++)
+ clrbits_le32(mux_base + mux_sion[i], IOMUX_CONFIG_SION);
+}
+
void board_init_f(ulong dummy)
{
struct udevice *dev;
@@ -180,5 +274,7 @@
/* DDR initialization */
spl_dram_init();
+ dh_imx8mp_board_cache_config();
+
board_init_r(NULL, 0);
}
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index f9cfabe..d1f662d 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -34,6 +34,7 @@
#include <phy.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <power/regulator.h>
#include <remoteproc.h>
#include <reset.h>
@@ -229,8 +230,9 @@
gpio_free_list_nodev(gpio, ret);
- printf("Code: SoM:rev=%d,ddr3=%d Board:rev=%d\n",
- somcode, ddr3code, brdcode);
+ if (CONFIG_IS_ENABLED(DISPLAY_PRINT))
+ printf("Code: SoM:rev=%d,ddr3=%d Board:rev=%d\n",
+ somcode, ddr3code, brdcode);
}
int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
diff --git a/board/ebv/socrates/Makefile b/board/ebv/socrates/Makefile
deleted file mode 100644
index e1c8a6b..0000000
--- a/board/ebv/socrates/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
-
-obj-y := socfpga.o
diff --git a/board/ebv/socrates/socfpga.c b/board/ebv/socrates/socfpga.c
deleted file mode 100644
index 48bfe32..0000000
--- a/board/ebv/socrates/socfpga.c
+++ /dev/null
@@ -1,5 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- */
-#include <common.h>
diff --git a/board/edgeble/neural-compute-module-2/Makefile b/board/edgeble/neural-compute-module-2/Makefile
deleted file mode 100644
index 3bfc89f..0000000
--- a/board/edgeble/neural-compute-module-2/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += neu2.o
diff --git a/board/edgeble/neural-compute-module-2/neu2.c b/board/edgeble/neural-compute-module-2/neu2.c
deleted file mode 100644
index 3d2262c..0000000
--- a/board/edgeble/neural-compute-module-2/neu2.c
+++ /dev/null
@@ -1,4 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- */
diff --git a/board/edgeble/neural-compute-module-6/Makefile b/board/edgeble/neural-compute-module-6/Makefile
deleted file mode 100644
index 28310b1..0000000
--- a/board/edgeble/neural-compute-module-6/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += neu6.o
diff --git a/board/edgeble/neural-compute-module-6/neu6.c b/board/edgeble/neural-compute-module-6/neu6.c
deleted file mode 100644
index 3d2262c..0000000
--- a/board/edgeble/neural-compute-module-6/neu6.c
+++ /dev/null
@@ -1,4 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- */
diff --git a/board/eets/pdu001/README b/board/eets/pdu001/README
index 50e7154..ab10cf9 100644
--- a/board/eets/pdu001/README
+++ b/board/eets/pdu001/README
@@ -14,7 +14,7 @@
The PDU-001 (Processor and Display Unit) is a plugin card for 19" racks. It is
manufactured by EETS GmbH (https://www.eets.ch). The core of the board is a m2
SOM from bytes at work (https://www.bytesatwork.ch) which in turn is based on
-AM3352 SOC from TI (http://www.ti.com).
+AM3352 SOC from TI (https://www.ti.com).
Customization
=============
diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c
index de224d4..3a52e4a 100644
--- a/board/eets/pdu001/board.c
+++ b/board/eets/pdu001/board.c
@@ -6,7 +6,7 @@
*
* Copyright (C) 2018, EETS GmbH, http://www.eets.ch/
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/eets/pdu001/board.h b/board/eets/pdu001/board.h
index bfea96e..6ad0fea 100644
--- a/board/eets/pdu001/board.h
+++ b/board/eets/pdu001/board.h
@@ -6,7 +6,7 @@
*
* Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _BOARD_H_
diff --git a/board/eets/pdu001/mux.c b/board/eets/pdu001/mux.c
index 886fef6..c97927e 100644
--- a/board/eets/pdu001/mux.c
+++ b/board/eets/pdu001/mux.c
@@ -4,7 +4,7 @@
*
* Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/efi/efi-x86_app/Makefile b/board/efi/efi-x86_app/Makefile
deleted file mode 100644
index cb48d1c..0000000
--- a/board/efi/efi-x86_app/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2015 Google, Inc
-
-obj-y += app.o
diff --git a/board/efi/efi-x86_app/app.c b/board/efi/efi-x86_app/app.c
deleted file mode 100644
index da3445b..0000000
--- a/board/efi/efi-x86_app/app.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015 Google, Inc
- */
-
-#include <common.h>
diff --git a/board/emulation/qemu-arm/Kconfig b/board/emulation/qemu-arm/Kconfig
index 9c70ec3..09c9541 100644
--- a/board/emulation/qemu-arm/Kconfig
+++ b/board/emulation/qemu-arm/Kconfig
@@ -12,8 +12,9 @@
imply VIRTIO_NET
imply VIRTIO_BLK
-config SYS_EARLY_PCI_INIT
- def_bool y
+config PRE_CON_BUF_ADDR
+ hex
+ default 0x40100000
endif
diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c
index 8adee2b..d58d449 100644
--- a/board/emulation/qemu-arm/qemu-arm.c
+++ b/board/emulation/qemu-arm/qemu-arm.c
@@ -11,6 +11,7 @@
#include <fdtdec.h>
#include <init.h>
#include <log.h>
+#include <usb.h>
#include <virtio_types.h>
#include <virtio.h>
#include <env.h>
@@ -183,6 +184,10 @@
*/
virtio_init();
+ /* start usb so that usb keyboard can be used as input device */
+ if (CONFIG_IS_ENABLED(USB_KEYBOARD))
+ usb_init();
+
return 0;
}
diff --git a/board/emulation/qemu-arm/qemu-arm.env b/board/emulation/qemu-arm/qemu-arm.env
index e658d5e..fb4adef 100644
--- a/board/emulation/qemu-arm/qemu-arm.env
+++ b/board/emulation/qemu-arm/qemu-arm.env
@@ -2,6 +2,9 @@
/* environment for qemu-arm and qemu-arm64 */
+stdin=serial,usbkbd
+stdout=serial,vidconsole
+stderr=serial,vidconsole
fdt_high=0xffffffff
initrd_high=0xffffffff
fdt_addr=0x40000000
diff --git a/board/emulation/qemu-ppce500/qemu-ppce500.c b/board/emulation/qemu-ppce500/qemu-ppce500.c
index a39bcb4..2213616 100644
--- a/board/emulation/qemu-ppce500/qemu-ppce500.c
+++ b/board/emulation/qemu-ppce500/qemu-ppce500.c
@@ -9,6 +9,7 @@
#include <cpu_func.h>
#include <dm.h>
#include <env.h>
+#include <event.h>
#include <init.h>
#include <log.h>
#include <net.h>
@@ -184,7 +185,7 @@
return 0;
}
-int last_stage_init(void)
+static int last_stage_init(void)
{
void *fdt = get_fdt_virt();
int len = 0;
@@ -204,6 +205,7 @@
return 0;
}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
static uint64_t get_linear_ram_size(void)
{
@@ -318,7 +320,7 @@
int cpu_numcores(void)
{
/*
- * The QEMU u-boot target only needs to drive the first core,
+ * The QEMU U-Boot target only needs to drive the first core,
* spinning and device tree nodes get driven by QEMU itself
*/
return 1;
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index d56b4b5..c490dcf 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -54,8 +54,8 @@
imply SCSI_AHCI
imply AHCI_PCI
imply E1000
- imply NVME
imply PCI
+ imply NVME_PCI
imply PCIE_ECAM_GENERIC
imply DM_RNG
imply SCSI
diff --git a/board/emulation/qemu-x86/Makefile b/board/emulation/qemu-x86/Makefile
deleted file mode 100644
index ff4aaa5..0000000
--- a/board/emulation/qemu-x86/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
-
-obj-y += qemu-x86.o
diff --git a/board/emulation/qemu-x86/qemu-x86.c b/board/emulation/qemu-x86/qemu-x86.c
deleted file mode 100644
index e69de29..0000000
--- a/board/emulation/qemu-x86/qemu-x86.c
+++ /dev/null
diff --git a/board/engicam/imx8mm/spl.c b/board/engicam/imx8mm/spl.c
index 1846134..af9044a 100644
--- a/board/engicam/imx8mm/spl.c
+++ b/board/engicam/imx8mm/spl.c
@@ -16,6 +16,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/ddr.h>
+#include <asm/sections.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/engicam/px30_core/Makefile b/board/engicam/px30_core/Makefile
deleted file mode 100644
index 321fdb0..0000000
--- a/board/engicam/px30_core/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2020 Amarula Solutions(India)
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += px30_core.o
diff --git a/board/engicam/px30_core/px30_core.c b/board/engicam/px30_core/px30_core.c
deleted file mode 100644
index 3adc2f1..0000000
--- a/board/engicam/px30_core/px30_core.c
+++ /dev/null
@@ -1,4 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2020 Amarula Solutions(India)
- */
diff --git a/board/freescale/common/ngpixis.c b/board/freescale/common/ngpixis.c
index 37a6f77..7be1cce 100644
--- a/board/freescale/common/ngpixis.c
+++ b/board/freescale/common/ngpixis.c
@@ -234,15 +234,13 @@
return 0;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char pixis_help_text[] =
+U_BOOT_LONGHELP(pixis,
"- hard reset to default bank\n"
"pixis_reset altbank - reset to alternate bank\n"
#ifdef DEBUG
"pixis_reset dump - display the PIXIS registers\n"
#endif
- "pixis_reset sysclk <SYSCLK_freq> - reset with SYSCLK frequency(KHz)\n";
-#endif
+ "pixis_reset sysclk <SYSCLK_freq> - reset with SYSCLK frequency(KHz)\n");
U_BOOT_CMD(
pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index 431f8ca..64139d4 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -424,7 +424,7 @@
prog_eeprom();
break;
default:
- return cmd_usage(cmdtp);
+ return CMD_RET_USAGE;
}
return 0;
@@ -623,3 +623,27 @@
return MPC85XX_CPU_BOARD_REV(be.major, be.minor);
}
#endif
+
+U_BOOT_LONGHELP(mac,
+ "[read|save|id|num|errata|date|ports|port_number]\n"
+ "mac read\n"
+ " - read EEPROM content into memory data structure\n"
+ "mac save\n"
+ " - save memory data structure to the EEPROM\n"
+ "mac id\n"
+ " - program system id per hard coded value\n"
+ "mac num string\n"
+ " - program system serial number to value string\n"
+ "mac errata string\n"
+ " - program errata data to value string\n"
+ "mac date YYMMDDhhmmss\n"
+ " - program date to string value YYMMDDhhmmss\n"
+ "mac ports N\n"
+ " - program the number of network ports to integer N\n"
+ "mac X string\n"
+ " - program MAC addr for port X [X=0,1..] to colon separated string");
+
+U_BOOT_CMD(
+ mac, 3, 1, do_mac,
+ "display and program the system ID and MAC addresses in EEPROM",
+ mac_help_text);
diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c
index 6e95138..3543781 100644
--- a/board/freescale/imx8mm_evk/spl.c
+++ b/board/freescale/imx8mm_evk/spl.c
@@ -19,6 +19,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/ddr.h>
+#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c
index ec0378b..dd54fa9 100644
--- a/board/freescale/imx8mn_evk/spl.c
+++ b/board/freescale/imx8mn_evk/spl.c
@@ -20,6 +20,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/ddr.h>
+#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c
index bea9ddc..818cdd6 100644
--- a/board/freescale/imx8mq_evk/spl.c
+++ b/board/freescale/imx8mq_evk/spl.c
@@ -20,6 +20,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#include <fsl_sec.h>
#include <mmc.h>
diff --git a/board/freescale/imx8qm_mek/spl.c b/board/freescale/imx8qm_mek/spl.c
index 332a662..17fd437 100644
--- a/board/freescale/imx8qm_mek/spl.c
+++ b/board/freescale/imx8qm_mek/spl.c
@@ -17,6 +17,7 @@
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <asm/arch/sys_proto.h>
+#include <asm/sections.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c
index 75aab16..462c43c 100644
--- a/board/freescale/imx8qxp_mek/spl.c
+++ b/board/freescale/imx8qxp_mek/spl.c
@@ -22,6 +22,7 @@
#include <asm/arch/imx8-pins.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
+#include <asm/sections.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c
index 66d0f68..c49b5be 100644
--- a/board/freescale/imx8ulp_evk/spl.c
+++ b/board/freescale/imx8ulp_evk/spl.c
@@ -20,6 +20,7 @@
#include <asm/arch/rdc.h>
#include <asm/arch/upower.h>
#include <asm/mach-imx/ele_api.h>
+#include <asm/sections.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/imx93_evk/imx93_evk.c b/board/freescale/imx93_evk/imx93_evk.c
index e73a4987..f4297f8 100644
--- a/board/freescale/imx93_evk/imx93_evk.c
+++ b/board/freescale/imx93_evk/imx93_evk.c
@@ -33,8 +33,6 @@
{
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
- init_uart_clk(LPUART1_CLK_ROOT);
-
return 0;
}
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index 63883b3..be9c24f 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -20,6 +20,7 @@
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch-mx7ulp/gpio.h>
#include <asm/mach-imx/syscounter.h>
+#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
index 75de782af..a7e59e6 100644
--- a/board/freescale/ls1012afrdm/Kconfig
+++ b/board/freescale/ls1012afrdm/Kconfig
@@ -20,9 +20,6 @@
hex "length of PFE firmware"
default 0x40000
-config SYS_LS_PPA_FW_ADDR
- hex "PPA Firmware Addr"
- default 0x40400000
endif
if FSL_PFE
@@ -73,14 +70,6 @@
hex "length of PFE firmware"
default 0x40000
-config SYS_LS_PPA_FW_ADDR
- hex "PPA Firmware Addr"
- default 0x40060000
-
-config SYS_LS_PPA_ESBC_ADDR
- hex "PPA Firmware HDR Addr"
- default 0x401f4000
-
config SYS_LS_PFE_ESBC_ADDR
hex "PFE Firmware HDR Addr"
default 0x401f8000
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
index f2b8750..271072b 100644
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -12,9 +12,6 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
-#ifdef CONFIG_FSL_LS_PPA
-#include <asm/arch/ppa.h>
-#endif
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <fsl_esdhc.h>
@@ -171,9 +168,6 @@
if (current_el() == 3)
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
-#ifdef CONFIG_FSL_LS_PPA
- ppa_init();
-#endif
return 0;
}
diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig
index 991ba60..d333069 100644
--- a/board/freescale/ls1012aqds/Kconfig
+++ b/board/freescale/ls1012aqds/Kconfig
@@ -12,15 +12,7 @@
config SYS_CONFIG_NAME
default "ls1012aqds"
-config SYS_LS_PPA_FW_ADDR
- hex "PPA Firmware Addr"
- default 0x40400000
-
if CHAIN_OF_TRUST
-config SYS_LS_PPA_ESBC_ADDR
- hex "PPA Firmware HDR Addr"
- default 0x40680000
-
config SYS_LS_PFE_ESBC_ADDR
hex "PFE Firmware HDR Addr"
default 0x40700000
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 194b5d2..a5ea8d6 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -13,9 +13,6 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
-#ifdef CONFIG_FSL_LS_PPA
-#include <asm/arch/ppa.h>
-#endif
#include <asm/arch/fdt.h>
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
@@ -150,9 +147,6 @@
erratum_a010315();
#endif
-#ifdef CONFIG_FSL_LS_PPA
- ppa_init();
-#endif
return 0;
}
diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
index aa15f5a..b55660d 100644
--- a/board/freescale/ls1012ardb/Kconfig
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -12,15 +12,7 @@
config SYS_CONFIG_NAME
default "ls1012ardb"
-config SYS_LS_PPA_FW_ADDR
- hex "PPA Firmware Addr"
- default 0x40400000
-
if CHAIN_OF_TRUST
-config SYS_LS_PPA_ESBC_ADDR
- hex "PPA Firmware HDR Addr"
- default 0x40680000
-
config SYS_LS_PFE_ESBC_ADDR
hex "PFE Firmware HDR Addr"
default 0x40640000
@@ -79,10 +71,6 @@
config SYS_CONFIG_NAME
default "ls1012a2g5rdb"
-config SYS_LS_PPA_FW_ADDR
- hex "PPA Firmware Addr"
- default 0x40400000
-
if FSL_PFE
config BOARD_SPECIFIC_OPTIONS # dummy
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index 62c935e..18f9208 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -15,9 +15,6 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
-#ifdef CONFIG_FSL_LS_PPA
-#include <asm/arch/ppa.h>
-#endif
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
@@ -173,9 +170,6 @@
erratum_a010315();
#endif
-#ifdef CONFIG_FSL_LS_PPA
- ppa_init();
-#endif
return 0;
}
diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c
index 8605d06..d6f22bd 100644
--- a/board/freescale/ls1021aiot/ls1021aiot.c
+++ b/board/freescale/ls1021aiot/ls1021aiot.c
@@ -18,6 +18,7 @@
#include <asm/arch/ls102xa_devdis.h>
#include <asm/arch/ls102xa_soc.h>
+#include <asm/sections.h>
#include <fsl_csu.h>
#include <fsl_immap.h>
#include <netdev.h>
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index d5cb731..a618ce1 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -16,6 +16,7 @@
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ls102xa_soc.h>
#include <asm/arch/ls102xa_devdis.h>
+#include <asm/sections.h>
#include <hwconfig.h>
#include <mmc.h>
#include <fsl_csu.h>
diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c
index d144f25..d0e4e79 100644
--- a/board/freescale/ls1021atsn/ls1021atsn.c
+++ b/board/freescale/ls1021atsn/ls1021atsn.c
@@ -12,6 +12,7 @@
#include <asm/arch/ls102xa_soc.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/global_data.h>
+#include <asm/sections.h>
#include <linux/delay.h>
#include "../common/sleep.h"
#include <fsl_validate.h>
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 4f58343..27b9d79 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -18,6 +18,7 @@
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ls102xa_devdis.h>
#include <asm/arch/ls102xa_soc.h>
+#include <asm/sections.h>
#include <hwconfig.h>
#include <mmc.h>
#include <fsl_csu.h>
diff --git a/board/freescale/ls1028a/Kconfig b/board/freescale/ls1028a/Kconfig
index 7d73d20..fb6ee17 100644
--- a/board/freescale/ls1028a/Kconfig
+++ b/board/freescale/ls1028a/Kconfig
@@ -20,18 +20,6 @@
default 0x82000000 if TFABOOT
default 0x20100000
-if FSL_LS_PPA
-config SYS_LS_PPA_FW_ADDR
- hex "PPA Firmware Addr"
- default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A
- default 0x400000 if SYS_LS_PPA_FW_IN_MMC && ARCH_LS1028A
-if CHAIN_OF_TRUST
-config SYS_LS_PPA_ESBC_ADDR
- hex "PPA header Addr"
- default 0x20600000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A
-endif
-endif
-
endif
if TARGET_LS1028ARDB
diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c
index faecb60..7f181ab 100644
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -20,9 +20,6 @@
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <i2c.h>
#include <asm/arch/soc.h>
-#ifdef CONFIG_FSL_LS_PPA
-#include <asm/arch/ppa.h>
-#endif
#include <fsl_immap.h>
#include <netdev.h>
@@ -74,10 +71,6 @@
int board_init(void)
{
-#ifdef CONFIG_FSL_LS_PPA
- ppa_init();
-#endif
-
#ifndef CONFIG_SYS_EARLY_PCI_INIT
pci_init();
#endif
diff --git a/board/freescale/ls1043aqds/Kconfig b/board/freescale/ls1043aqds/Kconfig
index 4be445e..7e27f8f 100644
--- a/board/freescale/ls1043aqds/Kconfig
+++ b/board/freescale/ls1043aqds/Kconfig
@@ -12,20 +12,4 @@
config SYS_CONFIG_NAME
default "ls1043aqds"
-if FSL_LS_PPA
-config SYS_LS_PPA_FW_ADDR
- hex "PPA Firmware Addr"
- default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
- default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
- default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-
-if CHAIN_OF_TRUST
-config SYS_LS_PPA_ESBC_ADDR
- hex "PPA Firmware HDR Addr"
- default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
- default 0x60680000 if SYS_LS_PPA_FW_IN_XIP
- default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-endif
-endif
-
endif
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index 841d8b5..b87da41 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -15,7 +15,6 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
-#include <asm/arch/ppa.h>
#include <asm/arch/fdt.h>
#include <asm/arch/mmu.h>
#include <asm/arch/cpu.h>
@@ -533,10 +532,6 @@
config_serdes_mux();
#endif
-#ifdef CONFIG_FSL_LS_PPA
- ppa_init();
-#endif
-
return 0;
}
diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig
index 56502f9..51818ec 100644
--- a/board/freescale/ls1043ardb/Kconfig
+++ b/board/freescale/ls1043ardb/Kconfig
@@ -13,18 +13,4 @@
config SYS_CONFIG_NAME
default "ls1043ardb"
-if FSL_LS_PPA
-config SYS_LS_PPA_FW_ADDR
- hex "PPA Firmware Addr"
- default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
- default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-
-if CHAIN_OF_TRUST
-config SYS_LS_PPA_ESBC_ADDR
- hex "PPA Firmware HDR Addr"
- default 0x60680000 if SYS_LS_PPA_FW_IN_XIP
- default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-endif
-endif
-
endif
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index 741a4d6..18869d8 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -25,7 +25,6 @@
#ifdef CONFIG_U_QE
#include <fsl_qe.h>
#endif
-#include <asm/arch/ppa.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -211,10 +210,6 @@
out_le32(SMMU_NSCR0, val);
#endif
-#ifdef CONFIG_FSL_LS_PPA
- ppa_init();
-#endif
-
#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
pci_init();
#endif
diff --git a/board/freescale/ls1046aqds/Kconfig b/board/freescale/ls1046aqds/Kconfig
index adf325f..723f4ba 100644
--- a/board/freescale/ls1046aqds/Kconfig
+++ b/board/freescale/ls1046aqds/Kconfig
@@ -12,20 +12,4 @@
config SYS_CONFIG_NAME
default "ls1046aqds"
-if FSL_LS_PPA
-config SYS_LS_PPA_FW_ADDR
- hex "PPA Firmware Addr"
- default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
- default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
- default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-
-if CHAIN_OF_TRUST
-config SYS_LS_PPA_ESBC_ADDR
- hex "PPA Firmware HDR Addr"
- default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
- default 0x60680000 if SYS_LS_PPA_FW_IN_XIP
- default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-endif
-endif
-
endif
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index 3d08816..2faac54 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -14,7 +14,6 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
-#include <asm/arch/ppa.h>
#include <asm/arch/fdt.h>
#include <asm/arch/mmu.h>
#include <asm/arch/cpu.h>
@@ -402,10 +401,6 @@
if (adjust_vdd(0))
printf("Warning: Adjusting core voltage failed.\n");
-#ifdef CONFIG_FSL_LS_PPA
- ppa_init();
-#endif
-
#ifdef CONFIG_NXP_ESBC
/*
* In case of Secure Boot, the IBR configures the SMMU
diff --git a/board/freescale/ls1046ardb/Kconfig b/board/freescale/ls1046ardb/Kconfig
index 1fb391c..a62255c 100644
--- a/board/freescale/ls1046ardb/Kconfig
+++ b/board/freescale/ls1046ardb/Kconfig
@@ -13,18 +13,4 @@
config SYS_CONFIG_NAME
default "ls1046ardb"
-if FSL_LS_PPA
-config SYS_LS_PPA_FW_ADDR
- hex "PPA Firmware Addr"
- default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
- default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-
-if CHAIN_OF_TRUST
-config SYS_LS_PPA_ESBC_ADDR
- hex "PPA Firmware HDR Addr"
- default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
- default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-endif
-endif
-
endif
diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c
index 1d12d91..26e69db 100644
--- a/board/freescale/ls1046ardb/ls1046ardb.c
+++ b/board/freescale/ls1046ardb/ls1046ardb.c
@@ -14,7 +14,6 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
-#include <asm/arch/ppa.h>
#include <asm/arch/soc.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <hwconfig.h>
@@ -96,10 +95,6 @@
out_le32(SMMU_NSCR0, val);
#endif
-#ifdef CONFIG_FSL_LS_PPA
- ppa_init();
-#endif
-
#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
pci_init();
#endif
diff --git a/board/freescale/ls1088a/Kconfig b/board/freescale/ls1088a/Kconfig
index f1a4523..1ada661 100644
--- a/board/freescale/ls1088a/Kconfig
+++ b/board/freescale/ls1088a/Kconfig
@@ -12,20 +12,6 @@
config SYS_CONFIG_NAME
default "ls1088aqds"
-if FSL_LS_PPA
-config SYS_LS_PPA_FW_ADDR
- hex "PPA Firmware Addr"
- default 0x20400000 if SYS_LS_PPA_FW_IN_XIP
- default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-
-if CHAIN_OF_TRUST
-config SYS_LS_PPA_ESBC_ADDR
- hex "PPA Firmware HDR Addr"
- default 0x20680000 if SYS_LS_PPA_FW_IN_XIP
- default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-endif
-endif
-
endif
if TARGET_LS1088ARDB
@@ -42,18 +28,4 @@
config SYS_CONFIG_NAME
default "ls1088ardb"
-if FSL_LS_PPA
-config SYS_LS_PPA_FW_ADDR
- hex "PPA Firmware Addr"
- default 0x20400000 if SYS_LS_PPA_FW_IN_XIP
- default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-
-if CHAIN_OF_TRUST
-config SYS_LS_PPA_ESBC_ADDR
- hex "PPA Firmware HDR Addr"
- default 0x20680000 if SYS_LS_PPA_FW_IN_XIP
- default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-endif
-endif
-
endif
diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index 7a1047a..98a91c4 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -22,7 +22,6 @@
#include <fsl-mc/fsl_mc.h>
#include <env_internal.h>
#include <asm/arch-fsl-layerscape/soc.h>
-#include <asm/arch/ppa.h>
#include <hwconfig.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
@@ -181,13 +180,14 @@
#endif
#if defined(CONFIG_VID)
-int init_func_vid(void)
+static int setup_core_voltage(void)
{
if (adjust_vdd(0) < 0)
printf("core voltage not adjusted\n");
return 0;
}
+EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, setup_core_voltage);
u16 soc_get_fuse_vid(int vid_index)
{
@@ -820,10 +820,6 @@
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
#endif
-#ifdef CONFIG_FSL_LS_PPA
- ppa_init();
-#endif
-
#if !defined(CONFIG_SYS_EARLY_PCI_INIT)
pci_init();
#endif
@@ -988,6 +984,7 @@
#ifdef CONFIG_FSL_MC_ENET
fdt_fixup_board_enet(blob);
+ fdt_reserve_mc_mem(blob, 0x300);
#endif
fdt_fixup_icid(blob);
diff --git a/board/freescale/ls2080aqds/Kconfig b/board/freescale/ls2080aqds/Kconfig
index 1036f33..2f997e9 100644
--- a/board/freescale/ls2080aqds/Kconfig
+++ b/board/freescale/ls2080aqds/Kconfig
@@ -13,20 +13,4 @@
config SYS_CONFIG_NAME
default "ls2080aqds"
-if FSL_LS_PPA
-config SYS_LS_PPA_FW_ADDR
- hex "PPA Firmware Addr"
- default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
- default 0x580400000 if SYS_LS_PPA_FW_IN_XIP
- default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-
-if CHAIN_OF_TRUST
-config SYS_LS_PPA_ESBC_ADDR
- hex "PPA Firmware HDR Addr"
- default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
- default 0x580680000 if SYS_LS_PPA_FW_IN_XIP
- default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-endif
-endif
-
endif
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index ab5ff6f..5c94c83 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -23,7 +23,6 @@
#include <rtc.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
-#include <asm/arch/ppa.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include "../common/i2c_mux.h"
@@ -223,10 +222,6 @@
#endif
#endif
-#ifdef CONFIG_FSL_LS_PPA
- ppa_init();
-#endif
-
#if !defined(CONFIG_SYS_EARLY_PCI_INIT)
pci_init();
#endif
@@ -330,6 +325,7 @@
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
fdt_fixup_board_enet(blob);
+ fdt_reserve_mc_mem(blob, 0x300);
#endif
fdt_fixup_icid(blob);
diff --git a/board/freescale/ls2080ardb/Kconfig b/board/freescale/ls2080ardb/Kconfig
index c8b0b94..671eead 100644
--- a/board/freescale/ls2080ardb/Kconfig
+++ b/board/freescale/ls2080ardb/Kconfig
@@ -12,20 +12,4 @@
config SYS_CONFIG_NAME
default "ls2080ardb"
-if FSL_LS_PPA
-config SYS_LS_PPA_FW_ADDR
- hex "PPA Firmware Addr"
- default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
- default 0x580400000 if SYS_LS_PPA_FW_IN_XIP
- default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-
-if CHAIN_OF_TRUST
-config SYS_LS_PPA_ESBC_ADDR
- hex "PPA Firmware HDR Addr"
- default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
- default 0x580680000 if SYS_LS_PPA_FW_IN_XIP
- default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-endif
-endif
-
endif
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index a7fc2b2..5c30de8 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -24,7 +24,6 @@
#include <i2c.h>
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
-#include <asm/arch/ppa.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include "../common/i2c_mux.h"
@@ -288,10 +287,6 @@
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
#endif
-#ifdef CONFIG_FSL_LS_PPA
- ppa_init();
-#endif
-
#ifdef CONFIG_FSL_MC_ENET
/* invert AQR405 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
@@ -527,6 +522,7 @@
#ifdef CONFIG_FSL_MC_ENET
fdt_fixup_board_enet(blob);
+ fdt_reserve_mc_mem(blob, 0x300);
#endif
fdt_fixup_icid(blob);
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index d631a11..b3187a1 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -13,6 +13,7 @@
#include <i2c.h>
#include <malloc.h>
#include <errno.h>
+#include <event.h>
#include <netdev.h>
#include <fsl_ddr.h>
#include <asm/io.h>
@@ -242,6 +243,7 @@
return 0;
}
#endif
+EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, init_func_vid);
int checkboard(void)
{
@@ -834,6 +836,7 @@
#ifdef CONFIG_FSL_MC_ENET
fdt_fsl_mc_fixup_iommu_map_entry(blob);
fdt_fixup_board_enet(blob);
+ fdt_reserve_mc_mem(blob, 0x4000);
#endif
fdt_fixup_icid(blob);
diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c
index 039deb5..77e9200 100644
--- a/board/freescale/mx6sabreauto/mx6sabreauto.c
+++ b/board/freescale/mx6sabreauto/mx6sabreauto.c
@@ -15,6 +15,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
+#include <asm/sections.h>
#include <env.h>
#include <linux/errno.h>
#include <asm/gpio.h>
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 96a76b0..b558a59 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -14,6 +14,7 @@
#include <asm/arch/mx6-pins.h>
#include <asm/global_data.h>
#include <asm/mach-imx/spi.h>
+#include <asm/sections.h>
#include <env.h>
#include <linux/errno.h>
#include <asm/gpio.h>
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index 2c90a35..e9ac571 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -19,6 +19,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
+#include <asm/sections.h>
#include <linux/sizes.h>
#include <common.h>
#include <fsl_esdhc_imx.h>
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 570b501..534b16c 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -18,6 +18,7 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
+#include <asm/sections.h>
#include <common.h>
#include <env.h>
#include <fsl_esdhc_imx.h>
diff --git a/board/friendlyelec/nanopc-t6-rk3588/Kconfig b/board/friendlyelec/nanopc-t6-rk3588/Kconfig
new file mode 100644
index 0000000..032ef48
--- /dev/null
+++ b/board/friendlyelec/nanopc-t6-rk3588/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_NANOPCT6_RK3588
+
+config SYS_BOARD
+ default "nanopc-t6-rk3588"
+
+config SYS_VENDOR
+ default "friendlyelec"
+
+config SYS_CONFIG_NAME
+ default "nanopc-t6-rk3588"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/board/friendlyelec/nanopc-t6-rk3588/MAINTAINERS b/board/friendlyelec/nanopc-t6-rk3588/MAINTAINERS
new file mode 100644
index 0000000..63ff6fa
--- /dev/null
+++ b/board/friendlyelec/nanopc-t6-rk3588/MAINTAINERS
@@ -0,0 +1,9 @@
+NANOPCT6-RK3588
+M: John Clark <inindev@gmail.com>
+R: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: board/friendlyelec/nanopc-t6-rk3588
+F: include/configs/nanopc-t6-rk3588.h
+F: configs/nanopc-t6-rk3588_defconfig
+F: arch/arm/dts/rk3588-nanopc-t6.dts
+F: arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi
diff --git a/board/friendlyelec/nanopc-t6-rk3588/Makefile b/board/friendlyelec/nanopc-t6-rk3588/Makefile
new file mode 100644
index 0000000..c1c49b1
--- /dev/null
+++ b/board/friendlyelec/nanopc-t6-rk3588/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
+#
+
+obj-y += nanopc-t6-rk3588.o
diff --git a/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c b/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
new file mode 100644
index 0000000..99bbef9
--- /dev/null
+++ b/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
+ */
+
+#include <fdtdec.h>
+#include <fdt_support.h>
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int nanopc_t6_add_reserved_memory_fdt_nodes(void *new_blob)
+{
+ struct fdt_memory gap1 = {
+ .start = 0x3fc000000,
+ .end = 0x3fc4fffff,
+ };
+ struct fdt_memory gap2 = {
+ .start = 0x3fff00000,
+ .end = 0x3ffffffff,
+ };
+ unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
+ unsigned int ret;
+
+ /*
+ * Inject the reserved-memory nodes into the DTS
+ */
+ ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0,
+ NULL, flags);
+ if (ret)
+ return ret;
+
+ return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0,
+ NULL, flags);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ return nanopc_t6_add_reserved_memory_fdt_nodes(blob);
+}
+#endif
diff --git a/board/gateworks/venice/lpddr4_timing_imx8mm_512mb.c b/board/gateworks/venice/lpddr4_timing_imx8mm_512mb.c
deleted file mode 100644
index 8803fbf..0000000
--- a/board/gateworks/venice/lpddr4_timing_imx8mm_512mb.c
+++ /dev/null
@@ -1,1849 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Generated code from MX8M_DDR_tool v3.20 using RPAv20
- * - 1x Micron MT53E128M32D2DS-046 32bit dual-channel for total of 512MiB
- * - imx8mm-gw7903
- *
- * Align with uboot version:
- * imx_v2019.04_5.4.x and above version
- * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga:
- * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h>
- */
-
-#include <linux/kernel.h>
-#include <asm/arch/ddr.h>
-
-static struct dram_cfg_param ddr_ddrc_cfg[] = {
- /** Initialize DDRC registers **/
- { 0x3d400304, 0x1 },
- { 0x3d400030, 0x1 },
- { 0x3d400000, 0xa1080020 },
- { 0x3d400020, 0x203 },
- { 0x3d400024, 0x3a980 },
- { 0x3d400064, 0x5b0062 },
- { 0x3d4000d0, 0xc00305ba },
- { 0x3d4000d4, 0x940000 },
- { 0x3d4000dc, 0xd4002d },
- { 0x3d4000e0, 0x310000 },
- { 0x3d4000e8, 0x66004d },
- { 0x3d4000ec, 0x16004d },
- { 0x3d400100, 0x191e1920 },
- { 0x3d400104, 0x60630 },
- { 0x3d40010c, 0xb0b000 },
- { 0x3d400110, 0xe04080e },
- { 0x3d400114, 0x2040c0c },
- { 0x3d400118, 0x1010007 },
- { 0x3d40011c, 0x401 },
- { 0x3d400130, 0x20600 },
- { 0x3d400134, 0xc100002 },
- { 0x3d400138, 0x68 },
- { 0x3d400144, 0x96004b },
- { 0x3d400180, 0x2ee0017 },
- { 0x3d400184, 0x2605b8e },
- { 0x3d400188, 0x0 },
- { 0x3d400190, 0x497820a },
- { 0x3d400194, 0x80303 },
- { 0x3d4001b4, 0x170a },
- { 0x3d4001a0, 0xe0400018 },
- { 0x3d4001a4, 0xdf00e4 },
- { 0x3d4001a8, 0x80000000 },
- { 0x3d4001b0, 0x11 },
- { 0x3d4001c0, 0x1 },
- { 0x3d4001c4, 0x1 },
- { 0x3d4000f4, 0xc99 },
- { 0x3d400108, 0x70e1617 },
- { 0x3d400200, 0x1f },
- { 0x3d40020c, 0x0 },
- { 0x3d400210, 0x1f1f },
- { 0x3d400204, 0x80808 },
- { 0x3d400214, 0x7070707 },
- { 0x3d400218, 0xf0f0707 },
- { 0x3d40021c, 0xf0f },
- { 0x3d400250, 0x29001701 },
- { 0x3d400254, 0x2c },
- { 0x3d40025c, 0x4000030 },
- { 0x3d400264, 0x900093e7 },
- { 0x3d40026c, 0x2005574 },
- { 0x3d400400, 0x111 },
- { 0x3d400408, 0x72ff },
- { 0x3d400494, 0x2100e07 },
- { 0x3d400498, 0x620096 },
- { 0x3d40049c, 0x1100e07 },
- { 0x3d4004a0, 0xc8012c },
- { 0x3d402020, 0x1 },
- { 0x3d402024, 0x7d00 },
- { 0x3d402050, 0x20d040 },
- { 0x3d402064, 0xc000d },
- { 0x3d4020dc, 0x840000 },
- { 0x3d4020e0, 0x310000 },
- { 0x3d4020e8, 0x66004d },
- { 0x3d4020ec, 0x16004d },
- { 0x3d402100, 0xa040305 },
- { 0x3d402104, 0x30407 },
- { 0x3d402108, 0x203060b },
- { 0x3d40210c, 0x505000 },
- { 0x3d402110, 0x2040202 },
- { 0x3d402114, 0x2030202 },
- { 0x3d402118, 0x1010004 },
- { 0x3d40211c, 0x301 },
- { 0x3d402130, 0x20300 },
- { 0x3d402134, 0xa100002 },
- { 0x3d402138, 0xe },
- { 0x3d402144, 0x14000a },
- { 0x3d402180, 0x640004 },
- { 0x3d402190, 0x3818200 },
- { 0x3d402194, 0x80303 },
- { 0x3d4021b4, 0x100 },
- { 0x3d4020f4, 0xc99 },
- { 0x3d403020, 0x1 },
- { 0x3d403024, 0x1f40 },
- { 0x3d403050, 0x20d040 },
- { 0x3d403064, 0x30004 },
- { 0x3d4030dc, 0x840000 },
- { 0x3d4030e0, 0x310000 },
- { 0x3d4030e8, 0x66004d },
- { 0x3d4030ec, 0x16004d },
- { 0x3d403100, 0xa010102 },
- { 0x3d403104, 0x30404 },
- { 0x3d403108, 0x203060b },
- { 0x3d40310c, 0x505000 },
- { 0x3d403110, 0x2040202 },
- { 0x3d403114, 0x2030202 },
- { 0x3d403118, 0x1010004 },
- { 0x3d40311c, 0x301 },
- { 0x3d403130, 0x20300 },
- { 0x3d403134, 0xa100002 },
- { 0x3d403138, 0x4 },
- { 0x3d403144, 0x50003 },
- { 0x3d403180, 0x190004 },
- { 0x3d403190, 0x3818200 },
- { 0x3d403194, 0x80303 },
- { 0x3d4031b4, 0x100 },
- { 0x3d4030f4, 0xc99 },
- { 0x3d400028, 0x0 },
-};
-
-/* PHY Initialize Configuration */
-static struct dram_cfg_param ddr_ddrphy_cfg[] = {
- { 0x100a0, 0x0 },
- { 0x100a1, 0x1 },
- { 0x100a2, 0x2 },
- { 0x100a3, 0x3 },
- { 0x100a4, 0x4 },
- { 0x100a5, 0x5 },
- { 0x100a6, 0x6 },
- { 0x100a7, 0x7 },
- { 0x110a0, 0x0 },
- { 0x110a1, 0x1 },
- { 0x110a2, 0x3 },
- { 0x110a3, 0x4 },
- { 0x110a4, 0x5 },
- { 0x110a5, 0x2 },
- { 0x110a6, 0x7 },
- { 0x110a7, 0x6 },
- { 0x120a0, 0x0 },
- { 0x120a1, 0x1 },
- { 0x120a2, 0x3 },
- { 0x120a3, 0x4 },
- { 0x120a4, 0x5 },
- { 0x120a5, 0x2 },
- { 0x120a6, 0x7 },
- { 0x120a7, 0x6 },
- { 0x130a0, 0x0 },
- { 0x130a1, 0x1 },
- { 0x130a2, 0x2 },
- { 0x130a3, 0x3 },
- { 0x130a4, 0x4 },
- { 0x130a5, 0x5 },
- { 0x130a6, 0x6 },
- { 0x130a7, 0x7 },
- { 0x1005f, 0x1ff },
- { 0x1015f, 0x1ff },
- { 0x1105f, 0x1ff },
- { 0x1115f, 0x1ff },
- { 0x1205f, 0x1ff },
- { 0x1215f, 0x1ff },
- { 0x1305f, 0x1ff },
- { 0x1315f, 0x1ff },
- { 0x11005f, 0x1ff },
- { 0x11015f, 0x1ff },
- { 0x11105f, 0x1ff },
- { 0x11115f, 0x1ff },
- { 0x11205f, 0x1ff },
- { 0x11215f, 0x1ff },
- { 0x11305f, 0x1ff },
- { 0x11315f, 0x1ff },
- { 0x21005f, 0x1ff },
- { 0x21015f, 0x1ff },
- { 0x21105f, 0x1ff },
- { 0x21115f, 0x1ff },
- { 0x21205f, 0x1ff },
- { 0x21215f, 0x1ff },
- { 0x21305f, 0x1ff },
- { 0x21315f, 0x1ff },
- { 0x55, 0x1ff },
- { 0x1055, 0x1ff },
- { 0x2055, 0x1ff },
- { 0x3055, 0x1ff },
- { 0x4055, 0x1ff },
- { 0x5055, 0x1ff },
- { 0x6055, 0x1ff },
- { 0x7055, 0x1ff },
- { 0x8055, 0x1ff },
- { 0x9055, 0x1ff },
- { 0x200c5, 0x19 },
- { 0x1200c5, 0x7 },
- { 0x2200c5, 0x7 },
- { 0x2002e, 0x2 },
- { 0x12002e, 0x2 },
- { 0x22002e, 0x2 },
- { 0x90204, 0x0 },
- { 0x190204, 0x0 },
- { 0x290204, 0x0 },
- { 0x20024, 0x1ab },
- { 0x2003a, 0x0 },
- { 0x120024, 0x1ab },
- { 0x2003a, 0x0 },
- { 0x220024, 0x1ab },
- { 0x2003a, 0x0 },
- { 0x20056, 0x3 },
- { 0x120056, 0x3 },
- { 0x220056, 0x3 },
- { 0x1004d, 0xe00 },
- { 0x1014d, 0xe00 },
- { 0x1104d, 0xe00 },
- { 0x1114d, 0xe00 },
- { 0x1204d, 0xe00 },
- { 0x1214d, 0xe00 },
- { 0x1304d, 0xe00 },
- { 0x1314d, 0xe00 },
- { 0x11004d, 0xe00 },
- { 0x11014d, 0xe00 },
- { 0x11104d, 0xe00 },
- { 0x11114d, 0xe00 },
- { 0x11204d, 0xe00 },
- { 0x11214d, 0xe00 },
- { 0x11304d, 0xe00 },
- { 0x11314d, 0xe00 },
- { 0x21004d, 0xe00 },
- { 0x21014d, 0xe00 },
- { 0x21104d, 0xe00 },
- { 0x21114d, 0xe00 },
- { 0x21204d, 0xe00 },
- { 0x21214d, 0xe00 },
- { 0x21304d, 0xe00 },
- { 0x21314d, 0xe00 },
- { 0x10049, 0xeba },
- { 0x10149, 0xeba },
- { 0x11049, 0xeba },
- { 0x11149, 0xeba },
- { 0x12049, 0xeba },
- { 0x12149, 0xeba },
- { 0x13049, 0xeba },
- { 0x13149, 0xeba },
- { 0x110049, 0xeba },
- { 0x110149, 0xeba },
- { 0x111049, 0xeba },
- { 0x111149, 0xeba },
- { 0x112049, 0xeba },
- { 0x112149, 0xeba },
- { 0x113049, 0xeba },
- { 0x113149, 0xeba },
- { 0x210049, 0xeba },
- { 0x210149, 0xeba },
- { 0x211049, 0xeba },
- { 0x211149, 0xeba },
- { 0x212049, 0xeba },
- { 0x212149, 0xeba },
- { 0x213049, 0xeba },
- { 0x213149, 0xeba },
- { 0x43, 0x63 },
- { 0x1043, 0x63 },
- { 0x2043, 0x63 },
- { 0x3043, 0x63 },
- { 0x4043, 0x63 },
- { 0x5043, 0x63 },
- { 0x6043, 0x63 },
- { 0x7043, 0x63 },
- { 0x8043, 0x63 },
- { 0x9043, 0x63 },
- { 0x20018, 0x3 },
- { 0x20075, 0x4 },
- { 0x20050, 0x0 },
- { 0x20008, 0x2ee },
- { 0x120008, 0x64 },
- { 0x220008, 0x19 },
- { 0x20088, 0x9 },
- { 0x200b2, 0xdc },
- { 0x10043, 0x5a1 },
- { 0x10143, 0x5a1 },
- { 0x11043, 0x5a1 },
- { 0x11143, 0x5a1 },
- { 0x12043, 0x5a1 },
- { 0x12143, 0x5a1 },
- { 0x13043, 0x5a1 },
- { 0x13143, 0x5a1 },
- { 0x1200b2, 0xdc },
- { 0x110043, 0x5a1 },
- { 0x110143, 0x5a1 },
- { 0x111043, 0x5a1 },
- { 0x111143, 0x5a1 },
- { 0x112043, 0x5a1 },
- { 0x112143, 0x5a1 },
- { 0x113043, 0x5a1 },
- { 0x113143, 0x5a1 },
- { 0x2200b2, 0xdc },
- { 0x210043, 0x5a1 },
- { 0x210143, 0x5a1 },
- { 0x211043, 0x5a1 },
- { 0x211143, 0x5a1 },
- { 0x212043, 0x5a1 },
- { 0x212143, 0x5a1 },
- { 0x213043, 0x5a1 },
- { 0x213143, 0x5a1 },
- { 0x200fa, 0x1 },
- { 0x1200fa, 0x1 },
- { 0x2200fa, 0x1 },
- { 0x20019, 0x1 },
- { 0x120019, 0x1 },
- { 0x220019, 0x1 },
- { 0x200f0, 0x660 },
- { 0x200f1, 0x0 },
- { 0x200f2, 0x4444 },
- { 0x200f3, 0x8888 },
- { 0x200f4, 0x5665 },
- { 0x200f5, 0x0 },
- { 0x200f6, 0x0 },
- { 0x200f7, 0xf000 },
- { 0x20025, 0x0 },
- { 0x2002d, 0x0 },
- { 0x12002d, 0x0 },
- { 0x22002d, 0x0 },
- { 0x200c7, 0x21 },
- { 0x1200c7, 0x21 },
- { 0x2200c7, 0x21 },
- { 0x200ca, 0x24 },
- { 0x1200ca, 0x24 },
- { 0x2200ca, 0x24 },
-};
-
-/* ddr phy trained csr */
-static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
- { 0x200b2, 0x0 },
- { 0x1200b2, 0x0 },
- { 0x2200b2, 0x0 },
- { 0x200cb, 0x0 },
- { 0x10043, 0x0 },
- { 0x110043, 0x0 },
- { 0x210043, 0x0 },
- { 0x10143, 0x0 },
- { 0x110143, 0x0 },
- { 0x210143, 0x0 },
- { 0x11043, 0x0 },
- { 0x111043, 0x0 },
- { 0x211043, 0x0 },
- { 0x11143, 0x0 },
- { 0x111143, 0x0 },
- { 0x211143, 0x0 },
- { 0x12043, 0x0 },
- { 0x112043, 0x0 },
- { 0x212043, 0x0 },
- { 0x12143, 0x0 },
- { 0x112143, 0x0 },
- { 0x212143, 0x0 },
- { 0x13043, 0x0 },
- { 0x113043, 0x0 },
- { 0x213043, 0x0 },
- { 0x13143, 0x0 },
- { 0x113143, 0x0 },
- { 0x213143, 0x0 },
- { 0x80, 0x0 },
- { 0x100080, 0x0 },
- { 0x200080, 0x0 },
- { 0x1080, 0x0 },
- { 0x101080, 0x0 },
- { 0x201080, 0x0 },
- { 0x2080, 0x0 },
- { 0x102080, 0x0 },
- { 0x202080, 0x0 },
- { 0x3080, 0x0 },
- { 0x103080, 0x0 },
- { 0x203080, 0x0 },
- { 0x4080, 0x0 },
- { 0x104080, 0x0 },
- { 0x204080, 0x0 },
- { 0x5080, 0x0 },
- { 0x105080, 0x0 },
- { 0x205080, 0x0 },
- { 0x6080, 0x0 },
- { 0x106080, 0x0 },
- { 0x206080, 0x0 },
- { 0x7080, 0x0 },
- { 0x107080, 0x0 },
- { 0x207080, 0x0 },
- { 0x8080, 0x0 },
- { 0x108080, 0x0 },
- { 0x208080, 0x0 },
- { 0x9080, 0x0 },
- { 0x109080, 0x0 },
- { 0x209080, 0x0 },
- { 0x10080, 0x0 },
- { 0x110080, 0x0 },
- { 0x210080, 0x0 },
- { 0x10180, 0x0 },
- { 0x110180, 0x0 },
- { 0x210180, 0x0 },
- { 0x11080, 0x0 },
- { 0x111080, 0x0 },
- { 0x211080, 0x0 },
- { 0x11180, 0x0 },
- { 0x111180, 0x0 },
- { 0x211180, 0x0 },
- { 0x12080, 0x0 },
- { 0x112080, 0x0 },
- { 0x212080, 0x0 },
- { 0x12180, 0x0 },
- { 0x112180, 0x0 },
- { 0x212180, 0x0 },
- { 0x13080, 0x0 },
- { 0x113080, 0x0 },
- { 0x213080, 0x0 },
- { 0x13180, 0x0 },
- { 0x113180, 0x0 },
- { 0x213180, 0x0 },
- { 0x10081, 0x0 },
- { 0x110081, 0x0 },
- { 0x210081, 0x0 },
- { 0x10181, 0x0 },
- { 0x110181, 0x0 },
- { 0x210181, 0x0 },
- { 0x11081, 0x0 },
- { 0x111081, 0x0 },
- { 0x211081, 0x0 },
- { 0x11181, 0x0 },
- { 0x111181, 0x0 },
- { 0x211181, 0x0 },
- { 0x12081, 0x0 },
- { 0x112081, 0x0 },
- { 0x212081, 0x0 },
- { 0x12181, 0x0 },
- { 0x112181, 0x0 },
- { 0x212181, 0x0 },
- { 0x13081, 0x0 },
- { 0x113081, 0x0 },
- { 0x213081, 0x0 },
- { 0x13181, 0x0 },
- { 0x113181, 0x0 },
- { 0x213181, 0x0 },
- { 0x100d0, 0x0 },
- { 0x1100d0, 0x0 },
- { 0x2100d0, 0x0 },
- { 0x101d0, 0x0 },
- { 0x1101d0, 0x0 },
- { 0x2101d0, 0x0 },
- { 0x110d0, 0x0 },
- { 0x1110d0, 0x0 },
- { 0x2110d0, 0x0 },
- { 0x111d0, 0x0 },
- { 0x1111d0, 0x0 },
- { 0x2111d0, 0x0 },
- { 0x120d0, 0x0 },
- { 0x1120d0, 0x0 },
- { 0x2120d0, 0x0 },
- { 0x121d0, 0x0 },
- { 0x1121d0, 0x0 },
- { 0x2121d0, 0x0 },
- { 0x130d0, 0x0 },
- { 0x1130d0, 0x0 },
- { 0x2130d0, 0x0 },
- { 0x131d0, 0x0 },
- { 0x1131d0, 0x0 },
- { 0x2131d0, 0x0 },
- { 0x100d1, 0x0 },
- { 0x1100d1, 0x0 },
- { 0x2100d1, 0x0 },
- { 0x101d1, 0x0 },
- { 0x1101d1, 0x0 },
- { 0x2101d1, 0x0 },
- { 0x110d1, 0x0 },
- { 0x1110d1, 0x0 },
- { 0x2110d1, 0x0 },
- { 0x111d1, 0x0 },
- { 0x1111d1, 0x0 },
- { 0x2111d1, 0x0 },
- { 0x120d1, 0x0 },
- { 0x1120d1, 0x0 },
- { 0x2120d1, 0x0 },
- { 0x121d1, 0x0 },
- { 0x1121d1, 0x0 },
- { 0x2121d1, 0x0 },
- { 0x130d1, 0x0 },
- { 0x1130d1, 0x0 },
- { 0x2130d1, 0x0 },
- { 0x131d1, 0x0 },
- { 0x1131d1, 0x0 },
- { 0x2131d1, 0x0 },
- { 0x10068, 0x0 },
- { 0x10168, 0x0 },
- { 0x10268, 0x0 },
- { 0x10368, 0x0 },
- { 0x10468, 0x0 },
- { 0x10568, 0x0 },
- { 0x10668, 0x0 },
- { 0x10768, 0x0 },
- { 0x10868, 0x0 },
- { 0x11068, 0x0 },
- { 0x11168, 0x0 },
- { 0x11268, 0x0 },
- { 0x11368, 0x0 },
- { 0x11468, 0x0 },
- { 0x11568, 0x0 },
- { 0x11668, 0x0 },
- { 0x11768, 0x0 },
- { 0x11868, 0x0 },
- { 0x12068, 0x0 },
- { 0x12168, 0x0 },
- { 0x12268, 0x0 },
- { 0x12368, 0x0 },
- { 0x12468, 0x0 },
- { 0x12568, 0x0 },
- { 0x12668, 0x0 },
- { 0x12768, 0x0 },
- { 0x12868, 0x0 },
- { 0x13068, 0x0 },
- { 0x13168, 0x0 },
- { 0x13268, 0x0 },
- { 0x13368, 0x0 },
- { 0x13468, 0x0 },
- { 0x13568, 0x0 },
- { 0x13668, 0x0 },
- { 0x13768, 0x0 },
- { 0x13868, 0x0 },
- { 0x10069, 0x0 },
- { 0x10169, 0x0 },
- { 0x10269, 0x0 },
- { 0x10369, 0x0 },
- { 0x10469, 0x0 },
- { 0x10569, 0x0 },
- { 0x10669, 0x0 },
- { 0x10769, 0x0 },
- { 0x10869, 0x0 },
- { 0x11069, 0x0 },
- { 0x11169, 0x0 },
- { 0x11269, 0x0 },
- { 0x11369, 0x0 },
- { 0x11469, 0x0 },
- { 0x11569, 0x0 },
- { 0x11669, 0x0 },
- { 0x11769, 0x0 },
- { 0x11869, 0x0 },
- { 0x12069, 0x0 },
- { 0x12169, 0x0 },
- { 0x12269, 0x0 },
- { 0x12369, 0x0 },
- { 0x12469, 0x0 },
- { 0x12569, 0x0 },
- { 0x12669, 0x0 },
- { 0x12769, 0x0 },
- { 0x12869, 0x0 },
- { 0x13069, 0x0 },
- { 0x13169, 0x0 },
- { 0x13269, 0x0 },
- { 0x13369, 0x0 },
- { 0x13469, 0x0 },
- { 0x13569, 0x0 },
- { 0x13669, 0x0 },
- { 0x13769, 0x0 },
- { 0x13869, 0x0 },
- { 0x1008c, 0x0 },
- { 0x11008c, 0x0 },
- { 0x21008c, 0x0 },
- { 0x1018c, 0x0 },
- { 0x11018c, 0x0 },
- { 0x21018c, 0x0 },
- { 0x1108c, 0x0 },
- { 0x11108c, 0x0 },
- { 0x21108c, 0x0 },
- { 0x1118c, 0x0 },
- { 0x11118c, 0x0 },
- { 0x21118c, 0x0 },
- { 0x1208c, 0x0 },
- { 0x11208c, 0x0 },
- { 0x21208c, 0x0 },
- { 0x1218c, 0x0 },
- { 0x11218c, 0x0 },
- { 0x21218c, 0x0 },
- { 0x1308c, 0x0 },
- { 0x11308c, 0x0 },
- { 0x21308c, 0x0 },
- { 0x1318c, 0x0 },
- { 0x11318c, 0x0 },
- { 0x21318c, 0x0 },
- { 0x1008d, 0x0 },
- { 0x11008d, 0x0 },
- { 0x21008d, 0x0 },
- { 0x1018d, 0x0 },
- { 0x11018d, 0x0 },
- { 0x21018d, 0x0 },
- { 0x1108d, 0x0 },
- { 0x11108d, 0x0 },
- { 0x21108d, 0x0 },
- { 0x1118d, 0x0 },
- { 0x11118d, 0x0 },
- { 0x21118d, 0x0 },
- { 0x1208d, 0x0 },
- { 0x11208d, 0x0 },
- { 0x21208d, 0x0 },
- { 0x1218d, 0x0 },
- { 0x11218d, 0x0 },
- { 0x21218d, 0x0 },
- { 0x1308d, 0x0 },
- { 0x11308d, 0x0 },
- { 0x21308d, 0x0 },
- { 0x1318d, 0x0 },
- { 0x11318d, 0x0 },
- { 0x21318d, 0x0 },
- { 0x100c0, 0x0 },
- { 0x1100c0, 0x0 },
- { 0x2100c0, 0x0 },
- { 0x101c0, 0x0 },
- { 0x1101c0, 0x0 },
- { 0x2101c0, 0x0 },
- { 0x102c0, 0x0 },
- { 0x1102c0, 0x0 },
- { 0x2102c0, 0x0 },
- { 0x103c0, 0x0 },
- { 0x1103c0, 0x0 },
- { 0x2103c0, 0x0 },
- { 0x104c0, 0x0 },
- { 0x1104c0, 0x0 },
- { 0x2104c0, 0x0 },
- { 0x105c0, 0x0 },
- { 0x1105c0, 0x0 },
- { 0x2105c0, 0x0 },
- { 0x106c0, 0x0 },
- { 0x1106c0, 0x0 },
- { 0x2106c0, 0x0 },
- { 0x107c0, 0x0 },
- { 0x1107c0, 0x0 },
- { 0x2107c0, 0x0 },
- { 0x108c0, 0x0 },
- { 0x1108c0, 0x0 },
- { 0x2108c0, 0x0 },
- { 0x110c0, 0x0 },
- { 0x1110c0, 0x0 },
- { 0x2110c0, 0x0 },
- { 0x111c0, 0x0 },
- { 0x1111c0, 0x0 },
- { 0x2111c0, 0x0 },
- { 0x112c0, 0x0 },
- { 0x1112c0, 0x0 },
- { 0x2112c0, 0x0 },
- { 0x113c0, 0x0 },
- { 0x1113c0, 0x0 },
- { 0x2113c0, 0x0 },
- { 0x114c0, 0x0 },
- { 0x1114c0, 0x0 },
- { 0x2114c0, 0x0 },
- { 0x115c0, 0x0 },
- { 0x1115c0, 0x0 },
- { 0x2115c0, 0x0 },
- { 0x116c0, 0x0 },
- { 0x1116c0, 0x0 },
- { 0x2116c0, 0x0 },
- { 0x117c0, 0x0 },
- { 0x1117c0, 0x0 },
- { 0x2117c0, 0x0 },
- { 0x118c0, 0x0 },
- { 0x1118c0, 0x0 },
- { 0x2118c0, 0x0 },
- { 0x120c0, 0x0 },
- { 0x1120c0, 0x0 },
- { 0x2120c0, 0x0 },
- { 0x121c0, 0x0 },
- { 0x1121c0, 0x0 },
- { 0x2121c0, 0x0 },
- { 0x122c0, 0x0 },
- { 0x1122c0, 0x0 },
- { 0x2122c0, 0x0 },
- { 0x123c0, 0x0 },
- { 0x1123c0, 0x0 },
- { 0x2123c0, 0x0 },
- { 0x124c0, 0x0 },
- { 0x1124c0, 0x0 },
- { 0x2124c0, 0x0 },
- { 0x125c0, 0x0 },
- { 0x1125c0, 0x0 },
- { 0x2125c0, 0x0 },
- { 0x126c0, 0x0 },
- { 0x1126c0, 0x0 },
- { 0x2126c0, 0x0 },
- { 0x127c0, 0x0 },
- { 0x1127c0, 0x0 },
- { 0x2127c0, 0x0 },
- { 0x128c0, 0x0 },
- { 0x1128c0, 0x0 },
- { 0x2128c0, 0x0 },
- { 0x130c0, 0x0 },
- { 0x1130c0, 0x0 },
- { 0x2130c0, 0x0 },
- { 0x131c0, 0x0 },
- { 0x1131c0, 0x0 },
- { 0x2131c0, 0x0 },
- { 0x132c0, 0x0 },
- { 0x1132c0, 0x0 },
- { 0x2132c0, 0x0 },
- { 0x133c0, 0x0 },
- { 0x1133c0, 0x0 },
- { 0x2133c0, 0x0 },
- { 0x134c0, 0x0 },
- { 0x1134c0, 0x0 },
- { 0x2134c0, 0x0 },
- { 0x135c0, 0x0 },
- { 0x1135c0, 0x0 },
- { 0x2135c0, 0x0 },
- { 0x136c0, 0x0 },
- { 0x1136c0, 0x0 },
- { 0x2136c0, 0x0 },
- { 0x137c0, 0x0 },
- { 0x1137c0, 0x0 },
- { 0x2137c0, 0x0 },
- { 0x138c0, 0x0 },
- { 0x1138c0, 0x0 },
- { 0x2138c0, 0x0 },
- { 0x100c1, 0x0 },
- { 0x1100c1, 0x0 },
- { 0x2100c1, 0x0 },
- { 0x101c1, 0x0 },
- { 0x1101c1, 0x0 },
- { 0x2101c1, 0x0 },
- { 0x102c1, 0x0 },
- { 0x1102c1, 0x0 },
- { 0x2102c1, 0x0 },
- { 0x103c1, 0x0 },
- { 0x1103c1, 0x0 },
- { 0x2103c1, 0x0 },
- { 0x104c1, 0x0 },
- { 0x1104c1, 0x0 },
- { 0x2104c1, 0x0 },
- { 0x105c1, 0x0 },
- { 0x1105c1, 0x0 },
- { 0x2105c1, 0x0 },
- { 0x106c1, 0x0 },
- { 0x1106c1, 0x0 },
- { 0x2106c1, 0x0 },
- { 0x107c1, 0x0 },
- { 0x1107c1, 0x0 },
- { 0x2107c1, 0x0 },
- { 0x108c1, 0x0 },
- { 0x1108c1, 0x0 },
- { 0x2108c1, 0x0 },
- { 0x110c1, 0x0 },
- { 0x1110c1, 0x0 },
- { 0x2110c1, 0x0 },
- { 0x111c1, 0x0 },
- { 0x1111c1, 0x0 },
- { 0x2111c1, 0x0 },
- { 0x112c1, 0x0 },
- { 0x1112c1, 0x0 },
- { 0x2112c1, 0x0 },
- { 0x113c1, 0x0 },
- { 0x1113c1, 0x0 },
- { 0x2113c1, 0x0 },
- { 0x114c1, 0x0 },
- { 0x1114c1, 0x0 },
- { 0x2114c1, 0x0 },
- { 0x115c1, 0x0 },
- { 0x1115c1, 0x0 },
- { 0x2115c1, 0x0 },
- { 0x116c1, 0x0 },
- { 0x1116c1, 0x0 },
- { 0x2116c1, 0x0 },
- { 0x117c1, 0x0 },
- { 0x1117c1, 0x0 },
- { 0x2117c1, 0x0 },
- { 0x118c1, 0x0 },
- { 0x1118c1, 0x0 },
- { 0x2118c1, 0x0 },
- { 0x120c1, 0x0 },
- { 0x1120c1, 0x0 },
- { 0x2120c1, 0x0 },
- { 0x121c1, 0x0 },
- { 0x1121c1, 0x0 },
- { 0x2121c1, 0x0 },
- { 0x122c1, 0x0 },
- { 0x1122c1, 0x0 },
- { 0x2122c1, 0x0 },
- { 0x123c1, 0x0 },
- { 0x1123c1, 0x0 },
- { 0x2123c1, 0x0 },
- { 0x124c1, 0x0 },
- { 0x1124c1, 0x0 },
- { 0x2124c1, 0x0 },
- { 0x125c1, 0x0 },
- { 0x1125c1, 0x0 },
- { 0x2125c1, 0x0 },
- { 0x126c1, 0x0 },
- { 0x1126c1, 0x0 },
- { 0x2126c1, 0x0 },
- { 0x127c1, 0x0 },
- { 0x1127c1, 0x0 },
- { 0x2127c1, 0x0 },
- { 0x128c1, 0x0 },
- { 0x1128c1, 0x0 },
- { 0x2128c1, 0x0 },
- { 0x130c1, 0x0 },
- { 0x1130c1, 0x0 },
- { 0x2130c1, 0x0 },
- { 0x131c1, 0x0 },
- { 0x1131c1, 0x0 },
- { 0x2131c1, 0x0 },
- { 0x132c1, 0x0 },
- { 0x1132c1, 0x0 },
- { 0x2132c1, 0x0 },
- { 0x133c1, 0x0 },
- { 0x1133c1, 0x0 },
- { 0x2133c1, 0x0 },
- { 0x134c1, 0x0 },
- { 0x1134c1, 0x0 },
- { 0x2134c1, 0x0 },
- { 0x135c1, 0x0 },
- { 0x1135c1, 0x0 },
- { 0x2135c1, 0x0 },
- { 0x136c1, 0x0 },
- { 0x1136c1, 0x0 },
- { 0x2136c1, 0x0 },
- { 0x137c1, 0x0 },
- { 0x1137c1, 0x0 },
- { 0x2137c1, 0x0 },
- { 0x138c1, 0x0 },
- { 0x1138c1, 0x0 },
- { 0x2138c1, 0x0 },
- { 0x10020, 0x0 },
- { 0x110020, 0x0 },
- { 0x210020, 0x0 },
- { 0x11020, 0x0 },
- { 0x111020, 0x0 },
- { 0x211020, 0x0 },
- { 0x12020, 0x0 },
- { 0x112020, 0x0 },
- { 0x212020, 0x0 },
- { 0x13020, 0x0 },
- { 0x113020, 0x0 },
- { 0x213020, 0x0 },
- { 0x20072, 0x0 },
- { 0x20073, 0x0 },
- { 0x20074, 0x0 },
- { 0x100aa, 0x0 },
- { 0x110aa, 0x0 },
- { 0x120aa, 0x0 },
- { 0x130aa, 0x0 },
- { 0x20010, 0x0 },
- { 0x120010, 0x0 },
- { 0x220010, 0x0 },
- { 0x20011, 0x0 },
- { 0x120011, 0x0 },
- { 0x220011, 0x0 },
- { 0x100ae, 0x0 },
- { 0x1100ae, 0x0 },
- { 0x2100ae, 0x0 },
- { 0x100af, 0x0 },
- { 0x1100af, 0x0 },
- { 0x2100af, 0x0 },
- { 0x110ae, 0x0 },
- { 0x1110ae, 0x0 },
- { 0x2110ae, 0x0 },
- { 0x110af, 0x0 },
- { 0x1110af, 0x0 },
- { 0x2110af, 0x0 },
- { 0x120ae, 0x0 },
- { 0x1120ae, 0x0 },
- { 0x2120ae, 0x0 },
- { 0x120af, 0x0 },
- { 0x1120af, 0x0 },
- { 0x2120af, 0x0 },
- { 0x130ae, 0x0 },
- { 0x1130ae, 0x0 },
- { 0x2130ae, 0x0 },
- { 0x130af, 0x0 },
- { 0x1130af, 0x0 },
- { 0x2130af, 0x0 },
- { 0x20020, 0x0 },
- { 0x120020, 0x0 },
- { 0x220020, 0x0 },
- { 0x100a0, 0x0 },
- { 0x100a1, 0x0 },
- { 0x100a2, 0x0 },
- { 0x100a3, 0x0 },
- { 0x100a4, 0x0 },
- { 0x100a5, 0x0 },
- { 0x100a6, 0x0 },
- { 0x100a7, 0x0 },
- { 0x110a0, 0x0 },
- { 0x110a1, 0x0 },
- { 0x110a2, 0x0 },
- { 0x110a3, 0x0 },
- { 0x110a4, 0x0 },
- { 0x110a5, 0x0 },
- { 0x110a6, 0x0 },
- { 0x110a7, 0x0 },
- { 0x120a0, 0x0 },
- { 0x120a1, 0x0 },
- { 0x120a2, 0x0 },
- { 0x120a3, 0x0 },
- { 0x120a4, 0x0 },
- { 0x120a5, 0x0 },
- { 0x120a6, 0x0 },
- { 0x120a7, 0x0 },
- { 0x130a0, 0x0 },
- { 0x130a1, 0x0 },
- { 0x130a2, 0x0 },
- { 0x130a3, 0x0 },
- { 0x130a4, 0x0 },
- { 0x130a5, 0x0 },
- { 0x130a6, 0x0 },
- { 0x130a7, 0x0 },
- { 0x2007c, 0x0 },
- { 0x12007c, 0x0 },
- { 0x22007c, 0x0 },
- { 0x2007d, 0x0 },
- { 0x12007d, 0x0 },
- { 0x22007d, 0x0 },
- { 0x400fd, 0x0 },
- { 0x400c0, 0x0 },
- { 0x90201, 0x0 },
- { 0x190201, 0x0 },
- { 0x290201, 0x0 },
- { 0x90202, 0x0 },
- { 0x190202, 0x0 },
- { 0x290202, 0x0 },
- { 0x90203, 0x0 },
- { 0x190203, 0x0 },
- { 0x290203, 0x0 },
- { 0x90204, 0x0 },
- { 0x190204, 0x0 },
- { 0x290204, 0x0 },
- { 0x90205, 0x0 },
- { 0x190205, 0x0 },
- { 0x290205, 0x0 },
- { 0x90206, 0x0 },
- { 0x190206, 0x0 },
- { 0x290206, 0x0 },
- { 0x90207, 0x0 },
- { 0x190207, 0x0 },
- { 0x290207, 0x0 },
- { 0x90208, 0x0 },
- { 0x190208, 0x0 },
- { 0x290208, 0x0 },
- { 0x10062, 0x0 },
- { 0x10162, 0x0 },
- { 0x10262, 0x0 },
- { 0x10362, 0x0 },
- { 0x10462, 0x0 },
- { 0x10562, 0x0 },
- { 0x10662, 0x0 },
- { 0x10762, 0x0 },
- { 0x10862, 0x0 },
- { 0x11062, 0x0 },
- { 0x11162, 0x0 },
- { 0x11262, 0x0 },
- { 0x11362, 0x0 },
- { 0x11462, 0x0 },
- { 0x11562, 0x0 },
- { 0x11662, 0x0 },
- { 0x11762, 0x0 },
- { 0x11862, 0x0 },
- { 0x12062, 0x0 },
- { 0x12162, 0x0 },
- { 0x12262, 0x0 },
- { 0x12362, 0x0 },
- { 0x12462, 0x0 },
- { 0x12562, 0x0 },
- { 0x12662, 0x0 },
- { 0x12762, 0x0 },
- { 0x12862, 0x0 },
- { 0x13062, 0x0 },
- { 0x13162, 0x0 },
- { 0x13262, 0x0 },
- { 0x13362, 0x0 },
- { 0x13462, 0x0 },
- { 0x13562, 0x0 },
- { 0x13662, 0x0 },
- { 0x13762, 0x0 },
- { 0x13862, 0x0 },
- { 0x20077, 0x0 },
- { 0x10001, 0x0 },
- { 0x11001, 0x0 },
- { 0x12001, 0x0 },
- { 0x13001, 0x0 },
- { 0x10040, 0x0 },
- { 0x10140, 0x0 },
- { 0x10240, 0x0 },
- { 0x10340, 0x0 },
- { 0x10440, 0x0 },
- { 0x10540, 0x0 },
- { 0x10640, 0x0 },
- { 0x10740, 0x0 },
- { 0x10840, 0x0 },
- { 0x10030, 0x0 },
- { 0x10130, 0x0 },
- { 0x10230, 0x0 },
- { 0x10330, 0x0 },
- { 0x10430, 0x0 },
- { 0x10530, 0x0 },
- { 0x10630, 0x0 },
- { 0x10730, 0x0 },
- { 0x10830, 0x0 },
- { 0x11040, 0x0 },
- { 0x11140, 0x0 },
- { 0x11240, 0x0 },
- { 0x11340, 0x0 },
- { 0x11440, 0x0 },
- { 0x11540, 0x0 },
- { 0x11640, 0x0 },
- { 0x11740, 0x0 },
- { 0x11840, 0x0 },
- { 0x11030, 0x0 },
- { 0x11130, 0x0 },
- { 0x11230, 0x0 },
- { 0x11330, 0x0 },
- { 0x11430, 0x0 },
- { 0x11530, 0x0 },
- { 0x11630, 0x0 },
- { 0x11730, 0x0 },
- { 0x11830, 0x0 },
- { 0x12040, 0x0 },
- { 0x12140, 0x0 },
- { 0x12240, 0x0 },
- { 0x12340, 0x0 },
- { 0x12440, 0x0 },
- { 0x12540, 0x0 },
- { 0x12640, 0x0 },
- { 0x12740, 0x0 },
- { 0x12840, 0x0 },
- { 0x12030, 0x0 },
- { 0x12130, 0x0 },
- { 0x12230, 0x0 },
- { 0x12330, 0x0 },
- { 0x12430, 0x0 },
- { 0x12530, 0x0 },
- { 0x12630, 0x0 },
- { 0x12730, 0x0 },
- { 0x12830, 0x0 },
- { 0x13040, 0x0 },
- { 0x13140, 0x0 },
- { 0x13240, 0x0 },
- { 0x13340, 0x0 },
- { 0x13440, 0x0 },
- { 0x13540, 0x0 },
- { 0x13640, 0x0 },
- { 0x13740, 0x0 },
- { 0x13840, 0x0 },
- { 0x13030, 0x0 },
- { 0x13130, 0x0 },
- { 0x13230, 0x0 },
- { 0x13330, 0x0 },
- { 0x13430, 0x0 },
- { 0x13530, 0x0 },
- { 0x13630, 0x0 },
- { 0x13730, 0x0 },
- { 0x13830, 0x0 },
-};
-
-/* P0 message block paremeter for training firmware */
-static struct dram_cfg_param ddr_fsp0_cfg[] = {
- { 0xd0000, 0x0 },
- { 0x54003, 0xbb8 },
- { 0x54004, 0x2 },
- { 0x54005, 0x2228 },
- { 0x54006, 0x11 },
- { 0x54008, 0x131f },
- { 0x54009, 0xc8 },
- { 0x5400b, 0x2 },
- { 0x54012, 0x110 },
- { 0x54019, 0x2dd4 },
- { 0x5401a, 0x31 },
- { 0x5401b, 0x4d66 },
- { 0x5401c, 0x4d00 },
- { 0x5401e, 0x16 },
- { 0x5401f, 0x2dd4 },
- { 0x54020, 0x31 },
- { 0x54021, 0x4d66 },
- { 0x54022, 0x4d00 },
- { 0x54024, 0x16 },
- { 0x5402b, 0x1000 },
- { 0x5402c, 0x1 },
- { 0x54032, 0xd400 },
- { 0x54033, 0x312d },
- { 0x54034, 0x6600 },
- { 0x54035, 0x4d },
- { 0x54036, 0x4d },
- { 0x54037, 0x1600 },
- { 0x54038, 0xd400 },
- { 0x54039, 0x312d },
- { 0x5403a, 0x6600 },
- { 0x5403b, 0x4d },
- { 0x5403c, 0x4d },
- { 0x5403d, 0x1600 },
- { 0xd0000, 0x1 },
-};
-
-/* P1 message block paremeter for training firmware */
-static struct dram_cfg_param ddr_fsp1_cfg[] = {
- { 0xd0000, 0x0 },
- { 0x54002, 0x101 },
- { 0x54003, 0x190 },
- { 0x54004, 0x2 },
- { 0x54005, 0x2228 },
- { 0x54006, 0x11 },
- { 0x54008, 0x121f },
- { 0x54009, 0xc8 },
- { 0x5400b, 0x2 },
- { 0x54012, 0x110 },
- { 0x54019, 0x84 },
- { 0x5401a, 0x31 },
- { 0x5401b, 0x4d66 },
- { 0x5401c, 0x4d00 },
- { 0x5401e, 0x16 },
- { 0x5401f, 0x84 },
- { 0x54020, 0x31 },
- { 0x54021, 0x4d66 },
- { 0x54022, 0x4d00 },
- { 0x54024, 0x16 },
- { 0x5402b, 0x1000 },
- { 0x5402c, 0x1 },
- { 0x54032, 0x8400 },
- { 0x54033, 0x3100 },
- { 0x54034, 0x6600 },
- { 0x54035, 0x4d },
- { 0x54036, 0x4d },
- { 0x54037, 0x1600 },
- { 0x54038, 0x8400 },
- { 0x54039, 0x3100 },
- { 0x5403a, 0x6600 },
- { 0x5403b, 0x4d },
- { 0x5403c, 0x4d },
- { 0x5403d, 0x1600 },
- { 0xd0000, 0x1 },
-};
-
-/* P2 message block paremeter for training firmware */
-static struct dram_cfg_param ddr_fsp2_cfg[] = {
- { 0xd0000, 0x0 },
- { 0x54002, 0x102 },
- { 0x54003, 0x64 },
- { 0x54004, 0x2 },
- { 0x54005, 0x2228 },
- { 0x54006, 0x11 },
- { 0x54008, 0x121f },
- { 0x54009, 0xc8 },
- { 0x5400b, 0x2 },
- { 0x54012, 0x110 },
- { 0x54019, 0x84 },
- { 0x5401a, 0x31 },
- { 0x5401b, 0x4d66 },
- { 0x5401c, 0x4d00 },
- { 0x5401e, 0x16 },
- { 0x5401f, 0x84 },
- { 0x54020, 0x31 },
- { 0x54021, 0x4d66 },
- { 0x54022, 0x4d00 },
- { 0x54024, 0x16 },
- { 0x5402b, 0x1000 },
- { 0x5402c, 0x1 },
- { 0x54032, 0x8400 },
- { 0x54033, 0x3100 },
- { 0x54034, 0x6600 },
- { 0x54035, 0x4d },
- { 0x54036, 0x4d },
- { 0x54037, 0x1600 },
- { 0x54038, 0x8400 },
- { 0x54039, 0x3100 },
- { 0x5403a, 0x6600 },
- { 0x5403b, 0x4d },
- { 0x5403c, 0x4d },
- { 0x5403d, 0x1600 },
- { 0xd0000, 0x1 },
-};
-
-/* P0 2D message block paremeter for training firmware */
-static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
- { 0xd0000, 0x0 },
- { 0x54003, 0xbb8 },
- { 0x54004, 0x2 },
- { 0x54005, 0x2228 },
- { 0x54006, 0x11 },
- { 0x54008, 0x61 },
- { 0x54009, 0xc8 },
- { 0x5400b, 0x2 },
- { 0x5400f, 0x100 },
- { 0x54010, 0x1f7f },
- { 0x54012, 0x110 },
- { 0x54019, 0x2dd4 },
- { 0x5401a, 0x31 },
- { 0x5401b, 0x4d66 },
- { 0x5401c, 0x4d00 },
- { 0x5401e, 0x16 },
- { 0x5401f, 0x2dd4 },
- { 0x54020, 0x31 },
- { 0x54021, 0x4d66 },
- { 0x54022, 0x4d00 },
- { 0x54024, 0x16 },
- { 0x5402b, 0x1000 },
- { 0x5402c, 0x1 },
- { 0x54032, 0xd400 },
- { 0x54033, 0x312d },
- { 0x54034, 0x6600 },
- { 0x54035, 0x4d },
- { 0x54036, 0x4d },
- { 0x54037, 0x1600 },
- { 0x54038, 0xd400 },
- { 0x54039, 0x312d },
- { 0x5403a, 0x6600 },
- { 0x5403b, 0x4d },
- { 0x5403c, 0x4d },
- { 0x5403d, 0x1600 },
- { 0xd0000, 0x1 },
-};
-
-/* DRAM PHY init engine image */
-static struct dram_cfg_param ddr_phy_pie[] = {
- { 0xd0000, 0x0 },
- { 0x90000, 0x10 },
- { 0x90001, 0x400 },
- { 0x90002, 0x10e },
- { 0x90003, 0x0 },
- { 0x90004, 0x0 },
- { 0x90005, 0x8 },
- { 0x90029, 0xb },
- { 0x9002a, 0x480 },
- { 0x9002b, 0x109 },
- { 0x9002c, 0x8 },
- { 0x9002d, 0x448 },
- { 0x9002e, 0x139 },
- { 0x9002f, 0x8 },
- { 0x90030, 0x478 },
- { 0x90031, 0x109 },
- { 0x90032, 0x0 },
- { 0x90033, 0xe8 },
- { 0x90034, 0x109 },
- { 0x90035, 0x2 },
- { 0x90036, 0x10 },
- { 0x90037, 0x139 },
- { 0x90038, 0xf },
- { 0x90039, 0x7c0 },
- { 0x9003a, 0x139 },
- { 0x9003b, 0x44 },
- { 0x9003c, 0x630 },
- { 0x9003d, 0x159 },
- { 0x9003e, 0x14f },
- { 0x9003f, 0x630 },
- { 0x90040, 0x159 },
- { 0x90041, 0x47 },
- { 0x90042, 0x630 },
- { 0x90043, 0x149 },
- { 0x90044, 0x4f },
- { 0x90045, 0x630 },
- { 0x90046, 0x179 },
- { 0x90047, 0x8 },
- { 0x90048, 0xe0 },
- { 0x90049, 0x109 },
- { 0x9004a, 0x0 },
- { 0x9004b, 0x7c8 },
- { 0x9004c, 0x109 },
- { 0x9004d, 0x0 },
- { 0x9004e, 0x1 },
- { 0x9004f, 0x8 },
- { 0x90050, 0x0 },
- { 0x90051, 0x45a },
- { 0x90052, 0x9 },
- { 0x90053, 0x0 },
- { 0x90054, 0x448 },
- { 0x90055, 0x109 },
- { 0x90056, 0x40 },
- { 0x90057, 0x630 },
- { 0x90058, 0x179 },
- { 0x90059, 0x1 },
- { 0x9005a, 0x618 },
- { 0x9005b, 0x109 },
- { 0x9005c, 0x40c0 },
- { 0x9005d, 0x630 },
- { 0x9005e, 0x149 },
- { 0x9005f, 0x8 },
- { 0x90060, 0x4 },
- { 0x90061, 0x48 },
- { 0x90062, 0x4040 },
- { 0x90063, 0x630 },
- { 0x90064, 0x149 },
- { 0x90065, 0x0 },
- { 0x90066, 0x4 },
- { 0x90067, 0x48 },
- { 0x90068, 0x40 },
- { 0x90069, 0x630 },
- { 0x9006a, 0x149 },
- { 0x9006b, 0x10 },
- { 0x9006c, 0x4 },
- { 0x9006d, 0x18 },
- { 0x9006e, 0x0 },
- { 0x9006f, 0x4 },
- { 0x90070, 0x78 },
- { 0x90071, 0x549 },
- { 0x90072, 0x630 },
- { 0x90073, 0x159 },
- { 0x90074, 0xd49 },
- { 0x90075, 0x630 },
- { 0x90076, 0x159 },
- { 0x90077, 0x94a },
- { 0x90078, 0x630 },
- { 0x90079, 0x159 },
- { 0x9007a, 0x441 },
- { 0x9007b, 0x630 },
- { 0x9007c, 0x149 },
- { 0x9007d, 0x42 },
- { 0x9007e, 0x630 },
- { 0x9007f, 0x149 },
- { 0x90080, 0x1 },
- { 0x90081, 0x630 },
- { 0x90082, 0x149 },
- { 0x90083, 0x0 },
- { 0x90084, 0xe0 },
- { 0x90085, 0x109 },
- { 0x90086, 0xa },
- { 0x90087, 0x10 },
- { 0x90088, 0x109 },
- { 0x90089, 0x9 },
- { 0x9008a, 0x3c0 },
- { 0x9008b, 0x149 },
- { 0x9008c, 0x9 },
- { 0x9008d, 0x3c0 },
- { 0x9008e, 0x159 },
- { 0x9008f, 0x18 },
- { 0x90090, 0x10 },
- { 0x90091, 0x109 },
- { 0x90092, 0x0 },
- { 0x90093, 0x3c0 },
- { 0x90094, 0x109 },
- { 0x90095, 0x18 },
- { 0x90096, 0x4 },
- { 0x90097, 0x48 },
- { 0x90098, 0x18 },
- { 0x90099, 0x4 },
- { 0x9009a, 0x58 },
- { 0x9009b, 0xa },
- { 0x9009c, 0x10 },
- { 0x9009d, 0x109 },
- { 0x9009e, 0x2 },
- { 0x9009f, 0x10 },
- { 0x900a0, 0x109 },
- { 0x900a1, 0x5 },
- { 0x900a2, 0x7c0 },
- { 0x900a3, 0x109 },
- { 0x900a4, 0x10 },
- { 0x900a5, 0x10 },
- { 0x900a6, 0x109 },
- { 0x40000, 0x811 },
- { 0x40020, 0x880 },
- { 0x40040, 0x0 },
- { 0x40060, 0x0 },
- { 0x40001, 0x4008 },
- { 0x40021, 0x83 },
- { 0x40041, 0x4f },
- { 0x40061, 0x0 },
- { 0x40002, 0x4040 },
- { 0x40022, 0x83 },
- { 0x40042, 0x51 },
- { 0x40062, 0x0 },
- { 0x40003, 0x811 },
- { 0x40023, 0x880 },
- { 0x40043, 0x0 },
- { 0x40063, 0x0 },
- { 0x40004, 0x720 },
- { 0x40024, 0xf },
- { 0x40044, 0x1740 },
- { 0x40064, 0x0 },
- { 0x40005, 0x16 },
- { 0x40025, 0x83 },
- { 0x40045, 0x4b },
- { 0x40065, 0x0 },
- { 0x40006, 0x716 },
- { 0x40026, 0xf },
- { 0x40046, 0x2001 },
- { 0x40066, 0x0 },
- { 0x40007, 0x716 },
- { 0x40027, 0xf },
- { 0x40047, 0x2800 },
- { 0x40067, 0x0 },
- { 0x40008, 0x716 },
- { 0x40028, 0xf },
- { 0x40048, 0xf00 },
- { 0x40068, 0x0 },
- { 0x40009, 0x720 },
- { 0x40029, 0xf },
- { 0x40049, 0x1400 },
- { 0x40069, 0x0 },
- { 0x4000a, 0xe08 },
- { 0x4002a, 0xc15 },
- { 0x4004a, 0x0 },
- { 0x4006a, 0x0 },
- { 0x4000b, 0x623 },
- { 0x4002b, 0x15 },
- { 0x4004b, 0x0 },
- { 0x4006b, 0x0 },
- { 0x4000c, 0x4028 },
- { 0x4002c, 0x80 },
- { 0x4004c, 0x0 },
- { 0x4006c, 0x0 },
- { 0x4000d, 0xe08 },
- { 0x4002d, 0xc1a },
- { 0x4004d, 0x0 },
- { 0x4006d, 0x0 },
- { 0x4000e, 0x623 },
- { 0x4002e, 0x1a },
- { 0x4004e, 0x0 },
- { 0x4006e, 0x0 },
- { 0x4000f, 0x4040 },
- { 0x4002f, 0x80 },
- { 0x4004f, 0x0 },
- { 0x4006f, 0x0 },
- { 0x40010, 0x2604 },
- { 0x40030, 0x15 },
- { 0x40050, 0x0 },
- { 0x40070, 0x0 },
- { 0x40011, 0x708 },
- { 0x40031, 0x5 },
- { 0x40051, 0x0 },
- { 0x40071, 0x2002 },
- { 0x40012, 0x8 },
- { 0x40032, 0x80 },
- { 0x40052, 0x0 },
- { 0x40072, 0x0 },
- { 0x40013, 0x2604 },
- { 0x40033, 0x1a },
- { 0x40053, 0x0 },
- { 0x40073, 0x0 },
- { 0x40014, 0x708 },
- { 0x40034, 0xa },
- { 0x40054, 0x0 },
- { 0x40074, 0x2002 },
- { 0x40015, 0x4040 },
- { 0x40035, 0x80 },
- { 0x40055, 0x0 },
- { 0x40075, 0x0 },
- { 0x40016, 0x60a },
- { 0x40036, 0x15 },
- { 0x40056, 0x1200 },
- { 0x40076, 0x0 },
- { 0x40017, 0x61a },
- { 0x40037, 0x15 },
- { 0x40057, 0x1300 },
- { 0x40077, 0x0 },
- { 0x40018, 0x60a },
- { 0x40038, 0x1a },
- { 0x40058, 0x1200 },
- { 0x40078, 0x0 },
- { 0x40019, 0x642 },
- { 0x40039, 0x1a },
- { 0x40059, 0x1300 },
- { 0x40079, 0x0 },
- { 0x4001a, 0x4808 },
- { 0x4003a, 0x880 },
- { 0x4005a, 0x0 },
- { 0x4007a, 0x0 },
- { 0x900a7, 0x0 },
- { 0x900a8, 0x790 },
- { 0x900a9, 0x11a },
- { 0x900aa, 0x8 },
- { 0x900ab, 0x7aa },
- { 0x900ac, 0x2a },
- { 0x900ad, 0x10 },
- { 0x900ae, 0x7b2 },
- { 0x900af, 0x2a },
- { 0x900b0, 0x0 },
- { 0x900b1, 0x7c8 },
- { 0x900b2, 0x109 },
- { 0x900b3, 0x10 },
- { 0x900b4, 0x2a8 },
- { 0x900b5, 0x129 },
- { 0x900b6, 0x8 },
- { 0x900b7, 0x370 },
- { 0x900b8, 0x129 },
- { 0x900b9, 0xa },
- { 0x900ba, 0x3c8 },
- { 0x900bb, 0x1a9 },
- { 0x900bc, 0xc },
- { 0x900bd, 0x408 },
- { 0x900be, 0x199 },
- { 0x900bf, 0x14 },
- { 0x900c0, 0x790 },
- { 0x900c1, 0x11a },
- { 0x900c2, 0x8 },
- { 0x900c3, 0x4 },
- { 0x900c4, 0x18 },
- { 0x900c5, 0xe },
- { 0x900c6, 0x408 },
- { 0x900c7, 0x199 },
- { 0x900c8, 0x8 },
- { 0x900c9, 0x8568 },
- { 0x900ca, 0x108 },
- { 0x900cb, 0x18 },
- { 0x900cc, 0x790 },
- { 0x900cd, 0x16a },
- { 0x900ce, 0x8 },
- { 0x900cf, 0x1d8 },
- { 0x900d0, 0x169 },
- { 0x900d1, 0x10 },
- { 0x900d2, 0x8558 },
- { 0x900d3, 0x168 },
- { 0x900d4, 0x70 },
- { 0x900d5, 0x788 },
- { 0x900d6, 0x16a },
- { 0x900d7, 0x1ff8 },
- { 0x900d8, 0x85a8 },
- { 0x900d9, 0x1e8 },
- { 0x900da, 0x50 },
- { 0x900db, 0x798 },
- { 0x900dc, 0x16a },
- { 0x900dd, 0x60 },
- { 0x900de, 0x7a0 },
- { 0x900df, 0x16a },
- { 0x900e0, 0x8 },
- { 0x900e1, 0x8310 },
- { 0x900e2, 0x168 },
- { 0x900e3, 0x8 },
- { 0x900e4, 0xa310 },
- { 0x900e5, 0x168 },
- { 0x900e6, 0xa },
- { 0x900e7, 0x408 },
- { 0x900e8, 0x169 },
- { 0x900e9, 0x6e },
- { 0x900ea, 0x0 },
- { 0x900eb, 0x68 },
- { 0x900ec, 0x0 },
- { 0x900ed, 0x408 },
- { 0x900ee, 0x169 },
- { 0x900ef, 0x0 },
- { 0x900f0, 0x8310 },
- { 0x900f1, 0x168 },
- { 0x900f2, 0x0 },
- { 0x900f3, 0xa310 },
- { 0x900f4, 0x168 },
- { 0x900f5, 0x1ff8 },
- { 0x900f6, 0x85a8 },
- { 0x900f7, 0x1e8 },
- { 0x900f8, 0x68 },
- { 0x900f9, 0x798 },
- { 0x900fa, 0x16a },
- { 0x900fb, 0x78 },
- { 0x900fc, 0x7a0 },
- { 0x900fd, 0x16a },
- { 0x900fe, 0x68 },
- { 0x900ff, 0x790 },
- { 0x90100, 0x16a },
- { 0x90101, 0x8 },
- { 0x90102, 0x8b10 },
- { 0x90103, 0x168 },
- { 0x90104, 0x8 },
- { 0x90105, 0xab10 },
- { 0x90106, 0x168 },
- { 0x90107, 0xa },
- { 0x90108, 0x408 },
- { 0x90109, 0x169 },
- { 0x9010a, 0x58 },
- { 0x9010b, 0x0 },
- { 0x9010c, 0x68 },
- { 0x9010d, 0x0 },
- { 0x9010e, 0x408 },
- { 0x9010f, 0x169 },
- { 0x90110, 0x0 },
- { 0x90111, 0x8b10 },
- { 0x90112, 0x168 },
- { 0x90113, 0x0 },
- { 0x90114, 0xab10 },
- { 0x90115, 0x168 },
- { 0x90116, 0x0 },
- { 0x90117, 0x1d8 },
- { 0x90118, 0x169 },
- { 0x90119, 0x80 },
- { 0x9011a, 0x790 },
- { 0x9011b, 0x16a },
- { 0x9011c, 0x18 },
- { 0x9011d, 0x7aa },
- { 0x9011e, 0x6a },
- { 0x9011f, 0xa },
- { 0x90120, 0x0 },
- { 0x90121, 0x1e9 },
- { 0x90122, 0x8 },
- { 0x90123, 0x8080 },
- { 0x90124, 0x108 },
- { 0x90125, 0xf },
- { 0x90126, 0x408 },
- { 0x90127, 0x169 },
- { 0x90128, 0xc },
- { 0x90129, 0x0 },
- { 0x9012a, 0x68 },
- { 0x9012b, 0x9 },
- { 0x9012c, 0x0 },
- { 0x9012d, 0x1a9 },
- { 0x9012e, 0x0 },
- { 0x9012f, 0x408 },
- { 0x90130, 0x169 },
- { 0x90131, 0x0 },
- { 0x90132, 0x8080 },
- { 0x90133, 0x108 },
- { 0x90134, 0x8 },
- { 0x90135, 0x7aa },
- { 0x90136, 0x6a },
- { 0x90137, 0x0 },
- { 0x90138, 0x8568 },
- { 0x90139, 0x108 },
- { 0x9013a, 0xb7 },
- { 0x9013b, 0x790 },
- { 0x9013c, 0x16a },
- { 0x9013d, 0x1f },
- { 0x9013e, 0x0 },
- { 0x9013f, 0x68 },
- { 0x90140, 0x8 },
- { 0x90141, 0x8558 },
- { 0x90142, 0x168 },
- { 0x90143, 0xf },
- { 0x90144, 0x408 },
- { 0x90145, 0x169 },
- { 0x90146, 0xc },
- { 0x90147, 0x0 },
- { 0x90148, 0x68 },
- { 0x90149, 0x0 },
- { 0x9014a, 0x408 },
- { 0x9014b, 0x169 },
- { 0x9014c, 0x0 },
- { 0x9014d, 0x8558 },
- { 0x9014e, 0x168 },
- { 0x9014f, 0x8 },
- { 0x90150, 0x3c8 },
- { 0x90151, 0x1a9 },
- { 0x90152, 0x3 },
- { 0x90153, 0x370 },
- { 0x90154, 0x129 },
- { 0x90155, 0x20 },
- { 0x90156, 0x2aa },
- { 0x90157, 0x9 },
- { 0x90158, 0x0 },
- { 0x90159, 0x400 },
- { 0x9015a, 0x10e },
- { 0x9015b, 0x8 },
- { 0x9015c, 0xe8 },
- { 0x9015d, 0x109 },
- { 0x9015e, 0x0 },
- { 0x9015f, 0x8140 },
- { 0x90160, 0x10c },
- { 0x90161, 0x10 },
- { 0x90162, 0x8138 },
- { 0x90163, 0x10c },
- { 0x90164, 0x8 },
- { 0x90165, 0x7c8 },
- { 0x90166, 0x101 },
- { 0x90167, 0x8 },
- { 0x90168, 0x0 },
- { 0x90169, 0x8 },
- { 0x9016a, 0x8 },
- { 0x9016b, 0x448 },
- { 0x9016c, 0x109 },
- { 0x9016d, 0xf },
- { 0x9016e, 0x7c0 },
- { 0x9016f, 0x109 },
- { 0x90170, 0x0 },
- { 0x90171, 0xe8 },
- { 0x90172, 0x109 },
- { 0x90173, 0x47 },
- { 0x90174, 0x630 },
- { 0x90175, 0x109 },
- { 0x90176, 0x8 },
- { 0x90177, 0x618 },
- { 0x90178, 0x109 },
- { 0x90179, 0x8 },
- { 0x9017a, 0xe0 },
- { 0x9017b, 0x109 },
- { 0x9017c, 0x0 },
- { 0x9017d, 0x7c8 },
- { 0x9017e, 0x109 },
- { 0x9017f, 0x8 },
- { 0x90180, 0x8140 },
- { 0x90181, 0x10c },
- { 0x90182, 0x0 },
- { 0x90183, 0x1 },
- { 0x90184, 0x8 },
- { 0x90185, 0x8 },
- { 0x90186, 0x4 },
- { 0x90187, 0x8 },
- { 0x90188, 0x8 },
- { 0x90189, 0x7c8 },
- { 0x9018a, 0x101 },
- { 0x90006, 0x0 },
- { 0x90007, 0x0 },
- { 0x90008, 0x8 },
- { 0x90009, 0x0 },
- { 0x9000a, 0x0 },
- { 0x9000b, 0x0 },
- { 0xd00e7, 0x400 },
- { 0x90017, 0x0 },
- { 0x9001f, 0x2a },
- { 0x90026, 0x6a },
- { 0x400d0, 0x0 },
- { 0x400d1, 0x101 },
- { 0x400d2, 0x105 },
- { 0x400d3, 0x107 },
- { 0x400d4, 0x10f },
- { 0x400d5, 0x202 },
- { 0x400d6, 0x20a },
- { 0x400d7, 0x20b },
- { 0x2003a, 0x2 },
- { 0x2000b, 0x5d },
- { 0x2000c, 0xbb },
- { 0x2000d, 0x753 },
- { 0x2000e, 0x2c },
- { 0x12000b, 0xc },
- { 0x12000c, 0x19 },
- { 0x12000d, 0xfa },
- { 0x12000e, 0x10 },
- { 0x22000b, 0x3 },
- { 0x22000c, 0x6 },
- { 0x22000d, 0x3e },
- { 0x22000e, 0x10 },
- { 0x9000c, 0x0 },
- { 0x9000d, 0x173 },
- { 0x9000e, 0x60 },
- { 0x9000f, 0x6110 },
- { 0x90010, 0x2152 },
- { 0x90011, 0xdfbd },
- { 0x90012, 0x60 },
- { 0x90013, 0x6152 },
- { 0x20010, 0x5a },
- { 0x20011, 0x3 },
- { 0x120010, 0x5a },
- { 0x120011, 0x3 },
- { 0x220010, 0x5a },
- { 0x220011, 0x3 },
- { 0x40080, 0xe0 },
- { 0x40081, 0x12 },
- { 0x40082, 0xe0 },
- { 0x40083, 0x12 },
- { 0x40084, 0xe0 },
- { 0x40085, 0x12 },
- { 0x140080, 0xe0 },
- { 0x140081, 0x12 },
- { 0x140082, 0xe0 },
- { 0x140083, 0x12 },
- { 0x140084, 0xe0 },
- { 0x140085, 0x12 },
- { 0x240080, 0xe0 },
- { 0x240081, 0x12 },
- { 0x240082, 0xe0 },
- { 0x240083, 0x12 },
- { 0x240084, 0xe0 },
- { 0x240085, 0x12 },
- { 0x400fd, 0xf },
- { 0x10011, 0x1 },
- { 0x10012, 0x1 },
- { 0x10013, 0x180 },
- { 0x10018, 0x1 },
- { 0x10002, 0x6209 },
- { 0x100b2, 0x1 },
- { 0x101b4, 0x1 },
- { 0x102b4, 0x1 },
- { 0x103b4, 0x1 },
- { 0x104b4, 0x1 },
- { 0x105b4, 0x1 },
- { 0x106b4, 0x1 },
- { 0x107b4, 0x1 },
- { 0x108b4, 0x1 },
- { 0x11011, 0x1 },
- { 0x11012, 0x1 },
- { 0x11013, 0x180 },
- { 0x11018, 0x1 },
- { 0x11002, 0x6209 },
- { 0x110b2, 0x1 },
- { 0x111b4, 0x1 },
- { 0x112b4, 0x1 },
- { 0x113b4, 0x1 },
- { 0x114b4, 0x1 },
- { 0x115b4, 0x1 },
- { 0x116b4, 0x1 },
- { 0x117b4, 0x1 },
- { 0x118b4, 0x1 },
- { 0x12011, 0x1 },
- { 0x12012, 0x1 },
- { 0x12013, 0x180 },
- { 0x12018, 0x1 },
- { 0x12002, 0x6209 },
- { 0x120b2, 0x1 },
- { 0x121b4, 0x1 },
- { 0x122b4, 0x1 },
- { 0x123b4, 0x1 },
- { 0x124b4, 0x1 },
- { 0x125b4, 0x1 },
- { 0x126b4, 0x1 },
- { 0x127b4, 0x1 },
- { 0x128b4, 0x1 },
- { 0x13011, 0x1 },
- { 0x13012, 0x1 },
- { 0x13013, 0x180 },
- { 0x13018, 0x1 },
- { 0x13002, 0x6209 },
- { 0x130b2, 0x1 },
- { 0x131b4, 0x1 },
- { 0x132b4, 0x1 },
- { 0x133b4, 0x1 },
- { 0x134b4, 0x1 },
- { 0x135b4, 0x1 },
- { 0x136b4, 0x1 },
- { 0x137b4, 0x1 },
- { 0x138b4, 0x1 },
- { 0x2003a, 0x2 },
- { 0xc0080, 0x2 },
- { 0xd0000, 0x1 }
-};
-
-static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
- {
- /* P0 3000mts 1D */
- .drate = 3000,
- .fw_type = FW_1D_IMAGE,
- .fsp_cfg = ddr_fsp0_cfg,
- .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
- },
- {
- /* P1 400mts 1D */
- .drate = 400,
- .fw_type = FW_1D_IMAGE,
- .fsp_cfg = ddr_fsp1_cfg,
- .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
- },
- {
- /* P2 100mts 1D */
- .drate = 100,
- .fw_type = FW_1D_IMAGE,
- .fsp_cfg = ddr_fsp2_cfg,
- .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
- },
- {
- /* P0 3000mts 2D */
- .drate = 3000,
- .fw_type = FW_2D_IMAGE,
- .fsp_cfg = ddr_fsp0_2d_cfg,
- .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
- },
-};
-
-/* ddr timing config params */
-struct dram_timing_info dram_timing_512mb = {
- .ddrc_cfg = ddr_ddrc_cfg,
- .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
- .ddrphy_cfg = ddr_ddrphy_cfg,
- .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
- .fsp_msg = ddr_dram_fsp_msg,
- .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
- .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
- .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
- .ddrphy_pie = ddr_phy_pie,
- .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 3000, 400, 100, },
-};
diff --git a/board/gateworks/venice/lpddr4_timing_imx8mp.c b/board/gateworks/venice/lpddr4_timing_imx8mp.c
index 7bfd1b5..56c6e2b 100644
--- a/board/gateworks/venice/lpddr4_timing_imx8mp.c
+++ b/board/gateworks/venice/lpddr4_timing_imx8mp.c
@@ -1211,9 +1211,9 @@
{ 0x400d7, 0x20b },
{ 0x2003a, 0x2 },
{ 0x200be, 0x3 },
- { 0x2000b, 0x34b },
- { 0x2000c, 0xbb },
- { 0x2000d, 0x753 },
+ { 0x2000b, 0x465 },
+ { 0x2000c, 0xfa },
+ { 0x2000d, 0x9c4 },
{ 0x2000e, 0x2c },
{ 0x12000b, 0x70 },
{ 0x12000c, 0x19 },
@@ -1323,42 +1323,42 @@
{ 0x3d400304, 0x1 },
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa1080020 },
- { 0x3d400020, 0x1203 },
- { 0x3d400024, 0x16e3600 },
- { 0x3d400064, 0x5b0087 },
+ { 0x3d400020, 0x1323 },
+ { 0x3d400024, 0x1e84800 },
+ { 0x3d400064, 0x7a00b4 },
{ 0x3d400070, 0x7027f90 },
{ 0x3d400074, 0x790 },
- { 0x3d4000d0, 0xc00305ba },
- { 0x3d4000d4, 0x940000 },
- { 0x3d4000dc, 0xd4002d },
- { 0x3d4000e0, 0x310000 },
+ { 0x3d4000d0, 0xc00307a3 },
+ { 0x3d4000d4, 0xc50000 },
+ { 0x3d4000dc, 0xf4003f },
+ { 0x3d4000e0, 0x330000 },
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
- { 0x3d400100, 0x191e1920 },
- { 0x3d400104, 0x60630 },
- { 0x3d40010c, 0xb0b000 },
- { 0x3d400110, 0xe04080e },
- { 0x3d400114, 0x2040c0c },
- { 0x3d400118, 0x1010007 },
- { 0x3d40011c, 0x402 },
- { 0x3d400130, 0x20600 },
- { 0x3d400134, 0xc100002 },
- { 0x3d400138, 0x8d },
- { 0x3d400144, 0x96004b },
- { 0x3d400180, 0x2ee0017 },
- { 0x3d400184, 0x2605b8e },
+ { 0x3d400100, 0x2028222a },
+ { 0x3d400104, 0x8083f },
+ { 0x3d40010c, 0xe0e000 },
+ { 0x3d400110, 0x12040a12 },
+ { 0x3d400114, 0x2050f0f },
+ { 0x3d400118, 0x1010009 },
+ { 0x3d40011c, 0x502 },
+ { 0x3d400130, 0x20800 },
+ { 0x3d400134, 0xe100002 },
+ { 0x3d400138, 0xbc },
+ { 0x3d400144, 0xc80064 },
+ { 0x3d400180, 0x3e8001e },
+ { 0x3d400184, 0x3207a12 },
{ 0x3d400188, 0x0 },
- { 0x3d400190, 0x497820a },
+ { 0x3d400190, 0x49f820e },
{ 0x3d400194, 0x80303 },
- { 0x3d4001b4, 0x170a },
+ { 0x3d4001b4, 0x1f0e },
{ 0x3d4001a0, 0xe0400018 },
{ 0x3d4001a4, 0xdf00e4 },
{ 0x3d4001a8, 0x80000000 },
{ 0x3d4001b0, 0x11 },
{ 0x3d4001c0, 0x1 },
{ 0x3d4001c4, 0x1 },
- { 0x3d4000f4, 0x699 },
- { 0x3d400108, 0x70e1617 },
+ { 0x3d4000f4, 0x799 },
+ { 0x3d400108, 0x9121b1c },
{ 0x3d400200, 0x1f },
{ 0x3d400208, 0x0 },
{ 0x3d40020c, 0x0 },
@@ -1379,7 +1379,7 @@
{ 0x3d400498, 0x620096 },
{ 0x3d40049c, 0x1100e07 },
{ 0x3d4004a0, 0xc8012c },
- { 0x3d402020, 0x1001 },
+ { 0x3d402020, 0x1021 },
{ 0x3d402024, 0x30d400 },
{ 0x3d402050, 0x20d000 },
{ 0x3d402064, 0xc0012 },
@@ -1404,7 +1404,7 @@
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
{ 0x3d4020f4, 0x599 },
- { 0x3d403020, 0x1001 },
+ { 0x3d403020, 0x1021 },
{ 0x3d403024, 0xc3500 },
{ 0x3d403050, 0x20d000 },
{ 0x3d403064, 0x30005 },
@@ -1436,36 +1436,36 @@
struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = {
{ 0x100a0, 0x0 },
{ 0x100a1, 0x1 },
- { 0x100a2, 0x3 },
- { 0x100a3, 0x2 },
- { 0x100a4, 0x5 },
- { 0x100a5, 0x4 },
- { 0x100a6, 0x7 },
- { 0x100a7, 0x6 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
{ 0x110a0, 0x0 },
{ 0x110a1, 0x1 },
- { 0x110a2, 0x2 },
- { 0x110a3, 0x3 },
- { 0x110a4, 0x4 },
- { 0x110a5, 0x5 },
- { 0x110a6, 0x6 },
- { 0x110a7, 0x7 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
{ 0x120a0, 0x0 },
{ 0x120a1, 0x1 },
- { 0x120a2, 0x2 },
- { 0x120a3, 0x3 },
- { 0x120a4, 0x4 },
- { 0x120a5, 0x5 },
- { 0x120a6, 0x6 },
- { 0x120a7, 0x7 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x7 },
+ { 0x120a7, 0x6 },
{ 0x130a0, 0x0 },
{ 0x130a1, 0x1 },
- { 0x130a2, 0x3 },
- { 0x130a3, 0x4 },
- { 0x130a4, 0x5 },
- { 0x130a5, 0x2 },
- { 0x130a6, 0x7 },
- { 0x130a7, 0x6 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x6 },
+ { 0x130a7, 0x7 },
{ 0x1005f, 0x1ff },
{ 0x1015f, 0x1ff },
{ 0x1105f, 0x1ff },
@@ -1500,7 +1500,7 @@
{ 0x7055, 0x1ff },
{ 0x8055, 0x1ff },
{ 0x9055, 0x1ff },
- { 0x200c5, 0x19 },
+ { 0x200c5, 0x18 },
{ 0x1200c5, 0x7 },
{ 0x2200c5, 0x7 },
{ 0x2002e, 0x2 },
@@ -1509,11 +1509,11 @@
{ 0x90204, 0x0 },
{ 0x190204, 0x0 },
{ 0x290204, 0x0 },
- { 0x20024, 0x1a3 },
+ { 0x20024, 0x1e3 },
{ 0x2003a, 0x2 },
- { 0x120024, 0x1a3 },
+ { 0x120024, 0x1e3 },
{ 0x2003a, 0x2 },
- { 0x220024, 0x1a3 },
+ { 0x220024, 0x1e3 },
{ 0x2003a, 0x2 },
{ 0x20056, 0x3 },
{ 0x120056, 0x3 },
@@ -1579,7 +1579,7 @@
{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
- { 0x20008, 0x2ee },
+ { 0x20008, 0x3e8 },
{ 0x120008, 0x64 },
{ 0x220008, 0x19 },
{ 0x20088, 0x9 },
@@ -1644,7 +1644,7 @@
/* P0 message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_cfg_1gb_single_die[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xbb8 },
+ { 0x54003, 0xfa0 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
@@ -1653,26 +1653,26 @@
{ 0x5400b, 0x2 },
{ 0x5400f, 0x100 },
{ 0x54012, 0x110 },
- { 0x54019, 0x2dd4 },
- { 0x5401a, 0x31 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x33 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
- { 0x5401f, 0x2dd4 },
- { 0x54020, 0x31 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x33 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
- { 0x54032, 0xd400 },
- { 0x54033, 0x312d },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x333f },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
- { 0x54038, 0xd400 },
- { 0x54039, 0x312d },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x333f },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1763,7 +1763,7 @@
/* P0 2D message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_2d_cfg_1gb_single_die[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xbb8 },
+ { 0x54003, 0xfa0 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
@@ -1773,26 +1773,26 @@
{ 0x5400f, 0x100 },
{ 0x54010, 0x1f7f },
{ 0x54012, 0x110 },
- { 0x54019, 0x2dd4 },
- { 0x5401a, 0x31 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x33 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
- { 0x5401f, 0x2dd4 },
- { 0x54020, 0x31 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x33 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
- { 0x54032, 0xd400 },
- { 0x54033, 0x312d },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x333f },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
- { 0x54038, 0xd400 },
- { 0x54039, 0x312d },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x333f },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1802,8 +1802,8 @@
struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = {
{
- /* P0 3000mts 1D */
- .drate = 3000,
+ /* P0 4000mts 1D */
+ .drate = 4000,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg_1gb_single_die,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_1gb_single_die),
@@ -1823,8 +1823,8 @@
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_1gb_single_die),
},
{
- /* P0 3000mts 2D */
- .drate = 3000,
+ /* P0 4000mts 2D */
+ .drate = 4000,
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg_1gb_single_die,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_1gb_single_die),
@@ -1843,7 +1843,7 @@
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 3000, 400, 100, },
+ .fsp_table = { 4000, 400, 100, },
};
/*
@@ -1856,43 +1856,44 @@
{ 0x3d400304, 0x1 },
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa3080020 },
- { 0x3d400020, 0x1203 },
- { 0x3d400024, 0x16e3600 },
- { 0x3d400064, 0x5b00d2 },
+ { 0x3d400020, 0x1323 },
+ { 0x3d400024, 0x1e84800 },
+ { 0x3d400064, 0x7a0118 },
{ 0x3d400070, 0x7027f90 },
{ 0x3d400074, 0x790 },
- { 0x3d4000d0, 0xc00305ba },
- { 0x3d4000d4, 0x940000 },
- { 0x3d4000dc, 0xd4002d },
- { 0x3d4000e0, 0x310000 },
+ { 0x3d4000d0, 0xc00307a3 },
+ { 0x3d4000d4, 0xc50000 },
+ { 0x3d4000dc, 0xf4003f },
+ { 0x3d4000e0, 0x330000 },
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
- { 0x3d400100, 0x191e1920 },
- { 0x3d400104, 0x60630 },
- { 0x3d40010c, 0xb0b000 },
- { 0x3d400110, 0xe04080e },
- { 0x3d400114, 0x2040c0c },
- { 0x3d400118, 0x1010007 },
- { 0x3d40011c, 0x401 },
- { 0x3d400130, 0x20600 },
- { 0x3d400134, 0xc100002 },
- { 0x3d400138, 0xd8 },
- { 0x3d400144, 0x96004b },
- { 0x3d400180, 0x2ee0017 },
- { 0x3d400184, 0x2605b8e },
+ { 0x3d400100, 0x2028222a },
+ { 0x3d400104, 0x8083f },
+ { 0x3d40010c, 0xe0e000 },
+ { 0x3d400110, 0x12040a12 },
+ { 0x3d400114, 0x2050f0f },
+ { 0x3d400118, 0x1010009 },
+ { 0x3d40011c, 0x502 },
+ { 0x3d400130, 0x20800 },
+ { 0x3d400134, 0xe100002 },
+ { 0x3d400138, 0x120 },
+ { 0x3d400144, 0xc80064 },
+ { 0x3d400180, 0x3e8001e },
+ { 0x3d400184, 0x3207a12 },
{ 0x3d400188, 0x0 },
- { 0x3d400190, 0x497820a },
+ { 0x3d400190, 0x49f820e},
{ 0x3d400194, 0x80303 },
- { 0x3d4001b4, 0x170a },
+ { 0x3d4001b4, 0x1f0e },
{ 0x3d4001a0, 0xe0400018 },
{ 0x3d4001a4, 0xdf00e4 },
{ 0x3d4001a8, 0x80000000 },
{ 0x3d4001b0, 0x11 },
{ 0x3d4001c0, 0x1 },
{ 0x3d4001c4, 0x1 },
- { 0x3d4000f4, 0xc99 },
- { 0x3d400108, 0x70e1617 },
+ { 0x3d4000f4, 0x799 },
+ { 0x3d400108, 0x9121b1c },
{ 0x3d400200, 0x17 },
+ { 0x3d400208, 0x0 },
{ 0x3d40020c, 0x0 },
{ 0x3d400210, 0x1f1f },
{ 0x3d400204, 0x80808 },
@@ -1911,7 +1912,7 @@
{ 0x3d400498, 0x620096 },
{ 0x3d40049c, 0x1100e07 },
{ 0x3d4004a0, 0xc8012c },
- { 0x3d402020, 0x1001 },
+ { 0x3d402020, 0x1021 },
{ 0x3d402024, 0x30d400 },
{ 0x3d402050, 0x20d000 },
{ 0x3d402064, 0xc001c },
@@ -1926,7 +1927,7 @@
{ 0x3d402110, 0x2040202 },
{ 0x3d402114, 0x2030202 },
{ 0x3d402118, 0x1010004 },
- { 0x3d40211c, 0x301 },
+ { 0x3d40211c, 0x302 },
{ 0x3d402130, 0x20300 },
{ 0x3d402134, 0xa100002 },
{ 0x3d402138, 0x1d },
@@ -1935,8 +1936,8 @@
{ 0x3d402190, 0x3818200 },
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
- { 0x3d4020f4, 0xc99 },
- { 0x3d403020, 0x1001 },
+ { 0x3d4020f4, 0x599 },
+ { 0x3d403020, 0x1021 },
{ 0x3d403024, 0xc3500 },
{ 0x3d403050, 0x20d000 },
{ 0x3d403064, 0x30007 },
@@ -1951,7 +1952,7 @@
{ 0x3d403110, 0x2040202 },
{ 0x3d403114, 0x2030202 },
{ 0x3d403118, 0x1010004 },
- { 0x3d40311c, 0x301 },
+ { 0x3d40311c, 0x302 },
{ 0x3d403130, 0x20300 },
{ 0x3d403134, 0xa100002 },
{ 0x3d403138, 0x8 },
@@ -1960,7 +1961,7 @@
{ 0x3d403190, 0x3818200 },
{ 0x3d403194, 0x80303 },
{ 0x3d4031b4, 0x100 },
- { 0x3d4030f4, 0xc99 },
+ { 0x3d4030f4, 0x599 },
{ 0x3d400028, 0x0 },
};
@@ -1968,36 +1969,36 @@
static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = {
{ 0x100a0, 0x0 },
{ 0x100a1, 0x1 },
- { 0x100a2, 0x3 },
- { 0x100a3, 0x2 },
- { 0x100a4, 0x5 },
- { 0x100a5, 0x4 },
- { 0x100a6, 0x7 },
- { 0x100a7, 0x6 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
{ 0x110a0, 0x0 },
{ 0x110a1, 0x1 },
- { 0x110a2, 0x2 },
- { 0x110a3, 0x3 },
- { 0x110a4, 0x4 },
- { 0x110a5, 0x5 },
- { 0x110a6, 0x6 },
- { 0x110a7, 0x7 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
{ 0x120a0, 0x0 },
{ 0x120a1, 0x1 },
- { 0x120a2, 0x2 },
- { 0x120a3, 0x3 },
- { 0x120a4, 0x4 },
- { 0x120a5, 0x5 },
- { 0x120a6, 0x6 },
- { 0x120a7, 0x7 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x7 },
+ { 0x120a7, 0x6 },
{ 0x130a0, 0x0 },
{ 0x130a1, 0x1 },
- { 0x130a2, 0x3 },
- { 0x130a3, 0x4 },
- { 0x130a4, 0x5 },
- { 0x130a5, 0x2 },
- { 0x130a6, 0x7 },
- { 0x130a7, 0x6 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x6 },
+ { 0x130a7, 0x7 },
{ 0x1005f, 0x1ff },
{ 0x1015f, 0x1ff },
{ 0x1105f, 0x1ff },
@@ -2032,7 +2033,7 @@
{ 0x7055, 0x1ff },
{ 0x8055, 0x1ff },
{ 0x9055, 0x1ff },
- { 0x200c5, 0x19 },
+ { 0x200c5, 0x18 },
{ 0x1200c5, 0x7 },
{ 0x2200c5, 0x7 },
{ 0x2002e, 0x2 },
@@ -2041,11 +2042,11 @@
{ 0x90204, 0x0 },
{ 0x190204, 0x0 },
{ 0x290204, 0x0 },
- { 0x20024, 0x1a3 },
+ { 0x20024, 0x1e3 },
{ 0x2003a, 0x2 },
- { 0x120024, 0x1a3 },
+ { 0x120024, 0x1e3 },
{ 0x2003a, 0x2 },
- { 0x220024, 0x1a3 },
+ { 0x220024, 0x1e3 },
{ 0x2003a, 0x2 },
{ 0x20056, 0x3 },
{ 0x120056, 0x3 },
@@ -2111,7 +2112,7 @@
{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
- { 0x20008, 0x2ee },
+ { 0x20008, 0x3e8 },
{ 0x120008, 0x64 },
{ 0x220008, 0x19 },
{ 0x20088, 0x9 },
@@ -2175,7 +2176,7 @@
static struct dram_cfg_param ddr_fsp0_cfg_4gb_dual_die[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xbb8 },
+ { 0x54003, 0xfa0 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
@@ -2184,26 +2185,26 @@
{ 0x5400b, 0x2 },
{ 0x5400f, 0x100 },
{ 0x54012, 0x310 },
- { 0x54019, 0x2dd4 },
- { 0x5401a, 0x31 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x33 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
- { 0x5401f, 0x2dd4 },
- { 0x54020, 0x31 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x33 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
- { 0x54032, 0xd400 },
- { 0x54033, 0x312d },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x333f },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
- { 0x54038, 0xd400 },
- { 0x54039, 0x312d },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x333f },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -2294,7 +2295,7 @@
/* P0 2D message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_2d_cfg_4gb_dual_die[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xbb8 },
+ { 0x54003, 0xfa0 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
@@ -2304,26 +2305,26 @@
{ 0x5400f, 0x100 },
{ 0x54010, 0x1f7f },
{ 0x54012, 0x310 },
- { 0x54019, 0x2dd4 },
- { 0x5401a, 0x31 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x33 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
- { 0x5401f, 0x2dd4 },
- { 0x54020, 0x31 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x33 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
- { 0x54032, 0xd400 },
- { 0x54033, 0x312d },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x333f },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
- { 0x54038, 0xd400 },
- { 0x54039, 0x312d },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x333f },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -2333,8 +2334,8 @@
static struct dram_fsp_msg ddr_dram_fsp_msg_4gb_dual_die[] = {
{
- /* P0 3000mts 1D */
- .drate = 3000,
+ /* P0 4000mts 1D */
+ .drate = 4000,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg_4gb_dual_die,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_4gb_dual_die),
@@ -2354,8 +2355,8 @@
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_4gb_dual_die),
},
{
- /* P0 3000mts 2D */
- .drate = 3000,
+ /* P0 4000mts 2D */
+ .drate = 4000,
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg_4gb_dual_die,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_4gb_dual_die),
@@ -2374,5 +2375,5 @@
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 3000, 400, 100, },
+ .fsp_table = { 4000, 400, 100, },
};
diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
index 5aa2095..b0a315b 100644
--- a/board/gateworks/venice/spl.c
+++ b/board/gateworks/venice/spl.c
@@ -19,6 +19,7 @@
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/ddr.h>
#include <asm-generic/gpio.h>
+#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/pinctrl.h>
@@ -158,9 +159,9 @@
}
else if (!strncmp(model, "GW74", 4)) {
- ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
+ ret = uclass_get_device_by_seq(UCLASS_I2C, 2, &bus);
if (ret) {
- printf("PMIC : failed I2C1 probe: %d\n", ret);
+ printf("PMIC : failed I2C3 probe: %d\n", ret);
return ret;
}
ret = dm_i2c_probe(bus, 0x25, 0, &dev);
@@ -345,7 +346,7 @@
}
}
-unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long raw_sect)
+unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long raw_sect)
{
if (!IS_SD(mmc)) {
switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) {
diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c
index a39ae58..0902a1d 100644
--- a/board/gateworks/venice/venice.c
+++ b/board/gateworks/venice/venice.c
@@ -238,12 +238,12 @@
if (!strncmp(base_model, "GW73", 4)) {
pcbrev = get_pcb_rev(base_model);
- if (pcbrev > 'B') {
+ if (pcbrev > 'B' && pcbrev < 'E') {
printf("adjusting dt for %s\n", base_model);
/*
- * revC replaced PCIe 5-port switch with 4-port
- * which changed ethernet1 PCIe GbE
+ * revC/D/E has PCIe 4-port switch which changes
+ * ethernet1 PCIe GbE:
* from: pcie@0,0/pcie@1,0/pcie@2,4/pcie@6.0
* to: pcie@0,0/pcie@1,0/pcie@2,3/pcie@5.0
*/
diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c
index ccebba7..0f620c2 100644
--- a/board/gdsys/a38x/controlcenterdc.c
+++ b/board/gdsys/a38x/controlcenterdc.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <command.h>
#include <dm.h>
+#include <event.h>
#include <init.h>
#include <miiphy.h>
#include <net.h>
@@ -35,19 +36,6 @@
#define DB_GP_88F68XX_GPP_POL_LOW 0x0
#define DB_GP_88F68XX_GPP_POL_MID 0x0
-static int get_tpm(struct udevice **devp)
-{
- int rc;
-
- rc = uclass_first_device_err(UCLASS_TPM, devp);
- if (rc) {
- printf("Could not find TPM (ret=%d)\n", rc);
- return CMD_RET_FAILURE;
- }
-
- return 0;
-}
-
/*
* Define the DDR layout / topology here in the board file. This will
* be used by the DDR3 init code in the SPL U-Boot version to configure
@@ -284,15 +272,22 @@
return 0;
}
-int last_stage_init(void)
+#ifndef CONFIG_SPL_BUILD
+static int last_stage_init(void)
{
struct udevice *tpm;
int ret;
-#ifndef CONFIG_SPL_BUILD
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ return 0;
ccdc_eth_init();
-#endif
- ret = get_tpm(&tpm);
+
+ ret = uclass_first_device_err(UCLASS_TPM, &tpm);
+ if (ret) {
+ printf("Could not find TPM (ret=%d)\n", ret);
+ return ret;
+ }
+
if (ret || tpm_init(tpm) || tpm1_startup(tpm, TPM_ST_CLEAR) ||
tpm1_continue_self_test(tpm)) {
return 1;
@@ -305,3 +300,5 @@
return 0;
}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
+#endif
diff --git a/board/gdsys/mpc8308/gazerbeam.c b/board/gdsys/mpc8308/gazerbeam.c
index ba88401..cc608c4 100644
--- a/board/gdsys/mpc8308/gazerbeam.c
+++ b/board/gdsys/mpc8308/gazerbeam.c
@@ -9,6 +9,7 @@
#include <command.h>
#include <dm.h>
#include <env.h>
+#include <event.h>
#include <fdt_support.h>
#include <fsl_esdhc.h>
#include <init.h>
@@ -124,7 +125,7 @@
osd_info->width, osd_info->height);
}
-int last_stage_init(void)
+static int last_stage_init(void)
{
int fpga_hw_rev = 0;
int i;
@@ -179,6 +180,7 @@
return 0;
}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index 4e9d841..2d89519 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -5,6 +5,7 @@
* Copyright 2012 Freescale Semiconductor, Inc.
*/
+#include <event.h>
#include <image.h>
#include <init.h>
#include <asm/arch/clock.h>
@@ -531,7 +532,7 @@
env_set(env_var_name, NULL);
}
-int last_stage_init(void)
+static int last_stage_init(void)
{
int i;
@@ -544,6 +545,7 @@
return 0;
}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
int checkboard(void)
{
diff --git a/board/geekbuying/geekbox/Makefile b/board/geekbuying/geekbox/Makefile
deleted file mode 100644
index ced2ff7..0000000
--- a/board/geekbuying/geekbox/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2016 Andreas Färber
-
-obj-y += geekbox.o
diff --git a/board/geekbuying/geekbox/geekbox.c b/board/geekbuying/geekbox/geekbox.c
deleted file mode 100644
index b0f9a5f..0000000
--- a/board/geekbuying/geekbox/geekbox.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2016 Andreas Färber
- */
-
-#include <common.h>
diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c
index 9e23f5c..9d9168d 100644
--- a/board/google/chromebook_coral/coral.c
+++ b/board/google/chromebook_coral/coral.c
@@ -33,7 +33,7 @@
int flags;
};
-static int coral_check_ll_boot(void *ctx, struct event *event)
+static int coral_check_ll_boot(void)
{
if (!ll_boot_init()) {
printf("Running as secondary loader");
@@ -57,7 +57,7 @@
return 0;
}
-EVENT_SPY(EVT_MISC_INIT_F, coral_check_ll_boot);
+EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, coral_check_ll_boot);
int arch_misc_init(void)
{
diff --git a/board/google/chromebook_link/Makefile b/board/google/chromebook_link/Makefile
deleted file mode 100644
index d84a848..0000000
--- a/board/google/chromebook_link/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2011 The Chromium OS Authors.
-# (C) Copyright 2008
-# Graeme Russ, graeme.russ@gmail.com.
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2002
-# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
-
-obj-y += link.o
diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
deleted file mode 100644
index e357e62..0000000
--- a/board/google/chromebook_link/link.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014 Google, Inc
- */
-
-#include <common.h>
diff --git a/board/google/chromebook_samus/Makefile b/board/google/chromebook_samus/Makefile
deleted file mode 100644
index 68c9e49..0000000
--- a/board/google/chromebook_samus/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2016 Google, Inc
-
-obj-y += samus.o
diff --git a/board/google/chromebook_samus/samus.c b/board/google/chromebook_samus/samus.c
deleted file mode 100644
index 83edf89..0000000
--- a/board/google/chromebook_samus/samus.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016 Google, Inc
- */
-
-#include <common.h>
diff --git a/board/google/chromebox_panther/Makefile b/board/google/chromebox_panther/Makefile
deleted file mode 100644
index 1a5518f..0000000
--- a/board/google/chromebox_panther/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2015 Google, Inc
-
-obj-y += panther.o
diff --git a/board/google/chromebox_panther/panther.c b/board/google/chromebox_panther/panther.c
deleted file mode 100644
index da3445b..0000000
--- a/board/google/chromebox_panther/panther.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015 Google, Inc
- */
-
-#include <common.h>
diff --git a/board/grinn/chiliboard/board.c b/board/grinn/chiliboard/board.c
index b472ca5..64b32ca 100644
--- a/board/grinn/chiliboard/board.c
+++ b/board/grinn/chiliboard/board.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
* Copyright (C) 2017, Grinn - http://grinn-global.com/
*/
diff --git a/board/hardkernel/odroid_m1/Makefile b/board/hardkernel/odroid_m1/Makefile
deleted file mode 100644
index ae8ea3d..0000000
--- a/board/hardkernel/odroid_m1/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += odroid_m1.o
diff --git a/board/hardkernel/odroid_m1/odroid_m1.c b/board/hardkernel/odroid_m1/odroid_m1.c
deleted file mode 100644
index 4c027f2..0000000
--- a/board/hardkernel/odroid_m1/odroid_m1.c
+++ /dev/null
@@ -1 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
diff --git a/board/hisilicon/hikey/MAINTAINERS b/board/hisilicon/hikey/MAINTAINERS
index 11088ee..1045abe 100644
--- a/board/hisilicon/hikey/MAINTAINERS
+++ b/board/hisilicon/hikey/MAINTAINERS
@@ -2,5 +2,6 @@
M: Peter Griffin <peter.griffin@linaro.org>
S: Maintained
F: board/hisilicon/hikey
+F: doc/board/hisilicon/hikey.rst
F: include/configs/hikey.h
F: configs/hikey_defconfig
diff --git a/board/hisilicon/hikey/README b/board/hisilicon/hikey/README
deleted file mode 100644
index 94e8397..0000000
--- a/board/hisilicon/hikey/README
+++ /dev/null
@@ -1,227 +0,0 @@
-Introduction
-============
-
-HiKey is the first certified 96Boards Consumer Edition board. The board/SoC has: -
-* HiSilicon Kirin 6220 eight-core ARM Cortex-A53 64-bit SoC running at 1.2GHz.
-* ARM Mali 450-MP4 GPU
-* 1GB 800MHz LPDDR3 DRAM
-* 4GB eMMC Flash Storage
-* microSD
-* 802.11a/b/g/n WiFi, Bluetooth
-
-The HiKey schematic can be found here: -
-https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey620/hardware-docs/HiKey_schematics_LeMaker_version_Rev_A1.pdf
-
-The SoC datasheet can be found here: -
-https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey620/hardware-docs/Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
-
-Currently the u-boot port supports: -
-* USB
-* eMMC
-* SD card
-* GPIO
-
-The HiKey U-Boot port has been tested with l-loader, booting ATF, which then boots
-U-Boot as the bl33.bin executable.
-
-Compile from source
-===================
-
-First get all the sources
-
- > mkdir -p ~/hikey/src ~/hikey/bin
- > cd ~/hikey/src
- > git clone https://github.com/96boards-hikey/edk2 -b testing/hikey960_v2.5
- > git clone https://github.com/ARM-software/arm-trusted-firmware
- > git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
- > git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
- > git clone https://github.com/96boards-hikey/atf-fastboot
- > wget https://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey/release/hisi-idt.py
-
-Get the BL30 mcuimage.bin binary. It is shipped as part of the UEFI source.
-The latest version can be obtained from the OpenPlatformPkg repo.
-
- > cp OpenPlatformPkg/Platforms/Hisilicon/HiKey/Binary/mcuimage.bin ~/hikey/bin/
-
-Get nvme.img binary
- > wget -P ~/hikey/bin https://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey/release/nvme.img
-
-Compile U-Boot
-==============
-
- > cd ~/hikey/src/u-boot
- > make CROSS_COMPILE=aarch64-linux-gnu- hikey_config
- > make CROSS_COMPILE=aarch64-linux-gnu-
- > cp u-boot.bin ~/hikey/bin
-
-Compile ARM Trusted Firmware (ATF)
-==================================
-
- > cd ~/hikey/src/arm-trusted-firmware
- > make CROSS_COMPILE=aarch64-linux-gnu- all fip \
- SCP_BL2=~/hikey/bin/mcuimage.bin \
- BL33=~/hikey/bin/u-boot.bin DEBUG=1 PLAT=hikey
-
-Copy the resulting FIP binary
- > cp build/hikey/debug/fip.bin ~/hikey/bin
-
-Compile ATF Fastboot
-====================
-
- > cd ~/hikey/src/atf-fastboot
- > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=hikey DEBUG=1
-
-Compile l-loader
-================
- > cd ~/hikey/src/l-loader
- > ln -sf ~/hikey/src/arm-trusted-firmware/build/hikey/debug/bl1.bin
- > ln -sf ~/hikey/src/arm-trusted-firmware/build/hikey/debug/bl2.bin
- > ln -sf ~/hikey/src/atf-fastboot/build/hikey/debug/bl1.bin fastboot.bin
- > make hikey PTABLE_LST=aosp-8g
-
-Copy the resulting binaries
- > cp *.img ~/hikey/bin
- > cp l-loader.bin ~/hikey/bin
- > cp recovery.bin ~/hikey/bin
-
-These instructions are adapted from
-https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/plat/hikey.rst
-
-FLASHING
-========
-
-1. Connect the second jumper on J15 BOOT SEL, to go into recovery mode and flash l-loader.bin with
-the hisi-idt.py utility. Then connect a USB A to B mini cable from your PC to the USB OTG port of HiKey and execute the below command.
-
-The command below assumes HiKey enumerated as the first USB serial port
-
- > sudo python ~/hikey/src/hisi-idt.py -d /dev/ttyUSB0 --img1 ~/hikey/bin/recovery.bin
-
-2. Once LED 0 comes on solid, HiKey board should be detected as a fastboot device.
-
- > sudo fastboot devices
-
-0123456789ABCDEF fastboot
-
-3. Flash the images
-
- > sudo fastboot flash ptable ~/hikey/bin/prm_ptable.img
- > sudo fastboot flash loader ~/hikey/bin/l-loader.bin
- > sudo fastboot flash fastboot ~/hikey/bin/fip.bin
- > sudo fastboot flash nvme ~/hikey/bin/nvme.img
-
-4. Disconnect second jumper on J15 BOOT SEL, and reset the board and you will now (hopefully)
- have ATF, booting u-boot from eMMC.
-
- Note: To get USB host working, also disconnect the USB OTG cable used for flashing. Otherwise you
- will get 'dwc_otg_core_host_init: Timeout!' errors.
-
-See working boot trace below on UART3 available at Low Speed Expansion header: -
-
-NOTICE: BL2: v1.5(debug):v1.5-694-g6d4f6aea
-NOTICE: BL2: Built : 09:21:42, Aug 29 2018
-INFO: BL2: Doing platform setup
-INFO: ddr3 rank1 init pass
-INFO: succeed to set ddrc 150mhz
-INFO: ddr3 rank1 init pass
-INFO: succeed to set ddrc 266mhz
-INFO: ddr3 rank1 init pass
-INFO: succeed to set ddrc 400mhz
-INFO: ddr3 rank1 init pass
-INFO: succeed to set ddrc 533mhz
-INFO: ddr3 rank1 init pass
-INFO: succeed to set ddrc 800mhz
-INFO: Samsung DDR
-INFO: ddr test value:0xa5a55a5a
-INFO: BL2: TrustZone: protecting 16777216 bytes of memory at 0x3f000000
-INFO: BL2: TrustZone: protecting 4194304 bytes of memory at 0x3e800000
-INFO: [BDID] [fff91c18] midr: 0x410fd033
-INFO: init_acpu_dvfs: pmic version 17
-INFO: init_acpu_dvfs: ACPU_CHIP_MAX_FREQ=0x186a00.
-INFO: acpu_dvfs_volt_init: success!
-INFO: acpu_dvfs_set_freq: support freq num is 5
-INFO: acpu_dvfs_set_freq: start prof is 0x4
-INFO: acpu_dvfs_set_freq: magic is 0x5a5ac5c5
-INFO: acpu_dvfs_set_freq: voltage:
-INFO: - 0: 0x49
-INFO: - 1: 0x49
-INFO: - 2: 0x50
-INFO: - 3: 0x60
-INFO: - 4: 0x78
-NOTICE: acpu_dvfs_set_freq: set acpu freq success!INFO: BL2: Loading image id 2
-INFO: Loading image id=2 at address 0x1000000
-INFO: Image id=2 loaded: 0x1000000 - 0x1023d00
-INFO: hisi_mcu_load_image: mcu sections 0:
-INFO: hisi_mcu_load_image: src = 0x1000200
-INFO: hisi_mcu_load_image: dst = 0xf6000000
-INFO: hisi_mcu_load_image: size = 31184
-INFO: hisi_mcu_load_image: [SRC 0x1000200] 0x8000 0x3701 0x7695 0x7689
-INFO: hisi_mcu_load_image: [DST 0xf6000000] 0x8000 0x3701 0x7695 0x7689
-INFO: hisi_mcu_load_image: mcu sections 1:
-INFO: hisi_mcu_load_image: src = 0x1007bd0
-INFO: hisi_mcu_load_image: dst = 0x5e00000
-INFO: hisi_mcu_load_image: size = 93828
-INFO: hisi_mcu_load_image: [SRC 0x1007bd0] 0xf000b510 0x2103fb3d 0xf0004604 0xf003fb57
-INFO: hisi_mcu_load_image: [DST 0x5e00000] 0xf000b510 0x2103fb3d 0xf0004604 0xf003fb57
-INFO: hisi_mcu_load_image: mcu sections 2:
-INFO: hisi_mcu_load_image: src = 0x101ea54
-INFO: hisi_mcu_load_image: dst = 0x5e16e84
-INFO: hisi_mcu_load_image: size = 15428
-INFO: hisi_mcu_load_image: [SRC 0x101ea54] 0x9 0x1020640 0x10001 0x8f0d180
-INFO: hisi_mcu_load_image: [DST 0x5e16e84] 0x9 0x1020640 0x10001 0x8f0d180
-INFO: hisi_mcu_load_image: mcu sections 3:
-INFO: hisi_mcu_load_image: src = 0x1022698
-INFO: hisi_mcu_load_image: dst = 0x5e22a10
-INFO: hisi_mcu_load_image: size = 3060
-INFO: hisi_mcu_load_image: [SRC 0x1022698] 0x0 0x0 0x0 0x0
-INFO: hisi_mcu_load_image: [DST 0x5e22a10] 0x0 0x0 0x0 0x0
-INFO: hisi_mcu_load_image: mcu sections 4:
-INFO: hisi_mcu_load_image: src = 0x102328c
-INFO: hisi_mcu_load_image: dst = 0x5e23604
-INFO: hisi_mcu_load_image: size = 2616
-INFO: hisi_mcu_load_image: [SRC 0x102328c] 0xf80000a0 0x0 0xf80000ac 0x0
-INFO: hisi_mcu_load_image: [DST 0x5e23604] 0xf80000a0 0x0 0xf80000ac 0x0
-INFO: hisi_mcu_start_run: AO_SC_SYS_CTRL2=0
-INFO: plat_hikey_bl2_handle_scp_bl2: MCU PC is at 0x42933301
-INFO: plat_hikey_bl2_handle_scp_bl2: AO_SC_PERIPH_CLKSTAT4 is 0x3b018f09
-WARNING: BL2: Platform setup already done!!
-INFO: BL2: Loading image id 3
-INFO: Loading image id=3 at address 0xf9858000
-INFO: Image id=3 loaded: 0xf9858000 - 0xf9860058
-INFO: BL2: Loading image id 5
-INFO: Loading image id=5 at address 0x35000000
-INFO: Image id=5 loaded: 0x35000000 - 0x35061cd2
-NOTICE: BL2: Booting BL31
-INFO: Entry point address = 0xf9858000
-INFO: SPSR = 0x3cd
-NOTICE: BL31: v1.5(debug):v1.5-694-g6d4f6aea
-NOTICE: BL31: Built : 09:21:44, Aug 29 2018
-WARNING: Using deprecated integer interrupt array in gicv2_driver_data_t
-WARNING: Please migrate to using an interrupt_prop_t array
-INFO: ARM GICv2 driver initialized
-INFO: BL31: Initializing runtime services
-INFO: BL31: cortex_a53: CPU workaround for disable_non_temporal_hint was applied
-INFO: BL31: cortex_a53: CPU workaround for 843419 was applied
-INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
-INFO: BL31: Preparing for EL3 exit to normal world
-INFO: Entry point address = 0x35000000
-INFO: SPSR = 0x3c9
-
-
-U-Boot 2018.09-rc1 (Aug 22 2018 - 14:55:49 +0530)hikey
-
-DRAM: 990 MiB
-HI6553 PMIC init
-MMC: config_sd_carddetect: SD card present
-Hisilicon DWMMC: 0, Hisilicon DWMMC: 1
-Loading Environment from FAT... Unable to use mmc 1:1... Failed (-5)
-In: uart@f7113000
-Out: uart@f7113000
-Err: uart@f7113000
-Net: Net Initialization Skipped
-No ethernet found.
-Hit any key to stop autoboot: 0
-starting USB...
-USB0: scanning bus 0 for devices... 2 USB Device(s) found
- scanning usb for storage devices... 0 Storage Device(s) found
- scanning usb for ethernet devices... 0 Ethernet Device(s) found
diff --git a/board/hisilicon/hikey960/MAINTAINERS b/board/hisilicon/hikey960/MAINTAINERS
index 2c98932..a442271 100644
--- a/board/hisilicon/hikey960/MAINTAINERS
+++ b/board/hisilicon/hikey960/MAINTAINERS
@@ -2,5 +2,6 @@
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
S: Maintained
F: board/hisilicon/hikey960
+F: doc/board/hisilicon/hikey960.rst
F: include/configs/hikey960.h
F: configs/hikey960_defconfig
diff --git a/board/hisilicon/hikey960/README b/board/hisilicon/hikey960/README
deleted file mode 100644
index e1e330d..0000000
--- a/board/hisilicon/hikey960/README
+++ /dev/null
@@ -1,247 +0,0 @@
-Introduction
-============
-
-HiKey960 is one of the 96Boards Consumer Edition board from HiSilicon.
-The board/SoC has: -
-* HiSilicon Kirin960 (HI3660) SoC with 4xCortex-A73 and 4xCortex-A53
-* ARM Mali G71 MP8 GPU
-* 3GB LPDDR4 SDRAM
-* 32GB UFS Flash Storage
-* microSD
-* 802.11a/b/g/n WiFi, Bluetooth
-
-More information about this board can be found in 96Boards website:
-https://www.96boards.org/product/hikey960/
-
-Currently the u-boot port supports: -
-* SD card
-
-Compile from source
-===================
-
-First get all the sources
-
- > mkdir -p ~/hikey960/src ~/hikey960/bin
- > cd ~/hikey960/src
- > git clone https://github.com/ARM-software/arm-trusted-firmware
- > git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
- > git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
- > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/config
- > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/hisi-sec_usb_xloader.img
- > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/hisi-sec_uce_boot.img
- > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/sec_xloader.img
- > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/recovery.bin
- > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/hikey_idt
-
-Get the SCP_BL2 lpm3.img binary. It is shipped as part of the UEFI source.
-The latest version can be obtained from the OpenPlatformPkg repo.
-
- > cp OpenPlatformPkg/Platforms/Hisilicon/HiKey960/Binary/lpm3.img ~/hikey960/bin/
-
-Compile U-Boot
-==============
-
- > cd ~/hikey960/src/u-boot
- > make CROSS_COMPILE=aarch64-linux-gnu- hikey960_defconfig
- > make CROSS_COMPILE=aarch64-linux-gnu-
- > cp u-boot.bin ~/hikey960/bin/
-
-Compile ARM Trusted Firmware (ATF)
-==================================
-
- > cd ~/hikey960/src/arm-trusted-firmware
- > make CROSS_COMPILE=aarch64-linux-gnu- all fip \
- SCP_BL2=~/hikey960/bin/lpm3.img \
- BL33=~/hikey960/bin/u-boot.bin DEBUG=1 PLAT=hikey960
-
-Copy the resulting FIP binary
- > cp build/hikey960/debug/fip.bin ~/hikey960/bin
-
-Compile l-loader
-================
- > cd ~/hikey960/src/l-loader
- > ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/bl1.bin
- > ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/bl2.bin
- > ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/fip.bin
- > ln -sf ~/hikey960/bin/u-boot.bin
- > make hikey960 PTABLE_LST=linux-32g NS_BL1U=u-boot.bin
-
-Copy the resulting binaries
- > cp *.img ~/hikey960/bin
- > cp l-loader.bin ~/hikey960/bin
-
-These instructions are adapted from
-https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/plat/hikey960.rst
-
-Setup Console
-=============
-
-Install ser2net. Use telnet as the console since UEFI in recovery mode
-output window fails to display in minicom.
-
- > sudo apt-get install ser2net
-
-Configure ser2net
-
- > sudo vi /etc/ser2net.conf
-
-Append one line for serial-over-USB in #ser2net.conf
-
- > 2004:telnet:0:/dev/ttyUSB0:115200 8DATABITS NONE 1STOPBIT banner
-
-Start ser2net
-
- > sudo killall ser2net
- > sudo ser2net -u
-
-Open the console.
-
- > telnet localhost 2004
-
-And you could open the console remotely, too.
-
-Flashing
-========
-
-1. Boot Hikey960 into recovery mode as per the below document:
-https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey960/installation/board-recovery.md
-
-Once Hikey960 is in recovery mode, flash the recovery binary:
-
- > cd ~/hikey960/src
- > chmod +x ./hikey_idt
- > sudo ./hikey_idt -c config -p /dev/ttyUSB1
-
-Now move to the Hikey960 console and press `f` during UEFI boot. This
-will allow the board to boot into fastboot mode. Once the board is in
-fastboot mode, you should see the ID of the HiKey960 board using the
-following command
-
- > sudo fastboot devices
-
-1ED3822A018E3372 fastboot
-
-3. Flash the images
-
-Now, the images can be flashed using fastboot:
-
- > sudo fastboot flash ptable ~/hikey960/bin/prm_ptable.img
- > sudo fastboot flash xloader ~/hikey960/bin/sec_xloader.img
- > sudo fastboot flash fastboot ~/hikey960/bin/l-loader.bin
- > sudo fastboot flash fip ~/hikey960/bin/fip.bin
-
-4. Set the "Boot Mode" switch to OFF position for normal boot mode.
-Then power on HiKey960
-
-Observe the console traces using UART6 on the Low Speed Expansion header:
-
-NOTICE: BL2: v2.1(debug):v2.1-531-g3ee48f40
-NOTICE: BL2: Built : 18:15:58, Aug 2 2019
-INFO: BL2: Doing platform setup
-INFO: UFS LUN0 contains 1024 blocks with 4096-byte size
-INFO: UFS LUN1 contains 1024 blocks with 4096-byte size
-INFO: UFS LUN2 contains 2048 blocks with 4096-byte size
-INFO: UFS LUN3 contains 7805952 blocks with 4096-byte size
-INFO: ufs: change power mode success
-INFO: BL2: Loading image id 2
-INFO: Loading image id=2 at address 0x89c80000
-INFO: Image id=2 loaded: 0x89c80000 - 0x89cb5088
-INFO: BL2: Initiating SCP_BL2 transfer to SCP
-INFO: BL2: SCP_BL2: 0x89c80000@0x35088
-INFO: BL2: SCP_BL2 HEAD:
-INFO: BL2: SCP_BL2 0x7000 0x179 0x159 0x149
-INFO: BL2: SCP_BL2 0x189 0x18b 0x18d 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x18f
-INFO: BL2: SCP_BL2 0x191 0x0 0x193 0x195
-INFO: BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
-INFO: BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
-INFO: BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
-INFO: BL2: SCP_BL2 0x4d454355 0x43494741 0x424d554e 0x21215245
-INFO: BL2: SCP_BL2 0x4a054904 0x42912000 0xf841bfbc 0xe7fa0b04
-INFO: BL2: SCP_BL2 0xb88cf000 0x3b18 0x3d1c 0x6809493e
-INFO: BL2: SCP_BL2 0x4613680a 0x201f102 0xf0002a04 0x600a804c
-INFO: BL2: SCP_BL2 0x204f04f 0xf203fb02 0xf102440a 0x60100204
-INFO: BL2: SCP_BL2 0x160f04f 0xf103fb01 0x68004834 0x61044408
-INFO: BL2: SCP_BL2 0x61866145 0xf8c061c7 0xf8c08020 0xf8c09024
-INFO: BL2: SCP_BL2 0xf8c0a028 0xf3efb02c 0xf3ef8208 0x68118309
-INFO: BL2: SCP_BL2 0xf1026401 0xf0110204 0xbf070f04 0x46113220
-INFO: BL2: SCP_BL2 TAIL:
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x19cad151 0x19b80040 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 transferred to SCP
-INFO: start fw loading
-INFO: fw load success
-WARNING: BL2: Platform setup already done!!
-INFO: BL2: Loading image id 3
-INFO: Loading image id=3 at address 0x1ac58000
-INFO: Image id=3 loaded: 0x1ac58000 - 0x1ac63024
-INFO: BL2: Loading image id 5
-INFO: Loading image id=5 at address 0x1ac98000
-INFO: Image id=5 loaded: 0x1ac98000 - 0x1ad0819c
-NOTICE: BL2: Booting BL31
-INFO: Entry point address = 0x1ac58000
-INFO: SPSR = 0x3cd
-NOTICE: BL31: v2.1(debug):v2.1-531-g3ee48f40
-NOTICE: BL31: Built : 18:16:01, Aug 2 2019
-INFO: ARM GICv2 driver initialized
-INFO: BL31: Initializing runtime services
-INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
-INFO: plat_setup_psci_ops: sec_entrypoint=0x1ac580fc
-INFO: BL31: Preparing for EL3 exit to normal world
-INFO: Entry point address = 0x1ac98000
-INFO: SPSR = 0x3c9
-
-
-U-Boot 2019.07-00628-g286f05a6fc-dirty (Aug 02 2019 - 17:14:05 +0530)
-Hikey960
-
-DRAM: 3 GiB
-PSCI: v1.1
-MMC: dwmmc1@ff37f000: 0
-Loading Environment from EXT4... ** File not found /uboot.env **
-
-** Unable to read "/uboot.env" from mmc0:2 **
-In: serial@fff32000
-Out: serial@fff32000
-Err: serial@fff32000
-Net: Net Initialization Skipped
-No ethernet found.
-Hit any key to stop autoboot: 0
-switch to partitions #0, OK
-mmc0 is current device
-Scanning mmc 0:1...
-Found /extlinux/extlinux.conf
-Retrieving file: /extlinux/extlinux.conf
-201 bytes read in 12 ms (15.6 KiB/s)
-1: hikey960-kernel
-Retrieving file: /Image
-24689152 bytes read in 4377 ms (5.4 MiB/s)
-append: earlycon=pl011,mmio32,0xfff32000 console=ttyAMA6,115200 rw root=/dev/mmcblk0p2 rot
-Retrieving file: /hi3660-hikey960.dtb
-35047 bytes read in 14 ms (2.4 MiB/s)
-## Flattened Device Tree blob at 10000000
- Booting using the fdt blob at 0x10000000
- Using Device Tree in place at 0000000010000000, end 000000001000b8e6
-
-Starting kernel ...
-
-[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
-[ 0.000000] Linux version 5.2.0-03138-gd75da80dce39 (mani@Mani-XPS-13-9360) (gcc versi9
-[ 0.000000] Machine model: HiKey960
-[ 0.000000] earlycon: pl11 at MMIO32 0x00000000fff32000 (options '')
-[ 0.000000] printk: bootconsole [pl11] enabled
-[ 0.000000] efi: Getting EFI parameters from FDT:
diff --git a/board/hisilicon/poplar/MAINTAINERS b/board/hisilicon/poplar/MAINTAINERS
index 9c045ea..bfd4a9b 100644
--- a/board/hisilicon/poplar/MAINTAINERS
+++ b/board/hisilicon/poplar/MAINTAINERS
@@ -3,5 +3,6 @@
M: Shawn Guo <shawn.guo@linaro.org>
S: Maintained
F: board/hisilicon/poplar
+F: doc/board/hisilicon/poplar.rst
F: include/configs/poplar.h
F: configs/poplar_defconfig
diff --git a/board/hisilicon/poplar/README b/board/hisilicon/poplar/README
deleted file mode 100644
index 77dcc3b..0000000
--- a/board/hisilicon/poplar/README
+++ /dev/null
@@ -1,288 +0,0 @@
-================================================================================
- Board Information
-================================================================================
-
-Developed by HiSilicon, the board features the Hi3798C V200 with an
-integrated quad-core 64-bit ARM Cortex A53 processor and high
-performance Mali T720 GPU, making it capable of running any commercial
-set-top solution based on Linux or Android. Its high performance
-specification also supports a premium user experience with up to H.265
-HEVC decoding of 4K video at 60 frames per second.
-
-SOC Hisilicon Hi3798CV200
-CPU Quad-core ARM Cortex-A53 64 bit
-DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB
-USB Two USB 2.0 ports One USB 3.0 ports
-CONSOLE USB-micro port for console support
-ETHERNET 1 GBe Ethernet
-PCIE One PCIe 2.0 interfaces
-JTAG 8-Pin JTAG
-EXPANSION INTERFACE Linaro 96Boards Low Speed Expansion slot
-DIMENSION Standard 160×120 mm 96Boards Enterprice Edition form factor
-WIFI 802.11AC 2*2 with Bluetooth
-CONNECTORS One connector for Smart Card One connector for TSI
-
-
-================================================================================
- BUILD INSTRUCTIONS
-================================================================================
-
-Note of warning:
-================
-
-U-Boot has a *strong* dependency with the l-loader and the arm trusted firmware
-repositories.
-
-The boot sequence is:
- l-loader --> arm_trusted_firmware --> u-boot
-
-U-Boot needs to be aware of the BL31 runtime location and size to avoid writing
-over it. Currently, BL31 is being placed below the kernel text offset (check
-poplar.c) but this could change in the future.
-
-The current version of u-boot has been tested with:
- - https://github.com/Linaro/poplar-l-loader.git
-
- commit f0988698dcc5c08bd0a8f50aa0457e138a5f438c
- Author: Alex Elder <elder@linaro.org>
- Date: Fri Jun 16 08:57:59 2017 -0500
-
- l-loader: use external memory region definitions
-
- The ARM Trusted Firmware code now has a header file that collects
- all the definitions for the memory regions used for its boot stages.
- Include that file where needed, and use the definitions found therein
-
- Signed-off-by: Alex Elder <elder@linaro.org>
-
-
- - https://github.com/Linaro/poplar-arm-trusted-firmware.git
-
- commit 6ac42dd3be13c99aa8ce29a15073e2f19d935f68
- Author: Alex Elder <elder@linaro.org>
- Date: Fri Jun 16 09:24:50 2017 -0500
-
- poplar: define memory regions in a separate file
-
- Separate the definitions for memory regions used for the BL stage
- images and FIP into a new file. The "l-loader" image uses knowledge
- of the sizes and locations of these memory regions, and it can now
- include this (external) header to get these definitions, rather than
- having to make coordinated changes to both code bases.
-
- The new file has a complete set of definitions (more than may be
- required by one or the other user). It also includes a summary of
- how the boot process works, and how it uses these regions.
-
- It should now be relatively easy to adjust the sizes and locations
- of these memory regions, or to add to them (e.g. for TEE).
-
- Signed-off-by: Alex Elder <elder@linaro.org>
-
-
-Compile from source:
-====================
-
-Get all the sources
-
- > mkdir -p ~/poplar/src ~/poplar/bin
- > cd ~/poplar/src
- > git clone https://github.com/Linaro/poplar-l-loader.git l-loader
- > git clone https://github.com/Linaro/poplar-arm-trusted-firmware.git atf
- > git clone https://github.com/Linaro/poplar-u-boot.git u-boot
-
-Make sure you are using the correct branch on each one of these repositories.
-The definition of "correct" might change over time (at this moment in time this
-would be the "latest" branch).
-
-Compile U-Boot:
-===============
-
- Prerequisite:
- # sudo apt-get install device-tree-compiler
-
- > cd ~/poplar/src/u-boot
- > make CROSS_COMPILE=aarch64-linux-gnu- poplar_defconfig
- > make CROSS_COMPILE=aarch64-linux-gnu-
- > cp u-boot.bin ~/poplar/bin
-
-Compile ARM Trusted Firmware (ATF):
-===================================
-
- > cd ~/poplar/src/atf
- > make CROSS_COMPILE=aarch64-linux-gnu- all fip \
- SPD=none BL33=~/poplar/bin/u-boot.bin DEBUG=1 PLAT=poplar
-
-Copy resulting binaries
- > cp build/hi3798cv200/debug/bl1.bin ~/poplar/src/l-loader/atf/
- > cp build/hi3798cv200/debug/fip.bin ~/poplar/src/l-loader/atf/
-
-Compile l-loader:
-=================
-
- > cd ~/poplar/src/l-loader
- > make clean
- > make CROSS_COMPILE=arm-linux-gnueabi-
-
- Due to BootROM requiremets, rename l-loader.bin to fastboot.bin:
- > cp l-loader.bin ~/poplar/bin/fastboot.bin
-
-
-================================================================================
- FLASH INSTRUCTIONS
-================================================================================
-
-Two methods:
-
-Using USB debrick support:
- Copy fastboot.bin to a FAT partition on the USB drive and reboot the
- poplar board while pressing S3(usb_boot).
-
- The system will execute the new u-boot and boot into a shell which you
- can then use to write to eMMC.
-
-Using U-BOOT from shell:
- 1) using AXIS usb ethernet dongle and tftp
- 2) using FAT formated USB drive
-
-
-1. TFTP (USB ethernet dongle)
-=============================
-
-Plug a USB AXIS ethernet dongle on any of the USB2 ports on the Poplar board.
-Copy fastboot.bin to your tftp server.
-In u-boot make sure your network is properly setup.
-
-Then
-
-=> tftp 0x30000000 fastboot.bin
-starting USB...
-USB0: USB EHCI 1.00
-scanning bus 0 for devices... 1 USB Device(s) found
-USB1: USB EHCI 1.00
-scanning bus 1 for devices... 3 USB Device(s) found
- scanning usb for storage devices... 0 Storage Device(s) found
- scanning usb for ethernet devices... 1 Ethernet Device(s) found
-Waiting for Ethernet connection... done.
-Using asx0 device
-TFTP from server 192.168.1.4; our IP address is 192.168.1.10
-Filename 'poplar/fastboot.bin'.
-Load address: 0x30000000
-Loading: #################################################################
- #################################################################
- ###############################################################
- 2 MiB/s
-done
-Bytes transferred = 983040 (f0000 hex)
-
-=> mmc write 0x30000000 0 0x780
-
-MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK
-=> reset
-
-
-2. USING USB FAT DRIVE
-=======================
-
-Copy fastboot.bin to any partition on a FAT32 formated usb flash drive.
-Enter the uboot prompt
-
-=> fatls usb 0:2
- 983040 fastboot.bin
-
-1 file(s), 0 dir(s)
-
-=> fatload usb 0:2 0x30000000 fastboot.bin
-reading fastboot.bin
-983040 bytes read in 44 ms (21.3 MiB/s)
-
-=> mmc write 0x30000000 0 0x780
-
-MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK
-
-
-================================================================================
- BOOT TRACE
-================================================================================
-
-Bootrom start
-Boot Media: eMMC
-Decrypt auxiliary code ...OK
-
-lsadc voltage min: 000000FE, max: 000000FF, aver: 000000FE, index: 00000000
-
-Entry boot auxiliary code
-
-Auxiliary code - v1.00
-DDR code - V1.1.2 20160205
-Build: Mar 24 2016 - 17:09:44
-Reg Version: v134
-Reg Time: 2016/03/18 09:44:55
-Reg Name: hi3798cv2dmb_hi3798cv200_ddr3_2gbyte_8bitx4_4layers.reg
-
-Boot auxiliary code success
-Bootrom success
-
-LOADER: Switched to aarch64 mode
-LOADER: Entering ARM TRUSTED FIRMWARE
-LOADER: CPU0 executes at 0x000ce000
-
-INFO: BL1: 0xe1000 - 0xe7000 [size = 24576]
-NOTICE: Booting Trusted Firmware
-NOTICE: BL1: v1.3(debug):v1.3-372-g1ba9c60
-NOTICE: BL1: Built : 17:51:33, Apr 30 2017
-INFO: BL1: RAM 0xe1000 - 0xe7000
-INFO: BL1: Loading BL2
-INFO: Loading image id=1 at address 0xe9000
-INFO: Image id=1 loaded at address 0xe9000, size = 0x5008
-NOTICE: BL1: Booting BL2
-INFO: Entry point address = 0xe9000
-INFO: SPSR = 0x3c5
-NOTICE: BL2: v1.3(debug):v1.3-372-g1ba9c60
-NOTICE: BL2: Built : 17:51:33, Apr 30 2017
-INFO: BL2: Loading BL31
-INFO: Loading image id=3 at address 0x129000
-INFO: Image id=3 loaded at address 0x129000, size = 0x8038
-INFO: BL2: Loading BL33
-INFO: Loading image id=5 at address 0x37000000
-INFO: Image id=5 loaded at address 0x37000000, size = 0x58f17
-NOTICE: BL1: Booting BL31
-INFO: Entry point address = 0x129000
-INFO: SPSR = 0x3cd
-INFO: Boot bl33 from 0x37000000 for 364311 Bytes
-NOTICE: BL31: v1.3(debug):v1.3-372-g1ba9c60
-NOTICE: BL31: Built : 17:51:33, Apr 30 2017
-INFO: BL31: Initializing runtime services
-INFO: BL31: Preparing for EL3 exit to normal world
-INFO: Entry point address = 0x37000000
-INFO: SPSR = 0x3c9
-
-
-U-Boot 2017.05-rc2-00130-gd2255b0 (Apr 30 2017 - 17:51:28 +0200)poplar
-
-Model: HiSilicon Poplar Development Board
-BOARD: Hisilicon HI3798cv200 Poplar
-DRAM: 1 GiB
-MMC: Hisilicon DWMMC: 0
-In: serial@f8b00000
-Out: serial@f8b00000
-Err: serial@f8b00000
-Net: Net Initialization Skipped
-No ethernet found.
-
-Hit any key to stop autoboot: 0
-starting USB...
-USB0: USB EHCI 1.00
-scanning bus 0 for devices... 1 USB Device(s) found
-USB1: USB EHCI 1.00
-scanning bus 1 for devices... 4 USB Device(s) found
- scanning usb for storage devices... 1 Storage Device(s) found
- scanning usb for ethernet devices... 1 Ethernet Device(s) found
-
-USB device 0:
- Device 0: Vendor: SanDisk Rev: 1.00 Prod: Cruzer Blade
- Type: Removable Hard Disk
- Capacity: 7632.0 MB = 7.4 GB (15630336 x 512)
-... is now current device
-Scanning usb 0:1...
-=>
diff --git a/board/htc/endeavoru/endeavoru.c b/board/htc/endeavoru/endeavoru.c
index 1d92870..e1a0b24 100644
--- a/board/htc/endeavoru/endeavoru.c
+++ b/board/htc/endeavoru/endeavoru.c
@@ -9,14 +9,12 @@
#include <common.h>
#include <dm.h>
-#include <env.h>
#include <fdt_support.h>
#include <i2c.h>
#include <log.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch/gpio.h>
-#include <asm/arch-tegra/fuse.h>
#include <asm/gpio.h>
#include <linux/delay.h>
#include "pinmux-config-endeavoru.h"
@@ -104,13 +102,3 @@
return 0;
}
#endif
-
-void nvidia_board_late_init(void)
-{
- char serialno_str[17];
-
- /* Set chip id as serialno */
- sprintf(serialno_str, "%016llx", tegra_chip_uid());
- env_set("serial#", serialno_str);
- env_set("platform", "Tegra 3 T30");
-}
diff --git a/board/huawei/hg556a/Makefile b/board/huawei/hg556a/Makefile
deleted file mode 100644
index 43e9be6..0000000
--- a/board/huawei/hg556a/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += hg556a.o
diff --git a/board/huawei/hg556a/hg556a.c b/board/huawei/hg556a/hg556a.c
deleted file mode 100644
index 1e4b728..0000000
--- a/board/huawei/hg556a/hg556a.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- */
-
-#include <common.h>
diff --git a/board/intel/agilex-socdk/Makefile b/board/intel/agilex-socdk/Makefile
deleted file mode 100644
index b86223a..0000000
--- a/board/intel/agilex-socdk/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (C) 2019 Intel Corporation <www.intel.com>
-#
-# SPDX-License-Identifier: GPL-2.0
-#
-
-obj-y := socfpga.o
diff --git a/board/intel/agilex-socdk/socfpga.c b/board/intel/agilex-socdk/socfpga.c
deleted file mode 100644
index 72a3e08..0000000
--- a/board/intel/agilex-socdk/socfpga.c
+++ /dev/null
@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2019 Intel Corporation <www.intel.com>
- *
- */
-
-#include <common.h>
diff --git a/board/intel/bayleybay/Makefile b/board/intel/bayleybay/Makefile
index fa263b7..8b9934f 100644
--- a/board/intel/bayleybay/Makefile
+++ b/board/intel/bayleybay/Makefile
@@ -2,5 +2,4 @@
#
# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
-obj-y += bayleybay.o
obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt_generated.o
diff --git a/board/intel/bayleybay/bayleybay.c b/board/intel/bayleybay/bayleybay.c
deleted file mode 100644
index 4f63c23..0000000
--- a/board/intel/bayleybay/bayleybay.c
+++ /dev/null
@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
- */
-
-#include <common.h>
-#include <asm/gpio.h>
diff --git a/board/intel/n5x-socdk/Makefile b/board/intel/n5x-socdk/Makefile
deleted file mode 100644
index accfdcd..0000000
--- a/board/intel/n5x-socdk/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
-#
-# SPDX-License-Identifier: GPL-2.0
-#
-
-obj-y := socfpga.o
diff --git a/board/intel/n5x-socdk/socfpga.c b/board/intel/n5x-socdk/socfpga.c
deleted file mode 100644
index 985ba19..0000000
--- a/board/intel/n5x-socdk/socfpga.c
+++ /dev/null
@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
- *
- */
-
-#include <common.h>
diff --git a/board/inteno/xg6846/Kconfig b/board/inteno/xg6846/Kconfig
new file mode 100644
index 0000000..4dd78b3
--- /dev/null
+++ b/board/inteno/xg6846/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_INTENO_XG6846
+
+config SYS_BOARD
+ default "xg6846"
+
+config SYS_VENDOR
+ default "inteno"
+
+config SYS_CONFIG_NAME
+ default "inteno_xg6846"
+
+endif
diff --git a/board/inteno/xg6846/MAINTAINERS b/board/inteno/xg6846/MAINTAINERS
new file mode 100644
index 0000000..ca41730
--- /dev/null
+++ b/board/inteno/xg6846/MAINTAINERS
@@ -0,0 +1,6 @@
+INTENO XG6846 BOARD
+M: Linus Walleij <linusw@kernel.org>
+S: Maintained
+F: board/inteno/xg6846
+F: include/configs/inteno_xg6846.h
+F: configs/inteno_xg6846_ram_defconfig
diff --git a/board/is1/Makefile b/board/is1/Makefile
deleted file mode 100644
index e499116..0000000
--- a/board/is1/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2015 Stefan Roese <sr@denx.de>
-
-obj-y := socfpga.o
diff --git a/board/is1/socfpga.c b/board/is1/socfpga.c
deleted file mode 100644
index 2a543bf..0000000
--- a/board/is1/socfpga.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/*
- * Currently nothing special is needed on this board, empty file to
- * make build scripts happy
- */
diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
index 103c453..5490243 100644
--- a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
+++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
@@ -14,6 +14,7 @@
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
+#include <asm/sections.h>
#include <asm/io.h>
#include <errno.h>
#include <spl.h>
diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig
index c6576aa..f7e9b74 100644
--- a/board/keymile/Kconfig
+++ b/board/keymile/Kconfig
@@ -125,7 +125,6 @@
config PG_WCOM_UBOOT_UPDATE_SUPPORTED
bool "Enable U-Boot Field Fail-Safe Update Functionality"
select EVENT
- default n
help
Indicates that field fail-safe u-boot update is supported.
This functionality works only for designs that are booting
@@ -133,7 +132,6 @@
config PG_WCOM_UBOOT_BOOTPACKAGE
bool "U-Boot Is Part Of Factory Boot-Package Image"
- default n
help
Indicates that u-boot will be a part of the factory programmed
boot-package image.
@@ -149,7 +147,6 @@
config PG_WCOM_UBOOT_UPDATE
bool "U-Boot Is Part Of Factory Boot-Package Image"
- default n
help
Indicates that u-boot will be a part of the embedded software and
programmed at field.
diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
index 8f2d873..acd1310 100644
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c
@@ -15,6 +15,7 @@
#include <common.h>
#include <env.h>
+#include <event.h>
#include <fdt_support.h>
#include <init.h>
#include <ioports.h>
@@ -184,7 +185,7 @@
return 0;
}
-int last_stage_init(void)
+static int last_stage_init(void)
{
#if defined(CONFIG_TARGET_KMCOGE5NE)
/*
@@ -202,6 +203,7 @@
set_km_env();
return 0;
}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
static int fixed_sdram(void)
{
diff --git a/board/keymile/kmcent2/kmcent2.c b/board/keymile/kmcent2/kmcent2.c
index ed552c5..783853d 100644
--- a/board/keymile/kmcent2/kmcent2.c
+++ b/board/keymile/kmcent2/kmcent2.c
@@ -182,7 +182,7 @@
return (gd->bus_clk / 2);
}
-static int kmcent2_misc_init_f(void *ctx, struct event *event)
+static int kmcent2_misc_init_f(void)
{
/* configure QRIO pis for i2c deblocking */
i2c_deblock_gpio_cfg();
@@ -210,7 +210,7 @@
return 0;
}
-EVENT_SPY(EVT_MISC_INIT_F, kmcent2_misc_init_f);
+EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, kmcent2_misc_init_f);
#define USED_SRDS_BANK 0
#define EXPECTED_SRDS_RFCK SRDS_PLLCR0_RFCK_SEL_100
@@ -261,7 +261,7 @@
return 0;
}
-int last_stage_init(void)
+static int last_stage_init(void)
{
const char *kmem;
/* DIP switch support on BFTIC */
@@ -287,11 +287,12 @@
return 0;
}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
void fdt_fixup_fman_mac_addresses(void *blob)
{
int node, ret;
- char path[24];
+ char path[25];
unsigned char mac_addr[6];
/*
diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
index 2f1731e..21c21aa 100644
--- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
+++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
@@ -110,14 +110,14 @@
return 0;
}
-static int pg_wcom_misc_init_f(void *ctx, struct event *event)
+static int pg_wcom_misc_init_f(void)
{
if (IS_ENABLED(CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED))
check_for_uboot_update();
return 0;
}
-EVENT_SPY(EVT_MISC_INIT_F, pg_wcom_misc_init_f);
+EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, pg_wcom_misc_init_f);
int board_init(void)
{
@@ -215,8 +215,4 @@
return 0;
}
-int last_stage_init(void)
-{
- set_km_env();
- return 0;
-}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, set_km_env);
diff --git a/board/kontron/pitx_imx8m/spl.c b/board/kontron/pitx_imx8m/spl.c
index f6fd170..a247803 100644
--- a/board/kontron/pitx_imx8m/spl.c
+++ b/board/kontron/pitx_imx8m/spl.c
@@ -16,6 +16,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/sections.h>
#include <linux/delay.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
diff --git a/board/kontron/sl-mx6ul/spl.c b/board/kontron/sl-mx6ul/spl.c
index a9d370b..b175885 100644
--- a/board/kontron/sl-mx6ul/spl.c
+++ b/board/kontron/sl-mx6ul/spl.c
@@ -11,6 +11,7 @@
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/mach-imx/iomux-v3.h>
+#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#include <init.h>
#include <linux/delay.h>
diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c
index b493734..54ee1e66 100644
--- a/board/kontron/sl-mx8mm/spl.c
+++ b/board/kontron/sl-mx8mm/spl.c
@@ -12,6 +12,7 @@
#include <asm/gpio.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
+#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
diff --git a/board/lego/ev3/legoev3.c b/board/lego/ev3/legoev3.c
index 8349260..43afe59 100644
--- a/board/lego/ev3/legoev3.c
+++ b/board/lego/ev3/legoev3.c
@@ -4,7 +4,7 @@
*
* Based on da850evm.c
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
*
* Based on da830evm.c. Original Copyrights follow:
*
diff --git a/board/lg/x3-t30/Kconfig b/board/lg/x3-t30/Kconfig
index 20ea4f5..53d7760 100644
--- a/board/lg/x3-t30/Kconfig
+++ b/board/lg/x3-t30/Kconfig
@@ -11,14 +11,12 @@
config DEVICE_P880
bool "Enable support for LG Optimus 4X HD"
- default n
help
LG Optimus 4X HD derives from x3 board but has slight
differences.
config DEVICE_P895
bool "Enable support for LG Optimus Vu"
- default n
help
LG Optimus Vu derives from x3 board but has slight
differences.
diff --git a/board/lg/x3-t30/MAINTAINERS b/board/lg/x3-t30/MAINTAINERS
index 0ad2956..13c8588 100644
--- a/board/lg/x3-t30/MAINTAINERS
+++ b/board/lg/x3-t30/MAINTAINERS
@@ -2,8 +2,6 @@
M: Svyatoslav Ryhel <clamor95@gmail.com>
S: Maintained
F: board/lg/x3-t30/
-F: configs/p880.config
-F: configs/p895.config
F: configs/x3_t30_defconfig
F: doc/board/lg/x3_t30.rst
F: include/configs/x3-t30.h
diff --git a/configs/p880.config b/board/lg/x3-t30/configs/p880.config
similarity index 100%
rename from configs/p880.config
rename to board/lg/x3-t30/configs/p880.config
diff --git a/configs/p895.config b/board/lg/x3-t30/configs/p895.config
similarity index 100%
rename from configs/p895.config
rename to board/lg/x3-t30/configs/p895.config
diff --git a/board/lg/x3-t30/x3-t30.c b/board/lg/x3-t30/x3-t30.c
index 594563c..a08e00d 100644
--- a/board/lg/x3-t30/x3-t30.c
+++ b/board/lg/x3-t30/x3-t30.c
@@ -9,7 +9,6 @@
#include <common.h>
#include <dm.h>
-#include <env.h>
#include <fdt_support.h>
#include <i2c.h>
#include <log.h>
@@ -164,13 +163,3 @@
return 0;
}
#endif
-
-void nvidia_board_late_init(void)
-{
- char serialno_str[17];
-
- /* Set chip id as serialno */
- sprintf(serialno_str, "%016llx", tegra_chip_uid());
- env_set("serial#", serialno_str);
- env_set("platform", "Tegra 3 T30");
-}
diff --git a/board/liebherr/display5/spl.c b/board/liebherr/display5/spl.c
index 4219d00..97928e9 100644
--- a/board/liebherr/display5/spl.c
+++ b/board/liebherr/display5/spl.c
@@ -25,6 +25,7 @@
#include "asm/arch/iomux.h"
#include <asm/mach-imx/iomux-v3.h>
#include <asm/gpio.h>
+#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#include <netdev.h>
#include <bootcount.h>
diff --git a/board/logicpd/am3517evm/Makefile b/board/logicpd/am3517evm/Makefile
index c07a98e9..c7da6e3 100644
--- a/board/logicpd/am3517evm/Makefile
+++ b/board/logicpd/am3517evm/Makefile
@@ -4,6 +4,6 @@
#
# Based on ti/evm/Makefile
#
-# Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
obj-y := am3517evm.o
diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c
index e787441..e69a73f 100644
--- a/board/logicpd/am3517evm/am3517evm.c
+++ b/board/logicpd/am3517evm/am3517evm.c
@@ -7,7 +7,7 @@
* Based on ti/evm/evm.c
*
* Copyright (C) 2010
- * Texas Instruments Incorporated - http://www.ti.com/
+ * Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h
index aec2b41..283b453 100644
--- a/board/logicpd/am3517evm/am3517evm.h
+++ b/board/logicpd/am3517evm/am3517evm.h
@@ -7,7 +7,7 @@
* Based on ti/evm/evm.h
*
* Copyright (C) 2010
- * Texas Instruments Incorporated - http://www.ti.com/
+ * Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef _AM3517EVM_H_
diff --git a/board/mediatek/mt7620/Makefile b/board/mediatek/mt7620/Makefile
deleted file mode 100644
index db129c5..0000000
--- a/board/mediatek/mt7620/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-
-obj-y += board.o
diff --git a/board/mediatek/mt7620/board.c b/board/mediatek/mt7620/board.c
deleted file mode 100644
index 119b8fc..0000000
--- a/board/mediatek/mt7620/board.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
- *
- * Author: Weijie Gao <weijie.gao@mediatek.com>
- */
diff --git a/board/mediatek/mt7621/Makefile b/board/mediatek/mt7621/Makefile
deleted file mode 100644
index db129c5..0000000
--- a/board/mediatek/mt7621/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-
-obj-y += board.o
diff --git a/board/mediatek/mt7621/board.c b/board/mediatek/mt7621/board.c
deleted file mode 100644
index 0496f3f..0000000
--- a/board/mediatek/mt7621/board.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2022 MediaTek Inc. All rights reserved.
- *
- * Author: Weijie Gao <weijie.gao@mediatek.com>
- */
diff --git a/board/mediatek/mt7628/Makefile b/board/mediatek/mt7628/Makefile
deleted file mode 100644
index db129c5..0000000
--- a/board/mediatek/mt7628/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-
-obj-y += board.o
diff --git a/board/mediatek/mt7628/board.c b/board/mediatek/mt7628/board.c
deleted file mode 100644
index f837a06..0000000
--- a/board/mediatek/mt7628/board.c
+++ /dev/null
@@ -1,8 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
- *
- * Author: Weijie Gao <weijie.gao@mediatek.com>
- */
-
-#include <common.h>
diff --git a/board/mediatek/mt8518/mt8518_ap1.c b/board/mediatek/mt8518/mt8518_ap1.c
index 2490b15..e03da63 100644
--- a/board/mediatek/mt8518/mt8518_ap1.c
+++ b/board/mediatek/mt8518/mt8518_ap1.c
@@ -8,6 +8,7 @@
#include <init.h>
#include <log.h>
#include <asm/global_data.h>
+#include <linux/printk.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/mntre/imx8mq_reform2/spl.c b/board/mntre/imx8mq_reform2/spl.c
index 21fad49..5120c62 100644
--- a/board/mntre/imx8mq_reform2/spl.c
+++ b/board/mntre/imx8mq_reform2/spl.c
@@ -21,6 +21,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <linux/delay.h>
diff --git a/board/mqmaker/miqi_rk3288/Makefile b/board/mqmaker/miqi_rk3288/Makefile
deleted file mode 100644
index ec95aff..0000000
--- a/board/mqmaker/miqi_rk3288/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2016 Rockchip Electronics Co., Ltd
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += miqi-rk3288.o
diff --git a/board/mqmaker/miqi_rk3288/miqi-rk3288.c b/board/mqmaker/miqi_rk3288/miqi-rk3288.c
deleted file mode 100644
index 1649bee..0000000
--- a/board/mqmaker/miqi_rk3288/miqi-rk3288.c
+++ /dev/null
@@ -1,4 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- */
diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
index f261346..d69db04 100644
--- a/board/mscc/ocelot/ocelot.c
+++ b/board/mscc/ocelot/ocelot.c
@@ -16,6 +16,7 @@
#include <wait_bit.h>
#include <miiphy.h>
#include <linux/bitops.h>
+#include <linux/printk.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/netgear/cg3100d/Makefile b/board/netgear/cg3100d/Makefile
deleted file mode 100644
index 3e05bb5..0000000
--- a/board/netgear/cg3100d/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += cg3100d.o
diff --git a/board/netgear/cg3100d/cg3100d.c b/board/netgear/cg3100d/cg3100d.c
deleted file mode 100644
index 1e4b728..0000000
--- a/board/netgear/cg3100d/cg3100d.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- */
-
-#include <common.h>
diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c
index e52e0a5..59e1a42 100644
--- a/board/nuvoton/arbel_evb/arbel_evb.c
+++ b/board/nuvoton/arbel_evb/arbel_evb.c
@@ -16,7 +16,7 @@
#define DRAM_1GB_SIZE 0x40000000ULL
#define DRAM_2GB_ECC_SIZE 0x70000000ULL
#define DRAM_2GB_SIZE 0x80000000ULL
-#define DRAM_4GB_ECC_SIZE 0xE00000000ULL
+#define DRAM_4GB_ECC_SIZE 0xE0000000ULL
#define DRAM_4GB_SIZE 0x100000000ULL
DECLARE_GLOBAL_DATA_PTR;
@@ -29,7 +29,6 @@
int dram_init(void)
{
struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
- uint64_t delta = 0ULL;
/*
* get dram active size value from bootblock.
@@ -38,17 +37,21 @@
*/
gd->ram_size = readl(&gcr->scrpad_c);
- debug("%s: scrpad_c: %llx ", __func__, gd->ram_size);
- if (gd->ram_size == 0) {
+ if (gd->ram_size == 0)
gd->ram_size = readl(&gcr->scrpad_b);
- debug("%s: scrpad_b: %llx ", __func__, gd->ram_size);
- } else {
+ else
gd->ram_size *= 0x100000ULL;
- }
+
+ debug("ram_size: %llx ", gd->ram_size);
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
gd->bd->bi_dram[0].start = 0;
- debug("ram_size: %llx ", gd->ram_size);
switch (gd->ram_size) {
case DRAM_512MB_ECC_SIZE:
@@ -62,32 +65,28 @@
gd->bd->bi_dram[1].size = 0;
break;
case DRAM_4GB_ECC_SIZE:
- gd->bd->bi_dram[0].size = DRAM_2GB_ECC_SIZE;
+ gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
- gd->bd->bi_dram[1].size = DRAM_2GB_SIZE;
- delta = DRAM_4GB_SIZE - DRAM_2GB_ECC_SIZE;
+ gd->bd->bi_dram[1].size = DRAM_2GB_SIZE -
+ (DRAM_4GB_SIZE - DRAM_4GB_ECC_SIZE);
+ /* use bank0 only */
+ gd->ram_size = DRAM_2GB_SIZE;
break;
case DRAM_4GB_SIZE:
gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
gd->bd->bi_dram[1].size = DRAM_2GB_SIZE;
- delta = DRAM_4GB_SIZE - DRAM_2GB_SIZE;
+ /* use bank0 only */
+ gd->ram_size = DRAM_2GB_SIZE;
break;
default:
gd->bd->bi_dram[0].size = DRAM_1GB_SIZE;
gd->bd->bi_dram[1].start = 0;
gd->bd->bi_dram[1].size = 0;
+ gd->ram_size = DRAM_1GB_SIZE;
break;
}
- gd->ram_size -= delta;
-
return 0;
}
-int dram_init_banksize(void)
-{
- dram_init();
-
- return 0;
-}
diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c
index d349531..7f3cdd7 100644
--- a/board/nvidia/jetson-tk1/jetson-tk1.c
+++ b/board/nvidia/jetson-tk1/jetson-tk1.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <dm.h>
#include <log.h>
+#include <linux/printk.h>
#include <power/as3722.h>
#include <power/pmic.h>
diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig
new file mode 100644
index 0000000..3b1c5aa
--- /dev/null
+++ b/board/phytec/common/Kconfig
@@ -0,0 +1,13 @@
+config PHYTEC_SOM_DETECTION
+ bool "Support SoM detection for PHYTEC platforms"
+ select SPL_CRC8 if SPL
+ help
+ Support of I2C EEPROM based SoM detection.
+
+config PHYTEC_IMX8M_SOM_DETECTION
+ bool "Support SoM detection for i.MX8M PHYTEC platforms"
+ depends on ARCH_IMX8M && PHYTEC_SOM_DETECTION
+ default y
+ help
+ Support of I2C EEPROM based SoM detection. Supported
+ for PHYTEC i.MX8MM/i.MX8MP boards
diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile
new file mode 100644
index 0000000..fe28964
--- /dev/null
+++ b/board/phytec/common/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2023 PHYTEC Messtechnik GmbH
+# Author: Teresa Remmet <t.remmet@phytec.de>
+
+ifdef CONFIG_SPL_BUILD
+# necessary to create built-in.o
+obj- := __dummy__.o
+endif
+
+obj-$(CONFIG_PHYTEC_SOM_DETECTION) += phytec_som_detection.o
+obj-$(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) += imx8m_som_detection.o
diff --git a/board/phytec/common/imx8m_som_detection.c b/board/phytec/common/imx8m_som_detection.c
new file mode 100644
index 0000000..c6c96ed
--- /dev/null
+++ b/board/phytec/common/imx8m_som_detection.c
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2023 PHYTEC Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <i2c.h>
+#include <u-boot/crc.h>
+
+#include "imx8m_som_detection.h"
+
+extern struct phytec_eeprom_data eeprom_data;
+
+/* Check if the SoM is actually one of the following products:
+ * - i.MX8MM
+ * - i.MX8MN
+ * - i.MX8MP
+ * - i.MX8MQ
+ *
+ * Returns 0 in case it's a known SoM. Otherwise, returns -1.
+ */
+u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data)
+{
+ char *opt;
+ u8 som;
+
+ /* We can not do the check for early API revisions */
+ if (data->api_rev < PHYTEC_API_REV2)
+ return -1;
+
+ if (!data)
+ data = &eeprom_data;
+
+ som = data->data.data_api2.som_no;
+ debug("%s: som id: %u\n", __func__, som);
+
+ opt = phytec_get_opt(data);
+ if (!opt)
+ return -1;
+
+ if (som == PHYTEC_IMX8MP_SOM && is_imx8mp())
+ return 0;
+
+ if (som == PHYTEC_IMX8MM_SOM) {
+ if ((PHYTEC_GET_OPTION(opt[0]) != 0) &&
+ (PHYTEC_GET_OPTION(opt[1]) == 0) && is_imx8mm())
+ return 0;
+ else if ((PHYTEC_GET_OPTION(opt[0]) == 0) &&
+ (PHYTEC_GET_OPTION(opt[1]) != 0) && is_imx8mn())
+ return 0;
+ }
+
+ if (som == PHYTEC_IMX8MQ_SOM && is_imx8mq())
+ return 0;
+
+ pr_err("%s: SoM ID does not match. Wrong EEPROM data?\n", __func__);
+ return -1;
+}
+
+/*
+ * All PHYTEC i.MX8M boards have RAM size definition at the
+ * same location.
+ */
+u8 __maybe_unused phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data)
+{
+ char *opt;
+ u8 ddr_id;
+
+ if (!data)
+ data = &eeprom_data;
+
+ opt = phytec_get_opt(data);
+ if (opt)
+ ddr_id = PHYTEC_GET_OPTION(opt[2]);
+ else
+ ddr_id = PHYTEC_EEPROM_INVAL;
+
+ debug("%s: ddr id: %u\n", __func__, ddr_id);
+ return ddr_id;
+}
+
+/*
+ * Filter SPI-NOR flash information. All i.MX8M boards have this at
+ * the same location.
+ * returns: 0x0 if no SPI is populated. Otherwise a board depended
+ * code for the size. PHYTEC_EEPROM_INVAL when the data is invalid.
+ */
+u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data)
+{
+ char *opt;
+ u8 spi;
+
+ if (!data)
+ data = &eeprom_data;
+
+ if (data->api_rev < PHYTEC_API_REV2)
+ return PHYTEC_EEPROM_INVAL;
+
+ opt = phytec_get_opt(data);
+ if (opt)
+ spi = PHYTEC_GET_OPTION(opt[4]);
+ else
+ spi = PHYTEC_EEPROM_INVAL;
+
+ debug("%s: spi: %u\n", __func__, spi);
+ return spi;
+}
+
+/*
+ * Filter ethernet phy information. All i.MX8M boards have this at
+ * the same location.
+ * returns: 0x0 if no ethernet phy is populated. 0x1 if it is populated.
+ * PHYTEC_EEPROM_INVAL when the data is invalid.
+ */
+u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data)
+{
+ char *opt;
+ u8 eth;
+
+ if (!data)
+ data = &eeprom_data;
+
+ if (data->api_rev < PHYTEC_API_REV2)
+ return PHYTEC_EEPROM_INVAL;
+
+ opt = phytec_get_opt(data);
+ if (opt) {
+ eth = PHYTEC_GET_OPTION(opt[5]);
+ eth &= 0x1;
+ } else {
+ eth = PHYTEC_EEPROM_INVAL;
+ }
+
+ debug("%s: eth: %u\n", __func__, eth);
+ return eth;
+}
+
+/*
+ * Filter RTC information for phyCORE-i.MX8MP.
+ * returns: 0 if no RTC is populated. 1 if it is populated.
+ * PHYTEC_EEPROM_INVAL when the data is invalid.
+ */
+u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data)
+{
+ char *opt;
+ u8 rtc;
+
+ if (!data)
+ data = &eeprom_data;
+
+ if (data->api_rev < PHYTEC_API_REV2)
+ return PHYTEC_EEPROM_INVAL;
+
+ opt = phytec_get_opt(data);
+ if (opt) {
+ rtc = PHYTEC_GET_OPTION(opt[5]);
+ rtc &= 0x4;
+ rtc = !(rtc >> 2);
+ } else {
+ rtc = PHYTEC_EEPROM_INVAL;
+ }
+ debug("%s: rtc: %u\n", __func__, rtc);
+ return rtc;
+}
diff --git a/board/phytec/common/imx8m_som_detection.h b/board/phytec/common/imx8m_som_detection.h
new file mode 100644
index 0000000..88d3037
--- /dev/null
+++ b/board/phytec/common/imx8m_som_detection.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2023 PHYTEC Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ */
+
+#ifndef _PHYTEC_IMX8M_SOM_DETECTION_H
+#define _PHYTEC_IMX8M_SOM_DETECTION_H
+
+#include "phytec_som_detection.h"
+
+#define PHYTEC_IMX8MQ_SOM 66
+#define PHYTEC_IMX8MM_SOM 69
+#define PHYTEC_IMX8MP_SOM 70
+
+#if IS_ENABLED(CONFIG_PHYTEC_IMX8M_SOM_DETECTION)
+
+u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data);
+u8 __maybe_unused phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data);
+u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data);
+u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data);
+u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data);
+
+#else
+
+inline u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data)
+{
+ return -1;
+}
+
+inline u8 __maybe_unused
+phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data)
+{
+ return PHYTEC_EEPROM_INVAL;
+}
+
+inline u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data)
+{
+ return PHYTEC_EEPROM_INVAL;
+}
+
+inline u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data)
+{
+ return PHYTEC_EEPROM_INVAL;
+}
+
+inline u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data)
+{
+ return PHYTEC_EEPROM_INVAL;
+}
+
+#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) */
+
+#endif /* _PHYTEC_IMX8M_SOM_DETECTION_H */
diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c
new file mode 100644
index 0000000..5556273
--- /dev/null
+++ b/board/phytec/common/phytec_som_detection.c
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2023 PHYTEC Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ */
+
+#include <common.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/sys_proto.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <i2c.h>
+#include <u-boot/crc.h>
+
+#include "phytec_som_detection.h"
+
+struct phytec_eeprom_data eeprom_data;
+
+int phytec_eeprom_data_setup_fallback(struct phytec_eeprom_data *data,
+ int bus_num, int addr, int addr_fallback)
+{
+ int ret;
+
+ ret = phytec_eeprom_data_init(data, bus_num, addr);
+ if (ret) {
+ pr_err("%s: init failed. Trying fall back address 0x%x\n",
+ __func__, addr_fallback);
+ ret = phytec_eeprom_data_init(data, bus_num, addr_fallback);
+ }
+
+ if (ret)
+ pr_err("%s: EEPROM data init failed\n", __func__);
+
+ return ret;
+}
+
+int phytec_eeprom_data_setup(struct phytec_eeprom_data *data,
+ int bus_num, int addr)
+{
+ int ret;
+
+ ret = phytec_eeprom_data_init(data, bus_num, addr);
+ if (ret)
+ pr_err("%s: EEPROM data init failed\n", __func__);
+
+ return ret;
+}
+
+int phytec_eeprom_data_init(struct phytec_eeprom_data *data,
+ int bus_num, int addr)
+{
+ int ret, i;
+ unsigned int crc;
+ int *ptr;
+
+ if (!data)
+ data = &eeprom_data;
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(bus_num, addr, 2, &dev);
+ if (ret) {
+ pr_err("%s: i2c EEPROM not found: %i.\n", __func__, ret);
+ return ret;
+ }
+
+ ret = dm_i2c_read(dev, 0, (uint8_t *)data,
+ sizeof(struct phytec_eeprom_data));
+ if (ret) {
+ pr_err("%s: Unable to read EEPROM data\n", __func__);
+ return ret;
+ }
+#else
+ i2c_set_bus_num(bus_num);
+ ret = i2c_read(addr, 0, 2, (uint8_t *)data,
+ sizeof(struct phytec_eeprom_data));
+#endif
+
+ if (data->api_rev == 0xff) {
+ pr_err("%s: EEPROM is not flashed. Prototype?\n", __func__);
+ return -EINVAL;
+ }
+
+ ptr = (int *)data;
+ for (i = 0; i < sizeof(struct phytec_eeprom_data); i += sizeof(ptr))
+ if (*ptr != 0x0)
+ break;
+
+ if (i == sizeof(struct phytec_eeprom_data)) {
+ pr_err("%s: EEPROM data is all zero. Erased?\n", __func__);
+ return -EINVAL;
+ }
+
+ /* We are done here for early revisions */
+ if (data->api_rev <= PHYTEC_API_REV1)
+ return 0;
+
+ crc = crc8(0, (const unsigned char *)data,
+ sizeof(struct phytec_eeprom_data));
+ debug("%s: crc: %x\n", __func__, crc);
+
+ if (crc) {
+ pr_err("%s: CRC mismatch. EEPROM data is not usable\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data)
+{
+ struct phytec_api2_data *api2;
+ char pcb_sub_rev;
+ unsigned int ksp_no, sub_som_type1, sub_som_type2;
+
+ if (!data)
+ data = &eeprom_data;
+
+ if (data->api_rev < PHYTEC_API_REV2)
+ return;
+
+ api2 = &data->data.data_api2;
+
+ /* Calculate PCB subrevision */
+ pcb_sub_rev = api2->pcb_sub_opt_rev & 0x0f;
+ pcb_sub_rev = pcb_sub_rev ? ((pcb_sub_rev - 1) + 'a') : ' ';
+
+ /* print standard product string */
+ if (api2->som_type <= 1) {
+ printf("SoM: %s-%03u-%s.%s PCB rev: %u%c\n",
+ phytec_som_type_str[api2->som_type], api2->som_no,
+ api2->opt, api2->bom_rev, api2->pcb_rev, pcb_sub_rev);
+ return;
+ }
+ /* print KSP/KSM string */
+ if (api2->som_type <= 3) {
+ ksp_no = (api2->ksp_no << 8) | api2->som_no;
+ printf("SoM: %s-%u ",
+ phytec_som_type_str[api2->som_type], ksp_no);
+ /* print standard product based KSP/KSM strings */
+ } else {
+ switch (api2->som_type) {
+ case 4:
+ sub_som_type1 = 0;
+ sub_som_type2 = 3;
+ break;
+ case 5:
+ sub_som_type1 = 0;
+ sub_som_type2 = 2;
+ break;
+ case 6:
+ sub_som_type1 = 1;
+ sub_som_type2 = 3;
+ break;
+ case 7:
+ sub_som_type1 = 1;
+ sub_som_type2 = 2;
+ break;
+ default:
+ break;
+ };
+
+ printf("SoM: %s-%03u-%s-%03u ",
+ phytec_som_type_str[sub_som_type1],
+ api2->som_no, phytec_som_type_str[sub_som_type2],
+ api2->ksp_no);
+ }
+
+ printf("Option: %s BOM rev: %s PCB rev: %u%c\n", api2->opt,
+ api2->bom_rev, api2->pcb_rev, pcb_sub_rev);
+}
+
+char * __maybe_unused phytec_get_opt(struct phytec_eeprom_data *data)
+{
+ char *opt;
+
+ if (!data)
+ data = &eeprom_data;
+
+ if (data->api_rev < PHYTEC_API_REV2)
+ opt = data->data.data_api0.opt;
+ else
+ opt = data->data.data_api2.opt;
+
+ return opt;
+}
+
+u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data)
+{
+ struct phytec_api2_data *api2;
+
+ if (!data)
+ data = &eeprom_data;
+
+ if (data->api_rev < PHYTEC_API_REV2)
+ return PHYTEC_EEPROM_INVAL;
+
+ api2 = &data->data.data_api2;
+
+ return api2->pcb_rev;
+}
diff --git a/board/phytec/common/phytec_som_detection.h b/board/phytec/common/phytec_som_detection.h
new file mode 100644
index 0000000..c68e230
--- /dev/null
+++ b/board/phytec/common/phytec_som_detection.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2023 PHYTEC Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ */
+
+#ifndef _PHYTEC_SOM_DETECTION_H
+#define _PHYTEC_SOM_DETECTION_H
+
+#define PHYTEC_MAX_OPTIONS 17
+#define PHYTEC_EEPROM_INVAL 0xff
+
+#define PHYTEC_GET_OPTION(option) \
+ (((option) > '9') ? (option) - 'A' + 10 : (option) - '0')
+
+enum {
+ PHYTEC_API_REV0 = 0,
+ PHYTEC_API_REV1,
+ PHYTEC_API_REV2,
+};
+
+static const char * const phytec_som_type_str[] = {
+ "PCM",
+ "PCL",
+ "KSM",
+ "KSP",
+};
+
+struct phytec_api0_data {
+ u8 pcb_rev; /* PCB revision of SoM */
+ u8 som_type; /* SoM type */
+ u8 ksp_no; /* KSP no */
+ char opt[16]; /* SoM options */
+ u8 mac[6]; /* MAC address (optional) */
+ u8 pad[5]; /* padding */
+ u8 cksum; /* checksum */
+} __packed;
+
+struct phytec_api2_data {
+ u8 pcb_rev; /* PCB revision of SoM */
+ u8 pcb_sub_opt_rev; /* PCB subrevision and opt revision */
+ u8 som_type; /* SoM type */
+ u8 som_no; /* SoM number */
+ u8 ksp_no; /* KSP information */
+ char opt[PHYTEC_MAX_OPTIONS]; /* SoM options */
+ char bom_rev[2]; /* BOM revision */
+ u8 mac[6]; /* MAC address (optional) */
+ u8 crc8; /* checksum */
+} __packed;
+
+struct phytec_eeprom_data {
+ u8 api_rev;
+ union {
+ struct phytec_api0_data data_api0;
+ struct phytec_api2_data data_api2;
+ } data;
+} __packed;
+
+#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION)
+
+int phytec_eeprom_data_setup_fallback(struct phytec_eeprom_data *data,
+ int bus_num, int addr,
+ int addr_fallback);
+int phytec_eeprom_data_setup(struct phytec_eeprom_data *data,
+ int bus_num, int addr);
+int phytec_eeprom_data_init(struct phytec_eeprom_data *data,
+ int bus_num, int addr);
+void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data);
+
+char * __maybe_unused phytec_get_opt(struct phytec_eeprom_data *data);
+u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data);
+
+#else
+
+inline int phytec_eeprom_data_setup(struct phytec_eeprom_data *data,
+ int bus_num, int addr)
+{
+ return PHYTEC_EEPROM_INVAL;
+}
+
+inline int phytec_eeprom_data_setup_fallback(struct phytec_eeprom_data *data,
+ int bus_num, int addr,
+ int addr_fallback)
+{
+ return PHYTEC_EEPROM_INVAL;
+}
+
+inline int phytec_eeprom_data_init(struct phytec_eeprom_data *data,
+ int bus_num, int addr)
+{
+ return PHYTEC_EEPROM_INVAL;
+}
+
+inline void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data)
+{
+}
+
+inline char *__maybe_unused phytec_get_opt(struct phytec_eeprom_data *data)
+{
+ return NULL;
+}
+
+u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data)
+{
+ return PHYTEC_EEPROM_INVAL;
+}
+#endif /* IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) */
+
+#endif /* _PHYTEC_SOM_DETECTION_H */
diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c
index 5e5b129..b37c6fe 100644
--- a/board/phytec/pcm058/pcm058.c
+++ b/board/phytec/pcm058/pcm058.c
@@ -17,6 +17,7 @@
#include <asm/global_data.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/sys_proto.h>
+#include <asm/sections.h>
#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/phytec/phycore_am335x_r2/Makefile b/board/phytec/phycore_am335x_r2/Makefile
index ff6f8b4..16ac38f 100644
--- a/board/phytec/phycore_am335x_r2/Makefile
+++ b/board/phytec/phycore_am335x_r2/Makefile
@@ -2,7 +2,7 @@
#
# Makefile
#
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
ifdef CONFIG_SPL_BUILD
obj-y += mux.o
diff --git a/board/phytec/phycore_am335x_r2/board.c b/board/phytec/phycore_am335x_r2/board.c
index eb573d0..5700eff 100644
--- a/board/phytec/phycore_am335x_r2/board.c
+++ b/board/phytec/phycore_am335x_r2/board.c
@@ -4,7 +4,7 @@
*
* Board functions for Phytec phyCORE-AM335x R2 (PCL060 / PCM060) based boards
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
* Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
* Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
* Copyright (C) 2019 DENX Software Engineering GmbH
diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c
index 1bae9b1..690a51f 100644
--- a/board/phytec/phycore_imx8mm/spl.c
+++ b/board/phytec/phycore_imx8mm/spl.c
@@ -12,6 +12,7 @@
#include <asm/global_data.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
+#include <asm/sections.h>
#include <hang.h>
#include <init.h>
#include <log.h>
diff --git a/board/phytec/phycore_imx8mp/Kconfig b/board/phytec/phycore_imx8mp/Kconfig
index c053a46..f846d10 100644
--- a/board/phytec/phycore_imx8mp/Kconfig
+++ b/board/phytec/phycore_imx8mp/Kconfig
@@ -12,4 +12,5 @@
config IMX_CONFIG
default "board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg"
+source "board/phytec/common/Kconfig"
endif
diff --git a/board/phytec/phycore_imx8mp/lpddr4_timing.c b/board/phytec/phycore_imx8mp/lpddr4_timing.c
index e59dd74..f2707b8 100644
--- a/board/phytec/phycore_imx8mp/lpddr4_timing.c
+++ b/board/phytec/phycore_imx8mp/lpddr4_timing.c
@@ -13,63 +13,68 @@
{ 0x3d400304, 0x1 },
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa1080020 },
- { 0x3d400020, 0x323 },
- { 0x3d400024, 0x1e84800 },
- { 0x3d400064, 0x7a0118 },
- { 0x3d4000d0, 0xc00307a3 },
- { 0x3d4000d4, 0xc50000 },
- { 0x3d4000dc, 0xf4003f },
- { 0x3d4000e0, 0x330000 },
+ { 0x3d400020, 0x1223 },
+ { 0x3d400024, 0x16e3600 },
+ { 0x3d400064, 0x5b00d2 },
+ { 0x3d400070, 0x7027f90 },
+ { 0x3d400074, 0x790 },
+ { 0x3d4000d0, 0xc00305ba },
+ { 0x3d4000d4, 0x940000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0xf10000 },
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
- { 0x3d400100, 0x2028222a },
- { 0x3d400104, 0x807bf },
- { 0x3d40010c, 0xe0e000 },
- { 0x3d400110, 0x12040a12 },
- { 0x3d400114, 0x2050f0f },
- { 0x3d400118, 0x1010009 },
- { 0x3d40011c, 0x501 },
- { 0x3d400130, 0x20800 },
- { 0x3d400134, 0xe100002 },
- { 0x3d400138, 0x120 },
- { 0x3d400144, 0xc80064 },
- { 0x3d400180, 0x3e8001e },
- { 0x3d400184, 0x3207a12 },
+ { 0x3d400100, 0x191e1920 },
+ { 0x3d400104, 0x60630 },
+ { 0x3d40010c, 0xb0b000 },
+ { 0x3d400110, 0xe04080e },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xc100002 },
+ { 0x3d400138, 0xd8 },
+ { 0x3d400144, 0x96004b },
+ { 0x3d400180, 0x2ee0017 },
+ { 0x3d400184, 0x2605b8e },
{ 0x3d400188, 0x0 },
- { 0x3d400190, 0x49f820e },
+ { 0x3d400190, 0x49b820a },
{ 0x3d400194, 0x80303 },
- { 0x3d4001b4, 0x1f0e },
+ { 0x3d4001b4, 0x1b0a },
{ 0x3d4001a0, 0xe0400018 },
{ 0x3d4001a4, 0xdf00e4 },
{ 0x3d4001a8, 0x80000000 },
{ 0x3d4001b0, 0x11 },
- { 0x3d4001c0, 0x1 },
+ { 0x3d4001c0, 0x7 },
{ 0x3d4001c4, 0x1 },
{ 0x3d4000f4, 0xc99 },
- { 0x3d400108, 0x9121c1c },
+ { 0x3d400108, 0x7101817 },
{ 0x3d400200, 0x1f },
+ { 0x3d400208, 0x0 },
{ 0x3d40020c, 0x0 },
{ 0x3d400210, 0x1f1f },
{ 0x3d400204, 0x80808 },
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0x7070707 },
- { 0x3d40021c, 0xf07 },
- { 0x3d400250, 0x1f05 },
- { 0x3d400254, 0x1f },
- { 0x3d400264, 0x90003ff },
- { 0x3d40026c, 0x20003ff },
+ { 0x3d40021c, 0xf0f },
+ { 0x3d400250, 0x1705 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
{ 0x3d400400, 0x111 },
+ { 0x3d400404, 0x72ff },
{ 0x3d400408, 0x72ff },
- { 0x3d400494, 0x1000e00 },
- { 0x3d400498, 0x3ff0000 },
- { 0x3d40049c, 0x1000e00 },
- { 0x3d4004a0, 0x3ff0000 },
- { 0x3d402020, 0x21 },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x1021 },
{ 0x3d402024, 0x30d400 },
- { 0x3d402050, 0x20d040 },
+ { 0x3d402050, 0x20d000 },
{ 0x3d402064, 0xc001c },
{ 0x3d4020dc, 0x840000 },
- { 0x3d4020e0, 0x330000 },
+ { 0x3d4020e0, 0xf30000 },
{ 0x3d4020e8, 0x660048 },
{ 0x3d4020ec, 0x160048 },
{ 0x3d402100, 0xa040305 },
@@ -89,12 +94,12 @@
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
{ 0x3d4020f4, 0xc99 },
- { 0x3d403020, 0x21 },
+ { 0x3d403020, 0x1021 },
{ 0x3d403024, 0xc3500 },
- { 0x3d403050, 0x20d040 },
+ { 0x3d403050, 0x20d000 },
{ 0x3d403064, 0x30007 },
{ 0x3d4030dc, 0x840000 },
- { 0x3d4030e0, 0x330000 },
+ { 0x3d4030e0, 0xf30000 },
{ 0x3d4030e8, 0x660048 },
{ 0x3d4030ec, 0x160048 },
{ 0x3d403100, 0xa010102 },
@@ -137,12 +142,12 @@
{ 0x110a7, 0x6 },
{ 0x120a0, 0x0 },
{ 0x120a1, 0x1 },
- { 0x120a2, 0x3 },
- { 0x120a3, 0x2 },
- { 0x120a4, 0x5 },
- { 0x120a5, 0x4 },
- { 0x120a6, 0x7 },
- { 0x120a7, 0x6 },
+ { 0x120a2, 0x2 },
+ { 0x120a3, 0x3 },
+ { 0x120a4, 0x4 },
+ { 0x120a5, 0x5 },
+ { 0x120a6, 0x6 },
+ { 0x120a7, 0x7 },
{ 0x130a0, 0x0 },
{ 0x130a1, 0x1 },
{ 0x130a2, 0x2 },
@@ -185,7 +190,7 @@
{ 0x7055, 0x1ff },
{ 0x8055, 0x1ff },
{ 0x9055, 0x1ff },
- { 0x200c5, 0x18 },
+ { 0x200c5, 0x19 },
{ 0x1200c5, 0x7 },
{ 0x2200c5, 0x7 },
{ 0x2002e, 0x2 },
@@ -194,11 +199,11 @@
{ 0x90204, 0x0 },
{ 0x190204, 0x0 },
{ 0x290204, 0x0 },
- { 0x20024, 0x1e3 },
+ { 0x20024, 0x1a3 },
{ 0x2003a, 0x2 },
- { 0x120024, 0x1e3 },
+ { 0x120024, 0x1a3 },
{ 0x2003a, 0x2 },
- { 0x220024, 0x1e3 },
+ { 0x220024, 0x1a3 },
{ 0x2003a, 0x2 },
{ 0x20056, 0x3 },
{ 0x120056, 0x3 },
@@ -264,7 +269,7 @@
{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
- { 0x20008, 0x3e8 },
+ { 0x20008, 0x2ee },
{ 0x120008, 0x64 },
{ 0x220008, 0x19 },
{ 0x20088, 0x9 },
@@ -310,19 +315,15 @@
{ 0x200f6, 0x0 },
{ 0x200f7, 0xf000 },
{ 0x20025, 0x0 },
- { 0x2002d, 0x0 },
- { 0x12002d, 0x0 },
- { 0x22002d, 0x0 },
+ { 0x2002d, 0x1 },
+ { 0x12002d, 0x1 },
+ { 0x22002d, 0x1 },
{ 0x2007d, 0x212 },
{ 0x12007d, 0x212 },
{ 0x22007d, 0x212 },
{ 0x2007c, 0x61 },
{ 0x12007c, 0x61 },
{ 0x22007c, 0x61 },
- { 0x1004a, 0x500 },
- { 0x1104a, 0x500 },
- { 0x1204a, 0x500 },
- { 0x1304a, 0x500 },
{ 0x2002c, 0x0 },
};
@@ -1052,7 +1053,7 @@
/* P0 message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xfa0 },
+ { 0x54003, 0xbb8 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
@@ -1061,26 +1062,26 @@
{ 0x5400b, 0x2 },
{ 0x5400f, 0x100 },
{ 0x54012, 0x110 },
- { 0x54019, 0x3ff4 },
- { 0x5401a, 0x33 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0xf1 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
- { 0x5401f, 0x3ff4 },
- { 0x54020, 0x33 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0xf1 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
- { 0x54032, 0xf400 },
- { 0x54033, 0x333f },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0xf12d },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
- { 0x54038, 0xf400 },
- { 0x54039, 0x333f },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0xf12d },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1102,25 +1103,25 @@
{ 0x5400f, 0x100 },
{ 0x54012, 0x110 },
{ 0x54019, 0x84 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
{ 0x54032, 0x8400 },
- { 0x54033, 0x3300 },
+ { 0x54033, 0xf300 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
- { 0x54039, 0x3300 },
+ { 0x54039, 0xf300 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1142,25 +1143,25 @@
{ 0x5400f, 0x100 },
{ 0x54012, 0x110 },
{ 0x54019, 0x84 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
{ 0x54032, 0x8400 },
- { 0x54033, 0x3300 },
+ { 0x54033, 0xf300 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
- { 0x54039, 0x3300 },
+ { 0x54039, 0xf300 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1171,37 +1172,36 @@
/* P0 2D message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xfa0 },
+ { 0x54003, 0xbb8 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
{ 0x54008, 0x61 },
{ 0x54009, 0xc8 },
{ 0x5400b, 0x2 },
- { 0x5400d, 0x100 },
{ 0x5400f, 0x100 },
{ 0x54010, 0x1f7f },
{ 0x54012, 0x110 },
- { 0x54019, 0x3ff4 },
- { 0x5401a, 0x33 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0xf1 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
- { 0x5401f, 0x3ff4 },
- { 0x54020, 0x33 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0xf1 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
- { 0x54032, 0xf400 },
- { 0x54033, 0x333f },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0xf12d },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
- { 0x54038, 0xf400 },
- { 0x54039, 0x333f },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0xf12d },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1629,67 +1629,58 @@
{ 0x90155, 0x20 },
{ 0x90156, 0x2aa },
{ 0x90157, 0x9 },
- { 0x90158, 0x0 },
- { 0x90159, 0x400 },
- { 0x9015a, 0x10e },
- { 0x9015b, 0x8 },
- { 0x9015c, 0xe8 },
- { 0x9015d, 0x109 },
- { 0x9015e, 0x0 },
- { 0x9015f, 0x8140 },
- { 0x90160, 0x10c },
- { 0x90161, 0x10 },
- { 0x90162, 0x8138 },
- { 0x90163, 0x10c },
- { 0x90164, 0x8 },
- { 0x90165, 0x7c8 },
- { 0x90166, 0x101 },
- { 0x90167, 0x8 },
- { 0x90168, 0x448 },
+ { 0x90158, 0x8 },
+ { 0x90159, 0xe8 },
+ { 0x9015a, 0x109 },
+ { 0x9015b, 0x0 },
+ { 0x9015c, 0x8140 },
+ { 0x9015d, 0x10c },
+ { 0x9015e, 0x10 },
+ { 0x9015f, 0x8138 },
+ { 0x90160, 0x104 },
+ { 0x90161, 0x8 },
+ { 0x90162, 0x448 },
+ { 0x90163, 0x109 },
+ { 0x90164, 0xf },
+ { 0x90165, 0x7c0 },
+ { 0x90166, 0x109 },
+ { 0x90167, 0x0 },
+ { 0x90168, 0xe8 },
{ 0x90169, 0x109 },
- { 0x9016a, 0xf },
- { 0x9016b, 0x7c0 },
+ { 0x9016a, 0x47 },
+ { 0x9016b, 0x630 },
{ 0x9016c, 0x109 },
- { 0x9016d, 0x0 },
- { 0x9016e, 0xe8 },
+ { 0x9016d, 0x8 },
+ { 0x9016e, 0x618 },
{ 0x9016f, 0x109 },
- { 0x90170, 0x47 },
- { 0x90171, 0x630 },
+ { 0x90170, 0x8 },
+ { 0x90171, 0xe0 },
{ 0x90172, 0x109 },
- { 0x90173, 0x8 },
- { 0x90174, 0x618 },
+ { 0x90173, 0x0 },
+ { 0x90174, 0x7c8 },
{ 0x90175, 0x109 },
{ 0x90176, 0x8 },
- { 0x90177, 0xe0 },
- { 0x90178, 0x109 },
+ { 0x90177, 0x8140 },
+ { 0x90178, 0x10c },
{ 0x90179, 0x0 },
- { 0x9017a, 0x7c8 },
+ { 0x9017a, 0x478 },
{ 0x9017b, 0x109 },
- { 0x9017c, 0x8 },
- { 0x9017d, 0x8140 },
- { 0x9017e, 0x10c },
- { 0x9017f, 0x0 },
- { 0x90180, 0x478 },
- { 0x90181, 0x109 },
- { 0x90182, 0x0 },
- { 0x90183, 0x1 },
- { 0x90184, 0x8 },
- { 0x90185, 0x8 },
- { 0x90186, 0x4 },
- { 0x90187, 0x8 },
- { 0x90188, 0x8 },
- { 0x90189, 0x7c8 },
- { 0x9018a, 0x101 },
- { 0x90006, 0x0 },
- { 0x90007, 0x0 },
- { 0x90008, 0x8 },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x1 },
+ { 0x9017e, 0x8 },
+ { 0x9017f, 0x8 },
+ { 0x90180, 0x4 },
+ { 0x90181, 0x0 },
+ { 0x90006, 0x8 },
+ { 0x90007, 0x7c8 },
+ { 0x90008, 0x109 },
{ 0x90009, 0x0 },
- { 0x9000a, 0x0 },
- { 0x9000b, 0x0 },
+ { 0x9000a, 0x400 },
+ { 0x9000b, 0x106 },
{ 0xd00e7, 0x400 },
{ 0x90017, 0x0 },
{ 0x9001f, 0x29 },
- { 0x90026, 0x6a },
+ { 0x90026, 0x68 },
{ 0x400d0, 0x0 },
{ 0x400d1, 0x101 },
{ 0x400d2, 0x105 },
@@ -1699,15 +1690,16 @@
{ 0x400d6, 0x20a },
{ 0x400d7, 0x20b },
{ 0x2003a, 0x2 },
- { 0x2000b, 0x7d },
- { 0x2000c, 0xfa },
- { 0x2000d, 0x9c4 },
+ { 0x200be, 0x3 },
+ { 0x2000b, 0x34b },
+ { 0x2000c, 0xbb },
+ { 0x2000d, 0x753 },
{ 0x2000e, 0x2c },
- { 0x12000b, 0xc },
+ { 0x12000b, 0x70 },
{ 0x12000c, 0x19 },
{ 0x12000d, 0xfa },
{ 0x12000e, 0x10 },
- { 0x22000b, 0x3 },
+ { 0x22000b, 0x1c },
{ 0x22000c, 0x6 },
{ 0x22000d, 0x3e },
{ 0x22000e, 0x10 },
@@ -1804,8 +1796,8 @@
static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
{
- /* P0 4000mts 1D */
- .drate = 4000,
+ /* P0 3000mts 1D */
+ .drate = 3000,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
@@ -1825,8 +1817,8 @@
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
},
{
- /* P0 4000mts 2D */
- .drate = 4000,
+ /* P0 3000mts 2D */
+ .drate = 3000,
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
@@ -1845,5 +1837,5 @@
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 4000, 400, 100, },
+ .fsp_table = { 3000, 400, 100, },
};
diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c
index faed6fc..d38f636 100644
--- a/board/phytec/phycore_imx8mp/spl.c
+++ b/board/phytec/phycore_imx8mp/spl.c
@@ -21,8 +21,13 @@
#include <power/pca9450.h>
#include <spl.h>
+#include "../common/imx8m_som_detection.h"
+
DECLARE_GLOBAL_DATA_PTR;
+#define EEPROM_ADDR 0x51
+#define EEPROM_ADDR_FALLBACK 0x59
+
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
return BOOT_DEVICE_BOOTROM;
@@ -30,6 +35,79 @@
void spl_dram_init(void)
{
+ int ret;
+
+ ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR,
+ EEPROM_ADDR_FALLBACK);
+ if (ret)
+ goto out;
+
+ ret = phytec_imx8m_detect(NULL);
+ if (!ret)
+ phytec_print_som_info(NULL);
+
+ ret = phytec_get_rev(NULL);
+ if (ret >= 3 && ret != PHYTEC_EEPROM_INVAL) {
+ dram_timing.ddrc_cfg[3].val = 0x1323;
+ dram_timing.ddrc_cfg[4].val = 0x1e84800;
+ dram_timing.ddrc_cfg[5].val = 0x7a0118;
+ dram_timing.ddrc_cfg[8].val = 0xc00307a3;
+ dram_timing.ddrc_cfg[9].val = 0xc50000;
+ dram_timing.ddrc_cfg[10].val = 0xf4003f;
+ dram_timing.ddrc_cfg[11].val = 0xf30000;
+ dram_timing.ddrc_cfg[14].val = 0x2028222a;
+ dram_timing.ddrc_cfg[15].val = 0x8083f;
+ dram_timing.ddrc_cfg[16].val = 0xe0e000;
+ dram_timing.ddrc_cfg[17].val = 0x12040a12;
+ dram_timing.ddrc_cfg[18].val = 0x2050f0f;
+ dram_timing.ddrc_cfg[19].val = 0x1010009;
+ dram_timing.ddrc_cfg[20].val = 0x502;
+ dram_timing.ddrc_cfg[21].val = 0x20800;
+ dram_timing.ddrc_cfg[22].val = 0xe100002;
+ dram_timing.ddrc_cfg[23].val = 0x120;
+ dram_timing.ddrc_cfg[24].val = 0xc80064;
+ dram_timing.ddrc_cfg[25].val = 0x3e8001e;
+ dram_timing.ddrc_cfg[26].val = 0x3207a12;
+ dram_timing.ddrc_cfg[28].val = 0x4a3820e;
+ dram_timing.ddrc_cfg[30].val = 0x230e;
+ dram_timing.ddrc_cfg[37].val = 0x799;
+ dram_timing.ddrc_cfg[38].val = 0x9141d1c;
+ dram_timing.ddrc_cfg[74].val = 0x302;
+ dram_timing.ddrc_cfg[83].val = 0x599;
+ dram_timing.ddrc_cfg[99].val = 0x302;
+ dram_timing.ddrc_cfg[108].val = 0x599;
+ dram_timing.ddrphy_cfg[66].val = 0x18;
+ dram_timing.ddrphy_cfg[75].val = 0x1e3;
+ dram_timing.ddrphy_cfg[77].val = 0x1e3;
+ dram_timing.ddrphy_cfg[79].val = 0x1e3;
+ dram_timing.ddrphy_cfg[145].val = 0x3e8;
+ dram_timing.fsp_msg[0].drate = 4000;
+ dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0;
+ dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4;
+ dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3;
+ dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4;
+ dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3;
+ dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400;
+ dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f;
+ dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400;
+ dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f;
+ dram_timing.fsp_msg[3].drate = 4000;
+ dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0;
+ dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4;
+ dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3;
+ dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4;
+ dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3;
+ dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400;
+ dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f;
+ dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400;
+ dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f;
+ dram_timing.ddrphy_pie[480].val = 0x465;
+ dram_timing.ddrphy_pie[481].val = 0xfa;
+ dram_timing.ddrphy_pie[482].val = 0x9c4;
+ dram_timing.fsp_table[0] = 4000;
+ }
+
+out:
ddr_init(&dram_timing);
}
diff --git a/board/phytium/durian/durian.c b/board/phytium/durian/durian.c
index ee48474..0a4048d 100644
--- a/board/phytium/durian/durian.c
+++ b/board/phytium/durian/durian.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <command.h>
#include <cpu_func.h>
+#include <event.h>
#include <init.h>
#include <log.h>
#include <asm/armv8/mmu.h>
@@ -99,7 +100,7 @@
return 0;
}
-int last_stage_init(void)
+static int last_stage_init(void)
{
int ret;
@@ -113,3 +114,4 @@
}
return ret;
}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c
index 75d2636..960e491 100644
--- a/board/phytium/pomelo/pomelo.c
+++ b/board/phytium/pomelo/pomelo.c
@@ -7,6 +7,7 @@
#include <stdio.h>
#include <command.h>
+#include <event.h>
#include <init.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
@@ -102,7 +103,7 @@
return 0;
}
-int last_stage_init(void)
+static int last_stage_init(void)
{
int ret;
@@ -116,3 +117,4 @@
}
return ret;
}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
diff --git a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
index 516292a..4ad7807 100644
--- a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
+++ b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
@@ -12,6 +12,7 @@
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/misc.h>
+#include <linux/printk.h>
#include <power/regulator.h>
#define GRF_IO_VSEL_BT565_SHIFT 0
diff --git a/board/pine64/quartz64_rk3566/Makefile b/board/pine64/quartz64_rk3566/Makefile
deleted file mode 100644
index c24a40e..0000000
--- a/board/pine64/quartz64_rk3566/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += quartz64-rk3566.o
diff --git a/board/pine64/quartz64_rk3566/quartz64-rk3566.c b/board/pine64/quartz64_rk3566/quartz64-rk3566.c
deleted file mode 100644
index 4c027f2..0000000
--- a/board/pine64/quartz64_rk3566/quartz64-rk3566.c
+++ /dev/null
@@ -1 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
diff --git a/board/pine64/quartzpro64-rk3588/Kconfig b/board/pine64/quartzpro64-rk3588/Kconfig
new file mode 100644
index 0000000..96aa792
--- /dev/null
+++ b/board/pine64/quartzpro64-rk3588/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_QUARTZPRO64_RK3588
+
+config SYS_BOARD
+ default "quartzpro64-rk3588"
+
+config SYS_VENDOR
+ default "pine64"
+
+config SYS_CONFIG_NAME
+ default "quartzpro64-rk3588"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/board/pine64/quartzpro64-rk3588/MAINTAINERS b/board/pine64/quartzpro64-rk3588/MAINTAINERS
new file mode 100644
index 0000000..a7e944b
--- /dev/null
+++ b/board/pine64/quartzpro64-rk3588/MAINTAINERS
@@ -0,0 +1,8 @@
+QUARTZPRO64-RK3588
+M: Tom Fitzhenry <tom@tom-fitzhenry.me.uk>
+S: Maintained
+F: board/pine64/quartzpro64-rk3588
+F: include/configs/quartzpro64-rk3588.h
+F: configs/quartzpro64-rk3588_defconfig
+F: arch/arm/dts/rk3588-quartzpro64.dts
+F: arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi
diff --git a/board/pine64/quartzpro64-rk3588/Makefile b/board/pine64/quartzpro64-rk3588/Makefile
new file mode 100644
index 0000000..47819d9
--- /dev/null
+++ b/board/pine64/quartzpro64-rk3588/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += quartzpro64-rk3588.o
diff --git a/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c b/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c
new file mode 100644
index 0000000..bda804a
--- /dev/null
+++ b/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Google, Inc
+ */
+
+#include <fdtdec.h>
+#include <fdt_support.h>
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int quartzpro64_add_reserved_memory_fdt_nodes(void *new_blob)
+{
+ struct fdt_memory gap1 = {
+ .start = 0x3fc000000,
+ .end = 0x3fc4fffff,
+ };
+ struct fdt_memory gap2 = {
+ .start = 0x3fff00000,
+ .end = 0x3ffffffff,
+ };
+ unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
+ unsigned int ret;
+
+ /*
+ * Inject the reserved-memory nodes into the DTS
+ */
+ ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0,
+ NULL, flags);
+ if (ret)
+ return ret;
+
+ return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0,
+ NULL, flags);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ return quartzpro64_add_reserved_memory_fdt_nodes(blob);
+}
+#endif
diff --git a/board/pine64/rockpro64_rk3399/MAINTAINERS b/board/pine64/rockpro64_rk3399/MAINTAINERS
index 303db14..220ee21 100644
--- a/board/pine64/rockpro64_rk3399/MAINTAINERS
+++ b/board/pine64/rockpro64_rk3399/MAINTAINERS
@@ -1,5 +1,4 @@
ROCKPRO64
-M: Akash Gajjar <akash@openedev.com>
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: board/pine64/rockpro64_rk3399
diff --git a/board/purism/librem5/spl.c b/board/purism/librem5/spl.c
index 90f1fcf..581f092 100644
--- a/board/purism/librem5/spl.c
+++ b/board/purism/librem5/spl.c
@@ -418,9 +418,9 @@
return rv;
}
-int usb_gadget_handle_interrupts(int index)
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
{
- dwc3_uboot_handle_interrupt(0);
+ dwc3_uboot_handle_interrupt(dev);
return 0;
}
diff --git a/board/qualcomm/dragonboard845c/Makefile b/board/qualcomm/dragonboard845c/Makefile
deleted file mode 100644
index fe585ad..0000000
--- a/board/qualcomm/dragonboard845c/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
-#
-# This empty file prevents make error.
-# Board logic defined in arch/arm/mach-snapdragon/init_sdm845.c, no custom logic for dragonboard845c so far.
-#
-
-obj-y += dragonboard845c.o
diff --git a/board/qualcomm/dragonboard845c/dragonboard845c.c b/board/qualcomm/dragonboard845c/dragonboard845c.c
deleted file mode 100644
index c7685de..0000000
--- a/board/qualcomm/dragonboard845c/dragonboard845c.c
+++ /dev/null
@@ -1,9 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * This empty file prevents make linking error.
- * No custom logic for dragonboard845c so far.
- *
- * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
- */
-
-void noop(void) {}
diff --git a/board/radxa/rock/Makefile b/board/radxa/rock/Makefile
deleted file mode 100644
index fe94b60..0000000
--- a/board/radxa/rock/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2015 Heiko Stuebner
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += rock.o
diff --git a/board/radxa/rock/rock.c b/board/radxa/rock/rock.c
deleted file mode 100644
index bdc02a6..0000000
--- a/board/radxa/rock/rock.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2015 Google, Inc
- */
-
-#include <common.h>
diff --git a/board/radxa/rock2/Makefile b/board/radxa/rock2/Makefile
deleted file mode 100644
index caa305b..0000000
--- a/board/radxa/rock2/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2015 Google, Inc
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += rock2.o
diff --git a/board/radxa/rock2/rock2.c b/board/radxa/rock2/rock2.c
deleted file mode 100644
index bdc02a6..0000000
--- a/board/radxa/rock2/rock2.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2015 Google, Inc
- */
-
-#include <common.h>
diff --git a/board/renesas/rzg2l/Kconfig b/board/renesas/rzg2l/Kconfig
new file mode 100644
index 0000000..1335fc7
--- /dev/null
+++ b/board/renesas/rzg2l/Kconfig
@@ -0,0 +1,18 @@
+# Copyright (C) 2023 Renesas Electronics Corporation
+# SPDX-License-Identifier: GPL-2.0+
+
+if TARGET_RZG2L_SMARC_EVK
+
+config SYS_SOC
+ default "rmobile"
+
+config SYS_BOARD
+ default "rzg2l"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "rzg2l-smarc"
+
+endif
diff --git a/board/renesas/rzg2l/MAINTAINERS b/board/renesas/rzg2l/MAINTAINERS
new file mode 100644
index 0000000..0a51391
--- /dev/null
+++ b/board/renesas/rzg2l/MAINTAINERS
@@ -0,0 +1,6 @@
+RENESAS RZG2L BOARD FAMILY
+M: Paul Barker <paul.barker.ct@bp.renesas.com>
+S: Supported
+F: arch/arm/dts/rz-smarc-common.dtsi
+N: rzg2l
+N: r9a07g044
diff --git a/board/renesas/rzg2l/Makefile b/board/renesas/rzg2l/Makefile
new file mode 100644
index 0000000..466935f
--- /dev/null
+++ b/board/renesas/rzg2l/Makefile
@@ -0,0 +1,4 @@
+# Copyright (C) 2023 Renesas Electronics Corporation
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := rzg2l.o
diff --git a/board/renesas/rzg2l/rzg2l.c b/board/renesas/rzg2l/rzg2l.c
new file mode 100644
index 0000000..73201a8
--- /dev/null
+++ b/board/renesas/rzg2l/rzg2l.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * RZ/G2L board support.
+ * Copyright (C) 2023 Renesas Electronics Corporation
+ */
+
+#include <fdtdec.h>
+#include <linux/libfdt.h>
+
+#if IS_ENABLED(CONFIG_MULTI_DTB_FIT)
+/* If the firmware passed a device tree, use it for board identification. */
+extern u64 rcar_atf_boot_args[];
+
+static bool is_rzg2l_board(const char *board_name)
+{
+ void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
+
+ return fdt_node_check_compatible(atf_fdt_blob, 0, board_name) == 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
+
+ if (fdt_magic(atf_fdt_blob) != FDT_MAGIC)
+ return -1;
+
+ if (is_rzg2l_board("renesas,r9a07g044l2"))
+ return strcmp(name, "r9a07g044l2-smarc");
+
+ return -1;
+}
+#endif
+
+static void apply_atf_overlay(void *fdt_blob)
+{
+ void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
+
+ if (fdt_magic(atf_fdt_blob) == FDT_MAGIC)
+ fdt_overlay_apply_node(fdt_blob, 0, atf_fdt_blob, 0);
+}
+
+int fdtdec_board_setup(const void *fdt_blob)
+{
+ apply_atf_overlay((void *)fdt_blob);
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+void reset_cpu(void)
+{
+ /*
+ * TODO: Implement reset support once TrustedFirmware supports
+ * the appropriate call.
+ */
+}
diff --git a/board/rikomagic/mk808/Makefile b/board/rikomagic/mk808/Makefile
deleted file mode 100644
index a4d1688..0000000
--- a/board/rikomagic/mk808/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += mk808.o
diff --git a/board/rikomagic/mk808/mk808.c b/board/rikomagic/mk808/mk808.c
deleted file mode 100644
index e0bfc6f..0000000
--- a/board/rikomagic/mk808/mk808.c
+++ /dev/null
@@ -1,3 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-#include <common.h>
diff --git a/board/rockchip/evb_px30/Makefile b/board/rockchip/evb_px30/Makefile
deleted file mode 100644
index 74b0b9f..0000000
--- a/board/rockchip/evb_px30/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2017 Rockchip Electronics Co., Ltd
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += evb_px30.o
diff --git a/board/rockchip/evb_px30/evb_px30.c b/board/rockchip/evb_px30/evb_px30.c
deleted file mode 100644
index 29464ae..0000000
--- a/board/rockchip/evb_px30/evb_px30.c
+++ /dev/null
@@ -1,4 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2019 Rockchip Electronics Co., Ltd
- */
diff --git a/board/rockchip/evb_px5/Makefile b/board/rockchip/evb_px5/Makefile
deleted file mode 100644
index 40f6ff8..0000000
--- a/board/rockchip/evb_px5/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2017 Rockchip Electronics Co., Ltd
-
-obj-y += evb-px5.o
diff --git a/board/rockchip/evb_px5/evb-px5.c b/board/rockchip/evb_px5/evb-px5.c
deleted file mode 100644
index b81f970..0000000
--- a/board/rockchip/evb_px5/evb-px5.c
+++ /dev/null
@@ -1,4 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2017 Andy Yan
- */
diff --git a/board/rockchip/evb_rk3128/Makefile b/board/rockchip/evb_rk3128/Makefile
deleted file mode 100644
index 078bb89..0000000
--- a/board/rockchip/evb_rk3128/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += evk-rk3128.o
diff --git a/board/rockchip/evb_rk3128/evk-rk3128.c b/board/rockchip/evb_rk3128/evk-rk3128.c
deleted file mode 100644
index e69de29..0000000
--- a/board/rockchip/evb_rk3128/evk-rk3128.c
+++ /dev/null
diff --git a/board/rockchip/evb_rk3229/Makefile b/board/rockchip/evb_rk3229/Makefile
deleted file mode 100644
index 65dcd8b..0000000
--- a/board/rockchip/evb_rk3229/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2015 Google, Inc
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += evb_rk3229.o
diff --git a/board/rockchip/evb_rk3229/evb_rk3229.c b/board/rockchip/evb_rk3229/evb_rk3229.c
deleted file mode 100644
index 0b14b24..0000000
--- a/board/rockchip/evb_rk3229/evb_rk3229.c
+++ /dev/null
@@ -1,9 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd
- */
-
-#include <common.h>
-#include <dm.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/uart.h>
diff --git a/board/rockchip/evb_rk3288/Makefile b/board/rockchip/evb_rk3288/Makefile
deleted file mode 100644
index c11b657..0000000
--- a/board/rockchip/evb_rk3288/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2016 Rockchip Electronics Co., Ltd
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += evb-rk3288.o
diff --git a/board/rockchip/evb_rk3288/evb-rk3288.c b/board/rockchip/evb_rk3288/evb-rk3288.c
deleted file mode 100644
index 1649bee..0000000
--- a/board/rockchip/evb_rk3288/evb-rk3288.c
+++ /dev/null
@@ -1,4 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- */
diff --git a/board/rockchip/evb_rk3328/Makefile b/board/rockchip/evb_rk3328/Makefile
deleted file mode 100644
index 81c5de8..0000000
--- a/board/rockchip/evb_rk3328/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2016 Rockchip Electronics Co., Ltd
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += evb-rk3328.o
diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c b/board/rockchip/evb_rk3328/evb-rk3328.c
deleted file mode 100644
index 1649bee..0000000
--- a/board/rockchip/evb_rk3328/evb-rk3328.c
+++ /dev/null
@@ -1,4 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- */
diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS
index c7e412b..acdb840 100644
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -93,7 +93,6 @@
F: arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
ROCK-PI-4
-M: Akash Gajjar <akash@openedev.com>
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: configs/rock-pi-4-rk3399_defconfig
diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS
index cc9eb43..e5b0986 100644
--- a/board/rockchip/evb_rk3568/MAINTAINERS
+++ b/board/rockchip/evb_rk3568/MAINTAINERS
@@ -1,3 +1,10 @@
+BANANAPI-BPI-R2-PRO
+M: Frank Wunderlich <frank-w@public-files.de>
+S: Maintained
+F: configs/bpi-r2-pro-rk3568_defconfig
+F: arch/arm/dts/rk3568-bpi-r2-pro.dts
+F: arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi
+
EVB-RK3568
M: Joseph Chen <chenjh@rock-chips.com>
S: Maintained
@@ -7,6 +14,13 @@
F: arch/arm/dts/rk3568-evb-u-boot.dtsi
F: arch/arm/dts/rk3568-evb.dts
+GENERIC-RK3568
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: configs/generic-rk3568_defconfig
+F: arch/arm/dts/rk3568-generic.dts
+F: arch/arm/dts/rk3568-generic-u-boot.dtsi
+
LUBANCAT-2
M: Andy Yan <andyshrk@163.com>
S: Maintained
diff --git a/board/rockchip/evb_rk3568/Makefile b/board/rockchip/evb_rk3568/Makefile
deleted file mode 100644
index cbda95f..0000000
--- a/board/rockchip/evb_rk3568/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2021 Rockchip Electronics Co., Ltd
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += evb_rk3568.o
diff --git a/board/rockchip/evb_rk3568/evb_rk3568.c b/board/rockchip/evb_rk3568/evb_rk3568.c
deleted file mode 100644
index c2fdf95..0000000
--- a/board/rockchip/evb_rk3568/evb_rk3568.c
+++ /dev/null
@@ -1,4 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2021 Rockchip Electronics Co., Ltd
- */
diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS
index 6b2c257..2bd44bc 100644
--- a/board/rockchip/evb_rk3588/MAINTAINERS
+++ b/board/rockchip/evb_rk3588/MAINTAINERS
@@ -6,3 +6,17 @@
F: configs/evb-rk3588_defconfig
F: arch/arm/dts/rk3588-evb1-v10.dts
F: arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi
+
+ORANGEPI-5-RK3588
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: configs/orangepi-5-rk3588s_defconfig
+F: arch/arm/dts/rk3588s-orangepi-5.dts
+F: arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi
+
+ORANGEPI-5-PLUS-RK3588
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: configs/orangepi-5-plus-rk3588_defconfig
+F: arch/arm/dts/rk3588-orangepi-5-plus.dts
+F: arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi
diff --git a/board/rockchip/sheep_rk3368/Makefile b/board/rockchip/sheep_rk3368/Makefile
deleted file mode 100644
index 9661528..0000000
--- a/board/rockchip/sheep_rk3368/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2017 Rockchip Electronics Co., Ltd
-
-obj-y += sheep_rk3368.o
diff --git a/board/rockchip/sheep_rk3368/sheep_rk3368.c b/board/rockchip/sheep_rk3368/sheep_rk3368.c
deleted file mode 100644
index b81f970..0000000
--- a/board/rockchip/sheep_rk3368/sheep_rk3368.c
+++ /dev/null
@@ -1,4 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2017 Andy Yan
- */
diff --git a/board/ronetix/imx7-cm/spl.c b/board/ronetix/imx7-cm/spl.c
index d36f734..b94cfd6 100644
--- a/board/ronetix/imx7-cm/spl.c
+++ b/board/ronetix/imx7-cm/spl.c
@@ -16,6 +16,7 @@
#include <asm/arch-mx7/mx7-ddr.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/gpio.h>
+#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#include <spl.h>
diff --git a/board/ronetix/imx8mq-cm/spl.c b/board/ronetix/imx8mq-cm/spl.c
index b9a6745..1c675bc 100644
--- a/board/ronetix/imx8mq-cm/spl.c
+++ b/board/ronetix/imx8mq-cm/spl.c
@@ -13,6 +13,7 @@
#include <asm/arch/clock.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#include <linux/delay.h>
#include <spl.h>
diff --git a/board/sagem/f@st1704/Makefile b/board/sagem/f@st1704/Makefile
deleted file mode 100644
index 08d44a0..0000000
--- a/board/sagem/f@st1704/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += f@st1704.o
diff --git a/board/sagem/f@st1704/f@st1704.c b/board/sagem/f@st1704/f@st1704.c
deleted file mode 100644
index 1e4b728..0000000
--- a/board/sagem/f@st1704/f@st1704.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- */
-
-#include <common.h>
diff --git a/board/samsung/axy17lte/Kconfig b/board/samsung/axy17lte/Kconfig
index a018547..64a4ffa 100644
--- a/board/samsung/axy17lte/Kconfig
+++ b/board/samsung/axy17lte/Kconfig
@@ -1,11 +1,3 @@
-config SYS_CONFIG_NAME
- string "Board configuration name"
- default "exynos78x0-common.h"
- help
- This option contains information about board configuration name.
- Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
- will be used for board configuration.
-
if TARGET_A5Y17LTE
config SYS_BOARD
default "axy17lte"
@@ -16,7 +8,7 @@
default "samsung"
config SYS_CONFIG_NAME
- default "a5y17lte"
+ default "exynos78x0-common"
config EXYNOS7880
bool "Exynos 7880 SOC support"
@@ -33,7 +25,7 @@
default "samsung"
config SYS_CONFIG_NAME
- default "a5y17lte"
+ default "exynos78x0-common"
config EXYNOS7880
bool "Exynos 7880 SOC support"
@@ -50,7 +42,7 @@
default "samsung"
config SYS_CONFIG_NAME
- default "a3y17lte"
+ default "exynos78x0-common"
config EXYNOS7870
bool "Exynos 7870 SOC support"
diff --git a/board/samsung/axy17lte/Makefile b/board/samsung/axy17lte/Makefile
deleted file mode 100644
index 4e11f28..0000000
--- a/board/samsung/axy17lte/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-obj-y += axy17lte.o
diff --git a/board/samsung/axy17lte/axy17lte.c b/board/samsung/axy17lte/axy17lte.c
deleted file mode 100644
index c38297a..0000000
--- a/board/samsung/axy17lte/axy17lte.c
+++ /dev/null
@@ -1,11 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Samsung A5Y17 and A3Y17 LTE boards based on Exynos 7880 and Exynos 7870 SoCs
- */
-
-#include <common.h>
-
-int exynos_init(void)
-{
- return 0;
-}
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 663d7ca..5a71982 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -43,6 +43,10 @@
return 0;
}
+__weak void exynos_init(void)
+{
+}
+
__weak int exynos_power_init(void)
{
return 0;
@@ -113,7 +117,9 @@
gd->ram_size -= size;
gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size;
#endif
- return exynos_init();
+ exynos_init();
+
+ return 0;
}
int dram_init(void)
diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c
index cde77d7..95cf6d2 100644
--- a/board/samsung/common/exynos5-dt.c
+++ b/board/samsung/common/exynos5-dt.c
@@ -26,6 +26,7 @@
#include <asm/arch/pinmux.h>
#include <asm/arch/power.h>
#include <asm/arch/sromc.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/max77686_pmic.h>
#include <power/regulator.h>
@@ -37,11 +38,6 @@
DECLARE_GLOBAL_DATA_PTR;
-int exynos_init(void)
-{
- return 0;
-}
-
static int exynos_set_regulator(const char *name, uint uv)
{
struct udevice *dev;
@@ -126,9 +122,9 @@
.index = 0,
};
-int usb_gadget_handle_interrupts(int index)
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
{
- dwc3_uboot_handle_interrupt(0);
+ dwc3_uboot_handle_interrupt(dev);
return 0;
}
diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
index 5ffa216..cc114aa 100644
--- a/board/samsung/common/misc.c
+++ b/board/samsung/common/misc.c
@@ -10,6 +10,7 @@
#include <libtizen.h>
#include <asm/global_data.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <samsung/misc.h>
#include <errno.h>
#include <version.h>
diff --git a/board/samsung/espresso7420/Makefile b/board/samsung/espresso7420/Makefile
deleted file mode 100644
index bb882ea..0000000
--- a/board/samsung/espresso7420/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2016 Samsung Electronics
-# Thomas Abraham <thomas.ab@samsung.com>
-
-obj-y += espresso7420.o
diff --git a/board/samsung/espresso7420/espresso7420.c b/board/samsung/espresso7420/espresso7420.c
deleted file mode 100644
index 9f6fa89..0000000
--- a/board/samsung/espresso7420/espresso7420.c
+++ /dev/null
@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Espresso7420 board file
- * Copyright (C) 2016 Samsung Electronics
- * Thomas Abraham <thomas.ab@samsung.com>
- */
-
-#include <common.h>
-
-int exynos_init(void)
-{
- return 0;
-}
diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
index 535f8e1..c8f5a15 100644
--- a/board/samsung/goni/goni.c
+++ b/board/samsung/goni/goni.c
@@ -13,6 +13,7 @@
#include <asm/arch/mmc.h>
#include <dm.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <usb/dwc2_udc.h>
#include <asm/arch/cpu.h>
diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
index 39a60e4..99e5613 100644
--- a/board/samsung/odroid/odroid.c
+++ b/board/samsung/odroid/odroid.c
@@ -15,6 +15,7 @@
#include <asm/arch/cpu.h>
#include <dm.h>
#include <env.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <power/max77686_pmic.h>
@@ -422,11 +423,9 @@
return 0;
}
-int exynos_init(void)
+void exynos_init(void)
{
board_gpio_init();
-
- return 0;
}
int exynos_power_init(void)
diff --git a/board/samsung/origen/origen.c b/board/samsung/origen/origen.c
index 7a91f44..ddf6a2b 100644
--- a/board/samsung/origen/origen.c
+++ b/board/samsung/origen/origen.c
@@ -12,11 +12,6 @@
#include <asm/arch/pinmux.h>
#include <usb.h>
-int exynos_init(void)
-{
- return 0;
-}
-
int board_usb_init(int index, enum usb_init_type init)
{
return 0;
diff --git a/board/samsung/starqltechn/Makefile b/board/samsung/starqltechn/Makefile
deleted file mode 100644
index e017c82..0000000
--- a/board/samsung/starqltechn/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
-#
-# This empty file prevents make error.
-# Board logic defined in arch/arm/mach-snapdragon/init_sdm845.c, no custom logic for starqltechn so far.
-#
-
-obj-y += starqltechn.o
diff --git a/board/samsung/starqltechn/starqltechn.c b/board/samsung/starqltechn/starqltechn.c
deleted file mode 100644
index f2cdb4e..0000000
--- a/board/samsung/starqltechn/starqltechn.c
+++ /dev/null
@@ -1,10 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * This empty file prevents make linking error.
- * No custom logic for starqltechn so far.
- *
- * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
- *
- */
-
-void nooop(void) {}
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index 1608d60..6a3e5b2 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -40,17 +40,8 @@
}
#endif
-static void check_hw_revision(void);
struct dwc2_plat_otg_data s5pc210_otg_data;
-int exynos_init(void)
-{
- check_hw_revision();
- printf("HW Revision:\t0x%x\n", board_rev);
-
- return 0;
-}
-
#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
static void trats_low_power_mode(void)
{
@@ -215,6 +206,11 @@
board_rev |= hwrev;
}
+void exynos_init(void)
+{
+ check_hw_revision();
+ printf("HW Revision:\t0x%x\n", board_rev);
+}
#ifdef CONFIG_USB_GADGET
static int s5pc210_phy_control(int on)
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index 93c9714..81ccc12 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -107,7 +107,7 @@
return 0;
}
-int exynos_init(void)
+void exynos_init(void)
{
struct exynos4_power *pwr =
(struct exynos4_power *)samsung_get_base_power();
@@ -124,8 +124,6 @@
*/
writel(0, &pwr->inform4);
writel(0, &pwr->inform5);
-
- return 0;
}
int exynos_power_init(void)
diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c
index 37c9d7f..2d61dff 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -265,7 +265,7 @@
return 0;
}
-int exynos_init(void)
+void exynos_init(void)
{
gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
@@ -293,6 +293,4 @@
check_hw_revision();
printf("HW Revision:\t0x%x\n", board_rev);
-
- return 0;
}
diff --git a/board/sandbox/capsule_priv_key_bad.key b/board/sandbox/capsule_priv_key_bad.key
new file mode 100644
index 0000000..2324f69
--- /dev/null
+++ b/board/sandbox/capsule_priv_key_bad.key
@@ -0,0 +1,28 @@
+-----BEGIN PRIVATE KEY-----
+MIIEvQIBADANBgkqhkiG9w0BAQEFAASCBKcwggSjAgEAAoIBAQCmPw1pGd2xNW0p
+lesRXkkek3uwUB06Nt61tnZvpMkBKt4IokqGWz1tZls+Z2CqvwOfcsPZ27cPRYSu
+xRnM3YdL4MG6SePV7i/YSNw3rq8CP8zLGtCbNIfsfsNfPQEtPBpw6+7pMJKhjqpV
+2U2UQzZEiX4qlnhLpyv2JNJag27yf0feLdJi7HnJ9xdvcXpA1DSGm4y+DDhgYeI8
+DEteEu6s0TYQfnOZSQOeJi+1/Qz0S594uFJB37MyGh/mB15ILb8gva4nA3ayHOBK
+0dd+HSiUCGYrLYO7aj+nfzQj9N1qTlzCnC1603bMczU5pkwcODg6xP0Sn11J6RYy
+y0c0qzJLAgMBAAECggEABDY2MLoew3IkBltrParAWAUUcFLi95jw92q6BkOHEJg8
+2qia1yCitPUtPodMLmOKF5x4EdgXg5sv2O8MGbWP1VtUKXGh3QJcnRnNmsZ1hXJC
+RBcrei2aVLsqf0V2Mg3+GuG8PW3vLWHyZ/Sd6afeuXEYm2Bzrw9J5rfd3dBVKm7f
+HBvIyy1ATO/2cbUaEaCLOyhxLhssTI2TIK5SjlsjFLxiQXEi6RyGfBxUCriKZykS
+krMdvYh7Tf0uYcv0STmQ5s5Rd+RhRIGCVAdsNBxxJjgBAgqqa/B+kWbcc6o2D41n
+yWjErUaBBx3t0A7oT4K4DSTYwMNDVY3fhdd+szsocQKBgQDjnm8LG4UO6OQDm6iX
+0vTQTItoAz5TU6GEjHTCfVEqiupD4LKfHhSXwp2hRyzxXO5oNTU9MQCzYd7Npes0
+oVk4Tjo3YDacNPgxqKjODu/Q+tkTH15ydzGr674+YXHfCA1uT5GKOiiF0H1FZgMa
+Dk0s+3uWX34vbL4QCu97bUhBewKBgQC6+Z0J9sClgWvvjkglJN3XhRnAacp+WgX7
+bkpgSboXIIsqeqhd1WCLeV7L1pcZgifYBMPojf5LTBqBedL1q3RuqiqQWD/bSIYN
+Oc9KCdTjksS8Zo+w+s5zDObDhW9y13H2mKwDqilYBrT4fiA62wPMf1SjEF+RSC6K
+ZrQzHO1xcQKBgAILsXnLFIYOx8XUh05eAf9BQNt9c/jxvnjffkklMS6Nsw9LHK/b
+aFn40MvbROcia64aFFFpeFUkYwk8HYIKlS+xXEqVHciHnVds6Z94eOVK69qFJKco
+tRSTeNE8tPZJLz23j1pLrYOOXSHbidmZGU53MCQo1Yx9kLO6NW7Ji6WzAoGBALP4
+lEoE80Xbn3NEdvkZ1VcfzLvCmKCqMlvjuz+Xd8HPF2VaDznSq01VFAQMmAB7obJy
+U8hC9OSxakn6Yy8JS9dBgBrUdxKxaibM4FQZxosOuMPHzMPDhniDkJPemnnmGtIL
+/nbAkW8jdYpCjO9Z5PwwC92xYuvKmNGrLgSM8ZhhAoGAfgSZTpASXubM18E3ecfw
+5z333wf9qEQgZj7i9MzByFZudyHUhv/FPW1ocUJf36Wu1dfofZg3noSL6oakrm2v
+dFDo4PoyCStuF0w9SSzpIld01ZG0t7XqphY0DmshCXIXsqr7Vb4WrbBI7KX+b3Um
+BzmROfaSud97NjQ/RA26OZk=
+-----END PRIVATE KEY-----
diff --git a/board/sandbox/capsule_priv_key_good.key b/board/sandbox/capsule_priv_key_good.key
new file mode 100644
index 0000000..9a37f59
--- /dev/null
+++ b/board/sandbox/capsule_priv_key_good.key
@@ -0,0 +1,28 @@
+-----BEGIN PRIVATE KEY-----
+MIIEvQIBADANBgkqhkiG9w0BAQEFAASCBKcwggSjAgEAAoIBAQCwBfaV0P1jRzS6
+13U1T+4VbuMVsxFXhwHJY5z5Fx6v+cWBf3K1ruK+7cEnW55ZHXvNE2JCkjMvISKm
+hI/DLJWIPnAus8tFdU/R2u5oJbKI+b6GbuamO/CG9HsXZ58lOC6r2ckjixxovsA9
+SFshccdIv2YrwiVsWeyFpH+rB3/+cFbrgdWpaUc1367GkU/ZCnSRDBvVvzRRI1a4
+y2NogFqbZHXHENpzWNJ3TTXhf9dwM5HFGkmX7SA43Dtazae6CB4EaUKzLYWj3+ae
+AQbdvBrupKZQz1PUKn7X6+BGaLujHthvibYppNegPvqbJ1xBbv59CQK+lRULwC05
+NYw5+sIxAgMBAAECggEAHn8h/knjpMAw/BAZP//VrYP1Nwy7u/Dpl9U43JUrXWzG
+Uc3dd2nR4id6GBIRCLqJePnbQ9JlqMwyXyxHZhbC34SF1imTVbjh9+dY99VULdQr
+NMphDrsCzLbt3pu24HFv8Jk+dniDFwi5cMSo+U3nq4xxrLIp3rBjwLHD5sNZYyEU
+9xZnj7ziTn5X8da8iRxNpyzz2kQeVemJ0ahr/IkX718bkakSFMesGkln06vH7rAs
+069SeqOPrFEbWYXI5iMktLugl3JZpzasRE48j0M42PuProgvT7jb8B35ZF7kn0jT
+MqTIHglsJRWcSY0fAb2lHSAvd2vLLVunxr9PDWZvGQKBgQDVzVTuvo1CrVrQLy+B
+tpy2k5mjR3qxAOcoWTnKcMErLe8imWWaxukODenP4XqQIX4Sl+X3BXxOqun0Klap
+FEsI7TWSHf0eULFtFj0SCgqfRR+V/nblP05eO2nFXgr5YdNa1bWf/aMHplBo4q9e
+bbAr4InUB7IGWL2cWjhOhWuJbQKBgQDSw81cBM+vGPUYH/wlxlTVgZCo2Dg2NHjt
+LUBqvOZNr21j2F+w8t1vKmqwhkqpc5HIi3pHjEA5gZLTRtmf4GQyo973I6MGn4bS
+eayOd6/+FkAi9DUD+WaF7yctJqeevav6KF2UCiz78OtCAU5Y9jFFJpuOANIztI7m
+t7ZCUpMFVQKBgFnAsP7oj3SGQbFTnaXeeztKCx04TJExx9hwXIpXe0AdMF5d9wFa
+r0tvG9Bg34rSBJLZoXhpnR2JMl2FyIuCMV219t84J6IqTdF1nH2OKZdi9TeKc28Z
+fFSirGxmZkT6hDeFr5FScLYtY2QkhWomseY5hKK1+E4hwrd4SFruN46hAoGBAJgh
+nzTBgEtqH1enlrCJhSiLmihV0dVGcNb559pjuXTvoG0GfKPT2gPowRPkCzZe5ia0
+jrHgSWd44MtCA8nEBW8MG9+VyJH6Si3Yh7ZaLB2iX+8bCL1yow8f/c44bZtGW0F5
+K3q1EZ1VW+rL2IqcQhog8P1CGHgb514f0x3yTo71AoGACGdb+Nb6lg8OSJPUcuuH
+xsWk6RhkJl9bldTleS+QT3R9zO3FvbTwnCCYJboh5Cq/jVmiA7T+fcVAyEJNHSdm
+hxbHdScuiJdNWL9+FczOkylnKH3VEdG3RS5lGdyi6r+miTMs3h8WfzGp4JINysjg
+PUFskK36qGjASfkRUn0hizQ=
+-----END PRIVATE KEY-----
diff --git a/board/sandbox/capsule_pub_esl_good.esl b/board/sandbox/capsule_pub_esl_good.esl
new file mode 100644
index 0000000..f8cc272
--- /dev/null
+++ b/board/sandbox/capsule_pub_esl_good.esl
Binary files differ
diff --git a/board/sandbox/capsule_pub_key_bad.crt b/board/sandbox/capsule_pub_key_bad.crt
new file mode 100644
index 0000000..2e8e5d5
--- /dev/null
+++ b/board/sandbox/capsule_pub_key_bad.crt
@@ -0,0 +1,19 @@
+-----BEGIN CERTIFICATE-----
+MIIDDzCCAfegAwIBAgIUWw3vHYnrjoHUXytxSm2eYWzbYVAwDQYJKoZIhvcNAQEL
+BQAwFjEUMBIGA1UEAwwLVEVTVF9TSUdORVIwIBcNMjMwODA0MTgwODEyWhgPMzAw
+MzEwMDYxODA4MTJaMBYxFDASBgNVBAMMC1RFU1RfU0lHTkVSMIIBIjANBgkqhkiG
+9w0BAQEFAAOCAQ8AMIIBCgKCAQEApj8NaRndsTVtKZXrEV5JHpN7sFAdOjbetbZ2
+b6TJASreCKJKhls9bWZbPmdgqr8Dn3LD2du3D0WErsUZzN2HS+DBuknj1e4v2Ejc
+N66vAj/MyxrQmzSH7H7DXz0BLTwacOvu6TCSoY6qVdlNlEM2RIl+KpZ4S6cr9iTS
+WoNu8n9H3i3SYux5yfcXb3F6QNQ0hpuMvgw4YGHiPAxLXhLurNE2EH5zmUkDniYv
+tf0M9EufeLhSQd+zMhof5gdeSC2/IL2uJwN2shzgStHXfh0olAhmKy2Du2o/p380
+I/Tdak5cwpwtetN2zHM1OaZMHDg4OsT9Ep9dSekWMstHNKsySwIDAQABo1MwUTAd
+BgNVHQ4EFgQUm9b8SnF811nweXSfGisfpzUHGwgwHwYDVR0jBBgwFoAUm9b8SnF8
+11nweXSfGisfpzUHGwgwDwYDVR0TAQH/BAUwAwEB/zANBgkqhkiG9w0BAQsFAAOC
+AQEAaOZFOcQzF1MRekcBmIZMaHSWYxOUrVLzBNSNhFD8muYiUAAufrkyTUq0Mmat
+w5hAnJ34VGpU1wxQlr/uwH7wpZZnGuj10rAp3tqES0g24AeH1bC9wmRs+rD6dcZR
+YmZq6FxtV7Cv3pQX7lhDYbcBj2za3YT6I1+yczskAHR6KYYuJzKJ7XRVCL7ZlYRX
+pUMZBQq2eAVWlW/c5iDT3KoGZUD9Of71F7qyUAqMMYafeDxguDz7gKstoXVCklQ+
+I4C7JKmRbrRvMgXx6O1clGhAsRZ0nNAtzi7XT5tD27qFwIPgwv48RWgsmPtzE03S
+YGQ5WhYMdHOOjWmcV6MDkCpiSA==
+-----END CERTIFICATE-----
diff --git a/board/sandbox/capsule_pub_key_good.crt b/board/sandbox/capsule_pub_key_good.crt
new file mode 100644
index 0000000..82d8576
--- /dev/null
+++ b/board/sandbox/capsule_pub_key_good.crt
@@ -0,0 +1,19 @@
+-----BEGIN CERTIFICATE-----
+MIIDDzCCAfegAwIBAgIUUzrWhMi7oPFshQP6eFlccqf7exswDQYJKoZIhvcNAQEL
+BQAwFjEUMBIGA1UEAwwLVEVTVF9TSUdORVIwIBcNMjMwODA0MTgwNzQyWhgPMzAw
+MzEwMDYxODA3NDJaMBYxFDASBgNVBAMMC1RFU1RfU0lHTkVSMIIBIjANBgkqhkiG
+9w0BAQEFAAOCAQ8AMIIBCgKCAQEAsAX2ldD9Y0c0utd1NU/uFW7jFbMRV4cByWOc
++Rcer/nFgX9yta7ivu3BJ1ueWR17zRNiQpIzLyEipoSPwyyViD5wLrPLRXVP0dru
+aCWyiPm+hm7mpjvwhvR7F2efJTguq9nJI4scaL7APUhbIXHHSL9mK8IlbFnshaR/
+qwd//nBW64HVqWlHNd+uxpFP2Qp0kQwb1b80USNWuMtjaIBam2R1xxDac1jSd001
+4X/XcDORxRpJl+0gONw7Ws2nuggeBGlCsy2Fo9/mngEG3bwa7qSmUM9T1Cp+1+vg
+Rmi7ox7Yb4m2KaTXoD76mydcQW7+fQkCvpUVC8AtOTWMOfrCMQIDAQABo1MwUTAd
+BgNVHQ4EFgQUHvG7Xchqzwdggky+oyzlpNem8UowHwYDVR0jBBgwFoAUHvG7Xchq
+zwdggky+oyzlpNem8UowDwYDVR0TAQH/BAUwAwEB/zANBgkqhkiG9w0BAQsFAAOC
+AQEAUn1ncSqeXbQAHNrVOFldLwu70hNlMxf2z4EfH2M7vJgrpwkRuIFw7PXNITBh
+CImd/ghm5NGFysrK7BwdHkFvUXZV3rE93BhcLC9leWfky33kW9olIzpE14i5FfBn
+ABmaokPhOrzAneGzU35sZHNotlqOrzgpKVkpOWrykhYZ5Qjk8Sz0xvzuG8TJc20s
+2og+W8Rm2u/xI9xPxtFbq9vUjvFS35o1pm+vkzpgNdo4YS1PG37BW/aopsooLSk7
+9Rxv5vzNXtQqeZ5qBdKbAVh3OsgqwigTmXVvOX3xpy9r9qiimhaISxCt83RZ7wQW
+I19t9pXyxAi6u7MRhJZlAeH/3w==
+-----END CERTIFICATE-----
diff --git a/board/sfr/nb4_ser/Makefile b/board/sfr/nb4_ser/Makefile
deleted file mode 100644
index ab7ad76..0000000
--- a/board/sfr/nb4_ser/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += nb4-ser.o
diff --git a/board/sfr/nb4_ser/nb4-ser.c b/board/sfr/nb4_ser/nb4-ser.c
deleted file mode 100644
index 1e4b728..0000000
--- a/board/sfr/nb4_ser/nb4-ser.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- */
-
-#include <common.h>
diff --git a/board/siemens/capricorn/spl.c b/board/siemens/capricorn/spl.c
index 8e077d7..e160c61 100644
--- a/board/siemens/capricorn/spl.c
+++ b/board/siemens/capricorn/spl.c
@@ -10,6 +10,7 @@
#include <spl.h>
#include <dm.h>
#include <asm/global_data.h>
+#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
index 8fa9197..d077751 100644
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c
@@ -6,7 +6,7 @@
*
* Based on:
* U-Boot file:/board/ti/am335x/board.c
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/siemens/draco/Makefile b/board/siemens/draco/Makefile
index 3e3394a..e94456a 100644
--- a/board/siemens/draco/Makefile
+++ b/board/siemens/draco/Makefile
@@ -7,7 +7,7 @@
#
# Based on:
# u-boot:/board/ti/am335x/Makefile
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
ifdef CONFIG_SPL_BUILD
obj-y := mux.o
diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c
index 88746590..8b13d23 100644
--- a/board/siemens/draco/board.c
+++ b/board/siemens/draco/board.c
@@ -9,7 +9,7 @@
* Board functions for TI AM335X based boards
* u-boot:/board/ti/am335x/board.c
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/siemens/draco/board.h b/board/siemens/draco/board.h
index 7c29a45..f027427 100644
--- a/board/siemens/draco/board.h
+++ b/board/siemens/draco/board.h
@@ -9,7 +9,7 @@
* TI AM335x boards information header
* u-boot:/board/ti/am335x/board.h
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _BOARD_H_
diff --git a/board/siemens/draco/mux.c b/board/siemens/draco/mux.c
index 3f2d41b..2632f05 100644
--- a/board/siemens/draco/mux.c
+++ b/board/siemens/draco/mux.c
@@ -7,7 +7,7 @@
*
* Based on:
* u-boot:/board/ti/am335x/mux.c
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c
index 15f5310..0b0686e 100644
--- a/board/siemens/iot2050/board.c
+++ b/board/siemens/iot2050/board.c
@@ -155,19 +155,20 @@
strstr((char *)info->name, "IOT2050-ADVANCED") != NULL;
}
-static bool board_is_sr1(void)
+static bool board_is_pg1(void)
{
struct iot2050_info *info = IOT2050_INFO_DATA;
return info->magic == IOT2050_INFO_MAGIC &&
- strstr((char *)info->name, "-PG2") != NULL;
+ (strcmp((char *)info->name, "IOT2050-BASIC") == 0 ||
+ strcmp((char *)info->name, "IOT2050-ADVANCED") == 0);
}
static bool board_is_m2(void)
{
struct iot2050_info *info = IOT2050_INFO_DATA;
- return !board_is_sr1() && info->magic == IOT2050_INFO_MAGIC &&
+ return info->magic == IOT2050_INFO_MAGIC &&
strcmp((char *)info->name, "IOT2050-ADVANCED-M2") == 0;
}
@@ -217,14 +218,14 @@
}
if (board_is_advanced()) {
- if (board_is_sr1())
+ if (board_is_pg1())
fdtfile = "ti/k3-am6548-iot2050-advanced.dtb";
else if(board_is_m2())
fdtfile = "ti/k3-am6548-iot2050-advanced-m2.dtb";
else
fdtfile = "ti/k3-am6548-iot2050-advanced-pg2.dtb";
} else {
- if (board_is_sr1())
+ if (board_is_pg1())
fdtfile = "ti/k3-am6528-iot2050-basic.dtb";
else
fdtfile = "ti/k3-am6528-iot2050-basic-pg2.dtb";
diff --git a/board/siemens/iot2050/iot2050.env b/board/siemens/iot2050/iot2050.env
index caa9f80..8bbd7ab 100644
--- a/board/siemens/iot2050/iot2050.env
+++ b/board/siemens/iot2050/iot2050.env
@@ -6,7 +6,7 @@
* Jan Kiszka <jan.kiszka@siemens.com>
*/
-#include <env/ti/ti_armv7_common.env>
+#include <env/ti/ti_common.env>
usb_pgood_delay=900
diff --git a/board/siemens/pxm2/Makefile b/board/siemens/pxm2/Makefile
index 3e3394a..e94456a 100644
--- a/board/siemens/pxm2/Makefile
+++ b/board/siemens/pxm2/Makefile
@@ -7,7 +7,7 @@
#
# Based on:
# u-boot:/board/ti/am335x/Makefile
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
ifdef CONFIG_SPL_BUILD
obj-y := mux.o
diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c
index 47f19bc..40aee7c 100644
--- a/board/siemens/pxm2/board.c
+++ b/board/siemens/pxm2/board.c
@@ -9,7 +9,7 @@
*
* Board functions for TI AM335X based boards
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/siemens/pxm2/board.h b/board/siemens/pxm2/board.h
index af21fc4..9067e4d 100644
--- a/board/siemens/pxm2/board.h
+++ b/board/siemens/pxm2/board.h
@@ -9,7 +9,7 @@
* TI AM335x boards information header
* u-boot:/board/ti/am335x/board.h
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _BOARD_H_
diff --git a/board/siemens/pxm2/mux.c b/board/siemens/pxm2/mux.c
index 2f35bb4..d21ef47 100644
--- a/board/siemens/pxm2/mux.c
+++ b/board/siemens/pxm2/mux.c
@@ -8,7 +8,7 @@
* Based on:
* u-boot:/board/ti/am335x/mux.c
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/siemens/pxm2/pmic.h b/board/siemens/pxm2/pmic.h
index 3766046..f4ce7f1 100644
--- a/board/siemens/pxm2/pmic.h
+++ b/board/siemens/pxm2/pmic.h
@@ -4,7 +4,7 @@
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef PMIC_H
#define PMIC_H
diff --git a/board/siemens/rut/Makefile b/board/siemens/rut/Makefile
index 3e3394a..e94456a 100644
--- a/board/siemens/rut/Makefile
+++ b/board/siemens/rut/Makefile
@@ -7,7 +7,7 @@
#
# Based on:
# u-boot:/board/ti/am335x/Makefile
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
ifdef CONFIG_SPL_BUILD
obj-y := mux.o
diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c
index a8b196a..bad0b71 100644
--- a/board/siemens/rut/board.c
+++ b/board/siemens/rut/board.c
@@ -7,7 +7,7 @@
* Based on:
* u-boot:/board/ti/am335x/board.c
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/siemens/rut/board.h b/board/siemens/rut/board.h
index af21fc4..9067e4d 100644
--- a/board/siemens/rut/board.h
+++ b/board/siemens/rut/board.h
@@ -9,7 +9,7 @@
* TI AM335x boards information header
* u-boot:/board/ti/am335x/board.h
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _BOARD_H_
diff --git a/board/siemens/rut/mux.c b/board/siemens/rut/mux.c
index d80120b..894a9bf 100644
--- a/board/siemens/rut/mux.c
+++ b/board/siemens/rut/mux.c
@@ -8,7 +8,7 @@
* Based on:
* u-boot:/board/ti/am335x/mux.c
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/sifive/unleashed/unleashed.c b/board/sifive/unleashed/unleashed.c
index b6ab06a..3c5dd50 100644
--- a/board/sifive/unleashed/unleashed.c
+++ b/board/sifive/unleashed/unleashed.c
@@ -122,7 +122,7 @@
return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
}
- return (ulong *)&_end;
+ return (ulong *)_end;
}
int board_init(void)
diff --git a/board/sifive/unmatched/hifive-platform-i2c-eeprom.c b/board/sifive/unmatched/hifive-platform-i2c-eeprom.c
index 2b985b9..d25c24b 100644
--- a/board/sifive/unmatched/hifive-platform-i2c-eeprom.c
+++ b/board/sifive/unmatched/hifive-platform-i2c-eeprom.c
@@ -9,7 +9,6 @@
* Timur Tabi (timur@freescale.com)
*/
-#include <common.h>
#include <command.h>
#include <env.h>
#include <i2c.h>
@@ -426,7 +425,7 @@
}
if (argc > 3)
- return cmd_usage(cmdtp);
+ return CMD_RET_USAGE;
cmd = argv[1];
@@ -443,7 +442,7 @@
}
if (argc != 3)
- return cmd_usage(cmdtp);
+ return CMD_RET_USAGE;
if (!is_match_magic()) {
printf("Please read the EEPROM ('read_eeprom') and/or initialize the EEPROM ('initialize') first.\n");
@@ -470,7 +469,7 @@
return 0;
}
- return cmd_usage(cmdtp);
+ return CMD_RET_USAGE;
}
/**
@@ -551,3 +550,19 @@
return be.pcb_revision;
}
+
+U_BOOT_LONGHELP(mac,
+ "- displays memory copy of EEPROM\n"
+ "mac read_eeprom - reads EEPROM into memory\n"
+ "mac initialize - initializes memory copy with magic number\n"
+ "mac write_eeprom - writes the EEPROM from memory\n"
+ "mac manuf_test_status [unknown|pass|fail] - sets test status in memory\n"
+ "mac_address <addr> - sets MAC address in memory\n"
+ "mac pcb_revision <rev> - sets PCB revision in memory\n"
+ "mac bom_variant <var> - sets BOM variant in memory\n"
+ "mac bom_revision <rev> - sets BOM revision in memory\n");
+
+U_BOOT_CMD(
+ mac, 3, 1, do_mac,
+ "display and program the board revision and MAC address in EEPROM",
+ mac_help_text);
diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c
index 6295dee..c869627 100644
--- a/board/sifive/unmatched/unmatched.c
+++ b/board/sifive/unmatched/unmatched.c
@@ -6,7 +6,6 @@
* Pragnesh Patel <pragnesh.patel@sifive.com>
*/
-#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <asm/sections.h>
@@ -19,7 +18,7 @@
return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
}
- return (ulong *)&_end;
+ return (ulong *)_end;
}
int board_init(void)
diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c
index 204e5a4..ac4415f 100644
--- a/board/socionext/developerbox/developerbox.c
+++ b/board/socionext/developerbox/developerbox.c
@@ -20,39 +20,18 @@
#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
struct efi_fw_image fw_images[] = {
-#if CONFIG_IS_ENABLED(FWU_MULTI_BANK_UPDATE)
{
.image_type_id = DEVELOPERBOX_FIP_IMAGE_GUID,
.fw_name = u"DEVELOPERBOX-FIP",
.image_index = 1,
},
-#else
- {
- .image_type_id = DEVELOPERBOX_UBOOT_IMAGE_GUID,
- .fw_name = u"DEVELOPERBOX-UBOOT",
- .image_index = 1,
- },
- {
- .image_type_id = DEVELOPERBOX_FIP_IMAGE_GUID,
- .fw_name = u"DEVELOPERBOX-FIP",
- .image_index = 2,
- },
- {
- .image_type_id = DEVELOPERBOX_OPTEE_IMAGE_GUID,
- .fw_name = u"DEVELOPERBOX-OPTEE",
- .image_index = 3,
- },
-#endif
};
struct efi_capsule_update_info update_info = {
- .dfu_string = "mtd nor1=u-boot.bin raw 200000 100000;"
- "fip.bin raw 180000 78000;"
- "optee.bin raw 500000 100000",
+ .dfu_string = "mtd nor1=fip.bin raw 600000 400000",
.num_images = ARRAY_SIZE(fw_images),
.images = fw_images,
};
-
#endif /* EFI_HAVE_CAPSULE_SUPPORT */
static struct mm_region sc2a11_mem_map[] = {
@@ -145,13 +124,27 @@
{
struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
struct draminfo_entry *ent = synquacer_draminfo->entry;
+ unsigned long size = 0;
+ int i;
- gd->ram_size = ent[0].size;
+ for (i = 0; i < synquacer_draminfo->nr_regions; i++)
+ size += ent[i].size;
+
+ gd->ram_size = size;
gd->ram_base = ent[0].base;
return 0;
}
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
+{
+ struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
+ struct draminfo_entry *ent = synquacer_draminfo->entry;
+
+ return ent[synquacer_draminfo->nr_regions - 1].base +
+ ent[synquacer_draminfo->nr_regions - 1].size;
+}
+
int dram_init_banksize(void)
{
struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c
index aaeeee3..4483bd7 100644
--- a/board/softing/vining_2000/vining_2000.c
+++ b/board/softing/vining_2000/vining_2000.c
@@ -19,6 +19,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/sections.h>
#include <env.h>
#include <linux/bitops.h>
#include <linux/delay.h>
diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
index 6edb422..6fa2fe5 100644
--- a/board/solidrun/clearfog/clearfog.c
+++ b/board/solidrun/clearfog/clearfog.c
@@ -36,7 +36,7 @@
#define BOARD_GPP_POL_LOW 0x0
#define BOARD_GPP_POL_MID 0x0
-static struct tlv_data cf_tlv_data;
+static struct tlv_data cf_tlv_data = { 0 };
static void cf_read_tlv_data(void)
{
@@ -159,6 +159,9 @@
cf_read_tlv_data();
switch (cf_tlv_data.ram_size) {
+ case 2:
+ ifp->memory_size = MV_DDR_DIE_CAP_2GBIT;
+ break;
case 4:
default:
ifp->memory_size = MV_DDR_DIE_CAP_4GBIT;
@@ -168,6 +171,18 @@
break;
}
+ switch (cf_tlv_data.ram_channels) {
+ default:
+ case 1:
+ for (uint8_t i = 0; i < 5; i++)
+ ifp->as_bus_params[i].cs_bitmask = 0x1;
+ break;
+ case 2:
+ for (uint8_t i = 0; i < 5; i++)
+ ifp->as_bus_params[i].cs_bitmask = 0x3;
+ break;
+ }
+
/* Return the board topology as defined in the board code */
return &board_topology_map;
}
diff --git a/board/solidrun/common/tlv_data.c b/board/solidrun/common/tlv_data.c
index 11d6e4a..cf58248 100644
--- a/board/solidrun/common/tlv_data.c
+++ b/board/solidrun/common/tlv_data.c
@@ -45,9 +45,14 @@
if (val[4] != SR_TLV_CODE_RAM_SIZE)
return;
- if (tlv_entry->length != 6)
+ if (tlv_entry->length < 6)
return;
td->ram_size = val[5];
+
+ /* extension with additional data field for number of ddr channels */
+ if (tlv_entry->length >= 7) {
+ td->ram_channels = val[6];
+ }
}
static void parse_tlv_data(u8 *eeprom, struct tlvinfo_header *hdr,
diff --git a/board/solidrun/common/tlv_data.h b/board/solidrun/common/tlv_data.h
index a1432e4..be3f782 100644
--- a/board/solidrun/common/tlv_data.h
+++ b/board/solidrun/common/tlv_data.h
@@ -10,6 +10,7 @@
/* Store product name of both SOM and carrier */
char tlv_product_name[2][32];
unsigned int ram_size;
+ uint8_t ram_channels;
};
void read_tlv_data(struct tlv_data *td);
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 6fa5cf4..e119330 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -32,6 +32,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/sata.h>
#include <asm/mach-imx/video.h>
+#include <asm/sections.h>
#include <mmc.h>
#include <fsl_esdhc_imx.h>
#include <malloc.h>
diff --git a/board/st/common/Makefile b/board/st/common/Makefile
index c960829..b01245e 100644
--- a/board/st/common/Makefile
+++ b/board/st/common/Makefile
@@ -8,6 +8,7 @@
ifeq ($(CONFIG_ARCH_STM32MP),y)
obj-$(CONFIG_SET_DFU_ALT_INFO) += stm32mp_dfu.o
+obj-$(CONFIG_$(SPL_)DFU_VIRT) += stm32mp_dfu_virt.o
endif
obj-$(CONFIG_TYPEC_STUSB160X) += stusb160x.o
diff --git a/board/st/common/stm32mp_dfu.c b/board/st/common/stm32mp_dfu.c
index 1cf4a3d..a8eb8d5 100644
--- a/board/st/common/stm32mp_dfu.c
+++ b/board/st/common/stm32mp_dfu.c
@@ -14,6 +14,7 @@
#include <mtd.h>
#include <mtd_node.h>
#include <asm/arch/stm32prog.h>
+#include <linux/printk.h>
#define DFU_ALT_BUF_LEN SZ_1K
@@ -147,108 +148,14 @@
board_get_alt_info_mtd(mtd, buf);
}
- if (IS_ENABLED(CONFIG_DFU_VIRT) &&
- IS_ENABLED(CMD_STM32PROG_USB)) {
- strncat(buf, "&virt 0=OTP", DFU_ALT_BUF_LEN);
+ if (IS_ENABLED(CONFIG_DFU_VIRT)) {
+ /* virtual device id 0 is aligned with stm32mp_dfu_virt.c */
+ strlcat(buf, "&virt 0=OTP", DFU_ALT_BUF_LEN);
if (IS_ENABLED(CONFIG_PMIC_STPMIC1))
- strncat(buf, "&virt 1=PMIC", DFU_ALT_BUF_LEN);
+ strlcat(buf, "&virt 1=PMIC", DFU_ALT_BUF_LEN);
}
env_set("dfu_alt_info", buf);
puts("DFU alt info setting: done\n");
}
-
-#if CONFIG_IS_ENABLED(DFU_VIRT)
-#include <dfu.h>
-#include <power/stpmic1.h>
-
-static int dfu_otp_read(u64 offset, u8 *buffer, long *size)
-{
- struct udevice *dev;
- int ret;
-
- ret = uclass_get_device_by_driver(UCLASS_MISC,
- DM_DRIVER_GET(stm32mp_bsec),
- &dev);
- if (ret)
- return ret;
-
- ret = misc_read(dev, offset + STM32_BSEC_OTP_OFFSET, buffer, *size);
- if (ret >= 0) {
- *size = ret;
- ret = 0;
- }
-
- return 0;
-}
-
-static int dfu_pmic_read(u64 offset, u8 *buffer, long *size)
-{
- int ret;
-#ifdef CONFIG_PMIC_STPMIC1
- struct udevice *dev;
-
- ret = uclass_get_device_by_driver(UCLASS_MISC,
- DM_DRIVER_GET(stpmic1_nvm),
- &dev);
- if (ret)
- return ret;
-
- ret = misc_read(dev, 0xF8 + offset, buffer, *size);
- if (ret >= 0) {
- *size = ret;
- ret = 0;
- }
- if (ret == -EACCES) {
- *size = 0;
- ret = 0;
- }
-#else
- log_err("PMIC update not supported");
- ret = -EOPNOTSUPP;
-#endif
-
- return ret;
-}
-
-int dfu_read_medium_virt(struct dfu_entity *dfu, u64 offset,
- void *buf, long *len)
-{
- switch (dfu->data.virt.dev_num) {
- case 0x0:
- return dfu_otp_read(offset, buf, len);
- case 0x1:
- return dfu_pmic_read(offset, buf, len);
- }
-
- if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
- dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
- return stm32prog_read_medium_virt(dfu, offset, buf, len);
-
- *len = 0;
- return 0;
-}
-
-int dfu_write_medium_virt(struct dfu_entity *dfu, u64 offset,
- void *buf, long *len)
-{
- if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
- dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
- return stm32prog_write_medium_virt(dfu, offset, buf, len);
-
- return -EOPNOTSUPP;
-}
-
-int __weak dfu_get_medium_size_virt(struct dfu_entity *dfu, u64 *size)
-{
- if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
- dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
- return stm32prog_get_medium_size_virt(dfu, size);
-
- *size = SZ_1K;
-
- return 0;
-}
-
-#endif
diff --git a/board/st/common/stm32mp_dfu_virt.c b/board/st/common/stm32mp_dfu_virt.c
new file mode 100644
index 0000000..f0f9960
--- /dev/null
+++ b/board/st/common/stm32mp_dfu_virt.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <dfu.h>
+#include <dm.h>
+#include <misc.h>
+#include <asm/arch/stm32prog.h>
+#include <power/stpmic1.h>
+
+static int dfu_otp_read(u64 offset, u8 *buffer, long *size)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(stm32mp_bsec),
+ &dev);
+ if (ret)
+ return ret;
+
+ ret = misc_read(dev, offset + STM32_BSEC_OTP_OFFSET, buffer, *size);
+ if (ret >= 0) {
+ *size = ret;
+ ret = 0;
+ }
+
+ return 0;
+}
+
+static int dfu_pmic_read(u64 offset, u8 *buffer, long *size)
+{
+ int ret;
+ struct udevice *dev;
+
+ if (!IS_ENABLED(CONFIG_PMIC_STPMIC1)) {
+ log_err("PMIC update not supported");
+ return -EOPNOTSUPP;
+ }
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(stpmic1_nvm),
+ &dev);
+ if (ret)
+ return ret;
+
+ ret = misc_read(dev, 0xF8 + offset, buffer, *size);
+ if (ret >= 0) {
+ *size = ret;
+ ret = 0;
+ }
+ if (ret == -EACCES) {
+ *size = 0;
+ ret = 0;
+ }
+
+ return ret;
+}
+
+int dfu_read_medium_virt(struct dfu_entity *dfu, u64 offset,
+ void *buf, long *len)
+{
+ switch (dfu->data.virt.dev_num) {
+ case 0x0:
+ return dfu_otp_read(offset, buf, len);
+ case 0x1:
+ return dfu_pmic_read(offset, buf, len);
+ }
+
+ if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
+ dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
+ return stm32prog_read_medium_virt(dfu, offset, buf, len);
+
+ *len = 0;
+ return 0;
+}
+
+int dfu_write_medium_virt(struct dfu_entity *dfu, u64 offset,
+ void *buf, long *len)
+{
+ if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
+ dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
+ return stm32prog_write_medium_virt(dfu, offset, buf, len);
+
+ return -EOPNOTSUPP;
+}
+
+int dfu_get_medium_size_virt(struct dfu_entity *dfu, u64 *size)
+{
+ if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
+ dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
+ return stm32prog_get_medium_size_virt(dfu, size);
+
+ *size = SZ_1K;
+
+ return 0;
+}
diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c
index cd3a7dc..e21cbc2 100644
--- a/board/st/stih410-b2260/board.c
+++ b/board/st/stih410-b2260/board.c
@@ -50,9 +50,9 @@
.index = 0,
};
-int usb_gadget_handle_interrupts(int index)
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
{
- dwc3_uboot_handle_interrupt(index);
+ dwc3_uboot_handle_interrupt(dev);
return 0;
}
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
index 4cfb29e..0f96660 100644
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -14,7 +14,6 @@
#include <serial.h>
#include <spl.h>
#include <splash.h>
-#include <st_logo_data.h>
#include <video.h>
#include <asm/global_data.h>
#include <asm/io.h>
@@ -134,10 +133,5 @@
}
#endif
-#if defined(CONFIG_CMD_BMP)
- bmp_display((ulong)stmicroelectronics_uboot_logo_8bit_rle,
- BMP_ALIGN_CENTER, BMP_ALIGN_CENTER);
-#endif /* CONFIG_CMD_BMP */
-
return 0;
}
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index 3205a31..8f5719c 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -44,6 +44,7 @@
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/iopoll.h>
+#include <linux/printk.h>
#include <power/regulator.h>
#include <usb/dwc2_udc.h>
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index 7acd399..336f0cd 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <asm/arch/eeprom.h>
+#include <asm/arch/gpio.h>
#include <asm/arch/regs.h>
#include <asm/arch/spl.h>
#include <asm/io.h>
@@ -172,10 +173,32 @@
/* Update the memory size which read form eeprom or DT */
fdt_fixup_memory(spl_image->fdt_addr, 0x40000000, gd->ram_size);
}
+
+static void jh7110_jtag_init(void)
+{
+ /* nTRST: GPIO36 */
+ SYS_IOMUX_DOEN(36, HIGH);
+ SYS_IOMUX_DIN(36, 4);
+ /* TDI: GPIO61 */
+ SYS_IOMUX_DOEN(61, HIGH);
+ SYS_IOMUX_DIN(61, 19);
+ /* TMS: GPIO63 */
+ SYS_IOMUX_DOEN(63, HIGH);
+ SYS_IOMUX_DIN(63, 20);
+ /* TCK: GPIO60 */
+ SYS_IOMUX_DOEN(60, HIGH);
+ SYS_IOMUX_DIN(60, 29);
+ /* TDO: GPIO44 */
+ SYS_IOMUX_DOEN(44, 8);
+ SYS_IOMUX_DOUT(44, 22);
+}
+
int spl_board_init_f(void)
{
int ret;
+ jh7110_jtag_init();
+
ret = spl_soc_init();
if (ret) {
debug("JH7110 SPL init failed: %d\n", ret);
@@ -218,7 +241,7 @@
if (ret)
panic("spl_early_init() failed: %d\n", ret);
- riscv_cpu_setup(NULL, NULL);
+ riscv_cpu_setup();
preloader_console_init();
/* Set the parent clock of cpu_root clock to pll0,
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c
index 19b7b44..78e118d 100644
--- a/board/starfive/visionfive2/starfive_visionfive2.c
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -90,7 +90,7 @@
return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
}
- return (ulong *)&_end;
+ return (ulong *)_end;
}
int ft_board_setup(void *blob, struct bd_info *bd)
diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
index c334d98..c36de1a 100644
--- a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
+++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
@@ -190,6 +190,7 @@
pbuf.eeprom.atom4.data.mac1_addr[4], pbuf.eeprom.atom4.data.mac1_addr[5]);
} else {
printf("Custom data v%d is not Supported\n", pbuf.eeprom.atom4.data.version);
+ dump_raw_eeprom();
}
printf("--------EEPROM INFO--------\n\n");
}
@@ -404,29 +405,6 @@
update_crc();
}
-static int print_usage(void)
-{
- printf("display and program the system ID and MAC addresses in EEPROM\n"
- "[read_eeprom|initialize|write_eeprom|mac_address|pcb_revision|bom_revision|product_id]\n"
- "mac read_eeprom\n"
- " - read EEPROM content into memory data structure\n"
- "mac write_eeprom\n"
- " - save memory data structure to the EEPROM\n"
- "mac initialize\n"
- " - initialize the in-memory EEPROM copy with default data\n"
- "mac mac0_address <xx:xx:xx:xx:xx:xx>\n"
- " - stores a MAC0 address into the local EEPROM copy\n"
- "mac mac1_address <xx:xx:xx:xx:xx:xx>\n"
- " - stores a MAC1 address into the local EEPROM copy\n"
- "mac pcb_revision <?>\n"
- " - stores a StarFive PCB revision into the local EEPROM copy\n"
- "mac bom_revision <A>\n"
- " - stores a StarFive BOM revision into the local EEPROM copy\n"
- "mac product_id <VF7110A1-2228-D008E000-xxxxxxxx>\n"
- " - stores a StarFive product ID into the local EEPROM copy\n");
- return 0;
-}
-
int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
char *cmd;
@@ -437,7 +415,7 @@
}
if (argc > 3)
- return print_usage();
+ return CMD_RET_USAGE;
cmd = argv[1];
@@ -450,10 +428,13 @@
return 0;
} else if (!strcmp(cmd, "write_eeprom")) {
return prog_eeprom(STARFIVE_EEPROM_HATS_SIZE_MAX);
+ } else if (!strcmp(cmd, "raw")) {
+ dump_raw_eeprom();
+ return 0;
}
if (argc != 3)
- return print_usage();
+ return CMD_RET_USAGE;
if (is_match_magic()) {
printf("Please read the EEPROM ('read_eeprom') and/or initialize the EEPROM ('initialize') first.\n");
@@ -477,7 +458,7 @@
return 0;
}
- return print_usage();
+ return CMD_RET_USAGE;
}
/**
@@ -559,3 +540,30 @@
return hextoul(&pbuf.eeprom.atom1.data.pstr[14], NULL);
}
+
+U_BOOT_LONGHELP(mac,
+ "\n"
+ " - display EEPROM content\n"
+ "mac read_eeprom\n"
+ " - read EEPROM content into memory data structure\n"
+ "mac write_eeprom\n"
+ " - save memory data structure to the EEPROM\n"
+ "mac initialize\n"
+ " - initialize the in-memory EEPROM copy with default data\n"
+ "mac raw\n"
+ " - hexdump memory data structure\n"
+ "mac mac0_address <xx:xx:xx:xx:xx:xx>\n"
+ " - stores a MAC0 address into the local EEPROM copy\n"
+ "mac mac1_address <xx:xx:xx:xx:xx:xx>\n"
+ " - stores a MAC1 address into the local EEPROM copy\n"
+ "mac pcb_revision <?>\n"
+ " - stores a StarFive PCB revision into the local EEPROM copy\n"
+ "mac bom_revision <A>\n"
+ " - stores a StarFive BOM revision into the local EEPROM copy\n"
+ "mac product_id <VF7110A1-2228-D008E000-xxxxxxxx>\n"
+ " - stores a StarFive product ID into the local EEPROM copy\n");
+
+U_BOOT_CMD(
+ mac, 3, 1, do_mac,
+ "display and program the board revision and MAC address in EEPROM",
+ mac_help_text);
diff --git a/board/storopack/smegw01/smegw01.c b/board/storopack/smegw01/smegw01.c
index 7b2c50a..345191b 100644
--- a/board/storopack/smegw01/smegw01.c
+++ b/board/storopack/smegw01/smegw01.c
@@ -111,18 +111,3 @@
return part;
}
-enum env_location env_get_location(enum env_operation op, int prio)
-{
- if (op == ENVOP_SAVE || op == ENVOP_ERASE)
- return ENVL_MMC;
-
- switch (prio) {
- case 0:
- return ENVL_NOWHERE;
-
- case 1:
- return ENVL_MMC;
- }
-
- return ENVL_UNKNOWN;
-}
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 98bbd2d..f556857 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -236,6 +236,11 @@
S: Maintained
F: configs/icnova-a20-swac_defconfig
+ICnova-A20-ADB4006 BOARD
+M: Ludwig Kormann <ludwig.kormann@ict42.de>
+S: Maintained
+F: configs/icnova-a20-adb4006_defconfig
+
ITEAD IBOX BOARD
M: Marcus Cooper <codekipper@gmail.com>
S: Maintained
@@ -291,6 +296,11 @@
S: Maintained
F: configs/Marsboard_A10_defconfig
+MANGOPI MQ-R BOARD
+M: Andre Przywara <andre.przywara@arm.com>
+S: Maintained
+F: configs/mangopi_mq_r_defconfig
+
MELE I7 BOARD
M: Marcus Cooper <codekipper@gmail.com>
S: Maintained
@@ -445,6 +455,11 @@
S: Maintained
F: configs/orangepi_zero2_defconfig
+ORANGEPI ZERO 3 BOARD
+M: Andre Przywara <andre.przywara@arm.com>
+S: Maintained
+F: configs/orangepi_zero3_defconfig
+
ORANGEPI PC 2 BOARD
M: Andre Przywara <andre.przywara@arm.com>
S: Maintained
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index f321cd5..8c12c8d 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -33,11 +33,13 @@
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <linux/delay.h>
-#include <u-boot/crc.h>
+#include <linux/printk.h>
+#include <linux/types.h>
#ifndef CONFIG_ARM64
#include <asm/armv7.h>
#endif
#include <asm/gpio.h>
+#include <sunxi_gpio.h>
#include <asm/io.h>
#include <u-boot/crc.h>
#include <env_internal.h>
@@ -187,7 +189,7 @@
/* add board specific code here */
int board_init(void)
{
- __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
+ __maybe_unused int id_pfr1, ret;
gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
@@ -224,29 +226,6 @@
if (ret)
return ret;
- /* strcmp() would look better, but doesn't get optimised away. */
- if (CONFIG_SATAPWR[0]) {
- satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
- if (satapwr_pin >= 0) {
- gpio_request(satapwr_pin, "satapwr");
- gpio_direction_output(satapwr_pin, 1);
-
- /*
- * Give the attached SATA device time to power-up
- * to avoid link timeouts
- */
- mdelay(500);
- }
- }
-
- if (CONFIG_MACPWR[0]) {
- macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
- if (macpwr_pin >= 0) {
- gpio_request(macpwr_pin, "macpwr");
- gpio_direction_output(macpwr_pin, 1);
- }
- }
-
#if CONFIG_IS_ENABLED(DM_I2C)
/*
* Temporary workaround for enabling I2C clocks until proper sunxi DM
@@ -254,7 +233,6 @@
*/
i2c_init_board();
#endif
-
eth_init_board();
return 0;
@@ -482,6 +460,13 @@
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}
+#elif defined(CONFIG_MACH_SUN8I_R528)
+ /* SDC2: PC2-PC7 */
+ for (pin = SUNXI_GPC(2); pin <= SUNXI_GPC(7); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
#else
puts("ERROR: No pinmux setup defined for MMC2!\n");
#endif
@@ -584,7 +569,8 @@
#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
defined CONFIG_AXP221_POWER || defined CONFIG_AXP305_POWER || \
- defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
+ defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER || \
+ defined CONFIG_AXP313_POWER
power_failed = axp_init();
if (IS_ENABLED(CONFIG_AXP_DISABLE_BOOT_ON_POWERON) && !power_failed) {
@@ -597,50 +583,46 @@
}
}
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
- defined CONFIG_AXP818_POWER
+#ifdef CONFIG_AXP_DCDC1_VOLT
power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
+ power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
#endif
-#if !defined(CONFIG_AXP305_POWER)
+#ifdef CONFIG_AXP_DCDC2_VOLT
power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
#endif
-#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
+#ifdef CONFIG_AXP_DCDC4_VOLT
power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
#endif
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
- defined CONFIG_AXP818_POWER
- power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
-#endif
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
- defined CONFIG_AXP818_POWER
+#ifdef CONFIG_AXP_ALDO1_VOLT
power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
#endif
-#if !defined(CONFIG_AXP305_POWER)
+#ifdef CONFIG_AXP_ALDO2_VOLT
power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
#endif
-#if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP305_POWER)
+#ifdef CONFIG_AXP_ALDO3_VOLT
power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
#endif
-#ifdef CONFIG_AXP209_POWER
+#ifdef CONFIG_AXP_ALDO4_VOLT
power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
#endif
-#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
- defined(CONFIG_AXP818_POWER)
+#ifdef CONFIG_AXP_DLDO1_VOLT
power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
-#if !defined CONFIG_AXP809_POWER
+#endif
+#ifdef CONFIG_AXP_DLDO3_VOLT
power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
#endif
+#ifdef CONFIG_AXP_ELDO1_VOLT
power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
#endif
-#ifdef CONFIG_AXP818_POWER
+#ifdef CONFIG_AXP_FLDO1_VOLT
power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
@@ -649,7 +631,7 @@
#if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
#endif
-#endif
+#endif /* CONFIG_AXPxxx_POWER */
printf("DRAM:");
gd->ram_size = sunxi_dram_init();
printf(" %d MiB\n", (int)(gd->ram_size >> 20));
@@ -957,7 +939,7 @@
#ifdef CONFIG_PINE64_DT_SELECTION
if (strstr(best_dt_name, "-pine64-plus")) {
/* Differentiate the Pine A64 boards by their DRAM size. */
- if ((gd->ram_size == 512 * 1024 * 1024))
+ if (gd->ram_size == SZ_512M)
best_dt_name = "sun50i-a64-pine64";
}
#endif
diff --git a/board/sunxi/chip.c b/board/sunxi/chip.c
index cde04be..eeee631 100644
--- a/board/sunxi/chip.c
+++ b/board/sunxi/chip.c
@@ -12,7 +12,7 @@
#include <w1-eeprom.h>
#include <dm/device-internal.h>
-#include <asm/arch/gpio.h>
+#include <sunxi_gpio.h>
#include <extension_board.h>
diff --git a/board/synopsys/axs10x/axs10x.c b/board/synopsys/axs10x/axs10x.c
index 75e4d03..95297a1 100644
--- a/board/synopsys/axs10x/axs10x.c
+++ b/board/synopsys/axs10x/axs10x.c
@@ -3,7 +3,6 @@
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
*/
-#include <common.h>
#include <cpu_func.h>
#include <dwmmc.h>
#include <init.h>
diff --git a/board/synopsys/emsdp/emsdp.c b/board/synopsys/emsdp/emsdp.c
index a3cee23..adec7d3 100644
--- a/board/synopsys/emsdp/emsdp.c
+++ b/board/synopsys/emsdp/emsdp.c
@@ -3,7 +3,6 @@
* Copyright (C) 2018 Synopsys, Inc. All rights reserved.
*/
-#include <common.h>
#include <command.h>
#include <cpu_func.h>
#include <dwmmc.h>
diff --git a/board/synopsys/hsdk/clk-lib.c b/board/synopsys/hsdk/clk-lib.c
index bd43179..be76d6c 100644
--- a/board/synopsys/hsdk/clk-lib.c
+++ b/board/synopsys/hsdk/clk-lib.c
@@ -8,6 +8,7 @@
#include <log.h>
#include <malloc.h>
#include <dm/device.h>
+#include <linux/printk.h>
#include "clk-lib.h"
diff --git a/board/synopsys/hsdk/clk-lib.h b/board/synopsys/hsdk/clk-lib.h
index 970bcd4..e1140a1 100644
--- a/board/synopsys/hsdk/clk-lib.h
+++ b/board/synopsys/hsdk/clk-lib.h
@@ -7,7 +7,6 @@
#ifndef __BOARD_CLK_LIB_H
#define __BOARD_CLK_LIB_H
-#include <common.h>
#include <linux/bitops.h>
enum clk_ctl_ops {
diff --git a/board/synopsys/hsdk/env-lib.c b/board/synopsys/hsdk/env-lib.c
index fd54ac7..85a2249 100644
--- a/board/synopsys/hsdk/env-lib.c
+++ b/board/synopsys/hsdk/env-lib.c
@@ -7,6 +7,9 @@
#include "env-lib.h"
#include <env.h>
#include <log.h>
+#include <vsprintf.h>
+#include <linux/errno.h>
+#include <linux/printk.h>
#define MAX_CMD_LEN 25
diff --git a/board/synopsys/hsdk/env-lib.h b/board/synopsys/hsdk/env-lib.h
index 48c17c4..cabca1d 100644
--- a/board/synopsys/hsdk/env-lib.h
+++ b/board/synopsys/hsdk/env-lib.h
@@ -7,7 +7,6 @@
#ifndef __BOARD_ENV_LIB_H
#define __BOARD_ENV_LIB_H
-#include <common.h>
#include <config.h>
#include <linux/kernel.h>
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 6cbc89a..8eb10f2 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -4,7 +4,6 @@
* Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
*/
-#include <common.h>
#include <command.h>
#include <config.h>
#include <cpu_func.h>
diff --git a/board/synopsys/iot_devkit/iot_devkit.c b/board/synopsys/iot_devkit/iot_devkit.c
index 650958f..dec49e3 100644
--- a/board/synopsys/iot_devkit/iot_devkit.c
+++ b/board/synopsys/iot_devkit/iot_devkit.c
@@ -3,7 +3,6 @@
* Copyright (C) 2018 Synopsys, Inc. All rights reserved.
*/
-#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <malloc.h>
diff --git a/board/synopsys/nsim/nsim.c b/board/synopsys/nsim/nsim.c
index 00e5cc3..5953b36 100644
--- a/board/synopsys/nsim/nsim.c
+++ b/board/synopsys/nsim/nsim.c
@@ -3,7 +3,6 @@
* Copyright (C) 2020 Synopsys, Inc. All rights reserved.
*/
-#include <common.h>
#include <init.h>
#include <dm/device.h>
#include <virtio_types.h>
diff --git a/board/tcl/sl50/board.c b/board/tcl/sl50/board.c
index 839a692..3f7d42f 100644
--- a/board/tcl/sl50/board.c
+++ b/board/tcl/sl50/board.c
@@ -4,7 +4,7 @@
*
* Board functions for TCL SL50 board
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/tcl/sl50/board.h b/board/tcl/sl50/board.h
index b8b9ed7..e624677 100644
--- a/board/tcl/sl50/board.h
+++ b/board/tcl/sl50/board.h
@@ -4,7 +4,7 @@
*
* TCL SL50 boards information header
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _BOARD_H_
diff --git a/board/tcl/sl50/mux.c b/board/tcl/sl50/mux.c
index b0a1dad..ab90881 100644
--- a/board/tcl/sl50/mux.c
+++ b/board/tcl/sl50/mux.c
@@ -2,7 +2,7 @@
/*
* mux.c
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/technexion/pico-imx6ul/spl.c b/board/technexion/pico-imx6ul/spl.c
index 251f5a1..ff56fd8 100644
--- a/board/technexion/pico-imx6ul/spl.c
+++ b/board/technexion/pico-imx6ul/spl.c
@@ -14,6 +14,7 @@
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
+#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#include <linux/libfdt.h>
#include <spl.h>
diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c
index f86fee9..c6b21aa 100644
--- a/board/technexion/pico-imx7d/spl.c
+++ b/board/technexion/pico-imx7d/spl.c
@@ -16,6 +16,7 @@
#include <asm/arch-mx7/mx7-ddr.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/gpio.h>
+#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#include <spl.h>
diff --git a/board/technexion/pico-imx8mq/spl.c b/board/technexion/pico-imx8mq/spl.c
index 2afb4d3..1a9c799 100644
--- a/board/technexion/pico-imx8mq/spl.c
+++ b/board/technexion/pico-imx8mq/spl.c
@@ -16,6 +16,7 @@
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/sections.h>
#include <linux/delay.h>
#include <errno.h>
#include <fsl_esdhc_imx.h>
diff --git a/board/terasic/de0-nano-soc/Makefile b/board/terasic/de0-nano-soc/Makefile
deleted file mode 100644
index e1c8a6b..0000000
--- a/board/terasic/de0-nano-soc/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
-
-obj-y := socfpga.o
diff --git a/board/terasic/de0-nano-soc/socfpga.c b/board/terasic/de0-nano-soc/socfpga.c
deleted file mode 100644
index 48bfe32..0000000
--- a/board/terasic/de0-nano-soc/socfpga.c
+++ /dev/null
@@ -1,5 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- */
-#include <common.h>
diff --git a/board/terasic/de10-nano/Makefile b/board/terasic/de10-nano/Makefile
deleted file mode 100644
index 2cf9240..0000000
--- a/board/terasic/de10-nano/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-# Copyright (C) 2017, Intel Corporation
-#
-#
-
-obj-y := socfpga.o
diff --git a/board/terasic/de10-nano/socfpga.c b/board/terasic/de10-nano/socfpga.c
deleted file mode 100644
index f9173f1..0000000
--- a/board/terasic/de10-nano/socfpga.c
+++ /dev/null
@@ -1,5 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017, Intel Corporation
- */
-#include <common.h>
diff --git a/board/terasic/de10-standard/Makefile b/board/terasic/de10-standard/Makefile
deleted file mode 100644
index 2cf9240..0000000
--- a/board/terasic/de10-standard/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-# Copyright (C) 2017, Intel Corporation
-#
-#
-
-obj-y := socfpga.o
diff --git a/board/terasic/de10-standard/socfpga.c b/board/terasic/de10-standard/socfpga.c
deleted file mode 100644
index f9173f1..0000000
--- a/board/terasic/de10-standard/socfpga.c
+++ /dev/null
@@ -1,5 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017, Intel Corporation
- */
-#include <common.h>
diff --git a/board/terasic/sockit/Makefile b/board/terasic/sockit/Makefile
deleted file mode 100644
index e1c8a6b..0000000
--- a/board/terasic/sockit/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
-
-obj-y := socfpga.o
diff --git a/board/terasic/sockit/socfpga.c b/board/terasic/sockit/socfpga.c
deleted file mode 100644
index 48bfe32..0000000
--- a/board/terasic/sockit/socfpga.c
+++ /dev/null
@@ -1,5 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- */
-#include <common.h>
diff --git a/board/theobroma-systems/lion_rk3368/Makefile b/board/theobroma-systems/lion_rk3368/Makefile
deleted file mode 100644
index fc8df27..0000000
--- a/board/theobroma-systems/lion_rk3368/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
-
-obj-y += lion_rk3368.o
diff --git a/board/theobroma-systems/lion_rk3368/lion_rk3368.c b/board/theobroma-systems/lion_rk3368/lion_rk3368.c
deleted file mode 100644
index 1b0d504..0000000
--- a/board/theobroma-systems/lion_rk3368/lion_rk3368.c
+++ /dev/null
@@ -1,4 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
- */
diff --git a/board/theobroma-systems/ringneck_px30/ringneck-px30.c b/board/theobroma-systems/ringneck_px30/ringneck-px30.c
index bb1bb4a..537ce0d 100644
--- a/board/theobroma-systems/ringneck_px30/ringneck-px30.c
+++ b/board/theobroma-systems/ringneck_px30/ringneck-px30.c
@@ -16,12 +16,14 @@
#include <usb.h>
#include <dm/pinctrl.h>
#include <dm/uclass-internal.h>
+#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/setup.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/periph.h>
#include <asm/arch-rockchip/misc.h>
+#include <linux/delay.h>
#include <power/regulator.h>
#include <u-boot/sha256.h>
@@ -169,3 +171,54 @@
return 0;
}
+
+#define STM32_RST 100 /* GPIO3_A4 */
+#define STM32_BOOT 101 /* GPIO3_A5 */
+
+void spl_board_init(void)
+{
+ /*
+ * Glitches on STM32_BOOT and STM32_RST lines during poweroff or power
+ * on may put the STM32 companion microcontroller into DFU mode, let's
+ * always reset it into normal mode instead.
+ * Toggling the STM32_RST line is safe to do with the ATtiny companion
+ * microcontroller variant because it will not trigger an MCU reset
+ * since only a UPDI reset command will. Since a UPDI reset is difficult
+ * to mistakenly trigger, glitches to the lines are theoretically also
+ * incapable of triggering an actual ATtiny reset.
+ */
+ int ret;
+
+ ret = gpio_request(STM32_RST, "STM32_RST");
+ if (ret) {
+ debug("Failed to request STM32_RST\n");
+ return;
+ }
+
+ ret = gpio_request(STM32_BOOT, "STM32_BOOT");
+ if (ret) {
+ debug("Failed to request STM32_BOOT\n");
+ return;
+ }
+
+ /* Rely on HW pull-down for inactive level */
+ ret = gpio_direction_input(STM32_BOOT);
+ if (ret) {
+ debug("Failed to configure STM32_BOOT as input\n");
+ return;
+ }
+
+ ret = gpio_direction_output(STM32_RST, 0);
+ if (ret) {
+ debug("Failed to configure STM32_RST as output low\n");
+ return;
+ }
+
+ mdelay(1);
+
+ ret = gpio_direction_output(STM32_RST, 1);
+ if (ret) {
+ debug("Failed to configure STM32_RST as output high\n");
+ return;
+ }
+}
diff --git a/board/ti/am335x/Makefile b/board/ti/am335x/Makefile
index 3ccf66b..2b1e21a 100644
--- a/board/ti/am335x/Makefile
+++ b/board/ti/am335x/Makefile
@@ -2,7 +2,7 @@
#
# Makefile
#
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index ecb9fa0..34f987c 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -4,7 +4,7 @@
*
* Board functions for TI AM335X based boards
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h
index c296211..1284c16 100644
--- a/board/ti/am335x/board.h
+++ b/board/ti/am335x/board.h
@@ -4,7 +4,7 @@
*
* TI AM335x boards information header
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _BOARD_H_
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index 7d31ade..0bad154 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -1,7 +1,7 @@
/*
* mux.c
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/board/ti/am43xx/Makefile b/board/ti/am43xx/Makefile
index 8dc1d89..b618f63 100644
--- a/board/ti/am43xx/Makefile
+++ b/board/ti/am43xx/Makefile
@@ -2,7 +2,7 @@
#
# Makefile
#
-# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 87e552a..ea0d0b9 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -4,7 +4,7 @@
*
* Board functions for TI AM43XX based boards
*
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
@@ -760,13 +760,13 @@
.index = 1,
};
-int usb_gadget_handle_interrupts(int index)
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
{
u32 status;
- status = dwc3_omap_uboot_interrupt_status(index);
+ status = dwc3_omap_uboot_interrupt_status(dev);
if (status)
- dwc3_uboot_handle_interrupt(index);
+ dwc3_uboot_handle_interrupt(dev);
return 0;
}
diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h
index 06b7374..37a169a 100644
--- a/board/ti/am43xx/board.h
+++ b/board/ti/am43xx/board.h
@@ -5,7 +5,7 @@
* TI AM437x boards information header
* Derived from AM335x board.
*
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _BOARD_H_
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index f59e93a..463f1cc 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -2,7 +2,7 @@
/*
* mux.c
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 9ea507a..b004a89 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com
*
* Author: Felipe Balbi <balbi@ti.com>
*
diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h
index 54b7050..f2f428e 100644
--- a/board/ti/am57xx/mux_data.h
+++ b/board/ti/am57xx/mux_data.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com
*
* Author: Felipe Balbi <balbi@ti.com>
*
diff --git a/board/ti/am62ax/am62ax.env b/board/ti/am62ax/am62ax.env
index 3f7c333..bfed7f3 100644
--- a/board/ti/am62ax/am62ax.env
+++ b/board/ti/am62ax/am62ax.env
@@ -1,4 +1,4 @@
-#include <env/ti/ti_armv7_common.env>
+#include <env/ti/ti_common.env>
#include <env/ti/mmc.env>
default_device_tree=ti/k3-am62a7-sk.dtb
diff --git a/board/ti/am62x/MAINTAINERS b/board/ti/am62x/MAINTAINERS
index 105e741..6ac4e65 100644
--- a/board/ti/am62x/MAINTAINERS
+++ b/board/ti/am62x/MAINTAINERS
@@ -6,3 +6,10 @@
F: include/configs/am62x_evm.h
F: configs/am62x_evm_r5_defconfig
F: configs/am62x_evm_a53_defconfig
+
+BEAGLEPLAY BOARD
+M: Nishanth Menon <nm@ti.com>
+M: Robert Nelson <robertcnelson@gmail.com>
+M: Tom Rini <trini@konsulko.com>
+S: Maintained
+N: beagleplay
diff --git a/board/ti/am62x/am62x.env b/board/ti/am62x/am62x.env
index f2dc878..e53a55c 100644
--- a/board/ti/am62x/am62x.env
+++ b/board/ti/am62x/am62x.env
@@ -1,23 +1,21 @@
-#include <env/ti/ti_armv7_common.env>
+#include <env/ti/ti_common.env>
+#include <env/ti/default_findfdt.env>
#include <env/ti/mmc.env>
-default_device_tree=ti/k3-am625-sk.dtb
-findfdt=
- setenv name_fdt ${default_device_tree};
- setenv fdtfile ${name_fdt}
name_kern=Image
console=ttyS2,115200n8
args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000
${mtdparts}
run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+boot_targets=mmc1 mmc0 usb pxe dhcp
boot=mmc
mmcdev=1
bootpart=1:2
bootdir=/boot
rd_spec=-
-splashfile=ti.gz
+splashfile=ti_logo_414x97_32bpp.bmp.gz
splashimage=0x80200000
splashpos=m,m
splashsource=sf
diff --git a/board/ti/am62x/beagleplay.env b/board/ti/am62x/beagleplay.env
new file mode 100644
index 0000000..4f0a94a
--- /dev/null
+++ b/board/ti/am62x/beagleplay.env
@@ -0,0 +1,19 @@
+#include <env/ti/ti_common.env>
+#include <env/ti/default_findfdt.env>
+#include <env/ti/mmc.env>
+
+name_kern=Image
+console=ttyS2,115200n8
+args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000
+run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+set_led_state_fail_load= led led-0 off; led led-1 on;
+ led led-2 off; led led-3 on; led led-4 off
+set_led_state_start_load=led led-0 on; led led-1 off;
+ led led-2 on; led led-3 off; led led-4 on
+boot=mmc
+mmcdev=1
+bootpart=1:1
+bootdir=/boot
+boot_targets=mmc1 mmc0 usb pxe
+bootmeths=script extlinux efi pxe
+rd_spec=-
diff --git a/board/ti/am62x/beagleplay_a53.config b/board/ti/am62x/beagleplay_a53.config
new file mode 100644
index 0000000..f038041
--- /dev/null
+++ b/board/ti/am62x/beagleplay_a53.config
@@ -0,0 +1,55 @@
+# Defconfig fragment to apply on top of am62x_evm_a53_defconfig
+
+CONFIG_DEFAULT_DEVICE_TREE="k3-am625-beagleplay"
+CONFIG_OF_LIST="k3-am625-beagleplay"
+CONFIG_SPL_OF_LIST="k3-am625-beagleplay"
+CONFIG_BOOTCOMMAND="run set_led_state_start_load;run findfdt; run envboot; bootflow scan -lb;run set_led_state_fail_load"
+CONFIG_EXT4_WRITE=y
+CONFIG_LZO=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
+CONFIG_AUTOBOOT_DELAY_STR="d"
+CONFIG_AUTOBOOT_STOP_STR=" "
+# Use the Beagleplay env file
+CONFIG_ENV_SOURCE_FILE="beagleplay"
+# Do not use emmc boot - we will use FS only
+CONFIG_SUPPORT_EMMC_BOOT=n
+CONFIG_MMC_IO_VOLTAGE=y
+# CONFIG_SPL_MMC_IO_VOLTAGE is not set
+CONFIG_MMC_UHS_SUPPORT=y
+# CONFIG_SPL_MMC_UHS_SUPPORT is not set
+CONFIG_MMC_HS200_SUPPORT=y
+# CONFIG_SPL_MMC_HS200_SUPPORT is not set
+# Enable GPIO control
+CONFIG_DM_GPIO=y
+CONFIG_SPL_GPIO=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPIO_READ=y
+# Enable LEDs
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SPL_LED=y
+CONFIG_SPL_LED_GPIO=y
+# Enable I2C bus
+CONFIG_SPL_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_CMD_I2C=y
+# Regulator
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_REGULATOR_TPS65219=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_TPS65219=y
+CONFIG_CMD_PMIC=y
+# Uses Realtek phy rather than TI phy
+CONFIG_PHY_TI_DP83867=n
+CONFIG_PHY_REALTEK=y
+# No SPI flash on Beagleplay
+CONFIG_SPI=n
+CONFIG_SPI_FLASH=n
+CONFIG_SPL_DM_SPI_FLASH=n
+CONFIG_SPL_SPI_FLASH_SUPPORT=n
diff --git a/board/ti/am62x/beagleplay_r5.config b/board/ti/am62x/beagleplay_r5.config
new file mode 100644
index 0000000..4ee0375
--- /dev/null
+++ b/board/ti/am62x/beagleplay_r5.config
@@ -0,0 +1,15 @@
+# Defconfig fragment to apply on top of:
+# am62x_evm_r5_defconfig
+#
+CONFIG_DEFAULT_DEVICE_TREE="k3-am625-r5-beagleplay"
+CONFIG_OF_LIST="k3-am625-r5-beagleplay"
+CONFIG_SPL_OF_LIST="k3-am625-r5-beagleplay"
+# Do spl board init
+CONFIG_SPL_BOARD_INIT=y
+# Do not use emmc boot - we will use FS only
+CONFIG_SUPPORT_EMMC_BOOT=n
+# No SPI flash on Beagleplay
+CONFIG_SPI=n
+CONFIG_SPI_FLASH=n
+CONFIG_SPL_DM_SPI_FLASH=n
+CONFIG_SPL_SPI_FLASH_SUPPORT=n
diff --git a/board/ti/am64x/am64x.env b/board/ti/am64x/am64x.env
index 1567907..efd736b 100644
--- a/board/ti/am64x/am64x.env
+++ b/board/ti/am64x/am64x.env
@@ -1,4 +1,4 @@
-#include <env/ti/ti_armv7_common.env>
+#include <env/ti/ti_common.env>
#include <env/ti/mmc.env>
#include <env/ti/k3_dfu.env>
@@ -15,6 +15,7 @@
args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 ${mtdparts}
run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+boot_targets=mmc1 mmc0 usb pxe dhcp
boot=mmc
mmcdev=1
bootpart=1:2
diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c
index 96f4e30..a080b2b 100644
--- a/board/ti/am64x/evm.c
+++ b/board/ti/am64x/evm.c
@@ -18,7 +18,8 @@
#include "../common/board_detect.h"
-#define board_is_am64x_gpevm() board_ti_k3_is("AM64-GPEVM")
+#define board_is_am64x_gpevm() (board_ti_k3_is("AM64-GPEVM") || \
+ board_ti_k3_is("AM64-HSEVM"))
#define board_is_am64x_skevm() (board_ti_k3_is("AM64-SKEVM") || \
board_ti_k3_is("AM64B-SKEVM"))
diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig
index 5fd19d6..78c7040 100644
--- a/board/ti/am65x/Kconfig
+++ b/board/ti/am65x/Kconfig
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
# Lokesh Vutla <lokeshvutla@ti.com>
choice
diff --git a/board/ti/am65x/Makefile b/board/ti/am65x/Makefile
index 94dddfc..079a86d 100644
--- a/board/ti/am65x/Makefile
+++ b/board/ti/am65x/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
# Lokesh Vutla <lokeshvutla@ti.com>
#
# SPDX-License-Identifier: GPL-2.0+
diff --git a/board/ti/am65x/am65x.env b/board/ti/am65x/am65x.env
index 755bff2..286b9c3 100644
--- a/board/ti/am65x/am65x.env
+++ b/board/ti/am65x/am65x.env
@@ -1,4 +1,4 @@
-#include <env/ti/ti_armv7_common.env>
+#include <env/ti/ti_common.env>
#include <env/ti/mmc.env>
#include <env/ti/k3_dfu.env>
#if CONFIG_CMD_REMOTEPROC
diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index d52ac33..9de3dda 100644
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -2,7 +2,7 @@
/*
* Board specific initialization for AM654 EVM
*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*
*/
@@ -20,6 +20,7 @@
#include <asm/omap_common.h>
#include <env.h>
#include <spl.h>
+#include <linux/printk.h>
#include "../common/board_detect.h"
diff --git a/board/ti/common/Makefile b/board/ti/common/Makefile
index 3172d87..26bf12e 100644
--- a/board/ti/common/Makefile
+++ b/board/ti/common/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
-# Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o
obj-${CONFIG_CMD_EXTENSION} += cape_detect.o
diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c
index 9a53884..0ec6d1a 100644
--- a/board/ti/common/board_detect.c
+++ b/board/ti/common/board_detect.c
@@ -2,7 +2,7 @@
/*
* Library to support early TI EVM EEPROM handling
*
- * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla
* Steve Kipisz
*/
@@ -19,6 +19,7 @@
#include <mmc.h>
#include <errno.h>
#include <malloc.h>
+#include <linux/printk.h>
#include "board_detect.h"
diff --git a/board/ti/common/board_detect.h b/board/ti/common/board_detect.h
index de7cb52..ca1aa80 100644
--- a/board/ti/common/board_detect.h
+++ b/board/ti/common/board_detect.h
@@ -2,7 +2,7 @@
/*
* Library to support early TI EVM EEPROM handling
*
- * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com
*/
#ifndef __BOARD_DETECT_H
diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig
index e6cb21f..9505330 100644
--- a/board/ti/j721e/Kconfig
+++ b/board/ti/j721e/Kconfig
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
# Lokesh Vutla <lokeshvutla@ti.com>
choice
diff --git a/board/ti/j721e/Makefile b/board/ti/j721e/Makefile
index 97535f5..6e91054 100644
--- a/board/ti/j721e/Makefile
+++ b/board/ti/j721e/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
# Lokesh Vutla <lokeshvutla@ti.com>
#
# SPDX-License-Identifier: GPL-2.0+
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 38fe447..c13c6b2 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -2,7 +2,7 @@
/*
* Board specific initialization for J721E EVM
*
- * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*
*/
@@ -22,6 +22,7 @@
#include <spl.h>
#include <dm.h>
#include <dm/uclass-internal.h>
+#include <linux/printk.h>
#include "../common/board_detect.h"
diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env
index 2f2fb05..8cc8232 100644
--- a/board/ti/j721e/j721e.env
+++ b/board/ti/j721e/j721e.env
@@ -1,4 +1,4 @@
-#include <env/ti/ti_armv7_common.env>
+#include <env/ti/ti_common.env>
#include <env/ti/mmc.env>
#include <env/ti/ufs.env>
#include <env/ti/k3_dfu.env>
diff --git a/board/ti/j721s2/MAINTAINERS b/board/ti/j721s2/MAINTAINERS
index 323bd23..08c8d11 100644
--- a/board/ti/j721s2/MAINTAINERS
+++ b/board/ti/j721s2/MAINTAINERS
@@ -1,16 +1,23 @@
J721S2 BOARD
-M: Aswath Govindraju <a-govindraju@ti.com>
+M: Manorit Chawdhry <m-chawdhry@ti.com>
S: Maintained
F: board/ti/j721s2
+F: arch/arm/mach-k3/j721s2
+F: doc/board/ti/j721s2_evm.rst
F: include/configs/j721s2_evm.h
F: configs/j721s2_evm_r5_defconfig
F: configs/j721s2_evm_a72_defconfig
F: arch/arm/dts/k3-j721s2.dtsi
F: arch/arm/dts/k3-j721s2-main.dtsi
F: arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
+F: arch/arm/dts/k3-j721s2-thermal.dtsi
F: arch/arm/dts/k3-j721s2-som-p0.dtsi
F: arch/arm/dts/k3-j721s2-common-proc-board.dts
F: arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
-F: arch/arm/dts//k3-j721s2-r5-common-proc-board.dts
+F: arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
F: arch/arm/dts/k3-j721s2-ddr.dtsi
F: arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi
+F: arch/arm/dts/k3-am68-sk-som.dtsi
+F: arch/arm/dts/k3-am68-sk-base-board.dts
+F: arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi
+F: arch/arm/dts/k3-am68-sk-r5-base-board.dts
diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c
index 7795300..01eb496 100644
--- a/board/ti/j721s2/evm.c
+++ b/board/ti/j721s2/evm.c
@@ -2,7 +2,7 @@
/*
* Board specific initialization for J721S2 EVM
*
- * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
* David Huang <d-huang@ti.com>
*
*/
diff --git a/board/ti/j721s2/j721s2.env b/board/ti/j721s2/j721s2.env
index 6825b14..64e3d9d 100644
--- a/board/ti/j721s2/j721s2.env
+++ b/board/ti/j721s2/j721s2.env
@@ -1,4 +1,4 @@
-#include <env/ti/ti_armv7_common.env>
+#include <env/ti/ti_common.env>
#include <env/ti/mmc.env>
#include <env/ti/ufs.env>
#include <env/ti/k3_dfu.env>
diff --git a/board/ti/ks2_evm/k2e_evm.env b/board/ti/ks2_evm/k2e_evm.env
index a145db5..3dbb793 100644
--- a/board/ti/ks2_evm/k2e_evm.env
+++ b/board/ti/ks2_evm/k2e_evm.env
@@ -1,4 +1,4 @@
-#include <env/ti/ti_armv7_common.env>
+#include <env/ti/ti_common.env>
#include <env/ti/ti_armv7_keystone2.env>
findfdt=setenv fdtfile ${name_fdt}
diff --git a/board/ti/ks2_evm/k2g_evm.env b/board/ti/ks2_evm/k2g_evm.env
index 4f4941d..2b500fc 100644
--- a/board/ti/ks2_evm/k2g_evm.env
+++ b/board/ti/ks2_evm/k2g_evm.env
@@ -1,4 +1,4 @@
-#include <env/ti/ti_armv7_common.env>
+#include <env/ti/ti_common.env>
#include <env/ti/ti_armv7_keystone2.env>
#include <env/ti/mmc.env>
diff --git a/board/ti/ks2_evm/k2hk_evm.env b/board/ti/ks2_evm/k2hk_evm.env
index 0714a51..9991b76 100644
--- a/board/ti/ks2_evm/k2hk_evm.env
+++ b/board/ti/ks2_evm/k2hk_evm.env
@@ -1,4 +1,4 @@
-#include <env/ti/ti_armv7_common.env>
+#include <env/ti/ti_common.env>
#include <env/ti/ti_armv7_keystone2.env>
findfdt=setenv fdtfile ${name_fdt}
diff --git a/board/ti/ks2_evm/k2l_evm.env b/board/ti/ks2_evm/k2l_evm.env
index e8a803a..4e2debc 100644
--- a/board/ti/ks2_evm/k2l_evm.env
+++ b/board/ti/ks2_evm/k2l_evm.env
@@ -1,4 +1,4 @@
-#include <env/ti/ti_armv7_common.env>
+#include <env/ti/ti_common.env>
#include <env/ti/ti_armv7_keystone2.env>
findfdt=setenv fdtfile ${name_fdt}
diff --git a/board/toradex/apalis-tk1/apalis-tk1.c b/board/toradex/apalis-tk1/apalis-tk1.c
index 86b1040..8513431 100644
--- a/board/toradex/apalis-tk1/apalis-tk1.c
+++ b/board/toradex/apalis-tk1/apalis-tk1.c
@@ -17,6 +17,7 @@
#include <fdt_support.h>
#include <pci_tegra.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <power/as3722.h>
#include <power/pmic.h>
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index 3c7cfa3..fa6b722 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -30,6 +30,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/sata.h>
#include <asm/mach-imx/video.h>
+#include <asm/sections.h>
#include <dm/device-internal.h>
#include <dm/platform_data/serial_mxc.h>
#include <dwc_ahsata.h>
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index 677caa4..e6c9b10 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -29,6 +29,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/sata.h>
#include <asm/mach-imx/video.h>
+#include <asm/sections.h>
#include <cpu.h>
#include <dm/platform_data/serial_mxc.h>
#include <fsl_esdhc_imx.h>
diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c
index 119e67b..3e7c5d6 100644
--- a/board/toradex/colibri_imx7/colibri_imx7.c
+++ b/board/toradex/colibri_imx7/colibri_imx7.c
@@ -53,6 +53,11 @@
#define USB_CDET_GPIO IMX_GPIO_NR(7, 14)
+#define FLASH_DETECTION_CTRL (PAD_CTL_HYS | PAD_CTL_PUE)
+#define FLASH_DET_GPIO IMX_GPIO_NR(6, 11)
+
+static bool is_emmc;
+
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, imx_ddr_size());
@@ -60,6 +65,10 @@
return 0;
}
+static iomux_v3_cfg_t const flash_detection_pads[] = {
+ MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(FLASH_DETECTION_CTRL) | MUX_MODE_SION,
+};
+
static iomux_v3_cfg_t const uart1_pads[] = {
MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
@@ -183,6 +192,16 @@
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+ /*
+ * Enable GPIO SION on NAND_WE_B/eMMC_RST with 100k pull-down. eMMC_RST
+ * is pulled high with 4.7k for eMMC devices. This allows to reliably
+ * detect eMMC vs NAND flash.
+ */
+ imx_iomux_v3_setup_multiple_pads(flash_detection_pads, ARRAY_SIZE(flash_detection_pads));
+ gpio_request(FLASH_DET_GPIO, "flash-detection-gpio");
+ is_emmc = gpio_get_value(FLASH_DET_GPIO);
+ gpio_free(FLASH_DET_GPIO);
+
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
@@ -348,6 +367,11 @@
env_set("bootcmd", "sdp 0");
}
#endif
+ if (is_emmc)
+ env_set("variant", "-emmc");
+ else
+ env_set("variant", "");
+
return 0;
}
#endif /* CONFIG_BOARD_LATE_INIT */
diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c
index a3d1d07..d09dda5 100644
--- a/board/toradex/verdin-am62/verdin-am62.c
+++ b/board/toradex/verdin-am62/verdin-am62.c
@@ -28,8 +28,8 @@
{
gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE);
- if (gd->ram_size < SZ_64M)
- puts("## WARNING: Less than 64MB RAM detected\n");
+ if (gd->ram_size < SZ_512M)
+ puts("## WARNING: Less than 512MB RAM detected\n");
return 0;
}
diff --git a/board/toradex/verdin-imx8mm/lpddr4_timing.c b/board/toradex/verdin-imx8mm/lpddr4_timing.c
index d114abf..4dfec67 100644
--- a/board/toradex/verdin-imx8mm/lpddr4_timing.c
+++ b/board/toradex/verdin-imx8mm/lpddr4_timing.c
@@ -1,12 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2020 Toradex
+ * Copyright 2023 Toradex
*
* Generated code from MX8M_DDR_tool
- * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
*
- * DDR calibration created with mscale_ddr_tool_v210_setup.exe using
- * MX8M_Mini_LPDDR4_RPA_v14 Verdin iMX8MM V1.0.xlsx as of 1. Nov. 2019.
+ * DDR calibration created with mscale_ddr_tool_v3.31_setup.exe using
+ * MX8M_Mini_LPDDR4_RPA_v22 Verdin iMX8MM V1.0.xlsx as of 7. Aug. 2023.
*/
#include <linux/kernel.h>
@@ -17,22 +16,22 @@
{0x3d400304, 0x1},
{0x3d400030, 0x1},
{0x3d400000, 0xa1080020},
- {0x3d400020, 0x203},
+ {0x3d400020, 0x202},
{0x3d400024, 0x3a980},
- {0x3d400064, 0x5b00d2},
+ {0x3d400064, 0x2d00d2},
{0x3d4000d0, 0xc00305ba},
{0x3d4000d4, 0x940000},
{0x3d4000dc, 0xd4002d},
{0x3d4000e0, 0x310000},
{0x3d4000e8, 0x66004d},
{0x3d4000ec, 0x16004d},
- {0x3d400100, 0x191e1920},
+ {0x3d400100, 0x191e0c20},
{0x3d400104, 0x60630},
{0x3d40010c, 0xb0b000},
{0x3d400110, 0xe04080e},
{0x3d400114, 0x2040c0c},
{0x3d400118, 0x1010007},
- {0x3d40011c, 0x401},
+ {0x3d40011c, 0x402},
{0x3d400130, 0x20600},
{0x3d400134, 0xc100002},
{0x3d400138, 0xd8},
@@ -49,7 +48,7 @@
{0x3d4001b0, 0x11},
{0x3d4001c0, 0x1},
{0x3d4001c4, 0x1},
- {0x3d4000f4, 0xc99},
+ {0x3d4000f4, 0x699},
{0x3d400108, 0x70e1617},
{0x3d400200, 0x1f},
{0x3d40020c, 0x0},
@@ -57,6 +56,7 @@
{0x3d400204, 0x80808},
{0x3d400214, 0x7070707},
{0x3d400218, 0x7070707},
+ {0x3d40021c, 0xf0f},
{0x3d400250, 0x29001701},
{0x3d400254, 0x2c},
{0x3d40025c, 0x4000030},
@@ -68,22 +68,22 @@
{0x3d400498, 0x620096},
{0x3d40049c, 0x1100e07},
{0x3d4004a0, 0xc8012c},
- {0x3d402020, 0x1},
+ {0x3d402020, 0x0},
{0x3d402024, 0x7d00},
{0x3d402050, 0x20d040},
- {0x3d402064, 0xc001c},
+ {0x3d402064, 0x6001c},
{0x3d4020dc, 0x840000},
{0x3d4020e0, 0x310000},
{0x3d4020e8, 0x66004d},
{0x3d4020ec, 0x16004d},
- {0x3d402100, 0xa040305},
+ {0x3d402100, 0xa040105},
{0x3d402104, 0x30407},
{0x3d402108, 0x203060b},
{0x3d40210c, 0x505000},
{0x3d402110, 0x2040202},
{0x3d402114, 0x2030202},
{0x3d402118, 0x1010004},
- {0x3d40211c, 0x301},
+ {0x3d40211c, 0x302},
{0x3d402130, 0x20300},
{0x3d402134, 0xa100002},
{0x3d402138, 0x1d},
@@ -92,8 +92,8 @@
{0x3d402190, 0x3818200},
{0x3d402194, 0x80303},
{0x3d4021b4, 0x100},
- {0x3d4020f4, 0xc99},
- {0x3d403020, 0x1},
+ {0x3d4020f4, 0x599},
+ {0x3d403020, 0x0},
{0x3d403024, 0x1f40},
{0x3d403050, 0x20d040},
{0x3d403064, 0x30007},
@@ -108,7 +108,7 @@
{0x3d403110, 0x2040202},
{0x3d403114, 0x2030202},
{0x3d403118, 0x1010004},
- {0x3d40311c, 0x301},
+ {0x3d40311c, 0x302},
{0x3d403130, 0x20300},
{0x3d403134, 0xa100002},
{0x3d403138, 0x8},
@@ -117,7 +117,7 @@
{0x3d403190, 0x3818200},
{0x3d403194, 0x80303},
{0x3d4031b4, 0x100},
- {0x3d4030f4, 0xc99},
+ {0x3d4030f4, 0x599},
{0x3d400028, 0x0},
};
@@ -205,8 +205,8 @@
{0x220024, 0x1ab},
{0x2003a, 0x0},
{0x20056, 0x3},
- {0x120056, 0xa},
- {0x220056, 0xa},
+ {0x120056, 0x3},
+ {0x220056, 0x3},
{0x1004d, 0xe00},
{0x1014d, 0xe00},
{0x1104d, 0xe00},
@@ -1058,7 +1058,6 @@
{0x54008, 0x131f},
{0x54009, 0xc8},
{0x5400b, 0x2},
- {0x5400d, 0x100},
{0x54012, 0x110},
{0x54019, 0x2dd4},
{0x5401a, 0x31},
@@ -1098,7 +1097,6 @@
{0x54008, 0x121f},
{0x54009, 0xc8},
{0x5400b, 0x2},
- {0x5400d, 0x100},
{0x54012, 0x110},
{0x54019, 0x84},
{0x5401a, 0x31},
@@ -1138,7 +1136,6 @@
{0x54008, 0x121f},
{0x54009, 0xc8},
{0x5400b, 0x2},
- {0x5400d, 0x100},
{0x54012, 0x110},
{0x54019, 0x84},
{0x5401a, 0x31},
@@ -1204,7 +1201,7 @@
{0x5403b, 0x4d},
{0x5403c, 0x4d},
{0x5403d, 0x1600},
- { 0xd0000, 0x1 },
+ {0xd0000, 0x1},
};
/* DRAM PHY init engine image */
@@ -1697,15 +1694,15 @@
{0x400d6, 0x20a},
{0x400d7, 0x20b},
{0x2003a, 0x2},
- {0x2000b, 0x5d},
+ {0x2000b, 0x34b},
{0x2000c, 0xbb},
{0x2000d, 0x753},
{0x2000e, 0x2c},
- {0x12000b, 0xc},
+ {0x12000b, 0x70},
{0x12000c, 0x19},
{0x12000d, 0xfa},
{0x12000e, 0x10},
- {0x22000b, 0x3},
+ {0x22000b, 0x1c},
{0x22000c, 0x6},
{0x22000d, 0x3e},
{0x22000e, 0x10},
@@ -1846,5 +1843,5 @@
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 3000, 400, 100, },
+ .fsp_table = {3000, 400, 100,},
};
diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c
index 9d54d60..afa3686 100644
--- a/board/toradex/verdin-imx8mm/spl.c
+++ b/board/toradex/verdin-imx8mm/spl.c
@@ -16,6 +16,7 @@
#include <asm/io.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
+#include <asm/sections.h>
#include <cpu_func.h>
#include <dm/device.h>
#include <dm/device-internal.h>
diff --git a/board/tq/tqma6/tqma6q.cfg b/board/tq/tqma6/tqma6q.cfg
index a49489a..a345c4d 100644
--- a/board/tq/tqma6/tqma6q.cfg
+++ b/board/tq/tqma6/tqma6q.cfg
@@ -36,7 +36,7 @@
DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
-DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
+DATA 4, MX6_IOM_DRAM_RESET, 0x00003030
DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
diff --git a/board/traverse/ten64/ten64.c b/board/traverse/ten64/ten64.c
index df9f0af..6ff5312 100644
--- a/board/traverse/ten64/ten64.c
+++ b/board/traverse/ten64/ten64.c
@@ -26,7 +26,6 @@
#include <fsl-mc/fsl_mc.h>
#include <env_internal.h>
#include <asm/arch-fsl-layerscape/soc.h>
-#include <asm/arch/ppa.h>
#include <hwconfig.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
index 1287f71..730e266 100644
--- a/board/udoo/neo/neo.c
+++ b/board/udoo/neo/neo.c
@@ -17,6 +17,7 @@
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
+#include <asm/sections.h>
#include <dm.h>
#include <env.h>
#include <mmc.h>
diff --git a/board/variscite/dart_6ul/spl.c b/board/variscite/dart_6ul/spl.c
index 17b1ae7..1dff69c 100644
--- a/board/variscite/dart_6ul/spl.c
+++ b/board/variscite/dart_6ul/spl.c
@@ -12,6 +12,7 @@
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/crm_regs.h>
+#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
diff --git a/board/variscite/imx8mn_var_som/spl.c b/board/variscite/imx8mn_var_som/spl.c
index 41e7050..01a63c6 100644
--- a/board/variscite/imx8mn_var_som/spl.c
+++ b/board/variscite/imx8mn_var_som/spl.c
@@ -13,6 +13,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/gpio.h>
+#include <asm/sections.h>
#include <dm/device.h>
#include <dm/uclass.h>
diff --git a/board/vocore/vocore2/Makefile b/board/vocore/vocore2/Makefile
deleted file mode 100644
index 70cd7a8..0000000
--- a/board/vocore/vocore2/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += board.o
diff --git a/board/vocore/vocore2/board.c b/board/vocore/vocore2/board.c
deleted file mode 100644
index 27e42d1..0000000
--- a/board/vocore/vocore2/board.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2019 Mauro Condarelli <mc5686@mclink.it>
- *
- * Nothing actually needed here
- */
diff --git a/board/vscom/baltos/Makefile b/board/vscom/baltos/Makefile
index 3ccf66b..2b1e21a 100644
--- a/board/vscom/baltos/Makefile
+++ b/board/vscom/baltos/Makefile
@@ -2,7 +2,7 @@
#
# Makefile
#
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c
index 8f23cda..bc7dc58 100644
--- a/board/vscom/baltos/board.c
+++ b/board/vscom/baltos/board.c
@@ -4,7 +4,7 @@
*
* Board functions for TI AM335X based boards
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/vscom/baltos/board.h b/board/vscom/baltos/board.h
index 630c9bb..db6e191 100644
--- a/board/vscom/baltos/board.h
+++ b/board/vscom/baltos/board.h
@@ -4,7 +4,7 @@
*
* TI AM335x boards information header
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _BOARD_H_
diff --git a/board/vscom/baltos/mux.c b/board/vscom/baltos/mux.c
index e01899c..7b99cf0 100644
--- a/board/vscom/baltos/mux.c
+++ b/board/vscom/baltos/mux.c
@@ -1,7 +1,7 @@
/*
* mux.c
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/board/work-microwave/work_92105/work_92105_display.c b/board/work-microwave/work_92105/work_92105_display.c
index 5f625e6..64dd5d4 100644
--- a/board/work-microwave/work_92105/work_92105_display.c
+++ b/board/work-microwave/work_92105/work_92105_display.c
@@ -293,12 +293,10 @@
return 1;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char max6957aax_help_text[] =
+U_BOOT_LONGHELP(max6957aax,
"max6957aax - write or read display register:\n"
"\tmax6957aax R|r reg - read display register;\n"
- "\tmax6957aax reg val - write display register.";
-#endif
+ "\tmax6957aax reg val - write display register.");
U_BOOT_CMD(
max6957aax, 6, 1, do_max6957aax,
@@ -337,13 +335,11 @@
return 0;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char hd44780_help_text[] =
+U_BOOT_LONGHELP(hd44780,
"hd44780 - control LCD driver:\n"
"\thd44780 cmd <val> - send command <val> to driver;\n"
"\thd44780 data <val> - send data <val> to driver;\n"
- "\thd44780 str \"<text>\" - send \"<text>\" to driver.";
-#endif
+ "\thd44780 str \"<text>\" - send \"<text>\" to driver.");
U_BOOT_CMD(
hd44780, 6, 1, do_hd44780,
diff --git a/board/xen/xenguest_arm64/MAINTAINERS b/board/xen/xenguest_arm64/MAINTAINERS
index 264920e..7a31736 100644
--- a/board/xen/xenguest_arm64/MAINTAINERS
+++ b/board/xen/xenguest_arm64/MAINTAINERS
@@ -6,3 +6,4 @@
F: doc/board/xen/
F: include/configs/xenguest_arm64.h
F: configs/xenguest_arm64_defconfig
+F: configs/xenguest_arm64_virtio_defconfig
diff --git a/board/xen/xenguest_arm64/xenguest_arm64.c b/board/xen/xenguest_arm64/xenguest_arm64.c
index 6e10bba..244070a 100644
--- a/board/xen/xenguest_arm64/xenguest_arm64.c
+++ b/board/xen/xenguest_arm64/xenguest_arm64.c
@@ -8,12 +8,15 @@
*/
#include <common.h>
+#include <log.h>
#include <cpu_func.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <xen.h>
#include <asm/global_data.h>
+#include <virtio_types.h>
+#include <virtio.h>
#include <asm/io.h>
#include <asm/armv8/mmu.h>
@@ -49,7 +52,14 @@
return (void *)rom_pointer[0];
}
-#define MAX_MEM_MAP_REGIONS 5
+/*
+ * MAX_MEM_MAP_REGIONS should respect to:
+ * 3 Xen related regions
+ * 6 regions for 2 PCI Host bridges
+ * 10 regions for MMIO devices
+ * 2 memory regions
+ */
+#define MAX_MEM_MAP_REGIONS 22
static struct mm_region xen_mem_map[MAX_MEM_MAP_REGIONS];
struct mm_region *mem_map = xen_mem_map;
@@ -63,6 +73,93 @@
return mem;
}
+#ifdef CONFIG_VIRTIO_BLK
+#ifdef CONFIG_VIRTIO_PCI
+static void add_pci_mem_map(const void *blob, int *cnt)
+{
+ struct fdt_resource reg_res;
+ int node = -1, len = 0, cells_per_record = 0, max_regions = 0;
+ int pci_addr_cells = 0, addr_cells = 0, size_cells = 0;
+
+ while ((node = fdt_node_offset_by_prop_value(blob, node, "compatible",
+ "pci-host-ecam-generic",
+ sizeof("pci-host-ecam-generic"))) >= 0) {
+ if ((*cnt) >= MAX_MEM_MAP_REGIONS ||
+ fdt_get_resource(blob, node, "reg", 0, ®_res) < 0)
+ return;
+
+ xen_mem_map[*cnt].virt = reg_res.start;
+ xen_mem_map[*cnt].phys = reg_res.start;
+ xen_mem_map[*cnt].size = fdt_resource_size(®_res);
+ xen_mem_map[*cnt].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE);
+ (*cnt)++;
+
+ const u32 *prop = fdt_getprop(blob, node, "ranges", &len);
+
+ if (!prop)
+ return;
+
+ pci_addr_cells = fdt_address_cells(blob, node);
+ addr_cells = fdt_address_cells(blob, 0);
+ size_cells = fdt_size_cells(blob, node);
+
+ /* PCI addresses are always 3-cells */
+ len /= sizeof(u32);
+ cells_per_record = pci_addr_cells + addr_cells + size_cells;
+ max_regions = len / cells_per_record + CONFIG_NR_DRAM_BANKS;
+
+ for (int i = 0; i < max_regions; i++, len -= cells_per_record) {
+ u64 pci_addr, addr, size;
+ int space_code;
+ u32 flags;
+
+ if (((*cnt) >= MAX_MEM_MAP_REGIONS) || len < cells_per_record)
+ return;
+
+ flags = fdt32_to_cpu(prop[0]);
+ space_code = (flags >> 24) & 3;
+ pci_addr = fdtdec_get_number(prop + 1, 2);
+ prop += pci_addr_cells;
+ addr = fdtdec_get_number(prop, addr_cells);
+ prop += addr_cells;
+ size = fdtdec_get_number(prop, size_cells);
+ prop += size_cells;
+
+ xen_mem_map[*cnt].virt = addr;
+ xen_mem_map[*cnt].phys = addr;
+ xen_mem_map[*cnt].size = size;
+ xen_mem_map[*cnt].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE);
+ (*cnt)++;
+ }
+ }
+}
+#endif
+
+#ifdef CONFIG_VIRTIO_MMIO
+static void add_mmio_mem_map(const void *blob, int *cnt)
+{
+ int node = -1;
+ struct fdt_resource reg_res;
+
+ if ((*cnt) >= MAX_MEM_MAP_REGIONS)
+ return;
+ while ((node = fdt_node_offset_by_prop_value(blob, node, "compatible", "virtio,mmio",
+ sizeof("virtio,mmio"))) >= 0) {
+ if (fdt_get_resource(blob, node, "reg", 0, ®_res) < 0)
+ return;
+ xen_mem_map[*cnt].virt = reg_res.start;
+ xen_mem_map[*cnt].phys = reg_res.start;
+ xen_mem_map[*cnt].size = roundup(fdt_resource_size(®_res), PAGE_SIZE);
+ xen_mem_map[*cnt].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE);
+ (*cnt)++;
+ }
+}
+#endif
+#endif
+
static int setup_mem_map(void)
{
int i = 0, ret, mem, reg = 0;
@@ -72,6 +169,7 @@
phys_addr_t gnttab_base;
phys_size_t gnttab_sz;
+ memset(xen_mem_map, 0, sizeof(xen_mem_map));
/*
* Add "magic" region which is used by Xen to provide some essentials
* for the guest: we need console and xenstore.
@@ -143,6 +241,14 @@
xen_mem_map[i].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE);
}
+#ifdef CONFIG_VIRTIO_BLK
+#ifdef CONFIG_VIRTIO_PCI
+ add_pci_mem_map(blob, &i);
+#endif
+#ifdef CONFIG_VIRTIO_MMIO
+ add_mmio_mem_map(blob, &i);
+#endif
+#endif
return 0;
}
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 906d5e3..9309b07 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -374,12 +374,12 @@
* region
*/
if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
- fdt_blob = (ulong *)&_image_binary_end;
+ fdt_blob = (ulong *)_image_binary_end;
else
- fdt_blob = (ulong *)&__bss_end;
+ fdt_blob = (ulong *)__bss_end;
} else {
/* FDT is at end of image */
- fdt_blob = (ulong *)&_end;
+ fdt_blob = (ulong *)_end;
}
if (fdt_magic(fdt_blob) == FDT_MAGIC)
@@ -411,19 +411,44 @@
int i, id, macid = 0;
struct xilinx_board_description *desc;
phys_size_t bootm_size = gd->ram_top - gd->ram_base;
+ u64 bootscr_flash_offset, bootscr_flash_size;
if (!IS_ENABLED(CONFIG_MICROBLAZE)) {
ulong scriptaddr;
+ u64 bootscr_address;
+ u64 bootscr_offset;
- scriptaddr = env_get_hex("scriptaddr", 0);
- ret |= env_set_hex("scriptaddr", gd->ram_base + scriptaddr);
+ /* Fetch bootscr_address/bootscr_offset from DT and update */
+ if (!ofnode_read_bootscript_address(&bootscr_address,
+ &bootscr_offset)) {
+ if (bootscr_offset)
+ ret |= env_set_hex("scriptaddr",
+ gd->ram_base +
+ bootscr_offset);
+ else
+ ret |= env_set_hex("scriptaddr",
+ bootscr_address);
+ } else {
+ /* Update scriptaddr(bootscr offset) from env */
+ scriptaddr = env_get_hex("scriptaddr", 0);
+ ret |= env_set_hex("scriptaddr",
+ gd->ram_base + scriptaddr);
+ }
+ }
+
+ if (!ofnode_read_bootscript_flash(&bootscr_flash_offset,
+ &bootscr_flash_size)) {
+ ret |= env_set_hex("script_offset_f", bootscr_flash_offset);
+ ret |= env_set_hex("script_size_f", bootscr_flash_size);
+ } else {
+ debug("!!! Please define bootscr-flash-offset via DT !!!\n");
+ ret |= env_set_hex("script_offset_f",
+ CONFIG_BOOT_SCRIPT_OFFSET);
}
if (IS_ENABLED(CONFIG_ARCH_ZYNQ) || IS_ENABLED(CONFIG_MICROBLAZE))
bootm_size = min(bootm_size, (phys_size_t)(SZ_512M + SZ_256M));
- ret |= env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
-
ret |= env_set_addr("bootm_low", (void *)gd->ram_base);
ret |= env_set_addr("bootm_size", (void *)bootm_size);
diff --git a/board/xilinx/common/fru.c b/board/xilinx/common/fru.c
index f6ca46c..c916c3d 100644
--- a/board/xilinx/common/fru.c
+++ b/board/xilinx/common/fru.c
@@ -72,17 +72,14 @@
}
/***************************************************/
-#ifdef CONFIG_SYS_LONGHELP
-static char fru_help_text[] =
+U_BOOT_LONGHELP(fru,
"capture <addr> - Parse and capture FRU table present at address.\n"
"fru display - Displays content of FRU table that was captured using\n"
" fru capture command\n"
"fru board_gen <addr> <manufacturer> <board name> <serial number>\n"
" <part number> <revision> - Generate FRU format with\n"
" board info area filled based on parameters. <addr> is\n"
- " pointing to place where FRU is generated.\n"
- ;
-#endif
+ " pointing to place where FRU is generated.\n");
U_BOOT_CMD(
fru, 8, 1, do_fru,
diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c
index a427ac9..2b035d5 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -10,7 +10,6 @@
* header files
*/
-#include <common.h>
#include <config.h>
#include <env.h>
#include <init.h>
diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c
index f0d2224..990ca16 100644
--- a/board/xilinx/versal-net/board.c
+++ b/board/xilinx/versal-net/board.c
@@ -194,25 +194,17 @@
return bootmode;
}
-int board_late_init(void)
+static int boot_targets_setup(void)
{
u8 bootmode;
struct udevice *dev;
int bootseq = -1;
int bootseq_len = 0;
int env_targets_len = 0;
- const char *mode;
+ const char *mode = NULL;
char *new_targets;
char *env_targets;
- if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
- debug("Saved variables - Skipping\n");
- return 0;
- }
-
- if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
- return 0;
-
bootmode = versal_net_get_bootmode();
puts("Bootmode: ");
@@ -229,8 +221,8 @@
puts("QSPI_MODE_24\n");
if (uclass_get_device_by_name(UCLASS_SPI,
"spi@f1030000", &dev)) {
- puts("Boot from QSPI but without QSPI enabled!\n");
- return -1;
+ debug("QSPI driver for QSPI device is not present\n");
+ break;
}
mode = "xspi";
bootseq = dev_seq(dev);
@@ -239,8 +231,8 @@
puts("QSPI_MODE_32\n");
if (uclass_get_device_by_name(UCLASS_SPI,
"spi@f1030000", &dev)) {
- puts("Boot from QSPI but without QSPI enabled!\n");
- return -1;
+ debug("QSPI driver for QSPI device is not present\n");
+ break;
}
mode = "xspi";
bootseq = dev_seq(dev);
@@ -249,8 +241,8 @@
puts("OSPI_MODE\n");
if (uclass_get_device_by_name(UCLASS_SPI,
"spi@f1010000", &dev)) {
- puts("Boot from OSPI but without OSPI enabled!\n");
- return -1;
+ debug("OSPI driver for OSPI device is not present\n");
+ break;
}
mode = "xspi";
bootseq = dev_seq(dev);
@@ -260,12 +252,15 @@
mode = "mmc";
bootseq = dev_seq(dev);
break;
+ case SELECTMAP_MODE:
+ puts("SELECTMAP_MODE\n");
+ break;
case SD_MODE:
puts("SD_MODE\n");
if (uclass_get_device_by_name(UCLASS_MMC,
"mmc@f1040000", &dev)) {
- puts("Boot from SD0 but without SD0 enabled!\n");
- return -1;
+ debug("SD0 driver for SD0 device is not present\n");
+ break;
}
debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
@@ -279,8 +274,8 @@
puts("SD_MODE1\n");
if (uclass_get_device_by_name(UCLASS_MMC,
"mmc@f1050000", &dev)) {
- puts("Boot from SD1 but without SD1 enabled!\n");
- return -1;
+ debug("SD1 driver for SD1 device is not present\n");
+ break;
}
debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
@@ -288,37 +283,59 @@
bootseq = dev_seq(dev);
break;
default:
- mode = "";
printf("Invalid Boot Mode:0x%x\n", bootmode);
break;
}
- if (bootseq >= 0) {
- bootseq_len = snprintf(NULL, 0, "%i", bootseq);
- debug("Bootseq len: %x\n", bootseq_len);
+ if (mode) {
+ if (bootseq >= 0) {
+ bootseq_len = snprintf(NULL, 0, "%i", bootseq);
+ debug("Bootseq len: %x\n", bootseq_len);
+ }
+
+ /*
+ * One terminating char + one byte for space between mode
+ * and default boot_targets
+ */
+ env_targets = env_get("boot_targets");
+ if (env_targets)
+ env_targets_len = strlen(env_targets);
+
+ new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
+ bootseq_len);
+ if (!new_targets)
+ return -ENOMEM;
+
+ if (bootseq >= 0)
+ sprintf(new_targets, "%s%x %s", mode, bootseq,
+ env_targets ? env_targets : "");
+ else
+ sprintf(new_targets, "%s %s", mode,
+ env_targets ? env_targets : "");
+
+ env_set("boot_targets", new_targets);
}
- /*
- * One terminating char + one byte for space between mode
- * and default boot_targets
- */
- env_targets = env_get("boot_targets");
- if (env_targets)
- env_targets_len = strlen(env_targets);
+ return 0;
+}
- new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
- bootseq_len);
- if (!new_targets)
- return -ENOMEM;
+int board_late_init(void)
+{
+ int ret;
- if (bootseq >= 0)
- sprintf(new_targets, "%s%x %s", mode, bootseq,
- env_targets ? env_targets : "");
- else
- sprintf(new_targets, "%s %s", mode,
- env_targets ? env_targets : "");
+ if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
+ debug("Saved variables - Skipping\n");
+ return 0;
+ }
- env_set("boot_targets", new_targets);
+ if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
+ return 0;
+
+ if (IS_ENABLED(CONFIG_DISTRO_DEFAULTS)) {
+ ret = boot_targets_setup();
+ if (ret)
+ return ret;
+ }
return board_late_init_xilinx();
}
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index 60bf37d..8c2e614 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -126,25 +126,17 @@
return bootmode;
}
-int board_late_init(void)
+static int boot_targets_setup(void)
{
u8 bootmode;
struct udevice *dev;
int bootseq = -1;
int bootseq_len = 0;
int env_targets_len = 0;
- const char *mode;
+ const char *mode = NULL;
char *new_targets;
char *env_targets;
- if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
- debug("Saved variables - Skipping\n");
- return 0;
- }
-
- if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
- return 0;
-
bootmode = versal_get_bootmode();
puts("Bootmode: ");
@@ -175,21 +167,24 @@
"mmc@f1050000", &dev) &&
uclass_get_device_by_name(UCLASS_MMC,
"sdhci@f1050000", &dev)) {
- puts("Boot from EMMC but without SD1 enabled!\n");
- return -1;
+ debug("SD1 driver for SD1 device is not present\n");
+ break;
}
debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
mode = "mmc";
bootseq = dev_seq(dev);
break;
+ case SELECTMAP_MODE:
+ puts("SELECTMAP_MODE\n");
+ break;
case SD_MODE:
puts("SD_MODE\n");
if (uclass_get_device_by_name(UCLASS_MMC,
"mmc@f1040000", &dev) &&
uclass_get_device_by_name(UCLASS_MMC,
"sdhci@f1040000", &dev)) {
- puts("Boot from SD0 but without SD0 enabled!\n");
- return -1;
+ debug("SD0 driver for SD0 device is not present\n");
+ break;
}
debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
@@ -205,8 +200,8 @@
"mmc@f1050000", &dev) &&
uclass_get_device_by_name(UCLASS_MMC,
"sdhci@f1050000", &dev)) {
- puts("Boot from SD1 but without SD1 enabled!\n");
- return -1;
+ debug("SD1 driver for SD1 device is not present\n");
+ break;
}
debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
@@ -214,37 +209,59 @@
bootseq = dev_seq(dev);
break;
default:
- mode = "";
printf("Invalid Boot Mode:0x%x\n", bootmode);
break;
}
- if (bootseq >= 0) {
- bootseq_len = snprintf(NULL, 0, "%i", bootseq);
- debug("Bootseq len: %x\n", bootseq_len);
+ if (mode) {
+ if (bootseq >= 0) {
+ bootseq_len = snprintf(NULL, 0, "%i", bootseq);
+ debug("Bootseq len: %x\n", bootseq_len);
+ }
+
+ /*
+ * One terminating char + one byte for space between mode
+ * and default boot_targets
+ */
+ env_targets = env_get("boot_targets");
+ if (env_targets)
+ env_targets_len = strlen(env_targets);
+
+ new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
+ bootseq_len);
+ if (!new_targets)
+ return -ENOMEM;
+
+ if (bootseq >= 0)
+ sprintf(new_targets, "%s%x %s", mode, bootseq,
+ env_targets ? env_targets : "");
+ else
+ sprintf(new_targets, "%s %s", mode,
+ env_targets ? env_targets : "");
+
+ env_set("boot_targets", new_targets);
}
- /*
- * One terminating char + one byte for space between mode
- * and default boot_targets
- */
- env_targets = env_get("boot_targets");
- if (env_targets)
- env_targets_len = strlen(env_targets);
+ return 0;
+}
- new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
- bootseq_len);
- if (!new_targets)
- return -ENOMEM;
+int board_late_init(void)
+{
+ int ret;
- if (bootseq >= 0)
- sprintf(new_targets, "%s%x %s", mode, bootseq,
- env_targets ? env_targets : "");
- else
- sprintf(new_targets, "%s %s", mode,
- env_targets ? env_targets : "");
+ if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
+ debug("Saved variables - Skipping\n");
+ return 0;
+ }
- env_set("boot_targets", new_targets);
+ if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
+ return 0;
+
+ if (IS_ENABLED(CONFIG_DISTRO_DEFAULTS)) {
+ ret = boot_targets_setup();
+ if (ret)
+ return ret;
+ }
return board_late_init_xilinx();
}
@@ -298,6 +315,7 @@
return ENVL_SPI_FLASH;
return ENVL_NOWHERE;
case JTAG_MODE:
+ case SELECTMAP_MODE:
default:
return ENVL_NOWHERE;
}
diff --git a/board/xilinx/versal/cmds.c b/board/xilinx/versal/cmds.c
index 148fa51..9cc2cdc 100644
--- a/board/xilinx/versal/cmds.c
+++ b/board/xilinx/versal/cmds.c
@@ -91,12 +91,9 @@
return cmd_process_error(c, ret);
}
-#ifdef CONFIG_SYS_LONGHELP
-static char versal_help_text[] =
+U_BOOT_LONGHELP(versal,
"loadpdi addr len - Load pdi image\n"
- "load pdi image at ddr address 'addr' with pdi image size 'len'\n"
-;
-#endif
+ "load pdi image at ddr address 'addr' with pdi image size 'len'\n");
U_BOOT_CMD(versal, 4, 1, do_versal,
"versal sub-system",
diff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c
index 024fac6..d7c7b2f 100644
--- a/board/xilinx/zynq/cmds.c
+++ b/board/xilinx/zynq/cmds.c
@@ -527,8 +527,7 @@
return cmd_process_error(zynq_cmd, ret);
}
-#ifdef CONFIG_SYS_LONGHELP
-static char zynq_help_text[] =
+U_BOOT_LONGHELP(zynq,
""
#ifdef CONFIG_CMD_ZYNQ_RSA
"rsa <baseaddr> - Verifies the authenticated and encrypted\n"
@@ -545,8 +544,7 @@
" if operation type is load or loadp, it loads the encrypted\n"
" full or partial bitstream on to PL respectively.\n"
#endif
- ;
-#endif
+ );
U_BOOT_CMD(zynq, 6, 0, do_zynq,
"Zynq specific commands", zynq_help_text
diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c
index ea404d5..f1f3eff 100644
--- a/board/xilinx/zynqmp/cmds.c
+++ b/board/xilinx/zynqmp/cmds.c
@@ -14,16 +14,7 @@
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
-
-struct aes {
- u64 srcaddr;
- u64 ivaddr;
- u64 keyaddr;
- u64 dstaddr;
- u64 len;
- u64 op;
- u64 keysrc;
-};
+#include <mach/zynqmp_aes.h>
static int do_zynqmp_verify_secure(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
@@ -121,9 +112,7 @@
static int do_zynqmp_aes(struct cmd_tbl *cmdtp, int flag, int argc,
char * const argv[])
{
- ALLOC_CACHE_ALIGN_BUFFER(struct aes, aes, 1);
- int ret;
- u32 ret_payload[PAYLOAD_ARG_CNT];
+ ALLOC_CACHE_ALIGN_BUFFER(struct zynqmp_aes, aes, 1);
if (zynqmp_firmware_version() <= PMUFW_V1_0) {
puts("ERR: PMUFW v1.0 or less is detected\n");
@@ -142,40 +131,14 @@
aes->keysrc = hextoul(argv[6], NULL);
aes->dstaddr = hextoul(argv[7], NULL);
- if (aes->srcaddr && aes->ivaddr && aes->dstaddr) {
- flush_dcache_range(aes->srcaddr,
- (aes->srcaddr +
- roundup(aes->len, ARCH_DMA_MINALIGN)));
- flush_dcache_range(aes->ivaddr,
- (aes->ivaddr +
- roundup(IV_SIZE, ARCH_DMA_MINALIGN)));
- flush_dcache_range(aes->dstaddr,
- (aes->dstaddr +
- roundup(aes->len, ARCH_DMA_MINALIGN)));
- }
-
if (aes->keysrc == 0) {
if (argc < cmdtp->maxargs)
return CMD_RET_USAGE;
aes->keyaddr = hextoul(argv[8], NULL);
- if (aes->keyaddr)
- flush_dcache_range(aes->keyaddr,
- (aes->keyaddr +
- roundup(KEY_PTR_LEN,
- ARCH_DMA_MINALIGN)));
}
- flush_dcache_range((ulong)aes, (ulong)(aes) +
- roundup(sizeof(struct aes), ARCH_DMA_MINALIGN));
-
- ret = xilinx_pm_request(PM_SECURE_AES, upper_32_bits((ulong)aes),
- lower_32_bits((ulong)aes), 0, 0, ret_payload);
- if (ret || ret_payload[1])
- printf("Failed: AES op status:0x%x, errcode:0x%x\n",
- ret, ret_payload[1]);
-
- return ret;
+ return zynqmp_aes_operation(aes);
}
#ifdef CONFIG_DEFINE_TCM_OCM_MMAP
@@ -418,8 +381,7 @@
}
/***************************************************/
-#ifdef CONFIG_SYS_LONGHELP
-static char zynqmp_help_text[] =
+U_BOOT_LONGHELP(zynqmp,
"secure src len [key_addr] - verifies secure images of $len bytes\n"
" long at address $src. Optional key_addr\n"
" can be specified if user key needs to\n"
@@ -459,8 +421,7 @@
" 48 bytes hash value into srcaddr\n"
" Optional key_addr can be specified for saving sha3 hash value\n"
" Note: srcaddr/srclen should not be 0\n"
- ;
-#endif
+ );
U_BOOT_CMD(
zynqmp, 9, 1, do_zynqmp,
diff --git a/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c
index 4510230..166e614 100644
--- a/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c
@@ -602,129 +602,6 @@
return 1;
}
-static unsigned long psu_serdes_init_data(void)
-{
- psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U);
- psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
- psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
- psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
- psu_mask_write(0xFD402864, 0x00000081U, 0x00000001U);
- psu_mask_write(0xFD402868, 0x00000082U, 0x00000002U);
- psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
- psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
- psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
- psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U);
- psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
- psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
- psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
- psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU);
- psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U);
- psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U);
- psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U);
- psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
- psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
- psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
- psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
- psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
- psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
- psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
- psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
- psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
- psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
- psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
- psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
- psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
- psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
- psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
- psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
- psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
- psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
- psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
- psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
- psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
- psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
- psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
- psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
- psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
- psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
- psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
- psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
- psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
- psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
- psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
- psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
- psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
- psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
- psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
- psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
- psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
- psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
- psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
- psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
- psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
- psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
- psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
- psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
- psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
- psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
- psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
- psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
- psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
- psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
- psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
- psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
- psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
- psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
- psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
- psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
-
- serdes_illcalib(0, 0, 3, 0, 4, 0, 4, 0);
- psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U);
- psu_mask_write(0xFD410014, 0x00000007U, 0x00000003U);
- psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U);
- psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
- psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
- psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
- psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
- psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U);
- psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
- psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U);
-
- return 1;
-}
-
-static unsigned long psu_resetout_init_data(void)
-{
- psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
- psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
- psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
- psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
- psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
- psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
- psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
- psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
- psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
- psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
- psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
- psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
- psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
- mask_poll(0xFD4063E4, 0x00000010U);
- mask_poll(0xFD40A3E4, 0x00000010U);
-
- return 1;
-}
-
-static unsigned long psu_resetin_init_data(void)
-{
- psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
- psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
- psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
- psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
- psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
-
- return 1;
-}
-
static unsigned long psu_afi_config(void)
{
psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 309f24a..f162803 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -384,37 +384,16 @@
return 0;
}
-int board_late_init(void)
+static int boot_targets_setup(void)
{
u8 bootmode;
struct udevice *dev;
int bootseq = -1;
int bootseq_len = 0;
int env_targets_len = 0;
- const char *mode;
+ const char *mode = NULL;
char *new_targets;
char *env_targets;
- int ret, multiboot;
-
-#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
- usb_ether_init();
-#endif
-
- if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
- debug("Saved variables - Skipping\n");
- return 0;
- }
-
- if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
- return 0;
-
- ret = set_fdtfile();
- if (ret)
- return ret;
-
- multiboot = multi_boot();
- if (multiboot >= 0)
- env_set_hex("multiboot", multiboot);
bootmode = zynqmp_get_bootmode();
@@ -442,8 +421,8 @@
"mmc@ff160000", &dev) &&
uclass_get_device_by_name(UCLASS_MMC,
"sdhci@ff160000", &dev)) {
- puts("Boot from EMMC but without SD0 enabled!\n");
- return -1;
+ debug("SD0 driver for SD0 device is not present\n");
+ break;
}
debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
@@ -457,8 +436,8 @@
"mmc@ff160000", &dev) &&
uclass_get_device_by_name(UCLASS_MMC,
"sdhci@ff160000", &dev)) {
- puts("Boot from SD0 but without SD0 enabled!\n");
- return -1;
+ debug("SD0 driver for SD0 device is not present\n");
+ break;
}
debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
@@ -475,8 +454,8 @@
"mmc@ff170000", &dev) &&
uclass_get_device_by_name(UCLASS_MMC,
"sdhci@ff170000", &dev)) {
- puts("Boot from SD1 but without SD1 enabled!\n");
- return -1;
+ debug("SD1 driver for SD1 device is not present\n");
+ break;
}
debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
@@ -490,39 +469,73 @@
env_set("modeboot", "nandboot");
break;
default:
- mode = "";
printf("Invalid Boot Mode:0x%x\n", bootmode);
break;
}
- if (bootseq >= 0) {
- bootseq_len = snprintf(NULL, 0, "%i", bootseq);
- debug("Bootseq len: %x\n", bootseq_len);
- env_set_hex("bootseq", bootseq);
+ if (mode) {
+ if (bootseq >= 0) {
+ bootseq_len = snprintf(NULL, 0, "%i", bootseq);
+ debug("Bootseq len: %x\n", bootseq_len);
+ env_set_hex("bootseq", bootseq);
+ }
+
+ /*
+ * One terminating char + one byte for space between mode
+ * and default boot_targets
+ */
+ env_targets = env_get("boot_targets");
+ if (env_targets)
+ env_targets_len = strlen(env_targets);
+
+ new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
+ bootseq_len);
+ if (!new_targets)
+ return -ENOMEM;
+
+ if (bootseq >= 0)
+ sprintf(new_targets, "%s%x %s", mode, bootseq,
+ env_targets ? env_targets : "");
+ else
+ sprintf(new_targets, "%s %s", mode,
+ env_targets ? env_targets : "");
+
+ env_set("boot_targets", new_targets);
+ free(new_targets);
}
- /*
- * One terminating char + one byte for space between mode
- * and default boot_targets
- */
- env_targets = env_get("boot_targets");
- if (env_targets)
- env_targets_len = strlen(env_targets);
+ return 0;
+}
- new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
- bootseq_len);
- if (!new_targets)
- return -ENOMEM;
+int board_late_init(void)
+{
+ int ret, multiboot;
- if (bootseq >= 0)
- sprintf(new_targets, "%s%x %s", mode, bootseq,
- env_targets ? env_targets : "");
- else
- sprintf(new_targets, "%s %s", mode,
- env_targets ? env_targets : "");
+#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
+ usb_ether_init();
+#endif
- env_set("boot_targets", new_targets);
- free(new_targets);
+ if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
+ debug("Saved variables - Skipping\n");
+ return 0;
+ }
+
+ if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
+ return 0;
+
+ ret = set_fdtfile();
+ if (ret)
+ return ret;
+
+ multiboot = multi_boot();
+ if (multiboot >= 0)
+ env_set_hex("multiboot", multiboot);
+
+ if (IS_ENABLED(CONFIG_DISTRO_DEFAULTS)) {
+ ret = boot_targets_setup();
+ if (ret)
+ return ret;
+ }
reset_reason();
diff --git a/board/zyxel/nsa325/Kconfig b/board/zyxel/nsa325/Kconfig
new file mode 100644
index 0000000..1fe5ead
--- /dev/null
+++ b/board/zyxel/nsa325/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NSA325
+
+config SYS_BOARD
+ default "nsa325"
+
+config SYS_VENDOR
+ default "zyxel"
+
+config SYS_CONFIG_NAME
+ default "nsa325"
+
+endif
diff --git a/board/zyxel/nsa325/MAINTAINERS b/board/zyxel/nsa325/MAINTAINERS
new file mode 100644
index 0000000..013cb84
--- /dev/null
+++ b/board/zyxel/nsa325/MAINTAINERS
@@ -0,0 +1,9 @@
+NSA325 BOARD
+M: Tony Dinh <mibodhi@gmail.com>
+S: Maintained
+F: arch/arm/dts/kirkwood-6282.dtsi
+F: arch/arm/dts/kirkwood-nsa325.dts
+F: arch/arm/dts/kirkwood-nsa3x0-common.dtsi
+F: board/zyxel/nsa325/
+F: include/configs/nsa325.h
+F: configs/nsa325_defconfig
diff --git a/board/zyxel/nsa325/Makefile b/board/zyxel/nsa325/Makefile
new file mode 100644
index 0000000..2887ba2
--- /dev/null
+++ b/board/zyxel/nsa325/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2015-2023 Tony Dinh <mibodhi@gmail.com>
+#
+# Based on
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+
+obj-y := nsa325.o
diff --git a/board/zyxel/nsa325/kwbimage.cfg b/board/zyxel/nsa325/kwbimage.cfg
new file mode 100644
index 0000000..a497300
--- /dev/null
+++ b/board/zyxel/nsa325/kwbimage.cfg
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015-2023 Tony Dinh <mibodhi@gmail.com>
+#
+# Extracted from Zyxel GPL source for u-boot-1.1.4_NSA325v2
+#
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization
+DATA 0xFFD01400 0x4301503E # DDR Configuration register
+DATA 0xFFD01404 0xB9843000 # DDR Controller Control Low
+DATA 0xFFD01408 0x33137777 # DDR Timing (Low)
+DATA 0xFFD0140C 0x16000C55 # DDR Timing (High)
+DATA 0xFFD01410 0x04000000 # DDR Address Control
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+DATA 0xFFD01418 0x00000000 # DDR Operation
+DATA 0xFFD0141C 0x00000672 # DDR Mode
+DATA 0xFFD01420 0x00000004 # DDR Extended Mode
+DATA 0xFFD01424 0x0000F14F # DDR Controller Control High
+DATA 0xFFD01428 0x000D6720 # DDR3 ODT Read Timing
+DATA 0xFFD0147C 0x0000B571 # DDR2 ODT Write Timing
+DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size
+DATA 0xFFD01508 0x20000000 # CS[1]n Base address to 512Mb
+DATA 0xFFD0150C 0x1FFFFFF4 # CS[1]n Size 512Mb Window enabled for CS1
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+DATA 0xFFD01494 0x00120000 # DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
+
+DATA 0xFFD015D0 0x00000630
+DATA 0xFFD015D4 0x00000046
+DATA 0xFFD015D8 0x00000008
+DATA 0xFFD015DC 0x00000000
+DATA 0xFFD015E0 0x00000023
+DATA 0xFFD015E4 0x00203C18
+DATA 0xFFD01620 0x00384800
+DATA 0xFFD01480 0x00000001
+DATA 0xFFD20134 0x66666666
+DATA 0xFFD20138 0x00066666
+
+DATA 0xFFD10100 0x00004000 # stop the watchdog
+DATA 0xFFD10104 0xFFFFBFFF
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/zyxel/nsa325/nsa325.c b/board/zyxel/nsa325/nsa325.c
new file mode 100644
index 0000000..f5f63ee
--- /dev/null
+++ b/board/zyxel/nsa325/nsa325.c
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014-2023 Tony Dinh <mibodhi@gmail.com>
+ *
+ * Based on
+ * Copyright (C) 2014 Jason Plum <jplum@archlinuxarm.org>
+ *
+ * Based on nsa320.c originall written by
+ * Copyright (C) 2012 Peter Schildmann <linux@schildmann.info>
+ *
+ * Based on guruplug.c originally written by
+ * Siddarth Gore <gores@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ */
+
+#include <common.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include <bootstage.h>
+#include <command.h>
+#include <init.h>
+#include <linux/bitops.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* low GPIO's */
+#define HDD2_GREEN_LED BIT(12)
+#define HDD2_RED_LED BIT(13)
+#define USB_GREEN_LED BIT(15)
+#define USB_POWER BIT(21)
+#define SYS_GREEN_LED BIT(28)
+#define SYS_ORANGE_LED BIT(29)
+
+#define PIN_USB_GREEN_LED 15
+#define PIN_USB_POWER 21
+
+#define NSA325_OE_LOW (~(HDD2_GREEN_LED | HDD2_RED_LED | \
+ USB_GREEN_LED | USB_POWER | \
+ SYS_GREEN_LED | SYS_ORANGE_LED))
+#define NSA325_VAL_LOW (SYS_GREEN_LED | USB_POWER)
+
+/* high GPIO's */
+#define COPY_GREEN_LED BIT(7)
+#define COPY_RED_LED BIT(8)
+#define HDD1_GREEN_LED BIT(9)
+#define HDD1_RED_LED BIT(10)
+#define HDD2_POWER BIT(15)
+#define WATCHDOG_SIGNAL BIT(14)
+
+#define NSA325_OE_HIGH (~(COPY_GREEN_LED | COPY_RED_LED | \
+ HDD1_GREEN_LED | HDD1_RED_LED | HDD2_POWER | WATCHDOG_SIGNAL))
+#define NSA325_VAL_HIGH (WATCHDOG_SIGNAL | HDD2_POWER)
+
+#define BTN_POWER 46
+#define BTN_RESET 36
+#define BTN_COPY 37
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(NSA325_VAL_LOW, NSA325_VAL_HIGH,
+ NSA325_OE_LOW, NSA325_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ /* (all LEDs & power off active high) */
+ u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA, /* PCF8563 RTC chip */
+ MPP9_TW_SCK, /* connected to TWSI */
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO, /* HDD2 LED (green) */
+ MPP13_GPIO, /* HDD2 LED (red) */
+ MPP14_GPIO, /* MCU DATA pin (in) */
+ MPP15_GPIO, /* USB LED (green) */
+ MPP16_GPIO, /* MCU CLK pin (out) */
+ MPP17_GPIO, /* MCU ACT pin (out) */
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GPIO,
+ MPP21_GPIO, /* USB power */
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO, /* SYS LED (green) */
+ MPP29_GPIO, /* SYS LED (orange) */
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ MPP36_GPIO, /* reset button */
+ MPP37_GPIO, /* copy button */
+ MPP38_GPIO, /* VID B0 */
+ MPP39_GPIO, /* COPY LED (green) */
+ MPP40_GPIO, /* COPY LED (red) */
+ MPP41_GPIO, /* HDD1 LED (green) */
+ MPP42_GPIO, /* HDD1 LED (red) */
+ MPP43_GPIO, /* HTP pin */
+ MPP44_GPIO, /* buzzer */
+ MPP45_GPIO, /* VID B1 */
+ MPP46_GPIO, /* power button */
+ MPP47_GPIO, /* HDD2 power */
+ MPP48_GPIO, /* power off */
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+ return cpu_eth_init(bis);
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ /* Do late init to ensure successful enumeration of XHCI devices */
+ pci_init();
+ return 0;
+}
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int val)
+{
+ struct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
+ u32 dout0 = readl(&gpio0->dout);
+ u32 blen0 = readl(&gpio0->blink_en);
+
+ struct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
+ u32 dout1 = readl(&gpio1->dout);
+ u32 blen1 = readl(&gpio1->blink_en);
+
+ switch (val) {
+ case BOOTSTAGE_ID_DECOMP_IMAGE:
+ writel(blen0 & ~(SYS_GREEN_LED | SYS_ORANGE_LED), &gpio0->blink_en);
+ writel((dout0 & ~SYS_GREEN_LED) | SYS_ORANGE_LED, &gpio0->dout);
+ break;
+ case BOOTSTAGE_ID_RUN_OS:
+ writel(dout0 & ~SYS_ORANGE_LED, &gpio0->dout);
+ writel(blen0 | SYS_GREEN_LED, &gpio0->blink_en);
+ break;
+ case BOOTSTAGE_ID_NET_START:
+ writel(dout1 & ~COPY_RED_LED, &gpio1->dout);
+ writel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en);
+ break;
+ case BOOTSTAGE_ID_NET_LOADED:
+ writel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en);
+ writel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout);
+ break;
+ case -BOOTSTAGE_ID_NET_NETLOOP_OK:
+ case -BOOTSTAGE_ID_NET_LOADED:
+ writel(dout1 & ~COPY_GREEN_LED, &gpio1->dout);
+ writel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en);
+ break;
+ default:
+ if (val < 0) {
+ /* error */
+ printf("Error occurred, error code = %d\n", -val);
+ writel(dout0 & ~SYS_GREEN_LED, &gpio0->dout);
+ writel(blen0 | SYS_ORANGE_LED, &gpio0->blink_en);
+ }
+ break;
+ }
+}
+#endif /* CONFIG_SHOW_BOOT_PROGRESS */
diff --git a/boot/Kconfig b/boot/Kconfig
index e3f1b7e..1d2b073 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -3,14 +3,25 @@
menu "Boot images"
config ANDROID_BOOT_IMAGE
- bool "Enable support for Android Boot Images"
+ bool "Android Boot Images"
default y if FASTBOOT
help
This enables support for booting images which use the Android
image format header.
-config FIT
- bool "Support Flattened Image Tree"
+config TIMESTAMP
+ bool "Show image date and time when displaying image information"
+ default y if CMD_DATE
+ help
+ When CONFIG_TIMESTAMP is selected, the timestamp (date and time) of
+ an image is printed by image commands like bootm or iminfo. This
+ is shown as 'Timestamp: xxx' and 'Created: xxx'. If this option is
+ enabled, then U-Boot requires FITs to have a timestamp. If a FIT is
+ loaded that does not, the message 'Wrong FIT format: no timestamp'
+ is shown.
+
+menuconfig FIT
+ bool "Flattened Image Tree (FIT)"
select HASH
select MD5
select SHA1
@@ -25,20 +36,10 @@
multiple configurations, verification through hashing and also
verified boot (secure boot using RSA).
-config TIMESTAMP
- bool "Show image date and time when displaying image information"
- default y if CMD_DATE
- help
- When CONFIG_TIMESTAMP is selected, the timestamp (date and time) of
- an image is printed by image commands like bootm or iminfo. This
- is shown as 'Timestamp: xxx' and 'Created: xxx'. If this option is
- enabled, then U-Boot requires FITs to have a timestamp. If a FIT is
- loaded that does not, the message 'Wrong FIT format: no timestamp'
- is shown.
+if FIT
config FIT_EXTERNAL_OFFSET
hex "FIT external data offset"
- depends on FIT
default 0x0
help
This specifies a data offset in fit image.
@@ -49,7 +50,6 @@
config FIT_FULL_CHECK
bool "Do a full check of the FIT before using it"
- depends on FIT
default y
help
Enable this do a full check of the FIT to make sure it is valid. This
@@ -59,7 +59,7 @@
config FIT_SIGNATURE
bool "Enable signature verification of FIT uImages"
- depends on DM && FIT
+ depends on DM
select HASH
imply RSA
imply RSA_VERIFY
@@ -97,7 +97,7 @@
config FIT_CIPHER
bool "Enable ciphering data in a FIT uImages"
- depends on DM && FIT
+ depends on DM
select AES
help
Enable the feature of data ciphering/unciphering in the tool mkimage
@@ -105,7 +105,6 @@
config FIT_VERBOSE
bool "Show verbose messages when FIT images fail"
- depends on FIT
help
Generally a system will have valid FIT images so debug messages
are a waste of code space. If you are debugging your images then
@@ -114,7 +113,6 @@
config FIT_BEST_MATCH
bool "Select the best match for the kernel device tree"
- depends on FIT
help
When no configuration is explicitly selected, default to the
one whose fdt's compatibility field best matches that of
@@ -124,7 +122,6 @@
config FIT_IMAGE_POST_PROCESS
bool "Enable post-processing of FIT artifacts after loading by U-Boot"
- depends on FIT
depends on SOCFPGA_SECURE_VAB_AUTH
help
Allows doing any sort of manipulation to blobs after they got extracted
@@ -139,14 +136,13 @@
config FIT_PRINT
bool "Support FIT printing"
- depends on FIT
default y
help
Support printing the content of the fitImage in a verbose manner.
config SPL_FIT
bool "Support Flattened Image Tree within SPL"
- depends on SPL && FIT
+ depends on SPL
select SPL_HASH
select SPL_OF_LIBFDT
@@ -197,7 +193,7 @@
config SPL_LOAD_FIT
bool "Enable SPL loading U-Boot as a FIT (basic fitImage features)"
- depends on SPL && FIT
+ depends on SPL
select SPL_FIT
help
Normally with the SPL framework a legacy image is generated as part
@@ -219,7 +215,7 @@
config SPL_LOAD_FIT_ADDRESS
hex "load address of fit image"
- depends on SPL_LOAD_FIT || SPL_RAM_SUPPORT || TPL_RAM_SUPPORT
+ depends on SPL_LOAD_FIT
default 0x0
help
Specify the load address of the fit image that will be loaded
@@ -245,7 +241,6 @@
config SPL_LOAD_FIT_FULL
bool "Enable SPL loading U-Boot as a FIT (full fitImage features)"
- depends on FIT
select SPL_FIT
help
Normally with the SPL framework a legacy image is generated as part
@@ -343,6 +338,8 @@
endif # VPL
+endif # FIT
+
config PXE_UTILS
bool
select MENU
@@ -375,8 +372,8 @@
of U-Boot to boot various images. Currently much functionality is
tied to enabling the command that exercises it.
-config BOOTSTD
- bool "Standard boot support"
+menuconfig BOOTSTD
+ bool "Standard boot"
default y
depends on DM && OF_CONTROL && BLK
help
@@ -396,6 +393,8 @@
U-Boot)
- bootflow - a description of how to boot (owned by the distro)
+if BOOTSTD
+
config SPL_BOOTSTD
bool "Standard boot support in SPL"
depends on SPL && SPL_DM && SPL_OF_CONTROL && SPL_BLK
@@ -416,8 +415,6 @@
boot. It is enabled by default since the main purpose of VPL is to
handle the firmware part of VBE.
-if BOOTSTD
-
config BOOTSTD_FULL
bool "Enhanced features for standard boot"
default y if SANDBOX
@@ -464,8 +461,11 @@
config BOOTMETH_CROS
bool "Bootdev support for Chromium OS"
- depends on X86 || SANDBOX
- default y
+ depends on X86 || ARM || SANDBOX
+ default y if !ARM
+ select EFI_PARTITION
+ select PARTITION_TYPE_GUID
+ select PARTITION_UUIDS
help
Enables support for booting Chromium OS using bootdevs. This uses the
kernel A slot and obtains the kernel command line from the parameters
@@ -673,7 +673,7 @@
This provides a way to try out standard boot on an existing boot flow.
It is not enabled by default to save space.
-endif
+endif # BOOTSTD
config LEGACY_IMAGE_FORMAT
bool "Enable support for the legacy image format"
@@ -685,6 +685,38 @@
loaded. If a board needs the legacy image format support in this
case, enable it here.
+config MEASURED_BOOT
+ bool "Measure boot images and configuration when booting without EFI"
+ depends on HASH && TPM_V2
+ help
+ This option enables measurement of the boot process when booting
+ without UEFI . Measurement involves creating cryptographic hashes
+ of the binary images that are booting and storing them in the TPM.
+ In addition, a log of these hashes is stored in memory for the OS
+ to verify the booted images and configuration. Enable this if the
+ OS has configured some memory area for the event log and you intend
+ to use some attestation tools on your system.
+
+if MEASURED_BOOT
+ config MEASURE_DEVICETREE
+ bool "Measure the devicetree image"
+ default y if MEASURED_BOOT
+ help
+ On some platforms, the devicetree is not static as it may contain
+ random MAC addresses or other such data that changes each boot.
+ Therefore, it should not be measured into the TPM. In that case,
+ disable the measurement here.
+
+ config MEASURE_IGNORE_LOG
+ bool "Ignore the existing event log"
+ default n
+ help
+ On platforms that use an event log memory region that persists
+ through system resets and are the first stage bootloader, then
+ this option should be enabled to ignore any existing data in the
+ event log memory region.
+endif # MEASURED_BOOT
+
config SUPPORT_RAW_INITRD
bool "Enable raw initrd images"
help
@@ -693,108 +725,6 @@
address of the initrd must be augmented by it's size, in the following
format: "<initrd address>:<initrd size>".
-config OF_BOARD_SETUP
- bool "Set up board-specific details in device tree before boot"
- depends on OF_LIBFDT
- help
- This causes U-Boot to call ft_board_setup() before booting into
- the Operating System. This function can set up various
- board-specific information in the device tree for use by the OS.
- The device tree is then passed to the OS.
-
-config OF_SYSTEM_SETUP
- bool "Set up system-specific details in device tree before boot"
- depends on OF_LIBFDT
- help
- This causes U-Boot to call ft_system_setup() before booting into
- the Operating System. This function can set up various
- system-specific information in the device tree for use by the OS.
- The device tree is then passed to the OS.
-
-config OF_STDOUT_VIA_ALIAS
- bool "Update the device-tree stdout alias from U-Boot"
- depends on OF_LIBFDT
- help
- This uses U-Boot's serial alias from the aliases node to update
- the device tree passed to the OS. The "linux,stdout-path" property
- in the chosen node is set to point to the correct serial node.
- This option currently references CONFIG_CONS_INDEX, which is
- incorrect when used with device tree as this option does not
- exist / should not be used.
-
-config HAVE_TEXT_BASE
- bool
- depends on !NIOS2 && !XTENSA
- depends on !EFI_APP
- default y
-
-config TEXT_BASE
- depends on HAVE_TEXT_BASE
- default 0x0 if POSITION_INDEPENDENT
- default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3
- default 0x81700000 if MACH_SUNIV
- default 0x2a000000 if MACH_SUN9I
- default 0x4a000000 if SUNXI_MINIMUM_DRAM_MB >= 256
- default 0x42e00000 if SUNXI_MINIMUM_DRAM_MB >= 64
- hex "Text Base"
- help
- The address in memory that U-Boot will be running from, initially.
-
-config HAVE_SYS_MONITOR_BASE
- bool
- depends on ARC || MIPS || M68K || NIOS2 || PPC || XTENSA || X86 \
- || ENV_IS_IN_FLASH || MTD_NOR_FLASH
- depends on !EFI_APP
- default y
-
-config SYS_MONITOR_BASE
- depends on HAVE_SYS_MONITOR_BASE
- hex "Physical start address of boot monitor code"
- default TEXT_BASE
- help
- The physical start address of boot monitor code (which is the same as
- CONFIG_TEXT_BASE when linking) and the same as CFG_SYS_FLASH_BASE
- when booting from flash.
-
-config SPL_SYS_MONITOR_BASE
- depends on MPC85xx && SPL && HAVE_SYS_MONITOR_BASE
- hex "Physical start address of SPL monitor code"
- default SPL_TEXT_BASE
-
-config TPL_SYS_MONITOR_BASE
- depends on MPC85xx && TPL && HAVE_SYS_MONITOR_BASE
- hex "Physical start address of TPL monitor code"
-
-config DYNAMIC_SYS_CLK_FREQ
- bool "Determine CPU clock frequency at run-time"
- help
- Implement a get_board_sys_clk function that will determine the CPU
- clock frequency at run time, rather than define it statically.
-
-config SYS_CLK_FREQ
- depends on !DYNAMIC_SYS_CLK_FREQ
- int "CPU clock frequency"
- default 125000000 if ARCH_LS1012A
- default 100000000 if ARCH_P2020 || ARCH_T1024 || ARCH_T1042 || \
- ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
- default 66666666 if ARCH_P1010 || ARCH_P1020 || ARCH_T4240
- default 66660000 if ARCH_T2080
- default 33333333 if RCAR_GEN3
- default 24000000 if ARCH_EXYNOS
- default 20000000 if RCAR_GEN2
- default 0
- help
- A static value for the CPU frequency. Note that if not required
- for a given SoC, this can be left at 0.
-
-config ARCH_FIXUP_FDT_MEMORY
- bool "Enable arch_fixup_memory_banks() call"
- default y
- help
- Enable FDT memory map syncup before OS boot. This feature can be
- used for booting OS with different memory setup where the part of
- the memory location should be used for different purpose.
-
config CHROMEOS
bool "Support booting Chrome OS"
help
@@ -878,7 +808,7 @@
endmenu # Boot images
config DISTRO_DEFAULTS
- bool "Select defaults suitable for booting general purpose Linux distributions"
+ bool "(deprecated) Script-based booting of Linux distributions"
select BOOT_DEFAULTS
select AUTO_COMPLETE
select CMDLINE_EDITING
@@ -886,6 +816,10 @@
select HUSH_PARSER
select SYS_LONGHELP
help
+ Note: These scripts have been replaced by Standard Boot. Do not use
+ them on new boards. See 'Migrating from distro_boot' at
+ doc/develop/bootstd.rst
+
Select this to enable various options and commands which are suitable
for building u-boot for booting general purpose Linux distributions.
@@ -1007,7 +941,7 @@
config BOOTSTAGE_STASH_ADDR
hex "Address to stash boot timing information"
- default 0
+ default 0x0
help
Provide an address which will not be overwritten by the OS when it
starts, so that it can read this information when ready.
@@ -1535,6 +1469,63 @@
endmenu
+if OF_LIBFDT
+
+menu "Devicetree fixup"
+
+config OF_BOARD_SETUP
+ bool "Set up board-specific details in device tree before boot"
+ help
+ This causes U-Boot to call ft_board_setup() before booting into
+ the Operating System. This function can set up various
+ board-specific information in the device tree for use by the OS.
+ The device tree is then passed to the OS.
+
+config OF_SYSTEM_SETUP
+ bool "Set up system-specific details in device tree before boot"
+ help
+ This causes U-Boot to call ft_system_setup() before booting into
+ the Operating System. This function can set up various
+ system-specific information in the device tree for use by the OS.
+ The device tree is then passed to the OS.
+
+config OF_STDOUT_VIA_ALIAS
+ bool "Update the device-tree stdout alias from U-Boot"
+ help
+ This uses U-Boot's serial alias from the aliases node to update
+ the device tree passed to the OS. The "linux,stdout-path" property
+ in the chosen node is set to point to the correct serial node.
+ This option currently references CONFIG_CONS_INDEX, which is
+ incorrect when used with device tree as this option does not
+ exist / should not be used.
+
+config FDT_FIXUP_PARTITIONS
+ bool "Overwrite MTD partitions in DTS through defined in 'mtdparts'"
+ help
+ Allow overwriting defined partitions in the device tree blob
+ using partition info defined in the 'mtdparts' environment
+ variable.
+
+config FDT_SIMPLEFB
+ bool "FDT tools for simplefb support"
+ help
+ Enable the fdt tools to manage the simple fb nodes in device tree.
+ These functions can be used by board to indicate to the OS
+ the presence of the simple frame buffer with associated reserved
+ memory
+
+config ARCH_FIXUP_FDT_MEMORY
+ bool "Enable arch_fixup_memory_banks() call"
+ default y
+ help
+ Enable FDT memory map syncup before OS boot. This feature can be
+ used for booting OS with different memory setup where the part of
+ the memory location should be used for different purpose.
+
+endmenu
+
+endif # OF_LIBFDT
+
config USE_BOOTARGS
bool "Enable boot arguments"
help
diff --git a/boot/Makefile b/boot/Makefile
index 33fd599..51811cf 100644
--- a/boot/Makefile
+++ b/boot/Makefile
@@ -16,6 +16,7 @@
endif
obj-y += image.o image-board.o
+
obj-$(CONFIG_ANDROID_AB) += android_ab.o
obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o image-android-dt.o
obj-$(CONFIG_ANDROID_BOOTLOADER) += android_bootloader.o
@@ -41,6 +42,9 @@
obj-$(CONFIG_$(SPL_TPL_)CEDIT) += cedit.o
endif
+obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o
+obj-$(CONFIG_$(SPL_TPL_)FDT_SIMPLEFB) += fdt_simplefb.o
+
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += image-fdt.o
obj-$(CONFIG_$(SPL_TPL_)FIT_SIGNATURE) += fdt_region.o
obj-$(CONFIG_$(SPL_TPL_)FIT) += image-fit.o
@@ -56,7 +60,8 @@
obj-$(CONFIG_SPL_LOAD_FIT) += common_fit.o
endif
-obj-$(CONFIG_$(SPL_TPL_)EXPO) += expo.o scene.o scene_menu.o expo_build.o
+obj-$(CONFIG_$(SPL_TPL_)EXPO) += expo.o scene.o expo_build.o
+obj-$(CONFIG_$(SPL_TPL_)EXPO) += scene_menu.o scene_textline.o
obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_VBE) += vbe.o
obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_VBE_REQUEST) += vbe_request.o
diff --git a/boot/android_ab.c b/boot/android_ab.c
index bd695be..ab7c469 100644
--- a/boot/android_ab.c
+++ b/boot/android_ab.c
@@ -12,7 +12,6 @@
#include <memalign.h>
#include <linux/err.h>
#include <u-boot/crc.h>
-#include <u-boot/crc.h>
/**
* Compute the CRC-32 of the bootloader control struct.
diff --git a/boot/bootdev-uclass.c b/boot/bootdev-uclass.c
index fa52bc3..4926a50 100644
--- a/boot/bootdev-uclass.c
+++ b/boot/bootdev-uclass.c
@@ -111,6 +111,8 @@
int bootdev_find_in_blk(struct udevice *dev, struct udevice *blk,
struct bootflow_iter *iter, struct bootflow *bflow)
{
+ struct bootmeth_uc_plat *plat = dev_get_uclass_plat(bflow->method);
+ bool allow_any_part = plat->flags & BOOTMETHF_ANY_PART;
struct blk_desc *desc = dev_get_uclass_plat(blk);
struct disk_partition info;
char partstr[20];
@@ -142,6 +144,7 @@
* us whether there is valid media there
*/
ret = part_get_info(desc, iter->part, &info);
+ log_debug("part_get_info() returned %d\n", ret);
if (!iter->part && ret == -ENOENT)
ret = 0;
@@ -154,7 +157,7 @@
ret = -ESHUTDOWN;
else
bflow->state = BOOTFLOWST_MEDIA;
- if (ret) {
+ if (ret && !allow_any_part) {
/* allow partition 1 to be missing */
if (iter->part == 1) {
iter->max_part = 3;
@@ -174,9 +177,15 @@
if (!iter->part) {
iter->first_bootable = part_get_bootable(desc);
log_debug("checking bootable=%d\n", iter->first_bootable);
+ } else if (allow_any_part) {
+ /*
+ * allow any partition to be scanned, by skipping any checks
+ * for filesystems or partition contents on this disk
+ */
/* if there are bootable partitions, scan only those */
- } else if (iter->first_bootable ? !info.bootable : iter->part != 1) {
+ } else if (iter->first_bootable >= 0 &&
+ (iter->first_bootable ? !info.bootable : iter->part != 1)) {
return log_msg_ret("boot", -EINVAL);
} else {
ret = fs_set_blk_dev_with_part(desc, bflow->part);
@@ -184,16 +193,16 @@
if (ret)
return log_msg_ret("fs", ret);
- /* Use an #ifdef due to info.sys_ind */
-#ifdef CONFIG_DOS_PARTITION
log_debug("%s: Found partition %x type %x fstype %d\n",
- blk->name, bflow->part, info.sys_ind,
+ blk->name, bflow->part,
+ IS_ENABLED(CONFIG_DOS_PARTITION) ?
+ disk_partition_sys_ind(&info) : 0,
ret ? -1 : fs_get_type());
-#endif
bflow->blk = blk;
bflow->state = BOOTFLOWST_FS;
}
+ log_debug("method %s\n", bflow->method->name);
ret = bootmeth_read_bootflow(bflow->method, bflow);
if (ret)
return log_msg_ret("method", ret);
@@ -460,10 +469,11 @@
* if no sequence number was provided, we must scan all
* bootdevs for this media uclass
*/
- if (IS_ENABLED(CONFIG_BOOTSTD_FULL) && seq == -1)
+ if (seq == -1)
method_flags |= BOOTFLOW_METHF_SINGLE_UCLASS;
if (method_flagsp)
*method_flagsp = method_flags;
+ log_debug("method flags %x\n", method_flags);
return 0;
}
log_debug("- no device in %s\n", media->name);
@@ -560,7 +570,8 @@
{
const struct bootdev_ops *ops = bootdev_get_ops(dev);
- log_debug("->get_bootflow %s=%p\n", dev->name, ops->get_bootflow);
+ log_debug("->get_bootflow %s,%x=%p\n", dev->name, iter->part,
+ ops->get_bootflow);
bootflow_init(bflow, dev, iter->method);
if (!ops->get_bootflow)
return default_get_bootflow(dev, iter, bflow);
@@ -773,7 +784,7 @@
if (info->hunt) {
ret = info->hunt(info, show);
log_debug(" - hunt result %d\n", ret);
- if (ret)
+ if (ret && ret != -ENOENT)
return ret;
}
std->hunters_used |= BIT(seq);
@@ -820,6 +831,33 @@
return result;
}
+int bootdev_unhunt(enum uclass_id id)
+{
+ struct bootdev_hunter *start;
+ int n_ent, i;
+
+ start = ll_entry_start(struct bootdev_hunter, bootdev_hunter);
+ n_ent = ll_entry_count(struct bootdev_hunter, bootdev_hunter);
+ for (i = 0; i < n_ent; i++) {
+ struct bootdev_hunter *info = start + i;
+
+ if (info->uclass == id) {
+ struct bootstd_priv *std;
+ int ret;
+
+ ret = bootstd_get_priv(&std);
+ if (ret)
+ return log_msg_ret("std", ret);
+ if (!(std->hunters_used & BIT(i)))
+ return -EALREADY;
+ std->hunters_used &= ~BIT(i);
+ return 0;
+ }
+ }
+
+ return -ENOENT;
+}
+
int bootdev_hunt_prio(enum bootdev_prio_t prio, bool show)
{
struct bootdev_hunter *start;
diff --git a/boot/bootflow.c b/boot/bootflow.c
index 81b5829..1ea2966 100644
--- a/boot/bootflow.c
+++ b/boot/bootflow.c
@@ -156,6 +156,27 @@
}
/**
+ * scan_next_in_uclass() - Scan for the next bootdev in the same media uclass
+ *
+ * Move through the following bootdevs until we find another in this media
+ * uclass, or run out
+ *
+ * @devp: On entry, the device to check, on exit the new device, or NULL if
+ * there is none
+ */
+static void scan_next_in_uclass(struct udevice **devp)
+{
+ struct udevice *dev = *devp;
+ enum uclass_id cur_id = device_get_uclass_id(dev->parent);
+
+ do {
+ uclass_find_next_device(&dev);
+ } while (dev && cur_id != device_get_uclass_id(dev->parent));
+
+ *devp = dev;
+}
+
+/**
* iter_incr() - Move to the next item (method, part, bootdev)
*
* Return: 0 if OK, BF_NO_MORE_DEVICES if there are no more bootdevs
@@ -230,8 +251,7 @@
&method_flags);
} else if (IS_ENABLED(CONFIG_BOOTSTD_FULL) &&
(iter->flags & BOOTFLOWIF_SINGLE_UCLASS)) {
- /* Move to the next bootdev in this uclass */
- uclass_find_next_device(&dev);
+ scan_next_in_uclass(&dev);
if (!dev) {
log_debug("finished uclass %s\n",
dev_get_uclass_name(dev));
@@ -260,8 +280,26 @@
} else {
log_debug("labels %p\n", iter->labels);
if (iter->labels) {
- ret = bootdev_next_label(iter, &dev,
- &method_flags);
+ /*
+ * when the label is "mmc" we want to scan all
+ * mmc bootdevs, not just the first. See
+ * bootdev_find_by_label() where this flag is
+ * set up
+ */
+ if (iter->method_flags &
+ BOOTFLOW_METHF_SINGLE_UCLASS) {
+ scan_next_in_uclass(&dev);
+ log_debug("looking for next device %s: %s\n",
+ iter->dev->name,
+ dev ? dev->name : "<none>");
+ } else {
+ dev = NULL;
+ }
+ if (!dev) {
+ log_debug("looking at next label\n");
+ ret = bootdev_next_label(iter, &dev,
+ &method_flags);
+ }
} else {
ret = bootdev_next_prio(iter, &dev);
method_flags = 0;
@@ -429,9 +467,11 @@
free(bflow->name);
free(bflow->subdir);
free(bflow->fname);
- free(bflow->buf);
+ if (!(bflow->flags & BOOTFLOWF_STATIC_BUF))
+ free(bflow->buf);
free(bflow->os_name);
free(bflow->fdt_fname);
+ free(bflow->bootmeth_priv);
}
void bootflow_remove(struct bootflow *bflow)
@@ -444,6 +484,22 @@
free(bflow);
}
+#if CONFIG_IS_ENABLED(BOOTSTD_FULL)
+int bootflow_read_all(struct bootflow *bflow)
+{
+ int ret;
+
+ if (bflow->state != BOOTFLOWST_READY)
+ return log_msg_ret("rd", -EPROTO);
+
+ ret = bootmeth_read_all(bflow->method, bflow);
+ if (ret)
+ return log_msg_ret("rd2", ret);
+
+ return 0;
+}
+#endif /* BOOTSTD_FULL */
+
int bootflow_boot(struct bootflow *bflow)
{
int ret;
@@ -697,7 +753,7 @@
in_quote = false;
continue;
}
- if (*p == '=') {
+ if (*p == '=' && !arg_end) {
arg_end = p;
val = p + 1;
} else if (*p == '"') {
@@ -733,7 +789,8 @@
}
/* if this is the target arg, update it */
- if (!strncmp(from, set_arg, arg_end - from)) {
+ if (arg_end - from == set_arg_len &&
+ !strncmp(from, set_arg, set_arg_len)) {
if (!buf) {
bool has_quote = val_end[-1] == '"';
diff --git a/boot/bootm.c b/boot/bootm.c
index 08bb77f..87e0e12 100644
--- a/boot/bootm.c
+++ b/boot/bootm.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <bootstage.h>
#include <cli.h>
+#include <command.h>
#include <cpu_func.h>
#include <env.h>
#include <errno.h>
@@ -22,6 +23,7 @@
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/sizes.h>
+#include <tpm-v2.h>
#if defined(CONFIG_CMD_USB)
#include <usb.h>
#endif
@@ -29,7 +31,6 @@
#include "mkimage.h"
#endif
-#include <command.h>
#include <bootm.h>
#include <image.h>
@@ -660,6 +661,75 @@
return 0;
}
+int bootm_measure(struct bootm_headers *images)
+{
+ int ret = 0;
+
+ /* Skip measurement if EFI is going to do it */
+ if (images->os.os == IH_OS_EFI &&
+ IS_ENABLED(CONFIG_EFI_TCG2_PROTOCOL) &&
+ IS_ENABLED(CONFIG_BOOTM_EFI))
+ return ret;
+
+ if (IS_ENABLED(CONFIG_MEASURED_BOOT)) {
+ struct tcg2_event_log elog;
+ struct udevice *dev;
+ void *initrd_buf;
+ void *image_buf;
+ const char *s;
+ u32 rd_len;
+ bool ign;
+
+ elog.log_size = 0;
+ ign = IS_ENABLED(CONFIG_MEASURE_IGNORE_LOG);
+ ret = tcg2_measurement_init(&dev, &elog, ign);
+ if (ret)
+ return ret;
+
+ image_buf = map_sysmem(images->os.image_start,
+ images->os.image_len);
+ ret = tcg2_measure_data(dev, &elog, 8, images->os.image_len,
+ image_buf, EV_COMPACT_HASH,
+ strlen("linux") + 1, (u8 *)"linux");
+ if (ret)
+ goto unmap_image;
+
+ rd_len = images->rd_end - images->rd_start;
+ initrd_buf = map_sysmem(images->rd_start, rd_len);
+ ret = tcg2_measure_data(dev, &elog, 9, rd_len, initrd_buf,
+ EV_COMPACT_HASH, strlen("initrd") + 1,
+ (u8 *)"initrd");
+ if (ret)
+ goto unmap_initrd;
+
+ if (IS_ENABLED(CONFIG_MEASURE_DEVICETREE)) {
+ ret = tcg2_measure_data(dev, &elog, 0, images->ft_len,
+ (u8 *)images->ft_addr,
+ EV_TABLE_OF_DEVICES,
+ strlen("dts") + 1,
+ (u8 *)"dts");
+ if (ret)
+ goto unmap_initrd;
+ }
+
+ s = env_get("bootargs");
+ if (!s)
+ s = "";
+ ret = tcg2_measure_data(dev, &elog, 1, strlen(s) + 1, (u8 *)s,
+ EV_PLATFORM_CONFIG_FLAGS,
+ strlen(s) + 1, (u8 *)s);
+
+unmap_initrd:
+ unmap_sysmem(initrd_buf);
+
+unmap_image:
+ unmap_sysmem(image_buf);
+ tcg2_measurement_term(dev, &elog, ret != 0);
+ }
+
+ return ret;
+}
+
/**
* Execute selected states of the bootm command.
*
@@ -711,6 +781,10 @@
if (!ret && (states & BOOTM_STATE_FINDOTHER))
ret = bootm_find_other(cmdtp, flag, argc, argv);
+ if (IS_ENABLED(CONFIG_MEASURED_BOOT) && !ret &&
+ (states & BOOTM_STATE_MEASURE))
+ bootm_measure(images);
+
/* Load the OS */
if (!ret && (states & BOOTM_STATE_LOADOS)) {
iflag = bootm_disable_interrupts();
@@ -810,6 +884,43 @@
return ret;
}
+int bootm_boot_start(ulong addr, const char *cmdline)
+{
+ static struct cmd_tbl cmd = {"bootm"};
+ char addr_str[30];
+ char *argv[] = {addr_str, NULL};
+ int states;
+ int ret;
+
+ /*
+ * TODO(sjg@chromium.org): This uses the command-line interface, but
+ * should not. To clean this up, the various bootm states need to be
+ * passed an info structure instead of cmdline flags. Then this can
+ * set up the required info and move through the states without needing
+ * the command line.
+ */
+ states = BOOTM_STATE_START | BOOTM_STATE_FINDOS | BOOTM_STATE_PRE_LOAD |
+ BOOTM_STATE_FINDOTHER | BOOTM_STATE_LOADOS |
+ BOOTM_STATE_OS_PREP | BOOTM_STATE_OS_FAKE_GO |
+ BOOTM_STATE_OS_GO;
+ if (IS_ENABLED(CONFIG_SYS_BOOT_RAMDISK_HIGH))
+ states |= BOOTM_STATE_RAMDISK;
+ if (IS_ENABLED(CONFIG_PPC) || IS_ENABLED(CONFIG_MIPS))
+ states |= BOOTM_STATE_OS_CMDLINE;
+ images.state |= states;
+
+ snprintf(addr_str, sizeof(addr_str), "%lx", addr);
+
+ ret = env_set("bootargs", cmdline);
+ if (ret) {
+ printf("Failed to set cmdline\n");
+ return ret;
+ }
+ ret = do_bootm_states(&cmd, 0, 1, argv, states, &images, 1);
+
+ return ret;
+}
+
#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
/**
* image_get_kernel - verify legacy format kernel image
diff --git a/boot/bootm_os.c b/boot/bootm_os.c
index 99ff0e6..9c035b5 100644
--- a/boot/bootm_os.c
+++ b/boot/bootm_os.c
@@ -609,19 +609,5 @@
boot_os_fn *bootm_os_get_boot_func(int os)
{
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
- static bool relocated;
-
- if (!relocated) {
- int i;
-
- /* relocate boot function table */
- for (i = 0; i < ARRAY_SIZE(boot_os); i++)
- if (boot_os[i] != NULL)
- boot_os[i] += gd->reloc_off;
-
- relocated = true;
- }
-#endif
return boot_os[os];
}
diff --git a/boot/bootmeth-uclass.c b/boot/bootmeth-uclass.c
index 175eb1d..1d157d5 100644
--- a/boot/bootmeth-uclass.c
+++ b/boot/bootmeth-uclass.c
@@ -61,6 +61,18 @@
return ops->set_bootflow(dev, bflow, buf, size);
}
+#if CONFIG_IS_ENABLED(BOOTSTD_FULL)
+int bootmeth_read_all(struct udevice *dev, struct bootflow *bflow)
+{
+ const struct bootmeth_ops *ops = bootmeth_get_ops(dev);
+
+ if (!ops->read_all)
+ return -ENOSYS;
+
+ return ops->read_all(dev, bflow);
+}
+#endif /* BOOTSTD_FULL */
+
int bootmeth_boot(struct udevice *dev, struct bootflow *bflow)
{
const struct bootmeth_ops *ops = bootmeth_get_ops(dev);
diff --git a/boot/bootmeth_cros.c b/boot/bootmeth_cros.c
index aa19ae0..cd72db8 100644
--- a/boot/bootmeth_cros.c
+++ b/boot/bootmeth_cros.c
@@ -12,24 +12,79 @@
#include <blk.h>
#include <bootdev.h>
#include <bootflow.h>
+#include <bootm.h>
#include <bootmeth.h>
+#include <display_options.h>
#include <dm.h>
+#include <efi.h>
#include <malloc.h>
#include <mapmem.h>
#include <part.h>
-#ifdef CONFIG_X86
-#include <asm/zimage.h>
-#endif
#include <linux/sizes.h>
+#include "bootmeth_cros.h"
+
+static const efi_guid_t cros_kern_type = PARTITION_CROS_KERNEL;
+
+/*
+ * Layout of the ChromeOS kernel
+ *
+ * Partitions 2 and 4 contain kernels with type GUID_CROS_KERNEL
+ *
+ * Contents are:
+ *
+ * Offset Contents
+ * 0 struct vb2_keyblock
+ * m struct vb2_kernel_preamble
+ * m + n kernel buffer
+ *
+ * m is keyblock->keyblock_size
+ * n is preamble->preamble_size
+ *
+ * The kernel buffer itself consists of various parts:
+ *
+ * Offset Contents
+ * m + n kernel image (Flat vmlinux binary or FIT)
+ * b - 8KB Command line text
+ * b - 4KB X86 setup block (struct boot_params, extends for about 16KB)
+ * b X86 bootloader (continuation of setup block)
+ * b + 16KB X86 setup block (copy, used for hold data pointed to)
+ *
+ * b is m + n + preamble->bootloader_address - preamble->body_load_address
+ *
+ * Useful metadata extends from b - 8KB through to b + 32 KB
+ */
enum {
- /* Offsets in the kernel-partition header */
- KERN_START = 0x4f0,
- KERN_SIZE = 0x518,
+ PROBE_SIZE = SZ_4K, /* initial bytes read from partition */
- SETUP_OFFSET = 0x1000, /* bytes before base */
- CMDLINE_OFFSET = 0x2000, /* bytes before base */
- OFFSET_BASE = 0x100000, /* assumed kernel load-address */
+ X86_SETUP_OFFSET = -0x1000, /* setup offset relative to base */
+ CMDLINE_OFFSET = -0x2000, /* cmdline offset relative to base */
+ X86_KERNEL_OFFSET = 0x4000, /* kernel offset relative to base */
+};
+
+/**
+ * struct cros_priv - Private data
+ *
+ * This is read from the disk and recorded for use when the full kernel must
+ * be loaded and booted
+ *
+ * @body_offset: Offset of kernel body from start of partition (in bytes)
+ * @body_size: Size of kernel body in bytes
+ * @part_start: Block offset of selected partition from the start of the disk
+ * @body_load_address: Nominal load address for kernel body
+ * @bootloader_address: Address of bootloader, after body is loaded at
+ * body_load_address
+ * @bootloader_size: Size of bootloader in bytes
+ * @info_buf: Buffer containing ChromiumOS info
+ */
+struct cros_priv {
+ ulong body_offset;
+ ulong body_size;
+ lbaint_t part_start;
+ ulong body_load_address;
+ ulong bootloader_address;
+ ulong bootloader_size;
+ void *info_buf;
};
static int cros_check(struct udevice *dev, struct bootflow_iter *iter)
@@ -77,61 +132,96 @@
return 0;
}
-static int cros_read_bootflow(struct udevice *dev, struct bootflow *bflow)
+/**
+ * scan_part() - Scan a kernel partition to see if has a ChromeOS header
+ *
+ * This reads the first PROBE_SIZE of a partition, loookng for
+ * VB2_KEYBLOCK_MAGIC
+ *
+ * @blk: Block device to scan
+ * @partnum: Partition number to scan
+ * @info: Please to put partition info
+ * @hdrp: Return allocated keyblock header on success
+ */
+static int scan_part(struct udevice *blk, int partnum,
+ struct disk_partition *info, struct vb2_keyblock **hdrp)
{
- struct blk_desc *desc = dev_get_uclass_plat(bflow->blk);
- ulong base, start, size, setup, cmdline, num_blks, kern_base;
- struct disk_partition info;
- const char *uuid = NULL;
- void *buf, *hdr;
+ struct blk_desc *desc = dev_get_uclass_plat(blk);
+ struct vb2_keyblock *hdr;
+ struct uuid type;
+ ulong num_blks;
int ret;
- log_debug("starting, part=%d\n", bflow->part);
+ if (!partnum)
+ return log_msg_ret("efi", -ENOENT);
- /* We consider the whole disk, not any one partition */
- if (bflow->part)
- return log_msg_ret("max", -ENOENT);
-
- /* Check partition 2 */
- ret = part_get_info(desc, 2, &info);
+ ret = part_get_info(desc, partnum, info);
if (ret)
return log_msg_ret("part", ret);
+ /* Check for kernel partition type */
+ log_debug("part %x: type=%s\n", partnum, info->type_guid);
+ if (uuid_str_to_bin(info->type_guid, (u8 *)&type, UUID_STR_FORMAT_GUID))
+ return log_msg_ret("typ", -EINVAL);
+
+ if (memcmp(&cros_kern_type, &type, sizeof(type)))
+ return log_msg_ret("typ", -ENOEXEC);
+
/* Make a buffer for the header information */
- num_blks = SZ_4K >> desc->log2blksz;
+ num_blks = PROBE_SIZE >> desc->log2blksz;
log_debug("Reading header, blk=%s, start=%lx, blocks=%lx\n",
- bflow->blk->name, (ulong)info.start, num_blks);
- hdr = memalign(SZ_1K, SZ_4K);
+ blk->name, (ulong)info->start, num_blks);
+ hdr = memalign(SZ_1K, PROBE_SIZE);
if (!hdr)
return log_msg_ret("hdr", -ENOMEM);
- ret = blk_read(bflow->blk, info.start, num_blks, hdr);
- if (ret != num_blks)
- return log_msg_ret("inf", ret);
+ ret = blk_read(blk, info->start, num_blks, hdr);
+ if (ret != num_blks) {
+ free(hdr);
+ return log_msg_ret("inf", -EIO);
+ }
- if (memcmp("CHROMEOS", hdr, 8))
+ if (memcmp(VB2_KEYBLOCK_MAGIC, hdr->magic, VB2_KEYBLOCK_MAGIC_SIZE)) {
+ free(hdr);
+ log_debug("no magic\n");
return -ENOENT;
+ }
- log_info("Header at %lx\n", (ulong)map_to_sysmem(hdr));
- start = *(u32 *)(hdr + KERN_START);
- size = ALIGN(*(u32 *)(hdr + KERN_SIZE), desc->blksz);
- log_debug("Reading start %lx size %lx\n", start, size);
- bflow->size = size;
+ *hdrp = hdr;
- buf = memalign(SZ_1K, size);
- if (!buf)
- return log_msg_ret("buf", -ENOMEM);
+ return 0;
+}
+
+/**
+ * cros_read_buf() - Read information into a buf and parse it
+ *
+ * @bflow: Bootflow to update
+ * @buf: Buffer to use
+ * @size: Size of buffer and number of bytes to read thereinto
+ * @start: Start offset to read from on disk
+ * @before_base: Number of bytes to read before the bootloader base
+ * @uuid: UUID string if supported, else NULL
+ * Return: 0 if OK, -ENOMEM if out of memory, -EIO on read failure
+ */
+static int cros_read_buf(struct bootflow *bflow, void *buf, ulong size,
+ loff_t start, ulong before_base, const char *uuid)
+{
+ struct blk_desc *desc = dev_get_uclass_plat(bflow->blk);
+ ulong base, setup, cmdline, kern_base;
+ ulong num_blks;
+ int ret;
+
num_blks = size >> desc->log2blksz;
- log_debug("Reading data, blk=%s, start=%lx, blocks=%lx\n",
- bflow->blk->name, (ulong)info.start, num_blks);
- ret = blk_read(bflow->blk, (ulong)info.start + 0x80, num_blks, buf);
+ log_debug("Reading info to %lx, blk=%s, size=%lx, blocks=%lx\n",
+ (ulong)map_to_sysmem(buf), bflow->blk->name, size, num_blks);
+ ret = blk_read(bflow->blk, start, num_blks, buf);
if (ret != num_blks)
- return log_msg_ret("inf", ret);
- base = map_to_sysmem(buf);
+ return log_msg_ret("inf", -EIO);
+ base = map_to_sysmem(buf) + before_base;
- setup = base + start - OFFSET_BASE - SETUP_OFFSET;
- cmdline = base + start - OFFSET_BASE - CMDLINE_OFFSET;
- kern_base = base + start - OFFSET_BASE + SZ_16K;
- log_debug("base %lx setup %lx, cmdline %lx, kern_base %lx\n", base,
+ setup = base + X86_SETUP_OFFSET;
+ cmdline = base + CMDLINE_OFFSET;
+ kern_base = base + X86_KERNEL_OFFSET;
+ log_debug("base %lx setup %lx cmdline %lx kern_base %lx\n", base,
setup, cmdline, kern_base);
#ifdef CONFIG_X86
@@ -151,35 +241,206 @@
if (!bflow->os_name)
return log_msg_ret("os", -ENOMEM);
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- uuid = info.uuid;
-#endif
ret = copy_cmdline(map_sysmem(cmdline, 0), uuid, &bflow->cmdline);
if (ret)
return log_msg_ret("cmd", ret);
+ bflow->x86_setup = map_sysmem(setup, 0);
- bflow->state = BOOTFLOWST_READY;
+ return 0;
+}
+
+/**
+ * cros_read_info() - Read information and fill out the bootflow
+ *
+ * @bflow: Bootflow to update
+ * @uuid: UUID string if supported, else NULL
+ * @preamble: Kernel preamble information
+ * Return: 0 if OK, -ENOMEM if out of memory, -EIO on read failure
+ */
+static int cros_read_info(struct bootflow *bflow, const char *uuid,
+ const struct vb2_kernel_preamble *preamble)
+{
+ struct cros_priv *priv = bflow->bootmeth_priv;
+ struct udevice *blk = bflow->blk;
+ struct blk_desc *desc = dev_get_uclass_plat(blk);
+ ulong offset, size, before_base;
+ void *buf;
+ int ret;
+
+ log_debug("Kernel preamble at %lx, version major %x, minor %x\n",
+ (ulong)map_to_sysmem(preamble),
+ preamble->header_version_major,
+ preamble->header_version_minor);
+
+ log_debug(" - load_address %lx, bl_addr %lx, bl_size %lx\n",
+ (ulong)preamble->body_load_address,
+ (ulong)preamble->bootloader_address,
+ (ulong)preamble->bootloader_size);
+
+ priv->body_size = preamble->body_signature.data_size;
+ priv->body_load_address = preamble->body_load_address;
+ priv->bootloader_address = preamble->bootloader_address;
+ priv->bootloader_size = preamble->bootloader_size;
+ log_debug("Kernel body at %lx size %lx\n", priv->body_offset,
+ priv->body_size);
+
+ /* Work out how many bytes to read before the bootloader base */
+ before_base = -CMDLINE_OFFSET;
+
+ /* Read the cmdline through to the end of the bootloader */
+ size = priv->bootloader_size + before_base;
+ offset = priv->body_offset +
+ (priv->bootloader_address - priv->body_load_address) +
+ CMDLINE_OFFSET;
+ buf = malloc(size);
+ if (!buf)
+ return log_msg_ret("buf", -ENOMEM);
+
+ ret = cros_read_buf(bflow, buf, size,
+ priv->part_start + (offset >> desc->log2blksz),
+ before_base, uuid);
+ if (ret) {
+ /* Clear this since the buffer is invalid */
+ bflow->x86_setup = NULL;
+ free(buf);
+ return log_msg_ret("pro", ret);
+ }
+ priv->info_buf = buf;
+
+ return 0;
+}
+
+static int cros_read_kernel(struct bootflow *bflow)
+{
+ struct blk_desc *desc = dev_get_uclass_plat(bflow->blk);
+ struct cros_priv *priv = bflow->bootmeth_priv;
+ ulong base, setup;
+ ulong num_blks;
+ void *buf;
+ int ret;
+
+ bflow->size = priv->body_size;
+
+ buf = memalign(SZ_1K, priv->body_size);
+ if (!buf)
+ return log_msg_ret("buf", -ENOMEM);
+
+ /* Check that the header is not smaller than permitted */
+ if (priv->body_offset < PROBE_SIZE)
+ return log_msg_ret("san", EFAULT);
+
+ /* Read kernel body */
+ num_blks = priv->body_size >> desc->log2blksz;
+ log_debug("Reading body to %lx, blk=%s, size=%lx, blocks=%lx\n",
+ (ulong)map_to_sysmem(buf), bflow->blk->name, priv->body_size,
+ num_blks);
+ ret = blk_read(bflow->blk,
+ priv->part_start + (priv->body_offset >> desc->log2blksz),
+ num_blks, buf);
+ if (ret != num_blks)
+ return log_msg_ret("inf", -EIO);
+ base = map_to_sysmem(buf) + priv->bootloader_address -
+ priv->body_load_address;
+ setup = base + X86_SETUP_OFFSET;
+
bflow->buf = buf;
bflow->x86_setup = map_sysmem(setup, 0);
return 0;
}
+static int cros_read_bootflow(struct udevice *dev, struct bootflow *bflow)
+{
+ const struct vb2_kernel_preamble *preamble;
+ struct disk_partition info;
+ struct vb2_keyblock *hdr;
+ const char *uuid = NULL;
+ struct cros_priv *priv;
+ int ret;
+
+ log_debug("starting, part=%x\n", bflow->part);
+
+ /* Check for kernel partitions */
+ ret = scan_part(bflow->blk, bflow->part, &info, &hdr);
+ if (ret) {
+ log_debug("- scan failed: err=%d\n", ret);
+ return log_msg_ret("scan", ret);
+ }
+
+ priv = malloc(sizeof(struct cros_priv));
+ if (!priv) {
+ free(hdr);
+ return log_msg_ret("buf", -ENOMEM);
+ }
+ bflow->bootmeth_priv = priv;
+
+ log_debug("Selected partition %d, header at %lx\n", bflow->part,
+ (ulong)map_to_sysmem(hdr));
+
+ /* Grab a few things from the preamble */
+ preamble = (void *)hdr + hdr->keyblock_size;
+ priv->body_offset = hdr->keyblock_size + preamble->preamble_size;
+ priv->part_start = info.start;
+
+ /* Now read everything we can learn about kernel */
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
+ uuid = info.uuid;
+#endif
+ ret = cros_read_info(bflow, uuid, preamble);
+ preamble = NULL;
+ free(hdr);
+ if (ret) {
+ free(priv->info_buf);
+ free(priv);
+ return log_msg_ret("inf", ret);
+ }
+ bflow->size = priv->body_size;
+ bflow->state = BOOTFLOWST_READY;
+
+ return 0;
+}
+
static int cros_read_file(struct udevice *dev, struct bootflow *bflow,
const char *file_path, ulong addr, ulong *sizep)
{
return -ENOSYS;
}
+#if CONFIG_IS_ENABLED(BOOTSTD_FULL)
+static int cros_read_all(struct udevice *dev, struct bootflow *bflow)
+{
+ int ret;
+
+ if (bflow->buf)
+ return log_msg_ret("ld", -EALREADY);
+ ret = cros_read_kernel(bflow);
+ if (ret)
+ return log_msg_ret("rd", ret);
+
+ return 0;
+}
+#endif /* BOOTSTD_FULL */
+
static int cros_boot(struct udevice *dev, struct bootflow *bflow)
{
-#ifdef CONFIG_X86
- zboot_start(map_to_sysmem(bflow->buf), bflow->size, 0, 0,
- map_to_sysmem(bflow->x86_setup),
- bflow->cmdline);
-#endif
+ int ret;
- return log_msg_ret("go", -EFAULT);
+ if (!bflow->buf) {
+ ret = cros_read_kernel(bflow);
+ if (ret)
+ return log_msg_ret("rd", ret);
+ }
+
+ if (IS_ENABLED(CONFIG_X86)) {
+ ret = zboot_start(map_to_sysmem(bflow->buf), bflow->size, 0, 0,
+ map_to_sysmem(bflow->x86_setup),
+ bflow->cmdline);
+ } else {
+ ret = bootm_boot_start(map_to_sysmem(bflow->buf),
+ bflow->cmdline);
+ }
+
+ return log_msg_ret("go", ret);
}
static int cros_bootmeth_bind(struct udevice *dev)
@@ -187,6 +448,7 @@
struct bootmeth_uc_plat *plat = dev_get_uclass_plat(dev);
plat->desc = "ChromiumOS boot";
+ plat->flags = BOOTMETHF_ANY_PART;
return 0;
}
@@ -196,6 +458,9 @@
.read_bootflow = cros_read_bootflow,
.read_file = cros_read_file,
.boot = cros_boot,
+#if CONFIG_IS_ENABLED(BOOTSTD_FULL)
+ .read_all = cros_read_all,
+#endif /* BOOTSTD_FULL */
};
static const struct udevice_id cros_bootmeth_ids[] = {
diff --git a/boot/bootmeth_cros.h b/boot/bootmeth_cros.h
new file mode 100644
index 0000000..8e30385
--- /dev/null
+++ b/boot/bootmeth_cros.h
@@ -0,0 +1,197 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Structures used by the ChromiumOS bootmeth
+ *
+ * See docs at:
+ * https://www.chromium.org/chromium-os/chromiumos-design-docs/verified-boot-data-structures/
+ *
+ * Original code at:
+ * https://chromium.googlesource.com/chromiumos/platform/vboot_reference/+/refs/heads/main/firmware/2lib/include/2struct.h
+ *
+ * Code taken from vboot_reference commit 5b8596ce file 2struct.h
+ *
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __BOOTMETH_CROS_H
+#define __BOOTMETH_CROS_H
+
+/* Signature data (a secure hash, possibly signed) */
+struct vb2_signature {
+ /* Offset of signature data from start of this struct */
+ uint32_t sig_offset;
+ uint32_t reserved0;
+
+ /* Size of signature data in bytes */
+ uint32_t sig_size;
+ uint32_t reserved1;
+
+ /* Size of the data block which was signed in bytes */
+ uint32_t data_size;
+ uint32_t reserved2;
+} __attribute__((packed));
+
+#define EXPECTED_VB2_SIGNATURE_SIZE 24
+
+/* Packed public key data */
+struct vb2_packed_key {
+ /* Offset of key data from start of this struct */
+ uint32_t key_offset;
+ uint32_t reserved0;
+
+ /* Size of key data in bytes (NOT strength of key in bits) */
+ uint32_t key_size;
+ uint32_t reserved1;
+
+ /* Signature algorithm used by the key (enum vb2_crypto_algorithm) */
+ uint32_t algorithm;
+ uint32_t reserved2;
+
+ /* Key version */
+ uint32_t key_version;
+ uint32_t reserved3;
+
+ /* TODO: when redoing this struct, add a text description of the key */
+} __attribute__((packed));
+
+#define EXPECTED_VB2_PACKED_KEY_SIZE 32
+
+#define VB2_KEYBLOCK_MAGIC "CHROMEOS"
+#define VB2_KEYBLOCK_MAGIC_SIZE 8
+
+/*
+ * Keyblock, containing the public key used to sign some other chunk of data.
+ *
+ * This should be followed by:
+ * 1) The data_key key data, pointed to by data_key.key_offset.
+ * 2) The checksum data for (vb2_keyblock + data_key data), pointed to
+ * by keyblock_checksum.sig_offset.
+ * 3) The signature data for (vb2_keyblock + data_key data), pointed to
+ * by keyblock_signature.sig_offset.
+ */
+struct vb2_keyblock {
+ /* Magic number */
+ uint8_t magic[VB2_KEYBLOCK_MAGIC_SIZE];
+
+ /* Version of this header format */
+ uint32_t header_version_major;
+ uint32_t header_version_minor;
+
+ /*
+ * Length of this entire keyblock, including keys, signatures, and
+ * padding, in bytes
+ */
+ uint32_t keyblock_size;
+ uint32_t reserved0;
+
+ /*
+ * Signature for this keyblock (header + data pointed to by data_key)
+ * For use with signed data keys
+ */
+ struct vb2_signature keyblock_signature;
+
+ /*
+ * SHA-512 hash for this keyblock (header + data pointed to by
+ * data_key) For use with unsigned data keys.
+ *
+ * Only supported for kernel keyblocks, not firmware keyblocks.
+ */
+ struct vb2_signature keyblock_hash;
+
+ /* Flags for key (VB2_KEYBLOCK_FLAG_*) */
+ uint32_t keyblock_flags;
+ uint32_t reserved1;
+
+ /* Key to verify the chunk of data */
+ struct vb2_packed_key data_key;
+} __attribute__((packed));
+
+#define EXPECTED_VB2_KEYBLOCK_SIZE 112
+
+/*
+ * Preamble block for kernel, version 2.2
+ *
+ * This should be followed by:
+ * 1) The signature data for the kernel body, pointed to by
+ * body_signature.sig_offset.
+ * 2) The signature data for (vb2_kernel_preamble + body signature data),
+ * pointed to by preamble_signature.sig_offset.
+ * 3) The 16-bit vmlinuz header, which is used for reconstruction of
+ * vmlinuz image.
+ */
+struct vb2_kernel_preamble {
+ /*
+ * Size of this preamble, including keys, signatures, vmlinuz header,
+ * and padding, in bytes
+ */
+ uint32_t preamble_size;
+ uint32_t reserved0;
+
+ /* Signature for this preamble (header + body signature) */
+ struct vb2_signature preamble_signature;
+
+ /* Version of this header format */
+ uint32_t header_version_major;
+ uint32_t header_version_minor;
+
+ /* Kernel version */
+ uint32_t kernel_version;
+ uint32_t reserved1;
+
+ /* Load address for kernel body */
+ uint64_t body_load_address;
+ /* TODO (vboot 2.1): we never used that */
+
+ /* Address of bootloader, after body is loaded at body_load_address */
+ uint64_t bootloader_address;
+ /* TODO (vboot 2.1): should be a 32-bit offset */
+
+ /* Size of bootloader in bytes */
+ uint32_t bootloader_size;
+ uint32_t reserved2;
+
+ /* Signature for the kernel body */
+ struct vb2_signature body_signature;
+
+ /*
+ * TODO (vboot 2.1): fields for kernel offset and size. Right now the
+ * size is implicitly the same as the size of data signed by the body
+ * signature, and the offset is implicitly at the end of the preamble.
+ * But that forces us to pad the preamble to 64KB rather than just
+ * having a tiny preamble and an offset field.
+ */
+
+ /*
+ * Fields added in header version 2.1. You must verify the header
+ * version before reading these fields!
+ */
+
+ /*
+ * Address of 16-bit header for vmlinuz reassembly. Readers should
+ * return 0 for header version < 2.1.
+ */
+ uint64_t vmlinuz_header_address;
+
+ /* Size of 16-bit header for vmlinuz in bytes. Readers should return 0
+ for header version < 2.1 */
+ uint32_t vmlinuz_header_size;
+ uint32_t reserved3;
+
+ /*
+ * Fields added in header version 2.2. You must verify the header
+ * version before reading these fields!
+ */
+
+ /*
+ * Flags; see VB2_KERNEL_PREAMBLE_*. Readers should return 0 for
+ * header version < 2.2. Flags field is currently defined as:
+ * [31:2] - Reserved (for future use)
+ * [1:0] - Kernel image type (0b00 - CrOS,
+ * 0b01 - bootimg,
+ * 0b10 - multiboot)
+ */
+ uint32_t flags;
+} __attribute__((packed));
+
+#endif /* __BOOTMETH_CROS_H */
diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c
index ae936c8..446cb73 100644
--- a/boot/bootmeth_efi.c
+++ b/boot/bootmeth_efi.c
@@ -312,6 +312,7 @@
*/
} else {
log_debug("No device tree available\n");
+ bflow->flags |= BOOTFLOWF_USE_BUILTIN_FDT;
}
return 0;
@@ -322,7 +323,7 @@
char file_addr[17], fname[256];
char *tftp_argv[] = {"tftp", file_addr, fname, NULL};
struct cmd_tbl cmdtp = {}; /* dummy */
- const char *addr_str, *fdt_addr_str;
+ const char *addr_str, *fdt_addr_str, *bootfile_name;
int ret, arch, size;
ulong addr, fdt_addr;
char str[36];
@@ -338,7 +339,7 @@
ret = env_set("bootp_vci", str);
if (ret)
return log_msg_ret("vcs", ret);
- ret = env_set_ulong("bootp_arch", arch);
+ ret = env_set_hex("bootp_arch", arch);
if (ret)
return log_msg_ret("ars", ret);
@@ -359,6 +360,12 @@
return log_msg_ret("sz", -EINVAL);
bflow->size = size;
+ /* bootfile should be setup by dhcp*/
+ bootfile_name = env_get("bootfile");
+ if (!bootfile_name)
+ return log_msg_ret("bootfile_name", ret);
+ bflow->fname = strdup(bootfile_name);
+
/* do the hideous EFI hack */
efi_set_bootdev("Net", "", bflow->fname, map_sysmem(addr, 0),
bflow->size);
@@ -384,6 +391,7 @@
bflow->fdt_addr = fdt_addr;
} else {
log_debug("No device tree available\n");
+ bflow->flags |= BOOTFLOWF_USE_BUILTIN_FDT;
}
bflow->state = BOOTFLOWST_READY;
@@ -395,6 +403,12 @@
{
int ret;
+ /*
+ * bootmeth_efi doesn't allocate any buffer neither for blk nor net device
+ * set flag to avoid freeing static buffer.
+ */
+ bflow->flags |= BOOTFLOWF_STATIC_BUF;
+
if (bootmeth_uses_network(bflow)) {
/* we only support reading from one device, so ignore 'dev' */
ret = distro_efi_read_bootflow_net(bflow);
@@ -422,13 +436,11 @@
return log_msg_ret("read", ret);
/*
- * use the provided device tree if available, else fall back to
- * the control FDT
+ * use the provided device tree if not using the built-in fdt
*/
- if (bflow->fdt_fname)
+ if (bflow->flags & ~BOOTFLOWF_USE_BUILTIN_FDT)
fdt = bflow->fdt_addr;
- else
- fdt = (ulong)map_to_sysmem(gd->fdt_blob);
+
} else {
/*
* This doesn't actually work for network devices:
@@ -445,7 +457,14 @@
* At some point we can add a real interface to bootefi so we can call
* this directly. For now, go through the CLI, like distro boot.
*/
- snprintf(cmd, sizeof(cmd), "bootefi %lx %lx", kernel, fdt);
+ if (bflow->flags & BOOTFLOWF_USE_BUILTIN_FDT) {
+ log_debug("Booting with built-in fdt\n");
+ snprintf(cmd, sizeof(cmd), "bootefi %lx", kernel);
+ } else {
+ log_debug("Booting with external fdt\n");
+ snprintf(cmd, sizeof(cmd), "bootefi %lx %lx", kernel, fdt);
+ }
+
if (run_command(cmd, 0))
return log_msg_ret("run", -EINVAL);
diff --git a/boot/bootmeth_efi_mgr.c b/boot/bootmeth_efi_mgr.c
index e9d9734..e6c42d4 100644
--- a/boot/bootmeth_efi_mgr.c
+++ b/boot/bootmeth_efi_mgr.c
@@ -14,6 +14,8 @@
#include <bootmeth.h>
#include <command.h>
#include <dm.h>
+#include <efi_loader.h>
+#include <efi_variable.h>
/**
* struct efi_mgr_priv - private info for the efi-mgr driver
@@ -46,13 +48,26 @@
static int efi_mgr_read_bootflow(struct udevice *dev, struct bootflow *bflow)
{
struct efi_mgr_priv *priv = dev_get_priv(dev);
+ efi_status_t ret;
+ efi_uintn_t size;
+ u16 *bootorder;
if (priv->fake_dev) {
bflow->state = BOOTFLOWST_READY;
return 0;
}
- /* To be implemented */
+ ret = efi_init_obj_list();
+ if (ret)
+ return log_msg_ret("init", ret);
+
+ /* Enable this method if the "BootOrder" UEFI exists. */
+ bootorder = efi_get_var(u"BootOrder", &efi_global_variable_guid,
+ &size);
+ if (bootorder) {
+ bflow->state = BOOTFLOWST_READY;
+ return 0;
+ }
return -EINVAL;
}
diff --git a/boot/bootmeth_script.c b/boot/bootmeth_script.c
index 58c57a2..06340e4 100644
--- a/boot/bootmeth_script.c
+++ b/boot/bootmeth_script.c
@@ -99,7 +99,7 @@
if (!bflow->subdir)
return log_msg_ret("prefix", -ENOMEM);
- ret = bootmeth_alloc_file(bflow, 0x10000, 1);
+ ret = bootmeth_alloc_file(bflow, 0x10000, ARCH_DMA_MINALIGN);
if (ret)
return log_msg_ret("read", ret);
@@ -188,12 +188,20 @@
{
struct blk_desc *desc = dev_get_uclass_plat(bflow->blk);
ulong addr;
- int ret;
+ int ret = 0;
- if (desc->uclass_id == UCLASS_USB)
+ if (desc->uclass_id == UCLASS_USB) {
ret = env_set("devtype", "usb");
- else
- ret = env_set("devtype", blk_get_devtype(bflow->blk));
+ } else {
+ /* If the uclass is AHCI, but the driver is ATA
+ * (not scsi), set devtype to sata
+ */
+ if (IS_ENABLED(CONFIG_SATA) &&
+ desc->uclass_id == UCLASS_AHCI)
+ ret = env_set("devtype", "sata");
+ else
+ ret = env_set("devtype", blk_get_devtype(bflow->blk));
+ }
if (!ret)
ret = env_set_hex("devnum", desc->devnum);
if (!ret)
diff --git a/boot/cedit.c b/boot/cedit.c
index ee24658..8c654db 100644
--- a/boot/cedit.c
+++ b/boot/cedit.c
@@ -6,15 +6,50 @@
* Written by Simon Glass <sjg@chromium.org>
*/
+#define LOG_CATEGORY LOGC_EXPO
+
#include <common.h>
+#include <abuf.h>
+#include <cedit.h>
#include <cli.h>
#include <dm.h>
+#include <env.h>
#include <expo.h>
+#include <malloc.h>
#include <menu.h>
+#include <rtc.h>
#include <video.h>
#include <linux/delay.h>
#include "scene_internal.h"
+enum {
+ CMOS_MAX_BITS = 2048,
+ CMOS_MAX_BYTES = CMOS_MAX_BITS / 8,
+};
+
+#define CMOS_BYTE(bit) ((bit) / 8)
+#define CMOS_BIT(bit) ((bit) % 8)
+
+/**
+ * struct cedit_iter_priv - private data for cedit operations
+ *
+ * @buf: Buffer to use when writing settings to the devicetree
+ * @node: Node to read from when reading settings from devicetree
+ * @verbose: true to show writing to environment variables
+ * @mask: Mask bits for the CMOS RAM. If a bit is set the byte containing it
+ * will be written
+ * @value: Value bits for CMOS RAM. This is the actual value written
+ * @dev: RTC device to write to
+ */
+struct cedit_iter_priv {
+ struct abuf *buf;
+ ofnode node;
+ bool verbose;
+ u8 *mask;
+ u8 *value;
+ struct udevice *dev;
+};
+
int cedit_arange(struct expo *exp, struct video_priv *vpriv, uint scene_id)
{
struct scene_obj_txt *txt;
@@ -36,28 +71,37 @@
y = 100;
list_for_each_entry(obj, &scn->obj_head, sibling) {
- if (obj->type == SCENEOBJT_MENU) {
+ switch (obj->type) {
+ case SCENEOBJT_NONE:
+ case SCENEOBJT_IMAGE:
+ case SCENEOBJT_TEXT:
+ break;
+ case SCENEOBJT_MENU:
scene_obj_set_pos(scn, obj->id, 50, y);
scene_menu_arrange(scn, (struct scene_obj_menu *)obj);
y += 50;
+ break;
+ case SCENEOBJT_TEXTLINE:
+ scene_obj_set_pos(scn, obj->id, 50, y);
+ scene_textline_arrange(scn,
+ (struct scene_obj_textline *)obj);
+ y += 50;
+ break;
}
}
return 0;
}
-int cedit_run(struct expo *exp)
+int cedit_prepare(struct expo *exp, struct video_priv **vid_privp,
+ struct scene **scnp)
{
- struct cli_ch_state s_cch, *cch = &s_cch;
struct video_priv *vid_priv;
- uint scene_id;
struct udevice *dev;
struct scene *scn;
- bool done;
+ uint scene_id;
int ret;
- cli_ch_init(cch);
-
/* For now we only support a video console */
ret = uclass_first_device_err(UCLASS_VIDEO, &dev);
if (ret)
@@ -92,6 +136,27 @@
if (ret)
return log_msg_ret("dim", ret);
+ *vid_privp = vid_priv;
+ *scnp = scn;
+
+ return scene_id;
+}
+
+int cedit_run(struct expo *exp)
+{
+ struct cli_ch_state s_cch, *cch = &s_cch;
+ struct video_priv *vid_priv;
+ uint scene_id;
+ struct scene *scn;
+ bool done;
+ int ret;
+
+ cli_ch_init(cch);
+ ret = cedit_prepare(exp, &vid_priv, &scn);
+ if (ret < 0)
+ return log_msg_ret("prep", ret);
+ scene_id = ret;
+
done = false;
do {
struct expo_action act;
@@ -117,7 +182,7 @@
key = 0;
if (ichar) {
key = bootmenu_conv_key(ichar);
- if (key == BKEY_NONE)
+ if (key == BKEY_NONE || key >= BKEY_FIRST_EXTRA)
key = ichar;
}
if (!key)
@@ -161,3 +226,593 @@
return 0;
}
+
+static int check_space(int ret, struct abuf *buf)
+{
+ if (ret == -FDT_ERR_NOSPACE) {
+ if (!abuf_realloc_inc(buf, CEDIT_SIZE_INC))
+ return log_msg_ret("spc", -ENOMEM);
+ ret = fdt_resize(abuf_data(buf), abuf_data(buf),
+ abuf_size(buf));
+ if (ret)
+ return log_msg_ret("res", -EFAULT);
+ }
+
+ return 0;
+}
+
+/**
+ * get_cur_menuitem_text() - Get the text of the currently selected item
+ *
+ * Looks up the object for the current item, finds text object for it and looks
+ * up the string for that text
+ *
+ * @menu: Menu to look at
+ * @strp: Returns a pointer to the next
+ * Return: 0 if OK, -ENOENT if something was not found
+ */
+static int get_cur_menuitem_text(const struct scene_obj_menu *menu,
+ const char **strp)
+{
+ struct scene *scn = menu->obj.scene;
+ const struct scene_menitem *mi;
+ const struct scene_obj_txt *txt;
+ const char *str;
+
+ mi = scene_menuitem_find(menu, menu->cur_item_id);
+ if (!mi)
+ return log_msg_ret("mi", -ENOENT);
+
+ txt = scene_obj_find(scn, mi->label_id, SCENEOBJT_TEXT);
+ if (!txt)
+ return log_msg_ret("txt", -ENOENT);
+
+ str = expo_get_str(scn->expo, txt->str_id);
+ if (!str)
+ return log_msg_ret("str", -ENOENT);
+ *strp = str;
+
+ return 0;
+}
+
+static int write_dt_string(struct abuf *buf, const char *name, const char *str)
+{
+ int ret, i;
+
+ /* write the text of the current item */
+ ret = -EAGAIN;
+ for (i = 0; ret && i < 2; i++) {
+ ret = fdt_property_string(abuf_data(buf), name, str);
+ if (!i) {
+ ret = check_space(ret, buf);
+ if (ret)
+ return log_msg_ret("rs2", -ENOMEM);
+ }
+ }
+
+ /* this should not happen */
+ if (ret)
+ return log_msg_ret("str", -EFAULT);
+
+ return 0;
+}
+
+static int h_write_settings(struct scene_obj *obj, void *vpriv)
+{
+ struct cedit_iter_priv *priv = vpriv;
+ struct abuf *buf = priv->buf;
+ int ret;
+
+ switch (obj->type) {
+ case SCENEOBJT_NONE:
+ case SCENEOBJT_IMAGE:
+ case SCENEOBJT_TEXT:
+ break;
+ case SCENEOBJT_TEXTLINE: {
+ const struct scene_obj_textline *tline;
+
+ tline = (struct scene_obj_textline *)obj;
+ ret = write_dt_string(buf, obj->name, abuf_data(&tline->buf));
+ if (ret)
+ return log_msg_ret("wr2", ret);
+ break;
+ }
+ case SCENEOBJT_MENU: {
+ const struct scene_obj_menu *menu;
+ const char *str;
+ char name[80];
+ int i;
+
+ /* write the ID of the current item */
+ menu = (struct scene_obj_menu *)obj;
+ ret = -EAGAIN;
+ for (i = 0; ret && i < 2; i++) {
+ ret = fdt_property_u32(abuf_data(buf), obj->name,
+ menu->cur_item_id);
+ if (!i) {
+ ret = check_space(ret, buf);
+ if (ret)
+ return log_msg_ret("res", -ENOMEM);
+ }
+ }
+ /* this should not happen */
+ if (ret)
+ return log_msg_ret("wrt", -EFAULT);
+
+ ret = get_cur_menuitem_text(menu, &str);
+ if (ret)
+ return log_msg_ret("mis", ret);
+
+ /* write the text of the current item */
+ snprintf(name, sizeof(name), "%s-str", obj->name);
+ ret = write_dt_string(buf, name, str);
+ if (ret)
+ return log_msg_ret("wr2", ret);
+
+ break;
+ }
+ }
+
+ return 0;
+}
+
+int cedit_write_settings(struct expo *exp, struct abuf *buf)
+{
+ struct cedit_iter_priv priv;
+ void *fdt;
+ int ret;
+
+ abuf_init(buf);
+ if (!abuf_realloc(buf, CEDIT_SIZE_INC))
+ return log_msg_ret("buf", -ENOMEM);
+
+ fdt = abuf_data(buf);
+ ret = fdt_create(fdt, abuf_size(buf));
+ if (!ret)
+ ret = fdt_finish_reservemap(fdt);
+ if (!ret)
+ ret = fdt_begin_node(fdt, "");
+ if (!ret)
+ ret = fdt_begin_node(fdt, CEDIT_NODE_NAME);
+ if (ret) {
+ log_debug("Failed to start FDT (err=%d)\n", ret);
+ return log_msg_ret("sta", -EINVAL);
+ }
+
+ /* write out the items */
+ priv.buf = buf;
+ ret = expo_iter_scene_objs(exp, h_write_settings, &priv);
+ if (ret) {
+ log_debug("Failed to write settings (err=%d)\n", ret);
+ return log_msg_ret("set", ret);
+ }
+
+ ret = fdt_end_node(fdt);
+ if (!ret)
+ ret = fdt_end_node(fdt);
+ if (!ret)
+ ret = fdt_finish(fdt);
+ if (ret) {
+ log_debug("Failed to finish FDT (err=%d)\n", ret);
+ return log_msg_ret("fin", -EINVAL);
+ }
+
+ return 0;
+}
+
+static int h_read_settings(struct scene_obj *obj, void *vpriv)
+{
+ struct cedit_iter_priv *priv = vpriv;
+ ofnode node = priv->node;
+
+ switch (obj->type) {
+ case SCENEOBJT_NONE:
+ case SCENEOBJT_IMAGE:
+ case SCENEOBJT_TEXT:
+ break;
+ case SCENEOBJT_TEXTLINE: {
+ const struct scene_obj_textline *tline;
+ const char *val;
+ int len;
+
+ tline = (struct scene_obj_textline *)obj;
+
+ val = ofnode_read_prop(node, obj->name, &len);
+ if (len >= tline->max_chars)
+ return log_msg_ret("str", -ENOSPC);
+ strcpy(abuf_data(&tline->buf), val);
+ break;
+ }
+ case SCENEOBJT_MENU: {
+ struct scene_obj_menu *menu;
+ uint val;
+
+ if (ofnode_read_u32(node, obj->name, &val))
+ return log_msg_ret("rd", -ENOENT);
+ menu = (struct scene_obj_menu *)obj;
+ menu->cur_item_id = val;
+
+ break;
+ }
+ }
+
+ return 0;
+}
+
+int cedit_read_settings(struct expo *exp, oftree tree)
+{
+ struct cedit_iter_priv priv;
+ ofnode root, node;
+ int ret;
+
+ root = oftree_root(tree);
+ if (!ofnode_valid(root))
+ return log_msg_ret("roo", -ENOENT);
+ node = ofnode_find_subnode(root, CEDIT_NODE_NAME);
+ if (!ofnode_valid(node))
+ return log_msg_ret("pat", -ENOENT);
+
+ /* read in the items */
+ priv.node = node;
+ ret = expo_iter_scene_objs(exp, h_read_settings, &priv);
+ if (ret) {
+ log_debug("Failed to read settings (err=%d)\n", ret);
+ return log_msg_ret("set", ret);
+ }
+
+ return 0;
+}
+
+static int h_write_settings_env(struct scene_obj *obj, void *vpriv)
+{
+ const struct scene_obj_menu *menu;
+ struct cedit_iter_priv *priv = vpriv;
+ char name[80], var[60];
+ const char *str;
+ int val, ret;
+
+ snprintf(var, sizeof(var), "c.%s", obj->name);
+
+ switch (obj->type) {
+ case SCENEOBJT_NONE:
+ case SCENEOBJT_IMAGE:
+ case SCENEOBJT_TEXT:
+ break;
+ case SCENEOBJT_MENU:
+ menu = (struct scene_obj_menu *)obj;
+ val = menu->cur_item_id;
+
+ if (priv->verbose)
+ printf("%s=%d\n", var, val);
+
+ ret = env_set_ulong(var, val);
+ if (ret)
+ return log_msg_ret("set", ret);
+
+ ret = get_cur_menuitem_text(menu, &str);
+ if (ret)
+ return log_msg_ret("mis", ret);
+
+ snprintf(name, sizeof(name), "c.%s-str", obj->name);
+ if (priv->verbose)
+ printf("%s=%s\n", name, str);
+
+ ret = env_set(name, str);
+ if (ret)
+ return log_msg_ret("st2", ret);
+ break;
+ case SCENEOBJT_TEXTLINE: {
+ const struct scene_obj_textline *tline;
+
+ tline = (struct scene_obj_textline *)obj;
+ str = abuf_data(&tline->buf);
+ ret = env_set(var, str);
+ if (ret)
+ return log_msg_ret("set", ret);
+
+ if (priv->verbose)
+ printf("%s=%s\n", var, str);
+
+ break;
+ }
+ }
+
+ return 0;
+}
+
+int cedit_write_settings_env(struct expo *exp, bool verbose)
+{
+ struct cedit_iter_priv priv;
+ int ret;
+
+ /* write out the items */
+ priv.verbose = verbose;
+ ret = expo_iter_scene_objs(exp, h_write_settings_env, &priv);
+ if (ret) {
+ log_debug("Failed to write settings to env (err=%d)\n", ret);
+ return log_msg_ret("set", ret);
+ }
+
+ return 0;
+}
+
+static int h_read_settings_env(struct scene_obj *obj, void *vpriv)
+{
+ struct cedit_iter_priv *priv = vpriv;
+ struct scene_obj_menu *menu;
+ char var[60];
+ int val;
+
+ snprintf(var, sizeof(var), "c.%s", obj->name);
+
+ switch (obj->type) {
+ case SCENEOBJT_NONE:
+ case SCENEOBJT_IMAGE:
+ case SCENEOBJT_TEXT:
+ break;
+ case SCENEOBJT_MENU:
+ menu = (struct scene_obj_menu *)obj;
+ val = env_get_ulong(var, 10, 0);
+ if (priv->verbose)
+ printf("%s=%d\n", var, val);
+ if (!val)
+ return log_msg_ret("get", -ENOENT);
+
+ /*
+ * note that no validation is done here, to make sure the ID is
+ * valid * and actually points to a menu item
+ */
+ menu->cur_item_id = val;
+ break;
+ case SCENEOBJT_TEXTLINE: {
+ const struct scene_obj_textline *tline;
+ const char *value;
+
+ tline = (struct scene_obj_textline *)obj;
+ value = env_get(var);
+ if (value && strlen(value) >= tline->max_chars)
+ return log_msg_ret("str", -ENOSPC);
+ if (!value)
+ value = "";
+ if (priv->verbose)
+ printf("%s=%s\n", var, value);
+ strcpy(abuf_data(&tline->buf), value);
+ break;
+ }
+ }
+
+ return 0;
+}
+
+int cedit_read_settings_env(struct expo *exp, bool verbose)
+{
+ struct cedit_iter_priv priv;
+ int ret;
+
+ /* write out the items */
+ priv.verbose = verbose;
+ ret = expo_iter_scene_objs(exp, h_read_settings_env, &priv);
+ if (ret) {
+ log_debug("Failed to read settings from env (err=%d)\n", ret);
+ return log_msg_ret("set", ret);
+ }
+
+ return 0;
+}
+
+/**
+ * get_cur_menuitem_seq() - Get the sequence number of a menu's current item
+ *
+ * Enumerates the items of a menu (0, 1, 2) and returns the sequence number of
+ * the currently selected item. If the first item is selected, this returns 0;
+ * if the second, 1; etc.
+ *
+ * @menu: Menu to check
+ * Return: Sequence number on success, else -ve error value
+ */
+static int get_cur_menuitem_seq(const struct scene_obj_menu *menu)
+{
+ const struct scene_menitem *mi;
+ int seq, found;
+
+ seq = 0;
+ found = -1;
+ list_for_each_entry(mi, &menu->item_head, sibling) {
+ if (mi->id == menu->cur_item_id) {
+ found = seq;
+ break;
+ }
+ seq++;
+ }
+
+ if (found == -1)
+ return log_msg_ret("nf", -ENOENT);
+
+ return found;
+}
+
+static int h_write_settings_cmos(struct scene_obj *obj, void *vpriv)
+{
+ const struct scene_obj_menu *menu;
+ struct cedit_iter_priv *priv = vpriv;
+ int val, ret;
+ uint i, seq;
+
+ if (obj->type != SCENEOBJT_MENU)
+ return 0;
+
+ menu = (struct scene_obj_menu *)obj;
+ val = menu->cur_item_id;
+
+ ret = get_cur_menuitem_seq(menu);
+ if (ret < 0)
+ return log_msg_ret("cur", ret);
+ seq = ret;
+ log_debug("%s: seq=%d\n", menu->obj.name, seq);
+
+ /* figure out where to place this item */
+ if (!obj->bit_length)
+ return log_msg_ret("len", -EINVAL);
+ if (obj->start_bit + obj->bit_length > CMOS_MAX_BITS)
+ return log_msg_ret("bit", -E2BIG);
+
+ for (i = 0; i < obj->bit_length; i++, seq >>= 1) {
+ uint bitnum = obj->start_bit + i;
+
+ priv->mask[CMOS_BYTE(bitnum)] |= 1 << CMOS_BIT(bitnum);
+ if (seq & 1)
+ priv->value[CMOS_BYTE(bitnum)] |= BIT(CMOS_BIT(bitnum));
+ log_debug("bit %x %x %x\n", bitnum,
+ priv->mask[CMOS_BYTE(bitnum)],
+ priv->value[CMOS_BYTE(bitnum)]);
+ }
+
+ return 0;
+}
+
+int cedit_write_settings_cmos(struct expo *exp, struct udevice *dev,
+ bool verbose)
+{
+ struct cedit_iter_priv priv;
+ int ret, i, count, first, last;
+
+ /* write out the items */
+ priv.mask = calloc(1, CMOS_MAX_BYTES);
+ if (!priv.mask)
+ return log_msg_ret("mas", -ENOMEM);
+ priv.value = calloc(1, CMOS_MAX_BYTES);
+ if (!priv.value) {
+ free(priv.mask);
+ return log_msg_ret("val", -ENOMEM);
+ }
+
+ ret = expo_iter_scene_objs(exp, h_write_settings_cmos, &priv);
+ if (ret) {
+ log_debug("Failed to write CMOS (err=%d)\n", ret);
+ ret = log_msg_ret("set", ret);
+ goto done;
+ }
+
+ /* write the data to the RTC */
+ first = CMOS_MAX_BYTES;
+ last = -1;
+ for (i = 0, count = 0; i < CMOS_MAX_BYTES; i++) {
+ if (priv.mask[i]) {
+ log_debug("Write byte %x: %x\n", i, priv.value[i]);
+ ret = rtc_write8(dev, i, priv.value[i]);
+ if (ret) {
+ ret = log_msg_ret("wri", ret);
+ goto done;
+ }
+ count++;
+ first = min(first, i);
+ last = max(last, i);
+ }
+ }
+ if (verbose) {
+ printf("Write %d bytes from offset %x to %x\n", count, first,
+ last);
+ }
+
+done:
+ free(priv.mask);
+ free(priv.value);
+ return ret;
+}
+
+static int h_read_settings_cmos(struct scene_obj *obj, void *vpriv)
+{
+ struct cedit_iter_priv *priv = vpriv;
+ const struct scene_menitem *mi;
+ struct scene_obj_menu *menu;
+ int val, ret;
+ uint i;
+
+ if (obj->type != SCENEOBJT_MENU)
+ return 0;
+
+ menu = (struct scene_obj_menu *)obj;
+
+ /* figure out where to place this item */
+ if (!obj->bit_length)
+ return log_msg_ret("len", -EINVAL);
+ if (obj->start_bit + obj->bit_length > CMOS_MAX_BITS)
+ return log_msg_ret("bit", -E2BIG);
+
+ val = 0;
+ for (i = 0; i < obj->bit_length; i++) {
+ uint bitnum = obj->start_bit + i;
+ uint offset = CMOS_BYTE(bitnum);
+
+ /* read the byte if not already read */
+ if (!priv->mask[offset]) {
+ ret = rtc_read8(priv->dev, offset);
+ if (ret < 0)
+ return log_msg_ret("rea", ret);
+ priv->value[offset] = ret;
+
+ /* mark it as read */
+ priv->mask[offset] = 0xff;
+ }
+
+ if (priv->value[offset] & BIT(CMOS_BIT(bitnum)))
+ val |= BIT(i);
+ log_debug("bit %x %x\n", bitnum, val);
+ }
+
+ /* update the current item */
+ mi = scene_menuitem_find_seq(menu, val);
+ if (!mi)
+ return log_msg_ret("seq", -ENOENT);
+
+ menu->cur_item_id = mi->id;
+ log_debug("Update menu %d cur_item_id %d\n", menu->obj.id, mi->id);
+
+ return 0;
+}
+
+int cedit_read_settings_cmos(struct expo *exp, struct udevice *dev,
+ bool verbose)
+{
+ struct cedit_iter_priv priv;
+ int ret, i, count, first, last;
+
+ /* read in the items */
+ priv.mask = calloc(1, CMOS_MAX_BYTES);
+ if (!priv.mask)
+ return log_msg_ret("mas", -ENOMEM);
+ priv.value = calloc(1, CMOS_MAX_BYTES);
+ if (!priv.value) {
+ free(priv.mask);
+ return log_msg_ret("val", -ENOMEM);
+ }
+ priv.dev = dev;
+
+ ret = expo_iter_scene_objs(exp, h_read_settings_cmos, &priv);
+ if (ret) {
+ log_debug("Failed to read CMOS (err=%d)\n", ret);
+ ret = log_msg_ret("set", ret);
+ goto done;
+ }
+
+ /* read the data to the RTC */
+ first = CMOS_MAX_BYTES;
+ last = -1;
+ for (i = 0, count = 0; i < CMOS_MAX_BYTES; i++) {
+ if (priv.mask[i]) {
+ log_debug("Read byte %x: %x\n", i, priv.value[i]);
+ count++;
+ first = min(first, i);
+ last = max(last, i);
+ }
+ }
+ if (verbose) {
+ printf("Read %d bytes from offset %x to %x\n", count, first,
+ last);
+ }
+
+done:
+ free(priv.mask);
+ free(priv.value);
+ return ret;
+}
diff --git a/boot/expo.c b/boot/expo.c
index db837f7..cadb6a0 100644
--- a/boot/expo.c
+++ b/boot/expo.c
@@ -190,10 +190,12 @@
struct udevice *dev = exp->display;
struct video_priv *vid_priv = dev_get_uclass_priv(dev);
struct scene *scn = NULL;
+ enum colour_idx back;
u32 colour;
int ret;
- colour = video_index_to_colour(vid_priv, VID_WHITE);
+ back = CONFIG_IS_ENABLED(SYS_WHITE_ON_BLACK) ? VID_BLACK : VID_WHITE;
+ colour = video_index_to_colour(vid_priv, back);
ret = video_fill(dev, colour);
if (ret)
return log_msg_ret("fill", ret);
@@ -266,3 +268,18 @@
return 0;
}
+
+int expo_iter_scene_objs(struct expo *exp, expo_scene_obj_iterator iter,
+ void *priv)
+{
+ struct scene *scn;
+ int ret;
+
+ list_for_each_entry(scn, &exp->scene_head, sibling) {
+ ret = scene_iter_objs(scn, iter, priv);
+ if (ret)
+ return log_msg_ret("wr", ret);
+ }
+
+ return 0;
+}
diff --git a/boot/expo_build.c b/boot/expo_build.c
index 702bf49..04d88a2 100644
--- a/boot/expo_build.c
+++ b/boot/expo_build.c
@@ -23,10 +23,14 @@
* if there is nothing for this ID. Since ID 0 is never used, the first
* element of this array is always NULL
* @str_count: Number of entries in @str_for_id
+ * @err_node: Node being processed (for error reporting)
+ * @err_prop: Property being processed (for error reporting)
*/
struct build_info {
const char **str_for_id;
int str_count;
+ ofnode err_node;
+ const char *err_prop;
};
/**
@@ -46,6 +50,7 @@
uint str_id;
int ret;
+ info->err_prop = find_name;
text = ofnode_read_string(node, find_name);
if (!text) {
char name[40];
@@ -54,7 +59,7 @@
snprintf(name, sizeof(name), "%s-id", find_name);
ret = ofnode_read_u32(node, name, &id);
if (ret)
- return log_msg_ret("id", -EINVAL);
+ return log_msg_ret("id", -ENOENT);
if (id >= info->str_count)
return log_msg_ret("id", -E2BIG);
@@ -164,9 +169,10 @@
int ret;
u32 id;
+ info->err_node = node;
ret = ofnode_read_u32(node, "id", &id);
if (ret)
- return log_msg_ret("id", -EINVAL);
+ return log_msg_ret("id", -ENOENT);
val = ofnode_read_string(node, "value");
if (!val)
return log_msg_ret("val", -EINVAL);
@@ -214,22 +220,21 @@
* @info: Build information
* @node: Node containing the menu description
* @scn: Scene to add the menu to
+ * @id: ID for the menu
+ * @objp: Returns the object pointer
* Returns: 0 if OK, -ENOMEM if out of memory, -EINVAL if there is a format
* error, -ENOENT if there is a references to a non-existent string
*/
-static int menu_build(struct build_info *info, ofnode node, struct scene *scn)
+static int menu_build(struct build_info *info, ofnode node, struct scene *scn,
+ uint id, struct scene_obj **objp)
{
struct scene_obj_menu *menu;
uint title_id, menu_id;
const u32 *item_ids;
int ret, size, i;
const char *name;
- u32 id;
name = ofnode_get_name(node);
- ret = ofnode_read_u32(node, "id", &id);
- if (ret)
- return log_msg_ret("id", -EINVAL);
ret = scene_menu(scn, name, id, &menu);
if (ret < 0)
@@ -242,6 +247,8 @@
return log_msg_ret("tit", ret);
title_id = ret;
ret = scene_menu_set_title(scn, menu_id, title_id);
+ if (ret)
+ return log_msg_ret("set", ret);
item_ids = ofnode_read_prop(node, "item-id", &size);
if (!item_ids)
@@ -275,12 +282,56 @@
if (ret < 0)
return log_msg_ret("mi", ret);
}
+ *objp = &menu->obj;
+
+ return 0;
+}
+
+static int textline_build(struct build_info *info, ofnode node,
+ struct scene *scn, uint id, struct scene_obj **objp)
+{
+ struct scene_obj_textline *ted;
+ uint ted_id, edit_id;
+ const char *name;
+ u32 max_chars;
+ int ret;
+
+ name = ofnode_get_name(node);
+
+ info->err_prop = "max-chars";
+ ret = ofnode_read_u32(node, "max-chars", &max_chars);
+ if (ret)
+ return log_msg_ret("max", -ENOENT);
+
+ ret = scene_textline(scn, name, id, max_chars, &ted);
+ if (ret < 0)
+ return log_msg_ret("ted", ret);
+ ted_id = ret;
+
+ /* Set the title */
+ ret = add_txt_str(info, node, scn, "title", 0);
+ if (ret < 0)
+ return log_msg_ret("tit", ret);
+ ted->label_id = ret;
+
+ /* Setup the editor */
+ info->err_prop = "edit-id";
+ ret = ofnode_read_u32(node, "edit-id", &id);
+ if (ret)
+ return log_msg_ret("id", -ENOENT);
+ edit_id = ret;
+
+ ret = scene_txt_str(scn, "edit", edit_id, 0, abuf_data(&ted->buf),
+ NULL);
+ if (ret < 0)
+ return log_msg_ret("add", ret);
+ ted->edit_id = ret;
return 0;
}
/**
- * menu_build() - Build an expo object and add it to a scene
+ * obj_build() - Build an expo object and add it to a scene
*
* See doc/develop/expo.rst for a description of the format
*
@@ -292,26 +343,34 @@
*/
static int obj_build(struct build_info *info, ofnode node, struct scene *scn)
{
+ struct scene_obj *obj;
const char *type;
- u32 id;
+ u32 id, val;
int ret;
log_debug("- object %s\n", ofnode_get_name(node));
ret = ofnode_read_u32(node, "id", &id);
if (ret)
- return log_msg_ret("id", -EINVAL);
+ return log_msg_ret("id", -ENOENT);
type = ofnode_read_string(node, "type");
if (!type)
return log_msg_ret("typ", -EINVAL);
if (!strcmp("menu", type))
- ret = menu_build(info, node, scn);
- else
- ret = -EINVAL;
+ ret = menu_build(info, node, scn, id, &obj);
+ else if (!strcmp("textline", type))
+ ret = textline_build(info, node, scn, id, &obj);
+ else
+ ret = -EOPNOTSUPP;
if (ret)
return log_msg_ret("bld", ret);
+ if (!ofnode_read_u32(node, "start-bit", &val))
+ obj->start_bit = val;
+ if (!ofnode_read_u32(node, "bit-length", &val))
+ obj->bit_length = val;
+
return 0;
}
@@ -335,11 +394,12 @@
ofnode node;
int ret;
+ info->err_node = scn_node;
name = ofnode_get_name(scn_node);
log_debug("Building scene %s\n", name);
ret = ofnode_read_u32(scn_node, "id", &id);
if (ret)
- return log_msg_ret("id", -EINVAL);
+ return log_msg_ret("id", -ENOENT);
ret = scene_new(exp, name, id, &scn);
if (ret < 0)
@@ -356,6 +416,7 @@
return log_msg_ret("pr", ret);
ofnode_for_each_subnode(node, scn_node) {
+ info->err_node = node;
ret = obj_build(info, node, scn);
if (ret < 0)
return log_msg_ret("mit", ret);
@@ -364,20 +425,19 @@
return 0;
}
-int expo_build(ofnode root, struct expo **expp)
+int build_it(struct build_info *info, ofnode root, struct expo **expp)
{
- struct build_info info;
ofnode scenes, node;
struct expo *exp;
u32 dyn_start;
int ret;
- memset(&info, '\0', sizeof(info));
- ret = read_strings(&info, root);
+ ret = read_strings(info, root);
if (ret)
return log_msg_ret("str", ret);
if (_DEBUG)
- list_strings(&info);
+ list_strings(info);
+ info->err_node = root;
ret = expo_new("name", NULL, &exp);
if (ret)
@@ -391,7 +451,7 @@
return log_msg_ret("sno", -EINVAL);
ofnode_for_each_subnode(node, scenes) {
- ret = scene_build(&info, node, exp);
+ ret = scene_build(info, node, exp);
if (ret < 0)
return log_msg_ret("scn", ret);
}
@@ -399,3 +459,27 @@
return 0;
}
+
+int expo_build(ofnode root, struct expo **expp)
+{
+ struct build_info info;
+ struct expo *exp;
+ int ret;
+
+ memset(&info, '\0', sizeof(info));
+ ret = build_it(&info, root, &exp);
+ if (ret) {
+ char buf[120];
+ int node_ret;
+
+ node_ret = ofnode_get_path(info.err_node, buf, sizeof(buf));
+ log_warning("Build failed at node %s, property %s\n",
+ node_ret ? ofnode_get_name(info.err_node) : buf,
+ info.err_prop);
+
+ return log_msg_ret("bui", ret);
+ }
+ *expp = exp;
+
+ return 0;
+}
diff --git a/common/fdt_simplefb.c b/boot/fdt_simplefb.c
similarity index 100%
rename from common/fdt_simplefb.c
rename to boot/fdt_simplefb.c
diff --git a/common/fdt_support.c b/boot/fdt_support.c
similarity index 99%
rename from common/fdt_support.c
rename to boot/fdt_support.c
index 5e49078..b15d077 100644
--- a/common/fdt_support.c
+++ b/boot/fdt_support.c
@@ -2095,7 +2095,7 @@
printf("failed on fdt_overlay_apply(): %s\n",
fdt_strerror(err));
if (!has_symbols) {
- printf("base fdt does did not have a /__symbols__ node\n");
+ printf("base fdt does not have a /__symbols__ node\n");
printf("make sure you've compiled with -@\n");
}
}
diff --git a/boot/image-sig.c b/boot/image-sig.c
index 1aa0b58..b5692d5 100644
--- a/boot/image-sig.c
+++ b/boot/image-sig.c
@@ -57,20 +57,6 @@
int i;
const char *name;
- if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC)) {
- static bool done;
-
- if (!done) {
- done = true;
- for (i = 0; i < ARRAY_SIZE(checksum_algos); i++) {
- struct checksum_algo *algo = &checksum_algos[i];
-
- MANUAL_RELOC(algo->name);
- MANUAL_RELOC(algo->calculate);
- }
- }
- }
-
for (i = 0; i < ARRAY_SIZE(checksum_algos); i++) {
name = checksum_algos[i].name;
/* Make sure names match and next char is a comma */
@@ -87,20 +73,6 @@
struct crypto_algo *crypto, *end;
const char *name;
- if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC)) {
- static bool done;
-
- if (!done) {
- done = true;
- crypto = ll_entry_start(struct crypto_algo, cryptos);
- end = ll_entry_end(struct crypto_algo, cryptos);
- for (; crypto < end; crypto++) {
- MANUAL_RELOC(crypto->name);
- MANUAL_RELOC(crypto->verify);
- }
- }
- }
-
/* Move name to after the comma */
name = strchr(full_name, ',');
if (!name)
diff --git a/boot/image.c b/boot/image.c
index 5c4f9b8..88b67bc 100644
--- a/boot/image.c
+++ b/boot/image.c
@@ -182,6 +182,7 @@
{ IH_TYPE_SUNXI_TOC0, "sunxi_toc0", "Allwinner TOC0 Boot Image" },
{ IH_TYPE_FDT_LEGACY, "fdt_legacy", "legacy Image with Flat Device Tree ", },
{ IH_TYPE_RENESAS_SPKG, "spkgimage", "Renesas SPKG Image" },
+ { IH_TYPE_STARFIVE_SPL, "sfspl", "StarFive SPL Image" },
{ -1, "", "", },
};
@@ -571,7 +572,7 @@
entry = get_table_entry(table_info[category].table, id);
if (!entry)
return unknown_msg(category);
- return manual_reloc(entry->lname);
+ return entry->lname;
}
/**
@@ -591,7 +592,7 @@
entry = get_table_entry(table_info[category].table, id);
if (!entry)
return unknown_msg(category);
- return manual_reloc(entry->sname);
+ return entry->sname;
}
int genimg_get_cat_count(enum ih_category category)
@@ -641,7 +642,7 @@
table = get_table_entry(table, id);
if (!table)
return msg;
- return manual_reloc(table->lname);
+ return table->lname;
}
const char *genimg_get_os_name(uint8_t os)
@@ -676,7 +677,7 @@
table = get_table_entry(table, val);
if (!table)
return "unknown";
- return manual_reloc(table->sname);
+ return table->sname;
}
const char *genimg_get_type_short_name(uint8_t type)
@@ -719,7 +720,7 @@
const table_entry_t *t;
for (t = table; t->id >= 0; ++t) {
- if (t->sname && !strcasecmp(manual_reloc(t->sname), name))
+ if (t->sname && !strcasecmp(t->sname, name))
return t->id;
}
debug("Invalid %s Type: %s\n", table_name, name);
diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c
index d13c47d..a92bb89 100644
--- a/boot/pxe_utils.c
+++ b/boot/pxe_utils.c
@@ -554,7 +554,7 @@
label->name);
goto cleanup;
}
-
+ strcpy(initrd_filesize, simple_xtoa(size));
initrd_addr_str = env_get("ramdisk_addr_r");
size = snprintf(initrd_str, sizeof(initrd_str), "%s:%lx",
initrd_addr_str, size);
@@ -702,8 +702,8 @@
}
}
- if (label->kaslrseed)
- label_boot_kaslrseed();
+ if (label->kaslrseed)
+ label_boot_kaslrseed();
#ifdef CONFIG_OF_LIBFDT_OVERLAY
if (label->fdtoverlays)
diff --git a/boot/scene.c b/boot/scene.c
index e523333..d4dfb49 100644
--- a/boot/scene.c
+++ b/boot/scene.c
@@ -32,6 +32,14 @@
return log_msg_ret("name", -ENOMEM);
}
+ abuf_init(&scn->buf);
+ if (!abuf_realloc(&scn->buf, EXPO_MAX_CHARS + 1)) {
+ free(scn->name);
+ free(scn);
+ return log_msg_ret("buf", -ENOMEM);
+ }
+ abuf_init(&scn->entry_save);
+
INIT_LIST_HEAD(&scn->obj_head);
scn->id = resolve_id(exp, id);
scn->expo = exp;
@@ -57,6 +65,8 @@
list_for_each_entry_safe(obj, next, &scn->obj_head, sibling)
scene_obj_destroy(obj);
+ abuf_uninit(&scn->entry_save);
+ abuf_uninit(&scn->buf);
free(scn->name);
free(scn);
}
@@ -79,7 +89,7 @@
return count;
}
-void *scene_obj_find(struct scene *scn, uint id, enum scene_obj_t type)
+void *scene_obj_find(const struct scene *scn, uint id, enum scene_obj_t type)
{
struct scene_obj *obj;
@@ -137,7 +147,7 @@
sizeof(struct scene_obj_img),
(struct scene_obj **)&img);
if (ret < 0)
- return log_msg_ret("obj", -ENOMEM);
+ return log_msg_ret("obj", ret);
img->data = data;
@@ -157,7 +167,7 @@
sizeof(struct scene_obj_txt),
(struct scene_obj **)&txt);
if (ret < 0)
- return log_msg_ret("obj", -ENOMEM);
+ return log_msg_ret("obj", ret);
txt->str_id = str_id;
@@ -176,14 +186,15 @@
ret = expo_str(scn->expo, name, str_id, str);
if (ret < 0)
return log_msg_ret("str", ret);
- else if (ret != str_id)
+ if (str_id && ret != str_id)
return log_msg_ret("id", -EEXIST);
+ str_id = ret;
ret = scene_obj_add(scn, name, id, SCENEOBJT_TEXT,
sizeof(struct scene_obj_txt),
(struct scene_obj **)&txt);
if (ret < 0)
- return log_msg_ret("obj", -ENOMEM);
+ return log_msg_ret("obj", ret);
txt->str_id = str_id;
@@ -269,6 +280,7 @@
switch (obj->type) {
case SCENEOBJT_NONE:
case SCENEOBJT_MENU:
+ case SCENEOBJT_TEXTLINE:
break;
case SCENEOBJT_IMAGE: {
struct scene_obj_img *img = (struct scene_obj_img *)obj;
@@ -314,6 +326,51 @@
}
/**
+ * scene_render_background() - Render the background for an object
+ *
+ * @obj: Object to render
+ * @box_only: true to show a box around the object, but keep the normal
+ * background colour inside
+ */
+static void scene_render_background(struct scene_obj *obj, bool box_only)
+{
+ struct expo *exp = obj->scene->expo;
+ const struct expo_theme *theme = &exp->theme;
+ struct vidconsole_bbox bbox, label_bbox;
+ struct udevice *dev = exp->display;
+ struct video_priv *vid_priv;
+ struct udevice *cons = exp->cons;
+ struct vidconsole_colour old;
+ enum colour_idx fore, back;
+ uint inset = theme->menu_inset;
+
+ /* draw a background for the object */
+ if (CONFIG_IS_ENABLED(SYS_WHITE_ON_BLACK)) {
+ fore = VID_BLACK;
+ back = VID_WHITE;
+ } else {
+ fore = VID_LIGHT_GRAY;
+ back = VID_BLACK;
+ }
+
+ /* see if this object wants to render a background */
+ if (scene_obj_calc_bbox(obj, &bbox, &label_bbox))
+ return;
+
+ vidconsole_push_colour(cons, fore, back, &old);
+ vid_priv = dev_get_uclass_priv(dev);
+ video_fill_part(dev, label_bbox.x0 - inset, label_bbox.y0 - inset,
+ label_bbox.x1 + inset, label_bbox.y1 + inset,
+ vid_priv->colour_fg);
+ vidconsole_pop_colour(cons, &old);
+ if (box_only) {
+ video_fill_part(dev, label_bbox.x0, label_bbox.y0,
+ label_bbox.x1, label_bbox.y1,
+ vid_priv->colour_bg);
+ }
+}
+
+/**
* scene_obj_render() - Render an object
*
*/
@@ -396,7 +453,7 @@
return -ENOTSUPP;
/* draw a background behind the menu items */
- scene_menu_render(menu);
+ scene_render_background(obj, false);
}
/*
* With a vidconsole, the text and item pointer are rendered as
@@ -412,6 +469,10 @@
break;
}
+ case SCENEOBJT_TEXTLINE:
+ if (obj->flags & SCENEOF_OPEN)
+ scene_render_background(obj, true);
+ break;
}
return 0;
@@ -423,13 +484,29 @@
int ret;
list_for_each_entry(obj, &scn->obj_head, sibling) {
- if (obj->type == SCENEOBJT_MENU) {
+ switch (obj->type) {
+ case SCENEOBJT_NONE:
+ case SCENEOBJT_IMAGE:
+ case SCENEOBJT_TEXT:
+ break;
+ case SCENEOBJT_MENU: {
struct scene_obj_menu *menu;
menu = (struct scene_obj_menu *)obj,
ret = scene_menu_arrange(scn, menu);
if (ret)
return log_msg_ret("arr", ret);
+ break;
+ }
+ case SCENEOBJT_TEXTLINE: {
+ struct scene_obj_textline *tline;
+
+ tline = (struct scene_obj_textline *)obj,
+ ret = scene_textline_arrange(scn, tline);
+ if (ret)
+ return log_msg_ret("arr", ret);
+ break;
+ }
}
}
@@ -452,9 +529,20 @@
if (ret && ret != -ENOTSUPP)
return log_msg_ret("ren", ret);
- if (obj->type == SCENEOBJT_MENU)
+ switch (obj->type) {
+ case SCENEOBJT_NONE:
+ case SCENEOBJT_IMAGE:
+ case SCENEOBJT_TEXT:
+ break;
+ case SCENEOBJT_MENU:
scene_menu_render_deps(scn,
(struct scene_obj_menu *)obj);
+ break;
+ case SCENEOBJT_TEXTLINE:
+ scene_textline_render_deps(scn,
+ (struct scene_obj_textline *)obj);
+ break;
+ }
}
return 0;
@@ -501,7 +589,7 @@
sibling)) {
obj = list_entry(obj->sibling.prev,
struct scene_obj, sibling);
- if (obj->type == SCENEOBJT_MENU) {
+ if (scene_obj_can_highlight(obj)) {
event->type = EXPOACT_POINT_OBJ;
event->select.id = obj->id;
log_debug("up to obj %d\n", event->select.id);
@@ -513,7 +601,7 @@
while (!list_is_last(&obj->sibling, &scn->obj_head)) {
obj = list_entry(obj->sibling.next, struct scene_obj,
sibling);
- if (obj->type == SCENEOBJT_MENU) {
+ if (scene_obj_can_highlight(obj)) {
event->type = EXPOACT_POINT_OBJ;
event->select.id = obj->id;
log_debug("down to obj %d\n", event->select.id);
@@ -522,7 +610,7 @@
}
break;
case BKEY_SELECT:
- if (obj->type == SCENEOBJT_MENU) {
+ if (scene_obj_can_highlight(obj)) {
event->type = EXPOACT_OPEN;
event->select.id = obj->id;
log_debug("open obj %d\n", event->select.id);
@@ -537,7 +625,6 @@
int scene_send_key(struct scene *scn, int key, struct expo_action *event)
{
- struct scene_obj_menu *menu;
struct scene_obj *obj;
int ret;
@@ -561,10 +648,30 @@
return 0;
}
- menu = (struct scene_obj_menu *)obj,
- ret = scene_menu_send_key(scn, menu, key, event);
- if (ret)
- return log_msg_ret("key", ret);
+ switch (obj->type) {
+ case SCENEOBJT_NONE:
+ case SCENEOBJT_IMAGE:
+ case SCENEOBJT_TEXT:
+ break;
+ case SCENEOBJT_MENU: {
+ struct scene_obj_menu *menu;
+
+ menu = (struct scene_obj_menu *)obj,
+ ret = scene_menu_send_key(scn, menu, key, event);
+ if (ret)
+ return log_msg_ret("key", ret);
+ break;
+ }
+ case SCENEOBJT_TEXTLINE: {
+ struct scene_obj_textline *tline;
+
+ tline = (struct scene_obj_textline *)obj,
+ ret = scene_textline_send_key(scn, tline, key, event);
+ if (ret)
+ return log_msg_ret("key", ret);
+ break;
+ }
+ }
return 0;
}
@@ -583,6 +690,32 @@
return 0;
}
+int scene_obj_calc_bbox(struct scene_obj *obj, struct vidconsole_bbox *bbox,
+ struct vidconsole_bbox *label_bbox)
+{
+ switch (obj->type) {
+ case SCENEOBJT_NONE:
+ case SCENEOBJT_IMAGE:
+ case SCENEOBJT_TEXT:
+ return -ENOSYS;
+ case SCENEOBJT_MENU: {
+ struct scene_obj_menu *menu = (struct scene_obj_menu *)obj;
+
+ scene_menu_calc_bbox(menu, bbox, label_bbox);
+ break;
+ }
+ case SCENEOBJT_TEXTLINE: {
+ struct scene_obj_textline *tline;
+
+ tline = (struct scene_obj_textline *)obj;
+ scene_textline_calc_bbox(tline, bbox, label_bbox);
+ break;
+ }
+ }
+
+ return 0;
+}
+
int scene_calc_dims(struct scene *scn, bool do_menus)
{
struct scene_obj *obj;
@@ -616,6 +749,16 @@
}
break;
}
+ case SCENEOBJT_TEXTLINE: {
+ struct scene_obj_textline *tline;
+
+ tline = (struct scene_obj_textline *)obj;
+ ret = scene_textline_calc_dims(tline);
+ if (ret)
+ return log_msg_ret("men", ret);
+
+ break;
+ }
}
}
@@ -635,6 +778,7 @@
case SCENEOBJT_NONE:
case SCENEOBJT_IMAGE:
case SCENEOBJT_MENU:
+ case SCENEOBJT_TEXTLINE:
break;
case SCENEOBJT_TEXT:
scene_txt_set_font(scn, obj->id, NULL,
@@ -660,20 +804,49 @@
struct scene_obj *obj;
list_for_each_entry(obj, &scn->obj_head, sibling) {
- switch (obj->type) {
- case SCENEOBJT_MENU:
+ if (scene_obj_can_highlight(obj)) {
scene_set_highlight_id(scn, obj->id);
return;
- default:
- break;
}
}
}
-int scene_set_open(struct scene *scn, uint id, bool open)
+static int scene_obj_open(struct scene *scn, struct scene_obj *obj)
{
int ret;
+ switch (obj->type) {
+ case SCENEOBJT_NONE:
+ case SCENEOBJT_IMAGE:
+ case SCENEOBJT_MENU:
+ case SCENEOBJT_TEXT:
+ break;
+ case SCENEOBJT_TEXTLINE:
+ ret = scene_textline_open(scn,
+ (struct scene_obj_textline *)obj);
+ if (ret)
+ return log_msg_ret("op", ret);
+ break;
+ }
+
+ return 0;
+}
+
+int scene_set_open(struct scene *scn, uint id, bool open)
+{
+ struct scene_obj *obj;
+ int ret;
+
+ obj = scene_obj_find(scn, id, SCENEOBJT_NONE);
+ if (!obj)
+ return log_msg_ret("find", -ENOENT);
+
+ if (open) {
+ ret = scene_obj_open(scn, obj);
+ if (ret)
+ return log_msg_ret("op", ret);
+ }
+
ret = scene_obj_flag_clrset(scn, id, SCENEOF_OPEN,
open ? SCENEOF_OPEN : 0);
if (ret)
@@ -681,3 +854,45 @@
return 0;
}
+
+int scene_iter_objs(struct scene *scn, expo_scene_obj_iterator iter,
+ void *priv)
+{
+ struct scene_obj *obj;
+
+ list_for_each_entry(obj, &scn->obj_head, sibling) {
+ int ret;
+
+ ret = iter(obj, priv);
+ if (ret)
+ return log_msg_ret("itr", ret);
+ }
+
+ return 0;
+}
+
+int scene_bbox_union(struct scene *scn, uint id, int inset,
+ struct vidconsole_bbox *bbox)
+{
+ struct scene_obj *obj;
+
+ if (!id)
+ return 0;
+ obj = scene_obj_find(scn, id, SCENEOBJT_NONE);
+ if (!obj)
+ return log_msg_ret("obj", -ENOENT);
+ if (bbox->valid) {
+ bbox->x0 = min(bbox->x0, obj->dim.x - inset);
+ bbox->y0 = min(bbox->y0, obj->dim.y);
+ bbox->x1 = max(bbox->x1, obj->dim.x + obj->dim.w + inset);
+ bbox->y1 = max(bbox->y1, obj->dim.y + obj->dim.h);
+ } else {
+ bbox->x0 = obj->dim.x - inset;
+ bbox->y0 = obj->dim.y;
+ bbox->x1 = obj->dim.x + obj->dim.w + inset;
+ bbox->y1 = obj->dim.y + obj->dim.h;
+ bbox->valid = true;
+ }
+
+ return 0;
+}
diff --git a/boot/scene_internal.h b/boot/scene_internal.h
index fb1ea55..e72202c 100644
--- a/boot/scene_internal.h
+++ b/boot/scene_internal.h
@@ -9,6 +9,10 @@
#ifndef __SCENE_INTERNAL_H
#define __SCENE_INTERNAL_H
+struct vidconsole_bbox;
+
+typedef int (*expo_scene_obj_iterator)(struct scene_obj *obj, void *priv);
+
/**
* expo_lookup_scene_id() - Look up a scene ID
*
@@ -38,7 +42,7 @@
* @type: Type of the object, or SCENEOBJT_NONE to match any type
* Returns: Object found, or NULL if not found
*/
-void *scene_obj_find(struct scene *scn, uint id, enum scene_obj_t type);
+void *scene_obj_find(const struct scene *scn, uint id, enum scene_obj_t type);
/**
* scene_obj_find_by_name() - Find an object in a scene by name
@@ -98,6 +102,18 @@
int scene_menu_arrange(struct scene *scn, struct scene_obj_menu *menu);
/**
+ * scene_textline_arrange() - Set the position of things in a textline
+ *
+ * This updates any items associated with a textline to make sure they are
+ * positioned correctly relative to the textline.
+ *
+ * @scn: Scene to update
+ * @tline: textline to process
+ * Returns: 0 if OK, -ve on error
+ */
+int scene_textline_arrange(struct scene *scn, struct scene_obj_textline *tline);
+
+/**
* scene_apply_theme() - Apply a theme to a scene
*
* @scn: Scene to update
@@ -120,6 +136,18 @@
struct expo_action *event);
/**
+ * scene_textline_send_key() - Send a key to a textline for processing
+ *
+ * @scn: Scene to use
+ * @tline: textline to use
+ * @key: Key code to send (KEY_...)
+ * @event: Place to put any event which is generated by the key
+ * Returns: 0 if OK (always)
+ */
+int scene_textline_send_key(struct scene *scn, struct scene_obj_textline *tline,
+ int key, struct expo_action *event);
+
+/**
* scene_menu_destroy() - Destroy a menu in a scene
*
* @scn: Scene to destroy
@@ -162,13 +190,6 @@
int scene_send_key(struct scene *scn, int key, struct expo_action *event);
/**
- * scene_menu_render() - Render the background behind a menu
- *
- * @menu: Menu to render
- */
-void scene_menu_render(struct scene_obj_menu *menu);
-
-/**
* scene_render_deps() - Render an object and its dependencies
*
* @scn: Scene to render
@@ -183,12 +204,24 @@
* Renders the menu and all of its attached objects
*
* @scn: Scene to render
- * @menu: Menu render
+ * @menu: Menu to render
* Returns: 0 if OK, -ve on error
*/
int scene_menu_render_deps(struct scene *scn, struct scene_obj_menu *menu);
/**
+ * scene_textline_render_deps() - Render a textline and its dependencies
+ *
+ * Renders the textline and all of its attached objects
+ *
+ * @scn: Scene to render
+ * @tline: textline to render
+ * Returns: 0 if OK, -ve on error
+ */
+int scene_textline_render_deps(struct scene *scn,
+ struct scene_obj_textline *tline);
+
+/**
* scene_menu_calc_dims() - Calculate the dimensions of a menu
*
* Updates the width and height of the menu based on its contents
@@ -198,4 +231,131 @@
*/
int scene_menu_calc_dims(struct scene_obj_menu *menu);
+/**
+ * scene_iter_objs() - Iterate through all scene objects
+ *
+ * @scn: Scene to process
+ * @iter: Iterator to call on each object
+ * @priv: Private data to pass to the iterator, in addition to the object
+ * Return: 0 if OK, -ve on error
+ */
+int scene_iter_objs(struct scene *scn, expo_scene_obj_iterator iter,
+ void *priv);
+
+/**
+ * expo_iter_scene_objects() - Iterate through all scene objects
+ *
+ * @exp: Expo to process
+ * @iter: Iterator to call on each object
+ * @priv: Private data to pass to the iterator, in addition to the object
+ * Return: 0 if OK, -ve on error
+ */
+int expo_iter_scene_objs(struct expo *exp, expo_scene_obj_iterator iter,
+ void *priv);
+
+/**
+ * scene_menuitem_find() - Find the menu item for an ID
+ *
+ * Looks up the menu to find the item with the given ID
+ *
+ * @menu: Menu to check
+ * @id: ID to look for
+ * Return: Menu item, or NULL if not found
+ */
+struct scene_menitem *scene_menuitem_find(const struct scene_obj_menu *menu,
+ int id);
+
+/**
+ * scene_menuitem_find_seq() - Find the menu item at a sequential position
+ *
+ * This numbers the items from 0 and returns the seq'th one
+ *
+ * @menu: Menu to check
+ * @seq: Sequence number to look for
+ * Return: menu item if found, else NULL
+ */
+struct scene_menitem *scene_menuitem_find_seq(const struct scene_obj_menu *menu,
+ uint seq);
+
+/**
+ * scene_bbox_union() - update bouding box with the demensions of an object
+ *
+ * Updates @bbox so that it encompasses the bounding box of object @id
+ *
+ * @snd: Scene containing object
+ * @id: Object id
+ * @inset: Amount of inset to use for width
+ * @bbox: Bounding box to update
+ * Return: 0 if OK, -ve on error
+ */
+int scene_bbox_union(struct scene *scn, uint id, int inset,
+ struct vidconsole_bbox *bbox);
+
+/**
+ * scene_textline_calc_dims() - Calculate the dimensions of a textline
+ *
+ * Updates the width and height of the textline based on its contents
+ *
+ * @tline: Textline to update
+ * Returns 0 if OK, -ENOTSUPP if there is no graphical console
+ */
+int scene_textline_calc_dims(struct scene_obj_textline *tline);
+
+/**
+ * scene_menu_calc_bbox() - Calculate bounding boxes for the menu
+ *
+ * @menu: Menu to process
+ * @bbox: Returns bounding box of menu including prompts
+ * @label_bbox: Returns bounding box of labels
+ * Return: 0 if OK, -ve on error
+ */
+void scene_menu_calc_bbox(struct scene_obj_menu *menu,
+ struct vidconsole_bbox *bbox,
+ struct vidconsole_bbox *label_bbox);
+
+/**
+ * scene_textline_calc_bbox() - Calculate bounding box for the textline
+ *
+ * @textline: Menu to process
+ * @bbox: Returns bounding box of textline including prompt
+ * @edit_bbox: Returns bounding box of editable part
+ * Return: 0 if OK, -ve on error
+ */
+void scene_textline_calc_bbox(struct scene_obj_textline *menu,
+ struct vidconsole_bbox *bbox,
+ struct vidconsole_bbox *label_bbox);
+
+/**
+ * scene_obj_calc_bbox() - Calculate bounding boxes for an object
+ *
+ * @obj: Object to process
+ * @bbox: Returns bounding box of object including prompts
+ * @label_bbox: Returns bounding box of labels (active area)
+ * Return: 0 if OK, -ve on error
+ */
+int scene_obj_calc_bbox(struct scene_obj *obj, struct vidconsole_bbox *bbox,
+ struct vidconsole_bbox *label_bbox);
+
+/**
+ * scene_textline_open() - Open a textline object
+ *
+ * Set up the text editor ready for use
+ *
+ * @scn: Scene containing the textline
+ * @tline: textline object
+ * Return: 0 if OK, -ve on error
+ */
+int scene_textline_open(struct scene *scn, struct scene_obj_textline *tline);
+
+/**
+ * scene_textline_close() - Close a textline object
+ *
+ * Close out the text editor after use
+ *
+ * @scn: Scene containing the textline
+ * @tline: textline object
+ * Return: 0 if OK, -ve on error
+ */
+int scene_textline_close(struct scene *scn, struct scene_obj_textline *tline);
+
#endif /* __SCENE_INTERNAL_H */
diff --git a/boot/scene_menu.c b/boot/scene_menu.c
index 8a355f8..6399416 100644
--- a/boot/scene_menu.c
+++ b/boot/scene_menu.c
@@ -33,8 +33,8 @@
scene_menuitem_destroy(item);
}
-static struct scene_menitem *scene_menuitem_find(struct scene_obj_menu *menu,
- int id)
+struct scene_menitem *scene_menuitem_find(const struct scene_obj_menu *menu,
+ int id)
{
struct scene_menitem *item;
@@ -46,6 +46,22 @@
return NULL;
}
+struct scene_menitem *scene_menuitem_find_seq(const struct scene_obj_menu *menu,
+ uint seq)
+{
+ struct scene_menitem *item;
+ uint i;
+
+ i = 0;
+ list_for_each_entry(item, &menu->item_head, sibling) {
+ if (i == seq)
+ return item;
+ i++;
+ }
+
+ return NULL;
+}
+
/**
* update_pointers() - Update the pointer object and handle highlights
*
@@ -98,42 +114,9 @@
update_pointers(menu, item_id, true);
}
-static int scene_bbox_union(struct scene *scn, uint id, int inset,
- struct vidconsole_bbox *bbox)
-{
- struct scene_obj *obj;
-
- if (!id)
- return 0;
- obj = scene_obj_find(scn, id, SCENEOBJT_NONE);
- if (!obj)
- return log_msg_ret("obj", -ENOENT);
- if (bbox->valid) {
- bbox->x0 = min(bbox->x0, obj->dim.x - inset);
- bbox->y0 = min(bbox->y0, obj->dim.y);
- bbox->x1 = max(bbox->x1, obj->dim.x + obj->dim.w + inset);
- bbox->y1 = max(bbox->y1, obj->dim.y + obj->dim.h);
- } else {
- bbox->x0 = obj->dim.x - inset;
- bbox->y0 = obj->dim.y;
- bbox->x1 = obj->dim.x + obj->dim.w + inset;
- bbox->y1 = obj->dim.y + obj->dim.h;
- bbox->valid = true;
- }
-
- return 0;
-}
-
-/**
- * scene_menu_calc_bbox() - Calculate bounding boxes for the menu
- *
- * @menu: Menu to process
- * @bbox: Returns bounding box of menu including prompts
- * @label_bbox: Returns bounding box of labels
- */
-static void scene_menu_calc_bbox(struct scene_obj_menu *menu,
- struct vidconsole_bbox *bbox,
- struct vidconsole_bbox *label_bbox)
+void scene_menu_calc_bbox(struct scene_obj_menu *menu,
+ struct vidconsole_bbox *bbox,
+ struct vidconsole_bbox *label_bbox)
{
const struct expo_theme *theme = &menu->obj.scene->expo->theme;
const struct scene_menitem *item;
@@ -416,7 +399,7 @@
if (!scene_obj_find(scn, label_id, SCENEOBJT_TEXT))
return log_msg_ret("txt", -EINVAL);
- item = calloc(1, sizeof(struct scene_obj_menu));
+ item = calloc(1, sizeof(struct scene_menitem));
if (!item)
return log_msg_ret("item", -ENOMEM);
item->name = strdup(name);
@@ -533,35 +516,6 @@
return -ENOTSUPP;
}
-void scene_menu_render(struct scene_obj_menu *menu)
-{
- struct expo *exp = menu->obj.scene->expo;
- const struct expo_theme *theme = &exp->theme;
- struct vidconsole_bbox bbox, label_bbox;
- struct udevice *dev = exp->display;
- struct video_priv *vid_priv;
- struct udevice *cons = exp->cons;
- struct vidconsole_colour old;
- enum colour_idx fore, back;
-
- if (CONFIG_IS_ENABLED(SYS_WHITE_ON_BLACK)) {
- fore = VID_BLACK;
- back = VID_WHITE;
- } else {
- fore = VID_LIGHT_GRAY;
- back = VID_BLACK;
- }
-
- scene_menu_calc_bbox(menu, &bbox, &label_bbox);
- vidconsole_push_colour(cons, fore, back, &old);
- vid_priv = dev_get_uclass_priv(dev);
- video_fill_part(dev, label_bbox.x0 - theme->menu_inset,
- label_bbox.y0 - theme->menu_inset,
- label_bbox.x1, label_bbox.y1 + theme->menu_inset,
- vid_priv->colour_fg);
- vidconsole_pop_colour(cons, &old);
-}
-
int scene_menu_render_deps(struct scene *scn, struct scene_obj_menu *menu)
{
struct scene_menitem *item;
diff --git a/boot/scene_textline.c b/boot/scene_textline.c
new file mode 100644
index 0000000..6ea072a
--- /dev/null
+++ b/boot/scene_textline.c
@@ -0,0 +1,229 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Implementation of a menu in a scene
+ *
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#define LOG_CATEGORY LOGC_EXPO
+
+#include <common.h>
+#include <expo.h>
+#include <menu.h>
+#include <video_console.h>
+#include "scene_internal.h"
+
+int scene_textline(struct scene *scn, const char *name, uint id, uint max_chars,
+ struct scene_obj_textline **tlinep)
+{
+ struct scene_obj_textline *tline;
+ char *buf;
+ int ret;
+
+ if (max_chars >= EXPO_MAX_CHARS)
+ return log_msg_ret("chr", -E2BIG);
+
+ ret = scene_obj_add(scn, name, id, SCENEOBJT_TEXTLINE,
+ sizeof(struct scene_obj_textline),
+ (struct scene_obj **)&tline);
+ if (ret < 0)
+ return log_msg_ret("obj", -ENOMEM);
+ abuf_init(&tline->buf);
+ if (!abuf_realloc(&tline->buf, max_chars + 1))
+ return log_msg_ret("buf", -ENOMEM);
+ buf = abuf_data(&tline->buf);
+ *buf = '\0';
+ tline->pos = max_chars;
+ tline->max_chars = max_chars;
+
+ if (tlinep)
+ *tlinep = tline;
+
+ return tline->obj.id;
+}
+
+void scene_textline_calc_bbox(struct scene_obj_textline *tline,
+ struct vidconsole_bbox *bbox,
+ struct vidconsole_bbox *edit_bbox)
+{
+ const struct expo_theme *theme = &tline->obj.scene->expo->theme;
+
+ bbox->valid = false;
+ scene_bbox_union(tline->obj.scene, tline->label_id, 0, bbox);
+ scene_bbox_union(tline->obj.scene, tline->edit_id, 0, bbox);
+
+ edit_bbox->valid = false;
+ scene_bbox_union(tline->obj.scene, tline->edit_id, theme->menu_inset,
+ edit_bbox);
+}
+
+int scene_textline_calc_dims(struct scene_obj_textline *tline)
+{
+ struct scene *scn = tline->obj.scene;
+ struct vidconsole_bbox bbox;
+ struct scene_obj_txt *txt;
+ int ret;
+
+ txt = scene_obj_find(scn, tline->edit_id, SCENEOBJT_NONE);
+ if (!txt)
+ return log_msg_ret("dim", -ENOENT);
+
+ ret = vidconsole_nominal(scn->expo->cons, txt->font_name,
+ txt->font_size, tline->max_chars, &bbox);
+ if (ret)
+ return log_msg_ret("nom", ret);
+
+ if (bbox.valid) {
+ tline->obj.dim.w = bbox.x1 - bbox.x0;
+ tline->obj.dim.h = bbox.y1 - bbox.y0;
+
+ scene_obj_set_size(scn, tline->edit_id, tline->obj.dim.w,
+ tline->obj.dim.h);
+ }
+
+ return 0;
+}
+
+int scene_textline_arrange(struct scene *scn, struct scene_obj_textline *tline)
+{
+ const bool open = tline->obj.flags & SCENEOF_OPEN;
+ bool point;
+ int x, y;
+ int ret;
+
+ x = tline->obj.dim.x;
+ y = tline->obj.dim.y;
+ if (tline->label_id) {
+ ret = scene_obj_set_pos(scn, tline->label_id, tline->obj.dim.x,
+ y);
+ if (ret < 0)
+ return log_msg_ret("tit", ret);
+
+ ret = scene_obj_set_pos(scn, tline->edit_id,
+ tline->obj.dim.x + 200, y);
+ if (ret < 0)
+ return log_msg_ret("tit", ret);
+
+ ret = scene_obj_get_hw(scn, tline->label_id, NULL);
+ if (ret < 0)
+ return log_msg_ret("hei", ret);
+
+ y += ret * 2;
+ }
+
+ point = scn->highlight_id == tline->obj.id;
+ point &= !open;
+ scene_obj_flag_clrset(scn, tline->edit_id, SCENEOF_POINT,
+ point ? SCENEOF_POINT : 0);
+
+ return 0;
+}
+
+int scene_textline_send_key(struct scene *scn, struct scene_obj_textline *tline,
+ int key, struct expo_action *event)
+{
+ const bool open = tline->obj.flags & SCENEOF_OPEN;
+
+ log_debug("key=%d\n", key);
+ switch (key) {
+ case BKEY_QUIT:
+ if (open) {
+ event->type = EXPOACT_CLOSE;
+ event->select.id = tline->obj.id;
+
+ /* Copy the backup text from the scene buffer */
+ memcpy(abuf_data(&tline->buf), abuf_data(&scn->buf),
+ abuf_size(&scn->buf));
+ } else {
+ event->type = EXPOACT_QUIT;
+ log_debug("menu quit\n");
+ }
+ break;
+ case BKEY_SELECT:
+ if (!open)
+ break;
+ event->type = EXPOACT_CLOSE;
+ event->select.id = tline->obj.id;
+ key = '\n';
+ fallthrough;
+ default: {
+ struct udevice *cons = scn->expo->cons;
+ int ret;
+
+ ret = vidconsole_entry_restore(cons, &scn->entry_save);
+ if (ret)
+ return log_msg_ret("sav", ret);
+ ret = cread_line_process_ch(&scn->cls, key);
+ ret = vidconsole_entry_save(cons, &scn->entry_save);
+ if (ret)
+ return log_msg_ret("sav", ret);
+ break;
+ }
+ }
+
+ return 0;
+}
+
+int scene_textline_render_deps(struct scene *scn,
+ struct scene_obj_textline *tline)
+{
+ const bool open = tline->obj.flags & SCENEOF_OPEN;
+ struct udevice *cons = scn->expo->cons;
+ struct scene_obj_txt *txt;
+ int ret;
+
+ scene_render_deps(scn, tline->label_id);
+ scene_render_deps(scn, tline->edit_id);
+
+ /* show the vidconsole cursor if open */
+ if (open) {
+ /* get the position within the field */
+ txt = scene_obj_find(scn, tline->edit_id, SCENEOBJT_NONE);
+ if (!txt)
+ return log_msg_ret("cur", -ENOENT);
+
+ if (txt->font_name || txt->font_size) {
+ ret = vidconsole_select_font(cons,
+ txt->font_name,
+ txt->font_size);
+ } else {
+ ret = vidconsole_select_font(cons, NULL, 0);
+ }
+
+ ret = vidconsole_entry_restore(cons, &scn->entry_save);
+ if (ret)
+ return log_msg_ret("sav", ret);
+
+ vidconsole_set_cursor_visible(cons, true, txt->obj.dim.x,
+ txt->obj.dim.y, scn->cls.num);
+ }
+
+ return 0;
+}
+
+int scene_textline_open(struct scene *scn, struct scene_obj_textline *tline)
+{
+ struct udevice *cons = scn->expo->cons;
+ struct scene_obj_txt *txt;
+ int ret;
+
+ /* Copy the text into the scene buffer in case the edit is cancelled */
+ memcpy(abuf_data(&scn->buf), abuf_data(&tline->buf),
+ abuf_size(&scn->buf));
+
+ /* get the position of the editable */
+ txt = scene_obj_find(scn, tline->edit_id, SCENEOBJT_NONE);
+ if (!txt)
+ return log_msg_ret("cur", -ENOENT);
+
+ vidconsole_set_cursor_pos(cons, txt->obj.dim.x, txt->obj.dim.y);
+ vidconsole_entry_start(cons);
+ cli_cread_init(&scn->cls, abuf_data(&tline->buf), tline->max_chars);
+ scn->cls.insert = true;
+ ret = vidconsole_entry_save(cons, &scn->entry_save);
+ if (ret)
+ return log_msg_ret("sav", ret);
+
+ return 0;
+}
diff --git a/boot/vbe_request.c b/boot/vbe_request.c
index 312edfa..917251a 100644
--- a/boot/vbe_request.c
+++ b/boot/vbe_request.c
@@ -187,7 +187,7 @@
ret = ofnode_add_subnode(dest_parent, name, &dest);
if (ret && ret != -EEXIST)
return log_msg_ret("add", ret);
- ret = ofnode_copy_props(node, dest);
+ ret = ofnode_copy_props(dest, node);
if (ret)
return log_msg_ret("cp", ret);
@@ -230,4 +230,4 @@
return 0;
}
-EVENT_SPY(EVT_FT_FIXUP, bootmeth_vbe_ft_fixup);
+EVENT_SPY_FULL(EVT_FT_FIXUP, bootmeth_vbe_ft_fixup);
diff --git a/boot/vbe_simple_os.c b/boot/vbe_simple_os.c
index 8c641ec..84626cd 100644
--- a/boot/vbe_simple_os.c
+++ b/boot/vbe_simple_os.c
@@ -94,7 +94,7 @@
/* Copy over the vbe properties for fwupd */
log_debug("Fixing up: %s\n", dev->name);
- ret = ofnode_copy_props(dev_ofnode(dev), subnode);
+ ret = ofnode_copy_props(subnode, dev_ofnode(dev));
if (ret)
return log_msg_ret("cp", ret);
@@ -109,4 +109,4 @@
return 0;
}
-EVENT_SPY(EVT_FT_FIXUP, bootmeth_vbe_simple_ft_fixup);
+EVENT_SPY_FULL(EVT_FT_FIXUP, bootmeth_vbe_simple_ft_fixup);
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 29b8fb2..46b79b4 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -176,6 +176,13 @@
help
Command to read the metadata and dump it's contents
+config CMD_HISTORY
+ bool "history"
+ depends on CMDLINE_EDITING
+ help
+ Show the command-line history, i.e. a list of commands that are in
+ the history buffer.
+
config CMD_LICENSE
bool "license"
select BUILD_BIN2C
@@ -239,7 +246,6 @@
bool "enable pre-load on bootm"
depends on CMD_BOOTM
depends on IMAGE_PRE_LOAD
- default n
help
Enable support of stage pre-load for the bootm command.
This stage allow to check or modify the image provided
@@ -500,11 +506,6 @@
help
Extract a part of a multi-image.
-config CMD_XXD
- bool "xxd"
- help
- Print file as hexdump to standard output
-
config CMD_SPL
bool "spl export - Export boot information for Falcon boot"
depends on SPL
@@ -517,7 +518,7 @@
config CMD_SPL_NAND_OFS
hex "Offset of OS args or dtb for Falcon-mode NAND boot"
depends on CMD_SPL && (TPL_NAND_SUPPORT || SPL_NAND_SUPPORT)
- default 0
+ default 0x0
help
This provides the offset of the command line arguments for Linux
when booting from NAND in Falcon mode. See doc/README.falcon
@@ -527,7 +528,7 @@
config CMD_SPL_NOR_OFS
hex "Offset of OS args or dtb for Falcon-mode NOR boot"
depends on CMD_SPL && SPL_NOR_SUPPORT
- default 0
+ default 0x0
help
This provides the offset of the command line arguments or dtb for
Linux when booting from NOR in Falcon mode.
@@ -544,6 +545,8 @@
config CMD_THOR_DOWNLOAD
bool "thor - TIZEN 'thor' download"
select DFU
+ select USB_FUNCTION_THOR
+ depends on USB_GADGET_DOWNLOAD
help
Implements the 'thor' download protocol. This is a way of
downloading a software update over USB from an attached host.
@@ -1315,6 +1318,13 @@
on a eMMC device. The feature is optionally available on eMMC devices
conforming to standard >= 4.41.
+config CMD_MMC_REG
+ bool "Enable support for reading card registers in the mmc command"
+ depends on CMD_MMC
+ help
+ Enable the commands for reading card registers. This is useful
+ mostly for debugging or extracting details from the card.
+
config CMD_MMC_RPMB
bool "Enable support for RPMB in the mmc command"
depends on SUPPORT_EMMC_RPMB
@@ -1529,7 +1539,7 @@
config DEFAULT_SPI_MODE
hex "default spi mode used by sspi command (see include/spi.h)"
depends on CMD_SPI
- default 0
+ default 0x0
config CMD_TEMPERATURE
bool "temperature - display the temperature from thermal sensors"
@@ -1569,6 +1579,14 @@
Enables the command "sdp" which is used to have U-Boot emulating the
Serial Download Protocol (SDP) via USB.
+config CMD_RKMTD
+ bool "rkmtd"
+ select RKMTD
+ help
+ Enable the command "rkmtd" to create a virtual block device to transfer
+ Rockchip boot block data to and from NAND with block orientated tools
+ like "ums" and "rockusb".
+
config CMD_ROCKUSB
bool "rockusb"
depends on USB_FUNCTION_ROCKUSB
@@ -1671,6 +1689,11 @@
Evaluate format string expression and store result in an environment
variable.
+config CMD_XXD
+ bool "xxd"
+ help
+ Print file as hexdump to standard output
+
endmenu
menu "Android support commands"
@@ -1830,7 +1853,11 @@
depends on BOOTP_PXE
default 0x16 if ARM64
default 0x15 if ARM
- default 0 if X86
+ default 0x0 if X86
+
+config BOOTP_PXE_DHCP_OPTION
+ bool "Request & store 'pxe_configfile' from BOOTP/DHCP server"
+ depends on BOOTP_PXE
config BOOTP_VCI_STRING
string
@@ -2358,7 +2385,6 @@
config CMD_SELECT_FONT
bool "select font size"
depends on VIDEO
- default n
help
Enabling this will provide 'font' command.
Allows font selection at runtime.
@@ -2878,7 +2904,6 @@
config MMC_SPEED_MODE_SET
bool "set speed mode using mmc command"
depends on CMD_MMC
- default n
help
Enable setting speed mode using mmc rescan and mmc dev commands.
The speed mode is provided as the last argument in these commands
diff --git a/cmd/Makefile b/cmd/Makefile
index cb6c2b8..0f0adc7 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -92,6 +92,7 @@
obj-$(CONFIG_CMD_FWU_METADATA) += fwu_mdata.o
obj-$(CONFIG_CMD_GETTIME) += gettime.o
obj-$(CONFIG_CMD_GPIO) += gpio.o
+obj-$(CONFIG_CMD_HISTORY) += history.o
obj-$(CONFIG_CMD_HVC) += smccc.o
obj-$(CONFIG_CMD_I2C) += i2c.o
obj-$(CONFIG_CMD_IOTRACE) += iotrace.o
@@ -108,7 +109,6 @@
obj-y += load.o
obj-$(CONFIG_CMD_LOG) += log.o
obj-$(CONFIG_CMD_LSBLK) += lsblk.o
-obj-$(CONFIG_ID_EEPROM) += mac.o
obj-$(CONFIG_CMD_MD5SUM) += md5sum.o
obj-$(CONFIG_CMD_MEMORY) += mem.o
obj-$(CONFIG_CMD_IO) += io.o
@@ -152,6 +152,7 @@
obj-$(CONFIG_CMD_REMOTEPROC) += remoteproc.o
obj-$(CONFIG_CMD_RNG) += rng.o
obj-$(CONFIG_CMD_KASLRSEED) += kaslrseed.o
+obj-$(CONFIG_CMD_RKMTD) += rkmtd.o
obj-$(CONFIG_CMD_ROCKUSB) += rockusb.o
obj-$(CONFIG_CMD_RTC) += rtc.o
obj-$(CONFIG_SANDBOX) += host.o
@@ -236,6 +237,11 @@
obj-$(CONFIG_CMD_MESON) += meson/
obj-$(CONFIG_ARCH_MVEBU) += mvebu/
+
+# TI
+obj-$(CONFIG_ARCH_KEYSTONE) += ti/
+obj-$(CONFIG_ARCH_K3) += ti/
+obj-$(CONFIG_ARCH_OMAP2PLUS) += ti/
endif # !CONFIG_SPL_BUILD
obj-$(CONFIG_$(SPL_)CMD_TLV_EEPROM) += tlv_eeprom.o
@@ -245,8 +251,6 @@
obj-$(CONFIG_CMD_BCM_EXT_UTILS) += broadcom/
-obj-$(CONFIG_TI_COMMON_CMD_OPTIONS) += ti/
-
filechk_data_gz = (echo "static const char data_gz[] ="; cat $< | scripts/bin2c; echo ";")
filechk_data_size = \
diff --git a/cmd/acpi.c b/cmd/acpi.c
index ede9c8c..7e397d1 100644
--- a/cmd/acpi.c
+++ b/cmd/acpi.c
@@ -171,13 +171,11 @@
return 0;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char acpi_help_text[] =
+U_BOOT_LONGHELP(acpi,
"list - list ACPI tables\n"
"acpi items [-d] - List/dump each piece of ACPI data from devices\n"
"acpi set [<addr>] - Set or show address of ACPI tables\n"
- "acpi dump <name> - Dump ACPI table";
-#endif
+ "acpi dump <name> - Dump ACPI table");
U_BOOT_CMD_WITH_SUBCMDS(acpi, "ACPI tables", acpi_help_text,
U_BOOT_SUBCMD_MKENT(list, 1, 1, do_acpi_list),
diff --git a/cmd/adc.c b/cmd/adc.c
index a739d9e..4cb18b6 100644
--- a/cmd/adc.c
+++ b/cmd/adc.c
@@ -7,6 +7,7 @@
#include <command.h>
#include <dm.h>
#include <adc.h>
+#include <linux/printk.h>
static int do_adc_list(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
diff --git a/cmd/aes.c b/cmd/aes.c
index 1936518..1264675 100644
--- a/cmd/aes.c
+++ b/cmd/aes.c
@@ -88,8 +88,7 @@
}
/***************************************************/
-#ifdef CONFIG_SYS_LONGHELP
-static char aes_help_text[] =
+U_BOOT_LONGHELP(aes,
"[.128,.192,.256] enc key iv src dst len - Encrypt block of data $len bytes long\n"
" at address $src using a key at address\n"
" $key with initialization vector at address\n"
@@ -101,8 +100,7 @@
" $key with initialization vector at address\n"
" $iv. Store the result at address $dst.\n"
" The $len size must be multiple of 16 bytes.\n"
- " The $key and $iv must be 16 bytes long.";
-#endif
+ " The $key and $iv must be 16 bytes long.");
U_BOOT_CMD(
aes, 7, 1, do_aes,
diff --git a/cmd/armffa.c b/cmd/armffa.c
index 7e6eafc..9585150 100644
--- a/cmd/armffa.c
+++ b/cmd/armffa.c
@@ -188,13 +188,13 @@
return CMD_RET_SUCCESS;
}
-static char armffa_help_text[] =
+U_BOOT_LONGHELP(armffa,
"getpart <partition UUID>\n"
" - lists the partition(s) info\n"
"ping <partition ID>\n"
" - sends a data pattern to the specified partition\n"
"devlist\n"
- " - displays information about the FF-A device/driver\n";
+ " - displays information about the FF-A device/driver\n");
U_BOOT_CMD_WITH_SUBCMDS(armffa, "Arm FF-A test command", armffa_help_text,
U_BOOT_SUBCMD_MKENT(getpart, 2, 1, do_ffa_getpart),
diff --git a/cmd/axi.c b/cmd/axi.c
index b97b43e..5620891 100644
--- a/cmd/axi.c
+++ b/cmd/axi.c
@@ -344,11 +344,11 @@
return CMD_RET_USAGE;
}
-static char axi_help_text[] =
+U_BOOT_LONGHELP(axi,
"bus - show AXI bus info\n"
"axi dev [bus] - show or set current AXI bus to bus number [bus]\n"
"axi md size addr [# of objects] - read from AXI device at address [addr] and data width [size] (one of 8, 16, 32)\n"
- "axi mw size addr value [count] - write data [value] to AXI device at address [addr] and data width [size] (one of 8, 16, 32)\n";
+ "axi mw size addr value [count] - write data [value] to AXI device at address [addr] and data width [size] (one of 8, 16, 32)\n");
U_BOOT_CMD(axi, 7, 1, do_ihs_axi,
"AXI sub-system",
diff --git a/cmd/blk_common.c b/cmd/blk_common.c
index 9f9d432..02ac928 100644
--- a/cmd/blk_common.c
+++ b/cmd/blk_common.c
@@ -25,18 +25,18 @@
case 2:
if (strncmp(argv[1], "inf", 3) == 0) {
blk_list_devices(uclass_id);
- return 0;
+ return CMD_RET_SUCCESS;
} else if (strncmp(argv[1], "dev", 3) == 0) {
if (blk_print_device_num(uclass_id, *cur_devnump)) {
printf("\nno %s devices available\n", if_name);
return CMD_RET_FAILURE;
}
- return 0;
+ return CMD_RET_SUCCESS;
} else if (strncmp(argv[1], "part", 4) == 0) {
if (blk_list_part(uclass_id))
printf("\nno %s partition table available\n",
if_name);
- return 0;
+ return CMD_RET_SUCCESS;
}
return CMD_RET_USAGE;
case 3:
@@ -49,7 +49,7 @@
} else {
return CMD_RET_FAILURE;
}
- return 0;
+ return CMD_RET_SUCCESS;
} else if (strncmp(argv[1], "part", 4) == 0) {
int dev = (int)dectoul(argv[2], NULL);
@@ -58,7 +58,7 @@
if_name, dev);
return CMD_RET_FAILURE;
}
- return 0;
+ return CMD_RET_SUCCESS;
}
return CMD_RET_USAGE;
@@ -67,38 +67,46 @@
phys_addr_t paddr = hextoul(argv[2], NULL);
lbaint_t blk = hextoul(argv[3], NULL);
ulong cnt = hextoul(argv[4], NULL);
+ struct blk_desc *desc;
void *vaddr;
ulong n;
+ int ret;
printf("\n%s read: device %d block # "LBAFU", count %lu ... ",
if_name, *cur_devnump, blk, cnt);
- vaddr = map_sysmem(paddr, 512 * cnt);
- n = blk_read_devnum(uclass_id, *cur_devnump, blk, cnt,
- vaddr);
+ ret = blk_get_desc(uclass_id, *cur_devnump, &desc);
+ if (ret)
+ return CMD_RET_FAILURE;
+ vaddr = map_sysmem(paddr, desc->blksz * cnt);
+ n = blk_dread(desc, blk, cnt, vaddr);
unmap_sysmem(vaddr);
printf("%ld blocks read: %s\n", n,
n == cnt ? "OK" : "ERROR");
- return n == cnt ? 0 : 1;
+ return n == cnt ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
} else if (strcmp(argv[1], "write") == 0) {
phys_addr_t paddr = hextoul(argv[2], NULL);
lbaint_t blk = hextoul(argv[3], NULL);
ulong cnt = hextoul(argv[4], NULL);
+ struct blk_desc *desc;
void *vaddr;
ulong n;
+ int ret;
printf("\n%s write: device %d block # "LBAFU", count %lu ... ",
if_name, *cur_devnump, blk, cnt);
- vaddr = map_sysmem(paddr, 512 * cnt);
- n = blk_write_devnum(uclass_id, *cur_devnump, blk, cnt,
- vaddr);
+ ret = blk_get_desc(uclass_id, *cur_devnump, &desc);
+ if (ret)
+ return CMD_RET_FAILURE;
+ vaddr = map_sysmem(paddr, desc->blksz * cnt);
+ n = blk_dwrite(desc, blk, cnt, vaddr);
unmap_sysmem(vaddr);
printf("%ld blocks written: %s\n", n,
n == cnt ? "OK" : "ERROR");
- return n == cnt ? 0 : 1;
+ return n == cnt ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
} else {
return CMD_RET_USAGE;
}
diff --git a/cmd/blkcache.c b/cmd/blkcache.c
index 47ea1ec..1456654 100644
--- a/cmd/blkcache.c
+++ b/cmd/blkcache.c
@@ -46,24 +46,11 @@
U_BOOT_CMD_MKENT(configure, 3, 0, blkc_configure, "", ""),
};
-static __maybe_unused void blkc_reloc(void)
-{
- static int relocated;
-
- if (!relocated) {
- fixup_cmdtable(cmd_blkc_sub, ARRAY_SIZE(cmd_blkc_sub));
- relocated = 1;
- };
-}
-
static int do_blkcache(struct cmd_tbl *cmdtp, int flag,
int argc, char *const argv[])
{
struct cmd_tbl *c;
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
- blkc_reloc();
-#endif
if (argc < 2)
return CMD_RET_USAGE;
diff --git a/cmd/blkmap.c b/cmd/blkmap.c
index b34c013..ef74ebc 100644
--- a/cmd/blkmap.c
+++ b/cmd/blkmap.c
@@ -25,7 +25,8 @@
map_parser_fn fn;
};
-int do_blkmap_map_linear(struct map_ctx *ctx, int argc, char *const argv[])
+static int do_blkmap_map_linear(struct map_ctx *ctx, int argc,
+ char *const argv[])
{
struct blk_desc *lbd;
int err, ldevnum;
@@ -58,7 +59,7 @@
return CMD_RET_SUCCESS;
}
-int do_blkmap_map_mem(struct map_ctx *ctx, int argc, char *const argv[])
+static int do_blkmap_map_mem(struct map_ctx *ctx, int argc, char *const argv[])
{
phys_addr_t addr;
int err;
@@ -80,7 +81,7 @@
return CMD_RET_SUCCESS;
}
-struct map_handler map_handlers[] = {
+static struct map_handler map_handlers[] = {
{ .name = "linear", .fn = do_blkmap_map_linear },
{ .name = "mem", .fn = do_blkmap_map_mem },
diff --git a/cmd/bloblist.c b/cmd/bloblist.c
index 21e7ff6..26548ec 100644
--- a/cmd/bloblist.c
+++ b/cmd/bloblist.c
@@ -29,11 +29,9 @@
return 0;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char bloblist_help_text[] =
+U_BOOT_LONGHELP(bloblist,
"info - show information about the bloblist\n"
- "bloblist list - list blobs in the bloblist";
-#endif
+ "bloblist list - list blobs in the bloblist");
U_BOOT_CMD_WITH_SUBCMDS(bloblist, "Bloblists", bloblist_help_text,
U_BOOT_SUBCMD_MKENT(info, 1, 1, do_bloblist_info),
diff --git a/cmd/bootcount.c b/cmd/bootcount.c
index 3898d25..30ce5db 100644
--- a/cmd/bootcount.c
+++ b/cmd/bootcount.c
@@ -46,16 +46,11 @@
return CMD_RET_USAGE;
}
-#if IS_ENABLED(CONFIG_SYS_LONGHELP)
-static char bootcount_help_text[] =
+U_BOOT_LONGHELP(bootcount,
"print - print current bootcounter\n"
- "reset - reset the bootcounter"
- ;
-#endif
+ "reset - reset the bootcounter");
U_BOOT_CMD(bootcount, 2, 1, do_bootcount,
"bootcount",
-#if IS_ENABLED(CONFIG_SYS_LONGHELP)
bootcount_help_text
-#endif
);
diff --git a/cmd/bootdev.c b/cmd/bootdev.c
index a657de6..471189c 100644
--- a/cmd/bootdev.c
+++ b/cmd/bootdev.c
@@ -139,13 +139,11 @@
return 0;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char bootdev_help_text[] =
+U_BOOT_LONGHELP(bootdev,
"list [-p] - list all available bootdevs (-p to probe)\n"
"bootdev hunt [-l|<spec>] - use hunt drivers to find bootdevs\n"
"bootdev select <bd> - select a bootdev by name | label | seq\n"
- "bootdev info [-p] - show information about a bootdev (-p to probe)";
-#endif
+ "bootdev info [-p] - show information about a bootdev (-p to probe)");
U_BOOT_CMD_WITH_SUBCMDS(bootdev, "Boot devices", bootdev_help_text,
U_BOOT_SUBCMD_MKENT(list, 2, 1, do_bootdev_list),
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index f73d6eb..395b062 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -162,8 +162,6 @@
return ret;
}
-#if !CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)
-
/**
* copy_fdt() - Copy the device tree to a new location available to EFI
*
@@ -237,8 +235,6 @@
return NULL;
}
-#endif /* !CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) */
-
/**
* efi_install_fdt() - install device tree
*
@@ -258,18 +254,15 @@
*/
efi_status_t efi_install_fdt(void *fdt)
{
+ struct bootm_headers img = { 0 };
+ efi_status_t ret;
+
/*
* The EBBR spec requires that we have either an FDT or an ACPI table
* but not both.
*/
-#if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)
- if (fdt) {
+ if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) && fdt)
log_warning("WARNING: Can't have ACPI table and device tree - ignoring DT.\n");
- return EFI_SUCCESS;
- }
-#else
- struct bootm_headers img = { 0 };
- efi_status_t ret;
if (fdt == EFI_FDT_USE_INTERNAL) {
const char *fdt_opt;
@@ -302,6 +295,12 @@
return EFI_LOAD_ERROR;
}
+ /* Create memory reservations as indicated by the device tree */
+ efi_carve_out_dt_rsv(fdt);
+
+ if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE))
+ return EFI_SUCCESS;
+
/* Prepare device tree for payload */
ret = copy_fdt(&fdt);
if (ret) {
@@ -314,9 +313,6 @@
return EFI_LOAD_ERROR;
}
- /* Create memory reservations as indicated by the device tree */
- efi_carve_out_dt_rsv(fdt);
-
efi_try_purge_kaslr_seed(fdt);
if (CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL_MEASURE_DTB)) {
@@ -333,7 +329,6 @@
log_err("ERROR: failed to install device tree\n");
return ret;
}
-#endif /* GENERATE_ACPI_TABLE */
return EFI_SUCCESS;
}
@@ -698,8 +693,7 @@
return ret;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char bootefi_help_text[] =
+U_BOOT_LONGHELP(bootefi,
"<image address>[:<image size>] [<fdt address>]\n"
" - boot EFI payload\n"
#ifdef CONFIG_CMD_BOOTEFI_HELLO
@@ -719,8 +713,7 @@
" If specified, the device tree located at <fdt address> gets\n"
" exposed as EFI configuration table.\n"
#endif
- ;
-#endif
+ );
U_BOOT_CMD(
bootefi, 4, 0, do_bootefi,
diff --git a/cmd/bootflow.c b/cmd/bootflow.c
index c0aa4f8..3aeb40d 100644
--- a/cmd/bootflow.c
+++ b/cmd/bootflow.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <bootdev.h>
#include <bootflow.h>
+#include <bootm.h>
#include <bootstd.h>
#include <command.h>
#include <console.h>
@@ -70,7 +71,7 @@
printf("%3x %-11s %-6s %-9.9s %4x %-25.25s %s\n", index,
bflow->method->name, bootflow_state_get_name(bflow->state),
bflow->dev ? dev_get_uclass_name(dev_get_parent(bflow->dev)) :
- "(none)", bflow->part, bflow->name, bflow->fname);
+ "(none)", bflow->part, bflow->name, bflow->fname ?: "");
if (errors)
report_bootflow_err(bflow, bflow->err);
}
@@ -88,6 +89,44 @@
num_valid);
}
+/**
+ * bootflow_handle_menu() - Handle running the menu and updating cur bootflow
+ *
+ * This shows the menu, allows the user to select something and then prints
+ * what happened
+ *
+ * @std: bootstd information
+ * @text_mode: true to run the menu in text mode
+ * @bflowp: Returns selected bootflow, on success
+ * Return: 0 on success (a bootflow was selected), -EAGAIN if nothing was
+ * chosen, other -ve value on other error
+ */
+__maybe_unused static int bootflow_handle_menu(struct bootstd_priv *std,
+ bool text_mode,
+ struct bootflow **bflowp)
+{
+ struct bootflow *bflow;
+ int ret;
+
+ ret = bootflow_menu_run(std, text_mode, &bflow);
+ if (ret) {
+ if (ret == -EAGAIN) {
+ printf("Nothing chosen\n");
+ std->cur_bootflow = NULL;
+ } else {
+ printf("Menu failed (err=%d)\n", ret);
+ }
+
+ return ret;
+ }
+
+ printf("Selected: %s\n", bflow->os_name ? bflow->os_name : bflow->name);
+ std->cur_bootflow = bflow;
+ *bflowp = bflow;
+
+ return 0;
+}
+
static int do_bootflow_scan(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -303,11 +342,14 @@
{
struct bootstd_priv *std;
struct bootflow *bflow;
+ bool x86_setup = false;
bool dump = false;
int ret;
- if (argc > 1 && *argv[1] == '-')
+ if (argc > 1 && *argv[1] == '-') {
dump = strchr(argv[1], 'd');
+ x86_setup = strchr(argv[1], 's');
+ }
ret = bootstd_get_priv(&std);
if (ret)
@@ -319,6 +361,12 @@
}
bflow = std->cur_bootflow;
+ if (IS_ENABLED(CONFIG_X86) && x86_setup) {
+ zimage_dump(bflow->x86_setup, false);
+
+ return 0;
+ }
+
printf("Name: %s\n", bflow->name);
printf("Device: %s\n", bflow->dev->name);
printf("Block dev: %s\n", bflow->blk ? bflow->blk->name : "(none)");
@@ -369,6 +417,35 @@
return 0;
}
+static int do_bootflow_read(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct bootstd_priv *std;
+ struct bootflow *bflow;
+ int ret;
+
+ ret = bootstd_get_priv(&std);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ /*
+ * Require a current bootflow. Users can use 'bootflow scan -b' to
+ * automatically scan and boot, if needed.
+ */
+ if (!std->cur_bootflow) {
+ printf("No bootflow selected\n");
+ return CMD_RET_FAILURE;
+ }
+ bflow = std->cur_bootflow;
+ ret = bootflow_read_all(bflow);
+ if (ret) {
+ printf("Failed: err=%dE\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
static int do_bootflow_boot(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -416,18 +493,9 @@
if (ret)
return CMD_RET_FAILURE;
- ret = bootflow_menu_run(std, text_mode, &bflow);
- if (ret) {
- if (ret == -EAGAIN)
- printf("Nothing chosen\n");
- else {
- printf("Menu failed (err=%d)\n", ret);
- return CMD_RET_FAILURE;
- }
- }
-
- printf("Selected: %s\n", bflow->os_name ? bflow->os_name : bflow->name);
- std->cur_bootflow = bflow;
+ ret = bootflow_handle_menu(std, text_mode, &bflow);
+ if (ret)
+ return CMD_RET_FAILURE;
return 0;
}
@@ -502,20 +570,20 @@
}
#endif /* CONFIG_CMD_BOOTFLOW_FULL */
-#ifdef CONFIG_SYS_LONGHELP
-static char bootflow_help_text[] =
+U_BOOT_LONGHELP(bootflow,
#ifdef CONFIG_CMD_BOOTFLOW_FULL
"scan [-abeGl] [bdev] - scan for valid bootflows (-l list, -a all, -e errors, -b boot, -G no global)\n"
"bootflow list [-e] - list scanned bootflows (-e errors)\n"
"bootflow select [<num>|<name>] - select a bootflow\n"
- "bootflow info [-d] - show info on current bootflow (-d dump bootflow)\n"
- "bootflow boot - boot current bootflow (or first available if none selected)\n"
+ "bootflow info [-ds] - show info on current bootflow (-d dump bootflow)\n"
+ "bootflow read - read all current-bootflow files\n"
+ "bootflow boot - boot current bootflow\n"
"bootflow menu [-t] - show a menu of available bootflows\n"
- "bootflow cmdline [set|get|clear|delete|auto] <param> [<value>] - update cmdline";
+ "bootflow cmdline [set|get|clear|delete|auto] <param> [<value>] - update cmdline"
#else
- "scan - boot first available bootflow\n";
+ "scan - boot first available bootflow\n"
#endif
-#endif /* CONFIG_SYS_LONGHELP */
+ );
U_BOOT_CMD_WITH_SUBCMDS(bootflow, "Boot flows", bootflow_help_text,
U_BOOT_SUBCMD_MKENT(scan, 3, 1, do_bootflow_scan),
@@ -523,6 +591,7 @@
U_BOOT_SUBCMD_MKENT(list, 2, 1, do_bootflow_list),
U_BOOT_SUBCMD_MKENT(select, 2, 1, do_bootflow_select),
U_BOOT_SUBCMD_MKENT(info, 2, 1, do_bootflow_info),
+ U_BOOT_SUBCMD_MKENT(read, 1, 1, do_bootflow_read),
U_BOOT_SUBCMD_MKENT(boot, 1, 1, do_bootflow_boot),
U_BOOT_SUBCMD_MKENT(menu, 2, 1, do_bootflow_menu),
U_BOOT_SUBCMD_MKENT(cmdline, 4, 1, do_bootflow_cmdline),
diff --git a/cmd/booti.c b/cmd/booti.c
index 6ac3919..a6c7db2 100644
--- a/cmd/booti.c
+++ b/cmd/booti.c
@@ -127,6 +127,7 @@
#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
BOOTM_STATE_RAMDISK |
#endif
+ BOOTM_STATE_MEASURE |
BOOTM_STATE_OS_PREP | BOOTM_STATE_OS_FAKE_GO |
BOOTM_STATE_OS_GO,
&images, 1);
@@ -134,8 +135,7 @@
return ret;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char booti_help_text[] =
+U_BOOT_LONGHELP(booti,
"[addr [initrd[:size]] [fdt]]\n"
" - boot Linux flat or compressed 'Image' stored at 'addr'\n"
"\tThe argument 'initrd' is optional and specifies the address\n"
@@ -151,8 +151,7 @@
"\tis required. To boot a kernel with a device-tree blob but\n"
"\twithout an initrd image, use a '-' for the initrd argument.\n"
#endif
- "";
-#endif
+ );
U_BOOT_CMD(
booti, CONFIG_SYS_MAXARGS, 1, do_booti,
diff --git a/cmd/bootm.c b/cmd/bootm.c
index 37c2af9..6ded091 100644
--- a/cmd/bootm.c
+++ b/cmd/bootm.c
@@ -123,20 +123,6 @@
int states;
int ret;
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
- static int relocated = 0;
-
- if (!relocated) {
- int i;
-
- /* relocate names of sub-command table */
- for (i = 0; i < ARRAY_SIZE(cmd_bootm_sub); i++)
- cmd_bootm_sub[i].name += gd->reloc_off;
-
- relocated = 1;
- }
-#endif
-
/* determine if we have a sub command */
argc--; argv++;
if (argc > 0) {
@@ -161,6 +147,8 @@
BOOTM_STATE_OS_GO;
if (IS_ENABLED(CONFIG_SYS_BOOT_RAMDISK_HIGH))
states |= BOOTM_STATE_RAMDISK;
+ if (IS_ENABLED(CONFIG_MEASURED_BOOT))
+ states |= BOOTM_STATE_MEASURE;
if (IS_ENABLED(CONFIG_PPC) || IS_ENABLED(CONFIG_MIPS))
states |= BOOTM_STATE_OS_CMDLINE;
ret = do_bootm_states(cmdtp, flag, argc, argv, states, &images, 1);
@@ -182,8 +170,7 @@
return 0;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char bootm_help_text[] =
+U_BOOT_LONGHELP(bootm,
"[addr [arg ...]]\n - boot application image stored in memory\n"
"\tpassing arguments 'arg ...'; when booting a Linux kernel,\n"
"\t'arg' can be the address of an initrd image\n"
@@ -222,8 +209,7 @@
#if defined(CONFIG_TRACE)
"\tfake - OS specific fake start without go\n"
#endif
- "\tgo - start OS";
-#endif
+ "\tgo - start OS");
U_BOOT_CMD(
bootm, CONFIG_SYS_MAXARGS, 1, do_bootm,
diff --git a/cmd/bootmeth.c b/cmd/bootmeth.c
index 9fbcccd..f5b0134 100644
--- a/cmd/bootmeth.c
+++ b/cmd/bootmeth.c
@@ -104,11 +104,9 @@
return 0;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char bootmeth_help_text[] =
+U_BOOT_LONGHELP(bootmeth,
"list [-a] - list available bootmeths (-a all)\n"
- "bootmeth order [<bd> ...] - select bootmeth order / subset to use";
-#endif
+ "bootmeth order [<bd> ...] - select bootmeth order / subset to use");
U_BOOT_CMD_WITH_SUBCMDS(bootmeth, "Boot methods", bootmeth_help_text,
U_BOOT_SUBCMD_MKENT(list, 2, 1, do_bootmeth_list),
diff --git a/cmd/bootz.c b/cmd/bootz.c
index f142357..dd6fe49 100644
--- a/cmd/bootz.c
+++ b/cmd/bootz.c
@@ -81,6 +81,7 @@
#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
BOOTM_STATE_RAMDISK |
#endif
+ BOOTM_STATE_MEASURE |
BOOTM_STATE_OS_PREP | BOOTM_STATE_OS_FAKE_GO |
BOOTM_STATE_OS_GO,
&images, 1);
@@ -88,8 +89,7 @@
return ret;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char bootz_help_text[] =
+U_BOOT_LONGHELP(bootz,
"[addr [initrd[:size]] [fdt]]\n"
" - boot Linux zImage stored in memory\n"
"\tThe argument 'initrd' is optional and specifies the address\n"
@@ -102,8 +102,7 @@
"\tuse a '-' for the second argument. If you do not pass a third\n"
"\ta bd_info struct will be passed instead\n"
#endif
- "";
-#endif
+ );
U_BOOT_CMD(
bootz, CONFIG_SYS_MAXARGS, 1, do_bootz,
diff --git a/cmd/cat.c b/cmd/cat.c
index b059080..18aa6ca 100644
--- a/cmd/cat.c
+++ b/cmd/cat.c
@@ -60,11 +60,9 @@
return 0;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char cat_help_text[] =
+U_BOOT_LONGHELP(cat,
"<interface> <dev[:part]> <file>\n"
- " - Print file from 'dev' on 'interface' to standard output\n";
-#endif
+ " - Print file from 'dev' on 'interface' to standard output\n");
U_BOOT_CMD(cat, 4, 1, do_cat,
"Print file to standard output",
diff --git a/cmd/cbfs.c b/cmd/cbfs.c
index 8a61f2c..3cfc9eb 100644
--- a/cmd/cbfs.c
+++ b/cmd/cbfs.c
@@ -118,7 +118,7 @@
case CBFS_TYPE_CBFSHEADER:
type_name = "cbfs header";
break;
- case CBFS_TYPE_STAGE:
+ case CBFS_TYPE_LEGACY_STAGE:
type_name = "stage";
break;
case CBFS_TYPE_PAYLOAD:
diff --git a/cmd/cedit.c b/cmd/cedit.c
index 0cae304..6352e63 100644
--- a/cmd/cedit.c
+++ b/cmd/cedit.c
@@ -7,14 +7,29 @@
*/
#include <common.h>
+#include <abuf.h>
+#include <cedit.h>
#include <command.h>
+#include <dm.h>
#include <expo.h>
#include <fs.h>
+#include <malloc.h>
+#include <mapmem.h>
#include <dm/ofnode.h>
#include <linux/sizes.h>
struct expo *cur_exp;
+static int check_cur_expo(void)
+{
+ if (!cur_exp) {
+ printf("No expo loaded\n");
+ return -ENOENT;
+ }
+
+ return 0;
+}
+
static int do_cedit_load(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -53,18 +68,192 @@
return 0;
}
+static int do_cedit_write_fdt(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ const char *fname;
+ struct abuf buf;
+ loff_t bytes;
+ int ret;
+
+ if (argc < 4)
+ return CMD_RET_USAGE;
+ fname = argv[3];
+
+ if (check_cur_expo())
+ return CMD_RET_FAILURE;
+
+ ret = cedit_write_settings(cur_exp, &buf);
+ if (ret) {
+ printf("Failed to write settings: %dE\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ if (fs_set_blk_dev(argv[1], argv[2], FS_TYPE_ANY))
+ return CMD_RET_FAILURE;
+
+ ret = fs_write(fname, map_to_sysmem(abuf_data(&buf)), 0,
+ abuf_size(&buf), &bytes);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return 0;
+}
+
+static int do_cedit_read_fdt(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ const char *fname;
+ void *buf;
+ oftree tree;
+ ulong size;
+ int ret;
+
+ if (argc < 4)
+ return CMD_RET_USAGE;
+ fname = argv[3];
+
+ ret = fs_load_alloc(argv[1], argv[2], argv[3], SZ_1M, 0, &buf, &size);
+ if (ret) {
+ printf("File not found\n");
+ return CMD_RET_FAILURE;
+ }
+
+ tree = oftree_from_fdt(buf);
+ if (!oftree_valid(tree)) {
+ free(buf);
+ printf("Cannot create oftree\n");
+ return CMD_RET_FAILURE;
+ }
+
+ ret = cedit_read_settings(cur_exp, tree);
+ oftree_dispose(tree);
+ free(buf);
+ if (ret) {
+ printf("Failed to read settings: %dE\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
+static int do_cedit_write_env(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ bool verbose;
+ int ret;
+
+ if (check_cur_expo())
+ return CMD_RET_FAILURE;
+
+ verbose = argc > 1 && !strcmp(argv[1], "-v");
+
+ ret = cedit_write_settings_env(cur_exp, verbose);
+ if (ret) {
+ printf("Failed to write settings to environment: %dE\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
+static int do_cedit_read_env(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ bool verbose;
+ int ret;
+
+ if (check_cur_expo())
+ return CMD_RET_FAILURE;
+
+ verbose = argc > 1 && !strcmp(argv[1], "-v");
+
+ ret = cedit_read_settings_env(cur_exp, verbose);
+ if (ret) {
+ printf("Failed to read settings from environment: %dE\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
+static int do_cedit_write_cmos(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct udevice *dev;
+ bool verbose = false;
+ int ret;
+
+ if (check_cur_expo())
+ return CMD_RET_FAILURE;
+
+ if (argc > 1 && !strcmp(argv[1], "-v")) {
+ verbose = true;
+ argc--;
+ argv++;
+ }
+
+ if (argc > 1)
+ ret = uclass_get_device_by_name(UCLASS_RTC, argv[1], &dev);
+ else
+ ret = uclass_first_device_err(UCLASS_RTC, &dev);
+ if (ret) {
+ printf("Failed to get RTC device: %dE\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ if (cedit_write_settings_cmos(cur_exp, dev, verbose)) {
+ printf("Failed to write settings to CMOS\n");
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
+static int do_cedit_read_cmos(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct udevice *dev;
+ bool verbose = false;
+ int ret;
+
+ if (check_cur_expo())
+ return CMD_RET_FAILURE;
+
+ if (argc > 1 && !strcmp(argv[1], "-v")) {
+ verbose = true;
+ argc--;
+ argv++;
+ }
+
+ if (argc > 1)
+ ret = uclass_get_device_by_name(UCLASS_RTC, argv[1], &dev);
+ else
+ ret = uclass_first_device_err(UCLASS_RTC, &dev);
+ if (ret) {
+ printf("Failed to get RTC device: %dE\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ ret = cedit_read_settings_cmos(cur_exp, dev, verbose);
+ if (ret) {
+ printf("Failed to read settings from CMOS: %dE\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
static int do_cedit_run(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
ofnode node;
int ret;
- if (!cur_exp) {
- printf("No expo loaded\n");
+ if (check_cur_expo())
return CMD_RET_FAILURE;
- }
- node = ofnode_path("/cedit-theme");
+ node = ofnode_path("/bootstd/cedit-theme");
if (ofnode_valid(node)) {
ret = expo_apply_theme(cur_exp, node);
if (ret)
@@ -81,13 +270,23 @@
return 0;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char cedit_help_text[] =
+U_BOOT_LONGHELP(cedit,
"load <interface> <dev[:part]> <filename> - load config editor\n"
- "cedit run - run config editor";
-#endif /* CONFIG_SYS_LONGHELP */
+ "cedit read_fdt <i/f> <dev[:part]> <filename> - read settings\n"
+ "cedit write_fdt <i/f> <dev[:part]> <filename> - write settings\n"
+ "cedit read_env [-v] - read settings from env vars\n"
+ "cedit write_env [-v] - write settings to env vars\n"
+ "cedit read_cmos [-v] [dev] - read settings from CMOS RAM\n"
+ "cedit write_cmos [-v] [dev] - write settings to CMOS RAM\n"
+ "cedit run - run config editor");
U_BOOT_CMD_WITH_SUBCMDS(cedit, "Configuration editor", cedit_help_text,
U_BOOT_SUBCMD_MKENT(load, 5, 1, do_cedit_load),
+ U_BOOT_SUBCMD_MKENT(read_fdt, 5, 1, do_cedit_read_fdt),
+ U_BOOT_SUBCMD_MKENT(write_fdt, 5, 1, do_cedit_write_fdt),
+ U_BOOT_SUBCMD_MKENT(read_env, 2, 1, do_cedit_read_env),
+ U_BOOT_SUBCMD_MKENT(write_env, 2, 1, do_cedit_write_env),
+ U_BOOT_SUBCMD_MKENT(read_cmos, 2, 1, do_cedit_read_cmos),
+ U_BOOT_SUBCMD_MKENT(write_cmos, 2, 1, do_cedit_write_cmos),
U_BOOT_SUBCMD_MKENT(run, 1, 1, do_cedit_run),
);
diff --git a/cmd/clk.c b/cmd/clk.c
index ff7c764..c7c379d 100644
--- a/cmd/clk.c
+++ b/cmd/clk.c
@@ -152,10 +152,8 @@
return CMD_RET_USAGE;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char clk_help_text[] =
+U_BOOT_LONGHELP(clk,
"dump - Print clock frequencies\n"
- "clk setfreq [clk] [freq] - Set clock frequency";
-#endif
+ "clk setfreq [clk] [freq] - Set clock frequency");
U_BOOT_CMD(clk, 4, 1, do_clk, "CLK sub-system", clk_help_text);
diff --git a/cmd/conitrace.c b/cmd/conitrace.c
index d50f3bf..9a1bc35 100644
--- a/cmd/conitrace.c
+++ b/cmd/conitrace.c
@@ -41,9 +41,7 @@
return CMD_RET_SUCCESS;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char conitrace_help_text[] = "";
-#endif
+U_BOOT_LONGHELP(conitrace, "");
U_BOOT_CMD_COMPLETE(
conitrace, 2, 0, do_conitrace,
diff --git a/cmd/cpu.c b/cmd/cpu.c
index 3148524..245a82f 100644
--- a/cmd/cpu.c
+++ b/cmd/cpu.c
@@ -83,12 +83,9 @@
return 0;
}
-#if IS_ENABLED(CONFIG_SYS_LONGHELP)
-static char cpu_help_text[] =
+U_BOOT_LONGHELP(cpu,
"list - list available CPUs\n"
- "cpu detail - show CPU detail"
- ;
-#endif
+ "cpu detail - show CPU detail");
U_BOOT_CMD_WITH_SUBCMDS(cpu, "display information about CPUs", cpu_help_text,
U_BOOT_SUBCMD_MKENT(list, 1, 1, do_cpu_list),
diff --git a/cmd/cyclic.c b/cmd/cyclic.c
index 946f1d7..ad7fc3b 100644
--- a/cmd/cyclic.c
+++ b/cmd/cyclic.c
@@ -76,9 +76,9 @@
return 0;
}
-static char cyclic_help_text[] =
+U_BOOT_LONGHELP(cyclic,
"demo <cycletime_ms> <delay_us> - register cyclic demo function\n"
- "cyclic list - list cyclic functions\n";
+ "cyclic list - list cyclic functions\n");
U_BOOT_CMD_WITH_SUBCMDS(cyclic, "Cyclic", cyclic_help_text,
U_BOOT_SUBCMD_MKENT(demo, 3, 1, do_cyclic_demo),
diff --git a/cmd/date.c b/cmd/date.c
index fe9c8c6..4f98b47 100644
--- a/cmd/date.c
+++ b/cmd/date.c
@@ -20,12 +20,6 @@
"Sun", "Mon", "Tues", "Wednes", "Thurs", "Fri", "Satur",
};
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
-#define RELOC(a) ((typeof(a))((unsigned long)(a) + gd->reloc_off))
-#else
-#define RELOC(a) a
-#endif
-
int mk_date (const char *, struct rtc_time *);
static struct rtc_time default_tm = { 0, 0, 0, 1, 1, 2000, 6, 0, 0 };
@@ -113,7 +107,7 @@
printf ("Date: %4d-%02d-%02d (%sday) Time: %2d:%02d:%02d\n",
tm.tm_year, tm.tm_mon, tm.tm_mday,
(tm.tm_wday<0 || tm.tm_wday>6) ?
- "unknown " : RELOC(weekdays[tm.tm_wday]),
+ "unknown " : weekdays[tm.tm_wday],
tm.tm_hour, tm.tm_min, tm.tm_sec);
break;
diff --git a/cmd/dm.c b/cmd/dm.c
index 3263547..fb605c2 100644
--- a/cmd/dm.c
+++ b/cmd/dm.c
@@ -59,11 +59,26 @@
static int do_dm_dump_tree(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- bool sort;
+ bool extended = false, sort = false;
+ char *device = NULL;
- sort = argc > 1 && !strcmp(argv[1], "-s");
+ for (; argc > 1; argc--, argv++) {
+ if (argv[1][0] != '-')
+ break;
- dm_dump_tree(sort);
+ if (!strcmp(argv[1], "-e")) {
+ extended = true;
+ } else if (!strcmp(argv[1], "-s")) {
+ sort = true;
+ } else {
+ printf("Unknown parameter: %s\n", argv[1]);
+ return 0;
+ }
+ }
+ if (argc > 1)
+ device = argv[1];
+
+ dm_dump_tree(device, extended, sort);
return 0;
}
@@ -71,7 +86,20 @@
static int do_dm_dump_uclass(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- dm_dump_uclass();
+ bool extended = false;
+ char *uclass = NULL;
+
+ if (argc > 1) {
+ if (!strcmp(argv[1], "-e")) {
+ extended = true;
+ argc--;
+ argv++;
+ }
+ if (argc > 1)
+ uclass = argv[1];
+ }
+
+ dm_dump_uclass(uclass, extended);
return 0;
}
@@ -84,17 +112,14 @@
#define DM_MEM
#endif
-#if IS_ENABLED(CONFIG_SYS_LONGHELP)
-static char dm_help_text[] =
+U_BOOT_LONGHELP(dm,
"compat Dump list of drivers with compatibility strings\n"
"dm devres Dump list of device resources for each device\n"
"dm drivers Dump list of drivers with uclass and instances\n"
DM_MEM_HELP
"dm static Dump list of drivers with static platform data\n"
- "dm tree [-s] Dump tree of driver model devices (-s=sort)\n"
- "dm uclass Dump list of instances for each uclass"
- ;
-#endif
+ "dm tree [-s][-e][name] Dump tree of driver model devices (-s=sort)\n"
+ "dm uclass [-e][name] Dump list of instances for each uclass");
U_BOOT_CMD_WITH_SUBCMDS(dm, "Driver model low level access", dm_help_text,
U_BOOT_SUBCMD_MKENT(compat, 1, 1, do_dm_dump_driver_compat),
@@ -102,5 +127,5 @@
U_BOOT_SUBCMD_MKENT(drivers, 1, 1, do_dm_dump_drivers),
DM_MEM
U_BOOT_SUBCMD_MKENT(static, 1, 1, do_dm_dump_static_driver_info),
- U_BOOT_SUBCMD_MKENT(tree, 2, 1, do_dm_dump_tree),
- U_BOOT_SUBCMD_MKENT(uclass, 1, 1, do_dm_dump_uclass));
+ U_BOOT_SUBCMD_MKENT(tree, 4, 1, do_dm_dump_tree),
+ U_BOOT_SUBCMD_MKENT(uclass, 3, 1, do_dm_dump_uclass));
diff --git a/cmd/efi_common.c b/cmd/efi_common.c
index f405609..1aa2351 100644
--- a/cmd/efi_common.c
+++ b/cmd/efi_common.c
@@ -17,10 +17,8 @@
for (i = 0; i < systab->nr_tables; i++) {
struct efi_configuration_table *tab = &systab->tables[i];
- char guid_str[37];
- uuid_bin_to_str(tab->guid.b, guid_str, 1);
- printf("%p %pUl %s\n", tab->table, guid_str,
+ printf("%p %pUl %s\n", tab->table, tab->guid.b,
uuid_guid_get_str(tab->guid.b) ?: "(unknown)");
}
}
diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c
index e6e8a0a..34a59cb 100644
--- a/cmd/eficonfig.c
+++ b/cmd/eficonfig.c
@@ -528,7 +528,10 @@
p += fp_size;
*((struct efi_device_path *)p) = END;
- dp = efi_dp_append(dp_volume, (struct efi_device_path *)buf);
+ dp = efi_dp_shorten(dp_volume);
+ if (!dp)
+ dp = dp_volume;
+ dp = efi_dp_append(dp, &fp->dp);
free(buf);
return dp;
diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index 0be3af3..201531a 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -1484,8 +1484,7 @@
return cp->cmd(cmdtp, flag, argc, argv);
}
-#ifdef CONFIG_SYS_LONGHELP
-static char efidebug_help_text[] =
+U_BOOT_LONGHELP(efidebug,
" - UEFI Shell-like interface to configure UEFI environment\n"
"\n"
"efidebug boot add - set UEFI BootXXXX variable\n"
@@ -1532,8 +1531,7 @@
" - run simple bootmgr for test\n"
#endif
"efidebug query [-nv][-bs][-rt][-at]\n"
- " - show size of UEFI variables store\n";
-#endif
+ " - show size of UEFI variables store\n");
U_BOOT_CMD(
efidebug, CONFIG_SYS_MAXARGS, 0, do_efidebug,
diff --git a/cmd/event.c b/cmd/event.c
index b4b779f..f6cdb55 100644
--- a/cmd/event.c
+++ b/cmd/event.c
@@ -18,10 +18,8 @@
return 0;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char event_help_text[] =
- "list - list event spies";
-#endif
+U_BOOT_LONGHELP(event,
+ "list - list event spies");
U_BOOT_CMD_WITH_SUBCMDS(event, "Events", event_help_text,
U_BOOT_SUBCMD_MKENT(list, 1, 1, do_event_list));
diff --git a/cmd/fastboot.c b/cmd/fastboot.c
index 22c485b..785ae93 100644
--- a/cmd/fastboot.c
+++ b/cmd/fastboot.c
@@ -15,6 +15,7 @@
#include <net6.h>
#include <usb.h>
#include <watchdog.h>
+#include <linux/printk.h>
#include <linux/stringify.h>
static int do_fastboot_udp(int argc, char *const argv[],
@@ -62,6 +63,7 @@
{
int controller_index;
char *usb_controller;
+ struct udevice *udc;
char *endp;
int ret;
@@ -80,7 +82,7 @@
return CMD_RET_FAILURE;
}
- ret = usb_gadget_initialize(controller_index);
+ ret = udc_device_get_by_index(controller_index, &udc);
if (ret) {
pr_err("USB init failed: %d\n", ret);
return CMD_RET_FAILURE;
@@ -104,13 +106,13 @@
if (ctrlc())
break;
schedule();
- usb_gadget_handle_interrupts(controller_index);
+ dm_usb_gadget_handle_interrupts(udc);
}
ret = CMD_RET_SUCCESS;
exit:
- usb_gadget_release(controller_index);
+ udc_device_put(udc);
g_dnl_unregister();
g_dnl_clear_detach();
diff --git a/cmd/fdt.c b/cmd/fdt.c
index 2401ea8..331564c 100644
--- a/cmd/fdt.c
+++ b/cmd/fdt.c
@@ -1113,8 +1113,7 @@
}
/********************************************************************/
-#ifdef CONFIG_SYS_LONGHELP
-static char fdt_help_text[] =
+U_BOOT_LONGHELP(fdt,
"addr [-c] [-q] <addr> [<size>] - Set the [control] fdt location to <addr>\n"
#ifdef CONFIG_OF_LIBFDT_OVERLAY
"fdt apply <addr> - Apply overlay to the DT\n"
@@ -1153,8 +1152,7 @@
" default gd->fdt_blob\n"
#endif
"NOTE: Dereference aliases by omitting the leading '/', "
- "e.g. fdt print ethernet0.";
-#endif
+ "e.g. fdt print ethernet0.");
U_BOOT_CMD(
fdt, 255, 0, do_fdt,
diff --git a/cmd/font.c b/cmd/font.c
index fe2d65c..cb39c88 100644
--- a/cmd/font.c
+++ b/cmd/font.c
@@ -79,12 +79,10 @@
}
-#ifdef CONFIG_SYS_LONGHELP
-static char font_help_text[] =
+U_BOOT_LONGHELP(font,
"list - list available fonts\n"
"font select <name> [<size>] - select font to use\n"
- "font size <size> - select font size to";
-#endif
+ "font size <size> - select font size to");
U_BOOT_CMD_WITH_SUBCMDS(font, "Fonts", font_help_text,
U_BOOT_SUBCMD_MKENT(list, 1, 1, do_font_list),
diff --git a/cmd/gpio.c b/cmd/gpio.c
index f456598..dab6f70 100644
--- a/cmd/gpio.c
+++ b/cmd/gpio.c
@@ -17,6 +17,7 @@
#endif
#include <asm/gpio.h>
#include <linux/err.h>
+#include <dm/device_compat.h>
__weak int name_to_gpio(const char *name)
{
@@ -69,7 +70,8 @@
printf("%s\n", buf);
return;
err:
- printf("Error %d\n", ret);
+ if (ret != -ENOENT)
+ printf("Error %d\n", ret);
}
static int do_gpio_status(bool all, const char *gpio_name)
diff --git a/cmd/gpt.c b/cmd/gpt.c
index fe9e066..d7e9652 100644
--- a/cmd/gpt.c
+++ b/cmd/gpt.c
@@ -162,22 +162,31 @@
return result;
}
+/**
+ * calc_parts_list_len() - get size of partition table description
+ *
+ * @numparts: number of partitions
+ * Return: string size including terminating NUL
+ */
static int calc_parts_list_len(int numparts)
{
- int partlistlen = UUID_STR_LEN + 1 + strlen("uuid_disk=");
- /* for the comma */
- partlistlen++;
+ /* number of hexadecimal digits of the lbaint_t representation */
+ const int lbaint_size = 2 * sizeof(lbaint_t);
+ int partlistlen;
- /* per-partition additions; numparts starts at 1, so this should be correct */
- partlistlen += numparts * (strlen("name=,") + PART_NAME_LEN + 1);
+ /* media description including terminating NUL */
+ partlistlen = strlen("uuid_disk=;") + UUID_STR_LEN + 1;
+ /* per-partition descriptions; numparts */
+ partlistlen += numparts * (strlen("name=,") + PART_NAME_LEN);
/* see part.h for definition of struct disk_partition */
- partlistlen += numparts * (strlen("start=MiB,") + sizeof(lbaint_t) + 1);
- partlistlen += numparts * (strlen("size=MiB,") + sizeof(lbaint_t) + 1);
- partlistlen += numparts * (strlen("uuid=;") + UUID_STR_LEN + 1);
- /* for the terminating null */
- partlistlen++;
- debug("Length of partitions_list is %d for %d partitions\n", partlistlen,
- numparts);
+ partlistlen += numparts * (strlen("start=0x,") + lbaint_size);
+ partlistlen += numparts * (strlen("size=0x,") + lbaint_size);
+ if (IS_ENABLED(CONFIG_PARTITION_UUIDS))
+ partlistlen += numparts * (strlen("uuid=,") + UUID_STR_LEN);
+ if (IS_ENABLED(CONFIG_PARTITION_TYPE_GUID))
+ partlistlen += numparts * (strlen("type=;") + UUID_STR_LEN);
+ debug("Length of partitions_list is %d for %d partitions\n",
+ partlistlen, numparts);
return partlistlen;
}
@@ -211,12 +220,12 @@
PART_TYPE_LEN);
newpart->gpt_part_info.type[PART_TYPE_LEN - 1] = '\0';
newpart->gpt_part_info.bootable = info->bootable;
-#ifdef CONFIG_PARTITION_UUIDS
- strncpy(newpart->gpt_part_info.uuid, (const char *)info->uuid,
- UUID_STR_LEN);
- /* UUID_STR_LEN is correct, as uuid[]'s length is UUID_STR_LEN+1 chars */
- newpart->gpt_part_info.uuid[UUID_STR_LEN] = '\0';
-#endif
+ if (IS_ENABLED(CONFIG_PARTITION_UUIDS))
+ disk_partition_set_uuid(&newpart->gpt_part_info,
+ disk_partition_uuid(info));
+ if (IS_ENABLED(CONFIG_PARTITION_TYPE_GUID))
+ disk_partition_set_type_guid(&newpart->gpt_part_info,
+ disk_partition_type_guid(info));
newpart->partnum = partnum;
return newpart;
@@ -252,9 +261,12 @@
curr->gpt_part_info.name);
printf("Type %s, bootable %d\n", curr->gpt_part_info.type,
curr->gpt_part_info.bootable & PART_BOOTABLE);
-#ifdef CONFIG_PARTITION_UUIDS
- printf("UUID %s\n", curr->gpt_part_info.uuid);
-#endif
+ if (CONFIG_IS_ENABLED(PARTITION_UUIDS))
+ printf("UUID %s\n",
+ disk_partition_uuid(&curr->gpt_part_info));
+ if (IS_ENABLED(CONFIG_PARTITION_TYPE_GUID))
+ printf("Type GUID %s\n",
+ disk_partition_type_guid(&curr->gpt_part_info));
printf("\n");
}
}
@@ -299,9 +311,20 @@
curr->gpt_part_info.blksz);
strncat(partitions_list, partstr, PART_NAME_LEN + 1);
- strcat(partitions_list, ",uuid=");
- strncat(partitions_list, curr->gpt_part_info.uuid,
- UUID_STR_LEN + 1);
+ if (IS_ENABLED(CONFIG_PARTITION_TYPE_GUID)) {
+ strcat(partitions_list, ",type=");
+ strncat(partitions_list,
+ disk_partition_type_guid(&curr->gpt_part_info),
+ UUID_STR_LEN + 1);
+ }
+ if (CONFIG_IS_ENABLED(PARTITION_UUIDS)) {
+ strcat(partitions_list, ",uuid=");
+ strncat(partitions_list,
+ disk_partition_uuid(&curr->gpt_part_info),
+ UUID_STR_LEN + 1);
+ }
+ if (curr->gpt_part_info.bootable & PART_BOOTABLE)
+ strcat(partitions_list, ",bootable");
strcat(partitions_list, ";");
}
return 0;
@@ -725,7 +748,7 @@
* gpt_setenv_part_variables() - setup partition environmental variables
*
* Setup the gpt_partition_name, gpt_partition_entry, gpt_partition_addr
- * and gpt_partition_size environment variables.
+ * and gpt_partition_size, gpt_partition_bootable environment variables.
*
* @pinfo: pointer to disk partition
* @i: partition entry
@@ -752,6 +775,10 @@
if (ret)
goto fail;
+ ret = env_set_ulong("gpt_partition_bootable", !!(pinfo->bootable & PART_BOOTABLE));
+ if (ret)
+ goto fail;
+
return 0;
fail:
@@ -835,8 +862,9 @@
u8 part_count = 0;
int partlistlen, ret, numparts = 0, partnum, i = 1, ctr1 = 0, ctr2 = 0;
- if ((subcomm == NULL) || (name1 == NULL) || (name2 == NULL) ||
- (strcmp(subcomm, "swap") && (strcmp(subcomm, "rename"))))
+ if (!subcomm || !name1 || !name2 ||
+ (strcmp(subcomm, "swap") && strcmp(subcomm, "rename") &&
+ strcmp(subcomm, "transpose")))
return -EINVAL;
ret = get_disk_guid(dev_desc, disk_guid);
@@ -897,6 +925,41 @@
ret = -EINVAL;
goto out;
}
+ } else if (!strcmp(subcomm, "transpose")) {
+ int idx1, idx2;
+ struct disk_partition* first = NULL;
+ struct disk_partition* second= NULL;
+ struct disk_partition tmp_part;
+
+ idx1 = simple_strtoul(name1, NULL, 10);
+ idx2 = simple_strtoul(name2, NULL, 10);
+ if (idx1 == idx2) {
+ printf("Cannot swap partition with itself\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ list_for_each(pos, &disk_partitions) {
+ curr = list_entry(pos, struct disk_part, list);
+ if (curr->partnum == idx1)
+ first = &curr->gpt_part_info;
+ else if (curr->partnum == idx2)
+ second = &curr->gpt_part_info;
+ }
+ if (!first) {
+ printf("Illegal partition number %s\n", name1);
+ ret = -EINVAL;
+ goto out;
+ }
+ if (!second) {
+ printf("Illegal partition number %s\n", name2);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ tmp_part = *first;
+ *first = *second;
+ *second = tmp_part;
} else { /* rename */
if (strlen(name2) > PART_NAME_LEN) {
printf("Names longer than %d characters are truncated.\n", PART_NAME_LEN);
@@ -968,6 +1031,81 @@
free(partitions_list);
return ret;
}
+
+/**
+ * gpt_set_bootable() - Set bootable flags for partitions
+ *
+ * Sets the bootable flag for any partition names in the comma separated list of
+ * partition names. Any partitions not in the list have their bootable flag
+ * cleared
+ *
+ * @desc: block device descriptor
+ * @name: Comma separated list of partition names
+ *
+ * @Return: '0' on success and -ve error on failure
+ */
+static int gpt_set_bootable(struct blk_desc *blk_dev_desc, char *const part_list)
+{
+ char *name;
+ char disk_guid[UUID_STR_LEN + 1];
+ struct list_head *pos;
+ struct disk_part *curr;
+ struct disk_partition *partitions = NULL;
+ int part_count = 0;
+ int ret = get_disk_guid(blk_dev_desc, disk_guid);
+
+ if (ret < 0)
+ return ret;
+
+ ret = get_gpt_info(blk_dev_desc);
+ if (ret <= 0)
+ goto out;
+
+ part_count = ret;
+ partitions = malloc(sizeof(*partitions) * part_count);
+ if (!partitions) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ /* Copy partitions and clear bootable flag */
+ part_count = 0;
+ list_for_each(pos, &disk_partitions) {
+ curr = list_entry(pos, struct disk_part, list);
+ partitions[part_count] = curr->gpt_part_info;
+ partitions[part_count].bootable &= ~PART_BOOTABLE;
+ part_count++;
+ }
+
+ name = strtok(part_list, ",");
+ while (name) {
+ bool found = false;
+
+ for (int i = 0; i < part_count; i++) {
+ if (strcmp((char *)partitions[i].name, name) == 0) {
+ partitions[i].bootable |= PART_BOOTABLE;
+ found = true;
+ }
+ }
+
+ if (!found) {
+ printf("Warning: No partition matching '%s' found\n",
+ name);
+ }
+
+ name = strtok(NULL, ",");
+ }
+
+ ret = gpt_restore(blk_dev_desc, disk_guid, partitions, part_count);
+
+out:
+ del_gpt_info();
+
+ if (partitions)
+ free(partitions);
+
+ return ret;
+}
#endif
/**
@@ -1025,8 +1163,11 @@
} else if (strcmp(argv[1], "read") == 0) {
ret = do_get_gpt_info(blk_dev_desc, (argc == 5) ? argv[4] : NULL);
} else if ((strcmp(argv[1], "swap") == 0) ||
- (strcmp(argv[1], "rename") == 0)) {
+ (strcmp(argv[1], "rename") == 0) ||
+ (strcmp(argv[1], "transpose") == 0)) {
ret = do_rename_gpt_parts(blk_dev_desc, argv[1], argv[4], argv[5]);
+ } else if ((strcmp(argv[1], "set-bootable") == 0)) {
+ ret = gpt_set_bootable(blk_dev_desc, argv[4]);
#endif
} else {
return CMD_RET_USAGE;
@@ -1057,7 +1198,8 @@
" gpt setenv mmc 0 $name\n"
" - setup environment variables for partition $name:\n"
" gpt_partition_addr, gpt_partition_size,\n"
- " gpt_partition_name, gpt_partition_entry\n"
+ " gpt_partition_name, gpt_partition_entry,\n"
+ " gpt_partition_bootable\n"
" gpt enumerate mmc 0\n"
" - store list of partitions to gpt_partition_list environment variable\n"
" gpt guid <interface> <dev>\n"
@@ -1075,10 +1217,16 @@
" gpt swap <interface> <dev> <name1> <name2>\n"
" - change all partitions named name1 to name2\n"
" and vice-versa\n"
+ " gpt transpose <interface> <dev> <part1> <part2>\n"
+ " - Swap the order of the entries for part1 and part2 in the partition table\n"
" gpt rename <interface> <dev> <part> <name>\n"
" - rename the specified partition\n"
+ " gpt set-bootable <interface> <dev> <list>\n"
+ " - make partition names in list bootable\n"
" Example usage:\n"
" gpt swap mmc 0 foo bar\n"
" gpt rename mmc 0 3 foo\n"
+ " gpt set-bootable mmc 0 boot_a,boot_b\n"
+ " gpt transpose mmc 0 1 2\n"
#endif
);
diff --git a/cmd/help.c b/cmd/help.c
index 8d67d97..9f8393e 100644
--- a/cmd/help.c
+++ b/cmd/help.c
@@ -29,7 +29,10 @@
);
#ifdef CONFIG_CMDLINE
-/* This does not use the U_BOOT_CMD macro as ? can't be used in symbol names */
+/*
+ * This does not use the U_BOOT_CMD macro as ? can't be used in symbol names
+ * nor can we rely on the CONFIG_SYS_LONGHELP helper macro
+ */
ll_entry_declare(struct cmd_tbl, question_mark, cmd) = {
"?", CONFIG_SYS_MAXARGS, cmd_always_repeatable, do_help,
"alias for 'help'",
diff --git a/cmd/history.c b/cmd/history.c
new file mode 100644
index 0000000..b6bf467
--- /dev/null
+++ b/cmd/history.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cli.h>
+
+static int do_history(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ cread_print_hist_list();
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ history, CONFIG_SYS_MAXARGS, 1, do_history,
+ "print command history",
+ ""
+);
diff --git a/cmd/host.c b/cmd/host.c
index fb1cb1f..c33c2a9 100644
--- a/cmd/host.c
+++ b/cmd/host.c
@@ -13,6 +13,7 @@
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
#include <linux/errno.h>
+#include <linux/log2.h>
static int do_host_load(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
@@ -45,6 +46,7 @@
struct udevice *dev;
const char *label;
char *file;
+ unsigned long blksz = DEFAULT_BLKSZ;
int ret;
/* Skip 'bind' */
@@ -59,12 +61,19 @@
argv++;
}
- if (argc > 2)
+ if (argc < 2 || argc > 3)
return CMD_RET_USAGE;
label = argv[0];
- file = argc > 1 ? argv[1] : NULL;
+ file = argv[1];
+ if (argc > 2) {
+ blksz = dectoul(argv[2], NULL);
+ if (blksz < DEFAULT_BLKSZ || !is_power_of_2(blksz)) {
+ printf("blksz must be >= 512 and power of 2\n");
+ return CMD_RET_FAILURE;
+ }
+ }
- ret = host_create_attach_file(label, file, removable, &dev);
+ ret = host_create_attach_file(label, file, removable, blksz, &dev);
if (ret) {
printf("Cannot create device / bind file\n");
return CMD_RET_FAILURE;
@@ -151,8 +160,8 @@
return;
desc = dev_get_uclass_plat(blk);
- printf("%12lu %-15s %s\n", (unsigned long)desc->lba, plat->label,
- plat->filename);
+ printf("%12lu %6lu %-15s %s\n", (unsigned long)desc->lba, desc->blksz,
+ plat->label, plat->filename);
}
static int do_host_info(struct cmd_tbl *cmdtp, int flag, int argc,
@@ -170,7 +179,8 @@
return CMD_RET_FAILURE;
}
- printf("%3s %12s %-15s %s\n", "dev", "blocks", "label", "path");
+ printf("%3s %12s %6s %-15s %s\n",
+ "dev", "blocks", "blksz", "label", "path");
if (dev) {
show_host_dev(dev);
} else {
@@ -253,7 +263,8 @@
"host save hostfs - <addr> <filename> <bytes> [<offset>] - "
"save a file to host\n"
"host size hostfs - <filename> - determine size of file on host\n"
- "host bind [-r] <label> [<filename>] - bind \"host\" device to file\n"
+ "host bind [-r] <label> <filename> [<blksz>] - bind \"host\" device to file,\n"
+ " and optionally set the device's logical block size\n"
" -r = mark as removable\n"
"host unbind <label> - unbind file from \"host\" device\n"
"host info [<label>] - show device binding & info\n"
diff --git a/cmd/i2c.c b/cmd/i2c.c
index dd803ee..8083156 100644
--- a/cmd/i2c.c
+++ b/cmd/i2c.c
@@ -1939,16 +1939,6 @@
U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""),
};
-static __maybe_unused void i2c_reloc(void)
-{
- static int relocated;
-
- if (!relocated) {
- fixup_cmdtable(cmd_i2c_sub, ARRAY_SIZE(cmd_i2c_sub));
- relocated = 1;
- };
-}
-
/**
* do_i2c() - Handle the "i2c" command-line command
* @cmdtp: Command data struct pointer
@@ -1963,10 +1953,6 @@
{
struct cmd_tbl *c;
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
- i2c_reloc();
-#endif
-
if (argc < 2)
return CMD_RET_USAGE;
@@ -1983,8 +1969,7 @@
}
/***************************************************/
-#ifdef CONFIG_SYS_LONGHELP
-static char i2c_help_text[] =
+U_BOOT_LONGHELP(i2c,
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C)
"bus [muxtype:muxaddr:muxchannel] - show I2C bus info\n"
"i2c " /* That's the prefix for the crc32 command below. */
@@ -2013,8 +1998,7 @@
#if defined(CONFIG_CMD_SDRAM)
"i2c sdram chip - print SDRAM configuration information\n"
#endif
- "i2c speed [speed] - show or set I2C bus speed";
-#endif
+ "i2c speed [speed] - show or set I2C bus speed");
U_BOOT_CMD(
i2c, 7, 1, do_i2c,
diff --git a/cmd/kaslrseed.c b/cmd/kaslrseed.c
index 8a1d812..9acb8e1 100644
--- a/cmd/kaslrseed.c
+++ b/cmd/kaslrseed.c
@@ -68,11 +68,9 @@
return ret;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char kaslrseed_help_text[] =
+U_BOOT_LONGHELP(kaslrseed,
"[n]\n"
- " - append random bytes to chosen kaslr-seed node\n";
-#endif
+ " - append random bytes to chosen kaslr-seed node\n");
U_BOOT_CMD(
kaslrseed, 1, 0, do_kaslr_seed,
diff --git a/cmd/log.c b/cmd/log.c
index c377aee..c9a23e4 100644
--- a/cmd/log.c
+++ b/cmd/log.c
@@ -375,8 +375,7 @@
return 0;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char log_help_text[] =
+U_BOOT_LONGHELP(log,
"level [<level>] - get/set log level\n"
"categories - list log categories\n"
"drivers - list log drivers\n"
@@ -405,9 +404,7 @@
"\tc=category, l=level, F=file, L=line number, f=function, m=msg\n"
"\tor 'default', or 'all' for all\n"
"log rec <category> <level> <file> <line> <func> <message> - "
- "output a log record"
- ;
-#endif
+ "output a log record");
U_BOOT_CMD_WITH_SUBCMDS(log, "log system", log_help_text,
U_BOOT_SUBCMD_MKENT(level, 2, 1, do_log_level),
diff --git a/cmd/mac.c b/cmd/mac.c
deleted file mode 100644
index a39e116..0000000
--- a/cmd/mac.c
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2006 Freescale Semiconductor
- * York Sun (yorksun@freescale.com)
- */
-
-#include <common.h>
-#include <command.h>
-
-extern int do_mac(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[]);
-
-U_BOOT_CMD(
- mac, 3, 1, do_mac,
- "display and program the system ID and MAC addresses in EEPROM",
- "[read|save|id|num|errata|date|ports|port_number]\n"
- "mac read\n"
- " - read EEPROM content into memory data structure\n"
- "mac save\n"
- " - save memory data structure to the EEPROM\n"
- "mac id\n"
- " - program system id per hard coded value\n"
- "mac num string\n"
- " - program system serial number to value string\n"
- "mac errata string\n"
- " - program errata data to value string\n"
- "mac date YYMMDDhhmmss\n"
- " - program date to string value YYMMDDhhmmss\n"
- "mac ports N\n"
- " - program the number of network ports to integer N\n"
- "mac X string\n"
- " - program MAC addr for port X [X=0,1..] to colon separated string"
-);
diff --git a/cmd/mmc.c b/cmd/mmc.c
index c6bd81c..96befb2 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -1110,6 +1110,93 @@
return CMD_RET_SUCCESS;
}
+#if CONFIG_IS_ENABLED(CMD_MMC_REG)
+static int do_mmc_reg(struct cmd_tbl *cmdtp, int flag,
+ int argc, char *const argv[])
+{
+ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
+ struct mmc *mmc;
+ int i, ret;
+ u32 off;
+
+ if (argc < 3 || argc > 5)
+ return CMD_RET_USAGE;
+
+ mmc = find_mmc_device(curr_device);
+ if (!mmc) {
+ printf("no mmc device at slot %x\n", curr_device);
+ return CMD_RET_FAILURE;
+ }
+
+ if (IS_SD(mmc)) {
+ printf("SD registers are not supported\n");
+ return CMD_RET_FAILURE;
+ }
+
+ off = simple_strtoul(argv[3], NULL, 10);
+ if (!strcmp(argv[2], "cid")) {
+ if (off > 3)
+ return CMD_RET_USAGE;
+ printf("CID[%i]: 0x%08x\n", off, mmc->cid[off]);
+ if (argv[4])
+ env_set_hex(argv[4], mmc->cid[off]);
+ return CMD_RET_SUCCESS;
+ }
+ if (!strcmp(argv[2], "csd")) {
+ if (off > 3)
+ return CMD_RET_USAGE;
+ printf("CSD[%i]: 0x%08x\n", off, mmc->csd[off]);
+ if (argv[4])
+ env_set_hex(argv[4], mmc->csd[off]);
+ return CMD_RET_SUCCESS;
+ }
+ if (!strcmp(argv[2], "dsr")) {
+ printf("DSR: 0x%08x\n", mmc->dsr);
+ if (argv[4])
+ env_set_hex(argv[4], mmc->dsr);
+ return CMD_RET_SUCCESS;
+ }
+ if (!strcmp(argv[2], "ocr")) {
+ printf("OCR: 0x%08x\n", mmc->ocr);
+ if (argv[4])
+ env_set_hex(argv[4], mmc->ocr);
+ return CMD_RET_SUCCESS;
+ }
+ if (!strcmp(argv[2], "rca")) {
+ printf("RCA: 0x%08x\n", mmc->rca);
+ if (argv[4])
+ env_set_hex(argv[4], mmc->rca);
+ return CMD_RET_SUCCESS;
+ }
+ if (!strcmp(argv[2], "extcsd") &&
+ mmc->version >= MMC_VERSION_4_41) {
+ ret = mmc_send_ext_csd(mmc, ext_csd);
+ if (ret)
+ return CMD_RET_FAILURE;
+ if (!strcmp(argv[3], "all")) {
+ /* Dump the entire register */
+ printf("EXT_CSD:");
+ for (i = 0; i < MMC_MAX_BLOCK_LEN; i++) {
+ if (!(i % 10))
+ printf("\n%03i: ", i);
+ printf(" %02x", ext_csd[i]);
+ }
+ printf("\n");
+ return CMD_RET_SUCCESS;
+ }
+ off = simple_strtoul(argv[3], NULL, 10);
+ if (off > 512)
+ return CMD_RET_USAGE;
+ printf("EXT_CSD[%i]: 0x%02x\n", off, ext_csd[off]);
+ if (argv[4])
+ env_set_hex(argv[4], ext_csd[off]);
+ return CMD_RET_SUCCESS;
+ }
+
+ return CMD_RET_FAILURE;
+}
+#endif
+
static struct cmd_tbl cmd_mmc[] = {
U_BOOT_CMD_MKENT(info, 1, 0, do_mmcinfo, "", ""),
U_BOOT_CMD_MKENT(read, 4, 1, do_mmc_read, "", ""),
@@ -1142,6 +1229,9 @@
U_BOOT_CMD_MKENT(bkops-enable, 2, 0, do_mmc_bkops_enable, "", ""),
U_BOOT_CMD_MKENT(bkops, 4, 0, do_mmc_bkops, "", ""),
#endif
+#if CONFIG_IS_ENABLED(CMD_MMC_REG)
+ U_BOOT_CMD_MKENT(reg, 5, 0, do_mmc_reg, "", ""),
+#endif
};
static int do_mmcops(struct cmd_tbl *cmdtp, int flag, int argc,
@@ -1230,6 +1320,12 @@
"mmc bkops <dev> [auto|manual] [enable|disable]\n"
" - configure background operations handshake on device\n"
#endif
+#if CONFIG_IS_ENABLED(CMD_MMC_REG)
+ "mmc reg read <reg> <offset> [env] - read card register <reg> offset <offset>\n"
+ " (optionally into [env] variable)\n"
+ " - reg: cid/csd/dsr/ocr/rca/extcsd\n"
+ " - offset: for cid/csd [0..3], for extcsd [0..511,all]\n"
+#endif
);
/* Old command kept for compatibility. Same as 'mmc info' */
diff --git a/cmd/mp.c b/cmd/mp.c
index 8d14401..1b4373f 100644
--- a/cmd/mp.c
+++ b/cmd/mp.c
@@ -66,8 +66,7 @@
return 0;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char cpu_help_text[] =
+U_BOOT_LONGHELP(cpu,
"<num> reset - Reset cpu <num>\n"
"cpu status - Status of all cpus\n"
"cpu <num> status - Status of cpu <num>\n"
@@ -86,8 +85,7 @@
" When cpu <num> is released r4 and r5 = 0.\n" \
" r7 will contain the size of the initial mapped area"
#endif
- "";
-#endif
+ );
U_BOOT_CMD(
cpu, CONFIG_SYS_MAXARGS, 1, cpu_cmd,
diff --git a/cmd/mtd.c b/cmd/mtd.c
index eb6e2d6..e63c011 100644
--- a/cmd/mtd.c
+++ b/cmd/mtd.c
@@ -541,8 +541,7 @@
}
#endif /* CONFIG_AUTO_COMPLETE */
-#ifdef CONFIG_SYS_LONGHELP
-static char mtd_help_text[] =
+U_BOOT_LONGHELP(mtd,
"- generic operations on memory technology devices\n\n"
"mtd list\n"
"mtd read[.raw][.oob] <name> <addr> [<off> [<size>]]\n"
@@ -563,8 +562,7 @@
"\t\t* must be a multiple of a block for erase\n"
"\t\t* must be a multiple of a page otherwise (special case: default is a page with dump)\n"
"\n"
- "The .dontskipff option forces writing empty pages, don't use it if unsure.\n";
-#endif
+ "The .dontskipff option forces writing empty pages, don't use it if unsure.\n");
U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils", mtd_help_text,
U_BOOT_SUBCMD_MKENT(list, 1, 1, do_mtd_list),
diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c
index 0984158..b31db73 100644
--- a/cmd/mtdparts.c
+++ b/cmd/mtdparts.c
@@ -2079,8 +2079,7 @@
" - change active partition (e.g. part-id = nand0,1) of a MTD device"
);
-#ifdef CONFIG_SYS_LONGHELP
-static char mtdparts_help_text[] =
+U_BOOT_LONGHELP(mtdparts,
"\n"
" - list partition table\n"
"mtdparts delall\n"
@@ -2122,8 +2121,7 @@
"<size> := standard linux memsize OR '-' to denote all remaining space\n"
"<offset> := partition start offset within the device\n"
"<name> := '(' NAME ')'\n"
- "<ro-flag> := when set to 'ro' makes partition read-only (not used, passed to kernel)";
-#endif
+ "<ro-flag> := when set to 'ro' makes partition read-only (not used, passed to kernel)");
U_BOOT_CMD(
mtdparts, 6, 0, do_mtdparts,
diff --git a/cmd/mux.c b/cmd/mux.c
index 833266f..388fb08 100644
--- a/cmd/mux.c
+++ b/cmd/mux.c
@@ -49,7 +49,7 @@
chip = dev_get_uclass_priv(dev);
if (!chip)
- return ERR_PTR(ret);
+ return ERR_PTR(-EINVAL);
if (id >= chip->controllers)
return ERR_PTR(-EINVAL);
@@ -173,10 +173,10 @@
return CMD_RET_SUCCESS;
}
-static char mux_help_text[] =
+U_BOOT_LONGHELP(mux,
"list - List all Muxes and their states\n"
"select <chip> <id> <state> - Select the given mux state\n"
- "deselect <chip> <id> - Deselect the given mux and reset it to its idle state";
+ "deselect <chip> <id> - Deselect the given mux and reset it to its idle state");
U_BOOT_CMD_WITH_SUBCMDS(mux, "List, select, and deselect muxes", mux_help_text,
U_BOOT_SUBCMD_MKENT(list, 1, 1, do_mux_list),
diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c
index ca24a5c..744b1c2 100644
--- a/cmd/mvebu/bubt.c
+++ b/cmd/mvebu/bubt.c
@@ -240,9 +240,16 @@
#endif
/* SD reserves LBA-0 for MBR and boots from LBA-1,
- * MMC/eMMC boots from LBA-0
+ * MMC/eMMC boots from LBA-0 and LBA-4096
*/
- start_lba = IS_SD(mmc) ? 1 : 0;
+ if (IS_SD(mmc))
+ start_lba = 1;
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+ else if (part)
+ start_lba = 0;
+#endif
+ else
+ start_lba = 4096;
#ifdef CONFIG_BLK
blk_count = image_size / mmc->write_bl_len;
if (image_size % mmc->write_bl_len)
diff --git a/cmd/nand.c b/cmd/nand.c
index b41e54e..71b8f96 100644
--- a/cmd/nand.c
+++ b/cmd/nand.c
@@ -919,8 +919,7 @@
return CMD_RET_USAGE;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char nand_help_text[] =
+U_BOOT_LONGHELP(nand,
"info - show available NAND devices\n"
"nand device [dev] - show or set current device\n"
"nand read - addr off|partition size\n"
@@ -965,8 +964,7 @@
"nand env.oob set off|partition - set enviromnent offset\n"
"nand env.oob get - get environment offset"
#endif
- "";
-#endif
+ );
U_BOOT_CMD(
nand, CONFIG_SYS_MAXARGS, 1, do_nand,
diff --git a/cmd/nvedit.c b/cmd/nvedit.c
index dc7655b..258f5db 100644
--- a/cmd/nvedit.c
+++ b/cmd/nvedit.c
@@ -36,6 +36,7 @@
#include <mapmem.h>
#include <asm/global_data.h>
#include <linux/bitops.h>
+#include <linux/printk.h>
#include <u-boot/crc.h>
#include <linux/stddef.h>
#include <asm/byteorder.h>
@@ -411,11 +412,7 @@
for (i = 0, clbkp = ll_entry_start(struct env_clbk_tbl, env_clbk);
i < num_callbacks;
i++, clbkp++) {
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- if (entry->callback == clbkp->callback + gd->reloc_off)
-#else
if (entry->callback == clbkp->callback)
-#endif
break;
}
@@ -1314,13 +1311,6 @@
#endif
};
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
-void env_reloc(void)
-{
- fixup_cmdtable(cmd_env_sub, ARRAY_SIZE(cmd_env_sub));
-}
-#endif
-
static int do_env(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
struct cmd_tbl *cp;
@@ -1340,8 +1330,7 @@
return CMD_RET_USAGE;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char env_help_text[] =
+U_BOOT_LONGHELP(env,
#if defined(CONFIG_CMD_ASKENV)
"ask name [message] [size] - ask for environment variable\nenv "
#endif
@@ -1409,8 +1398,7 @@
"env set -e [-nv][-bs][-rt][-at][-a][-i addr:size][-v] name [arg ...]\n"
" - set UEFI variable; unset if '-i' or 'arg' not specified\n"
#endif
- "env set [-f] name [arg ...]\n";
-#endif
+ "env set [-f] name [arg ...]\n");
U_BOOT_CMD(
env, CONFIG_SYS_MAXARGS, 1, do_env,
diff --git a/cmd/nvedit_efi.c b/cmd/nvedit_efi.c
index 24944ab..7a30b5c 100644
--- a/cmd/nvedit_efi.c
+++ b/cmd/nvedit_efi.c
@@ -262,7 +262,7 @@
char *tmp_buf = NULL, *new_buf = NULL, *value;
unsigned long len = 0;
- if (!strncmp(data, "=0x", 2)) { /* hexadecimal number */
+ if (!strncmp(data, "=0x", 3)) { /* hexadecimal number */
union {
u8 u8;
u16 u16;
diff --git a/cmd/onenand.c b/cmd/onenand.c
index d633f19..fad7815 100644
--- a/cmd/onenand.c
+++ b/cmd/onenand.c
@@ -12,6 +12,7 @@
#include <common.h>
#include <command.h>
#include <malloc.h>
+#include <linux/printk.h>
#include <linux/compat.h>
#include <linux/mtd/mtd.h>
@@ -560,12 +561,6 @@
U_BOOT_CMD_MKENT(markbad, CONFIG_SYS_MAXARGS, 0, do_onenand_markbad, "", ""),
};
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
-void onenand_reloc(void) {
- fixup_cmdtable(cmd_onenand_sub, ARRAY_SIZE(cmd_onenand_sub));
-}
-#endif
-
static int do_onenand(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
diff --git a/cmd/osd.c b/cmd/osd.c
index c8c62d4..210bc5d 100644
--- a/cmd/osd.c
+++ b/cmd/osd.c
@@ -278,12 +278,12 @@
return CMD_RET_USAGE;
}
-static char osd_help_text[] =
+U_BOOT_LONGHELP(osd,
"show - show OSD info\n"
"osd dev [dev] - show or set current OSD\n"
"write [pos_x] [pos_y] [buffer] [count] - write 8-bit hex encoded buffer to osd memory at a given position\n"
"print [pos_x] [pos_y] [color] [text] - write ASCII buffer (given by text data and driver-specific color information) to osd memory\n"
- "size [size_x] [size_y] - set OSD XY size in characters\n";
+ "size [size_x] [size_y] - set OSD XY size in characters\n");
U_BOOT_CMD(
osd, 6, 1, do_osd,
diff --git a/cmd/pcap.c b/cmd/pcap.c
index ab5c1a7..a014920 100644
--- a/cmd/pcap.c
+++ b/cmd/pcap.c
@@ -48,7 +48,7 @@
return pcap_clear() ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
}
-static char pcap_help_text[] =
+U_BOOT_LONGHELP(pcap,
"- network packet capture\n\n"
"pcap\n"
"pcap init\t\t\t<addr> <max_size>\n"
@@ -60,7 +60,7 @@
"With:\n"
"\t<addr>: user address to which pcap will be stored (hexedcimal)\n"
"\t<max_size>: Maximum size of pcap file (decimal)\n"
- "\n";
+ "\n");
U_BOOT_CMD_WITH_SUBCMDS(pcap, "pcap", pcap_help_text,
U_BOOT_SUBCMD_MKENT(init, 3, 0, do_pcap_init),
diff --git a/cmd/pci.c b/cmd/pci.c
index 78b661d..d89e71c 100644
--- a/cmd/pci.c
+++ b/cmd/pci.c
@@ -620,8 +620,7 @@
/***************************************************/
-#ifdef CONFIG_SYS_LONGHELP
-static char pci_help_text[] =
+U_BOOT_LONGHELP(pci,
"[bus|*] [long]\n"
" - short or long list of PCI devices on bus 'bus'\n"
"pci enum\n"
@@ -639,8 +638,7 @@
"pci modify[.b, .w, .l] b.d.f address\n"
" - modify, auto increment CFG address\n"
"pci write[.b, .w, .l] b.d.f address value\n"
- " - write to CFG address";
-#endif
+ " - write to CFG address");
U_BOOT_CMD(
pci, 5, 1, do_pci,
diff --git a/cmd/pci_mps.c b/cmd/pci_mps.c
index 555a5fd..98161da 100644
--- a/cmd/pci_mps.c
+++ b/cmd/pci_mps.c
@@ -152,13 +152,11 @@
/***************************************************/
-#ifdef CONFIG_SYS_LONGHELP
-static char pci_mps_help_text[] =
+U_BOOT_LONGHELP(pci_mps,
"safe\n"
" - Set PCI Express MPS of all devices to safe values\n"
"pci_mps peer2peer\n"
- " - Set PCI Express MPS of all devices to support hotplug and peer-to-peer DMA\n";
-#endif
+ " - Set PCI Express MPS of all devices to support hotplug and peer-to-peer DMA\n");
U_BOOT_CMD(pci_mps, 2, 0, do_pci_mps,
"configure PCI Express MPS", pci_mps_help_text);
diff --git a/cmd/pstore.c b/cmd/pstore.c
index cd6f6fe..9795eea 100644
--- a/cmd/pstore.c
+++ b/cmd/pstore.c
@@ -486,6 +486,8 @@
{
char node[32];
int nodeoffset; /* node offset from libfdt */
+ u32 addr_cells_root;
+ u32 size_cells_root;
u32 addr_cells;
u32 size_cells;
@@ -495,6 +497,8 @@
log_err("fdt_path_offset() returned %s\n", fdt_strerror(nodeoffset));
return;
}
+ addr_cells_root = fdt_getprop_u32_default_node(blob, nodeoffset, 0, "#address-cells", 2);
+ size_cells_root = fdt_getprop_u32_default_node(blob, nodeoffset, 0, "#size-cells", 2);
nodeoffset = fdt_find_or_add_subnode(blob, nodeoffset, "reserved-memory");
if (nodeoffset < 0) {
@@ -503,8 +507,10 @@
return;
}
- addr_cells = fdt_getprop_u32_default_node(blob, nodeoffset, 0, "#address-cells", 2);
- size_cells = fdt_getprop_u32_default_node(blob, nodeoffset, 0, "#size-cells", 2);
+ addr_cells = fdt_getprop_u32_default_node(blob, nodeoffset, 0,
+ "#address-cells", addr_cells_root);
+ size_cells = fdt_getprop_u32_default_node(blob, nodeoffset, 0,
+ "#size-cells", size_cells_root);
fdt_setprop_u32(blob, nodeoffset, "#address-cells", addr_cells);
fdt_setprop_u32(blob, nodeoffset, "#size-cells", size_cells);
diff --git a/cmd/pxe.c b/cmd/pxe.c
index 6771425..21134eb 100644
--- a/cmd/pxe.c
+++ b/cmd/pxe.c
@@ -141,6 +141,14 @@
env_get("bootfile"), use_ipv6))
return -ENOMEM;
+ if (IS_ENABLED(CONFIG_BOOTP_PXE_DHCP_OPTION) &&
+ pxelinux_configfile && !use_ipv6) {
+ if (pxe_dhcp_option_path(&ctx, pxefile_addr_r) > 0)
+ goto done;
+
+ goto error_exit;
+ }
+
if (IS_ENABLED(CONFIG_DHCP6_PXE_DHCP_OPTION) &&
pxelinux_configfile && use_ipv6) {
if (pxe_dhcp_option_path(&ctx, pxefile_addr_r) > 0)
@@ -299,24 +307,10 @@
U_BOOT_CMD_MKENT(boot, 3, 1, do_pxe_boot, "", "")
};
-static void __maybe_unused pxe_reloc(void)
-{
- static int relocated_pxe;
-
- if (!relocated_pxe) {
- fixup_cmdtable(cmd_pxe_sub, ARRAY_SIZE(cmd_pxe_sub));
- relocated_pxe = 1;
- }
-}
-
static int do_pxe(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
struct cmd_tbl *cp;
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- pxe_reloc();
-#endif
-
if (argc < 2)
return CMD_RET_USAGE;
@@ -333,8 +327,7 @@
}
U_BOOT_CMD(pxe, 4, 1, do_pxe,
- "commands to get and boot from pxe files\n"
- "To use IPv6 add -ipv6 parameter",
+ "get and boot from pxe files",
"get [" USE_IP6_CMD_PARAM "] - try to retrieve a pxe file using tftp\n"
"pxe boot [pxefile_addr_r] [-ipv6] - boot from the pxe file at pxefile_addr_r\n"
);
diff --git a/cmd/regulator.c b/cmd/regulator.c
index 8988c90..635a9ad 100644
--- a/cmd/regulator.c
+++ b/cmd/regulator.c
@@ -8,6 +8,7 @@
#include <errno.h>
#include <dm.h>
#include <dm/uclass-internal.h>
+#include <linux/printk.h>
#include <power/regulator.h>
#define LIMIT_DEVNAME 20
diff --git a/cmd/remoteproc.c b/cmd/remoteproc.c
index ca3b436..ea8724a 100644
--- a/cmd/remoteproc.c
+++ b/cmd/remoteproc.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2015
- * Texas Instruments Incorporated - http://www.ti.com/
+ * Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
#include <command.h>
diff --git a/cmd/riscv/exception.c b/cmd/riscv/exception.c
index 7a08061..f38f454 100644
--- a/cmd/riscv/exception.c
+++ b/cmd/riscv/exception.c
@@ -8,6 +8,15 @@
#include <common.h>
#include <command.h>
+static int do_compressed(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ /* c.li a0, 0; c.li a0, 0 */
+ asm volatile (".long 0x45014501\n");
+ printf("The system supports compressed instructions.\n");
+ return CMD_RET_SUCCESS;
+}
+
static int do_ebreak(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -15,6 +24,19 @@
return CMD_RET_FAILURE;
}
+static int do_ialign16(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ asm volatile (
+ /* jump skipping 2 bytes */
+ ".long 0x0060006f\n"
+ ".long 0x006f0000\n"
+ ".long 0x00000060\n"
+ );
+ printf("The system supports 16 bit aligned instructions.\n");
+ return CMD_RET_SUCCESS;
+}
+
static int do_unaligned(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -35,8 +57,12 @@
}
static struct cmd_tbl cmd_sub[] = {
+ U_BOOT_CMD_MKENT(compressed, CONFIG_SYS_MAXARGS, 1, do_compressed,
+ "", ""),
U_BOOT_CMD_MKENT(ebreak, CONFIG_SYS_MAXARGS, 1, do_ebreak,
"", ""),
+ U_BOOT_CMD_MKENT(ialign16, CONFIG_SYS_MAXARGS, 1, do_ialign16,
+ "", ""),
U_BOOT_CMD_MKENT(unaligned, CONFIG_SYS_MAXARGS, 1, do_unaligned,
"", ""),
U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined,
@@ -46,9 +72,11 @@
static char exception_help_text[] =
"<ex>\n"
" The following exceptions are available:\n"
- " ebreak - breakpoint\n"
- " undefined - illegal instruction\n"
- " unaligned - load address misaligned\n"
+ " compressed - compressed instruction\n"
+ " ebreak - breakpoint\n"
+ " ialign16 - 16 bit aligned instruction\n"
+ " undefined - illegal instruction\n"
+ " unaligned - load address misaligned\n"
;
#include <exception.h>
diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c
index 32761c5..940d9bc 100644
--- a/cmd/riscv/sbi.c
+++ b/cmd/riscv/sbi.c
@@ -119,11 +119,8 @@
return 0;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char sbi_help_text[] =
- "- display SBI spec version, implementation, and available extensions";
-
-#endif
+U_BOOT_LONGHELP(sbi,
+ "- display SBI spec version, implementation, and available extensions");
U_BOOT_CMD_COMPLETE(
sbi, 1, 0, do_sbi,
diff --git a/cmd/rkmtd.c b/cmd/rkmtd.c
new file mode 100644
index 0000000..5b80427
--- /dev/null
+++ b/cmd/rkmtd.c
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * Driver interface derived from:
+ * /cmd/host.c
+ * Copyright (c) 2012, Google Inc.
+ *
+ * Copyright (C) 2023 Johan Jonker <jbx6244@gmail.com>
+ */
+
+#include <common.h>
+#include <blk.h>
+#include <command.h>
+#include <dm.h>
+#include <rkmtd.h>
+#include <stdio.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
+
+static int do_rkmtd_bind(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct udevice *dev;
+ const char *label;
+ int ret;
+
+ argc--;
+ argv++;
+
+ if (argc < 1)
+ return CMD_RET_USAGE;
+
+ if (argc > 1)
+ return CMD_RET_USAGE;
+
+ label = argv[0];
+ ret = rkmtd_create_attach_mtd(label, &dev);
+ if (ret) {
+ printf("Cannot create device / bind mtd\n");
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
+static struct udevice *parse_rkmtd_label(const char *label)
+{
+ struct udevice *dev;
+
+ dev = rkmtd_find_by_label(label);
+ if (!dev) {
+ int devnum;
+ char *ep;
+
+ devnum = hextoul(label, &ep);
+ if (*ep ||
+ uclass_find_device_by_seq(UCLASS_RKMTD, devnum, &dev)) {
+ printf("No such device '%s'\n", label);
+ return NULL;
+ }
+ }
+
+ return dev;
+}
+
+static int do_rkmtd_unbind(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct udevice *dev;
+ const char *label;
+ int ret;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ label = argv[1];
+ dev = parse_rkmtd_label(label);
+ if (!dev)
+ return CMD_RET_FAILURE;
+
+ ret = rkmtd_detach(dev);
+ if (ret) {
+ printf("Cannot detach mtd\n");
+ return CMD_RET_FAILURE;
+ }
+
+ ret = device_unbind(dev);
+ if (ret) {
+ printf("Cannot unbind device '%s'\n", dev->name);
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
+static void show_rkmtd_dev(struct udevice *dev)
+{
+ struct rkmtd_dev *plat = dev_get_plat(dev);
+ struct blk_desc *desc;
+ struct udevice *blk;
+ int ret;
+
+ printf("%3d ", dev_seq(dev));
+
+ ret = blk_get_from_parent(dev, &blk);
+ if (ret)
+ return;
+
+ desc = dev_get_uclass_plat(blk);
+ printf("%12lu %-15s\n", (unsigned long)desc->lba, plat->label);
+}
+
+static int do_rkmtd_info(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct udevice *dev;
+
+ if (argc < 1)
+ return CMD_RET_USAGE;
+
+ dev = NULL;
+ if (argc >= 2) {
+ dev = parse_rkmtd_label(argv[1]);
+ if (!dev)
+ return CMD_RET_FAILURE;
+ }
+
+ printf("%3s %12s %-15s\n", "dev", "blocks", "label");
+ if (dev) {
+ show_rkmtd_dev(dev);
+ } else {
+ struct uclass *uc;
+
+ uclass_id_foreach_dev(UCLASS_RKMTD, dev, uc)
+ show_rkmtd_dev(dev);
+ }
+
+ return 0;
+}
+
+static int do_rkmtd_dev(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct udevice *dev;
+ const char *label;
+
+ if (argc < 1 || argc > 3)
+ return CMD_RET_USAGE;
+
+ if (argc == 1) {
+ struct rkmtd_dev *plat;
+
+ dev = rkmtd_get_cur_dev();
+ if (!dev) {
+ printf("No current rkmtd device\n");
+ return CMD_RET_FAILURE;
+ }
+ plat = dev_get_plat(dev);
+ printf("Current rkmtd device: %d: %s\n", dev_seq(dev),
+ plat->label);
+ return 0;
+ }
+
+ label = argv[1];
+ dev = parse_rkmtd_label(argv[1]);
+ if (!dev)
+ return CMD_RET_FAILURE;
+
+ rkmtd_set_cur_dev(dev);
+
+ return 0;
+}
+
+static struct cmd_tbl cmd_rkmtd_sub[] = {
+ U_BOOT_CMD_MKENT(bind, 4, 0, do_rkmtd_bind, "", ""),
+ U_BOOT_CMD_MKENT(unbind, 4, 0, do_rkmtd_unbind, "", ""),
+ U_BOOT_CMD_MKENT(info, 3, 0, do_rkmtd_info, "", ""),
+ U_BOOT_CMD_MKENT(dev, 0, 1, do_rkmtd_dev, "", ""),
+};
+
+static int do_rkmtd(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct cmd_tbl *c;
+
+ argc--;
+ argv++;
+
+ c = find_cmd_tbl(argv[0], cmd_rkmtd_sub, ARRAY_SIZE(cmd_rkmtd_sub));
+
+ if (c)
+ return c->cmd(cmdtp, flag, argc, argv);
+ else
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+ rkmtd, 8, 1, do_rkmtd,
+ "Rockchip MTD sub-system",
+ "bind <label> - bind RKMTD device\n"
+ "rkmtd unbind <label> - unbind RKMTD device\n"
+ "rkmtd info [<label>] - show all available RKMTD devices\n"
+ "rkmtd dev [<label>] - show or set current RKMTD device\n"
+);
diff --git a/cmd/rng.c b/cmd/rng.c
index 81a2396..52f722c 100644
--- a/cmd/rng.c
+++ b/cmd/rng.c
@@ -56,11 +56,9 @@
return ret;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char rng_help_text[] =
+U_BOOT_LONGHELP(rng,
"[dev [n]]\n"
- " - print n random bytes(max 64) read from dev\n";
-#endif
+ " - print n random bytes(max 64) read from dev\n");
U_BOOT_CMD(
rng, 3, 0, do_rng,
diff --git a/cmd/rockusb.c b/cmd/rockusb.c
index f181ec6..0708856 100644
--- a/cmd/rockusb.c
+++ b/cmd/rockusb.c
@@ -15,6 +15,7 @@
{
int controller_index, dev_index;
char *usb_controller;
+ struct udevice *udc;
char *devtype;
char *devnum;
int ret;
@@ -34,7 +35,7 @@
dev_index = simple_strtoul(devnum, NULL, 0);
rockusb_dev_init(devtype, dev_index);
- ret = usb_gadget_initialize(controller_index);
+ ret = udc_device_get_by_index(controller_index, &udc);
if (ret) {
printf("USB init failed: %d\n", ret);
return CMD_RET_FAILURE;
@@ -56,14 +57,14 @@
break;
if (ctrlc())
break;
- usb_gadget_handle_interrupts(controller_index);
+ dm_usb_gadget_handle_interrupts(udc);
}
ret = CMD_RET_SUCCESS;
exit:
g_dnl_unregister();
g_dnl_clear_detach();
- usb_gadget_release(controller_index);
+ udc_device_put(udc);
return ret;
}
diff --git a/cmd/sandbox/exception.c b/cmd/sandbox/exception.c
index 1aa1d67..c082401 100644
--- a/cmd/sandbox/exception.c
+++ b/cmd/sandbox/exception.c
@@ -31,11 +31,10 @@
"", ""),
};
-static char exception_help_text[] =
+U_BOOT_LONGHELP(exception,
"<ex>\n"
" The following exceptions are available:\n"
" undefined - undefined instruction\n"
- " sigsegv - illegal memory access\n"
- ;
+ " sigsegv - illegal memory access\n");
#include <exception.h>
diff --git a/cmd/scp03.c b/cmd/scp03.c
index 216c942..2b8d5ae 100644
--- a/cmd/scp03.c
+++ b/cmd/scp03.c
@@ -41,11 +41,12 @@
return CMD_RET_SUCCESS;
}
-static char text[] =
+U_BOOT_LONGHELP(scp03,
"provides a command to enable SCP03 and provision the SCP03 keys\n"
" enable - enable SCP03 on the TEE\n"
- " provision - provision SCP03 on the TEE\n";
+ " provision - provision SCP03 on the TEE\n");
-U_BOOT_CMD_WITH_SUBCMDS(scp03, "Secure Channel Protocol 03 control", text,
+U_BOOT_CMD_WITH_SUBCMDS(scp03, "Secure Channel Protocol 03 control",
+ scp03_help_text,
U_BOOT_SUBCMD_MKENT(enable, 1, 1, do_scp03_enable),
U_BOOT_SUBCMD_MKENT(provision, 1, 1, do_scp03_provision));
diff --git a/cmd/setexpr.c b/cmd/setexpr.c
index 4d671e7..233471f 100644
--- a/cmd/setexpr.c
+++ b/cmd/setexpr.c
@@ -215,7 +215,7 @@
if (res == 0) {
if (loop == 0) {
- printf("%s: No match\n", data);
+ debug("%s: No match\n", data);
return 1;
} else {
break;
@@ -359,7 +359,7 @@
if (ret)
return 1;
- printf("%s=%s\n", name, data);
+ debug("%s=%s\n", name, data);
return env_set(name, data);
}
diff --git a/cmd/sf.c b/cmd/sf.c
index 55bef2f..730996c 100644
--- a/cmd/sf.c
+++ b/cmd/sf.c
@@ -366,7 +366,7 @@
}
if (flash->flash_is_unlocked &&
- !flash->flash_is_unlocked(flash, offset, len)) {
+ !flash->flash_is_unlocked(flash, offset, size)) {
printf("ERROR: flash area is locked\n");
return CMD_RET_FAILURE;
}
@@ -604,7 +604,7 @@
ret = do_spi_flash_read_write(argc, argv);
else if (strcmp(cmd, "erase") == 0)
ret = do_spi_flash_erase(argc, argv);
- else if (strcmp(cmd, "protect") == 0)
+ else if (IS_ENABLED(CONFIG_SPI_FLASH_LOCK) && strcmp(cmd, "protect") == 0)
ret = do_spi_protect(argc, argv);
else if (IS_ENABLED(CONFIG_CMD_SF_TEST) && !strcmp(cmd, "test"))
ret = do_spi_flash_test(argc, argv);
@@ -614,8 +614,7 @@
return ret;
}
-#ifdef CONFIG_SYS_LONGHELP
-static const char long_help[] =
+U_BOOT_LONGHELP(sf,
"probe [[bus:]cs] [hz] [mode] - init flash device on given SPI bus\n"
" and chip select\n"
"sf read addr offset|partition len - read `len' bytes starting at\n"
@@ -630,15 +629,16 @@
"sf update addr offset|partition len - erase and write `len' bytes from memory\n"
" at `addr' to flash at `offset'\n"
" or to start of mtd `partition'\n"
+#ifdef CONFIG_SPI_FLASH_LOCK
"sf protect lock/unlock sector len - protect/unprotect 'len' bytes starting\n"
" at address 'sector'"
+#endif
#ifdef CONFIG_CMD_SF_TEST
"\nsf test offset len - run a very basic destructive test"
#endif
-#endif /* CONFIG_SYS_LONGHELP */
- ;
+ );
U_BOOT_CMD(
sf, 5, 1, do_spi_flash,
- "SPI flash sub-system", long_help
+ "SPI flash sub-system", sf_help_text
);
diff --git a/cmd/source.c b/cmd/source.c
index 92c7835..0ba9736 100644
--- a/cmd/source.c
+++ b/cmd/source.c
@@ -54,19 +54,18 @@
return rcode;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char source_help_text[] =
+U_BOOT_LONGHELP(source,
#if defined(CONFIG_FIT)
"[<addr>][:[<image>]|#[<config>]]\n"
"\t- Run script starting at addr\n"
"\t- A FIT config name or subimage name may be specified with : or #\n"
"\t (like bootm). If the image or config name is omitted, the\n"
- "\t default is used.";
+ "\t default is used."
#else
"[<addr>]\n"
- "\t- Run script starting at addr";
+ "\t- Run script starting at addr"
#endif
-#endif
+ );
U_BOOT_CMD(
source, 2, 0, do_source,
diff --git a/cmd/thordown.c b/cmd/thordown.c
index 838764c..48e22b3 100644
--- a/cmd/thordown.c
+++ b/cmd/thordown.c
@@ -12,26 +12,29 @@
#include <dfu.h>
#include <g_dnl.h>
#include <usb.h>
+#include <linux/printk.h>
int do_thor_down(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
+ char *interface, *devstring;
+ int controller_index;
+ struct udevice *udc;
+ int ret;
+
if (argc < 4)
return CMD_RET_USAGE;
- char *usb_controller = argv[1];
- char *interface = argv[2];
- char *devstring = argv[3];
-
- int ret;
-
puts("TIZEN \"THOR\" Downloader\n");
+ interface = argv[2];
+ devstring = argv[3];
+
ret = dfu_init_env_entities(interface, devstring);
if (ret)
goto done;
- int controller_index = simple_strtoul(usb_controller, NULL, 0);
- ret = usb_gadget_initialize(controller_index);
+ controller_index = simple_strtoul(argv[1], NULL, 0);
+ ret = udc_device_get_by_index(controller_index, &udc);
if (ret) {
pr_err("USB init failed: %d\n", ret);
ret = CMD_RET_FAILURE;
@@ -45,7 +48,7 @@
goto exit;
}
- ret = thor_init();
+ ret = thor_init(udc);
if (ret) {
pr_err("THOR DOWNLOAD failed: %d\n", ret);
ret = CMD_RET_FAILURE;
@@ -53,7 +56,7 @@
}
do {
- ret = thor_handle();
+ ret = thor_handle(udc);
if (ret == THOR_DFU_REINIT_NEEDED) {
dfu_free_entities();
ret = dfu_init_env_entities(interface, devstring);
@@ -66,7 +69,7 @@
} while (ret == 0);
exit:
g_dnl_unregister();
- usb_gadget_release(controller_index);
+ udc_device_put(udc);
done:
dfu_free_entities();
diff --git a/cmd/ti/Kconfig b/cmd/ti/Kconfig
index db55744..9442c99 100644
--- a/cmd/ti/Kconfig
+++ b/cmd/ti/Kconfig
@@ -2,6 +2,7 @@
config CMD_DDR3
bool "command for verifying DDR features"
+ depends on ARCH_KEYSTONE || DRA7XX
help
Support for testing ddr3 on TI platforms. This command
supports memory verification, memory comapre and ecc
diff --git a/cmd/ti/Makefile b/cmd/ti/Makefile
index 0455933..5f9c64f 100644
--- a/cmd/ti/Makefile
+++ b/cmd/ti/Makefile
@@ -1,9 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
-# Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
-obj- += dummy.o
-
-ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_CMD_DDR3) += ddr3.o
obj-$(CONFIG_CMD_PD) += pd.o
-endif
diff --git a/cmd/ti/pd.c b/cmd/ti/pd.c
index a9a182f..a0492a5 100644
--- a/cmd/ti/pd.c
+++ b/cmd/ti/pd.c
@@ -175,11 +175,11 @@
return CMD_RET_USAGE;
}
-U_BOOT_CMD(pd, 4, 1, ti_do_pd,
- "TI power domain control",
-#if IS_ENABLED(CONFIG_SYS_LONGHELP)
+U_BOOT_LONGHELP(pd,
"dump - show power domain status\n"
"enable [psc] [lpsc] - enable power domain\n"
- "disable [psc] [lpsc] - disable power domain\n"
-#endif
+ "disable [psc] [lpsc] - disable power domain\n");
+
+U_BOOT_CMD(pd, 4, 1, ti_do_pd,
+ "TI power domain control", pd_help_text
);
diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
index 7979639..57cfd35 100644
--- a/cmd/tlv_eeprom.c
+++ b/cmd/tlv_eeprom.c
@@ -1088,19 +1088,7 @@
return 0;
}
-/**
- * populate_serial_number - read the serial number from EEPROM
- *
- * This function reads the serial number from the EEPROM and sets the
- * appropriate environment variable.
- *
- * The environment variable is only set if it has not been set
- * already. This ensures that any user-saved variables are never
- * overwritten.
- *
- * This function must be called after relocation.
- */
-int populate_serial_number(int devnum)
+int serial_read_from_eeprom(int devnum)
{
char serialstr[257];
int eeprom_index;
diff --git a/cmd/tpm_test.c b/cmd/tpm_test.c
index c4ed8e5..c7fa6e7 100644
--- a/cmd/tpm_test.c
+++ b/cmd/tpm_test.c
@@ -8,6 +8,7 @@
#include <cpu_func.h>
#include <log.h>
#include <tpm-v1.h>
+#include <linux/printk.h>
#include "tpm-user-utils.h"
#include <tpm_api.h>
@@ -294,8 +295,8 @@
*/
index_0 += 1;
if (tpm_nv_write_value(dev, INDEX0, (uint8_t *)&index_0,
- sizeof(index_0) !=
- TPM_SUCCESS)) {
+ sizeof(index_0)) !=
+ TPM_SUCCESS) {
pr_err("\tcould not write index 0\n");
}
tpm_nv_write_value_lock(dev, INDEX0);
diff --git a/cmd/ufs.c b/cmd/ufs.c
index 143e946..282b414 100644
--- a/cmd/ufs.c
+++ b/cmd/ufs.c
@@ -2,7 +2,7 @@
/**
* ufs.c - UFS specific U-Boot commands
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*
*/
#include <common.h>
diff --git a/cmd/usb_gadget_sdp.c b/cmd/usb_gadget_sdp.c
index 1af82e1..cbdda73 100644
--- a/cmd/usb_gadget_sdp.c
+++ b/cmd/usb_gadget_sdp.c
@@ -11,17 +11,21 @@
#include <g_dnl.h>
#include <sdp.h>
#include <usb.h>
+#include <linux/printk.h>
static int do_sdp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
+ int controller_index;
+ struct udevice *udc;
int ret;
if (argc < 2)
return CMD_RET_USAGE;
- char *usb_controller = argv[1];
- int controller_index = simple_strtoul(usb_controller, NULL, 0);
- usb_gadget_initialize(controller_index);
+ controller_index = simple_strtoul(argv[1], NULL, 0);
+ ret = udc_device_get_by_index(controller_index, &udc);
+ if (ret)
+ return ret;
g_dnl_clear_detach();
ret = g_dnl_register("usb_dnl_sdp");
@@ -30,20 +34,20 @@
goto exit_register;
}
- ret = sdp_init(controller_index);
+ ret = sdp_init(udc);
if (ret) {
pr_err("SDP init failed: %d\n", ret);
goto exit;
}
/* This command typically does not return but jumps to an image */
- sdp_handle(controller_index);
+ sdp_handle(udc);
pr_err("SDP ended\n");
exit:
g_dnl_unregister();
exit_register:
- usb_gadget_release(controller_index);
+ udc_device_put(udc);
return CMD_RET_FAILURE;
}
diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
index c3cc197..a8ddeb4 100644
--- a/cmd/usb_mass_storage.c
+++ b/cmd/usb_mass_storage.c
@@ -18,6 +18,7 @@
#include <usb_mass_storage.h>
#include <watchdog.h>
#include <linux/delay.h>
+#include <linux/printk.h>
static int ums_read_sector(struct ums *ums_dev,
ulong start, lbaint_t blkcnt, void *buf)
@@ -143,6 +144,7 @@
const char *devtype;
const char *devnum;
unsigned int controller_index;
+ struct udevice *udc;
int rc;
int cable_ready_timeout __maybe_unused;
@@ -164,13 +166,14 @@
controller_index = (unsigned int)(simple_strtoul(
usb_controller, NULL, 0));
- if (usb_gadget_initialize(controller_index)) {
+ rc = udc_device_get_by_index(controller_index, &udc);
+ if (rc) {
pr_err("Couldn't init USB controller.\n");
rc = CMD_RET_FAILURE;
goto cleanup_ums_init;
}
- rc = fsg_init(ums, ums_count, controller_index);
+ rc = fsg_init(ums, ums_count, udc);
if (rc) {
pr_err("fsg_init failed\n");
rc = CMD_RET_FAILURE;
@@ -215,7 +218,7 @@
}
while (1) {
- usb_gadget_handle_interrupts(controller_index);
+ dm_usb_gadget_handle_interrupts(udc);
rc = fsg_main_thread(NULL);
if (rc) {
@@ -247,7 +250,7 @@
cleanup_register:
g_dnl_unregister();
cleanup_board:
- usb_gadget_release(controller_index);
+ udc_device_put(udc);
cleanup_ums_init:
ums_fini();
diff --git a/cmd/vbe.c b/cmd/vbe.c
index 6006903..0e84b0e 100644
--- a/cmd/vbe.c
+++ b/cmd/vbe.c
@@ -104,13 +104,11 @@
return 0;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char vbe_help_text[] =
+U_BOOT_LONGHELP(vbe,
"list - list VBE bootmeths\n"
"vbe select - select a VBE bootmeth by sequence or name\n"
"vbe info - show information about a VBE bootmeth\n"
- "vbe state - show VBE state";
-#endif
+ "vbe state - show VBE state");
U_BOOT_CMD_WITH_SUBCMDS(vbe, "Verified Boot for Embedded", vbe_help_text,
U_BOOT_SUBCMD_MKENT(list, 1, 1, do_vbe_list),
diff --git a/cmd/wdt.c b/cmd/wdt.c
index 2741098..b9fdf7a 100644
--- a/cmd/wdt.c
+++ b/cmd/wdt.c
@@ -157,13 +157,13 @@
return CMD_RET_SUCCESS;
}
-static char wdt_help_text[] =
+U_BOOT_LONGHELP(wdt,
"list - list watchdog devices\n"
"wdt dev [<name>] - get/set current watchdog device\n"
"wdt start <timeout ms> [flags] - start watchdog timer\n"
"wdt stop - stop watchdog timer\n"
"wdt reset - reset watchdog timer\n"
- "wdt expire [flags] - expire watchdog timer immediately\n";
+ "wdt expire [flags] - expire watchdog timer immediately\n");
U_BOOT_CMD_WITH_SUBCMDS(wdt, "Watchdog sub-system", wdt_help_text,
U_BOOT_SUBCMD_MKENT(list, 1, 1, do_wdt_list),
diff --git a/cmd/ximg.c b/cmd/ximg.c
index 60ed2c9..a50dd20 100644
--- a/cmd/ximg.c
+++ b/cmd/ximg.c
@@ -258,8 +258,7 @@
return 0;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char imgextract_help_text[] =
+U_BOOT_LONGHELP(imgextract,
"addr part [dest]\n"
" - extract <part> from legacy image at <addr> and copy to <dest>"
#if defined(CONFIG_FIT)
@@ -267,8 +266,7 @@
"addr uname [dest]\n"
" - extract <uname> subimage from FIT image at <addr> and copy to <dest>"
#endif
- "";
-#endif
+ );
U_BOOT_CMD(
imxtract, 4, 1, do_imgextract,
diff --git a/cmd/xxd.c b/cmd/xxd.c
index 742a85c..446ac19 100644
--- a/cmd/xxd.c
+++ b/cmd/xxd.c
@@ -73,11 +73,9 @@
return 0;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char xxd_help_text[] =
+U_BOOT_LONGHELP(xxd,
"<interface> <dev[:part]> <file>\n"
- " - Print file from 'dev' on 'interface' as hexdump to standard output\n";
-#endif
+ " - Print file from 'dev' on 'interface' as hexdump to standard output\n");
U_BOOT_CMD(xxd, 4, 1, do_xxd,
"Print file as hexdump to standard output",
diff --git a/common/Kconfig b/common/Kconfig
index 60891e1..b926d96 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -28,26 +28,26 @@
depends on CONSOLE_RECORD
default 0x400 if CONSOLE_RECORD
help
- Set the size of the console output buffer. When this fills up, no
- more data will be recorded until some is removed. The buffer is
- allocated immediately after the malloc() region is ready.
+ Set the size of the console recording output buffer. When this fills
+ up, no more data will be recorded until some is removed. The buffer
+ is allocated immediately after the malloc() region is ready.
config CONSOLE_RECORD_OUT_SIZE_F
hex "Output buffer size before relocation"
depends on CONSOLE_RECORD
default 0x400 if CONSOLE_RECORD
help
- Set the size of the console output buffer before relocation. When
- this fills up, no more data will be recorded until some is removed.
- The buffer is allocated immediately after the early malloc() region is
- ready.
+ Set the size of the console recording output buffer before
+ relocation. When this fills up, no more data will be recorded until
+ some is removed. The buffer is allocated immediately after the early
+ malloc() region is ready.
config CONSOLE_RECORD_IN_SIZE
hex "Input buffer size"
depends on CONSOLE_RECORD
default 0x100 if CONSOLE_RECORD
help
- Set the size of the console input buffer. When this contains data,
+ Set the size of the console recording input buffer. When this contains data,
tstc() and getc() will use this in preference to real device input.
The buffer is allocated immediately after the malloc() region is
ready.
@@ -224,6 +224,16 @@
help
This enables compilation of flush() function for console flush support.
+config CONSOLE_FLUSH_ON_NEWLINE
+ bool "Flush console buffer on every newline character"
+ depends on DM_SERIAL
+ help
+ This makes the serial core code flush the console device
+ whenever a newline (\n) character has been emitted. This can
+ be especially useful when "printf debugging", as otherwise
+ lots of output could still be in the UART's FIFO by the time
+ one hits the code which causes the CPU to hang or reset.
+
config CONSOLE_MUX
bool "Enable console multiplexing"
default y if VIDEO || LCD
@@ -689,7 +699,7 @@
bool
help
Enable this to support adding an event spy at runtime, without adding
- it to the EVENT_SPY() linker list. This increases code size slightly
+ it to the EVENT_SPY*() linker list. This increases code size slightly
but provides more flexibility for boards and subsystems that need it.
config EVENT_DEBUG
@@ -717,7 +727,7 @@
depends on SPL_EVENT && EVENT_DYNAMIC
help
Enable this to support adding an event spy at runtime, without adding
- it to the EVENT_SPY() linker list. This increases code size slightly
+ it to the EVENT_SPY*() linker list. This increases code size slightly
but provides more flexibility for boards and subsystems that need it.
endif # EVENT
@@ -789,6 +799,7 @@
config LAST_STAGE_INIT
bool "Call board-specific as last setup step"
+ select EVENT
help
Some boards need to perform initialisation immediately before control
is passed to the command-line interpreter (e.g. for initializations
@@ -1102,7 +1113,7 @@
config BLOBLIST_ADDR
hex "Address of bloblist"
- default 0xc000 if SANDBOX
+ default 0xb000 if SANDBOX
depends on BLOBLIST_FIXED
help
Sets the address of the bloblist, set up by the first part of U-Boot
@@ -1122,7 +1133,7 @@
config BLOBLIST_SIZE_RELOC
hex "Size of bloblist after relocation"
default BLOBLIST_SIZE if BLOBLIST_FIXED || BLOBLIST_ALLOC
- default 0 if BLOBLIST_PASSAGE
+ default 0x0 if BLOBLIST_PASSAGE
help
Sets the size of the bloblist in bytes after relocation. Since U-Boot
has a lot more memory available then, it is possible to use a larger
@@ -1247,25 +1258,5 @@
endif
-config FDT_SIMPLEFB
- bool "FDT tools for simplefb support"
- depends on OF_LIBFDT
- help
- Enable the fdt tools to manage the simple fb nodes in device tree.
- These functions can be used by board to indicate to the OS
- the presence of the simple frame buffer with associated reserved
- memory
-
config IO_TRACE
bool
-
-config BMP
- bool "Enable bmp image display"
- help
- Enable bmp functions to display bmp image and get bmp info.
-
-config SPL_BMP
- bool "Enable bmp image display at SPL"
- depends on SPL_VIDEO
- help
- Enable bmp functions to display bmp image and get bmp info at SPL.
diff --git a/common/Makefile b/common/Makefile
index 75dd960..4998bc1 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -17,8 +17,6 @@
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-$(CONFIG_DISPLAY_BOARDINFO_LATE) += board_info.o
-obj-$(CONFIG_FDT_SIMPLEFB) += fdt_simplefb.o
-obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o
obj-$(CONFIG_MII) += miiphyutil.o
obj-$(CONFIG_CMD_MII) += miiphyutil.o
obj-$(CONFIG_PHYLIB) += miiphyutil.o
@@ -45,14 +43,12 @@
obj-$(CONFIG_$(SPL_TPL_)BOOTSTAGE) += bootstage.o
obj-$(CONFIG_$(SPL_TPL_)BLOBLIST) += bloblist.o
-obj-$(CONFIG_$(SPL_)BMP) += bmp.o
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_DFU
obj-$(CONFIG_DFU_OVER_USB) += dfu.o
endif
obj-$(CONFIG_SPL_NET) += miiphyutil.o
-obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o
obj-$(CONFIG_SPL_USB_HOST) += usb.o usb_hub.o
obj-$(CONFIG_SPL_USB_STORAGE) += usb_storage.o
@@ -78,11 +74,7 @@
obj-$(CONFIG_CROS_EC) += cros_ec.o
obj-y += dlmalloc.o
-ifdef CONFIG_SYS_MALLOC_F
-ifneq ($(CONFIG_$(SPL_TPL_)SYS_MALLOC_F_LEN),0x0)
-obj-y += malloc_simple.o
-endif
-endif
+obj-$(CONFIG_$(SPL_TPL_)SYS_MALLOC_F) += malloc_simple.o
obj-$(CONFIG_CYCLIC) += cyclic.o
obj-$(CONFIG_$(SPL_TPL_)EVENT) += event.o
diff --git a/common/bloblist.c b/common/bloblist.c
index 2144b10..a22f6c1 100644
--- a/common/bloblist.c
+++ b/common/bloblist.c
@@ -51,6 +51,7 @@
/* BLOBLISTT_PROJECT_AREA */
{ BLOBLISTT_U_BOOT_SPL_HANDOFF, "SPL hand-off" },
+ { BLOBLISTT_VBE, "VBE" },
{ BLOBLISTT_U_BOOT_VIDEO, "SPL video handoff" },
/* BLOBLISTT_VENDOR_AREA */
@@ -476,6 +477,17 @@
log_debug("Found existing bloblist size %lx at %lx\n", size,
addr);
}
+ if (ret)
+ return log_msg_ret("ini", ret);
+ gd->flags |= GD_FLG_BLOBLIST_READY;
- return ret;
+ return 0;
+}
+
+int bloblist_maybe_init(void)
+{
+ if (CONFIG_IS_ENABLED(BLOBLIST) && !(gd->flags & GD_FLG_BLOBLIST_READY))
+ return bloblist_init();
+
+ return 0;
}
diff --git a/common/board_f.c b/common/board_f.c
index e9f4edb..d4d7d01 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -124,8 +124,8 @@
#if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
ulong bss_start, bss_end, text_base;
- bss_start = (ulong)&__bss_start;
- bss_end = (ulong)&__bss_end;
+ bss_start = (ulong)__bss_start;
+ bss_end = (ulong)__bss_end;
#ifdef CONFIG_TEXT_BASE
text_base = CONFIG_TEXT_BASE;
@@ -148,11 +148,12 @@
bool status_printed = false;
int ret;
- /* Not all boards have sysreset drivers available during early
+ /*
+ * Not all boards have sysreset drivers available during early
* boot, so don't fail if one can't be found.
*/
for (ret = uclass_first_device_check(UCLASS_SYSRESET, &dev); dev;
- ret = uclass_next_device_check(&dev)) {
+ ret = uclass_next_device_check(&dev)) {
if (ret) {
debug("%s: %s sysreset device (error: %d)\n",
__func__, dev->name, ret);
@@ -279,31 +280,24 @@
}
#endif
-#if defined(CONFIG_VID)
-__weak int init_func_vid(void)
-{
- return 0;
-}
-#endif
-
static int setup_mon_len(void)
{
#if defined(__ARM__) || defined(__MICROBLAZE__)
- gd->mon_len = (ulong)&__bss_end - (ulong)_start;
+ gd->mon_len = (ulong)__bss_end - (ulong)_start;
#elif defined(CONFIG_SANDBOX) && !defined(__riscv)
- gd->mon_len = (ulong)&_end - (ulong)_init;
+ gd->mon_len = (ulong)_end - (ulong)_init;
#elif defined(CONFIG_SANDBOX)
/* gcc does not provide _init in crti.o on RISC-V */
gd->mon_len = 0;
#elif defined(CONFIG_EFI_APP)
- gd->mon_len = (ulong)&_end - (ulong)_init;
+ gd->mon_len = (ulong)_end - (ulong)_init;
#elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
gd->mon_len = CONFIG_SYS_MONITOR_LEN;
#elif defined(CONFIG_SH) || defined(CONFIG_RISCV)
- gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
+ gd->mon_len = (ulong)(__bss_end) - (ulong)(_start);
#elif defined(CONFIG_SYS_MONITOR_BASE)
- /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
- gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
+ /* TODO: use (ulong)__bss_end - (ulong)__text_start; ? */
+ gd->mon_len = (ulong)__bss_end - CONFIG_SYS_MONITOR_BASE;
#endif
return 0;
}
@@ -800,7 +794,7 @@
static int initf_dm(void)
{
-#if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if defined(CONFIG_DM) && CONFIG_IS_ENABLED(SYS_MALLOC_F)
int ret;
bootstage_start(BOOTSTAGE_ID_ACCUM_DM_F, "dm_f");
@@ -835,11 +829,6 @@
return 0;
}
-static int misc_init_f(void)
-{
- return event_notify_null(EVT_MISC_INIT_F);
-}
-
static const init_fnc_t init_sequence_f[] = {
setup_mon_len,
#ifdef CONFIG_OF_CONTROL
@@ -852,16 +841,12 @@
log_init,
initf_bootstage, /* uses its own timer, so does not need DM */
event_init,
-#ifdef CONFIG_BLOBLIST
- bloblist_init,
-#endif
+ bloblist_maybe_init,
setup_spl_handoff,
#if defined(CONFIG_CONSOLE_RECORD_INIT_F)
console_record_init,
#endif
-#if defined(CONFIG_HAVE_FSP)
- arch_fsp_init,
-#endif
+ INITCALL_EVENT(EVT_FSP_INIT_F),
arch_cpu_init, /* basic arch cpu dependent setup */
mach_cpu_init, /* SoC/machine dependent CPU setup */
initf_dm,
@@ -898,14 +883,11 @@
show_board_info,
#endif
INIT_FUNC_WATCHDOG_INIT
- misc_init_f,
+ INITCALL_EVENT(EVT_MISC_INIT_F),
INIT_FUNC_WATCHDOG_RESET
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
init_func_i2c,
#endif
-#if defined(CONFIG_VID) && !defined(CONFIG_SPL)
- init_func_vid,
-#endif
announce_dram_init,
dram_init, /* configure available RAM banks */
#ifdef CONFIG_POST
diff --git a/common/board_r.c b/common/board_r.c
index 88137e4..d80680f 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -126,9 +126,9 @@
#ifdef __ARM__
monitor_flash_len = _end - __image_copy_start;
#elif defined(CONFIG_RISCV)
- monitor_flash_len = (ulong)&_end - (ulong)&_start;
+ monitor_flash_len = (ulong)_end - (ulong)_start;
#elif !defined(CONFIG_SANDBOX) && !defined(CONFIG_NIOS2)
- monitor_flash_len = (ulong)&__init_end - gd->relocaddr;
+ monitor_flash_len = (ulong)__init_end - gd->relocaddr;
#endif
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
/*
@@ -151,13 +151,6 @@
*/
gd->env_addr += gd->reloc_off;
#endif
- /*
- * The fdt_blob needs to be moved to new relocation address
- * incase of FDT blob is embedded with in image
- */
- if (IS_ENABLED(CONFIG_OF_EMBED) && IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC))
- gd->fdt_blob += gd->reloc_off;
-
#ifdef CONFIG_EFI_LOADER
/*
* On the ARM architecture gd is mapped to a fixed register (r9 or x18).
@@ -198,7 +191,7 @@
{
ulong start;
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
debug("Pre-reloc malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr,
gd->malloc_ptr / 1024);
#endif
@@ -295,15 +288,6 @@
return 0;
}
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
-static int initr_manual_reloc_cmdtable(void)
-{
- fixup_cmdtable(ll_entry_start(struct cmd_tbl, cmd),
- ll_entry_count(struct cmd_tbl, cmd));
- return 0;
-}
-#endif
-
static int initr_binman(void)
{
int ret;
@@ -583,7 +567,10 @@
}
/*
- * We hope to remove most of the driver-related init and do it if/when
+ * Over time we hope to remove these functions with code fragments and
+ * stub functions, and instead call the relevant function directly.
+ *
+ * We also hope to remove most of the driver-related init and do it if/when
* the driver is later used.
*
* TODO: perhaps reset the watchdog in the initcall function after each call?
@@ -603,9 +590,6 @@
*/
#endif
initr_reloc_global_data,
-#if IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC) && CONFIG_IS_ENABLED(EVENT)
- event_manual_reloc,
-#endif
#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
initr_unlock_ram_in_cache,
#endif
@@ -654,12 +638,6 @@
initr_watchdog,
#endif
INIT_FUNC_WATCHDOG_RESET
-#if defined(CONFIG_NEEDS_MANUAL_RELOC) && defined(CONFIG_BLOCK_CACHE)
- blkcache_init,
-#endif
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
- initr_manual_reloc_cmdtable,
-#endif
arch_initr_trap,
#if defined(CONFIG_BOARD_EARLY_INIT_R)
board_early_init_r,
@@ -715,6 +693,7 @@
#if defined(CONFIG_ID_EEPROM)
mac_read_from_eeprom,
#endif
+ INITCALL_EVENT(EVT_SETTINGS_R),
INIT_FUNC_WATCHDOG_RESET
#if defined(CONFIG_PCI_INIT_R) && !defined(CONFIG_SYS_EARLY_PCI_INIT)
/*
@@ -770,15 +749,8 @@
#ifdef CONFIG_POST
initr_post,
#endif
-#ifdef CONFIG_LAST_STAGE_INIT
INIT_FUNC_WATCHDOG_RESET
- /*
- * Some parts can be only initialized if all others (like
- * Interrupts) are up and running (i.e. the PC-style ISA
- * keyboard).
- */
- last_stage_init,
-#endif
+ INITCALL_EVENT(EVT_LAST_STAGE_INIT),
#if defined(CFG_PRAM)
initr_mem,
#endif
@@ -811,11 +783,6 @@
#endif
gd->flags &= ~GD_FLG_LOG_READY;
- if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC)) {
- for (int i = 0; i < ARRAY_SIZE(init_sequence_r); i++)
- MANUAL_RELOC(init_sequence_r[i]);
- }
-
if (initcall_run_list(init_sequence_r))
hang();
diff --git a/common/bootstage.c b/common/bootstage.c
index 326c40f..0e6d807 100644
--- a/common/bootstage.c
+++ b/common/bootstage.c
@@ -137,7 +137,7 @@
rec->flags = flags;
rec->id = id;
} else {
- log_warning("Bootstage space exhasuted\n");
+ log_warning("Bootstage space exhausted\n");
}
}
@@ -502,6 +502,20 @@
return 0;
}
+int _bootstage_stash_default(void)
+{
+ return bootstage_stash(map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR, 0),
+ CONFIG_BOOTSTAGE_STASH_SIZE);
+}
+
+int _bootstage_unstash_default(void)
+{
+ const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
+ CONFIG_BOOTSTAGE_STASH_SIZE);
+
+ return bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
+}
+
int bootstage_get_size(void)
{
struct bootstage_data *data = gd->bootstage;
diff --git a/common/bouncebuf.c b/common/bouncebuf.c
index 93a3566..934b83f 100644
--- a/common/bouncebuf.c
+++ b/common/bouncebuf.c
@@ -79,7 +79,7 @@
{
if (state->flags & GEN_BB_WRITE) {
/* Invalidate cache so that CPU can see any newly DMA'd data */
- dma_unmap_single((dma_addr_t)state->bounce_buffer,
+ dma_unmap_single((dma_addr_t)(uintptr_t)state->bounce_buffer,
state->len_aligned,
DMA_BIDIRECTIONAL);
}
diff --git a/common/cli_getch.c b/common/cli_getch.c
index 61d4cb2..0ee7908 100644
--- a/common/cli_getch.c
+++ b/common/cli_getch.c
@@ -46,6 +46,8 @@
case 1:
if (ichar == '[' || ichar == 'O')
act = ESC_SAVE;
+ else
+ act = ESC_CONVERTED;
break;
case 2:
switch (ichar) {
diff --git a/common/cli_hush.c b/common/cli_hush.c
index cee8724..9cda97f 100644
--- a/common/cli_hush.c
+++ b/common/cli_hush.c
@@ -3305,19 +3305,6 @@
}
#ifdef __U_BOOT__
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
-static void u_boot_hush_reloc(void)
-{
- unsigned long addr;
- struct reserved_combo *r;
-
- for (r=reserved_list; r<reserved_list+NRES; r++) {
- addr = (ulong) (r->literal) + gd->reloc_off;
- r->literal = (char *)addr;
- }
-}
-#endif
-
int u_boot_hush_start(void)
{
if (top_vars == NULL) {
@@ -3327,9 +3314,6 @@
top_vars->next = NULL;
top_vars->flg_export = 0;
top_vars->flg_read_only = 1;
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
- u_boot_hush_reloc();
-#endif
}
return 0;
}
diff --git a/common/cli_readline.c b/common/cli_readline.c
index e83743e..06b8d46 100644
--- a/common/cli_readline.c
+++ b/common/cli_readline.c
@@ -89,6 +89,14 @@
#define add_idx_minus_one() ((hist_add_idx == 0) ? hist_max : hist_add_idx-1)
+static void getcmd_putchars(int count, int ch)
+{
+ int i;
+
+ for (i = 0; i < count; i++)
+ getcmd_putch(ch);
+}
+
static void hist_init(void)
{
int i;
@@ -160,11 +168,10 @@
return ret;
}
-#ifndef CONFIG_CMDLINE_EDITING
-static void cread_print_hist_list(void)
+void cread_print_hist_list(void)
{
int i;
- unsigned long n;
+ uint n;
n = hist_num - hist_max;
@@ -179,36 +186,35 @@
i++;
}
}
-#endif /* CONFIG_CMDLINE_EDITING */
#define BEGINNING_OF_LINE() { \
- while (num) { \
+ while (cls->num) { \
getcmd_putch(CTL_BACKSPACE); \
- num--; \
+ cls->num--; \
} \
}
#define ERASE_TO_EOL() { \
- if (num < eol_num) { \
- printf("%*s", (int)(eol_num - num), ""); \
+ if (cls->num < cls->eol_num) { \
+ printf("%*s", (int)(cls->eol_num - cls->num), ""); \
do { \
getcmd_putch(CTL_BACKSPACE); \
- } while (--eol_num > num); \
+ } while (--cls->eol_num > cls->num); \
} \
}
-#define REFRESH_TO_EOL() { \
- if (num < eol_num) { \
- wlen = eol_num - num; \
- putnstr(buf + num, wlen); \
- num = eol_num; \
- } \
+#define REFRESH_TO_EOL() { \
+ if (cls->num < cls->eol_num) { \
+ uint wlen = cls->eol_num - cls->num; \
+ putnstr(buf + cls->num, wlen); \
+ cls->num = cls->eol_num; \
+ } \
}
-static void cread_add_char(char ichar, int insert, unsigned long *num,
- unsigned long *eol_num, char *buf, unsigned long len)
+static void cread_add_char(char ichar, int insert, uint *num,
+ uint *eol_num, char *buf, uint len)
{
- unsigned long wlen;
+ uint wlen;
/* room ??? */
if (insert || *num == *eol_num) {
@@ -239,8 +245,7 @@
}
static void cread_add_str(char *str, int strsize, int insert,
- unsigned long *num, unsigned long *eol_num,
- char *buf, unsigned long len)
+ uint *num, uint *eol_num, char *buf, uint len)
{
while (strsize--) {
cread_add_char(*str, insert, num, eol_num, buf, len);
@@ -248,24 +253,208 @@
}
}
+int cread_line_process_ch(struct cli_line_state *cls, char ichar)
+{
+ char *buf = cls->buf;
+
+ /* ichar=0x0 when error occurs in U-Boot getc */
+ if (!ichar)
+ return -EAGAIN;
+
+ if (ichar == '\n') {
+ putc('\n');
+ buf[cls->eol_num] = '\0'; /* terminate the string */
+ return 0;
+ }
+
+ switch (ichar) {
+ case CTL_CH('a'):
+ BEGINNING_OF_LINE();
+ break;
+ case CTL_CH('c'): /* ^C - break */
+ *buf = '\0'; /* discard input */
+ return -EINTR;
+ case CTL_CH('f'):
+ if (cls->num < cls->eol_num) {
+ getcmd_putch(buf[cls->num]);
+ cls->num++;
+ }
+ break;
+ case CTL_CH('b'):
+ if (cls->num) {
+ getcmd_putch(CTL_BACKSPACE);
+ cls->num--;
+ }
+ break;
+ case CTL_CH('d'):
+ if (cls->num < cls->eol_num) {
+ uint wlen;
+
+ wlen = cls->eol_num - cls->num - 1;
+ if (wlen) {
+ memmove(&buf[cls->num], &buf[cls->num + 1],
+ wlen);
+ putnstr(buf + cls->num, wlen);
+ }
+
+ getcmd_putch(' ');
+ do {
+ getcmd_putch(CTL_BACKSPACE);
+ } while (wlen--);
+ cls->eol_num--;
+ }
+ break;
+ case CTL_CH('k'):
+ ERASE_TO_EOL();
+ break;
+ case CTL_CH('e'):
+ REFRESH_TO_EOL();
+ break;
+ case CTL_CH('o'):
+ cls->insert = !cls->insert;
+ break;
+ case CTL_CH('w'):
+ if (cls->num) {
+ uint base, wlen;
+
+ for (base = cls->num - 1;
+ base >= 0 && buf[base] == ' ';)
+ base--;
+ for (; base > 0 && buf[base - 1] != ' ';)
+ base--;
+
+ /* now delete chars from base to cls->num */
+ wlen = cls->num - base;
+ cls->eol_num -= wlen;
+ memmove(&buf[base], &buf[cls->num],
+ cls->eol_num - base + 1);
+ cls->num = base;
+ getcmd_putchars(wlen, CTL_BACKSPACE);
+ puts(buf + base);
+ getcmd_putchars(wlen, ' ');
+ getcmd_putchars(wlen + cls->eol_num - cls->num,
+ CTL_BACKSPACE);
+ }
+ break;
+ case CTL_CH('x'):
+ case CTL_CH('u'):
+ BEGINNING_OF_LINE();
+ ERASE_TO_EOL();
+ break;
+ case DEL:
+ case DEL7:
+ case 8:
+ if (cls->num) {
+ uint wlen;
+
+ wlen = cls->eol_num - cls->num;
+ cls->num--;
+ memmove(&buf[cls->num], &buf[cls->num + 1], wlen);
+ getcmd_putch(CTL_BACKSPACE);
+ putnstr(buf + cls->num, wlen);
+ getcmd_putch(' ');
+ do {
+ getcmd_putch(CTL_BACKSPACE);
+ } while (wlen--);
+ cls->eol_num--;
+ }
+ break;
+ case CTL_CH('p'):
+ case CTL_CH('n'):
+ if (cls->history) {
+ char *hline;
+
+ if (ichar == CTL_CH('p'))
+ hline = hist_prev();
+ else
+ hline = hist_next();
+
+ if (!hline) {
+ getcmd_cbeep();
+ break;
+ }
+
+ /* nuke the current line */
+ /* first, go home */
+ BEGINNING_OF_LINE();
+
+ /* erase to end of line */
+ ERASE_TO_EOL();
+
+ /* copy new line into place and display */
+ strcpy(buf, hline);
+ cls->eol_num = strlen(buf);
+ REFRESH_TO_EOL();
+ break;
+ }
+ break;
+ case '\t':
+ if (IS_ENABLED(CONFIG_AUTO_COMPLETE) && cls->cmd_complete) {
+ int num2, col;
+
+ /* do not autocomplete when in the middle */
+ if (cls->num < cls->eol_num) {
+ getcmd_cbeep();
+ break;
+ }
+
+ buf[cls->num] = '\0';
+ col = strlen(cls->prompt) + cls->eol_num;
+ num2 = cls->num;
+ if (cmd_auto_complete(cls->prompt, buf, &num2, &col)) {
+ col = num2 - cls->num;
+ cls->num += col;
+ cls->eol_num += col;
+ }
+ break;
+ }
+ fallthrough;
+ default:
+ cread_add_char(ichar, cls->insert, &cls->num, &cls->eol_num,
+ buf, cls->len);
+ break;
+ }
+
+ /*
+ * keep the string terminated...if we added a char at the end then we
+ * want a \0 after it
+ */
+ buf[cls->eol_num] = '\0';
+
+ return -EAGAIN;
+}
+
+void cli_cread_init(struct cli_line_state *cls, char *buf, uint buf_size)
+{
+ int init_len = strlen(buf);
+
+ memset(cls, '\0', sizeof(struct cli_line_state));
+ cls->insert = true;
+ cls->buf = buf;
+ cls->len = buf_size;
+
+ if (init_len)
+ cread_add_str(buf, init_len, 0, &cls->num, &cls->eol_num, buf,
+ buf_size);
+}
+
static int cread_line(const char *const prompt, char *buf, unsigned int *len,
- int timeout)
+ int timeout)
{
struct cli_ch_state s_cch, *cch = &s_cch;
- unsigned long num = 0;
- unsigned long eol_num = 0;
- unsigned long wlen;
+ struct cli_line_state s_cls, *cls = &s_cls;
char ichar;
- int insert = 1;
- int init_len = strlen(buf);
int first = 1;
cli_ch_init(cch);
-
- if (init_len)
- cread_add_str(buf, init_len, 1, &num, &eol_num, buf, *len);
+ cli_cread_init(cls, buf, *len);
+ cls->prompt = prompt;
+ cls->history = true;
+ cls->cmd_complete = true;
while (1) {
+ int ret;
+
/* Check for saved characters */
ichar = cli_ch_process(cch, 0);
@@ -287,136 +476,13 @@
ichar = cli_ch_process(cch, ichar);
}
- /* ichar=0x0 when error occurs in U-Boot getc */
- if (!ichar)
- continue;
-
- if (ichar == '\n') {
- putc('\n');
- break;
- }
-
- switch (ichar) {
- case CTL_CH('a'):
- BEGINNING_OF_LINE();
- break;
- case CTL_CH('c'): /* ^C - break */
- *buf = '\0'; /* discard input */
+ ret = cread_line_process_ch(cls, ichar);
+ if (ret == -EINTR)
return -1;
- case CTL_CH('f'):
- if (num < eol_num) {
- getcmd_putch(buf[num]);
- num++;
- }
+ else if (!ret)
break;
- case CTL_CH('b'):
- if (num) {
- getcmd_putch(CTL_BACKSPACE);
- num--;
- }
- break;
- case CTL_CH('d'):
- if (num < eol_num) {
- wlen = eol_num - num - 1;
- if (wlen) {
- memmove(&buf[num], &buf[num+1], wlen);
- putnstr(buf + num, wlen);
- }
-
- getcmd_putch(' ');
- do {
- getcmd_putch(CTL_BACKSPACE);
- } while (wlen--);
- eol_num--;
- }
- break;
- case CTL_CH('k'):
- ERASE_TO_EOL();
- break;
- case CTL_CH('e'):
- REFRESH_TO_EOL();
- break;
- case CTL_CH('o'):
- insert = !insert;
- break;
- case CTL_CH('x'):
- case CTL_CH('u'):
- BEGINNING_OF_LINE();
- ERASE_TO_EOL();
- break;
- case DEL:
- case DEL7:
- case 8:
- if (num) {
- wlen = eol_num - num;
- num--;
- memmove(&buf[num], &buf[num+1], wlen);
- getcmd_putch(CTL_BACKSPACE);
- putnstr(buf + num, wlen);
- getcmd_putch(' ');
- do {
- getcmd_putch(CTL_BACKSPACE);
- } while (wlen--);
- eol_num--;
- }
- break;
- case CTL_CH('p'):
- case CTL_CH('n'):
- {
- char *hline;
-
- if (ichar == CTL_CH('p'))
- hline = hist_prev();
- else
- hline = hist_next();
-
- if (!hline) {
- getcmd_cbeep();
- continue;
- }
-
- /* nuke the current line */
- /* first, go home */
- BEGINNING_OF_LINE();
-
- /* erase to end of line */
- ERASE_TO_EOL();
-
- /* copy new line into place and display */
- strcpy(buf, hline);
- eol_num = strlen(buf);
- REFRESH_TO_EOL();
- continue;
- }
-#ifdef CONFIG_AUTO_COMPLETE
- case '\t': {
- int num2, col;
-
- /* do not autocomplete when in the middle */
- if (num < eol_num) {
- getcmd_cbeep();
- break;
- }
-
- buf[num] = '\0';
- col = strlen(prompt) + eol_num;
- num2 = num;
- if (cmd_auto_complete(prompt, buf, &num2, &col)) {
- col = num2 - num;
- num += col;
- eol_num += col;
- }
- break;
- }
-#endif
- default:
- cread_add_char(ichar, insert, &num, &eol_num, buf,
- *len);
- break;
- }
}
- *len = eol_num;
- buf[eol_num] = '\0'; /* lose the newline */
+ *len = cls->eol_num;
if (buf[0] && buf[0] != CREAD_HIST_CHAR)
cread_add_to_hist(buf);
@@ -425,6 +491,18 @@
return 0;
}
+#else /* !CONFIG_CMDLINE_EDITING */
+
+static inline void hist_init(void)
+{
+}
+
+static int cread_line(const char *const prompt, char *buf, unsigned int *len,
+ int timeout)
+{
+ return 0;
+}
+
#endif /* CONFIG_CMDLINE_EDITING */
/****************************************************************************/
@@ -440,41 +518,22 @@
return cli_readline_into_buffer(prompt, console_buffer, 0);
}
-
-int cli_readline_into_buffer(const char *const prompt, char *buffer,
- int timeout)
+/**
+ * cread_line_simple() - Simple (small) command-line reader
+ *
+ * This supports only basic editing, with no cursor movement
+ *
+ * @prompt: Prompt to display
+ * @p: Text buffer to edit
+ * Return: length of text buffer, or -1 if input was cannncelled (Ctrl-C)
+ */
+static int cread_line_simple(const char *const prompt, char *p)
{
- char *p = buffer;
-#ifdef CONFIG_CMDLINE_EDITING
- unsigned int len = CONFIG_SYS_CBSIZE;
- int rc;
- static int initted;
-
- /*
- * History uses a global array which is not
- * writable until after relocation to RAM.
- * Revert to non-history version if still
- * running from flash.
- */
- if (gd->flags & GD_FLG_RELOC) {
- if (!initted) {
- hist_init();
- initted = 1;
- }
-
- if (prompt)
- puts(prompt);
-
- rc = cread_line(prompt, p, &len, timeout);
- return rc < 0 ? rc : len;
-
- } else {
-#endif /* CONFIG_CMDLINE_EDITING */
char *p_buf = p;
- int n = 0; /* buffer index */
- int plen = 0; /* prompt length */
- int col; /* output column cnt */
- char c;
+ int n = 0; /* buffer index */
+ int plen = 0; /* prompt length */
+ int col; /* output column cnt */
+ char c;
/* print prompt */
if (prompt) {
@@ -528,14 +587,15 @@
continue;
default:
- /*
- * Must be a normal character then
- */
- if (n < CONFIG_SYS_CBSIZE-2) {
- if (c == '\t') { /* expand TABs */
-#ifdef CONFIG_AUTO_COMPLETE
+ /* Must be a normal character then */
+ if (n >= CONFIG_SYS_CBSIZE - 2) { /* Buffer full */
+ putc('\a');
+ break;
+ }
+ if (c == '\t') { /* expand TABs */
+ if (IS_ENABLED(CONFIG_AUTO_COMPLETE)) {
/*
- * if auto completion triggered just
+ * if auto-completion triggered just
* continue
*/
*p = '\0';
@@ -545,29 +605,55 @@
p = p_buf + n; /* reset */
continue;
}
-#endif
- puts(tab_seq + (col & 07));
- col += 8 - (col & 07);
- } else {
- char __maybe_unused buf[2];
-
- /*
- * Echo input using puts() to force an
- * LCD flush if we are using an LCD
- */
- ++col;
- buf[0] = c;
- buf[1] = '\0';
- puts(buf);
}
- *p++ = c;
- ++n;
- } else { /* Buffer full */
- putc('\a');
+ puts(tab_seq + (col & 07));
+ col += 8 - (col & 07);
+ } else {
+ char __maybe_unused buf[2];
+
+ /*
+ * Echo input using puts() to force an LCD
+ * flush if we are using an LCD
+ */
+ ++col;
+ buf[0] = c;
+ buf[1] = '\0';
+ puts(buf);
}
+ *p++ = c;
+ ++n;
+ break;
}
}
-#ifdef CONFIG_CMDLINE_EDITING
+}
+
+int cli_readline_into_buffer(const char *const prompt, char *buffer,
+ int timeout)
+{
+ char *p = buffer;
+ uint len = CONFIG_SYS_CBSIZE;
+ int rc;
+ static int initted;
+
+ /*
+ * History uses a global array which is not
+ * writable until after relocation to RAM.
+ * Revert to non-history version if still
+ * running from flash.
+ */
+ if (IS_ENABLED(CONFIG_CMDLINE_EDITING) && (gd->flags & GD_FLG_RELOC)) {
+ if (!initted) {
+ hist_init();
+ initted = 1;
+ }
+
+ if (prompt)
+ puts(prompt);
+
+ rc = cread_line(prompt, p, &len, timeout);
+ return rc < 0 ? rc : len;
+
+ } else {
+ return cread_line_simple(prompt, p);
}
-#endif
}
diff --git a/common/dfu.c b/common/dfu.c
index 9619088..0d154e8 100644
--- a/common/dfu.c
+++ b/common/dfu.c
@@ -19,22 +19,25 @@
#include <g_dnl.h>
#include <usb.h>
#include <net.h>
+#include <linux/printk.h>
int run_usb_dnl_gadget(int usbctrl_index, char *usb_dnl_gadget)
{
bool dfu_reset = false;
+ struct udevice *udc;
int ret, i = 0;
- ret = usb_gadget_initialize(usbctrl_index);
+ ret = udc_device_get_by_index(usbctrl_index, &udc);
if (ret) {
- pr_err("usb_gadget_initialize failed\n");
+ pr_err("udc_device_get_by_index failed\n");
return CMD_RET_FAILURE;
}
g_dnl_clear_detach();
ret = g_dnl_register(usb_dnl_gadget);
if (ret) {
pr_err("g_dnl_register failed");
- return CMD_RET_FAILURE;
+ ret = CMD_RET_FAILURE;
+ goto err_detach;
}
#ifdef CONFIG_DFU_TIMEOUT
@@ -54,7 +57,7 @@
}
/*
- * This extra number of usb_gadget_handle_interrupts()
+ * This extra number of dm_usb_gadget_handle_interrupts()
* calls is necessary to assure correct transmission
* completion with dfu-util
*/
@@ -67,7 +70,7 @@
if (dfu_get_defer_flush()) {
/*
- * Call to usb_gadget_handle_interrupts() is necessary
+ * Call to dm_usb_gadget_handle_interrupts() is necessary
* to act on ZLP OUT transaction from HOST PC after
* transmitting the whole file.
*
@@ -76,7 +79,7 @@
* 5 seconds). In such situation the dfu-util program
* exits with error message.
*/
- usb_gadget_handle_interrupts(usbctrl_index);
+ dm_usb_gadget_handle_interrupts(udc);
ret = dfu_flush(dfu_get_defer_flush(), NULL, 0, 0);
dfu_set_defer_flush(NULL);
if (ret) {
@@ -102,11 +105,12 @@
goto exit;
schedule();
- usb_gadget_handle_interrupts(usbctrl_index);
+ dm_usb_gadget_handle_interrupts(udc);
}
exit:
g_dnl_unregister();
- usb_gadget_release(usbctrl_index);
+err_detach:
+ udc_device_put(udc);
if (dfu_reset)
do_reset(NULL, 0, 0, NULL);
diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index dcecdb8..de3f042 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -8,14 +8,14 @@
* as file malloc-2.6.6.c.
*/
-#include <common.h>
-#include <log.h>
-#include <asm/global_data.h>
-
#if CONFIG_IS_ENABLED(UNIT_TEST)
#define DEBUG
#endif
+#include <common.h>
+#include <log.h>
+#include <asm/global_data.h>
+
#include <malloc.h>
#include <asm/io.h>
#include <valgrind/memcheck.h>
@@ -575,19 +575,6 @@
IAV(120), IAV(121), IAV(122), IAV(123), IAV(124), IAV(125), IAV(126), IAV(127)
};
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
-static void malloc_bin_reloc(void)
-{
- mbinptr *p = &av_[2];
- size_t i;
-
- for (i = 2; i < ARRAY_SIZE(av_); ++i, ++p)
- *p = (mbinptr)((ulong)*p + gd->reloc_off);
-}
-#else
-static inline void malloc_bin_reloc(void) {}
-#endif
-
#ifdef CONFIG_SYS_MALLOC_DEFAULT_TO_INIT
static void malloc_init(void);
#endif
@@ -634,7 +621,6 @@
#if CONFIG_IS_ENABLED(SYS_MALLOC_CLEAR_ON_INIT)
memset((void *)mem_malloc_start, 0x0, size);
#endif
- malloc_bin_reloc();
}
/* field-extraction macros */
@@ -1305,7 +1291,7 @@
INTERNAL_SIZE_T nb;
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT))
return malloc_simple(bytes);
#endif
@@ -1586,7 +1572,7 @@
mchunkptr fwd; /* misc temp for linking */
int islr; /* track whether merging with last_remainder */
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
/* free() is a no-op - all the memory will be freed on relocation */
if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) {
VALGRIND_FREELIKE_BLOCK(mem, SIZE_SZ);
@@ -1749,7 +1735,7 @@
/* realloc of null is supposed to be same as malloc */
if (oldmem == NULL) return mALLOc(bytes);
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) {
/* This is harder to support and should not be needed */
panic("pre-reloc realloc() is not supported");
@@ -1971,7 +1957,7 @@
if ((long)bytes < 0) return NULL;
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) {
return memalign_simple(alignment, bytes);
}
@@ -2167,7 +2153,7 @@
return NULL;
else
{
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) {
memset(mem, 0, sz);
return mem;
@@ -2469,7 +2455,7 @@
int initf_malloc(void)
{
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
assert(gd->malloc_base); /* Set up by crt0.S */
gd->malloc_limit = CONFIG_VAL(SYS_MALLOC_F_LEN);
gd->malloc_ptr = 0;
diff --git a/common/event.c b/common/event.c
index 6653300..dc61b96 100644
--- a/common/event.c
+++ b/common/event.c
@@ -36,6 +36,9 @@
/* init hooks */
"misc_init_f",
+ "fsp_init_r",
+ "settings_r",
+ "last_stage_init",
/* Fpga load hook */
"fpga_load",
@@ -50,7 +53,7 @@
_Static_assert(ARRAY_SIZE(type_name) == EVT_COUNT, "event type_name size");
#endif
-static const char *event_type_name(enum event_t type)
+const char *event_type_name(enum event_t type)
{
#if CONFIG_IS_ENABLED(EVENT_DEBUG)
return type_name[type];
@@ -72,7 +75,14 @@
log_debug("Sending event %x/%s to spy '%s'\n", ev->type,
event_type_name(ev->type), event_spy_id(spy));
- ret = spy->func(NULL, ev);
+ if (spy->flags & EVSPYF_SIMPLE) {
+ const struct evspy_info_simple *simple;
+
+ simple = (struct evspy_info_simple *)spy;
+ ret = simple->func();
+ } else {
+ ret = spy->func(NULL, ev);
+ }
/*
* TODO: Handle various return codes to
@@ -159,20 +169,6 @@
}
}
-#if IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC)
-int event_manual_reloc(void)
-{
- struct evspy_info *spy, *end;
-
- spy = ll_entry_start(struct evspy_info, evspy_info);
- end = ll_entry_end(struct evspy_info, evspy_info);
- for (; spy < end; spy++)
- MANUAL_RELOC(spy->func);
-
- return 0;
-}
-#endif
-
#if CONFIG_IS_ENABLED(EVENT_DYNAMIC)
static void spy_free(struct event_spy *spy)
{
diff --git a/common/hash.c b/common/hash.c
index cbffdfd..e837c56 100644
--- a/common/hash.c
+++ b/common/hash.c
@@ -21,7 +21,6 @@
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/errno.h>
-#include <u-boot/crc.h>
#else
#include "mkimage.h"
#include <linux/compiler_attributes.h>
@@ -37,12 +36,6 @@
#include <u-boot/sha512.h>
#include <u-boot/md5.h>
-#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC)
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
-static void reloc_update(void);
-
static int __maybe_unused hash_init_sha1(struct hash_algo *algo, void **ctxp)
{
sha1_context *ctx = malloc(sizeof(sha1_context));
@@ -334,31 +327,10 @@
#define multi_hash() 0
#endif
-static void reloc_update(void)
-{
-#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC)
- int i;
- static bool done;
-
- if (!done) {
- done = true;
- for (i = 0; i < ARRAY_SIZE(hash_algo); i++) {
- hash_algo[i].name += gd->reloc_off;
- hash_algo[i].hash_func_ws += gd->reloc_off;
- hash_algo[i].hash_init += gd->reloc_off;
- hash_algo[i].hash_update += gd->reloc_off;
- hash_algo[i].hash_finish += gd->reloc_off;
- }
- }
-#endif
-}
-
int hash_lookup_algo(const char *algo_name, struct hash_algo **algop)
{
int i;
- reloc_update();
-
for (i = 0; i < ARRAY_SIZE(hash_algo); i++) {
if (!strcmp(algo_name, hash_algo[i].name)) {
*algop = &hash_algo[i];
@@ -375,8 +347,6 @@
{
int i;
- reloc_update();
-
for (i = 0; i < ARRAY_SIZE(hash_algo); i++) {
if (!strcmp(algo_name, hash_algo[i].name)) {
if (hash_algo[i].hash_init) {
diff --git a/common/init/board_init.c b/common/init/board_init.c
index b0b5657..5c87906 100644
--- a/common/init/board_init.c
+++ b/common/init/board_init.c
@@ -79,7 +79,7 @@
{
/* Reserve early malloc arena */
#ifndef CFG_MALLOC_F_ADDR
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
top -= CONFIG_VAL(SYS_MALLOC_F_LEN);
#endif
#endif
@@ -159,7 +159,7 @@
* Use gd as it is now properly set for all architectures.
*/
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
/* go down one 'early malloc arena' */
gd->malloc_base = base;
#if CONFIG_IS_ENABLED(ZERO_MEM_BEFORE_USE)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index c5dd476..c521b02 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -67,7 +67,7 @@
config SPL_SIZE_LIMIT_PROVIDE_STACK
hex "SPL image size check: provide stack space before relocation"
depends on SPL_SIZE_LIMIT > 0
- default 0
+ default 0x0
help
If set, this size is reserved in SPL_SIZE_LIMIT check to ensure such
an image does not overflow SRAM if SPL_SIZE_LIMIT describes the size
@@ -265,7 +265,7 @@
default 0x402F0400 if AM33XX
default 0x40301350 if OMAP54XX
default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I
- default 0x20060 if SUN50I_GEN_H6
+ default 0x20060 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2
default 0x00060 if ARCH_SUNXI
default 0xfffc0000 if ARCH_ZYNQMP
default 0x0
@@ -330,6 +330,20 @@
If disabled, Legacy images are booted if the image magic and size
are correct, without further integrity checks.
+config SPL_LOAD_IMX_CONTAINER
+ bool "Enable SPL loading and booting of i.MX8 Containers"
+ depends on SPL
+ help
+ Support booting U-Boot from an i.MX8 container image. If you are not
+ using i.MX8, say 'n'.
+
+config IMX_CONTAINER_CFG
+ string "i.MX8 Container config file"
+ depends on SPL && SPL_LOAD_IMX_CONTAINER
+ help
+ Specify the cfg file for generating the container image which will be
+ loaded by SPL.
+
config SPL_SYS_MALLOC_SIMPLE
bool "Only use malloc_simple functions in the SPL"
help
@@ -356,7 +370,8 @@
default 0x93ffb8 if ARCH_MX6 && MX6_OCRAM_256KB
default 0x91ffb8 if ARCH_MX6 && !MX6_OCRAM_256KB
default 0x118000 if MACH_SUN50I_H6
- default 0x58000 if MACH_SUN50I_H616
+ default 0x52a00 if MACH_SUN50I_H616
+ default 0x40000 if MACH_SUN8I_R528
default 0x54000 if MACH_SUN50I || MACH_SUN50I_H5
default 0x18000 if MACH_SUN9I
default 0x8000 if ARCH_SUNXI
@@ -402,21 +417,21 @@
location is used. Normally we put the device tree at the end of BSS
but with this option enabled, it goes at _image_binary_end.
-config SYS_SPL_MALLOC
+config SPL_SYS_MALLOC
bool "Enable malloc pool in SPL"
depends on SPL_FRAMEWORK
-config HAS_CUSTOM_SPL_MALLOC_START
+config SPL_HAS_CUSTOM_MALLOC_START
bool "For the SPL malloc pool, define a custom starting address"
- depends on SYS_SPL_MALLOC
+ depends on SPL_SYS_MALLOC
-config CUSTOM_SYS_SPL_MALLOC_ADDR
+config SPL_CUSTOM_SYS_MALLOC_ADDR
hex "SPL malloc addr"
- depends on HAS_CUSTOM_SPL_MALLOC_START
+ depends on SPL_HAS_CUSTOM_MALLOC_START
-config SYS_SPL_MALLOC_SIZE
+config SPL_SYS_MALLOC_SIZE
hex "Size of the SPL malloc pool"
- depends on SYS_SPL_MALLOC
+ depends on SPL_SYS_MALLOC
default 0x100000
config SPL_READ_ONLY
@@ -643,6 +658,7 @@
config SPL_FS_EXT4
bool "Support EXT filesystems"
+ select SPL_CRC16 if EXT4_WRITE
help
Enable support for EXT2/3/4 filesystems with SPL. This permits
U-Boot (or Linux in Falcon mode) to be loaded from an EXT
@@ -1063,7 +1079,7 @@
Enable booting directly to an OS from SPL.
for more info read doc/README.falcon
-config SYS_SPL_ARGS_ADDR
+config SPL_PAYLOAD_ARGS_ADDR
hex "Address in memory to load 'args' file for Falcon Mode to"
depends on SPL_OS_BOOT
default 0x88000000 if ARCH_OMAP2PLUS
diff --git a/common/spl/Kconfig.nxp b/common/spl/Kconfig.nxp
index fc696cf..53e9b9f 100644
--- a/common/spl/Kconfig.nxp
+++ b/common/spl/Kconfig.nxp
@@ -59,7 +59,7 @@
config SPL_RELOC_STACK
hex "Address of the start of the stack SPL will use after relocation."
help
- If unspecified, this is equal to CFG_SYS_SPL_MALLOC_START. Starting
+ If unspecified, this is equal to CFG_SPL_SYS_MALLOC_START. Starting
address of the malloc pool used in SPL. When this option is set the full
malloc is used in SPL and it is set up by spl_init() and before that, the
simple malloc() can be used if CONFIG_SYS_MALLOC_F is defined.
diff --git a/common/spl/Kconfig.tpl b/common/spl/Kconfig.tpl
index 3d6cf1e..cc71578 100644
--- a/common/spl/Kconfig.tpl
+++ b/common/spl/Kconfig.tpl
@@ -126,7 +126,7 @@
config TPL_TEXT_BASE
hex "Base address for the .text section of the TPL stage"
- default 0
+ default 0x0
help
The base address for the .text section of the TPL stage.
diff --git a/common/spl/Makefile b/common/spl/Makefile
index bad2bbf..4809f9c 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2012
-# Texas Instruments Incorporated - http://www.ti.com/
+# Texas Instruments Incorporated - https://www.ti.com/
# Aneesh V <aneesh@ti.com>
# Based on common/Makefile.
#
@@ -28,6 +28,7 @@
obj-$(CONFIG_$(SPL_TPL_)USB_STORAGE) += spl_usb.o
obj-$(CONFIG_$(SPL_TPL_)FS_FAT) += spl_fat.o
obj-$(CONFIG_$(SPL_TPL_)FS_EXT4) += spl_ext.o
+obj-$(CONFIG_$(SPL_TPL_)LOAD_IMX_CONTAINER) += spl_imx_container.o
obj-$(CONFIG_$(SPL_TPL_)SATA) += spl_sata.o
obj-$(CONFIG_$(SPL_TPL_)NVME) += spl_nvme.o
obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += spl_semihosting.o
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 0062f3f..732d90d 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -45,10 +45,6 @@
DECLARE_GLOBAL_DATA_PTR;
DECLARE_BINMAN_MAGIC_SYM;
-#ifndef CFG_SYS_UBOOT_START
-#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
-#endif
-
u32 *boot_params_ptr = NULL;
#if CONFIG_IS_ENABLED(BINMAN_UBOOT_SYMBOLS)
@@ -252,7 +248,7 @@
spl_image->entry_point = u_boot_pos;
spl_image->load_addr = u_boot_pos;
} else {
- spl_image->entry_point = CFG_SYS_UBOOT_START;
+ spl_image->entry_point = CONFIG_SYS_UBOOT_START;
spl_image->load_addr = CONFIG_TEXT_BASE;
}
spl_image->os = IH_OS_U_BOOT;
@@ -260,102 +256,6 @@
}
#endif
-#if CONFIG_IS_ENABLED(LOAD_FIT_FULL)
-/* Parse and load full fitImage in SPL */
-static int spl_load_fit_image(struct spl_image_info *spl_image,
- const struct legacy_img_hdr *header)
-{
- struct bootm_headers images;
- const char *fit_uname_config = NULL;
- uintptr_t fdt_hack;
- const char *uname;
- ulong fw_data = 0, dt_data = 0, img_data = 0;
- ulong fw_len = 0, dt_len = 0, img_len = 0;
- int idx, conf_noffset;
- int ret;
-
-#ifdef CONFIG_SPL_FIT_SIGNATURE
- images.verify = 1;
-#endif
- ret = fit_image_load(&images, (ulong)header,
- NULL, &fit_uname_config,
- IH_ARCH_DEFAULT, IH_TYPE_STANDALONE, -1,
- FIT_LOAD_OPTIONAL, &fw_data, &fw_len);
- if (ret >= 0) {
- printf("DEPRECATED: 'standalone = ' property.");
- printf("Please use either 'firmware =' or 'kernel ='\n");
- } else {
- ret = fit_image_load(&images, (ulong)header, NULL,
- &fit_uname_config, IH_ARCH_DEFAULT,
- IH_TYPE_FIRMWARE, -1, FIT_LOAD_OPTIONAL,
- &fw_data, &fw_len);
- }
-
- if (ret < 0) {
- ret = fit_image_load(&images, (ulong)header, NULL,
- &fit_uname_config, IH_ARCH_DEFAULT,
- IH_TYPE_KERNEL, -1, FIT_LOAD_OPTIONAL,
- &fw_data, &fw_len);
- }
-
- if (ret < 0)
- return ret;
-
- spl_image->size = fw_len;
- spl_image->entry_point = fw_data;
- spl_image->load_addr = fw_data;
- if (fit_image_get_os(header, ret, &spl_image->os))
- spl_image->os = IH_OS_INVALID;
- spl_image->name = genimg_get_os_name(spl_image->os);
-
- debug(SPL_TPL_PROMPT "payload image: %32s load addr: 0x%lx size: %d\n",
- spl_image->name, spl_image->load_addr, spl_image->size);
-
-#ifdef CONFIG_SPL_FIT_SIGNATURE
- images.verify = 1;
-#endif
- ret = fit_image_load(&images, (ulong)header, NULL, &fit_uname_config,
- IH_ARCH_DEFAULT, IH_TYPE_FLATDT, -1,
- FIT_LOAD_OPTIONAL, &dt_data, &dt_len);
- if (ret >= 0) {
- spl_image->fdt_addr = (void *)dt_data;
-
- if (spl_image->os == IH_OS_U_BOOT) {
- /* HACK: U-Boot expects FDT at a specific address */
- fdt_hack = spl_image->load_addr + spl_image->size;
- fdt_hack = (fdt_hack + 3) & ~3;
- debug("Relocating FDT to %p\n", spl_image->fdt_addr);
- memcpy((void *)fdt_hack, spl_image->fdt_addr, dt_len);
- }
- }
-
- conf_noffset = fit_conf_get_node((const void *)header,
- fit_uname_config);
- if (conf_noffset < 0)
- return 0;
-
- for (idx = 0;
- uname = fdt_stringlist_get((const void *)header, conf_noffset,
- FIT_LOADABLE_PROP, idx,
- NULL), uname;
- idx++)
- {
-#ifdef CONFIG_SPL_FIT_SIGNATURE
- images.verify = 1;
-#endif
- ret = fit_image_load(&images, (ulong)header,
- &uname, &fit_uname_config,
- IH_ARCH_DEFAULT, IH_TYPE_LOADABLE, -1,
- FIT_LOAD_OPTIONAL_NON_ZERO,
- &img_data, &img_len);
- if (ret < 0)
- return ret;
- }
-
- return 0;
-}
-#endif
-
__weak int spl_parse_board_header(struct spl_image_info *spl_image,
const struct spl_boot_device *bootdev,
const void *image_header, size_t size)
@@ -375,12 +275,14 @@
const struct spl_boot_device *bootdev,
const struct legacy_img_hdr *header)
{
-#if CONFIG_IS_ENABLED(LOAD_FIT_FULL)
- int ret = spl_load_fit_image(spl_image, header);
+ int ret;
- if (!ret)
- return ret;
-#endif
+ if (CONFIG_IS_ENABLED(LOAD_FIT_FULL)) {
+ ret = spl_load_fit_image(spl_image, header);
+
+ if (!ret)
+ return ret;
+ }
if (image_get_magic(header) == IH_MAGIC) {
int ret;
@@ -527,7 +429,7 @@
{
int ret;
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
if (setup_malloc) {
#ifdef CFG_MALLOC_F_ADDR
gd->malloc_base = CFG_MALLOC_F_ADDR;
@@ -542,17 +444,11 @@
ret);
return ret;
}
-#ifdef CONFIG_BOOTSTAGE_STASH
if (!u_boot_first_phase()) {
- const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
- CONFIG_BOOTSTAGE_STASH_SIZE);
-
- ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
+ ret = bootstage_unstash_default();
if (ret)
- debug("%s: Failed to unstash bootstage: ret=%d\n",
- __func__, ret);
+ log_debug("Failed to unstash bootstage: ret=%d\n", ret);
}
-#endif /* CONFIG_BOOTSTAGE_STASH */
bootstage_mark_name(get_bootstage_id(true),
spl_phase_name(spl_phase()));
#if CONFIG_IS_ENABLED(LOG)
@@ -747,28 +643,26 @@
BOOT_DEVICE_NONE,
BOOT_DEVICE_NONE,
};
+ typedef void __noreturn (*jump_to_image_t)(struct spl_image_info *);
+ jump_to_image_t jump_to_image = &jump_to_image_no_args;
struct spl_image_info spl_image;
- int ret;
+ int ret, os;
debug(">>" SPL_TPL_PROMPT "board_init_r()\n");
spl_set_bd();
-#if defined(CONFIG_SYS_SPL_MALLOC)
- mem_malloc_init(SYS_SPL_MALLOC_START, CONFIG_SYS_SPL_MALLOC_SIZE);
- gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-#endif
+ if (IS_ENABLED(CONFIG_SPL_SYS_MALLOC)) {
+ mem_malloc_init((ulong)map_sysmem(SPL_SYS_MALLOC_START,
+ SPL_SYS_MALLOC_SIZE),
+ SPL_SYS_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
+ }
if (!(gd->flags & GD_FLG_SPL_INIT)) {
if (spl_init())
hang();
}
-#if !defined(CONFIG_PPC) && !defined(CONFIG_ARCH_MX6)
- /*
- * timer_init() does not exist on PPC systems. The timer is initialized
- * and enabled (decrementer) in interrupt_init() here.
- */
timer_init();
-#endif
if (CONFIG_IS_ENABLED(BLOBLIST)) {
ret = bloblist_init();
if (ret) {
@@ -788,19 +682,17 @@
}
}
-#if CONFIG_IS_ENABLED(BOARD_INIT)
- spl_board_init();
-#endif
+ if (CONFIG_IS_ENABLED(BOARD_INIT))
+ spl_board_init();
-#if defined(CONFIG_SPL_WATCHDOG) && CONFIG_IS_ENABLED(WDT)
- initr_watchdog();
-#endif
+ if (IS_ENABLED(CONFIG_SPL_WATCHDOG) && CONFIG_IS_ENABLED(WDT))
+ initr_watchdog();
if (IS_ENABLED(CONFIG_SPL_OS_BOOT) || CONFIG_IS_ENABLED(HANDOFF) ||
IS_ENABLED(CONFIG_SPL_ATF))
dram_init_banksize();
- if (CONFIG_IS_ENABLED(PCI)) {
+ if (CONFIG_IS_ENABLED(PCI) && !(gd->flags & GD_FLG_DM_DEAD)) {
ret = pci_init();
if (ret)
puts(SPL_TPL_PROMPT "Cannot initialize PCI\n");
@@ -818,9 +710,8 @@
}
memset(&spl_image, '\0', sizeof(spl_image));
-#ifdef CONFIG_SYS_SPL_ARGS_ADDR
- spl_image.arg = (void *)CONFIG_SYS_SPL_ARGS_ADDR;
-#endif
+ if (IS_ENABLED(CONFIG_SPL_OS_BOOT))
+ spl_image.arg = (void *)SPL_PAYLOAD_ARGS_ADDR;
spl_image.boot_device = BOOT_DEVICE_NONE;
board_boot_order(spl_boot_list);
@@ -837,66 +728,39 @@
}
spl_perform_fixups(&spl_image);
- if (CONFIG_IS_ENABLED(HANDOFF)) {
- ret = write_spl_handoff();
- if (ret)
- printf(SPL_TPL_PROMPT
- "SPL hand-off write failed (err=%d)\n", ret);
- }
- if (CONFIG_IS_ENABLED(BLOBLIST)) {
- ret = bloblist_finish();
- if (ret)
- printf("Warning: Failed to finish bloblist (ret=%d)\n",
- ret);
- }
- switch (spl_image.os) {
- case IH_OS_U_BOOT:
+ os = spl_image.os;
+ if (os == IH_OS_U_BOOT) {
debug("Jumping to %s...\n", spl_phase_name(spl_next_phase()));
- break;
-#if CONFIG_IS_ENABLED(ATF)
- case IH_OS_ARM_TRUSTED_FIRMWARE:
+ } else if (CONFIG_IS_ENABLED(ATF) && os == IH_OS_ARM_TRUSTED_FIRMWARE) {
debug("Jumping to U-Boot via ARM Trusted Firmware\n");
- spl_fixup_fdt(spl_image.fdt_addr);
- spl_invoke_atf(&spl_image);
- break;
-#endif
-#if CONFIG_IS_ENABLED(OPTEE_IMAGE)
- case IH_OS_TEE:
+ spl_fixup_fdt(spl_image_fdt_addr(&spl_image));
+ jump_to_image = &spl_invoke_atf;
+ } else if (CONFIG_IS_ENABLED(OPTEE_IMAGE) && os == IH_OS_TEE) {
debug("Jumping to U-Boot via OP-TEE\n");
- spl_board_prepare_for_optee(spl_image.fdt_addr);
- jump_to_image_optee(&spl_image);
- break;
-#endif
-#if CONFIG_IS_ENABLED(OPENSBI)
- case IH_OS_OPENSBI:
+ spl_board_prepare_for_optee(spl_image_fdt_addr(&spl_image));
+ jump_to_image = &jump_to_image_optee;
+ } else if (CONFIG_IS_ENABLED(OPENSBI) && os == IH_OS_OPENSBI) {
debug("Jumping to U-Boot via RISC-V OpenSBI\n");
- spl_invoke_opensbi(&spl_image);
- break;
-#endif
-#if CONFIG_IS_ENABLED(OS_BOOT)
- case IH_OS_LINUX:
+ jump_to_image = &spl_invoke_opensbi;
+ } else if (CONFIG_IS_ENABLED(OS_BOOT) && os == IH_OS_LINUX) {
debug("Jumping to Linux\n");
-#if defined(CONFIG_SYS_SPL_ARGS_ADDR)
- spl_fixup_fdt((void *)CONFIG_SYS_SPL_ARGS_ADDR);
-#endif
+ if (IS_ENABLED(CONFIG_SPL_OS_BOOT))
+ spl_fixup_fdt((void *)SPL_PAYLOAD_ARGS_ADDR);
spl_board_prepare_for_linux();
- jump_to_image_linux(&spl_image);
-#endif
- default:
+ jump_to_image = &jump_to_image_linux;
+ } else {
debug("Unsupported OS image.. Jumping nevertheless..\n");
}
-#if CONFIG_VAL(SYS_MALLOC_F_LEN) && !defined(CONFIG_SYS_SPL_MALLOC_SIZE)
- debug("SPL malloc() used 0x%lx bytes (%ld KB)\n", gd->malloc_ptr,
- gd->malloc_ptr / 1024);
-#endif
+ if (CONFIG_IS_ENABLED(SYS_MALLOC_F) &&
+ !IS_ENABLED(CONFIG_SPL_SYS_MALLOC_SIZE))
+ debug("SPL malloc() used 0x%lx bytes (%ld KB)\n",
+ gd_malloc_ptr(), gd_malloc_ptr() / 1024);
+
bootstage_mark_name(get_bootstage_id(false), "end phase");
-#ifdef CONFIG_BOOTSTAGE_STASH
- ret = bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
- CONFIG_BOOTSTAGE_STASH_SIZE);
+ ret = bootstage_stash_default();
if (ret)
debug("Failed to stash bootstage: err=%d\n", ret);
-#endif
if (IS_ENABLED(CONFIG_SPL_VIDEO_REMOVE)) {
struct udevice *dev;
@@ -910,9 +774,21 @@
dev->name, rc);
}
}
+ if (CONFIG_IS_ENABLED(HANDOFF)) {
+ ret = write_spl_handoff();
+ if (ret)
+ printf(SPL_TPL_PROMPT
+ "SPL hand-off write failed (err=%d)\n", ret);
+ }
+ if (CONFIG_IS_ENABLED(BLOBLIST)) {
+ ret = bloblist_finish();
+ if (ret)
+ printf("Warning: Failed to finish bloblist (ret=%d)\n",
+ ret);
+ }
spl_board_prepare_for_boot();
- jump_to_image_no_args(&spl_image);
+ jump_to_image(&spl_image);
}
/*
@@ -987,7 +863,7 @@
if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE))
spl_relocate_stack_check();
-#if defined(CONFIG_SPL_SYS_MALLOC_SIMPLE) && CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if defined(CONFIG_SPL_SYS_MALLOC_SIMPLE) && CONFIG_IS_ENABLED(SYS_MALLOC_F)
if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) {
debug("SPL malloc() before relocation used 0x%lx bytes (%ld KB)\n",
gd->malloc_ptr, gd->malloc_ptr / 1024);
diff --git a/common/spl/spl_atf.c b/common/spl/spl_atf.c
index 2c10252..3bdd013 100644
--- a/common/spl/spl_atf.c
+++ b/common/spl/spl_atf.c
@@ -187,10 +187,10 @@
__asm__ __volatile__("msr DAIF, %x0\n\t" : : "r" (daif) : "memory");
}
-typedef void (*atf_entry_t)(struct bl31_params *params, void *plat_params);
+typedef void __noreturn (*atf_entry_t)(struct bl31_params *params, void *plat_params);
-static void bl31_entry(uintptr_t bl31_entry, uintptr_t bl32_entry,
- uintptr_t bl33_entry, uintptr_t fdt_addr)
+static void __noreturn bl31_entry(uintptr_t bl31_entry, uintptr_t bl32_entry,
+ uintptr_t bl33_entry, uintptr_t fdt_addr)
{
atf_entry_t atf_entry = (atf_entry_t)bl31_entry;
void *bl31_params;
@@ -251,7 +251,7 @@
return val;
}
-void spl_invoke_atf(struct spl_image_info *spl_image)
+void __noreturn spl_invoke_atf(struct spl_image_info *spl_image)
{
uintptr_t bl32_entry = 0;
uintptr_t bl33_entry = CONFIG_TEXT_BASE;
diff --git a/common/spl/spl_blk_fs.c b/common/spl/spl_blk_fs.c
index ea5d1a5..63825d6 100644
--- a/common/spl/spl_blk_fs.c
+++ b/common/spl/spl_blk_fs.c
@@ -9,6 +9,7 @@
#include <spl.h>
#include <image.h>
#include <fs.h>
+#include <asm/io.h>
struct blk_dev {
const char *ifname;
@@ -29,7 +30,8 @@
return ret;
}
- ret = fs_read(load->filename, (ulong)buf, file_offset, size, &actlen);
+ ret = fs_read(load->filename, virt_to_phys(buf), file_offset, size,
+ &actlen);
if (ret < 0) {
printf("spl: error reading image %s. Err - %d\n",
load->filename, ret);
@@ -69,7 +71,7 @@
goto out;
}
- ret = fs_read(filename, (ulong)header, 0,
+ ret = fs_read(filename, virt_to_phys(header), 0,
sizeof(struct legacy_img_hdr), &actlen);
if (ret) {
printf("spl: unable to read file %s. Err - %d\n", filename,
diff --git a/common/spl/spl_dfu.c b/common/spl/spl_dfu.c
index 5728d43..8a779da 100644
--- a/common/spl/spl_dfu.c
+++ b/common/spl/spl_dfu.c
@@ -15,6 +15,7 @@
#include <g_dnl.h>
#include <usb.h>
#include <dfu.h>
+#include <linux/printk.h>
static int run_dfu(int usb_index, char *interface, char *devstring)
{
diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index 2bf3434..af836ca 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -2,6 +2,7 @@
#include <common.h>
#include <env.h>
+#include <mapmem.h>
#include <part.h>
#include <spl.h>
#include <asm/u-boot.h>
@@ -53,7 +54,8 @@
goto end;
}
- err = ext4fs_read((char *)spl_image->load_addr, 0, filelen, &actlen);
+ err = ext4fs_read(map_sysmem(spl_image->load_addr, filelen), 0, filelen,
+ &actlen);
end:
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
@@ -97,7 +99,7 @@
puts("spl: ext4fs_open failed\n");
goto defaults;
}
- err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, 0, filelen, &actlen);
+ err = ext4fs_read((void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR, 0, filelen, &actlen);
if (err < 0) {
printf("spl: error reading image %s, err - %d, falling back to default\n",
file, err);
@@ -127,7 +129,7 @@
if (err < 0)
puts("spl: ext4fs_open failed\n");
- err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, 0, filelen, &actlen);
+ err = ext4fs_read((void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR, 0, filelen, &actlen);
if (err < 0) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: error reading image %s, err - %d\n",
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index f8a5b80..014074f 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -11,6 +11,7 @@
#include <common.h>
#include <env.h>
#include <log.h>
+#include <mapmem.h>
#include <spl.h>
#include <asm/u-boot.h>
#include <fat.h>
@@ -20,6 +21,11 @@
static int fat_registered;
+void spl_fat_force_reregister(void)
+{
+ fat_registered = 0;
+}
+
static int spl_register_fat_device(struct blk_desc *block_dev, int partition)
{
int err = 0;
@@ -74,11 +80,13 @@
if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL) &&
image_get_magic(header) == FDT_MAGIC) {
- err = file_fat_read(filename, (void *)CONFIG_SYS_LOAD_ADDR, 0);
+ err = file_fat_read(filename,
+ map_sysmem(CONFIG_SYS_LOAD_ADDR, 0), 0);
if (err <= 0)
goto end;
err = spl_parse_image_header(spl_image, bootdev,
- (struct legacy_img_hdr *)CONFIG_SYS_LOAD_ADDR);
+ map_sysmem(CONFIG_SYS_LOAD_ADDR,
+ err));
if (err == -EAGAIN)
return err;
if (err == 0)
@@ -99,8 +107,8 @@
if (err)
goto end;
- err = file_fat_read(filename,
- (u8 *)(uintptr_t)spl_image->load_addr, 0);
+ err = file_fat_read(filename, map_sysmem(spl_image->load_addr,
+ spl_image->size), 0);
}
end:
@@ -128,7 +136,7 @@
#if defined(CONFIG_SPL_ENV_SUPPORT) && defined(CONFIG_SPL_OS_BOOT)
file = env_get("falcon_args_file");
if (file) {
- err = file_fat_read(file, (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0);
+ err = file_fat_read(file, (void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR, 0);
if (err <= 0) {
printf("spl: error reading image %s, err - %d, falling back to default\n",
file, err);
@@ -153,7 +161,7 @@
#endif
err = file_fat_read(CONFIG_SPL_FS_LOAD_ARGS_NAME,
- (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0);
+ (void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR, 0);
if (err <= 0) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: error reading image %s, err - %d\n",
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 730639f..70d8d59 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -16,7 +16,9 @@
#include <sysinfo.h>
#include <asm/cache.h>
#include <asm/global_data.h>
+#include <asm/io.h>
#include <linux/libfdt.h>
+#include <linux/printk.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -43,7 +45,7 @@
for (child = fdt_first_subnode(fit, node); child >= 0;
child = fdt_next_subnode(fit, child)) {
int len;
- const char *desc = fdt_getprop(fit, child, "description", &len);
+ const char *desc = fdt_getprop(fit, child, FIT_DESC_PROP, &len);
if (!desc)
continue;
@@ -207,7 +209,7 @@
}
/**
- * spl_load_fit_image(): load the image described in a certain FIT node
+ * load_simple_fit(): load the image described in a certain FIT node
* @info: points to information about the device to load data from
* @sector: the start sector of the FIT image on the device
* @ctx: points to the FIT context structure
@@ -220,9 +222,9 @@
*
* Return: 0 on success or a negative error number.
*/
-static int spl_load_fit_image(struct spl_load_info *info, ulong sector,
- const struct spl_fit_info *ctx, int node,
- struct spl_image_info *image_info)
+static int load_simple_fit(struct spl_load_info *info, ulong sector,
+ const struct spl_fit_info *ctx, int node,
+ struct spl_image_info *image_info)
{
int offset;
size_t length;
@@ -239,14 +241,14 @@
bool external_data = false;
if (IS_ENABLED(CONFIG_SPL_FPGA) ||
- (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP))) {
+ (IS_ENABLED(CONFIG_SPL_OS_BOOT) && spl_decompression_enabled())) {
if (fit_image_get_type(fit, node, &type))
puts("Cannot get image type.\n");
else
debug("%s ", genimg_get_type_name(type));
}
- if (IS_ENABLED(CONFIG_SPL_GZIP)) {
+ if (spl_decompression_enabled()) {
fit_image_get_comp(fit, node, &image_comp);
debug("%s ", genimg_get_comp_name(image_comp));
}
@@ -281,7 +283,11 @@
return 0;
}
- src_ptr = map_sysmem(ALIGN(load_addr, ARCH_DMA_MINALIGN), len);
+ if (spl_decompression_enabled() &&
+ (image_comp == IH_COMP_GZIP || image_comp == IH_COMP_LZMA))
+ src_ptr = map_sysmem(ALIGN(CONFIG_SYS_LOAD_ADDR, ARCH_DMA_MINALIGN), len);
+ else
+ src_ptr = map_sysmem(ALIGN(load_addr, ARCH_DMA_MINALIGN), len);
length = len;
overhead = get_aligned_image_overhead(info, offset);
@@ -326,6 +332,16 @@
return -EIO;
}
length = size;
+ } else if (IS_ENABLED(CONFIG_SPL_LZMA) && image_comp == IH_COMP_LZMA) {
+ size = CONFIG_SYS_BOOTM_LEN;
+ ulong loadEnd;
+
+ if (image_decomp(IH_COMP_LZMA, CONFIG_SYS_LOAD_ADDR, 0, 0,
+ load_ptr, src, length, size, &loadEnd)) {
+ puts("Uncompressing error\n");
+ return -EIO;
+ }
+ length = loadEnd - CONFIG_SYS_LOAD_ADDR;
} else {
memcpy(load_ptr, src, length);
}
@@ -351,12 +367,18 @@
case IH_OS_U_BOOT:
return true;
case IH_OS_LINUX:
- return IS_ENABLED(CONFIG_SPL_OS_BOOT);
+ return IS_ENABLED(CONFIG_SPL_OS_BOOT) ||
+ IS_ENABLED(CONFIG_SPL_OPENSBI);
default:
return false;
}
}
+__weak int board_spl_fit_append_fdt_skip(const char *name)
+{
+ return 0; /* Do not skip */
+}
+
static int spl_fit_append_fdt(struct spl_image_info *spl_image,
struct spl_load_info *info, ulong sector,
const struct spl_fit_info *ctx)
@@ -373,26 +395,32 @@
/* Figure out which device tree the board wants to use */
node = spl_fit_get_image_node(ctx, FIT_FDT_PROP, index++);
if (node < 0) {
+ size_t size;
+
debug("%s: cannot find FDT node\n", __func__);
/*
* U-Boot did not find a device tree inside the FIT image. Use
* the U-Boot device tree instead.
*/
- if (gd->fdt_blob)
- memcpy((void *)image_info.load_addr, gd->fdt_blob,
- fdt_totalsize(gd->fdt_blob));
- else
+ if (!gd->fdt_blob)
return node;
+
+ /*
+ * Make the load-address of the FDT available for the SPL
+ * framework
+ */
+ size = fdt_totalsize(gd->fdt_blob);
+ spl_image->fdt_addr = map_sysmem(image_info.load_addr, size);
+ memcpy(spl_image->fdt_addr, gd->fdt_blob, size);
} else {
- ret = spl_load_fit_image(info, sector, ctx, node,
- &image_info);
+ ret = load_simple_fit(info, sector, ctx, node, &image_info);
if (ret < 0)
return ret;
+
+ spl_image->fdt_addr = phys_to_virt(image_info.load_addr);
}
- /* Make the load-address of the FDT available for the SPL framework */
- spl_image->fdt_addr = map_sysmem(image_info.load_addr, 0);
if (CONFIG_IS_ENABLED(FIT_IMAGE_TINY))
return 0;
@@ -400,11 +428,23 @@
void *tmpbuffer = NULL;
for (; ; index++) {
- node = spl_fit_get_image_node(ctx, FIT_FDT_PROP, index);
- if (node == -E2BIG) {
+ const char *str;
+
+ ret = spl_fit_get_image_name(ctx, FIT_FDT_PROP, index, &str);
+ if (ret == -E2BIG) {
debug("%s: No additional FDT node\n", __func__);
+ ret = 0;
break;
- } else if (node < 0) {
+ } else if (ret < 0) {
+ continue;
+ }
+
+ ret = board_spl_fit_append_fdt_skip(str);
+ if (ret)
+ continue;
+
+ node = fdt_subnode_offset(ctx->fit, ctx->images_node, str);
+ if (node < 0) {
debug("%s: unable to find FDT node %d\n",
__func__, index);
continue;
@@ -425,8 +465,8 @@
__func__);
}
image_info.load_addr = (ulong)tmpbuffer;
- ret = spl_load_fit_image(info, sector, ctx,
- node, &image_info);
+ ret = load_simple_fit(info, sector, ctx, node,
+ &image_info);
if (ret < 0)
break;
@@ -476,10 +516,11 @@
node = spl_fit_get_image_node(ctx, "loadables", index);
ret = fdt_record_loadable(blob, index, name, image->load_addr,
- image->size, image->entry_point,
- fdt_getprop(ctx->fit, node, "type", NULL),
- fdt_getprop(ctx->fit, node, "os", NULL),
- fdt_getprop(ctx->fit, node, "arch", NULL));
+ image->size, image->entry_point,
+ fdt_getprop(ctx->fit, node, FIT_TYPE_PROP, NULL),
+ fdt_getprop(ctx->fit, node, FIT_OS_PROP, NULL),
+ fdt_getprop(ctx->fit, node, FIT_ARCH_PROP, NULL));
+
return ret;
}
@@ -530,7 +571,7 @@
buf = malloc_cache_aligned(size);
if (!buf) {
pr_err("Could not get FIT buffer of %lu bytes\n", (ulong)size);
- pr_err("\tcheck CONFIG_SYS_SPL_MALLOC_SIZE\n");
+ pr_err("\tcheck CONFIG_SPL_SYS_MALLOC_SIZE\n");
buf = spl_get_load_buffer(0, size);
}
return buf;
@@ -616,7 +657,7 @@
warn_deprecated("'fpga' property in config node. Use 'loadables'");
/* Load the image and set up the fpga_image structure */
- ret = spl_load_fit_image(info, sector, ctx, node, &fpga_image);
+ ret = load_simple_fit(info, sector, ctx, node, &fpga_image);
if (ret) {
printf("%s: Cannot load the FPGA: %i\n", __func__, ret);
return ret;
@@ -741,7 +782,7 @@
}
/* Load the image and set up the spl_image structure */
- ret = spl_load_fit_image(info, sector, &ctx, node, spl_image);
+ ret = load_simple_fit(info, sector, &ctx, node, spl_image);
if (ret)
return ret;
@@ -782,7 +823,7 @@
continue;
image_info.load_addr = 0;
- ret = spl_load_fit_image(info, sector, &ctx, node, &image_info);
+ ret = load_simple_fit(info, sector, &ctx, node, &image_info);
if (ret < 0) {
printf("%s: can't load image loadables index %d (ret = %d)\n",
__func__, index, ret);
@@ -816,7 +857,7 @@
}
/*
- * If a platform does not provide CFG_SYS_UBOOT_START, U-Boot's
+ * If a platform does not provide CONFIG_SYS_UBOOT_START, U-Boot's
* Makefile will set it to 0 and it will end up as the entry point
* here. What it actually means is: use the load address.
*/
@@ -827,3 +868,97 @@
return 0;
}
+
+/* Parse and load full fitImage in SPL */
+int spl_load_fit_image(struct spl_image_info *spl_image,
+ const struct legacy_img_hdr *header)
+{
+ struct bootm_headers images;
+ const char *fit_uname_config = NULL;
+ uintptr_t fdt_hack;
+ const char *uname;
+ ulong fw_data = 0, dt_data = 0, img_data = 0;
+ ulong fw_len = 0, dt_len = 0, img_len = 0;
+ int idx, conf_noffset;
+ int ret;
+
+#ifdef CONFIG_SPL_FIT_SIGNATURE
+ images.verify = 1;
+#endif
+ ret = fit_image_load(&images, virt_to_phys((void *)header),
+ NULL, &fit_uname_config,
+ IH_ARCH_DEFAULT, IH_TYPE_STANDALONE, -1,
+ FIT_LOAD_OPTIONAL, &fw_data, &fw_len);
+ if (ret >= 0) {
+ printf("DEPRECATED: 'standalone = ' property.");
+ printf("Please use either 'firmware =' or 'kernel ='\n");
+ } else {
+ ret = fit_image_load(&images, virt_to_phys((void *)header),
+ NULL, &fit_uname_config, IH_ARCH_DEFAULT,
+ IH_TYPE_FIRMWARE, -1, FIT_LOAD_OPTIONAL,
+ &fw_data, &fw_len);
+ }
+
+ if (ret < 0) {
+ ret = fit_image_load(&images, virt_to_phys((void *)header),
+ NULL, &fit_uname_config, IH_ARCH_DEFAULT,
+ IH_TYPE_KERNEL, -1, FIT_LOAD_OPTIONAL,
+ &fw_data, &fw_len);
+ }
+
+ if (ret < 0)
+ return ret;
+
+ spl_image->size = fw_len;
+ spl_image->load_addr = fw_data;
+ if (fit_image_get_entry(header, ret, &spl_image->entry_point))
+ spl_image->entry_point = fw_data;
+ if (fit_image_get_os(header, ret, &spl_image->os))
+ spl_image->os = IH_OS_INVALID;
+ spl_image->name = genimg_get_os_name(spl_image->os);
+
+ debug(SPL_TPL_PROMPT "payload image: %32s load addr: 0x%lx size: %d\n",
+ spl_image->name, spl_image->load_addr, spl_image->size);
+
+#ifdef CONFIG_SPL_FIT_SIGNATURE
+ images.verify = 1;
+#endif
+ ret = fit_image_load(&images, virt_to_phys((void *)header), NULL,
+ &fit_uname_config, IH_ARCH_DEFAULT, IH_TYPE_FLATDT,
+ -1, FIT_LOAD_OPTIONAL, &dt_data, &dt_len);
+ if (ret >= 0) {
+ spl_image->fdt_addr = (void *)dt_data;
+
+ if (spl_image->os == IH_OS_U_BOOT) {
+ /* HACK: U-Boot expects FDT at a specific address */
+ fdt_hack = spl_image->load_addr + spl_image->size;
+ fdt_hack = (fdt_hack + 3) & ~3;
+ debug("Relocating FDT to %p\n", spl_image->fdt_addr);
+ memcpy((void *)fdt_hack, spl_image->fdt_addr, dt_len);
+ }
+ }
+
+ conf_noffset = fit_conf_get_node((const void *)header,
+ fit_uname_config);
+ if (conf_noffset < 0)
+ return 0;
+
+ for (idx = 0;
+ uname = fdt_stringlist_get((const void *)header, conf_noffset,
+ FIT_LOADABLE_PROP, idx,
+ NULL), uname;
+ idx++) {
+#ifdef CONFIG_SPL_FIT_SIGNATURE
+ images.verify = 1;
+#endif
+ ret = fit_image_load(&images, (ulong)header,
+ &uname, &fit_uname_config,
+ IH_ARCH_DEFAULT, IH_TYPE_LOADABLE, -1,
+ FIT_LOAD_OPTIONAL_NON_ZERO,
+ &img_data, &img_len);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-imx/parse-container.c b/common/spl/spl_imx_container.c
similarity index 91%
rename from arch/arm/mach-imx/parse-container.c
rename to common/spl/spl_imx_container.c
index e2a9e2b..127802f 100644
--- a/arch/arm/mach-imx/parse-container.c
+++ b/common/spl/spl_imx_container.c
@@ -3,12 +3,14 @@
* Copyright 2018-2021 NXP
*/
+#define LOG_CATEGORY LOGC_ARCH
#include <common.h>
#include <stdlib.h>
#include <errno.h>
+#include <imx_container.h>
#include <log.h>
+#include <mapmem.h>
#include <spl.h>
-#include <asm/mach-imx/image.h>
#ifdef CONFIG_AHAB_BOOT
#include <asm/mach-imx/ahab.h>
#endif
@@ -45,7 +47,8 @@
debug("%s: container: %p sector: %lu sectors: %u\n", __func__,
container, sector, sectors);
if (info->read(info, sector, sectors,
- (void *)images[image_index].entry) != sectors) {
+ map_sysmem(images[image_index].dst,
+ images[image_index].size)) != sectors) {
printf("%s wrong\n", __func__);
return NULL;
}
@@ -84,14 +87,14 @@
goto end;
}
- if (container->tag != 0x87 && container->version != 0x0) {
- printf("Wrong container header");
+ if (!valid_container_hdr(container)) {
+ log_err("Wrong container header\n");
ret = -ENOENT;
goto end;
}
if (!container->num_images) {
- printf("Wrong container, no image found");
+ log_err("Wrong container, no image found\n");
ret = -ENOENT;
goto end;
}
diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c
index 095443c..51656fb 100644
--- a/common/spl/spl_legacy.c
+++ b/common/spl/spl_legacy.c
@@ -7,6 +7,7 @@
#include <image.h>
#include <log.h>
#include <malloc.h>
+#include <mapmem.h>
#include <asm/sections.h>
#include <spl.h>
@@ -19,7 +20,7 @@
static void spl_parse_legacy_validate(uintptr_t start, uintptr_t size)
{
uintptr_t spl_start = (uintptr_t)_start;
- uintptr_t spl_end = (uintptr_t)_image_binary_end;
+ uintptr_t spl_end = (uintptr_t)&_image_binary_end;
uintptr_t end = start + size;
if ((start >= spl_start && start < spl_end) ||
@@ -129,7 +130,7 @@
dataptr += sizeof(*hdr);
load->read(load, dataptr, spl_image->size,
- (void *)(unsigned long)spl_image->load_addr);
+ map_sysmem(spl_image->load_addr, spl_image->size));
break;
case IH_COMP_LZMA:
@@ -148,7 +149,8 @@
}
load->read(load, dataptr, spl_image->size, src);
- ret = lzmaBuffToBuffDecompress((void *)spl_image->load_addr,
+ ret = lzmaBuffToBuffDecompress(map_sysmem(spl_image->load_addr,
+ spl_image->size),
&lzma_len, src, spl_image->size);
if (ret) {
printf("LZMA decompression error: %d\n", ret);
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index a665091..82689da 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <dm.h>
#include <log.h>
+#include <mapmem.h>
#include <part.h>
#include <spl.h>
#include <linux/compiler.h>
@@ -16,6 +17,7 @@
#include <errno.h>
#include <mmc.h>
#include <image.h>
+#include <imx_container.h>
static int mmc_load_legacy(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev,
@@ -45,7 +47,8 @@
count = blk_dread(mmc_get_blk_desc(mmc),
sector + image_offset_sectors,
image_size_sectors,
- (void *)(ulong)spl_image->load_addr);
+ map_sysmem(spl_image->load_addr,
+ image_size_sectors * mmc->read_bl_len));
debug("read %x sectors to %lx\n", image_size_sectors,
spl_image->load_addr);
if (count != image_size_sectors)
@@ -108,7 +111,8 @@
load.bl_len = mmc->read_bl_len;
load.read = h_spl_load_read;
ret = spl_load_simple_fit(spl_image, &load, sector, header);
- } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) {
+ } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) &&
+ valid_container_hdr((void *)header)) {
struct spl_load_info load;
load.dev = mmc;
@@ -229,13 +233,13 @@
{
int ret;
-#if CONFIG_VAL(SYS_MMCSD_RAW_MODE_ARGS_SECTOR)
+#if defined(CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR)
unsigned long count;
count = blk_dread(mmc_get_blk_desc(mmc),
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS,
- (void *) CONFIG_SYS_SPL_ARGS_ADDR);
+ (void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR);
if (count != CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
puts("mmc_load_image_raw_os: mmc block read error\n");
@@ -361,10 +365,22 @@
}
#endif
+unsigned long __weak arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
+ unsigned long raw_sect)
+{
+ return raw_sect;
+}
+
+unsigned long __weak board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
+ unsigned long raw_sect)
+{
+ return arch_spl_mmc_get_uboot_raw_sector(mmc, raw_sect);
+}
+
unsigned long __weak spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
unsigned long raw_sect)
{
- return raw_sect;
+ return board_spl_mmc_get_uboot_raw_sector(mmc, raw_sect);
}
int default_spl_mmc_emmc_boot_partition(struct mmc *mmc)
@@ -396,18 +412,24 @@
#if !CONFIG_IS_ENABLED(BLK)
block_dev = &mmc->block_dev;
#else
- block_dev = dev_get_uclass_plat(mmc->dev);
+ block_dev = mmc_get_blk_desc(mmc);
#endif
return block_dev->devnum;
}
+static struct mmc *mmc;
+
+void spl_mmc_clear_cache(void)
+{
+ mmc = NULL;
+}
+
int spl_mmc_load(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev,
const char *filename,
int raw_part,
unsigned long raw_sect)
{
- static struct mmc *mmc;
u32 boot_mode;
int err = 0;
__maybe_unused int part = 0;
diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index dc45204..07916be 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -7,6 +7,7 @@
#include <config.h>
#include <fdt_support.h>
#include <image.h>
+#include <imx_container.h>
#include <log.h>
#include <spl.h>
#include <asm/io.h>
@@ -99,7 +100,8 @@
load.bl_len = bl_len;
load.read = spl_nand_fit_read;
return spl_load_simple_fit(spl_image, &load, offset / bl_len, header);
- } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) {
+ } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) &&
+ valid_container_hdr((void *)header)) {
struct spl_load_info load;
load.dev = NULL;
@@ -159,11 +161,11 @@
CONFIG_CMD_SPL_WRITE_SIZE,
(void *)CONFIG_TEXT_BASE);
/* copy to destintion */
- for (dst = (int *)CONFIG_SYS_SPL_ARGS_ADDR,
- src = (int *)CONFIG_TEXT_BASE;
- src < (int *)(CONFIG_TEXT_BASE +
- CONFIG_CMD_SPL_WRITE_SIZE);
- src++, dst++) {
+ for (dst = (int *)CONFIG_SPL_PAYLOAD_ARGS_ADDR,
+ src = (int *)CONFIG_TEXT_BASE;
+ src < (int *)(CONFIG_TEXT_BASE +
+ CONFIG_CMD_SPL_WRITE_SIZE);
+ src++, dst++) {
writel(readl(src), dst);
}
diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c
index b2c901b..f01d4df 100644
--- a/common/spl/spl_net.c
+++ b/common/spl/spl_net.c
@@ -11,6 +11,7 @@
#include <errno.h>
#include <image.h>
#include <log.h>
+#include <mapmem.h>
#include <spl.h>
#include <net.h>
#include <linux/libfdt.h>
@@ -21,14 +22,15 @@
{
debug("%s: sector %lx, count %lx, buf %lx\n",
__func__, sector, count, (ulong)buf);
- memcpy(buf, (void *)(image_load_addr + sector), count);
+ memcpy(buf, map_sysmem(image_load_addr + sector, count), count);
return count;
}
static int spl_net_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
- struct legacy_img_hdr *header = (struct legacy_img_hdr *)image_load_addr;
+ struct legacy_img_hdr *header = map_sysmem(image_load_addr,
+ sizeof(*header));
int rv;
env_init();
@@ -62,7 +64,9 @@
if (rv)
return rv;
- memcpy((void *)spl_image->load_addr, header, spl_image->size);
+ memcpy(map_sysmem(spl_image->load_addr, spl_image->size),
+ map_sysmem(image_load_addr, spl_image->size),
+ spl_image->size);
}
return rv;
diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c
index 5b65b96..236b071 100644
--- a/common/spl/spl_nor.c
+++ b/common/spl/spl_nor.c
@@ -5,7 +5,9 @@
#include <common.h>
#include <image.h>
+#include <imx_container.h>
#include <log.h>
+#include <mapmem.h>
#include <spl.h>
static ulong spl_nor_load_read(struct spl_load_info *load, ulong sector,
@@ -13,7 +15,7 @@
{
debug("%s: sector %lx, count %lx, buf %p\n",
__func__, sector, count, buf);
- memcpy(buf, (void *)sector, count);
+ memcpy(buf, map_sysmem(sector, count), count);
return count;
}
@@ -26,7 +28,7 @@
static int spl_nor_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
- __maybe_unused const struct legacy_img_hdr *header;
+ struct legacy_img_hdr *header;
__maybe_unused struct spl_load_info load;
/*
@@ -41,7 +43,7 @@
* Load Linux from its location in NOR flash to its defined
* location in SDRAM
*/
- header = (const struct legacy_img_hdr *)CONFIG_SYS_OS_BASE;
+ header = (void *)CONFIG_SYS_OS_BASE;
#ifdef CONFIG_SPL_LOAD_FIT
if (image_get_magic(header) == FDT_MAGIC) {
int ret;
@@ -54,8 +56,8 @@
CONFIG_SYS_OS_BASE,
(void *)header);
-#if defined CONFIG_SYS_SPL_ARGS_ADDR && defined CONFIG_CMD_SPL_NOR_OFS
- memcpy((void *)CONFIG_SYS_SPL_ARGS_ADDR,
+#if defined CONFIG_SPL_PAYLOAD_ARGS_ADDR && defined CONFIG_CMD_SPL_NOR_OFS
+ memcpy((void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR,
(void *)CONFIG_CMD_SPL_NOR_OFS,
CONFIG_CMD_SPL_WRITE_SIZE);
#endif
@@ -74,8 +76,8 @@
(void *)(CONFIG_SYS_OS_BASE +
sizeof(struct legacy_img_hdr)),
spl_image->size);
-#ifdef CONFIG_SYS_SPL_ARGS_ADDR
- spl_image->arg = (void *)CONFIG_SYS_SPL_ARGS_ADDR;
+#ifdef CONFIG_SPL_PAYLOAD_ARGS_ADDR
+ spl_image->arg = (void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR;
#endif
return 0;
@@ -91,8 +93,8 @@
* Load real U-Boot from its location in NOR flash to its
* defined location in SDRAM
*/
+ header = map_sysmem(spl_nor_get_uboot_base(), sizeof(*header));
#ifdef CONFIG_SPL_LOAD_FIT
- header = (const struct legacy_img_hdr *)spl_nor_get_uboot_base();
if (image_get_magic(header) == FDT_MAGIC) {
debug("Found FIT format U-Boot\n");
load.bl_len = 1;
@@ -102,7 +104,8 @@
(void *)header);
}
#endif
- if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) {
+ if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) &&
+ valid_container_hdr((void *)header)) {
load.bl_len = 1;
load.read = spl_nor_load_read;
return spl_load_imx_container(spl_image, &load,
@@ -111,14 +114,11 @@
/* Legacy image handling */
if (IS_ENABLED(CONFIG_SPL_LEGACY_IMAGE_FORMAT)) {
- struct legacy_img_hdr hdr;
-
load.bl_len = 1;
load.read = spl_nor_load_read;
- spl_nor_load_read(&load, spl_nor_get_uboot_base(), sizeof(hdr), &hdr);
return spl_load_legacy_img(spl_image, bootdev, &load,
spl_nor_get_uboot_base(),
- &hdr);
+ header);
}
return -EINVAL;
diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
index e2aaa46..9801d38 100644
--- a/common/spl/spl_opensbi.c
+++ b/common/spl/spl_opensbi.c
@@ -15,12 +15,13 @@
#include <asm/smp.h>
#include <opensbi.h>
#include <linux/libfdt.h>
+#include <linux/printk.h>
DECLARE_GLOBAL_DATA_PTR;
struct fw_dynamic_info opensbi_info;
-static int spl_opensbi_find_uboot_node(void *blob, int *uboot_node)
+static int spl_opensbi_find_os_node(void *blob, int *uboot_node, int os_type)
{
int fit_images_node, node;
const char *fit_os;
@@ -34,7 +35,7 @@
if (!fit_os)
continue;
- if (genimg_get_os_id(fit_os) == IH_OS_U_BOOT) {
+ if (genimg_get_os_id(fit_os) == os_type) {
*uboot_node = node;
return 0;
}
@@ -45,8 +46,9 @@
void __noreturn spl_invoke_opensbi(struct spl_image_info *spl_image)
{
- int ret, uboot_node;
- ulong uboot_entry;
+ int ret, os_node;
+ ulong os_entry;
+ int os_type;
typedef void __noreturn (*opensbi_entry_t)(ulong hartid, ulong dtb, ulong info);
opensbi_entry_t opensbi_entry;
@@ -55,22 +57,32 @@
hang();
}
- /* Find U-Boot image in /fit-images */
- ret = spl_opensbi_find_uboot_node(spl_image->fdt_addr, &uboot_node);
+ /*
+ * Find next os image in /fit-images
+ * The next os image default is u-boot proper, once enable
+ * OpenSBI OS boot mode, the OS image should be linux.
+ */
+ if (CONFIG_IS_ENABLED(LOAD_FIT_OPENSBI_OS_BOOT))
+ os_type = IH_OS_LINUX;
+ else
+ os_type = IH_OS_U_BOOT;
+
+ ret = spl_opensbi_find_os_node(spl_image->fdt_addr, &os_node, os_type);
if (ret) {
- pr_err("Can't find U-Boot node, %d\n", ret);
+ pr_err("Can't find %s node for opensbi, %d\n",
+ genimg_get_os_name(os_type), ret);
hang();
}
/* Get U-Boot entry point */
- ret = fit_image_get_entry(spl_image->fdt_addr, uboot_node, &uboot_entry);
+ ret = fit_image_get_entry(spl_image->fdt_addr, os_node, &os_entry);
if (ret)
- ret = fit_image_get_load(spl_image->fdt_addr, uboot_node, &uboot_entry);
+ ret = fit_image_get_load(spl_image->fdt_addr, os_node, &os_entry);
/* Prepare opensbi_info object */
opensbi_info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE;
opensbi_info.version = FW_DYNAMIC_INFO_VERSION;
- opensbi_info.next_addr = uboot_entry;
+ opensbi_info.next_addr = os_entry;
opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S;
opensbi_info.options = CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS;
opensbi_info.boot_hart = gd->arch.boot_hart;
diff --git a/common/spl/spl_ram.c b/common/spl/spl_ram.c
index 93cf420..4158ed1 100644
--- a/common/spl/spl_ram.c
+++ b/common/spl/spl_ram.c
@@ -20,12 +20,16 @@
static ulong spl_ram_load_read(struct spl_load_info *load, ulong sector,
ulong count, void *buf)
{
- ulong addr;
+ ulong addr = 0;
debug("%s: sector %lx, count %lx, buf %lx\n",
__func__, sector, count, (ulong)buf);
- addr = (ulong)CONFIG_SPL_LOAD_FIT_ADDRESS + sector;
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) {
+ addr = IF_ENABLED_INT(CONFIG_SPL_LOAD_FIT,
+ CONFIG_SPL_LOAD_FIT_ADDRESS);
+ }
+ addr += sector;
if (CONFIG_IS_ENABLED(IMAGE_PRE_LOAD))
addr += image_load_offset;
@@ -38,20 +42,23 @@
struct spl_boot_device *bootdev)
{
struct legacy_img_hdr *header;
+ ulong addr = 0;
int ret;
- header = (struct legacy_img_hdr *)CONFIG_SPL_LOAD_FIT_ADDRESS;
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) {
+ addr = IF_ENABLED_INT(CONFIG_SPL_LOAD_FIT,
+ CONFIG_SPL_LOAD_FIT_ADDRESS);
+ }
if (CONFIG_IS_ENABLED(IMAGE_PRE_LOAD)) {
- unsigned long addr = (unsigned long)header;
ret = image_pre_load(addr);
if (ret)
return ret;
addr += image_load_offset;
- header = (struct legacy_img_hdr *)addr;
}
+ header = map_sysmem(addr, 0);
#if CONFIG_IS_ENABLED(DFU)
if (bootdev->boot_device == BOOT_DEVICE_DFU)
@@ -84,7 +91,7 @@
u_boot_pos = (ulong)spl_get_load_buffer(-sizeof(*header),
sizeof(*header));
}
- header = (struct legacy_img_hdr *)map_sysmem(u_boot_pos, 0);
+ header = map_sysmem(u_boot_pos, 0);
ret = spl_parse_image_header(spl_image, bootdev, header);
}
diff --git a/common/spl/spl_sdp.c b/common/spl/spl_sdp.c
index cc4fb4f..9143c27 100644
--- a/common/spl/spl_sdp.c
+++ b/common/spl/spl_sdp.c
@@ -10,14 +10,18 @@
#include <usb.h>
#include <g_dnl.h>
#include <sdp.h>
+#include <linux/printk.h>
static int spl_sdp_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
- int ret;
const int controller_index = CONFIG_SPL_SDP_USB_DEV;
+ struct udevice *udc;
+ int ret;
- usb_gadget_initialize(controller_index);
+ ret = udc_device_get_by_index(controller_index, &udc);
+ if (ret)
+ return ret;
board_usb_init(controller_index, USB_INIT_DEVICE);
@@ -25,13 +29,13 @@
ret = g_dnl_register("usb_dnl_sdp");
if (ret) {
pr_err("SDP dnl register failed: %d\n", ret);
- return ret;
+ goto err_detach;
}
- ret = sdp_init(controller_index);
+ ret = sdp_init(udc);
if (ret) {
pr_err("SDP init failed: %d\n", ret);
- return -ENODEV;
+ goto err_unregister;
}
/*
@@ -39,10 +43,13 @@
* or it loads a FIT image and returns it to be handled by the SPL
* code.
*/
- ret = spl_sdp_handle(controller_index, spl_image, bootdev);
+ ret = spl_sdp_handle(udc, spl_image, bootdev);
debug("SDP ended\n");
- usb_gadget_release(controller_index);
+err_unregister:
+ g_dnl_unregister();
+err_detach:
+ udc_device_put(udc);
return ret;
}
SPL_LOAD_IMAGE_METHOD("USB SDP", 0, BOOT_DEVICE_BOARD, spl_sdp_load_image);
diff --git a/common/spl/spl_semihosting.c b/common/spl/spl_semihosting.c
index 5b5e842..f7dd289 100644
--- a/common/spl/spl_semihosting.c
+++ b/common/spl/spl_semihosting.c
@@ -21,6 +21,23 @@
return 0;
}
+static ulong smh_fit_read(struct spl_load_info *load, ulong file_offset,
+ ulong size, void *buf)
+{
+ long fd;
+ ulong ret;
+
+ fd = smh_open(load->filename, MODE_READ | MODE_BINARY);
+ if (fd < 0) {
+ log_debug("could not open %s: %ld\n", load->filename, fd);
+ return 0;
+ }
+ ret = smh_read(fd, buf, size);
+ smh_close(fd);
+
+ return ret;
+}
+
static int spl_smh_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
@@ -49,6 +66,20 @@
goto out;
}
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+ image_get_magic(header) == FDT_MAGIC) {
+ struct spl_load_info load;
+
+ debug("Found FIT\n");
+ load.read = smh_fit_read;
+ load.bl_len = 1;
+ load.filename = filename;
+ load.priv = NULL;
+ smh_close(fd);
+
+ return spl_load_simple_fit(spl_image, &load, 0, header);
+ }
+
ret = spl_parse_image_header(spl_image, bootdev, header);
if (ret) {
log_debug("failed to parse image header: %d\n", ret);
diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c
index 2aff025..3ac4b1b 100644
--- a/common/spl/spl_spi.c
+++ b/common/spl/spl_spi.c
@@ -10,12 +10,15 @@
#include <common.h>
#include <image.h>
+#include <imx_container.h>
#include <log.h>
+#include <mapmem.h>
#include <spi.h>
#include <spi_flash.h>
#include <errno.h>
#include <spl.h>
#include <asm/global_data.h>
+#include <asm/io.h>
#include <dm/ofnode.h>
#if CONFIG_IS_ENABLED(OS_BOOT)
@@ -47,7 +50,7 @@
/* Read device tree. */
spi_flash_read(flash, CFG_SYS_SPI_ARGS_OFFS,
CFG_SYS_SPI_ARGS_SIZE,
- (void *)CONFIG_SYS_SPL_ARGS_ADDR);
+ (void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR);
return 0;
}
@@ -133,13 +136,16 @@
if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL) &&
image_get_magic(header) == FDT_MAGIC) {
+ u32 size = roundup(fdt_totalsize(header), 4);
+
err = spi_flash_read(flash, payload_offs,
- roundup(fdt_totalsize(header), 4),
- (void *)CONFIG_SYS_LOAD_ADDR);
+ size,
+ map_sysmem(CONFIG_SYS_LOAD_ADDR,
+ size));
if (err)
return err;
err = spl_parse_image_header(spl_image, bootdev,
- (struct legacy_img_hdr *)CONFIG_SYS_LOAD_ADDR);
+ phys_to_virt(CONFIG_SYS_LOAD_ADDR));
} else if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
image_get_magic(header) == FDT_MAGIC) {
struct spl_load_info load;
@@ -153,7 +159,8 @@
err = spl_load_simple_fit(spl_image, &load,
payload_offs,
header);
- } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) {
+ } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) &&
+ valid_container_hdr((void *)header)) {
struct spl_load_info load;
load.dev = flash;
@@ -170,7 +177,8 @@
return err;
err = spi_flash_read(flash, payload_offs + spl_image->offset,
spl_image->size,
- (void *)spl_image->load_addr);
+ map_sysmem(spl_image->load_addr,
+ spl_image->size));
}
if (IS_ENABLED(CONFIG_SPI_FLASH_SOFT_RESET)) {
err = spi_nor_remove(flash);
diff --git a/common/spl/spl_ubi.c b/common/spl/spl_ubi.c
index bcac25c..d7ab9ef 100644
--- a/common/spl/spl_ubi.c
+++ b/common/spl/spl_ubi.c
@@ -50,7 +50,7 @@
volumes[0].vol_id = CONFIG_SPL_UBI_LOAD_KERNEL_ID;
volumes[0].load_addr = (void *)CONFIG_SYS_LOAD_ADDR;
volumes[1].vol_id = CONFIG_SPL_UBI_LOAD_ARGS_ID;
- volumes[1].load_addr = (void *)CONFIG_SYS_SPL_ARGS_ADDR;
+ volumes[1].load_addr = (void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR;
ret = ubispl_load_volumes(&info, volumes, 2);
if (!ret) {
diff --git a/common/spl/spl_xip.c b/common/spl/spl_xip.c
index 77c23ba..959915f 100644
--- a/common/spl/spl_xip.c
+++ b/common/spl/spl_xip.c
@@ -14,7 +14,7 @@
{
#if CONFIG_IS_ENABLED(OS_BOOT)
if (!spl_start_uboot()) {
- spl_image->arg = (void *)CONFIG_SYS_SPL_ARGS_ADDR;
+ spl_image->arg = (void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR;
spl_image->name = "Linux";
spl_image->os = IH_OS_LINUX;
spl_image->load_addr = CONFIG_SYS_LOAD_ADDR;
diff --git a/common/stdio.c b/common/stdio.c
index 894cbd3..e3354f0 100644
--- a/common/stdio.c
+++ b/common/stdio.c
@@ -259,7 +259,7 @@
int stdio_deregister_dev(struct stdio_dev *dev, int force)
{
struct list_head *pos;
- char temp_names[3][16];
+ char temp_names[3][STDIO_NAME_LEN];
int i;
/* get stdio devices (ListRemoveItem changes the dev list) */
@@ -272,8 +272,8 @@
/* Device is assigned -> report error */
return -EBUSY;
}
- memcpy(&temp_names[i][0], stdio_devices[i]->name,
- sizeof(temp_names[i]));
+ strlcpy(&temp_names[i][0], stdio_devices[i]->name,
+ sizeof(temp_names[i]));
}
list_del(&dev->list);
@@ -293,18 +293,6 @@
int stdio_init_tables(void)
{
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- /* already relocated for current ARM implementation */
- ulong relocation_offset = gd->reloc_off;
- int i;
-
- /* relocate device name pointers */
- for (i = 0; i < (sizeof (stdio_names) / sizeof (char *)); ++i) {
- stdio_names[i] = (char *) (((ulong) stdio_names[i]) +
- relocation_offset);
- }
-#endif /* CONFIG_NEEDS_MANUAL_RELOC */
-
/* Initialize the list */
INIT_LIST_HEAD(&devs.list);
diff --git a/common/update.c b/common/update.c
index 3502713..ec302ca 100644
--- a/common/update.c
+++ b/common/update.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <cpu_func.h>
#include <image.h>
+#include <linux/printk.h>
#include <command.h>
#include <env.h>
diff --git a/common/usb_hub.c b/common/usb_hub.c
index 85c0822..70279f3 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -395,6 +395,13 @@
break;
}
+ /*
+ * USB 2.0 7.1.7.5: devices must be able to accept a SetAddress()
+ * request (refer to Section 11.24.2 and Section 9.4 respectively)
+ * after the reset recovery time 10 ms
+ */
+ mdelay(10);
+
#if CONFIG_IS_ENABLED(DM_USB)
struct udevice *child;
diff --git a/common/usb_storage.c b/common/usb_storage.c
index 8577422..774d5bd 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -102,6 +102,7 @@
trans_reset transport_reset; /* reset routine */
trans_cmnd transport; /* transport routine */
unsigned short max_xfer_blk; /* maximum transfer blocks */
+ bool cmd12; /* use 12-byte commands (RBC/UFI) */
};
#if !CONFIG_IS_ENABLED(BLK)
@@ -219,8 +220,8 @@
snprintf(str, sizeof(str), "lun%d", lun);
ret = blk_create_devicef(udev->dev, "usb_storage_blk", str,
- UCLASS_USB, usb_max_devs, 512, 0,
- &dev);
+ UCLASS_USB, usb_max_devs,
+ DEFAULT_BLKSZ, 0, &dev);
if (ret) {
debug("Cannot bind driver\n");
return ret;
@@ -359,7 +360,7 @@
{
int i;
printf("SRB: len %d datalen 0x%lX\n ", pccb->cmdlen, pccb->datalen);
- for (i = 0; i < 12; i++)
+ for (i = 0; i < pccb->cmdlen; i++)
printf("%02X ", pccb->cmd[i]);
printf("\n");
}
@@ -898,7 +899,7 @@
psrb->cmd[4] = 18;
psrb->datalen = 18;
psrb->pdata = &srb->sense_buf[0];
- psrb->cmdlen = 12;
+ psrb->cmdlen = us->cmd12 ? 12 : 6;
/* issue the command */
result = usb_stor_CB_comdat(psrb, us);
debug("auto request returned %d\n", result);
@@ -999,7 +1000,7 @@
srb->cmd[1] = srb->lun << 5;
srb->cmd[4] = 36;
srb->datalen = 36;
- srb->cmdlen = 12;
+ srb->cmdlen = ss->cmd12 ? 12 : 6;
i = ss->transport(srb, ss);
debug("inquiry returns %d\n", i);
if (i == 0)
@@ -1024,7 +1025,7 @@
srb->cmd[4] = 18;
srb->datalen = 18;
srb->pdata = &srb->sense_buf[0];
- srb->cmdlen = 12;
+ srb->cmdlen = ss->cmd12 ? 12 : 6;
ss->transport(srb, ss);
debug("Request Sense returned %02X %02X %02X\n",
srb->sense_buf[2], srb->sense_buf[12],
@@ -1042,7 +1043,7 @@
srb->cmd[0] = SCSI_TST_U_RDY;
srb->cmd[1] = srb->lun << 5;
srb->datalen = 0;
- srb->cmdlen = 12;
+ srb->cmdlen = ss->cmd12 ? 12 : 6;
if (ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD) {
ss->flags |= USB_READY;
return 0;
@@ -1074,7 +1075,7 @@
srb->cmd[0] = SCSI_RD_CAPAC;
srb->cmd[1] = srb->lun << 5;
srb->datalen = 8;
- srb->cmdlen = 12;
+ srb->cmdlen = ss->cmd12 ? 12 : 10;
if (ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD)
return 0;
} while (retry--);
@@ -1094,7 +1095,7 @@
srb->cmd[5] = ((unsigned char) (start)) & 0xff;
srb->cmd[7] = ((unsigned char) (blocks >> 8)) & 0xff;
srb->cmd[8] = (unsigned char) blocks & 0xff;
- srb->cmdlen = 12;
+ srb->cmdlen = ss->cmd12 ? 12 : 10;
debug("read10: start %lx blocks %x\n", start, blocks);
return ss->transport(srb, ss);
}
@@ -1111,7 +1112,7 @@
srb->cmd[5] = ((unsigned char) (start)) & 0xff;
srb->cmd[7] = ((unsigned char) (blocks >> 8)) & 0xff;
srb->cmd[8] = (unsigned char) blocks & 0xff;
- srb->cmdlen = 12;
+ srb->cmdlen = ss->cmd12 ? 12 : 10;
debug("write10: start %lx blocks %x\n", start, blocks);
return ss->transport(srb, ss);
}
@@ -1417,6 +1418,11 @@
printf("Sorry, protocol %d not yet supported.\n", ss->subclass);
return 0;
}
+
+ /* UFI uses 12-byte commands (like RBC, unlike SCSI) */
+ if (ss->subclass == US_SC_UFI)
+ ss->cmd12 = true;
+
if (ss->ep_int) {
/* we had found an interrupt endpoint, prepare irq pipe
* set up the IRQ pipe and handler
diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig
index b76f31b..02f1249 100644
--- a/configs/10m50_defconfig
+++ b/configs/10m50_defconfig
@@ -11,8 +11,8 @@
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SYS_LOAD_ADDR=0xcc000000
CONFIG_ENV_ADDR=0xF4080000
-CONFIG_FIT=y
CONFIG_SYS_MONITOR_BASE=0xCFF80000
+CONFIG_FIT=y
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/3c120_defconfig b/configs/3c120_defconfig
index 13da353..6bd5471 100644
--- a/configs/3c120_defconfig
+++ b/configs/3c120_defconfig
@@ -11,8 +11,8 @@
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SYS_LOAD_ADDR=0xd4000000
CONFIG_ENV_ADDR=0xE2880000
-CONFIG_FIT=y
CONFIG_SYS_MONITOR_BASE=0xD7F80000
+CONFIG_FIT=y
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index df4fdfa..57e91d0 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -7,7 +7,6 @@
CONFIG_DRAM_EMR1=4
CONFIG_SYS_CLK_FREQ=912000000
CONFIG_I2C1_ENABLE=y
-CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
index be49e93..44770ff 100644
--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
@@ -8,7 +8,6 @@
CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
-CONFIG_SATAPWR="PC3"
CONFIG_SPL_SPI_SUNXI=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index 43cd28c..e10660c 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -7,7 +7,6 @@
CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
-CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig
index 7c77f38..4ed666a 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -5,7 +5,6 @@
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_I2C1_ENABLE=y
-CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
index 0211699..ca5869f 100644
--- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig
+++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
@@ -7,7 +7,6 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_I2C1_ENABLE=y
CONFIG_VIDEO_VGA=y
-CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index 895e8db..db4270f 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -7,7 +7,6 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_I2C1_ENABLE=y
CONFIG_VIDEO_VGA=y
-CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index 5bcc9f9..ac90047 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -7,7 +7,6 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_USB0_VBUS_DET="PH5"
-CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
index e588109..00a9814 100644
--- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
+++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
@@ -8,7 +8,6 @@
CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
-CONFIG_SATAPWR="PC3"
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig
index 592a79a..f4ae3ae 100644
--- a/configs/A20-Olimex-SOM204-EVB_defconfig
+++ b/configs/A20-Olimex-SOM204-EVB_defconfig
@@ -7,7 +7,6 @@
CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
-CONFIG_SATAPWR="PC3"
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig
index a5fe76a..2cc7bbb 100644
--- a/configs/Bananapi_M2_Ultra_defconfig
+++ b/configs/Bananapi_M2_Ultra_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN8I_R40=y
CONFIG_DRAM_CLK=576
-CONFIG_MACPWR="PA17"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB1_VBUS_PIN="PH23"
CONFIG_USB2_VBUS_PIN="PH23"
diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
index 6c2a1f6..f4910ba 100644
--- a/configs/Bananapi_defconfig
+++ b/configs/Bananapi_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
-CONFIG_MACPWR="PH23"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
index 94fd747..02be897 100644
--- a/configs/Bananapro_defconfig
+++ b/configs/Bananapro_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
-CONFIG_MACPWR="PH23"
CONFIG_USB1_VBUS_PIN="PH0"
CONFIG_USB2_VBUS_PIN="PH1"
CONFIG_VIDEO_COMPOSITE=y
diff --git a/configs/CMPC885_defconfig b/configs/CMPC885_defconfig
index 24592a2..0c33dad 100644
--- a/configs/CMPC885_defconfig
+++ b/configs/CMPC885_defconfig
@@ -22,7 +22,6 @@
CONFIG_SYS_SCCR_MASK=0x00000000
CONFIG_SYS_DER=0x2002000F
CONFIG_FIT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_FLUSH_STDIN=y
@@ -30,6 +29,7 @@
CONFIG_AUTOBOOT_ENCRYPTION=y
CONFIG_AUTOBOOT_STOP_STR_ENABLE=y
CONFIG_AUTOBOOT_STOP_STR_SHA256="4813494d137e1631bba301d5acab6e7bb7aa74ce1185d456565ef51d737677b2"
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run flashboot"
CONFIG_MISC_INIT_R=y
diff --git a/configs/CMPCPRO_defconfig b/configs/CMPCPRO_defconfig
index 6d7dfff..58b28f0 100644
--- a/configs/CMPCPRO_defconfig
+++ b/configs/CMPCPRO_defconfig
@@ -101,8 +101,6 @@
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
CONFIG_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=5
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_FLUSH_STDIN=y
@@ -110,6 +108,8 @@
CONFIG_AUTOBOOT_ENCRYPTION=y
CONFIG_AUTOBOOT_STOP_STR_ENABLE=y
CONFIG_AUTOBOOT_STOP_STR_SHA256="4813494d137e1631bba301d5acab6e7bb7aa74ce1185d456565ef51d737677b2"
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run flashboot"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
index 0c23368..ef4f11b 100644
--- a/configs/Cubieboard2_defconfig
+++ b/configs/Cubieboard2_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
-CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig
index 2f93a7b..d3678ad 100644
--- a/configs/Cubieboard4_defconfig
+++ b/configs/Cubieboard4_defconfig
@@ -11,6 +11,5 @@
CONFIG_USB3_VBUS_PIN="PH15"
CONFIG_AXP_GPIO=y
CONFIG_SYS_I2C_SUN8I_RSB=y
-CONFIG_DM_REGULATOR=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP809_POWER=y
diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
index 71743f7..ab3f65a 100644
--- a/configs/Cubieboard_defconfig
+++ b/configs/Cubieboard_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=480
-CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index 184f305..184143d 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -8,7 +8,6 @@
CONFIG_USB0_VBUS_DET="PH22"
CONFIG_USB0_ID_DET="PH19"
CONFIG_VIDEO_VGA=y
-CONFIG_SATAPWR="PH12"
CONFIG_GMAC_TX_DELAY=1
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig
index 5d05f33..d03fa62 100644
--- a/configs/Itead_Ibox_A20_defconfig
+++ b/configs/Itead_Ibox_A20_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
-CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
index 5294608..66f57ab 100644
--- a/configs/Lamobo_R1_defconfig
+++ b/configs/Lamobo_R1_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
-CONFIG_MACPWR="PH23"
-CONFIG_SATAPWR="PB3"
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig
index e3e30a4..9eb9a918 100644
--- a/configs/Linksprite_pcDuino3_Nano_defconfig
+++ b/configs/Linksprite_pcDuino3_Nano_defconfig
@@ -6,7 +6,6 @@
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=122
CONFIG_USB1_VBUS_PIN="PH11"
-CONFIG_SATAPWR="PH2"
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
index 1fda0db..7db10e6 100644
--- a/configs/Linksprite_pcDuino3_defconfig
+++ b/configs/Linksprite_pcDuino3_defconfig
@@ -5,7 +5,6 @@
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_ZQ=122
-CONFIG_SATAPWR="PH2"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig
index 52be89d..2061eda 100644
--- a/configs/MCR3000_defconfig
+++ b/configs/MCR3000_defconfig
@@ -19,9 +19,8 @@
CONFIG_SYS_SCCR=0x00C20000
CONFIG_SYS_SCCR_MASK=0x60000000
CONFIG_SYS_DER=0x2002000F
-CONFIG_FIT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_MONITOR_BASE=0x04000000
+CONFIG_FIT=y
CONFIG_BOOTDELAY=5
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_FLUSH_STDIN=y
@@ -29,6 +28,7 @@
CONFIG_AUTOBOOT_ENCRYPTION=y
CONFIG_AUTOBOOT_STOP_STR_ENABLE=y
CONFIG_AUTOBOOT_STOP_STR_SHA256="4813494d137e1631bba301d5acab6e7bb7aa74ce1185d456565ef51d737677b2"
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run flashboot"
# CONFIG_HWCONFIG is not set
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index bf7370f..33f0bab 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -119,9 +119,9 @@
CONFIG_FSL_SERDES=y
CONFIG_USE_UBOOTPATH=y
CONFIG_DEBUG_UART=y
+CONFIG_BOOTDELAY=6
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=6
CONFIG_BOARD_LATE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_PCI_INIT_R=y
diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig
index ebffbb2..4d3d691 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig
@@ -20,10 +20,10 @@
CONFIG_UBOOTPATH="8548cds/u-boot.bin"
CONFIG_PCIE1=y
CONFIG_PHYS_64BIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
# CONFIG_MISC_INIT_R is not set
diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
index 4ed84d0..b7f7e7b 100644
--- a/configs/MPC8548CDS_defconfig
+++ b/configs/MPC8548CDS_defconfig
@@ -19,10 +19,10 @@
CONFIG_USE_UBOOTPATH=y
CONFIG_UBOOTPATH="8548cds/u-boot.bin"
CONFIG_PCIE1=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
# CONFIG_MISC_INIT_R is not set
diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig
index 684a4fa..9acc8bd 100644
--- a/configs/MPC8548CDS_legacy_defconfig
+++ b/configs/MPC8548CDS_legacy_defconfig
@@ -20,10 +20,10 @@
CONFIG_USE_UBOOTPATH=y
CONFIG_UBOOTPATH="8548cds/u-boot.bin"
CONFIG_PCIE1=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
# CONFIG_MISC_INIT_R is not set
diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig
index f5b6d90..9ac2e48 100644
--- a/configs/Mele_A1000_defconfig
+++ b/configs/Mele_A1000_defconfig
@@ -3,7 +3,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000"
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
-CONFIG_MACPWR="PH15"
CONFIG_VIDEO_VGA=y
CONFIG_VIDEO_COMPOSITE=y
CONFIG_AHCI=y
diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig
index f0c54e2..a26677e 100644
--- a/configs/Merrii_A80_Optimus_defconfig
+++ b/configs/Merrii_A80_Optimus_defconfig
@@ -11,6 +11,5 @@
CONFIG_USB3_VBUS_PIN="PH5"
CONFIG_AXP_GPIO=y
CONFIG_SYS_I2C_SUN8I_RSB=y
-CONFIG_DM_REGULATOR=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP809_POWER=y
diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig
index c89a9a1..53edf52 100644
--- a/configs/Orangepi_defconfig
+++ b/configs/Orangepi_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
-CONFIG_MACPWR="PH23"
CONFIG_USB1_VBUS_PIN="PH26"
CONFIG_USB2_VBUS_PIN="PH22"
CONFIG_VIDEO_VGA=y
diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
index fe9ce80..ccf3267 100644
--- a/configs/Orangepi_mini_defconfig
+++ b/configs/Orangepi_mini_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
-CONFIG_MACPWR="PH23"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_USB1_VBUS_PIN="PH26"
CONFIG_USB2_VBUS_PIN="PH22"
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index 1f4b600..37a1398 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -26,12 +26,12 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
+CONFIG_TPL_SYS_MONITOR_BASE=0xD0000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_TPL_SYS_MONITOR_BASE=0xD0000000
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index 5ef7247..caf1b34 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -19,10 +19,10 @@
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_NO_PBL=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index 317499a..cc998a8 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -26,10 +26,10 @@
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_FSL_FIXED_MMC_LOCATION=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index b81971d..bb263ab 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -28,10 +28,10 @@
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SPIFLASH=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index 6a8b713..960229c 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -25,12 +25,12 @@
CONFIG_USE_UBOOTPATH=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_TPL_SYS_MONITOR_BASE=0xD0000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_TPL_SYS_MONITOR_BASE=0xD0000000
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index 037489c..78be54e 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig
@@ -18,10 +18,10 @@
CONFIG_PCIE2=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_NO_PBL=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index 859d058..c664a99 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -25,10 +25,10 @@
CONFIG_PCIE2=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_FSL_FIXED_MMC_LOCATION=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index 84f7415..2ffba7d 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -27,10 +27,10 @@
CONFIG_PCIE2=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SPIFLASH=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index 7a38a56..b9790cd 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -26,12 +26,12 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
+CONFIG_TPL_SYS_MONITOR_BASE=0xD0000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_TPL_SYS_MONITOR_BASE=0xD0000000
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index f390a72..a76c91b 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -19,10 +19,10 @@
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_NO_PBL=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index 58dc156..b6504a5 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -26,10 +26,10 @@
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_FSL_FIXED_MMC_LOCATION=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index 66acf63..14bfd97 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -28,10 +28,10 @@
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SPIFLASH=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index fa3f5fa..589fd5d 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -25,12 +25,12 @@
CONFIG_USE_UBOOTPATH=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_TPL_SYS_MONITOR_BASE=0xD0000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_TPL_SYS_MONITOR_BASE=0xD0000000
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index 2bf2041..d96b8fc 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig
@@ -18,10 +18,10 @@
CONFIG_PCIE2=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_NO_PBL=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index 2ff163b..c08089a 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -25,10 +25,10 @@
CONFIG_PCIE2=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_FSL_FIXED_MMC_LOCATION=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index eda92b6..8d5b13b 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -27,10 +27,10 @@
CONFIG_PCIE2=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SPIFLASH=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index b3c4f2f..bb459cd 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -27,12 +27,12 @@
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
CONFIG_MP=y
+CONFIG_TPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_TPL_SYS_MONITOR_BASE=0xF8F80000
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index 9a38955..55046af 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -25,13 +25,13 @@
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
CONFIG_MP=y
+CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_FSL_FIXED_MMC_LOCATION=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index b59812e..2b24877 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -27,13 +27,13 @@
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
CONFIG_MP=y
+CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_SPIFLASH=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index 46b6206..9f5e46c 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -21,10 +21,10 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_NO_PBL=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index 05ea596..e38cd0a 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -26,12 +26,12 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_MP=y
+CONFIG_TPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_TPL_SYS_MONITOR_BASE=0xF8F80000
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index 763b20a..95df450 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -24,13 +24,13 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_MP=y
+CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_FSL_FIXED_MMC_LOCATION=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index 7db19bd..b519d6c 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -26,13 +26,13 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_MP=y
+CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_SPIFLASH=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index e8f79ea..fd42057 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -20,10 +20,10 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_NO_PBL=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index ad33e90..c049927 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -26,12 +26,12 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_MP=y
+CONFIG_TPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_TPL_SYS_MONITOR_BASE=0xF8F80000
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index 24e0ede..e833bb2 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -24,13 +24,13 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_MP=y
+CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_FSL_FIXED_MMC_LOCATION=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index aa09fa1..4e7c605 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -26,13 +26,13 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_MP=y
+CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_SPIFLASH=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index e665a59..e3435da 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -20,10 +20,10 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_NO_PBL=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index 6c1017b..ea17afb 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -27,12 +27,12 @@
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
CONFIG_MP=y
+CONFIG_TPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_TPL_SYS_MONITOR_BASE=0xF8F80000
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index 3e194d1..476b3d4 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -25,13 +25,13 @@
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
CONFIG_MP=y
+CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_FSL_FIXED_MMC_LOCATION=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index 16c47b2..8a31de0 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -27,13 +27,13 @@
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
CONFIG_MP=y
+CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_SPIFLASH=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index 2c9ff67..93d22fb 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -21,10 +21,10 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_NO_PBL=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index a7f562b..46d60f3 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -26,12 +26,12 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_MP=y
+CONFIG_TPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_TPL_SYS_MONITOR_BASE=0xF8F80000
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index 6f5316d..6076b54 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -24,13 +24,13 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_MP=y
+CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_FSL_FIXED_MMC_LOCATION=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index 9fa1a39..46e8d1e 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -26,13 +26,13 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_MP=y
+CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
CONFIG_SPIFLASH=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index 2a1a7ac..5eaf70b 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -20,10 +20,10 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_NO_PBL=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index 4b038f0..786c826 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -23,15 +23,15 @@
CONFIG_PCIE3=y
CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/p2041rdb/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/p2041rdb/rcw_p2041rdb.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index d05d53a..7aa2634 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -23,15 +23,15 @@
CONFIG_PCIE3=y
CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/p2041rdb/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/p2041rdb/rcw_p2041rdb.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 70279c0..6862875 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -24,16 +24,16 @@
CONFIG_PCIE3=y
CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SPIFLASH=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/p2041rdb/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/p2041rdb/rcw_p2041rdb.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 6978936..4ea2b47 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -24,12 +24,12 @@
CONFIG_PCIE3=y
CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
index 5642e52..ad41dbd 100644
--- a/configs/Sinovoip_BPI_M3_defconfig
+++ b/configs/Sinovoip_BPI_M3_defconfig
@@ -12,7 +12,6 @@
CONFIG_USB0_ID_DET="PH11"
CONFIG_USB1_VBUS_PIN="PD24"
CONFIG_AXP_GPIO=y
-CONFIG_SATAPWR="PD25"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
CONFIG_PHY_REALTEK=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index 9b322c0..7c1345b 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -29,12 +29,12 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t102xrdb/t1024_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t102xrdb/t1024_nand_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index 8243cc6..cb398f7 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -29,12 +29,12 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t102xrdb/t1024_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t102xrdb/t1024_sd_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 7e89d3c..464b36b 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -31,13 +31,13 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SPIFLASH=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t102xrdb/t1024_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t102xrdb/t1024_spi_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index 0d0707e..f632684 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -23,9 +23,9 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index 7ffa2e7..a44c768 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -28,12 +28,12 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index 1add5b6..800f063 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -28,12 +28,12 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index 0902483..3fe25ec 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -30,13 +30,13 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SPIFLASH=y
CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index fe84f36..4ca833c 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -22,9 +22,9 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index db9b6c3..431c485 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -37,15 +37,15 @@
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_nand_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index a5a9eb5..eb060f4 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -37,15 +37,15 @@
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_sd_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index 7a31104..64befc5 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -32,12 +32,12 @@
# CONFIG_QIXIS_I2C_ACCESS is not set
# CONFIG_SYS_MALLOC_F is not set
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_BOARD_EARLY_INIT_R=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index e4f1cf5..5f3997a 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -39,16 +39,16 @@
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SPIFLASH=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_spi_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index 0198812..3b09789 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -31,12 +31,12 @@
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index 8e746ac..c8b0e40 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -31,12 +31,12 @@
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index b7e54b8..89e8b95 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -34,12 +34,12 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_nand_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index 098cb8e..585daeb 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -34,12 +34,12 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_sd_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index 4d94972..6c23831 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -36,13 +36,13 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SPIFLASH=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_spi_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index e1e9630..370e8e8 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -28,9 +28,9 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig
index 582c07c..fcf9c9f 100644
--- a/configs/T2080RDB_revD_NAND_defconfig
+++ b/configs/T2080RDB_revD_NAND_defconfig
@@ -35,12 +35,12 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_nand_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig
index a981775..530c5d9 100644
--- a/configs/T2080RDB_revD_SDCARD_defconfig
+++ b/configs/T2080RDB_revD_SDCARD_defconfig
@@ -35,12 +35,12 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_sd_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig
index a5638f7..42babd4 100644
--- a/configs/T2080RDB_revD_SPIFLASH_defconfig
+++ b/configs/T2080RDB_revD_SPIFLASH_defconfig
@@ -37,13 +37,13 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SPIFLASH=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_spi_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig
index d9116df..6874fb8 100644
--- a/configs/T2080RDB_revD_defconfig
+++ b/configs/T2080RDB_revD_defconfig
@@ -29,9 +29,9 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index 8d790c5..8bbba9f 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -32,12 +32,12 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index 4b63ef4..b3affca 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -26,9 +26,9 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/a3y17lte_defconfig b/configs/a3y17lte_defconfig
index 42fcd2a..043f3a0 100644
--- a/configs/a3y17lte_defconfig
+++ b/configs/a3y17lte_defconfig
@@ -1,5 +1,4 @@
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="exynos78x0-common"
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=26000000
CONFIG_ARCH_EXYNOS=y
diff --git a/configs/a5y17lte_defconfig b/configs/a5y17lte_defconfig
index 3b80536..14590f6 100644
--- a/configs/a5y17lte_defconfig
+++ b/configs/a5y17lte_defconfig
@@ -1,5 +1,4 @@
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="exynos78x0-common"
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=26000000
CONFIG_ARCH_EXYNOS=y
diff --git a/configs/a7y17lte_defconfig b/configs/a7y17lte_defconfig
index 9390e35..ccb0bf2 100644
--- a/configs/a7y17lte_defconfig
+++ b/configs/a7y17lte_defconfig
@@ -1,5 +1,4 @@
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="exynos78x0-common"
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=26000000
CONFIG_ARCH_EXYNOS=y
diff --git a/configs/ad401_defconfig b/configs/ad401_defconfig
index 31752cc..b44b9c6 100644
--- a/configs/ad401_defconfig
+++ b/configs/ad401_defconfig
@@ -51,4 +51,8 @@
CONFIG_MESON_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_MESON_SPIFC_A1=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_GADGET=y
CONFIG_WDT=y
diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
index 38ab1d0..06cd972 100644
--- a/configs/ae350_rv32_defconfig
+++ b/configs/ae350_rv32_defconfig
@@ -8,9 +8,9 @@
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AE350=y
-CONFIG_FIT=y
+CONFIG_TARGET_ANDES_AE350=y
CONFIG_SYS_MONITOR_BASE=0x88000000
+CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_DISPLAY_CPUINFO=y
diff --git a/configs/ae350_rv32_falcon_defconfig b/configs/ae350_rv32_falcon_defconfig
new file mode 100644
index 0000000..3f2993e
--- /dev/null
+++ b/configs/ae350_rv32_falcon_defconfig
@@ -0,0 +1,60 @@
+CONFIG_RISCV=y
+CONFIG_TEXT_BASE=0x01800000
+CONFIG_SYS_MALLOC_LEN=0x80000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
+CONFIG_SYS_MONITOR_LEN=786432
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000
+CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x100000
+CONFIG_TARGET_ANDES_AE350=y
+CONFIG_RISCV_SMODE=y
+# CONFIG_AVAILABLE_HARTS is not set
+CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y
+CONFIG_SYS_MONITOR_BASE=0x88000000
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=3
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_MAX_SIZE=0x100000
+CONFIG_SPL_BSS_START_ADDR=0x400000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_CACHE=y
+CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_SYS_PBSIZE=1050
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF_TEST=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_CMD_CACHE=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RETRY_COUNT=50
+CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
+CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
+CONFIG_FLASH_SHOW_PROGRESS=0
+CONFIG_SYS_CFI_FLASH_STATUS_POLL=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_ATCSPI200_SPI=y
+# CONFIG_BINMAN_FDT is not set
diff --git a/configs/ae350_rv32_falcon_xip_defconfig b/configs/ae350_rv32_falcon_xip_defconfig
new file mode 100644
index 0000000..e4f4c78
--- /dev/null
+++ b/configs/ae350_rv32_falcon_xip_defconfig
@@ -0,0 +1,61 @@
+CONFIG_RISCV=y
+CONFIG_TEXT_BASE=0x01800000
+CONFIG_SYS_MALLOC_LEN=0x80000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
+CONFIG_SPL_TEXT_BASE=0x80000000
+CONFIG_SYS_MONITOR_LEN=786432
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000
+CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x100000
+CONFIG_TARGET_ANDES_AE350=y
+CONFIG_RISCV_SMODE=y
+CONFIG_SPL_XIP=y
+CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y
+CONFIG_SYS_MONITOR_BASE=0x88000000
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=3
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_MAX_SIZE=0x100000
+CONFIG_SPL_BSS_START_ADDR=0x400000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_CACHE=y
+CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_SYS_PBSIZE=1050
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF_TEST=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_CMD_CACHE=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RETRY_COUNT=50
+CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
+CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
+CONFIG_FLASH_SHOW_PROGRESS=0
+CONFIG_SYS_CFI_FLASH_STATUS_POLL=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_ATCSPI200_SPI=y
+# CONFIG_BINMAN_FDT is not set
diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig
index b29193a..f469d5b 100644
--- a/configs/ae350_rv32_spl_defconfig
+++ b/configs/ae350_rv32_spl_defconfig
@@ -7,24 +7,25 @@
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_SYS_MONITOR_LEN=786432
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AE350=y
+CONFIG_TARGET_ANDES_AE350=y
CONFIG_RISCV_SMODE=y
# CONFIG_AVAILABLE_HARTS is not set
-CONFIG_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000
CONFIG_SYS_MONITOR_BASE=0x88000000
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_MAX_SIZE=0x100000
-CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_CACHE=y
+CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SYS_PBSIZE=1050
CONFIG_SYS_BOOTM_LEN=0x4000000
diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig
index c023b68..9672a19 100644
--- a/configs/ae350_rv32_spl_xip_defconfig
+++ b/configs/ae350_rv32_spl_xip_defconfig
@@ -8,24 +8,25 @@
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_SYS_MONITOR_LEN=786432
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AE350=y
+CONFIG_TARGET_ANDES_AE350=y
CONFIG_RISCV_SMODE=y
CONFIG_SPL_XIP=y
+CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
-CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_MAX_SIZE=0x100000
-CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_CACHE=y
+CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SYS_PBSIZE=1050
CONFIG_SYS_BOOTM_LEN=0x4000000
diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig
index 6d04936..b90200a 100644
--- a/configs/ae350_rv32_xip_defconfig
+++ b/configs/ae350_rv32_xip_defconfig
@@ -8,10 +8,10 @@
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AE350=y
+CONFIG_TARGET_ANDES_AE350=y
CONFIG_XIP=y
-CONFIG_FIT=y
CONFIG_SYS_MONITOR_BASE=0x88000000
+CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_DISPLAY_CPUINFO=y
diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
index 5b465f7..a4b9ad6 100644
--- a/configs/ae350_rv64_defconfig
+++ b/configs/ae350_rv64_defconfig
@@ -7,10 +7,10 @@
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AE350=y
+CONFIG_TARGET_ANDES_AE350=y
CONFIG_ARCH_RV64I=y
-CONFIG_FIT=y
CONFIG_SYS_MONITOR_BASE=0x88000000
+CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_DISPLAY_CPUINFO=y
diff --git a/configs/ae350_rv64_falcon_defconfig b/configs/ae350_rv64_falcon_defconfig
new file mode 100644
index 0000000..4fb83d8
--- /dev/null
+++ b/configs/ae350_rv64_falcon_defconfig
@@ -0,0 +1,60 @@
+CONFIG_RISCV=y
+CONFIG_TEXT_BASE=0x01800000
+CONFIG_SYS_MALLOC_LEN=0x80000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000
+CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x100000
+CONFIG_TARGET_ANDES_AE350=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+# CONFIG_AVAILABLE_HARTS is not set
+CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y
+CONFIG_SYS_MONITOR_BASE=0x88000000
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=3
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_MAX_SIZE=0x100000
+CONFIG_SPL_BSS_START_ADDR=0x400000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_CACHE=y
+CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_SYS_PBSIZE=1050
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF_TEST=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_CMD_CACHE=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RETRY_COUNT=50
+CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
+CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
+CONFIG_FLASH_SHOW_PROGRESS=0
+CONFIG_SYS_CFI_FLASH_STATUS_POLL=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_ATCSPI200_SPI=y
+# CONFIG_BINMAN_FDT is not set
diff --git a/configs/ae350_rv64_falcon_xip_defconfig b/configs/ae350_rv64_falcon_xip_defconfig
new file mode 100644
index 0000000..4546426
--- /dev/null
+++ b/configs/ae350_rv64_falcon_xip_defconfig
@@ -0,0 +1,61 @@
+CONFIG_RISCV=y
+CONFIG_TEXT_BASE=0x01800000
+CONFIG_SYS_MALLOC_LEN=0x80000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
+CONFIG_SPL_TEXT_BASE=0x80000000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000
+CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x100000
+CONFIG_TARGET_ANDES_AE350=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_SPL_XIP=y
+CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y
+CONFIG_SYS_MONITOR_BASE=0x88000000
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=3
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_MAX_SIZE=0x100000
+CONFIG_SPL_BSS_START_ADDR=0x400000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_CACHE=y
+CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_SYS_PBSIZE=1050
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF_TEST=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_CMD_CACHE=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RETRY_COUNT=50
+CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
+CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
+CONFIG_FLASH_SHOW_PROGRESS=0
+CONFIG_SYS_CFI_FLASH_STATUS_POLL=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_ATCSPI200_SPI=y
+# CONFIG_BINMAN_FDT is not set
diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig
index 3133f4b..834a0fb 100644
--- a/configs/ae350_rv64_spl_defconfig
+++ b/configs/ae350_rv64_spl_defconfig
@@ -6,25 +6,26 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AE350=y
+CONFIG_TARGET_ANDES_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
# CONFIG_AVAILABLE_HARTS is not set
-CONFIG_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000
CONFIG_SYS_MONITOR_BASE=0x88000000
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_MAX_SIZE=0x100000
-CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_CACHE=y
+CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SYS_PBSIZE=1050
CONFIG_SYS_BOOTM_LEN=0x4000000
diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig
index eb5b8e7..b52b8d7 100644
--- a/configs/ae350_rv64_spl_xip_defconfig
+++ b/configs/ae350_rv64_spl_xip_defconfig
@@ -7,25 +7,26 @@
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_SPL_TEXT_BASE=0x80000000
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AE350=y
+CONFIG_TARGET_ANDES_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_SPL_XIP=y
+CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
-CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_MAX_SIZE=0x100000
-CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_CACHE=y
+CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SYS_PBSIZE=1050
CONFIG_SYS_BOOTM_LEN=0x4000000
diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig
index 11f683f..cc5e751 100644
--- a/configs/ae350_rv64_xip_defconfig
+++ b/configs/ae350_rv64_xip_defconfig
@@ -7,11 +7,11 @@
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AE350=y
+CONFIG_TARGET_ANDES_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_XIP=y
-CONFIG_FIT=y
CONFIG_SYS_MONITOR_BASE=0x88000000
+CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_DISPLAY_CPUINFO=y
diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index 6ef3c78..16993ef 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig
@@ -14,12 +14,12 @@
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run usbboot;run mmcboot;setenv mmcdev 1; setenv bootpart 1:2; run mmcboot;run nandboot;"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MTD_SUPPORT=y
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index e581acc..5317030 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -23,8 +23,8 @@
CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_MUSB_NEW=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_NET=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index a179f1e..f048e60 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -14,14 +14,14 @@
CONFIG_SPL=y
CONFIG_TIMESTAMP=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd"
CONFIG_LOGLEVEL=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_ETH=y
# CONFIG_SPL_FS_EXT4 is not set
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index 09d5e80..9866246 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -17,14 +17,14 @@
CONFIG_SPL_SPI=y
CONFIG_TIMESTAMP=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd"
CONFIG_LOGLEVEL=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FIT_IMAGE_TINY=y
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig
index a485cc6..01d848c 100644
--- a/configs/am335x_guardian_defconfig
+++ b/configs/am335x_guardian_defconfig
@@ -17,7 +17,6 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SPL=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_ENV_OFFSET_REDUND=0x540000
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SYS_MEMTEST_START=0x80000000
@@ -32,8 +31,8 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_ETH=y
diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index a3a4ab3..b961b6c 100644
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig
@@ -14,15 +14,15 @@
CONFIG_SPL=y
CONFIG_TIMESTAMP=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd"
CONFIG_LOGLEVEL=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_MAX_SIZE=0xb0b0
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FIT_IMAGE_TINY=y
# CONFIG_SPL_ENV_SUPPORT is not set
# CONFIG_SPL_FS_EXT4 is not set
diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig
index 6e4d327..b5d8eac 100644
--- a/configs/am335x_hs_evm_uart_defconfig
+++ b/configs/am335x_hs_evm_uart_defconfig
@@ -17,15 +17,15 @@
# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_TIMESTAMP=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd"
CONFIG_LOGLEVEL=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_MAX_SIZE=0x9ab0
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FIT_IMAGE_TINY=y
# CONFIG_SPL_ENV_SUPPORT is not set
# CONFIG_SPL_FS_EXT4 is not set
diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig
index 37e1259..4dd6366 100644
--- a/configs/am335x_igep003x_defconfig
+++ b/configs/am335x_igep003x_defconfig
@@ -15,12 +15,13 @@
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_BOOTCOMMAND="run findfdt;run mmcboot;run nandboot;run netboot;"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MTD_SUPPORT=y
@@ -94,4 +95,3 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig
index e68efde..557949c 100644
--- a/configs/am335x_pdu001_defconfig
+++ b/configs/am335x_pdu001_defconfig
@@ -24,8 +24,8 @@
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_BOOTCOMMAND="run eval_boot_device;part uuid mmc ${mmc_boot}:${root_fs_partition} root_fs_partuuid;setenv bootargs console=${console} vt.global_cursor_default=0 root=PARTUUID=${root_fs_partuuid} rootfstype=ext4 rootwait rootdelay=1;fatload mmc ${mmc_boot} ${fdtaddr} ${fdtfile};fatload mmc ${mmc_boot} ${loadaddr} ${bootfile};bootz ${loadaddr} - ${fdtaddr}"
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_I2C=y
# CONFIG_SPL_NAND_SUPPORT is not set
diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig
index 85c5826..24041e2 100644
--- a/configs/am335x_shc_defconfig
+++ b/configs/am335x_shc_defconfig
@@ -32,8 +32,8 @@
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
# CONFIG_SPL_NAND_SUPPORT is not set
diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig
index 7f2d9e6..ab06034 100644
--- a/configs/am335x_shc_ict_defconfig
+++ b/configs/am335x_shc_ict_defconfig
@@ -30,8 +30,8 @@
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
# CONFIG_SPL_NAND_SUPPORT is not set
diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig
index a2ab9e1..995cbfc 100644
--- a/configs/am335x_shc_netboot_defconfig
+++ b/configs/am335x_shc_netboot_defconfig
@@ -33,8 +33,8 @@
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig
index 5933035..03db57c 100644
--- a/configs/am335x_shc_sdboot_defconfig
+++ b/configs/am335x_shc_sdboot_defconfig
@@ -33,8 +33,8 @@
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
# CONFIG_SPL_NAND_SUPPORT is not set
diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig
index 44c2301..9ba376f 100644
--- a/configs/am335x_sl50_defconfig
+++ b/configs/am335x_sl50_defconfig
@@ -23,8 +23,8 @@
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index c514b52..0a83ac9 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -21,8 +21,8 @@
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then echo SD/MMC found on device $mmcdev; if run loadbootenv; then run importbootenv; fi; echo Checking if uenvcmd is set ...; if test -n $uenvcmd; then echo Running uenvcmd ...; run uenvcmd; fi; echo Running default loadimage ...; setenv bootfile zImage; if run loadimage; then run loadfdt; run mmcboot; fi; else run nandboot; fi"
CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
@@ -32,7 +32,7 @@
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SPL_NAND_BASE=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x84000000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x84000000
CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x2a0000
CONFIG_SPL_FALCON_BOOT_MMCSD=y
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 3238620..6571afd 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -18,8 +18,8 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_MAX_SIZE=0x439e0
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_ETH=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_MTD_SUPPORT=y
diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig
index 9cafe9c..e84aed4 100644
--- a/configs/am43xx_evm_rtconly_defconfig
+++ b/configs/am43xx_evm_rtconly_defconfig
@@ -18,8 +18,8 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_MAX_SIZE=0x439e0
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_NAND_DRIVERS=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 406c0fc..0cae324 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -17,8 +17,8 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_MAX_SIZE=0x37690
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_NAND_DRIVERS=y
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index 01428ac..370ee96 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -18,14 +18,14 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_MAX_SIZE=0x36100
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_ETH=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_MTD_SUPPORT=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index d3be5a6..38b3e14 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -18,8 +18,8 @@
CONFIG_ARMV7_LPAE=y
CONFIG_AHCI=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=beagle_x15board"
CONFIG_BOOTCOMMAND="if test ${dofastboot} -eq 1; then echo Boot fastboot requested, resetting dofastboot ...;setenv dofastboot 0; saveenv;echo Booting into fastboot ...; fastboot 1;fi;if test ${boot_fit} -eq 1; then run update_to_fit;fi;run findfdt; run finduuid; run distro_bootcmd;run emmc_android_boot; "
@@ -30,8 +30,8 @@
CONFIG_ANDROID_AB=y
CONFIG_SPL_MAX_SIZE=0x7bc00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_DMA=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
# CONFIG_SPL_NAND_SUPPORT is not set
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 94ffce1..cc04390 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -21,8 +21,8 @@
CONFIG_ARMV7_LPAE=y
CONFIG_AHCI=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=beagle_x15board"
CONFIG_BOOTCOMMAND="if test ${dofastboot} -eq 1; then echo Boot fastboot requested, resetting dofastboot ...;setenv dofastboot 0; saveenv;echo Booting into fastboot ...; fastboot 1;fi;if test ${boot_fit} -eq 1; then run update_to_fit;fi;run findfdt; run finduuid; run distro_bootcmd;run emmc_android_boot; "
@@ -33,8 +33,8 @@
CONFIG_ANDROID_AB=y
CONFIG_SPL_MAX_SIZE=0x7a8b0
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_DMA=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
# CONFIG_SPL_NAND_SUPPORT is not set
diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig
index fe11169..aa5d326 100644
--- a/configs/am57xx_hs_evm_usb_defconfig
+++ b/configs/am57xx_hs_evm_usb_defconfig
@@ -23,8 +23,8 @@
CONFIG_AHCI=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=beagle_x15board"
CONFIG_BOOTCOMMAND="if test ${dofastboot} -eq 1; then echo Boot fastboot requested, resetting dofastboot ...;setenv dofastboot 0; saveenv;echo Booting into fastboot ...; fastboot 1;fi;if test ${boot_fit} -eq 1; then run update_to_fit;fi;run findfdt; run finduuid; run distro_bootcmd;run emmc_android_boot; "
@@ -35,8 +35,8 @@
CONFIG_ANDROID_AB=y
CONFIG_SPL_MAX_SIZE=0x74eb0
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_DMA=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
# CONFIG_SPL_NAND_SUPPORT is not set
diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig
index 773cf3a..d0a34c7 100644
--- a/configs/am62ax_evm_a53_defconfig
+++ b/configs/am62ax_evm_a53_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig
index 05c30cb..d52de8b 100644
--- a/configs/am62ax_evm_r5_defconfig
+++ b/configs/am62ax_evm_r5_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_F_LEN=0x9000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
@@ -36,9 +35,9 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_EARLY_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig
index d55caab..df25115 100644
--- a/configs/am62x_evm_a53_defconfig
+++ b/configs/am62x_evm_a53_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
@@ -25,11 +24,13 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
+# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;"
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb"
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80c80000
@@ -69,6 +70,7 @@
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig
index 3c5f367..9ec3d56 100644
--- a/configs/am62x_evm_r5_defconfig
+++ b/configs/am62x_evm_r5_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x08000000
CONFIG_SYS_MALLOC_F_LEN=0x9000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -43,10 +42,10 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
@@ -92,6 +91,7 @@
CONFIG_K3_SEC_PROXY=y
CONFIG_SPL_MISC=y
CONFIG_ESM_K3=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
index 718ad17..20b101a 100644
--- a/configs/am64x_evm_a53_defconfig
+++ b/configs/am64x_evm_a53_defconfig
@@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
@@ -31,8 +30,9 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;"
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x180000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -41,8 +41,8 @@
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig
index b501c17..0f9757b 100644
--- a/configs/am64x_evm_r5_defconfig
+++ b/configs/am64x_evm_r5_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x80000
CONFIG_SPL_GPIO=y
@@ -44,10 +43,10 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index 4301553..4d95e3b 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -32,19 +32,18 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;"
CONFIG_LOGLEVEL=7
-CONFIG_CONSOLE_MUX=y
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80a00000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig
index d5196c2..b892f2e 100644
--- a/configs/am65x_evm_r5_defconfig
+++ b/configs/am65x_evm_r5_defconfig
@@ -40,10 +40,10 @@
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
@@ -118,6 +118,8 @@
CONFIG_TI_SCI_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_DM_REGULATOR_GPIO=y
CONFIG_DM_REGULATOR_TPS62360=y
diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig
index 88f68aa..f610b2d 100644
--- a/configs/am65x_evm_r5_usbdfu_defconfig
+++ b/configs/am65x_evm_r5_usbdfu_defconfig
@@ -37,10 +37,10 @@
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/am65x_evm_r5_usbmsc_defconfig b/configs/am65x_evm_r5_usbmsc_defconfig
index b6adcf6..57a0e72 100644
--- a/configs/am65x_evm_r5_usbmsc_defconfig
+++ b/configs/am65x_evm_r5_usbmsc_defconfig
@@ -36,10 +36,10 @@
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig
deleted file mode 100644
index 3f9626e..0000000
--- a/configs/am65x_hs_evm_a53_defconfig
+++ /dev/null
@@ -1,158 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SOC_K3_AM654=y
-CONFIG_TARGET_AM654_A53_EVM=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0x680000
-CONFIG_DM_GPIO=y
-CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board"
-CONFIG_SPL_TEXT_BASE=0x80080000
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_DM_RESET=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_ENV_OFFSET_REDUND=0x6A0000
-CONFIG_SPL_FS_FAT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-# CONFIG_PSCI_RESET is not set
-CONFIG_PCI=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_fit_${boot}; run get_overlaystring; run run_fit"
-CONFIG_LOGLEVEL=7
-CONFIG_CONSOLE_MUX=y
-CONFIG_SPL_MAX_SIZE=0x58000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x80a00000
-CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
-CONFIG_SPL_DMA=y
-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
-CONFIG_SPL_I2C=y
-CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER_DOMAIN=y
-# CONFIG_SPL_SPI_FLASH_TINY is not set
-CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_REMOTEPROC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TIME=y
-CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs)"
-CONFIG_CMD_UBI=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_MMC_ENV_PART=1
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_DFU_SF=y
-CONFIG_SYS_DFU_DATA_BUF_SIZE=0x20000
-CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
-CONFIG_DMA_CHANNELS=y
-CONFIG_TI_K3_NAVSS_UDMA=y
-CONFIG_TI_SCI_PROTOCOL=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_DM_MAILBOX=y
-CONFIG_K3_SEC_PROXY=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ADMA=y
-CONFIG_SPL_MMC_SDHCI_ADMA=y
-CONFIG_MMC_SDHCI_AM654=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHY_TI_DP83867=y
-CONFIG_PHY_FIXED=y
-CONFIG_E1000=y
-CONFIG_CMD_E1000=y
-CONFIG_TI_AM65_CPSW_NUSS=y
-CONFIG_PCI_KEYSTONE=y
-CONFIG_PHY=y
-CONFIG_AM654_PHY=y
-CONFIG_OMAP_USB2_PHY=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_GENERIC is not set
-CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_GENERIC is not set
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
-CONFIG_REMOTEPROC_TI_K3_R5F=y
-CONFIG_RESET_TI_SCI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SOC_DEVICE=y
-CONFIG_SOC_DEVICE_TI_K3=y
-CONFIG_SOC_TI=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_TI_SCI=y
-CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0x6162
-CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am65x_hs_evm_r5_defconfig b/configs/am65x_hs_evm_r5_defconfig
deleted file mode 100644
index 0c7b53c..0000000
--- a/configs/am65x_hs_evm_r5_defconfig
+++ /dev/null
@@ -1,135 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x55000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SOC_K3_AM654=y
-CONFIG_K3_EARLY_CONS=y
-CONFIG_TARGET_AM654_R5_EVM=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c7effc
-CONFIG_ENV_SIZE=0x20000
-CONFIG_DM_GPIO=y
-CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
-CONFIG_SPL_TEXT_BASE=0x41c00000
-CONFIG_DM_RESET=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_FS_FAT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_USE_BOOTCOMMAND=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_MAX_SIZE=0x58000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x41c7effc
-CONFIG_SPL_BSS_MAX_SIZE=0xc00
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
-CONFIG_SPL_EARLY_BSS=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
-CONFIG_SPL_DMA=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
-# CONFIG_SPL_SPI_FLASH_TINY is not set
-CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
-CONFIG_DMA_CHANNELS=y
-CONFIG_TI_K3_NAVSS_UDMA=y
-CONFIG_TI_SCI_PROTOCOL=y
-CONFIG_DA8XX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_DM_MAILBOX=y
-CONFIG_K3_SEC_PROXY=y
-CONFIG_K3_AVS0=y
-CONFIG_MMC_SDHCI=y
-CONFIG_SPL_MMC_SDHCI_ADMA=y
-CONFIG_MMC_SDHCI_AM654=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_GENERIC is not set
-CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_GENERIC is not set
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
-CONFIG_DM_REGULATOR=y
-CONFIG_SPL_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPL_DM_REGULATOR_GPIO=y
-CONFIG_DM_REGULATOR_TPS62360=y
-CONFIG_RAM=y
-CONFIG_SPL_RAM=y
-CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
-CONFIG_RESET_TI_SCI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SOC_DEVICE=y
-CONFIG_SOC_DEVICE_TI_K3=y
-CONFIG_SOC_TI=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_TI_SCI=y
-CONFIG_TIMER=y
-CONFIG_SPL_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig
index c668cef..d11a31e 100644
--- a/configs/apalis-imx8_defconfig
+++ b/configs/apalis-imx8_defconfig
@@ -20,9 +20,9 @@
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-apalis${variant}-${fdt_board}.dtb"
CONFIG_LOG=y
@@ -65,6 +65,7 @@
CONFIG_BOOTCOUNT_ENV=y
CONFIG_CLK_IMX8=y
CONFIG_CPU=y
+CONFIG_GPIO_HOG=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig
index 6c80834..eca326c 100644
--- a/configs/apalis-tk1_defconfig
+++ b/configs/apalis-tk1_defconfig
@@ -17,8 +17,8 @@
CONFIG_PCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=1
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="setenv fdtfile ${soc}-${fdt_module}-${fdt_board}.dtb && run distro_bootcmd"
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
@@ -28,10 +28,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Apalis TK1 # "
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_CBSIZE=1024
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 6214b44..aa9cf77 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -39,7 +39,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_DMA=y
CONFIG_SPL_I2C=y
CONFIG_SYS_PROMPT="Apalis iMX6 # "
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index d902fc1..b2d9254 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -23,10 +23,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Apalis T30 # "
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_CBSIZE=1024
diff --git a/configs/apple_m1_defconfig b/configs/apple_m1_defconfig
index 7555609..b868d0e 100644
--- a/configs/apple_m1_defconfig
+++ b/configs/apple_m1_defconfig
@@ -16,9 +16,10 @@
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_DWC3=y
CONFIG_USB_KEYBOARD=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_NO_FB_CLEAR=y
CONFIG_VIDEO_SIMPLE=y
-# CONFIG_GENERATE_SMBIOS_TABLE is not set
+# CONFIG_SMBIOS is not set
CONFIG_LMB_MAX_REGIONS=64
diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig
index 8c32b4b..6cfb5a7 100644
--- a/configs/arbel_evb_defconfig
+++ b/configs/arbel_evb_defconfig
@@ -58,6 +58,7 @@
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/axm_defconfig b/configs/axm_defconfig
index d7d14cf..f9c0214 100644
--- a/configs/axm_defconfig
+++ b/configs/axm_defconfig
@@ -44,10 +44,10 @@
# CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x20ba0000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x460000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x20ba0000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x460000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_RAW_ONLY=y
CONFIG_SPL_NAND_DRIVERS=y
diff --git a/configs/bananapi-cm4-cm4io_defconfig b/configs/bananapi-cm4-cm4io_defconfig
index bb43cc4..116147f 100644
--- a/configs/bananapi-cm4-cm4io_defconfig
+++ b/configs/bananapi-cm4-cm4io_defconfig
@@ -17,12 +17,17 @@
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=32
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -37,6 +42,7 @@
CONFIG_SARADC_MESON=y
CONFIG_BUTTON=y
CONFIG_BUTTON_ADC=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_MDIO=y
diff --git a/configs/bananapi-m2-pro_defconfig b/configs/bananapi-m2-pro_defconfig
index 4f8cec9..755bccb 100644
--- a/configs/bananapi-m2-pro_defconfig
+++ b/configs/bananapi-m2-pro_defconfig
@@ -16,12 +16,17 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=32
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -33,6 +38,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ADC=y
CONFIG_SARADC_MESON=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_MDIO=y
@@ -50,6 +56,7 @@
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/bananapi-m2s_defconfig b/configs/bananapi-m2s_defconfig
index 3dd8ddc..af8dace 100644
--- a/configs/bananapi-m2s_defconfig
+++ b/configs/bananapi-m2s_defconfig
@@ -18,12 +18,17 @@
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=32
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -36,6 +41,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ADC=y
CONFIG_SARADC_MESON=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_MDIO=y
@@ -55,6 +61,7 @@
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/bananapi-m5_defconfig b/configs/bananapi-m5_defconfig
index 696d2fc..6de5d5f 100644
--- a/configs/bananapi-m5_defconfig
+++ b/configs/bananapi-m5_defconfig
@@ -16,12 +16,17 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=32
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -33,6 +38,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ADC=y
CONFIG_SARADC_MESON=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_MDIO=y
diff --git a/configs/bananapi_m1_plus_defconfig b/configs/bananapi_m1_plus_defconfig
index 0fbb619..a432a01 100644
--- a/configs/bananapi_m1_plus_defconfig
+++ b/configs/bananapi_m1_plus_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
-CONFIG_MACPWR="PH23"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
diff --git a/configs/bananapi_m2_plus_h3_defconfig b/configs/bananapi_m2_plus_h3_defconfig
index 26ced59..a8f9b50 100644
--- a/configs/bananapi_m2_plus_h3_defconfig
+++ b/configs/bananapi_m2_plus_h3_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
-CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SUN8I_EMAC=y
diff --git a/configs/bananapi_m2_plus_h5_defconfig b/configs/bananapi_m2_plus_h5_defconfig
index fb6c945..1634f62 100644
--- a/configs/bananapi_m2_plus_h5_defconfig
+++ b/configs/bananapi_m2_plus_h5_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=672
-CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SUN8I_EMAC=y
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index a44c9b7..f1dec69 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -25,7 +25,6 @@
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
@@ -47,7 +46,6 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
diff --git a/configs/bcmns_defconfig b/configs/bcmns_defconfig
index 593edaa..2d488fd 100644
--- a/configs/bcmns_defconfig
+++ b/configs/bcmns_defconfig
@@ -11,11 +11,11 @@
CONFIG_SYS_LOAD_ADDR=0x00008000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
# CONFIG_BOOTSTD is not set
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=1
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Boot Northstar system in %d seconds\n"
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run bootcmd_dlink_dir8xxl"
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index 7684ae6..a4d299e 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -21,10 +21,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra30 (Beaver) # "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2084
diff --git a/configs/beelink-gsking-x_defconfig b/configs/beelink-gsking-x_defconfig
index c022097..99e36e9 100644
--- a/configs/beelink-gsking-x_defconfig
+++ b/configs/beelink-gsking-x_defconfig
@@ -17,12 +17,17 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=32
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -32,6 +37,7 @@
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/beelink-gt1-ultimate_defconfig b/configs/beelink-gt1-ultimate_defconfig
index c0d22c4..1313dde 100644
--- a/configs/beelink-gt1-ultimate_defconfig
+++ b/configs/beelink-gt1-ultimate_defconfig
@@ -16,6 +16,10 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
@@ -23,6 +27,7 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_ADC=y
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -33,6 +38,7 @@
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SARADC_MESON=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/beelink-gtking_defconfig b/configs/beelink-gtking_defconfig
index 42e1ba6..5c21d8e 100644
--- a/configs/beelink-gtking_defconfig
+++ b/configs/beelink-gtking_defconfig
@@ -17,12 +17,17 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=32
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -32,6 +37,7 @@
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/beelink-gtkingpro_defconfig b/configs/beelink-gtkingpro_defconfig
index a371332..37bb4cd 100644
--- a/configs/beelink-gtkingpro_defconfig
+++ b/configs/beelink-gtkingpro_defconfig
@@ -17,12 +17,17 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=32
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -32,6 +37,7 @@
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig
index 161b44c..b8c9afd 100644
--- a/configs/bitmain_antminer_s9_defconfig
+++ b/configs/bitmain_antminer_s9_defconfig
@@ -33,8 +33,8 @@
CONFIG_SPL_BSS_MAX_SIZE=0x100000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x2000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="antminer> "
CONFIG_SYS_MAXARGS=32
diff --git a/configs/boston32r2_defconfig b/configs/boston32r2_defconfig
index 526dbbe..82565bd 100644
--- a/configs/boston32r2_defconfig
+++ b/configs/boston32r2_defconfig
@@ -18,8 +18,8 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_PROMPT="boston # "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
diff --git a/configs/boston32r2el_defconfig b/configs/boston32r2el_defconfig
index 1377cee..a64b191 100644
--- a/configs/boston32r2el_defconfig
+++ b/configs/boston32r2el_defconfig
@@ -19,8 +19,8 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_PROMPT="boston # "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
diff --git a/configs/boston32r6_defconfig b/configs/boston32r6_defconfig
index 77d8c03..e23726b 100644
--- a/configs/boston32r6_defconfig
+++ b/configs/boston32r6_defconfig
@@ -19,8 +19,8 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_PROMPT="boston # "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
diff --git a/configs/boston32r6el_defconfig b/configs/boston32r6el_defconfig
index 5dbcd13..be8e4e4 100644
--- a/configs/boston32r6el_defconfig
+++ b/configs/boston32r6el_defconfig
@@ -20,8 +20,8 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_PROMPT="boston # "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
diff --git a/configs/boston64r2_defconfig b/configs/boston64r2_defconfig
index a93c6a7..d4dcf0c 100644
--- a/configs/boston64r2_defconfig
+++ b/configs/boston64r2_defconfig
@@ -19,8 +19,8 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_PROMPT="boston # "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
diff --git a/configs/boston64r2el_defconfig b/configs/boston64r2el_defconfig
index 57d0111..731943a 100644
--- a/configs/boston64r2el_defconfig
+++ b/configs/boston64r2el_defconfig
@@ -20,8 +20,8 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_PROMPT="boston # "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
diff --git a/configs/boston64r6_defconfig b/configs/boston64r6_defconfig
index 711d06c..905a2fc 100644
--- a/configs/boston64r6_defconfig
+++ b/configs/boston64r6_defconfig
@@ -19,8 +19,8 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_PROMPT="boston # "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
diff --git a/configs/boston64r6el_defconfig b/configs/boston64r6el_defconfig
index 8a0b4c0..a7bce2c 100644
--- a/configs/boston64r6el_defconfig
+++ b/configs/boston64r6el_defconfig
@@ -20,8 +20,8 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_PROMPT="boston # "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
diff --git a/configs/bpi-r2-pro-rk3568_defconfig b/configs/bpi-r2-pro-rk3568_defconfig
new file mode 100644
index 0000000..c08ceba
--- /dev/null
+++ b/configs/bpi-r2-pro-rk3568_defconfig
@@ -0,0 +1,93 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-bpi-r2-pro"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-bpi-r2-pro.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_SYS_PROMPT="BPI-R2PRO> "
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SYSBOOT=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_DWC_AHCI=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
index 6536202..640daa6 100644
--- a/configs/brppt1_mmc_defconfig
+++ b/configs/brppt1_mmc_defconfig
@@ -24,8 +24,8 @@
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_EXPERT is not set
# CONFIG_FIT is not set
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=0
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run b_default"
CONFIG_USE_PREBOOT=y
@@ -37,8 +37,8 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x500000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
CONFIG_SPL_I2C=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_POWER=y
diff --git a/configs/brppt2_defconfig b/configs/brppt2_defconfig
index 05ee4c5..e17dad9 100644
--- a/configs/brppt2_defconfig
+++ b/configs/brppt2_defconfig
@@ -25,14 +25,14 @@
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_LOAD_ADDR=0x10700000
# CONFIG_EXPERT is not set
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=0
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run b_default"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_SPI_FLASH=y
diff --git a/configs/brsmarc1_defconfig b/configs/brsmarc1_defconfig
index 94943fc..3c3f6d5 100644
--- a/configs/brsmarc1_defconfig
+++ b/configs/brsmarc1_defconfig
@@ -25,8 +25,8 @@
CONFIG_SYS_LOAD_ADDR=0x80000000
# CONFIG_EXPERT is not set
# CONFIG_FIT is not set
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=0
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run b_default"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
@@ -38,8 +38,8 @@
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x500000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_I2C=y
# CONFIG_SPL_NAND_SUPPORT is not set
@@ -96,7 +96,6 @@
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_OF_TRANSLATE is not set
-# CONFIG_SPL_BLK is not set
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_MMC_OMAP_HS=y
diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig
index b50aef0..91c2560 100644
--- a/configs/brxre1_defconfig
+++ b/configs/brxre1_defconfig
@@ -22,8 +22,8 @@
CONFIG_SYS_LOAD_ADDR=0x80000000
# CONFIG_EXPERT is not set
# CONFIG_FIT is not set
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=0
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev 1; run b_default"
CONFIG_USE_PREBOOT=y
@@ -34,8 +34,8 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x500000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
CONFIG_SPL_I2C=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_POWER=y
diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig
index a264ebe..0cac763 100644
--- a/configs/cardhu_defconfig
+++ b/configs/cardhu_defconfig
@@ -20,10 +20,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra30 (Cardhu) # "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2084
diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig
index 8542399..628a9d1 100644
--- a/configs/cei-tk1-som_defconfig
+++ b/configs/cei-tk1-som_defconfig
@@ -24,10 +24,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra124 (TK1-SOM) # "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2086
diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig
index 32e0647..aef7069 100644
--- a/configs/cgtqmx8_defconfig
+++ b/configs/cgtqmx8_defconfig
@@ -23,8 +23,8 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_LOG=y
@@ -36,10 +36,10 @@
# CONFIG_SPL_BINMAN_UBOOT_SYMBOLS is not set
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x120000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x3000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x3000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=0
diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig
index 0079971..4967be0 100644
--- a/configs/cherryhill_defconfig
+++ b/configs/cherryhill_defconfig
@@ -18,7 +18,6 @@
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
@@ -36,7 +35,6 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig
index 0c3fd42..06642d2 100644
--- a/configs/chiliboard_defconfig
+++ b/configs/chiliboard_defconfig
@@ -24,8 +24,8 @@
CONFIG_DEFAULT_FDT_FILE="am335x-chiliboard.dtb"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig
index 152f297..7d825c7 100644
--- a/configs/chromebook_coral_defconfig
+++ b/configs/chromebook_coral_defconfig
@@ -23,8 +23,8 @@
CONFIG_X86_OFFSET_SPL=0xffe80000
CONFIG_INTEL_ACPIGEN=y
CONFIG_INTEL_GENERIC_WIFI=y
-CONFIG_BOOTSTD_FULL=y
CONFIG_SYS_MONITOR_BASE=0x01110000
+CONFIG_BOOTSTD_FULL=y
CONFIG_CHROMEOS=y
CONFIG_BOOTSTAGE=y
CONFIG_SPL_BOOTSTAGE=y
@@ -40,7 +40,6 @@
CONFIG_LOG=y
CONFIG_LOGF_FUNC=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_BLOBLIST=y
# CONFIG_TPL_BLOBLIST is not set
CONFIG_BLOBLIST_ADDR=0x100000
@@ -82,7 +81,6 @@
# CONFIG_SPL_MAC_PARTITION is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent interrupts linux-name acpi,name acpi,path u-boot,acpi-dsdt-order u-boot,acpi-ssdt-order"
CONFIG_ENV_OVERWRITE=y
diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig
index 558609e..eb8923c 100644
--- a/configs/chromebook_link64_defconfig
+++ b/configs/chromebook_link64_defconfig
@@ -29,7 +29,6 @@
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index 96c26f1..94ffb56 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -25,7 +25,6 @@
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=532
@@ -50,7 +49,6 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig
index 4019c16..611d649 100644
--- a/configs/chromebook_samus_defconfig
+++ b/configs/chromebook_samus_defconfig
@@ -25,7 +25,6 @@
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=532
@@ -52,7 +51,6 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig
index 4cfaf4b..8b692bd 100644
--- a/configs/chromebook_samus_tpl_defconfig
+++ b/configs/chromebook_samus_tpl_defconfig
@@ -9,6 +9,8 @@
CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus"
CONFIG_SPL_TEXT_BASE=0xffe70000
CONFIG_TPL_TEXT_BASE=0xfffd8100
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x3000
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -19,7 +21,6 @@
CONFIG_HAVE_REFCODE=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
-CONFIG_X86_OFFSET_U_BOOT=0xffee0000
CONFIG_SYS_MONITOR_BASE=0xFFED0000
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
@@ -30,7 +31,6 @@
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_BLOBLIST=y
CONFIG_BLOBLIST_ADDR=0xff7c0000
@@ -69,7 +69,6 @@
# CONFIG_SPL_MAC_PARTITION is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index f050d06..b6b12b4 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -21,7 +21,6 @@
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=532
@@ -44,7 +43,6 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
diff --git a/configs/ci20_mmc_defconfig b/configs/ci20_mmc_defconfig
index 6621ca9..bf522e1 100644
--- a/configs/ci20_mmc_defconfig
+++ b/configs/ci20_mmc_defconfig
@@ -47,7 +47,6 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_JZ4780_EFUSE=y
CONFIG_MMC=y
diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig
index 503da92..26f50a5 100644
--- a/configs/cl-som-imx7_defconfig
+++ b/configs/cl-som-imx7_defconfig
@@ -31,7 +31,7 @@
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_MAX_SIZE=0x100000
CONFIG_SPL_BOARD_INIT=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
CONFIG_SPL_I2C=y
CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index 3c0d8af..fab8351 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -25,14 +25,15 @@
CONFIG_SPL_SPI=y
# CONFIG_CMD_BMODE is not set
CONFIG_AHCI=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run legacy_bootcmd"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="usb start;sf probe"
CONFIG_MISC_INIT_R=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
CONFIG_SPL_I2C=y
CONFIG_SPL_SPI_LOAD=y
@@ -119,4 +120,3 @@
CONFIG_IMX_HDMI=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SOURCE=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index bc2ab1a..73ccefd 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -32,8 +32,8 @@
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_MAX_SIZE=0x37690
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x480
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig
index 2c3086a..13c16bd 100644
--- a/configs/colibri-imx8x_defconfig
+++ b/configs/colibri-imx8x_defconfig
@@ -20,9 +20,9 @@
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-colibri-${fdt_board}.dtb"
CONFIG_LOG=y
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index de5633c..51f3eec 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -38,7 +38,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_DMA=y
CONFIG_SPL_I2C=y
CONFIG_SYS_PROMPT="Colibri iMX6 # "
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index 28a77d1..62b7cc5 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -21,10 +21,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x90000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Colibri T20 # "
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_CBSIZE=1024
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index 88dc245..43f9e21 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -22,10 +22,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Colibri T30 # "
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_CBSIZE=1024
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index 1d34a46..8b2324f 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -18,6 +18,7 @@
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=520192
CONFIG_BOOTDELAY=1
+CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run ubiboot || run distro_bootcmd;"
CONFIG_USE_PREBOOT=y
@@ -104,5 +105,4 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
index 656d575..e1e1afe 100644
--- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
+++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
@@ -31,7 +31,6 @@
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
@@ -54,7 +53,6 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig
index 54dc59e..27d6d4f 100644
--- a/configs/conga-qeval20-qa3-e3845_defconfig
+++ b/configs/conga-qeval20-qa3-e3845_defconfig
@@ -27,7 +27,6 @@
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
@@ -50,7 +49,6 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig
index 8aadaa6..1f1327f 100644
--- a/configs/coreboot64_defconfig
+++ b/configs/coreboot64_defconfig
@@ -1,5 +1,6 @@
CONFIG_X86=y
CONFIG_TEXT_BASE=0x1120000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="coreboot"
@@ -8,41 +9,34 @@
CONFIG_X86_RUN_64BIT=y
CONFIG_VENDOR_COREBOOT=y
CONFIG_TARGET_COREBOOT=y
+CONFIG_SYS_MONITOR_BASE=0x01120000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
-CONFIG_SYS_MONITOR_BASE=0x01120000
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_LOG=y
+CONFIG_LOGF_LINE=y
+CONFIG_LOGF_FUNC=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_SPL_NO_BSS_LIMIT=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_IDE=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
+CONFIG_CMD_SATA=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
CONFIG_BOOTP_BOOTFILESIZE=y
-CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_SOUND=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
# CONFIG_SPL_MAC_PARTITION is not set
# CONFIG_SPL_DOS_PARTITION is not set
-CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@@ -60,8 +54,14 @@
CONFIG_ATAPI=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
+CONFIG_NVME_PCI=y
# CONFIG_PCI_PNP is not set
+CONFIG_SYS_NS16550_MEM32=y
CONFIG_SOUND=y
CONFIG_SOUND_I8254=y
+CONFIG_VIDEO_COPY=y
CONFIG_CONSOLE_SCROLL_LINES=5
+CONFIG_SPL_ACPI=y
+CONFIG_CMD_DHRYSTONE=y
# CONFIG_GZIP is not set
+CONFIG_SMBIOS_PARSER=y
diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig
index 8e11de6..8356bc1 100644
--- a/configs/coreboot_defconfig
+++ b/configs/coreboot_defconfig
@@ -7,10 +7,11 @@
CONFIG_PRE_CON_BUF_ADDR=0x100000
CONFIG_VENDOR_COREBOOT=y
CONFIG_TARGET_COREBOOT=y
+CONFIG_SYS_MONITOR_BASE=0x01110000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTD_FULL=y
-CONFIG_SYS_MONITOR_BASE=0x01110000
+CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
@@ -20,25 +21,17 @@
CONFIG_LOGF_LINE=y
CONFIG_LOGF_FUNC=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_PCI_INIT_R=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
+CONFIG_CMD_SATA=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
CONFIG_BOOTP_BOOTFILESIZE=y
-CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_SOUND=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
@@ -48,10 +41,19 @@
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_ACPIGEN is not set
+CONFIG_SYS_IDE_MAXDEVICE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_ALT_OFFSET=0
+CONFIG_ATAPI=y
+CONFIG_LBA48=y
+CONFIG_SYS_64BIT_LBA=y
CONFIG_NVME_PCI=y
# CONFIG_PCI_PNP is not set
+CONFIG_SYS_NS16550_MEM32=y
CONFIG_SOUND=y
CONFIG_SOUND_I8254=y
+CONFIG_VIDEO_COPY=y
CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_CMD_DHRYSTONE=y
# CONFIG_GZIP is not set
diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
index 074936d..3cd6aa0 100644
--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
@@ -14,7 +14,7 @@
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9 ip=dhcp earlyprintk"
-CONFIG_BOOTCOMMAND="echo Loading kernel from $kernel_addr to memory ... ; loadm $kernel_addr $kernel_addr_r 0xc00000; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;"
+CONFIG_BOOTCOMMAND="echo Loading kernel from $kernel_addr to memory ... ; unzip $kernel_addr 0x90000000; loadm 0x90000000 $kernel_addr_r $filesize; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;"
CONFIG_CONSOLE_RECORD=y
CONFIG_LOGLEVEL=7
# CONFIG_DISPLAY_CPUINFO is not set
@@ -55,6 +55,7 @@
CONFIG_RTC_EMULATION=y
CONFIG_DM_SERIAL=y
CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_USB=y
diff --git a/configs/cortina_presidio-asic-emmc_defconfig b/configs/cortina_presidio-asic-emmc_defconfig
index 3f73020..c55fdd0 100644
--- a/configs/cortina_presidio-asic-emmc_defconfig
+++ b/configs/cortina_presidio-asic-emmc_defconfig
@@ -18,7 +18,6 @@
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_SYS_PROMPT="G3#"
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_CBSIZE=256
diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig
index da5ff55..dd9d912 100644
--- a/configs/cougarcanyon2_defconfig
+++ b/configs/cougarcanyon2_defconfig
@@ -20,7 +20,6 @@
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
@@ -40,7 +39,6 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index 70e1a50..cef6f82 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -21,7 +21,6 @@
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
@@ -43,7 +42,6 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index 7d87588..8043ecf 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -45,10 +45,10 @@
CONFIG_SPL_MAX_FOOTPRINT=0x8000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xc0f70000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x110000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0f70000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x110000
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig
index 0ccd1b4..5f6f5d7 100644
--- a/configs/da850evm_nand_defconfig
+++ b/configs/da850evm_nand_defconfig
@@ -41,10 +41,10 @@
CONFIG_SPL_MAX_FOOTPRINT=0x8000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xc0f70000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x110000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0f70000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x110000
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_DRIVERS=y
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index 442827d..85b349f 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -20,10 +20,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra114 (Dalmore) # "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2086
diff --git a/configs/deneb_defconfig b/configs/deneb_defconfig
index 3e2675f..65b9809 100644
--- a/configs/deneb_defconfig
+++ b/configs/deneb_defconfig
@@ -22,19 +22,17 @@
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x2000
CONFIG_IDENT_STRING=" ##v01.06"
-CONFIG_SPL_LOAD_IMX_CONTAINER=y
-CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="if usrbutton; then run flash_self_test; reset; fi;run flash_self;reset;"
CONFIG_LOG=y
@@ -44,12 +42,16 @@
CONFIG_SPL_BSS_START_ADDR=0x128000
CONFIG_SPL_BSS_MAX_SIZE=0x1000
CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x120000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x3000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x3000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_POWER_DOMAIN=y
diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig
index caeb009..ef16da1 100644
--- a/configs/devkit8000_defconfig
+++ b/configs/devkit8000_defconfig
@@ -19,16 +19,16 @@
CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_BSS_START_ADDR=0x80000500
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80208000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SPL_NAND_BASE=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x80000100
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x80000100
CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x280000
CONFIG_SPL_FALCON_BOOT_MMCSD=y
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x500
diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig
index 9313e7f..6b5bbc1 100644
--- a/configs/dfi-bt700-q7x-151_defconfig
+++ b/configs/dfi-bt700-q7x-151_defconfig
@@ -26,7 +26,6 @@
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
@@ -48,7 +47,6 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
index 5ea9e0b..5a83b6a 100644
--- a/configs/dh_imx6_defconfig
+++ b/configs/dh_imx6_defconfig
@@ -38,7 +38,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
CONFIG_SPL_WATCHDOG=y
diff --git a/configs/display5_defconfig b/configs/display5_defconfig
index 481c737..24f22f0 100644
--- a/configs/display5_defconfig
+++ b/configs/display5_defconfig
@@ -38,14 +38,14 @@
CONFIG_BOOTCOMMAND="if run check_em_pad; then run recovery;else if test ${BOOT_FROM} = FACTORY; then run factory_nfs;else run boot_mmc;fi;fi"
CONFIG_MISC_INIT_R=y
CONFIG_SPL_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SAVEENV=y
CONFIG_SPL_I2C=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x18000000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x18000000
CONFIG_SPL_FALCON_BOOT_MMCSD=y
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x100
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x3F00
diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig
index e480499..19b1898 100644
--- a/configs/display5_factory_defconfig
+++ b/configs/display5_factory_defconfig
@@ -30,17 +30,17 @@
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="echo SDP Display5 recovery"
CONFIG_MISC_INIT_R=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_DMA=y
CONFIG_SPL_I2C=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x18000000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x18000000
CONFIG_SPL_FALCON_BOOT_MMCSD=y
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x100
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x3F00
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 14dff63..19ca89f 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -20,8 +20,8 @@
CONFIG_AHCI=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS0,115200 androidboot.console=ttyS0 androidboot.hardware=jacinto6evmboard"
CONFIG_BOOTCOMMAND="if test ${dofastboot} -eq 1; then echo Boot fastboot requested, resetting dofastboot ...;setenv dofastboot 0; saveenv;echo Booting into fastboot ...; fastboot 1;fi;if test ${boot_fit} -eq 1; then run update_to_fit;fi;run findfdt; run finduuid; run distro_bootcmd;run emmc_android_boot; "
@@ -30,8 +30,8 @@
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_MAX_SIZE=0x7bc00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_DMA=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_NAND_DRIVERS=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 0d6d9ef..0a53f62 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -23,8 +23,8 @@
CONFIG_AHCI=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS0,115200 androidboot.console=ttyS0 androidboot.hardware=jacinto6evmboard"
CONFIG_BOOTCOMMAND="if test ${dofastboot} -eq 1; then echo Boot fastboot requested, resetting dofastboot ...;setenv dofastboot 0; saveenv;echo Booting into fastboot ...; fastboot 1;fi;if test ${boot_fit} -eq 1; then run update_to_fit;fi;run findfdt; run finduuid; run distro_bootcmd;run emmc_android_boot; "
@@ -33,8 +33,8 @@
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_MAX_SIZE=0x7a8b0
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_DMA=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
# CONFIG_SPL_NAND_SUPPORT is not set
diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig
index 506a65a..3a1b48f 100644
--- a/configs/dra7xx_hs_evm_usb_defconfig
+++ b/configs/dra7xx_hs_evm_usb_defconfig
@@ -24,8 +24,8 @@
CONFIG_AHCI=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS0,115200 androidboot.console=ttyS0 androidboot.hardware=jacinto6evmboard"
CONFIG_BOOTCOMMAND="if test ${dofastboot} -eq 1; then echo Boot fastboot requested, resetting dofastboot ...;setenv dofastboot 0; saveenv;echo Booting into fastboot ...; fastboot 1;fi;if test ${boot_fit} -eq 1; then run update_to_fit;fi;run findfdt; run finduuid; run distro_bootcmd;run emmc_android_boot; "
@@ -34,8 +34,8 @@
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_MAX_SIZE=0x74eb0
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_DMA=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
# CONFIG_SPL_NAND_SUPPORT is not set
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index 981a364..ee19920 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -37,9 +37,9 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_BSS_START_ADDR=0x80000000
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80208000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000
CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig
index 32d761c..b338326 100644
--- a/configs/dragonboard410c_defconfig
+++ b/configs/dragonboard410c_defconfig
@@ -15,8 +15,8 @@
CONFIG_REMAKE_ELF=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/ds116_defconfig b/configs/ds116_defconfig
index 0cd546c..2437be7 100644
--- a/configs/ds116_defconfig
+++ b/configs/ds116_defconfig
@@ -28,7 +28,8 @@
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_BOOTDELAY=10
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/durian_defconfig b/configs/durian_defconfig
index 1a32139..72214b1 100644
--- a/configs/durian_defconfig
+++ b/configs/durian_defconfig
@@ -19,7 +19,6 @@
CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_LAST_STAGE_INIT=y
CONFIG_SYS_PROMPT="durian#"
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=280
diff --git a/configs/eDPU_defconfig b/configs/eDPU_defconfig
index f51df78..238f91c 100644
--- a/configs/eDPU_defconfig
+++ b/configs/eDPU_defconfig
@@ -81,6 +81,7 @@
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
# CONFIG_SCSI is not set
+CONFIG_DEFAULT_ENV_IS_RW=y
CONFIG_MVEBU_A3700_UART=y
CONFIG_MVEBU_A3700_SPI=y
CONFIG_SYSINFO=y
diff --git a/configs/ea-lpc3250devkitv2_defconfig b/configs/ea-lpc3250devkitv2_defconfig
index 216806d..5865ffb 100644
--- a/configs/ea-lpc3250devkitv2_defconfig
+++ b/configs/ea-lpc3250devkitv2_defconfig
@@ -14,9 +14,9 @@
CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=1048575
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_AUTOBOOT is not set
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="EA-LPC3250v2=> "
diff --git a/configs/edison_defconfig b/configs/edison_defconfig
index 8692a8a..f134680 100644
--- a/configs/edison_defconfig
+++ b/configs/edison_defconfig
@@ -13,7 +13,6 @@
CONFIG_SMP=y
CONFIG_SYS_MONITOR_BASE=0x01101000
CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=128
CONFIG_SYS_CBSIZE=2048
diff --git a/configs/efi-x86_app32_defconfig b/configs/efi-x86_app32_defconfig
index 50975db..dfc3157 100644
--- a/configs/efi-x86_app32_defconfig
+++ b/configs/efi-x86_app32_defconfig
@@ -2,7 +2,7 @@
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="efi-x86_app"
-CONFIG_DEBUG_UART_BASE=0
+CONFIG_DEBUG_UART_BASE=0x0
CONFIG_DEBUG_UART_CLOCK=0
CONFIG_VENDOR_EFI=y
CONFIG_TARGET_EFI_APP32=y
@@ -16,7 +16,6 @@
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
diff --git a/configs/efi-x86_app64_defconfig b/configs/efi-x86_app64_defconfig
index 0fc358d..e0cfe3e 100644
--- a/configs/efi-x86_app64_defconfig
+++ b/configs/efi-x86_app64_defconfig
@@ -2,7 +2,7 @@
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="efi-x86_app"
-CONFIG_DEBUG_UART_BASE=0
+CONFIG_DEBUG_UART_BASE=0x0
CONFIG_DEBUG_UART_CLOCK=0
CONFIG_X86_RUN_64BIT=y
CONFIG_VENDOR_EFI=y
@@ -17,7 +17,6 @@
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
diff --git a/configs/efi-x86_payload32_defconfig b/configs/efi-x86_payload32_defconfig
index 4149eea..194a7ab 100644
--- a/configs/efi-x86_payload32_defconfig
+++ b/configs/efi-x86_payload32_defconfig
@@ -15,7 +15,6 @@
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_IDE=y
@@ -34,7 +33,6 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
diff --git a/configs/efi-x86_payload64_defconfig b/configs/efi-x86_payload64_defconfig
index d41f73c..a060080 100644
--- a/configs/efi-x86_payload64_defconfig
+++ b/configs/efi-x86_payload64_defconfig
@@ -7,16 +7,15 @@
CONFIG_TARGET_EFI_PAYLOAD=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_IDE=y
CONFIG_CMD_MMC=y
@@ -34,8 +33,10 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_INTERFACE="scsi"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="bzImage"
diff --git a/configs/endeavoru_defconfig b/configs/endeavoru_defconfig
index 681aae2..d605acd 100644
--- a/configs/endeavoru_defconfig
+++ b/configs/endeavoru_defconfig
@@ -15,19 +15,19 @@
CONFIG_TARGET_ENDEAVORU=y
CONFIG_CMD_EBTUPDATE=y
CONFIG_SYS_LOAD_ADDR=0x82000000
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=0
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="if run check_button; then bootmenu; fi; run bootcmd_mmc0; poweroff;"
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra30 (Endeavoru) # "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2084
diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig
index 870d8d2..c0ce7a3 100644
--- a/configs/etamin_defconfig
+++ b/configs/etamin_defconfig
@@ -38,9 +38,9 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_BSS_START_ADDR=0x80000000
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80208000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000
CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 02254ef..21c657a 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -41,7 +41,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-# CONFIG_SPL_BLK is not set
CONFIG_CLK=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index c1e7f39..7469f3f 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -12,7 +12,6 @@
CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb"
CONFIG_SPL_TEXT_BASE=0x60000000
CONFIG_ROCKCHIP_RK322X=y
-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_TARGET_EVB_RK3229=y
CONFIG_SPL_STACK_R_ADDR=0x60600000
CONFIG_DEBUG_UART_BASE=0x11030000
diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig
index a13a809..2729060 100644
--- a/configs/evb-rk3308_defconfig
+++ b/configs/evb-rk3308_defconfig
@@ -11,7 +11,6 @@
CONFIG_DEFAULT_DEVICE_TREE="rk3308-evb"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3308=y
-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_EVB_RK3308=y
CONFIG_SPL_STACK_R_ADDR=0xc00000
@@ -24,6 +23,7 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=0
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-evb.dtb"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0x20000
@@ -47,7 +47,7 @@
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_SLEEP is not set
-# CONFIG_DOS_PARTITION is not set
+# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
CONFIG_SPL_OF_CONTROL=y
diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig
index 5f3fab7..cb9b87f 100644
--- a/configs/evb-rk3568_defconfig
+++ b/configs/evb-rk3568_defconfig
@@ -46,6 +46,7 @@
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
@@ -58,8 +59,9 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_RK8XX=y
diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index f49c2ca..0b7b4f2 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -58,8 +58,9 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index c6d989e..3eb1917 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -17,7 +17,6 @@
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
@@ -38,7 +37,6 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig
index f6a6740..439fcc0 100644
--- a/configs/gardena-smart-gateway-at91sam_defconfig
+++ b/configs/gardena-smart-gateway-at91sam_defconfig
@@ -43,8 +43,8 @@
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_RAW_ONLY=y
diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig
index aecd6fb..bedc596 100644
--- a/configs/gardena-smart-gateway-mt7688_defconfig
+++ b/configs/gardena-smart-gateway-mt7688_defconfig
@@ -29,9 +29,9 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR="x"
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="cp.b 83000000 84000000 10000 && dhcp uEnv.txt && env import -t ${fileaddr} ${filesize} && run do_u_boot_init; reset"
CONFIG_USE_PREBOOT=y
diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig
index 7901a19..3c212c7 100644
--- a/configs/gazerbeam_defconfig
+++ b/configs/gazerbeam_defconfig
@@ -94,11 +94,11 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=5
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/mmcblk0p3 rw rootwait console=$consoledev,$baudrate $othbootargs;ext2load mmc 0:2 ${kernel_addr} $bootfile;ext2load mmc 0:2 ${fdt_addr} $fdtfile;bootm ${kernel_addr} - ${fdt_addr}"
# CONFIG_CONSOLE_MUX is not set
diff --git a/configs/ge_b1x5v2_defconfig b/configs/ge_b1x5v2_defconfig
index b3b69a6..278a5a1 100644
--- a/configs/ge_b1x5v2_defconfig
+++ b/configs/ge_b1x5v2_defconfig
@@ -29,8 +29,8 @@
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=1
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run tryboot;"
CONFIG_DEFAULT_FDT_FILE="imx6dl-b1x5v2.dtb"
@@ -39,7 +39,7 @@
CONFIG_LOG_DEFAULT_LEVEL=4
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
CONFIG_HUSH_PARSER=y
diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig
index 2ef560c..61f338f 100644
--- a/configs/ge_bx50v3_defconfig
+++ b/configs/ge_bx50v3_defconfig
@@ -15,8 +15,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=1
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run doquiet; run tryboot"
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig
new file mode 100644
index 0000000..8f0a9c8
--- /dev/null
+++ b/configs/generic-rk3568_defconfig
@@ -0,0 +1,64 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-generic"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-generic.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_MISC=y
+# CONFIG_ROCKCHIP_IODOMAIN is not set
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/giedi_defconfig b/configs/giedi_defconfig
index 57b0645..3c3c7fb 100644
--- a/configs/giedi_defconfig
+++ b/configs/giedi_defconfig
@@ -22,19 +22,17 @@
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x2000
CONFIG_IDENT_STRING=" ##v01.07"
-CONFIG_SPL_LOAD_IMX_CONTAINER=y
-CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="if usrbutton; then run flash_self_test; reset; fi;run flash_self;reset;"
CONFIG_LOG=y
@@ -44,12 +42,16 @@
CONFIG_SPL_BSS_START_ADDR=0x128000
CONFIG_SPL_BSS_MAX_SIZE=0x1000
CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x120000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x3000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x3000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_POWER_DOMAIN=y
diff --git a/configs/grouper_common_defconfig b/configs/grouper_common_defconfig
index 45485d6..258d7b1 100644
--- a/configs/grouper_common_defconfig
+++ b/configs/grouper_common_defconfig
@@ -15,19 +15,19 @@
CONFIG_TARGET_GROUPER=y
CONFIG_CMD_EBTUPDATE=y
CONFIG_SYS_LOAD_ADDR=0x82000000
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=0
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="if run check_button; then bootmenu; fi; run bootcmd_mmc0; poweroff;"
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra30 (Grouper) # "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2084
@@ -59,8 +59,6 @@
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_GPIO_HOG=y
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_GPIO=y
CONFIG_BUTTON_KEYBOARD=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig
index fd2489d..08afc7f 100644
--- a/configs/gwventana_emmc_defconfig
+++ b/configs/gwventana_emmc_defconfig
@@ -30,8 +30,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="for btype in ${bootdevs}; do echo; echo Attempting ${btype} boot...; if run ${btype}_boot; then; fi; done"
CONFIG_USE_PREBOOT=y
@@ -43,12 +44,12 @@
CONFIG_PCI_INIT_R=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_DMA=y
CONFIG_SPL_I2C=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x18000000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x18000000
CONFIG_SPL_FALCON_BOOT_MMCSD=y
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1000
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x800
@@ -176,4 +177,3 @@
CONFIG_HIDE_LOGO_VERSION=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
CONFIG_IMX_WATCHDOG=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig
index eaab1d8..3f0cb19 100644
--- a/configs/gwventana_nand_defconfig
+++ b/configs/gwventana_nand_defconfig
@@ -30,8 +30,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="for btype in ${bootdevs}; do echo; echo Attempting ${btype} boot...; if run ${btype}_boot; then; fi; done"
CONFIG_USE_PREBOOT=y
@@ -43,13 +44,13 @@
CONFIG_PCI_INIT_R=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_DMA=y
CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x18000000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x18000000
CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x1200000
CONFIG_SPL_FALCON_BOOT_MMCSD=y
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1000
@@ -183,4 +184,3 @@
CONFIG_HIDE_LOGO_VERSION=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
CONFIG_IMX_WATCHDOG=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index 6558a67..ba58e23 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -18,10 +18,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x90000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra20 (Harmony) # "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2085
diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig
index 4eac7b2..e4764c3 100644
--- a/configs/highbank_defconfig
+++ b/configs/highbank_defconfig
@@ -16,7 +16,6 @@
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_ENV_ADDR=0xFFF88000
CONFIG_FIT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds...\nPress <s> to stop or <d> to delay\n"
@@ -24,6 +23,7 @@
CONFIG_BOOT_RETRY=y
CONFIG_BOOT_RETRY_TIME=-1
CONFIG_RESET_TO_RETRY=y
+CONFIG_OF_BOARD_SETUP=y
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig
index 257dd89..37f0f53 100644
--- a/configs/i12-tvbox_defconfig
+++ b/configs/i12-tvbox_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
-CONFIG_MACPWR="PH21"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/icnova-a20-adb4006_defconfig b/configs/icnova-a20-adb4006_defconfig
new file mode 100644
index 0000000..22cbb61
--- /dev/null
+++ b/configs/icnova-a20-adb4006_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-icnova-a20-adb4006"
+CONFIG_SPL=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_I2C=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SYS_64BIT_LBA=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_SUN7I_GMAC=y
+CONFIG_AXP_ALDO4_VOLT=2800
+CONFIG_SCSI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig
index a0078e1..993bbe2 100644
--- a/configs/igep00x0_defconfig
+++ b/configs/igep00x0_defconfig
@@ -11,17 +11,18 @@
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_NAND_DRIVERS=y
@@ -42,7 +43,7 @@
CONFIG_SPL_UBI_LOAD_ARGS_ID=4
CONFIG_SPL_ONENAND_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x84000000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x84000000
CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x280000
CONFIG_SPL_FALCON_BOOT_MMCSD=y
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
@@ -87,4 +88,3 @@
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_BCH=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig
index 96d15e8..c1b0487 100644
--- a/configs/imx28_xea_defconfig
+++ b/configs/imx28_xea_defconfig
@@ -27,8 +27,8 @@
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_SPL_PAYLOAD="u-boot.img"
-CONFIG_FIT=y
CONFIG_TIMESTAMP=y
+CONFIG_FIT=y
# CONFIG_BOOTMETH_EXTLINUX is not set
# CONFIG_BOOTMETH_VBE is not set
CONFIG_OF_BOARD_SETUP=y
@@ -51,7 +51,7 @@
CONFIG_SPL_MMC_TINY=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x44000000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x44000000
CONFIG_SPL_FALCON_BOOT_MMCSD=y
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x800
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x400
diff --git a/configs/imx28_xea_sb_defconfig b/configs/imx28_xea_sb_defconfig
index a431834..0b32598 100644
--- a/configs/imx28_xea_sb_defconfig
+++ b/configs/imx28_xea_sb_defconfig
@@ -12,7 +12,6 @@
CONFIG_DEFAULT_DEVICE_TREE="imx28-xea"
CONFIG_SPL_TEXT_BASE=0x1000
CONFIG_TARGET_XEA=y
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x90000
CONFIG_SYS_LOAD_ADDR=0x42000000
@@ -69,7 +68,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_DEVRES=y
-# CONFIG_SPL_BLK is not set
CONFIG_MXS_GPIO=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_MXS=y
diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig
index 8d53282..da62af9 100644
--- a/configs/imx6dl_icore_nand_defconfig
+++ b/configs/imx6dl_icore_nand_defconfig
@@ -24,7 +24,7 @@
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run $modeboot"
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig
index 8c7c13e..35ded27 100644
--- a/configs/imx6dl_mamoj_defconfig
+++ b/configs/imx6dl_mamoj_defconfig
@@ -18,9 +18,9 @@
CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x13000000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x13000000
CONFIG_SPL_FALCON_BOOT_MMCSD=y
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1000
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x800
diff --git a/configs/imx6q_bosch_acc_defconfig b/configs/imx6q_bosch_acc_defconfig
index c44d43a..05bab03 100644
--- a/configs/imx6q_bosch_acc_defconfig
+++ b/configs/imx6q_bosch_acc_defconfig
@@ -35,7 +35,7 @@
CONFIG_BOOTCOMMAND="run mmc_mmc_fit"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xaa
# CONFIG_SPL_CRYPTO is not set
CONFIG_SPL_WATCHDOG=y
diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig
index 59c6d6b..ffad04f 100644
--- a/configs/imx6q_icore_nand_defconfig
+++ b/configs/imx6q_icore_nand_defconfig
@@ -25,7 +25,7 @@
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run $modeboot"
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
index cbacb96..5ee1f5d 100644
--- a/configs/imx6q_logic_defconfig
+++ b/configs/imx6q_logic_defconfig
@@ -28,14 +28,14 @@
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_DMA=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x18000000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x18000000
CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x500000
CONFIG_SPL_FALCON_BOOT_MMCSD=y
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1000
@@ -86,7 +86,6 @@
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/imx6qdl_icore_mipi_defconfig b/configs/imx6qdl_icore_mipi_defconfig
index c170638..46be3b6 100644
--- a/configs/imx6qdl_icore_mipi_defconfig
+++ b/configs/imx6qdl_icore_mipi_defconfig
@@ -33,9 +33,9 @@
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run $modeboot"
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x18000000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x18000000
CONFIG_SPL_FALCON_BOOT_MMCSD=y
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1000
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x800
diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig
index 90d01f2..c71e87e 100644
--- a/configs/imx6qdl_icore_mmc_defconfig
+++ b/configs/imx6qdl_icore_mmc_defconfig
@@ -36,9 +36,9 @@
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run $modeboot"
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x18000000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x18000000
CONFIG_SPL_FALCON_BOOT_MMCSD=y
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1000
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x800
diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig
index 59c6d6b..ffad04f 100644
--- a/configs/imx6qdl_icore_nand_defconfig
+++ b/configs/imx6qdl_icore_nand_defconfig
@@ -25,7 +25,7 @@
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run $modeboot"
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
diff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig
index d5a69b3..83d5e19 100644
--- a/configs/imx6qdl_icore_rqs_defconfig
+++ b/configs/imx6qdl_icore_rqs_defconfig
@@ -30,9 +30,9 @@
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run $modeboot"
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x18000000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x18000000
CONFIG_SPL_FALCON_BOOT_MMCSD=y
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1000
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x800
diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig
index a33d2ac..a7f913c 100644
--- a/configs/imx6ul_geam_mmc_defconfig
+++ b/configs/imx6ul_geam_mmc_defconfig
@@ -29,7 +29,7 @@
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run $modeboot"
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="geam6ul> "
diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig
index 3767949..05cac0b 100644
--- a/configs/imx6ul_geam_nand_defconfig
+++ b/configs/imx6ul_geam_nand_defconfig
@@ -25,7 +25,7 @@
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run $modeboot"
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig
index fe31e85..3a3ac3a 100644
--- a/configs/imx6ul_isiot_emmc_defconfig
+++ b/configs/imx6ul_isiot_emmc_defconfig
@@ -29,7 +29,7 @@
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run $modeboot"
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="isiotmx6ul> "
diff --git a/configs/imx6ul_isiot_nand_defconfig b/configs/imx6ul_isiot_nand_defconfig
index 6f55ce6..afd2790 100644
--- a/configs/imx6ul_isiot_nand_defconfig
+++ b/configs/imx6ul_isiot_nand_defconfig
@@ -25,7 +25,7 @@
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run $modeboot"
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
diff --git a/configs/imx6ulz_smm_m2_defconfig b/configs/imx6ulz_smm_m2_defconfig
index f3da19d..d6edc71 100644
--- a/configs/imx6ulz_smm_m2_defconfig
+++ b/configs/imx6ulz_smm_m2_defconfig
@@ -23,7 +23,7 @@
CONFIG_BOOTDELAY=3
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BSS_START_ADDR=0x84100000
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_DMA=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
diff --git a/configs/imx7_cm_defconfig b/configs/imx7_cm_defconfig
index c43aed4..30bf4eb 100644
--- a/configs/imx7_cm_defconfig
+++ b/configs/imx7_cm_defconfig
@@ -28,7 +28,7 @@
CONFIG_SPL_MAX_SIZE=0xe000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_MAX_SIZE=0x100000
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_I2C=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig
index b99488e..22bc964 100644
--- a/configs/imx8mm-cl-iot-gate-optee_defconfig
+++ b/configs/imx8mm-cl-iot-gate-optee_defconfig
@@ -22,18 +22,18 @@
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig
index 781c7eb..fdec2f8 100644
--- a/configs/imx8mm-cl-iot-gate_defconfig
+++ b/configs/imx8mm-cl-iot-gate_defconfig
@@ -24,18 +24,18 @@
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
index f94cf70..1f1a5b0 100644
--- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
+++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
@@ -21,18 +21,18 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-ctouch2.dtb"
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_POWER=y
diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
index 49cfb8f..a582004 100644
--- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
+++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
@@ -21,18 +21,18 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-edimm2.2.dtb"
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_POWER=y
diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig
index f5b2667..30719a37 100644
--- a/configs/imx8mm-mx8menlo_defconfig
+++ b/configs/imx8mm-mx8menlo_defconfig
@@ -28,8 +28,8 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="mmc partconf 0 distro_bootpart && load ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset"
CONFIG_DEFAULT_FDT_FILE="imx8mm-mx8menlo.dtb"
CONFIG_LOG=y
@@ -42,10 +42,10 @@
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
index 6e617e0..031470c 100644
--- a/configs/imx8mm_beacon_defconfig
+++ b/configs/imx8mm_beacon_defconfig
@@ -32,10 +32,10 @@
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm_beacon_fspi_defconfig b/configs/imx8mm_beacon_fspi_defconfig
index fc4ef94..cb9e6e7 100644
--- a/configs/imx8mm_beacon_fspi_defconfig
+++ b/configs/imx8mm_beacon_fspi_defconfig
@@ -35,10 +35,10 @@
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig
index 1814795..d61f839 100644
--- a/configs/imx8mm_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mm_data_modul_edm_sbc_defconfig
@@ -53,10 +53,10 @@
CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
@@ -119,7 +119,6 @@
CONFIG_CMD_UUID=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_HASH=y
CONFIG_CMD_SMC=y
CONFIG_HASH_VERIFY=y
CONFIG_CMD_BTRFS=y
@@ -157,6 +156,7 @@
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MM=y
CONFIG_CLK_IMX8MM=y
+CONFIG_FSL_CAAM=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y
@@ -171,7 +171,6 @@
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
# CONFIG_INPUT is not set
-CONFIG_MISC=y
CONFIG_USB_HUB_USB251XB=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
@@ -232,6 +231,5 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
-CONFIG_SDP_LOADADDR=0x0
CONFIG_USB_FUNCTION_ACM=y
CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index 0cdffdd..f1067d7 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -22,18 +22,18 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig
index 03d110f..93611a8 100644
--- a/configs/imx8mm_evk_fspi_defconfig
+++ b/configs/imx8mm_evk_fspi_defconfig
@@ -24,8 +24,8 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -33,10 +33,10 @@
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm_phg_defconfig b/configs/imx8mm_phg_defconfig
index 8b3e78d..67db255 100644
--- a/configs/imx8mm_phg_defconfig
+++ b/configs/imx8mm_phg_defconfig
@@ -22,18 +22,18 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
index d127d61..01cfb96 100644
--- a/configs/imx8mm_venice_defconfig
+++ b/configs/imx8mm_venice_defconfig
@@ -26,9 +26,9 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="gsc wd-disable"
CONFIG_BOARD_LATE_INIT=y
@@ -37,9 +37,9 @@
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
@@ -75,7 +75,7 @@
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="imx8mm-venice imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x imx8mm-venice-gw7901 imx8mm-venice-gw7902 imx8mm-venice-gw7903 imx8mm-venice-gw7904"
+CONFIG_OF_LIST="imx8mm-venice imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x imx8mm-venice-gw7901 imx8mm-venice-gw7902 imx8mm-venice-gw7903 imx8mm-venice-gw7904 imx8mm-venice-gw7905-0x"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_MMC_ENV_DEV=2
diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig
index c88c685..c0d7e3c 100644
--- a/configs/imx8mn_beacon_2g_defconfig
+++ b/configs/imx8mn_beacon_2g_defconfig
@@ -42,10 +42,10 @@
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
@@ -142,4 +142,3 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
-CONFIG_SDP_LOADADDR=0x0
diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig
index 0f3b1eb..9409d51 100644
--- a/configs/imx8mn_beacon_defconfig
+++ b/configs/imx8mn_beacon_defconfig
@@ -41,10 +41,10 @@
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
@@ -149,5 +149,4 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
-CONFIG_SDP_LOADADDR=0x0
CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig
index 3ea98fd..2456803 100644
--- a/configs/imx8mn_beacon_fspi_defconfig
+++ b/configs/imx8mn_beacon_fspi_defconfig
@@ -41,10 +41,10 @@
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
@@ -149,7 +149,6 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
-CONFIG_SDP_LOADADDR=0x0
CONFIG_IMX_WATCHDOG=y
CONFIG_FSPI_CONF_HEADER=y
CONFIG_FSPI_CONF_FILE="fspi_header.bin"
diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig
index c3f250e..657eb35 100644
--- a/configs/imx8mn_bsh_smm_s2_defconfig
+++ b/configs/imx8mn_bsh_smm_s2_defconfig
@@ -23,8 +23,8 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-bsh-smm-s2.dtb"
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
@@ -35,10 +35,10 @@
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_DMA=y
diff --git a/configs/imx8mn_bsh_smm_s2pro_defconfig b/configs/imx8mn_bsh_smm_s2pro_defconfig
index e60087d..52d9972 100644
--- a/configs/imx8mn_bsh_smm_s2pro_defconfig
+++ b/configs/imx8mn_bsh_smm_s2pro_defconfig
@@ -24,8 +24,8 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-bsh-smm-s2pro.dtb"
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
@@ -36,10 +36,10 @@
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig
index 57b64f7..ac5f9fc 100644
--- a/configs/imx8mn_ddr4_evk_defconfig
+++ b/configs/imx8mn_ddr4_evk_defconfig
@@ -22,8 +22,8 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-evk.dtb"
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
@@ -34,10 +34,10 @@
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig
index da329af..0fce798 100644
--- a/configs/imx8mn_evk_defconfig
+++ b/configs/imx8mn_evk_defconfig
@@ -22,8 +22,8 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb"
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
@@ -37,10 +37,10 @@
CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig
index 54f35a0..fa2f43b 100644
--- a/configs/imx8mn_var_som_defconfig
+++ b/configs/imx8mn_var_som_defconfig
@@ -26,9 +26,9 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-var-som-symphony.dtb"
CONFIG_BOARD_TYPES=y
CONFIG_ARCH_MISC_INIT=y
@@ -39,10 +39,10 @@
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig
index 290f866..5d2e5a4 100644
--- a/configs/imx8mn_venice_defconfig
+++ b/configs/imx8mn_venice_defconfig
@@ -27,9 +27,9 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="gsc wd-disable"
CONFIG_BOARD_LATE_INIT=y
@@ -40,10 +40,10 @@
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
index fa56c65..ff27d99 100644
--- a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
+++ b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
@@ -25,8 +25,8 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mp-icore-mx8mp-edimm2.2.dtb"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x26000
@@ -37,10 +37,10 @@
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig
index 70cdabc..b686af8 100644
--- a/configs/imx8mp_beacon_defconfig
+++ b/configs/imx8mp_beacon_defconfig
@@ -38,8 +38,8 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_DEFAULT_FDT_FILE="imx8mp-beacon-kit.dtb"
# CONFIG_SYS_DEVICE_NULLDEV is not set
@@ -51,10 +51,10 @@
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
@@ -172,7 +172,6 @@
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
-CONFIG_SDP_LOADADDR=0x0
CONFIG_USB_FUNCTION_ACM=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig
index bec4e40..cc7d562 100644
--- a/configs/imx8mp_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mp_data_modul_edm_sbc_defconfig
@@ -59,10 +59,10 @@
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x4c000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
@@ -125,7 +125,6 @@
CONFIG_CMD_UUID=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_HASH=y
CONFIG_CMD_SMC=y
CONFIG_HASH_VERIFY=y
CONFIG_CMD_BTRFS=y
@@ -164,6 +163,8 @@
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MP=y
CONFIG_CLK_IMX8MP=y
+CONFIG_FSL_CAAM=y
+CONFIG_IMX8M_DRAM_INLINE_ECC=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y
@@ -182,7 +183,6 @@
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
-CONFIG_MISC=y
CONFIG_USB_HUB_USB251XB=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
@@ -256,7 +256,6 @@
CONFIG_USB_GADGET_MANUFACTURER="Data Modul"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_SDP_LOADADDR=0x0
CONFIG_USB_FUNCTION_ACM=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig
index a891141..dc482ab 100644
--- a/configs/imx8mp_dhcom_pdk2_defconfig
+++ b/configs/imx8mp_dhcom_pdk2_defconfig
@@ -50,17 +50,17 @@
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
+CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x96fc00
CONFIG_SPL_BSS_MAX_SIZE=0x400
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x4c000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
@@ -120,7 +120,6 @@
CONFIG_CMD_UUID=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_HASH=y
CONFIG_CMD_SMC=y
CONFIG_HASH_VERIFY=y
CONFIG_CMD_BTRFS=y
@@ -160,6 +159,8 @@
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MP=y
CONFIG_CLK_IMX8MP=y
+CONFIG_FSL_CAAM=y
+CONFIG_IMX8M_DRAM_INLINE_ECC=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y
@@ -178,7 +179,6 @@
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
-CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SUPPORT_EMMC_BOOT=y
@@ -254,7 +254,6 @@
CONFIG_USB_GADGET_MANUFACTURER="DH electronics"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_SDP_LOADADDR=0x0
CONFIG_USB_FUNCTION_ACM=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig
index 6f00acf..3442af6 100644
--- a/configs/imx8mp_dhcom_pdk3_defconfig
+++ b/configs/imx8mp_dhcom_pdk3_defconfig
@@ -15,7 +15,6 @@
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-dhcom-pdk3"
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_TARGET_IMX8MP_DH_DHCOM_PDK2=y
-CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_SPL_MMC=y
@@ -39,6 +38,7 @@
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
+CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTARGS=y
@@ -51,19 +51,20 @@
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
+CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x96fc00
CONFIG_SPL_BSS_MAX_SIZE=0x400
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x4c000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+# CONFIG_SPL_FIT_IMAGE_TINY is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
@@ -121,7 +122,6 @@
CONFIG_CMD_UUID=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_HASH=y
CONFIG_CMD_SMC=y
CONFIG_HASH_VERIFY=y
CONFIG_CMD_BTRFS=y
@@ -161,6 +161,8 @@
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MP=y
CONFIG_CLK_IMX8MP=y
+CONFIG_FSL_CAAM=y
+CONFIG_IMX8M_DRAM_INLINE_ECC=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y
@@ -174,6 +176,7 @@
CONFIG_GPIO_HOG=y
CONFIG_SPL_GPIO_HOG=y
CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
@@ -181,7 +184,6 @@
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
-CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SUPPORT_EMMC_BOOT=y
@@ -257,7 +259,6 @@
CONFIG_USB_GADGET_MANUFACTURER="DH electronics"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_SDP_LOADADDR=0x0
CONFIG_USB_FUNCTION_ACM=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index da1f5d1..08998a6 100644
--- a/configs/imx8mp_evk_defconfig
+++ b/configs/imx8mp_evk_defconfig
@@ -25,8 +25,8 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x26000
@@ -37,10 +37,10 @@
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
@@ -59,6 +59,9 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
@@ -71,9 +74,18 @@
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eth1"
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_CLK_IMX8MP=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
+CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
CONFIG_MXC_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
@@ -94,10 +106,15 @@
CONFIG_DWC_ETH_QOS_IMX=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_SPL_POWER_LEGACY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
CONFIG_POWER_PCA9450=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
@@ -109,4 +126,18 @@
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_MX7 is not set
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig
index 817d6c65..ca3c3ef 100644
--- a/configs/imx8mp_rsb3720a1_4G_defconfig
+++ b/configs/imx8mp_rsb3720a1_4G_defconfig
@@ -31,9 +31,9 @@
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_DEFAULT_FDT_FILE="imx8mp-rsb3720-a1.dtb"
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
@@ -46,10 +46,10 @@
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig
index faade0a..61d539f 100644
--- a/configs/imx8mp_rsb3720a1_6G_defconfig
+++ b/configs/imx8mp_rsb3720a1_6G_defconfig
@@ -31,9 +31,9 @@
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_DEFAULT_FDT_FILE="imx8mp-rsb3720-a1.dtb"
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
@@ -46,10 +46,10 @@
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig
index 913ec0f..730c359 100644
--- a/configs/imx8mp_venice_defconfig
+++ b/configs/imx8mp_venice_defconfig
@@ -27,9 +27,9 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="gsc wd-disable"
CONFIG_BOARD_LATE_INIT=y
@@ -40,10 +40,10 @@
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
@@ -77,7 +77,7 @@
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="imx8mp-venice imx8mp-venice-gw74xx imx8mp-venice-gw7905-2x"
+CONFIG_OF_LIST="imx8mp-venice imx8mp-venice-gw71xx-2x imx8mp-venice-gw72xx-2x imx8mp-venice-gw73xx-2x imx8mp-venice-gw74xx imx8mp-venice-gw7905-2x"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_MMC_ENV_DEV=2
diff --git a/configs/imx8mq_cm_defconfig b/configs/imx8mq_cm_defconfig
index de15af8..c703671 100644
--- a/configs/imx8mq_cm_defconfig
+++ b/configs/imx8mq_cm_defconfig
@@ -25,8 +25,8 @@
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x1f000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -34,10 +34,10 @@
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index a32150f..72e1757 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -27,8 +27,8 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x1f000
@@ -37,10 +37,10 @@
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig
index 114ddab..35f429f 100644
--- a/configs/imx8mq_phanbell_defconfig
+++ b/configs/imx8mq_phanbell_defconfig
@@ -27,8 +27,8 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SD_BOOT=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_BOARD_EARLY_INIT_F=y
@@ -38,10 +38,10 @@
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig
index 3448b61..e503175 100644
--- a/configs/imx8mq_reform2_defconfig
+++ b/configs/imx8mq_reform2_defconfig
@@ -27,8 +27,8 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="freescale/imx8mq-mnt-reform2.dtb"
CONFIG_CONSOLE_MUX=y
@@ -40,10 +40,10 @@
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8qm_dmsse20a1_defconfig b/configs/imx8qm_dmsse20a1_defconfig
index 70f7b37..01eabc4 100644
--- a/configs/imx8qm_dmsse20a1_defconfig
+++ b/configs/imx8qm_dmsse20a1_defconfig
@@ -26,8 +26,8 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_LOG=y
diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig
index 7f7a20e..d7cf869 100644
--- a/configs/imx8qm_mek_defconfig
+++ b/configs/imx8qm_mek_defconfig
@@ -20,15 +20,13 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0x13e000
CONFIG_SPL=y
-CONFIG_SPL_LOAD_IMX_CONTAINER=y
-CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_LOG=y
@@ -38,12 +36,16 @@
CONFIG_SPL_BSS_START_ADDR=0x128000
CONFIG_SPL_BSS_MAX_SIZE=0x1000
CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x120000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x3000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x3000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_POWER_DOMAIN=y
diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index f34b988..37c5147 100644
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -20,15 +20,13 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0x13e000
CONFIG_SPL=y
-CONFIG_SPL_LOAD_IMX_CONTAINER=y
-CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_LOG=y
@@ -38,12 +36,16 @@
CONFIG_SPL_BSS_START_ADDR=0x128000
CONFIG_SPL_BSS_MAX_SIZE=0x1000
CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x120000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x3000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x3000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_POWER_DOMAIN=y
diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig
index c08db70..7a5147a 100644
--- a/configs/imx8ulp_evk_defconfig
+++ b/configs/imx8ulp_evk_defconfig
@@ -19,7 +19,6 @@
CONFIG_SPL_STACK=0x22050000
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
-CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_SYS_LOAD_ADDR=0x80480000
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
@@ -36,11 +35,12 @@
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x22040000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x8000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x22040000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x8000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_WATCHDOG=y
diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig
index 89130c4..9ced5ed 100644
--- a/configs/imx93_11x11_evk_defconfig
+++ b/configs/imx93_11x11_evk_defconfig
@@ -18,7 +18,6 @@
CONFIG_SPL_STACK=0x20519dd0
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
-CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_SYS_LOAD_ADDR=0x80400000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
@@ -33,11 +32,12 @@
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x83200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
CONFIG_SPL_I2C=y
@@ -81,7 +81,10 @@
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
+CONFIG_ADC=y
CONFIG_ADC_IMX93=y
+CONFIG_SPL_CLK_IMX93=y
+CONFIG_CLK_IMX93=y
CONFIG_CPU=y
CONFIG_CPU_IMX=y
CONFIG_IMX_RGPIO2P=y
diff --git a/configs/imx93_11x11_evk_ld_defconfig b/configs/imx93_11x11_evk_ld_defconfig
index 8084032..abd646b 100644
--- a/configs/imx93_11x11_evk_ld_defconfig
+++ b/configs/imx93_11x11_evk_ld_defconfig
@@ -19,7 +19,6 @@
CONFIG_SPL_STACK=0x20519dd0
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
-CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_SYS_LOAD_ADDR=0x80400000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
@@ -34,11 +33,12 @@
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x83200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
CONFIG_SPL_I2C=y
diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig
index 40210a5..6b63b80 100644
--- a/configs/imxrt1020-evk_defconfig
+++ b/configs/imxrt1020-evk_defconfig
@@ -19,6 +19,8 @@
CONFIG_SPL_SIZE_LIMIT=0x20000
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x20209000
+CONFIG_HAVE_SYS_UBOOT_START=y
+CONFIG_SYS_UBOOT_START=0x800023FD
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SD_BOOT=y
# CONFIG_USE_BOOTCOMMAND is not set
diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig
index 8f7a36f..cbf9469 100644
--- a/configs/imxrt1050-evk_defconfig
+++ b/configs/imxrt1050-evk_defconfig
@@ -21,6 +21,8 @@
CONFIG_SPL_SIZE_LIMIT=0x20000
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x20209000
+CONFIG_HAVE_SYS_UBOOT_START=y
+CONFIG_SYS_UBOOT_START=0x800023FD
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SD_BOOT=y
# CONFIG_USE_BOOTCOMMAND is not set
diff --git a/configs/imxrt1170-evk_defconfig b/configs/imxrt1170-evk_defconfig
index 8320c09..83825da 100644
--- a/configs/imxrt1170-evk_defconfig
+++ b/configs/imxrt1170-evk_defconfig
@@ -21,6 +21,8 @@
CONFIG_SPL_SIZE_LIMIT=0x20000
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x202C0000
+CONFIG_HAVE_SYS_UBOOT_START=y
+CONFIG_SYS_UBOOT_START=0x202403FD
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SD_BOOT=y
# CONFIG_USE_BOOTCOMMAND is not set
diff --git a/configs/inteno_xg6846_ram_defconfig b/configs/inteno_xg6846_ram_defconfig
new file mode 100644
index 0000000..00fe36d
--- /dev/null
+++ b/configs/inteno_xg6846_ram_defconfig
@@ -0,0 +1,73 @@
+CONFIG_MIPS=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_TEXT_BASE=0x81c00000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="inteno,xg6846"
+CONFIG_DM_RESET=y
+CONFIG_IDENT_STRING="Inteno XG6846"
+CONFIG_SYS_LOAD_ADDR=0x81000000
+CONFIG_ARCH_BMIPS=y
+CONFIG_SOC_BMIPS_BCM6328=y
+CONFIG_SYS_MIPS_TIMER_FREQ=160000000
+CONFIG_MIPS_CACHE_SETUP=y
+CONFIG_MIPS_CACHE_DISABLE=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REMAKE_ELF=y
+CONFIG_BOOTDELAY=1
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Boot XG6846 in %d seconds\n"
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe; sf read 0x81000000 0x40000 0x500000; bootm 0x81000000"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_SYS_MALLOC_BOOTPARAMS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="XG6846 # "
+CONFIG_SYS_MAXARGS=24
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=541
+CONFIG_CMD_CPU=y
+CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_BOOTD is not set
+CONFIG_SYS_BOOTM_LEN=0x1000000
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_SLEEP is not set
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_DMA=y
+CONFIG_BCM6348_IUDMA=y
+CONFIG_LED=y
+CONFIG_LED_BCM6328=y
+CONFIG_LED_BLINK=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_RESET_DELAY=20
+CONFIG_POWER_DOMAIN=y
+CONFIG_BCM6328_POWER_DOMAIN=y
+CONFIG_RESET_BCM6345=y
+CONFIG_DM_SERIAL=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_BCM63XX_HSSPI=y
+CONFIG_LZMA=y
diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig
index 4fc3bcb..c2def97 100644
--- a/configs/iot2050_defconfig
+++ b/configs/iot2050_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_K3=y
+# CONFIG_TI_SECURE_DEVICE is not set
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
@@ -29,8 +30,6 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTSTAGE=y
CONFIG_SHOW_BOOT_PROGRESS=y
@@ -39,6 +38,8 @@
CONFIG_AUTOBOOT_FLUSH_STDIN=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE to stop autoboot in %d seconds...\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="run start_watchdog; run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0x58000
@@ -48,8 +49,8 @@
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DM_MAILBOX=y
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index ad8492a..889358a 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
@@ -30,9 +29,9 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;"
CONFIG_LOGLEVEL=7
CONFIG_SPL_MAX_SIZE=0xc0000
@@ -42,8 +41,8 @@
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800
CONFIG_SPL_DMA=y
@@ -114,6 +113,7 @@
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_GPIO_HOG=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
@@ -138,7 +138,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_HBMC_AM654=y
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
@@ -146,6 +145,7 @@
CONFIG_SPI_FLASH_MTD=y
CONFIG_MULTIPLEXER=y
CONFIG_MUX_MMIO=y
+CONFIG_PHY_TI_DP83869=y
CONFIG_PHY_FIXED=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_PHY=y
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index c4dd336..6452c60 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x70000
CONFIG_SPL_GPIO=y
@@ -37,10 +36,10 @@
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
@@ -115,7 +114,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_HBMC_AM654=y
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 214fa8b..99e0e16 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
@@ -30,9 +29,9 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;"
CONFIG_LOGLEVEL=7
CONFIG_SPL_MAX_SIZE=0xc0000
@@ -42,8 +41,8 @@
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
@@ -140,7 +139,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_HBMC_AM654=y
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index cf7bc87..e76ab59 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x70000
CONFIG_SPL_GPIO=y
@@ -42,10 +41,10 @@
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
@@ -127,7 +126,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_HBMC_AM654=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index 09addcb..876f078 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
@@ -30,8 +29,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;"
CONFIG_LOGLEVEL=7
CONFIG_SPL_MAX_SIZE=0xc0000
@@ -41,8 +40,8 @@
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index 1e66ac2..4990e27 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
@@ -42,11 +41,12 @@
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x140000
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig
index 0ff666b..c99be7c 100644
--- a/configs/jesurun_q5_defconfig
+++ b/configs/jesurun_q5_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=312
-CONFIG_MACPWR="PH19"
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/jethub_j100_defconfig b/configs/jethub_j100_defconfig
index 549d551..1e6d5c7 100644
--- a/configs/jethub_j100_defconfig
+++ b/configs/jethub_j100_defconfig
@@ -18,6 +18,10 @@
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
@@ -26,6 +30,7 @@
# CONFIG_CMD_IMI is not set
CONFIG_CMD_EEPROM=y
CONFIG_CMD_ADC=y
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_RANDOM_UUID=y
CONFIG_CMD_I2C=y
@@ -39,6 +44,7 @@
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SARADC_MESON=y
+CONFIG_DFU_RAM=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MESON=y
CONFIG_MMC_MESON_GX=y
diff --git a/configs/jethub_j80_defconfig b/configs/jethub_j80_defconfig
index df9b8f3..b370e5d 100644
--- a/configs/jethub_j80_defconfig
+++ b/configs/jethub_j80_defconfig
@@ -18,6 +18,10 @@
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
@@ -27,6 +31,7 @@
# CONFIG_CMD_IMI is not set
CONFIG_CMD_EEPROM=y
CONFIG_CMD_ADC=y
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_RANDOM_UUID=y
CONFIG_CMD_I2C=y
@@ -40,6 +45,7 @@
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SARADC_MESON=y
+CONFIG_DFU_RAM=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MESON=y
CONFIG_MMC_MESON_GX=y
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index 2a2e5f5..77af459 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -23,10 +23,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra124 (Jetson TK1) # "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2089
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index 44bed00..ab8dea3 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -26,8 +26,8 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_TIMESTAMP=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run init_${boot}; run get_mon_${boot} run_mon; run get_kern_${boot}; run init_fw_rd_${boot}; run get_fdt_${boot}; run run_kern"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
@@ -36,8 +36,8 @@
CONFIG_SPL_BSS_START_ADDR=0xc10fff8
CONFIG_SPL_BSS_MAX_SIZE=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x8000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x8000
CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig
index 55c0182..39086be 100644
--- a/configs/k2e_hs_evm_defconfig
+++ b/configs/k2e_hs_evm_defconfig
@@ -17,8 +17,8 @@
CONFIG_ENV_OFFSET=0x100000
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm"
CONFIG_TIMESTAMP=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run run_mon_hs; run init_${boot}; run get_fit_${boot}; bootm ${addr_fit}#${name_fdt}"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 45c7fad..7a9a379 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -25,8 +25,8 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_TIMESTAMP=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_mon_${boot} run_mon; run set_name_pmmc get_pmmc_${boot} run_pmmc; run get_kern_${boot}; run init_fw_rd_${boot}; run get_fdt_${boot}; run run_kern"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
@@ -35,8 +35,8 @@
CONFIG_SPL_BSS_START_ADDR=0xc0afff8
CONFIG_SPL_BSS_MAX_SIZE=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x8000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x8000
CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig
index 54a980c..f55c21b 100644
--- a/configs/k2g_hs_evm_defconfig
+++ b/configs/k2g_hs_evm_defconfig
@@ -16,8 +16,8 @@
CONFIG_ENV_SIZE=0x40000
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm"
CONFIG_TIMESTAMP=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run run_mon_hs; run init_${boot}; run get_fit_${boot}; bootm ${addr_fit}#${name_fdt}"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index a265178..d5ed309 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -26,8 +26,8 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_TIMESTAMP=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run init_${boot}; run get_mon_${boot} run_mon; run get_kern_${boot}; run init_fw_rd_${boot}; run get_fdt_${boot}; run run_kern"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
@@ -36,8 +36,8 @@
CONFIG_SPL_BSS_START_ADDR=0xc20fff8
CONFIG_SPL_BSS_MAX_SIZE=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x8000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x8000
CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig
index 8c0472d..604042e 100644
--- a/configs/k2hk_hs_evm_defconfig
+++ b/configs/k2hk_hs_evm_defconfig
@@ -17,8 +17,8 @@
CONFIG_ENV_OFFSET=0x100000
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm"
CONFIG_TIMESTAMP=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run run_mon_hs; run init_${boot}; run get_fit_${boot}; bootm ${addr_fit}#${name_fdt}"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 55ddd3c..c405748 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -26,8 +26,8 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_TIMESTAMP=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run init_${boot}; run get_mon_${boot} run_mon; run get_kern_${boot}; run init_fw_rd_${boot}; run get_fdt_${boot}; run run_kern"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
@@ -36,8 +36,8 @@
CONFIG_SPL_BSS_START_ADDR=0xc10fff8
CONFIG_SPL_BSS_MAX_SIZE=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x8000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x8000
CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig
index 38b9b2b..28e9052 100644
--- a/configs/khadas-vim2_defconfig
+++ b/configs/khadas-vim2_defconfig
@@ -16,6 +16,10 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
@@ -24,6 +28,7 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_ADC=y
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -36,6 +41,7 @@
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SARADC_MESON=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/khadas-vim3_android_ab_defconfig b/configs/khadas-vim3_android_ab_defconfig
index ccd6f6f..b41c266 100644
--- a/configs/khadas-vim3_android_ab_defconfig
+++ b/configs/khadas-vim3_android_ab_defconfig
@@ -7,6 +7,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x0
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-khadas-vim3"
CONFIG_OF_LIBFDT_OVERLAY=y
@@ -19,6 +20,10 @@
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
@@ -45,7 +50,10 @@
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_AVB=y
CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_MMC_ENV_PART=2
CONFIG_ADC=y
CONFIG_SARADC_MESON=y
CONFIG_BUTTON=y
diff --git a/configs/khadas-vim3_android_defconfig b/configs/khadas-vim3_android_defconfig
index 5c3d565..88197f5 100644
--- a/configs/khadas-vim3_android_defconfig
+++ b/configs/khadas-vim3_android_defconfig
@@ -7,6 +7,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x0
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-khadas-vim3"
CONFIG_OF_LIBFDT_OVERLAY=y
@@ -19,6 +20,10 @@
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
@@ -43,7 +48,10 @@
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_AVB=y
CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_MMC_ENV_PART=2
CONFIG_ADC=y
CONFIG_SARADC_MESON=y
CONFIG_BUTTON=y
diff --git a/configs/khadas-vim3_defconfig b/configs/khadas-vim3_defconfig
index d611124..5df4b92 100644
--- a/configs/khadas-vim3_defconfig
+++ b/configs/khadas-vim3_defconfig
@@ -18,12 +18,17 @@
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=32
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
@@ -41,6 +46,7 @@
CONFIG_SARADC_MESON=y
CONFIG_BUTTON=y
CONFIG_BUTTON_ADC=y
+CONFIG_DFU_RAM=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MESON=y
CONFIG_MMC_MESON_GX=y
diff --git a/configs/khadas-vim3l_android_ab_defconfig b/configs/khadas-vim3l_android_ab_defconfig
index 0d6de80..3381d2e 100644
--- a/configs/khadas-vim3l_android_ab_defconfig
+++ b/configs/khadas-vim3l_android_ab_defconfig
@@ -7,6 +7,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x0
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-khadas-vim3l"
CONFIG_OF_LIBFDT_OVERLAY=y
@@ -19,6 +20,10 @@
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
@@ -45,7 +50,10 @@
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_AVB=y
CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_MMC_ENV_PART=2
CONFIG_ADC=y
CONFIG_SARADC_MESON=y
CONFIG_BUTTON=y
diff --git a/configs/khadas-vim3l_android_defconfig b/configs/khadas-vim3l_android_defconfig
index 827752f..3fa587e 100644
--- a/configs/khadas-vim3l_android_defconfig
+++ b/configs/khadas-vim3l_android_defconfig
@@ -7,6 +7,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x0
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-khadas-vim3l"
CONFIG_OF_LIBFDT_OVERLAY=y
@@ -19,6 +20,10 @@
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
@@ -43,7 +48,10 @@
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_AVB=y
CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_MMC_ENV_PART=2
CONFIG_ADC=y
CONFIG_SARADC_MESON=y
CONFIG_BUTTON=y
diff --git a/configs/khadas-vim3l_defconfig b/configs/khadas-vim3l_defconfig
index f959d33..de8fdd8 100644
--- a/configs/khadas-vim3l_defconfig
+++ b/configs/khadas-vim3l_defconfig
@@ -18,12 +18,17 @@
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=32
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
@@ -41,6 +46,7 @@
CONFIG_SARADC_MESON=y
CONFIG_BUTTON=y
CONFIG_BUTTON_ADC=y
+CONFIG_DFU_RAM=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MESON=y
CONFIG_MMC_MESON_GX=y
diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig
index 6a9e851..d27ab6f 100644
--- a/configs/khadas-vim_defconfig
+++ b/configs/khadas-vim_defconfig
@@ -16,6 +16,10 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
@@ -24,6 +28,7 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_ADC=y
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -34,6 +39,7 @@
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SARADC_MESON=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_MDIO=y
diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig
index 0faf3ff..2cf9565 100644
--- a/configs/kmcent2_defconfig
+++ b/configs/kmcent2_defconfig
@@ -21,11 +21,11 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_KM_IVM_BUS=2
CONFIG_MP=y
+CONFIG_SYS_MONITOR_BASE=0xEBF40000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_MONITOR_BASE=0xEBF40000
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_LAST_STAGE_INIT=y
diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig
index 0849445..257ceec 100644
--- a/configs/kmcoge5ne_defconfig
+++ b/configs/kmcoge5ne_defconfig
@@ -122,11 +122,11 @@
CONFIG_LCRR_CLKDIV_4=y
CONFIG_83XX_PCICLK=0x3ef1480
# CONFIG_PCI is not set
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_HWCONFIG is not set
CONFIG_LAST_STAGE_INIT=y
diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig
index 834e040..46e0370 100644
--- a/configs/kmeter1_defconfig
+++ b/configs/kmeter1_defconfig
@@ -102,11 +102,11 @@
CONFIG_LCRR_EADC_2=y
CONFIG_LCRR_CLKDIV_4=y
# CONFIG_PCI is not set
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_HWCONFIG is not set
CONFIG_LAST_STAGE_INIT=y
diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig
index c6fbd39..c6c021a 100644
--- a/configs/kmopti2_defconfig
+++ b/configs/kmopti2_defconfig
@@ -110,11 +110,11 @@
CONFIG_LCRR_CLKDIV_2=y
CONFIG_83XX_PCICLK=0x3ef1480
# CONFIG_PCI is not set
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_HWCONFIG is not set
CONFIG_LAST_STAGE_INIT=y
diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig
index 433f6a1..25642e7 100644
--- a/configs/kmsupx5_defconfig
+++ b/configs/kmsupx5_defconfig
@@ -96,11 +96,11 @@
CONFIG_LCRR_CLKDIV_2=y
CONFIG_83XX_PCICLK=0x3ef1480
# CONFIG_PCI is not set
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_HWCONFIG is not set
CONFIG_LAST_STAGE_INIT=y
diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig
index a8adde1..ea37a29 100644
--- a/configs/kmtepr2_defconfig
+++ b/configs/kmtepr2_defconfig
@@ -110,11 +110,11 @@
CONFIG_LCRR_CLKDIV_2=y
CONFIG_83XX_PCICLK=0x3ef1480
# CONFIG_PCI is not set
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_HWCONFIG is not set
CONFIG_LAST_STAGE_INIT=y
diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig
index d54e603..1e3a6b5 100644
--- a/configs/kontron-sl-mx6ul_defconfig
+++ b/configs/kontron-sl-mx6ul_defconfig
@@ -25,15 +25,16 @@
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_TYPES=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
CONFIG_SPL_WATCHDOG=y
@@ -107,4 +108,3 @@
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SPL_USB_SDP_SUPPORT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig
index 9558cf1..78e44ab 100644
--- a/configs/kontron-sl-mx8mm_defconfig
+++ b/configs/kontron-sl-mx8mm_defconfig
@@ -29,8 +29,8 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOARD_TYPES=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -38,10 +38,10 @@
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/kontron_pitx_imx8m_defconfig b/configs/kontron_pitx_imx8m_defconfig
index 295cc51..6e9b289 100644
--- a/configs/kontron_pitx_imx8m_defconfig
+++ b/configs/kontron_pitx_imx8m_defconfig
@@ -27,8 +27,8 @@
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_MISC_INIT_R=y
@@ -37,10 +37,10 @@
CONFIG_SPL_BSS_START_ADDR=0x180000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig
index 8fe2798..ef01452 100644
--- a/configs/kontron_sl28_defconfig
+++ b/configs/kontron_sl28_defconfig
@@ -20,7 +20,6 @@
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0x18009ff0
CONFIG_SPL_SIZE_LIMIT=0x20000
-CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x3f0000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -34,10 +33,10 @@
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOARD_LATE_INIT=y
# CONFIG_HWCONFIG is not set
@@ -48,7 +47,7 @@
CONFIG_SPL_BSS_MAX_SIZE=0x100000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x900
CONFIG_SPL_MPC8XXX_INIT_DDR=y
@@ -130,7 +129,6 @@
CONFIG_WDT=y
CONFIG_WDT_SL28CPLD=y
CONFIG_WDT_SP805=y
-CONFIG_OF_LIBFDT_ASSUME_MASK=0x0
CONFIG_EFI_SET_TIME=y
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig
index dbfb0ba..3a7763c 100644
--- a/configs/kp_imx6q_tpc_defconfig
+++ b/configs/kp_imx6q_tpc_defconfig
@@ -28,7 +28,7 @@
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
diff --git a/configs/kstr_sama5d27_defconfig b/configs/kstr_sama5d27_defconfig
new file mode 100644
index 0000000..fa7a549
--- /dev/null
+++ b/configs/kstr_sama5d27_defconfig
@@ -0,0 +1,73 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TEXT_BASE=0x26f00000
+CONFIG_TARGET_KSTR_SAMA5D27=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-kstr-sama5d27"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_SYS_LOAD_ADDR=0x24000000
+CONFIG_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
+# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_TLV_EEPROM=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
+CONFIG_MICROCHIP_FLEXCOM=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_PHY_MICREL=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_RESET_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATMEL_USART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_AT91=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x16c0
+CONFIG_USB_GADGET_PRODUCT_NUM=0x03e9
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 1aab157..8d3f1a7 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -45,7 +45,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-# CONFIG_SPL_BLK is not set
CONFIG_CLK=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
diff --git a/configs/librem5_defconfig b/configs/librem5_defconfig
index 166ef5f..7f630ed 100644
--- a/configs/librem5_defconfig
+++ b/configs/librem5_defconfig
@@ -27,9 +27,9 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=0
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_SYS_DEVICE_NULLDEV is not set
CONFIG_ARCH_MISC_INIT=y
@@ -41,10 +41,10 @@
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig
index 0fa7f3d..bc17b42 100644
--- a/configs/libretech-ac_defconfig
+++ b/configs/libretech-ac_defconfig
@@ -19,6 +19,10 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
@@ -28,6 +32,7 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_ADC=y
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -41,6 +46,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SARADC_MESON=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig
index dee03b3..baa9b1b 100644
--- a/configs/libretech-cc_defconfig
+++ b/configs/libretech-cc_defconfig
@@ -16,6 +16,10 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
@@ -23,6 +27,7 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_ADC=y
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -33,6 +38,7 @@
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SARADC_MESON=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_MDIO=y
diff --git a/configs/libretech-cc_v2_defconfig b/configs/libretech-cc_v2_defconfig
index 628c6ba..b1c267a 100644
--- a/configs/libretech-cc_v2_defconfig
+++ b/configs/libretech-cc_v2_defconfig
@@ -18,6 +18,10 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
@@ -26,6 +30,7 @@
CONFIG_SYS_MAXARGS=32
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -37,6 +42,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SARADC_MESON=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
@@ -60,6 +66,7 @@
CONFIG_DM_SPI=y
CONFIG_MESON_SPIFC=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
diff --git a/configs/libretech-s905d-pc_defconfig b/configs/libretech-s905d-pc_defconfig
index 1c8787c..cd138d6 100644
--- a/configs/libretech-s905d-pc_defconfig
+++ b/configs/libretech-s905d-pc_defconfig
@@ -19,6 +19,10 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
@@ -27,6 +31,7 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_ADC=y
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -39,6 +44,7 @@
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SARADC_MESON=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/libretech-s912-pc_defconfig b/configs/libretech-s912-pc_defconfig
index 170492e..dabb4ca 100644
--- a/configs/libretech-s912-pc_defconfig
+++ b/configs/libretech-s912-pc_defconfig
@@ -18,6 +18,10 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
@@ -26,6 +30,7 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_ADC=y
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -38,6 +43,7 @@
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SARADC_MESON=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
index 7c55b3b..9c29eb6 100644
--- a/configs/lion-rk3368_defconfig
+++ b/configs/lion-rk3368_defconfig
@@ -10,7 +10,6 @@
CONFIG_DEFAULT_DEVICE_TREE="rk3368-lion-haikou"
CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_ROCKCHIP_RK3368=y
-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig
index 83be20f..1ff5b3c 100644
--- a/configs/liteboard_defconfig
+++ b/configs/liteboard_defconfig
@@ -25,7 +25,7 @@
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_DEFAULT_FDT_FILE="imx6ul-liteboard.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig
deleted file mode 100644
index 72b590a..0000000
--- a/configs/ls1012a2g5rdb_qspi_defconfig
+++ /dev/null
@@ -1,69 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1012A2G5RDB=y
-CONFIG_TEXT_BASE=0x40100000
-CONFIG_SYS_MALLOC_LEN=0x500000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb"
-CONFIG_FSL_LS_PPA=y
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_SPANSION=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_FSL_PFE=y
-CONFIG_DM_RTC=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig
index a99afe3..199f36a 100644
--- a/configs/ls1012a2g5rdb_tfa_defconfig
+++ b/configs/ls1012a2g5rdb_tfa_defconfig
@@ -19,10 +19,10 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
deleted file mode 100644
index 7e12f6e..0000000
--- a/configs/ls1012afrdm_qspi_defconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1012AFRDM=y
-CONFIG_TEXT_BASE=0x40100000
-CONFIG_SYS_MALLOC_LEN=0x500000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
-CONFIG_FSL_LS_PPA=y
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_PCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
-CONFIG_BOOTCOMMAND="run distro_bootcmd;run qspi_bootcmd"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_SPANSION=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_FSL_PFE=y
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig
index 3c9a748..ec900bd 100644
--- a/configs/ls1012afrdm_tfa_defconfig
+++ b/configs/ls1012afrdm_tfa_defconfig
@@ -19,10 +19,10 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
deleted file mode 100644
index 4e5079d..0000000
--- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,72 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1012AFRWY=y
-CONFIG_TEXT_BASE=0x40100000
-CONFIG_SYS_MALLOC_LEN=0x500000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
-CONFIG_FSL_LS_PPA=y
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_NXP_ESBC=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_FSL_SEC_MON_BE=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_FSL_PFE=y
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_RTC=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig
deleted file mode 100644
index b944f80..0000000
--- a/configs/ls1012afrwy_qspi_defconfig
+++ /dev/null
@@ -1,72 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1012AFRWY=y
-CONFIG_TEXT_BASE=0x40100000
-CONFIG_SYS_MALLOC_LEN=0x500000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x1D0000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
-CONFIG_FSL_LS_PPA=y
-CONFIG_ENV_ADDR=0x401D0000
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_FSL_PFE=y
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_RTC=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
index 56dcbcc..5e95c6e 100644
--- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
@@ -19,10 +19,10 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig
index 90083fa..d10886f 100644
--- a/configs/ls1012afrwy_tfa_defconfig
+++ b/configs/ls1012afrwy_tfa_defconfig
@@ -20,10 +20,10 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
deleted file mode 100644
index 34bdb1a..0000000
--- a/configs/ls1012aqds_qspi_defconfig
+++ /dev/null
@@ -1,95 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1012AQDS=y
-CONFIG_TEXT_BASE=0x40100000
-CONFIG_SYS_MALLOC_LEN=0x500000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
-CONFIG_FSL_LS_PPA=y
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_FSL_QIXIS=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
-CONFIG_ID_EEPROM=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SPI=y
-CONFIG_DEFAULT_SPI_BUS=1
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_SPI_BUS=0
-CONFIG_ENV_SPI_MAX_HZ=1000000
-CONFIG_ENV_SPI_MODE=0x03
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_BUS=1
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_FSL_PFE=y
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_PCF8563=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
index dc0f1c5..06aaa42 100644
--- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
@@ -21,10 +21,10 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
# CONFIG_USE_BOOTCOMMAND is not set
diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig
index 7884f38..594ad12 100644
--- a/configs/ls1012aqds_tfa_defconfig
+++ b/configs/ls1012aqds_tfa_defconfig
@@ -23,10 +23,10 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
# CONFIG_USE_BOOTCOMMAND is not set
diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
deleted file mode 100644
index dcd18b4..0000000
--- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,77 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1012ARDB=y
-CONFIG_TEXT_BASE=0x40100000
-CONFIG_SYS_MALLOC_LEN=0x500000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
-CONFIG_FSL_LS_PPA=y
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_NXP_ESBC=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_FSL_SEC_MON_BE=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_SPANSION=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_RTC=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
deleted file mode 100644
index 10fe826..0000000
--- a/configs/ls1012ardb_qspi_defconfig
+++ /dev/null
@@ -1,77 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1012ARDB=y
-CONFIG_TEXT_BASE=0x40100000
-CONFIG_SYS_MALLOC_LEN=0x500000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
-CONFIG_FSL_LS_PPA=y
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_ENV_ADDR=0x40300000
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_SPANSION=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_FSL_PFE=y
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_RTC=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
index 336692b..ac2c9cc 100644
--- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
@@ -20,10 +20,10 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
# CONFIG_USE_BOOTCOMMAND is not set
diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig
index 647e8ea..cc0f046 100644
--- a/configs/ls1012ardb_tfa_defconfig
+++ b/configs/ls1012ardb_tfa_defconfig
@@ -21,10 +21,10 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig
index 0c72f8a..c705345 100644
--- a/configs/ls1021aiot_qspi_defconfig
+++ b/configs/ls1021aiot_qspi_defconfig
@@ -19,9 +19,9 @@
CONFIG_LAYERSCAPE_NS_ACCESS=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_QSPI_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_QSPI_BOOT=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig
index b271792..5927d3e 100644
--- a/configs/ls1021aiot_sdcard_defconfig
+++ b/configs/ls1021aiot_sdcard_defconfig
@@ -26,13 +26,13 @@
CONFIG_LAYERSCAPE_NS_ACCESS=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aiot/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg"
CONFIG_SD_BOOT=y
CONFIG_SD_BOOT_QSPI=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
@@ -44,9 +44,9 @@
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SPL_FSL_PBL=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x82080000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82080000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index b28ae07..5a4c364 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -24,12 +24,12 @@
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index 136246b..094a7b1 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -24,12 +24,12 @@
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index ee569ea..2279544 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -32,16 +32,16 @@
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg"
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
@@ -54,9 +54,9 @@
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SPL_FSL_PBL=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80200000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80200000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index 78eb747..a3ed4cf 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -24,12 +24,12 @@
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index 04223a9..07f47fa 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -24,12 +24,12 @@
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index 3a7bc40..c6b0fc4 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -24,12 +24,12 @@
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index cfb6bcf..008c49b 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -25,10 +25,10 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index 25bd6c7..c639eb2 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -33,9 +33,9 @@
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg"
@@ -53,9 +53,9 @@
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SPL_FSL_PBL=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x820c0000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x820c0000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index 2845386..8e4b218 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -52,9 +52,9 @@
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SPL_FSL_PBL=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x820c0000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x820c0000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig
index f0ab507..a1faabd 100644
--- a/configs/ls1021atsn_qspi_defconfig
+++ b/configs/ls1021atsn_qspi_defconfig
@@ -19,11 +19,11 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SILENT_CONSOLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig
index 7a8b157..e78f27e 100644
--- a/configs/ls1021atsn_sdcard_defconfig
+++ b/configs/ls1021atsn_sdcard_defconfig
@@ -26,8 +26,6 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atsn/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg"
@@ -35,6 +33,8 @@
CONFIG_SD_BOOT=y
CONFIG_SD_BOOT_QSPI=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SILENT_CONSOLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
@@ -46,9 +46,9 @@
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SPL_FSL_PBL=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x82100000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82100000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index dcb48c3..9afa09b 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -23,10 +23,10 @@
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd;env exists secureboot && esbc_halt;"
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index 61e9edf..d476f2b 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -23,10 +23,10 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd;env exists secureboot && esbc_halt;"
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index 9975f6a..f6a2def 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -23,10 +23,10 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd;env exists secureboot && esbc_halt;"
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index 2e7d786..c654320 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -23,11 +23,11 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt"
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index 4a42427..376a3e4 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -31,14 +31,14 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atwr/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=0
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;"
@@ -54,9 +54,9 @@
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SPL_FSL_PBL=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x82104000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82104000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index 34b229e..0a84595 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -31,14 +31,14 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atwr/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;"
@@ -55,9 +55,9 @@
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SPL_FSL_PBL=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x82100000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82100000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 3738107..26d302c 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -31,8 +31,6 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atwr/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg"
@@ -40,6 +38,8 @@
CONFIG_SD_BOOT=y
CONFIG_SD_BOOT_QSPI=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt"
@@ -56,9 +56,9 @@
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SPL_FSL_PBL=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x82100000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82100000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
index 63c5506..5bf649a 100644
--- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
@@ -24,10 +24,10 @@
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
CONFIG_MISC_INIT_R=y
diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig
index 149bc57..c36e116 100644
--- a/configs/ls1028aqds_tfa_defconfig
+++ b/configs/ls1028aqds_tfa_defconfig
@@ -26,10 +26,10 @@
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
CONFIG_MISC_INIT_R=y
diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig
index 4750a57..0691c01 100644
--- a/configs/ls1028aqds_tfa_lpuart_defconfig
+++ b/configs/ls1028aqds_tfa_lpuart_defconfig
@@ -25,10 +25,10 @@
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
CONFIG_MISC_INIT_R=y
diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
index 9be2f32..a3d936b 100644
--- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
@@ -24,10 +24,10 @@
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
CONFIG_ID_EEPROM=y
diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig
index d158187..de893ff 100644
--- a/configs/ls1028ardb_tfa_defconfig
+++ b/configs/ls1028ardb_tfa_defconfig
@@ -26,10 +26,10 @@
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
CONFIG_ID_EEPROM=y
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
deleted file mode 100644
index 18bf4bd..0000000
--- a/configs/ls1043aqds_defconfig
+++ /dev/null
@@ -1,107 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1043AQDS=y
-CONFIG_TEXT_BASE=0x60100000
-CONFIG_SYS_MALLOC_LEN=0x120000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
-CONFIG_FSL_LS_PPA=y
-CONFIG_ENV_ADDR=0x60300000
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
-CONFIG_VOL_MONITOR_INA220=y
-CONFIG_VOL_MONITOR_IR36021_SET=y
-CONFIG_FSL_QIXIS=y
-# CONFIG_QIXIS_I2C_ACCESS is not set
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
-CONFIG_DYNAMIC_DDR_CLK_FREQ=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig
deleted file mode 100644
index 9dcbe71..0000000
--- a/configs/ls1043aqds_lpuart_defconfig
+++ /dev/null
@@ -1,109 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1043AQDS=y
-CONFIG_TEXT_BASE=0x60100000
-CONFIG_SYS_MALLOC_LEN=0x120000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart"
-CONFIG_FSL_LS_PPA=y
-CONFIG_ENV_ADDR=0x60300000
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
-CONFIG_VOL_MONITOR_INA220=y
-CONFIG_VOL_MONITOR_IR36021_SET=y
-CONFIG_FSL_QIXIS=y
-# CONFIG_QIXIS_I2C_ACCESS is not set
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
-CONFIG_DYNAMIC_DDR_CLK_FREQ=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
-CONFIG_DM_SERIAL=y
-CONFIG_FSL_LPUART=y
-CONFIG_LPUART=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
deleted file mode 100644
index e5f570a..0000000
--- a/configs/ls1043aqds_nand_defconfig
+++ /dev/null
@@ -1,138 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1043AQDS=y
-CONFIG_TEXT_BASE=0x82000000
-CONFIG_SYS_MALLOC_LEN=0x102000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
-CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_FSL_LS_PPA=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x1001d000
-CONFIG_SPL=y
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
-CONFIG_VOL_MONITOR_INA220=y
-CONFIG_VOL_MONITOR_IR36021_SET=y
-CONFIG_FSL_QIXIS=y
-# CONFIG_QIXIS_I2C_ACCESS is not set
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_RAMBOOT_PBL=y
-CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg"
-CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg"
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NAND_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_MAX_SIZE=0x1a000
-CONFIG_SPL_PAD_TO=0x20000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x80100000
-CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SPL_FSL_PBL=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80200000
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
-CONFIG_DYNAMIC_DDR_CLK_FREQ=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
-CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
-CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
deleted file mode 100644
index 67d8288..0000000
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ /dev/null
@@ -1,108 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1043AQDS=y
-CONFIG_TEXT_BASE=0x60100000
-CONFIG_SYS_MALLOC_LEN=0x120000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
-CONFIG_FSL_LS_PPA=y
-CONFIG_ENV_ADDR=0x60300000
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
-CONFIG_VOL_MONITOR_INA220=y
-CONFIG_VOL_MONITOR_IR36021_SET=y
-CONFIG_FSL_QIXIS=y
-# CONFIG_QIXIS_I2C_ACCESS is not set
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
-CONFIG_DYNAMIC_DDR_CLK_FREQ=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
deleted file mode 100644
index fa0b47f..0000000
--- a/configs/ls1043aqds_qspi_defconfig
+++ /dev/null
@@ -1,98 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1043AQDS=y
-CONFIG_TEXT_BASE=0x40100000
-CONFIG_SYS_MALLOC_LEN=0x102000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
-CONFIG_FSL_LS_PPA=y
-CONFIG_ENV_ADDR=0x40300000
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
-CONFIG_VOL_MONITOR_INA220=y
-CONFIG_VOL_MONITOR_IR36021_SET=y
-CONFIG_FSL_QIXIS=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
-CONFIG_DYNAMIC_DDR_CLK_FREQ=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_EARLY_INIT=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
deleted file mode 100644
index 6cb961d..0000000
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ /dev/null
@@ -1,135 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1043AQDS=y
-CONFIG_TEXT_BASE=0x82000000
-CONFIG_SYS_MALLOC_LEN=0x102000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
-CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_FSL_LS_PPA=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x1001e000
-CONFIG_SPL=y
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
-CONFIG_VOL_MONITOR_INA220=y
-CONFIG_VOL_MONITOR_IR36021_SET=y
-CONFIG_FSL_QIXIS=y
-# CONFIG_QIXIS_I2C_ACCESS is not set
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_RAMBOOT_PBL=y
-CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg"
-CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg"
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SD_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_MAX_SIZE=0x17000
-CONFIG_SPL_PAD_TO=0x1d000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x8f000000
-CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SPL_FSL_PBL=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
-CONFIG_DYNAMIC_DDR_CLK_FREQ=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
deleted file mode 100644
index 4e41508..0000000
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ /dev/null
@@ -1,124 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1043AQDS=y
-CONFIG_TEXT_BASE=0x82000000
-CONFIG_SYS_MALLOC_LEN=0x102000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
-CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_FSL_LS_PPA=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x1001e000
-CONFIG_SPL=y
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
-CONFIG_VOL_MONITOR_INA220=y
-CONFIG_VOL_MONITOR_IR36021_SET=y
-CONFIG_FSL_QIXIS=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_RAMBOOT_PBL=y
-CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg"
-CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg"
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SD_BOOT=y
-CONFIG_SD_BOOT_QSPI=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_MAX_SIZE=0x17000
-CONFIG_SPL_PAD_TO=0x1d000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x8f000000
-CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SPL_FSL_PBL=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
-CONFIG_DYNAMIC_DDR_CLK_FREQ=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_EARLY_INIT=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
index 3e1d234..8bb93d5 100644
--- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
@@ -31,11 +31,11 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
+CONFIG_FIT_VERBOSE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig
index 2c50162..59ee11e 100644
--- a/configs/ls1043aqds_tfa_defconfig
+++ b/configs/ls1043aqds_tfa_defconfig
@@ -33,11 +33,11 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
+CONFIG_FIT_VERBOSE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
deleted file mode 100644
index ea195d7..0000000
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,99 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1043ARDB=y
-CONFIG_TEXT_BASE=0x60100000
-CONFIG_SYS_MALLOC_LEN=0x120000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x20000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
-CONFIG_FSL_LS_PPA=y
-CONFIG_PCI=y
-CONFIG_OF_BOARD_FIXUP=y
-CONFIG_NXP_ESBC=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;"
-CONFIG_MISC_INIT_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_IMLS=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="FM1@DTSEC3"
-# CONFIG_DDR_SPD is not set
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_DDR_RAW_TIMING=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_FSL_SEC_MON_BE=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x53
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_DM_MDIO=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_SYS_FMAN_FW_ADDR=0x60900000
-CONFIG_NVME_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_SYS_QE_FW_ADDR=0x60940000
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
deleted file mode 100644
index ae8600f..0000000
--- a/configs/ls1043ardb_defconfig
+++ /dev/null
@@ -1,100 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1043ARDB=y
-CONFIG_TEXT_BASE=0x60100000
-CONFIG_SYS_MALLOC_LEN=0x120000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
-CONFIG_FSL_LS_PPA=y
-CONFIG_ENV_ADDR=0x60300000
-CONFIG_PCI=y
-CONFIG_OF_BOARD_FIXUP=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;"
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_IMLS=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="FM1@DTSEC3"
-CONFIG_FSL_CAAM=y
-# CONFIG_DDR_SPD is not set
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_DDR_RAW_TIMING=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x53
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_DM_MDIO=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_SYS_FMAN_FW_ADDR=0x60900000
-CONFIG_NVME_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_SYS_QE_FW_ADDR=0x60940000
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
deleted file mode 100644
index d9ff0fd..0000000
--- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,124 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1043ARDB=y
-CONFIG_TEXT_BASE=0x82000000
-CONFIG_SYS_MALLOC_LEN=0x102000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
-CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_FSL_LS_PPA=y
-CONFIG_SYS_MONITOR_LEN=1064960
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x1001d000
-CONFIG_SPL=y
-CONFIG_PCI=y
-CONFIG_OF_BOARD_FIXUP=y
-CONFIG_NXP_ESBC=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_RAMBOOT_PBL=y
-CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043ardb/ls1043ardb_pbi.cfg"
-CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg"
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NAND_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_MAX_SIZE=0x1a000
-CONFIG_SPL_PAD_TO=0x20000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x80100000
-CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SPL_FSL_PBL=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80200000
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_IMLS=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="FM1@DTSEC3"
-CONFIG_SPL_DM=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_FSL_SEC_MON_BE=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x53
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
-CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
-CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_DM_MDIO=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-# CONFIG_SPL_USE_TINY_PRINTF is not set
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
deleted file mode 100644
index ad11818..0000000
--- a/configs/ls1043ardb_nand_defconfig
+++ /dev/null
@@ -1,128 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1043ARDB=y
-CONFIG_TEXT_BASE=0x82000000
-CONFIG_SYS_MALLOC_LEN=0x102000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
-CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_FSL_LS_PPA=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x1001d000
-CONFIG_SPL=y
-CONFIG_PCI=y
-CONFIG_OF_BOARD_FIXUP=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_RAMBOOT_PBL=y
-CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043ardb/ls1043ardb_pbi.cfg"
-CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg"
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NAND_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_MAX_SIZE=0x1a000
-CONFIG_SPL_PAD_TO=0x20000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x80100000
-CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_BOARD_INIT=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80200000
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_IMLS=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="FM1@DTSEC3"
-CONFIG_FSL_CAAM=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x53
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
-CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
-CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_DM_MDIO=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPL_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-# CONFIG_SPL_USE_TINY_PRINTF is not set
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
deleted file mode 100644
index fe0dd04..0000000
--- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,124 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1043ARDB=y
-CONFIG_TEXT_BASE=0x82000000
-CONFIG_SYS_MALLOC_LEN=0x102000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
-CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_FSL_LS_PPA=y
-CONFIG_SYS_MONITOR_LEN=1064960
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x1001e000
-CONFIG_SPL=y
-CONFIG_PCI=y
-CONFIG_OF_BOARD_FIXUP=y
-CONFIG_NXP_ESBC=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_RAMBOOT_PBL=y
-CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043ardb/ls1043ardb_pbi.cfg"
-CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg"
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SD_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;"
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_MAX_SIZE=0x17000
-CONFIG_SPL_PAD_TO=0x1d000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x8f000000
-CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SPL_FSL_PBL=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_SPL=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="FM1@DTSEC3"
-CONFIG_SPL_DM=y
-# CONFIG_SPL_BLK is not set
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_FSL_SEC_MON_BE=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x53
-# CONFIG_SPL_DM_MMC is not set
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_DM_MDIO=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_SYS_QE_FW_ADDR=0x940000
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-# CONFIG_SPL_USE_TINY_PRINTF is not set
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
deleted file mode 100644
index aa5404c..0000000
--- a/configs/ls1043ardb_sdcard_defconfig
+++ /dev/null
@@ -1,126 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1043ARDB=y
-CONFIG_TEXT_BASE=0x82000000
-CONFIG_SYS_MALLOC_LEN=0x102000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
-CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_FSL_LS_PPA=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x1001e000
-CONFIG_SPL=y
-CONFIG_PCI=y
-CONFIG_OF_BOARD_FIXUP=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_RAMBOOT_PBL=y
-CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043ardb/ls1043ardb_pbi.cfg"
-CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg"
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SD_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;"
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_MAX_SIZE=0x17000
-CONFIG_SPL_PAD_TO=0x1d000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x8f000000
-CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_BOARD_INIT=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_SPL=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="FM1@DTSEC3"
-CONFIG_FSL_CAAM=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x53
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_DM_MDIO=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_SYS_QE_FW_ADDR=0x940000
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPL_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-# CONFIG_SPL_USE_TINY_PRINTF is not set
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
index 480e928..72685a2 100644
--- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
@@ -24,9 +24,9 @@
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
CONFIG_MISC_INIT_R=y
diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig
index e259041..21518d2 100644
--- a/configs/ls1043ardb_tfa_defconfig
+++ b/configs/ls1043ardb_tfa_defconfig
@@ -26,9 +26,9 @@
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
index d280cf8..6f1d71b 100644
--- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
@@ -22,8 +22,8 @@
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig
index 207f411..b58d989 100644
--- a/configs/ls1046afrwy_tfa_defconfig
+++ b/configs/ls1046afrwy_tfa_defconfig
@@ -24,9 +24,9 @@
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig
deleted file mode 100644
index 5bdcc86..0000000
--- a/configs/ls1046aqds_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,108 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1046AQDS=y
-CONFIG_TEXT_BASE=0x60100000
-CONFIG_SYS_MALLOC_LEN=0x120000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x20000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
-CONFIG_FSL_LS_PPA=y
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_NXP_ESBC=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
-CONFIG_VOL_MONITOR_INA220=y
-CONFIG_VOL_MONITOR_IR36021_SET=y
-CONFIG_FSL_QIXIS=y
-# CONFIG_QIXIS_I2C_ACCESS is not set
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;;"
-CONFIG_MISC_INIT_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_DYNAMIC_DDR_CLK_FREQ=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_FSL_SEC_MON_BE=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_SYS_MAX_FLASH_BANKS=2
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_PCIE_LAYERSCAPE_EP=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_RSA=y
diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig
deleted file mode 100644
index 51aa5dc..0000000
--- a/configs/ls1046aqds_defconfig
+++ /dev/null
@@ -1,110 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1046AQDS=y
-CONFIG_TEXT_BASE=0x60100000
-CONFIG_SYS_MALLOC_LEN=0x120000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
-CONFIG_FSL_LS_PPA=y
-CONFIG_ENV_ADDR=0x60300000
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
-CONFIG_VOL_MONITOR_INA220=y
-CONFIG_VOL_MONITOR_IR36021_SET=y
-CONFIG_FSL_QIXIS=y
-# CONFIG_QIXIS_I2C_ACCESS is not set
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;;"
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
-CONFIG_DYNAMIC_DDR_CLK_FREQ=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_SYS_MAX_FLASH_BANKS=2
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_PCIE_LAYERSCAPE_EP=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig
deleted file mode 100644
index 9c1df24..0000000
--- a/configs/ls1046aqds_lpuart_defconfig
+++ /dev/null
@@ -1,112 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1046AQDS=y
-CONFIG_TEXT_BASE=0x60100000
-CONFIG_SYS_MALLOC_LEN=0x120000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-lpuart"
-CONFIG_FSL_LS_PPA=y
-CONFIG_ENV_ADDR=0x60300000
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
-CONFIG_VOL_MONITOR_INA220=y
-CONFIG_VOL_MONITOR_IR36021_SET=y
-CONFIG_FSL_QIXIS=y
-# CONFIG_QIXIS_I2C_ACCESS is not set
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;;"
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
-CONFIG_DYNAMIC_DDR_CLK_FREQ=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_SYS_MAX_FLASH_BANKS=2
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_PCIE_LAYERSCAPE_EP=y
-CONFIG_DM_SCSI=y
-CONFIG_DM_SERIAL=y
-CONFIG_FSL_LPUART=y
-CONFIG_LPUART=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig
deleted file mode 100644
index 95616f9..0000000
--- a/configs/ls1046aqds_nand_defconfig
+++ /dev/null
@@ -1,139 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1046AQDS=y
-CONFIG_TEXT_BASE=0x82000000
-CONFIG_SYS_MALLOC_LEN=0x102000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
-CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_FSL_LS_PPA=y
-CONFIG_SYS_MONITOR_LEN=655360
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x1001f000
-CONFIG_SPL=y
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
-CONFIG_VOL_MONITOR_INA220=y
-CONFIG_VOL_MONITOR_IR36021_SET=y
-CONFIG_FSL_QIXIS=y
-# CONFIG_QIXIS_I2C_ACCESS is not set
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_RAMBOOT_PBL=y
-CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046aqds/ls1046aqds_pbi.cfg"
-CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg"
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NAND_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run nand_bootcmd; env exists secureboot && esbc_halt;;"
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_MAX_SIZE=0x17000
-CONFIG_SPL_PAD_TO=0x40000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x8f000000
-CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_BOARD_INIT=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
-CONFIG_DYNAMIC_DDR_CLK_FREQ=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_SYS_MAX_FLASH_BANKS=2
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
-CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
-CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_PCIE_LAYERSCAPE_EP=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig
deleted file mode 100644
index f3796f3..0000000
--- a/configs/ls1046aqds_qspi_defconfig
+++ /dev/null
@@ -1,101 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1046AQDS=y
-CONFIG_TEXT_BASE=0x40100000
-CONFIG_SYS_MALLOC_LEN=0x102000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
-CONFIG_FSL_LS_PPA=y
-CONFIG_ENV_ADDR=0x40300000
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
-CONFIG_VOL_MONITOR_INA220=y
-CONFIG_VOL_MONITOR_IR36021_SET=y
-CONFIG_FSL_QIXIS=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:2m(uboot),14m(free)"
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;;"
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:2m(uboot),14m(free)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
-CONFIG_DYNAMIC_DDR_CLK_FREQ=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_EARLY_INIT=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_PCIE_LAYERSCAPE_EP=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig
deleted file mode 100644
index 179fa70..0000000
--- a/configs/ls1046aqds_sdcard_ifc_defconfig
+++ /dev/null
@@ -1,139 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1046AQDS=y
-CONFIG_TEXT_BASE=0x82000000
-CONFIG_SYS_MALLOC_LEN=0x102000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
-CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_FSL_LS_PPA=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x10020000
-CONFIG_SPL=y
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
-CONFIG_VOL_MONITOR_INA220=y
-CONFIG_VOL_MONITOR_IR36021_SET=y
-CONFIG_FSL_QIXIS=y
-# CONFIG_QIXIS_I2C_ACCESS is not set
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_RAMBOOT_PBL=y
-CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046aqds/ls1046aqds_pbi.cfg"
-CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg"
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SD_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;;"
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_MAX_SIZE=0x1f000
-CONFIG_SPL_PAD_TO=0x21000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x8f000000
-CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_BOARD_INIT=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
-CONFIG_DYNAMIC_DDR_CLK_FREQ=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_SYS_MAX_FLASH_BANKS=2
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_PCIE_LAYERSCAPE_EP=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig
deleted file mode 100644
index b571eaa..0000000
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ /dev/null
@@ -1,128 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1046AQDS=y
-CONFIG_TEXT_BASE=0x82000000
-CONFIG_SYS_MALLOC_LEN=0x102000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
-CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_FSL_LS_PPA=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x10020000
-CONFIG_SPL=y
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
-CONFIG_VOL_MONITOR_INA220=y
-CONFIG_VOL_MONITOR_IR36021_SET=y
-CONFIG_FSL_QIXIS=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_RAMBOOT_PBL=y
-CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046aqds/ls1046aqds_pbi.cfg"
-CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg"
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SD_BOOT=y
-CONFIG_SD_BOOT_QSPI=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:2m(uboot),14m(free)"
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;;"
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_MAX_SIZE=0x1f000
-CONFIG_SPL_PAD_TO=0x21000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x8f000000
-CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_BOARD_INIT=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:2m(uboot),14m(free)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
-CONFIG_DYNAMIC_DDR_CLK_FREQ=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_EARLY_INIT=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_PCIE_LAYERSCAPE_EP=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
index 9cb79e1..9f4e2bf 100644
--- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
@@ -31,11 +31,11 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
+CONFIG_FIT_VERBOSE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
# CONFIG_USE_BOOTCOMMAND is not set
diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig
index fde5659..fb87379 100644
--- a/configs/ls1046aqds_tfa_defconfig
+++ b/configs/ls1046aqds_tfa_defconfig
@@ -33,11 +33,11 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
+CONFIG_FIT_VERBOSE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
# CONFIG_USE_BOOTCOMMAND is not set
diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig
deleted file mode 100644
index 924ff78..0000000
--- a/configs/ls1046ardb_emmc_defconfig
+++ /dev/null
@@ -1,122 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1046ARDB=y
-CONFIG_TEXT_BASE=0x82000000
-CONFIG_SYS_MALLOC_LEN=0x102000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
-CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_FSL_LS_PPA=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x10020000
-CONFIG_SPL=y
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_RAMBOOT_PBL=y
-CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_pbi.cfg"
-CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg"
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SD_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_MAX_SIZE=0x1f000
-CONFIG_SPL_PAD_TO=0x21000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x8f000000
-CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_BOARD_INIT=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="FM1@DTSEC3"
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x53
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-# CONFIG_SPI_FLASH_BAR is not set
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_FIXED=y
-CONFIG_DM_MDIO=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_PCIE_LAYERSCAPE_EP=y
-CONFIG_POWER_LEGACY=y
-CONFIG_POWER_I2C=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_DM_SCSI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPL_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
deleted file mode 100644
index bb27884..0000000
--- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,99 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1046ARDB=y
-CONFIG_TEXT_BASE=0x40100000
-CONFIG_SYS_MALLOC_LEN=0x102000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
-CONFIG_FSL_LS_PPA=y
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_NXP_ESBC=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_RAMBOOT_PBL=y
-CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg"
-CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg"
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;;"
-CONFIG_MISC_INIT_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="FM1@DTSEC3"
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_FSL_SEC_MON_BE=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x53
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_SPANSION=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_FIXED=y
-CONFIG_DM_MDIO=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_SYS_FMAN_FW_ADDR=0x40900000
-CONFIG_NVME_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_PCIE_LAYERSCAPE_EP=y
-CONFIG_POWER_LEGACY=y
-CONFIG_POWER_I2C=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_DM_SCSI=y
-CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_RSA=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig
deleted file mode 100644
index 0fb1a6c..0000000
--- a/configs/ls1046ardb_qspi_defconfig
+++ /dev/null
@@ -1,102 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1046ARDB=y
-CONFIG_TEXT_BASE=0x40100000
-CONFIG_SYS_MALLOC_LEN=0x102000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
-CONFIG_FSL_LS_PPA=y
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_ENV_ADDR=0x40300000
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_RAMBOOT_PBL=y
-CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg"
-CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg"
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;;"
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="FM1@DTSEC3"
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x53
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_SPANSION=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_FIXED=y
-CONFIG_DM_MDIO=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_SYS_FMAN_FW_ADDR=0x40900000
-CONFIG_NVME_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_PCIE_LAYERSCAPE_EP=y
-CONFIG_POWER_LEGACY=y
-CONFIG_POWER_I2C=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_DM_SCSI=y
-CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig
deleted file mode 100644
index eb0184c..0000000
--- a/configs/ls1046ardb_qspi_spl_defconfig
+++ /dev/null
@@ -1,130 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1046ARDB=y
-CONFIG_TEXT_BASE=0x82000000
-CONFIG_SYS_MALLOC_LEN=0x102000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
-CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_FSL_LS_PPA=y
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x10020000
-CONFIG_SPL=y
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_RAMBOOT_PBL=y
-CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg"
-CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg"
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;;"
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_MAX_SIZE=0x1f000
-CONFIG_SPL_PAD_TO=0x20000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x8f000000
-CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SPL_BOARD_INIT=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x90000000
-CONFIG_SYS_OS_BASE=0x40980000
-CONFIG_SPL_WATCHDOG=y
-CONFIG_SPL_TARGET="spl/u-boot-spl.pbl"
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_SPL=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_ENV_IS_NOWHERE=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="FM1@DTSEC3"
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x53
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-# CONFIG_SPI_FLASH_BAR is not set
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_FIXED=y
-CONFIG_DM_MDIO=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_SYS_FMAN_FW_ADDR=0x40900000
-CONFIG_NVME_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_PCIE_LAYERSCAPE_EP=y
-CONFIG_POWER_LEGACY=y
-CONFIG_POWER_I2C=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_DM_SCSI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPL_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_SPL_GZIP=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
deleted file mode 100644
index 2813c79..0000000
--- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,123 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1046ARDB=y
-CONFIG_TEXT_BASE=0x82000000
-CONFIG_SYS_MALLOC_LEN=0x102000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
-CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_FSL_LS_PPA=y
-CONFIG_SYS_MONITOR_LEN=1064960
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x10020000
-CONFIG_SPL=y
-CONFIG_PCI=y
-CONFIG_NXP_ESBC=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_RAMBOOT_PBL=y
-CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_pbi.cfg"
-CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg"
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SD_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_BOOTCOMMAND="run distro_bootcmd;run sd_bootcmd; env exists secureboot && esbc_halt;"
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_MAX_SIZE=0x1f000
-CONFIG_SPL_PAD_TO=0x21000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x8f000000
-CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SPL_FSL_PBL=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="FM1@DTSEC3"
-CONFIG_SPL_DM=y
-# CONFIG_SPL_BLK is not set
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-# CONFIG_SPL_DM_I2C is not set
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_FSL_SEC_MON_BE=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x53
-# CONFIG_SPL_DM_MMC is not set
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-# CONFIG_SPI_FLASH_BAR is not set
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_FIXED=y
-CONFIG_DM_MDIO=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_PCIE_LAYERSCAPE_EP=y
-CONFIG_POWER_LEGACY=y
-CONFIG_POWER_I2C=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SCSI_AHCI_PLAT=y
-CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
deleted file mode 100644
index a621859..0000000
--- a/configs/ls1046ardb_sdcard_defconfig
+++ /dev/null
@@ -1,122 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1046ARDB=y
-CONFIG_TEXT_BASE=0x82000000
-CONFIG_SYS_MALLOC_LEN=0x102000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
-CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_FSL_LS_PPA=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x10020000
-CONFIG_SPL=y
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_RAMBOOT_PBL=y
-CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_pbi.cfg"
-CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg"
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SD_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_BOOTCOMMAND="run distro_bootcmd;run sd_bootcmd; env exists secureboot && esbc_halt;"
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_MAX_SIZE=0x1f000
-CONFIG_SPL_PAD_TO=0x21000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x8f000000
-CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_BOARD_INIT=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="FM1@DTSEC3"
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x53
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-# CONFIG_SPI_FLASH_BAR is not set
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_FIXED=y
-CONFIG_DM_MDIO=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_PCIE_LAYERSCAPE_EP=y
-CONFIG_POWER_LEGACY=y
-CONFIG_POWER_I2C=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_DM_SCSI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPL_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
index fbcf294..0c73b3b 100644
--- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
@@ -25,9 +25,9 @@
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig
index 24a5423..dffb052 100644
--- a/configs/ls1046ardb_tfa_defconfig
+++ b/configs/ls1046ardb_tfa_defconfig
@@ -27,9 +27,9 @@
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig
deleted file mode 100644
index f53fbad..0000000
--- a/configs/ls1088aqds_defconfig
+++ /dev/null
@@ -1,112 +0,0 @@
-CONFIG_ARM=y
-CONFIG_GIC_V3_ITS=y
-CONFIG_TARGET_LS1088AQDS=y
-CONFIG_TEXT_BASE=0x30100000
-CONFIG_SYS_MALLOC_LEN=0x0220000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
-CONFIG_FSL_LS_PPA=y
-CONFIG_ENV_ADDR=0x80300000
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
-CONFIG_VOL_MONITOR_LTC3882_READ=y
-CONFIG_VOL_MONITOR_LTC3882_SET=y
-CONFIG_SYS_FSL_NUM_CC_PLLS=3
-CONFIG_FSL_QIXIS=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="fsl_mc lazyapply dpl 0x580d00000 && cp.b $kernel_start $kernel_load $kernel_size && bootm $kernel_load"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_RESET_PHY_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="DPMAC1@xgmii"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_DYNAMIC_DDR_CLK_FREQ=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_EARLY_INIT=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_ESDHC_DETECT_QUIRK=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_SYS_MAX_FLASH_BANKS=2
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_MAX_OOBFREE=2
-CONFIG_SYS_NAND_MAX_ECCPOS=256
-CONFIG_DM_SPI_FLASH=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_FSL_MEMAC=y
-CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
deleted file mode 100644
index 921240c..0000000
--- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,107 +0,0 @@
-CONFIG_ARM=y
-CONFIG_GIC_V3_ITS=y
-CONFIG_TARGET_LS1088AQDS=y
-CONFIG_TEXT_BASE=0x20100000
-CONFIG_SYS_MALLOC_LEN=0x202000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
-CONFIG_FSL_LS_PPA=y
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_NXP_ESBC=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
-CONFIG_VOL_MONITOR_LTC3882_READ=y
-CONFIG_VOL_MONITOR_LTC3882_SET=y
-CONFIG_SYS_FSL_NUM_CC_PLLS=3
-CONFIG_FSL_QIXIS=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_QSPI_BOOT=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-CONFIG_BOOTCOMMAND="sf probe 0:0;sf read 0x80001000 0xd00000 0x100000; fsl_mc lazyapply dpl 0x80001000 && sf read $kernel_load $kernel_start $kernel_size && bootm $kernel_load"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_RESET_PHY_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="DPMAC1@xgmii"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_ESDHC_DETECT_QUIRK=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_MAX_OOBFREE=2
-CONFIG_SYS_NAND_MAX_ECCPOS=256
-CONFIG_DM_SPI_FLASH=y
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_FSL_MEMAC=y
-CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_GADGET=y
-CONFIG_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig
deleted file mode 100644
index 45c93c8..0000000
--- a/configs/ls1088aqds_qspi_defconfig
+++ /dev/null
@@ -1,108 +0,0 @@
-CONFIG_ARM=y
-CONFIG_GIC_V3_ITS=y
-CONFIG_TARGET_LS1088AQDS=y
-CONFIG_TEXT_BASE=0x20100000
-CONFIG_SYS_MALLOC_LEN=0x202000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
-CONFIG_FSL_LS_PPA=y
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_ENV_ADDR=0x20300000
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
-CONFIG_VOL_MONITOR_LTC3882_READ=y
-CONFIG_VOL_MONITOR_LTC3882_SET=y
-CONFIG_SYS_FSL_NUM_CC_PLLS=3
-CONFIG_FSL_QIXIS=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_QSPI_BOOT=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-CONFIG_BOOTCOMMAND="sf probe 0:0;sf read 0x80001000 0xd00000 0x100000; fsl_mc lazyapply dpl 0x80001000 && sf read $kernel_load $kernel_start $kernel_size && bootm $kernel_load"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_RESET_PHY_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="DPMAC1@xgmii"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_ESDHC_DETECT_QUIRK=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_MAX_OOBFREE=2
-CONFIG_SYS_NAND_MAX_ECCPOS=256
-CONFIG_DM_SPI_FLASH=y
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_FSL_MEMAC=y
-CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_GADGET=y
diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig
deleted file mode 100644
index 1f52769..0000000
--- a/configs/ls1088aqds_sdcard_ifc_defconfig
+++ /dev/null
@@ -1,130 +0,0 @@
-CONFIG_ARM=y
-CONFIG_GIC_V3_ITS=y
-CONFIG_TARGET_LS1088AQDS=y
-CONFIG_TEXT_BASE=0x80400000
-CONFIG_SYS_MALLOC_LEN=0x202000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
-CONFIG_SPL_TEXT_BASE=0x1800a000
-CONFIG_FSL_LS_PPA=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x18009ff0
-CONFIG_SPL=y
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_SPL_VID=y
-CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
-CONFIG_VOL_MONITOR_LTC3882_READ=y
-CONFIG_VOL_MONITOR_LTC3882_SET=y
-CONFIG_SYS_FSL_NUM_CC_PLLS=3
-CONFIG_FSL_QIXIS=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_SD_BOOT=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmcinfo;mmc read 0x80001000 0x6800 0x800; fsl_mc lazyapply dpl 0x80001000 && mmc read $kernel_load $kernel_start $kernel_size && bootm $kernel_load"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_RESET_PHY_R=y
-CONFIG_SPL_MAX_SIZE=0x16000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x80100000
-CONFIG_SPL_BSS_MAX_SIZE=0x100000
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_SPL_TARGET="u-boot-with-spl.bin"
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="DPMAC1@xgmii"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_DYNAMIC_DDR_CLK_FREQ=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_EARLY_INIT=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_ESDHC_DETECT_QUIRK=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_SYS_MAX_FLASH_BANKS=2
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_MAX_OOBFREE=2
-CONFIG_SYS_NAND_MAX_ECCPOS=256
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_FSL_MEMAC=y
-CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig
deleted file mode 100644
index 93d0782..0000000
--- a/configs/ls1088aqds_sdcard_qspi_defconfig
+++ /dev/null
@@ -1,128 +0,0 @@
-CONFIG_ARM=y
-CONFIG_GIC_V3_ITS=y
-CONFIG_TARGET_LS1088AQDS=y
-CONFIG_TEXT_BASE=0x80400000
-CONFIG_SYS_MALLOC_LEN=0x202000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
-CONFIG_SPL_TEXT_BASE=0x1800a000
-CONFIG_FSL_LS_PPA=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x18009ff0
-CONFIG_SPL=y
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_SPL_VID=y
-CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
-CONFIG_VOL_MONITOR_LTC3882_READ=y
-CONFIG_VOL_MONITOR_LTC3882_SET=y
-CONFIG_SYS_FSL_NUM_CC_PLLS=3
-CONFIG_FSL_QIXIS=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SD_BOOT=y
-CONFIG_SD_BOOT_QSPI=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-CONFIG_BOOTCOMMAND="mmcinfo;mmc read 0x80001000 0x6800 0x800; fsl_mc lazyapply dpl 0x80001000 && mmc read $kernel_load $kernel_start $kernel_size && bootm $kernel_load"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_RESET_PHY_R=y
-CONFIG_SPL_MAX_SIZE=0x16000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x80100000
-CONFIG_SPL_BSS_MAX_SIZE=0x100000
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_SPL_TARGET="u-boot-with-spl.bin"
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="DPMAC1@xgmii"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_ESDHC_DETECT_QUIRK=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_MAX_OOBFREE=2
-CONFIG_SYS_NAND_MAX_ECCPOS=256
-CONFIG_DM_SPI_FLASH=y
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_FSL_MEMAC=y
-CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_GADGET=y
diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig
index 05f5496..f074430 100644
--- a/configs/ls1088aqds_tfa_defconfig
+++ b/configs/ls1088aqds_tfa_defconfig
@@ -28,11 +28,11 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT_VERBOSE=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
deleted file mode 100644
index 48bd56b..0000000
--- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,104 +0,0 @@
-CONFIG_ARM=y
-CONFIG_GIC_V3_ITS=y
-CONFIG_TARGET_LS1088ARDB=y
-CONFIG_TEXT_BASE=0x20100000
-CONFIG_SYS_MALLOC_LEN=0x202000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
-CONFIG_FSL_LS_PPA=y
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_NXP_ESBC=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
-CONFIG_VOL_MONITOR_LTC3882_READ=y
-CONFIG_VOL_MONITOR_LTC3882_SET=y
-CONFIG_SYS_FSL_NUM_CC_PLLS=3
-CONFIG_FSL_QIXIS=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_QSPI_BOOT=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
-CONFIG_RESET_PHY_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="DPMAC1@xgmii"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_MXC_I2C1_SPEED=40000000
-CONFIG_SYS_MXC_I2C2_SPEED=40000000
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_MAX_OOBFREE=2
-CONFIG_SYS_NAND_MAX_ECCPOS=256
-CONFIG_DM_SPI_FLASH=y
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_SPANSION=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
-CONFIG_PHY_VITESSE=y
-CONFIG_FSL_MEMAC=y
-CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_NVME_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_GADGET=y
-CONFIG_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig
deleted file mode 100644
index 7dcd12d..0000000
--- a/configs/ls1088ardb_qspi_defconfig
+++ /dev/null
@@ -1,105 +0,0 @@
-CONFIG_ARM=y
-CONFIG_GIC_V3_ITS=y
-CONFIG_TARGET_LS1088ARDB=y
-CONFIG_TEXT_BASE=0x20100000
-CONFIG_SYS_MALLOC_LEN=0x202000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
-CONFIG_FSL_LS_PPA=y
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_ENV_ADDR=0x20300000
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
-CONFIG_VOL_MONITOR_LTC3882_READ=y
-CONFIG_VOL_MONITOR_LTC3882_SET=y
-CONFIG_SYS_FSL_NUM_CC_PLLS=3
-CONFIG_FSL_QIXIS=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_QSPI_BOOT=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
-CONFIG_RESET_PHY_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="DPMAC1@xgmii"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_MXC_I2C1_SPEED=40000000
-CONFIG_SYS_MXC_I2C2_SPEED=40000000
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_MAX_OOBFREE=2
-CONFIG_SYS_NAND_MAX_ECCPOS=256
-CONFIG_DM_SPI_FLASH=y
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_SPANSION=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
-CONFIG_PHY_VITESSE=y
-CONFIG_FSL_MEMAC=y
-CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_NVME_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_GADGET=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
deleted file mode 100644
index c0812a9..0000000
--- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,124 +0,0 @@
-CONFIG_ARM=y
-CONFIG_GIC_V3_ITS=y
-CONFIG_TARGET_LS1088ARDB=y
-CONFIG_TEXT_BASE=0x80400000
-CONFIG_SYS_MALLOC_LEN=0x202000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
-CONFIG_SPL_TEXT_BASE=0x1800a000
-CONFIG_FSL_LS_PPA=y
-CONFIG_SYS_MONITOR_LEN=1064960
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x18009ff0
-CONFIG_SPL=y
-CONFIG_PCI=y
-CONFIG_NXP_ESBC=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_SPL_VID=y
-CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
-CONFIG_VOL_MONITOR_LTC3882_READ=y
-CONFIG_VOL_MONITOR_LTC3882_SET=y
-CONFIG_SYS_FSL_NUM_CC_PLLS=3
-CONFIG_FSL_QIXIS=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SD_BOOT=y
-CONFIG_SD_BOOT_QSPI=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
-CONFIG_RESET_PHY_R=y
-CONFIG_SPL_MAX_SIZE=0x16000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x80100000
-CONFIG_SPL_BSS_MAX_SIZE=0x100000
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_SPL_TARGET="u-boot-with-spl.bin"
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="DPMAC1@xgmii"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SCSI_AHCI=y
-# CONFIG_SPL_BLK is not set
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_MXC_I2C1_SPEED=40000000
-CONFIG_SYS_MXC_I2C2_SPEED=40000000
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-# CONFIG_SPL_DM_MMC is not set
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_MAX_OOBFREE=2
-CONFIG_SYS_NAND_MAX_ECCPOS=256
-CONFIG_DM_SPI_FLASH=y
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_SPANSION=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
-CONFIG_PHY_VITESSE=y
-CONFIG_FSL_MEMAC=y
-CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_SCSI_AHCI_PLAT=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig
deleted file mode 100644
index b98825c..0000000
--- a/configs/ls1088ardb_sdcard_qspi_defconfig
+++ /dev/null
@@ -1,124 +0,0 @@
-CONFIG_ARM=y
-CONFIG_GIC_V3_ITS=y
-CONFIG_TARGET_LS1088ARDB=y
-CONFIG_TEXT_BASE=0x80400000
-CONFIG_SYS_MALLOC_LEN=0x202000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
-CONFIG_SPL_TEXT_BASE=0x1800a000
-CONFIG_FSL_LS_PPA=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x18009ff0
-CONFIG_SPL=y
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_SPL_VID=y
-CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
-CONFIG_VOL_MONITOR_LTC3882_READ=y
-CONFIG_VOL_MONITOR_LTC3882_SET=y
-CONFIG_SYS_FSL_NUM_CC_PLLS=3
-CONFIG_FSL_QIXIS=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SD_BOOT=y
-CONFIG_SD_BOOT_QSPI=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
-CONFIG_RESET_PHY_R=y
-CONFIG_SPL_MAX_SIZE=0x16000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x80100000
-CONFIG_SPL_BSS_MAX_SIZE=0x100000
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_SPL_TARGET="u-boot-with-spl.bin"
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="DPMAC1@xgmii"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_MXC_I2C1_SPEED=40000000
-CONFIG_SYS_MXC_I2C2_SPEED=40000000
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_MAX_OOBFREE=2
-CONFIG_SYS_NAND_MAX_ECCPOS=256
-CONFIG_DM_SPI_FLASH=y
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_SPANSION=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
-CONFIG_PHY_VITESSE=y
-CONFIG_FSL_MEMAC=y
-CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_NVME_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_GADGET=y
diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
index 4291aa9..1ebba60 100644
--- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
@@ -27,9 +27,9 @@
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig
index de3a082..c651c04 100644
--- a/configs/ls1088ardb_tfa_defconfig
+++ b/configs/ls1088ardb_tfa_defconfig
@@ -29,9 +29,9 @@
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
deleted file mode 100644
index d841626..0000000
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,108 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_GIC_V3_ITS=y
-CONFIG_TARGET_LS2080AQDS=y
-CONFIG_TEXT_BASE=0x30100000
-CONFIG_SYS_MALLOC_LEN=0x202000
-CONFIG_NR_DRAM_BANKS=3
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
-CONFIG_FSL_LS_PPA=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_NXP_ESBC=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_FSL_QIXIS=y
-# CONFIG_QIXIS_I2C_ACCESS is not set
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-CONFIG_BOOTCOMMAND="fsl_mc apply dpl 0x580d00000 && cp.b $kernel_start $kernel_load $kernel_size && bootm $kernel_load"
-CONFIG_RESET_PHY_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="DPMAC1@xgmii"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_DYNAMIC_DDR_CLK_FREQ=y
-CONFIG_DIMM_SLOTS_PER_CTLR=2
-CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_FSL_DDR_INTLV_256B=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_ESDHC_DETECT_QUIRK=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_SYS_MAX_FLASH_BANKS=2
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_MAX_OOBFREE=2
-CONFIG_SYS_NAND_MAX_ECCPOS=256
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_FSL_MEMAC=y
-CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
-CONFIG_RTC_DS3231=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
deleted file mode 100644
index be08d5b..0000000
--- a/configs/ls2080aqds_defconfig
+++ /dev/null
@@ -1,109 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_GIC_V3_ITS=y
-CONFIG_TARGET_LS2080AQDS=y
-CONFIG_TEXT_BASE=0x30100000
-CONFIG_SYS_MALLOC_LEN=0x202000
-CONFIG_NR_DRAM_BANKS=3
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
-CONFIG_FSL_LS_PPA=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_ENV_ADDR=0x80300000
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_FSL_QIXIS=y
-# CONFIG_QIXIS_I2C_ACCESS is not set
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-CONFIG_BOOTCOMMAND="fsl_mc apply dpl 0x580d00000 && cp.b $kernel_start $kernel_load $kernel_size && bootm $kernel_load"
-CONFIG_RESET_PHY_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="DPMAC1@xgmii"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
-CONFIG_DYNAMIC_DDR_CLK_FREQ=y
-CONFIG_DIMM_SLOTS_PER_CTLR=2
-CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_FSL_DDR_INTLV_256B=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_ESDHC_DETECT_QUIRK=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_SYS_MAX_FLASH_BANKS=2
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_MAX_OOBFREE=2
-CONFIG_SYS_NAND_MAX_ECCPOS=256
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_FSL_MEMAC=y
-CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
-CONFIG_RTC_DS3231=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 1afaac2..d796d9f 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -25,13 +25,13 @@
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_BOOTCOMMAND="fsl_mc apply dpl 0x580d00000 && cp.b $kernel_start $kernel_load $kernel_size && bootm $kernel_load"
@@ -42,7 +42,7 @@
CONFIG_SPL_BSS_START_ADDR=0x80100000
CONFIG_SPL_BSS_MAX_SIZE=0x100000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig
index b29f1db..e0a5508 100644
--- a/configs/ls2080aqds_qspi_defconfig
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -19,13 +19,13 @@
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_BOOTCOMMAND="fsl_mc apply dpl 0x580d00000 && cp.b $kernel_start $kernel_load $kernel_size && bootm $kernel_load"
diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig
deleted file mode 100644
index b45819f..0000000
--- a/configs/ls2080aqds_sdcard_defconfig
+++ /dev/null
@@ -1,116 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_GIC_V3_ITS=y
-CONFIG_TARGET_LS2080AQDS=y
-CONFIG_TEXT_BASE=0x80400000
-CONFIG_SYS_MALLOC_LEN=0x0220000
-CONFIG_SYS_MALLOC_F_LEN=0x400
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=3
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
-CONFIG_SPL_TEXT_BASE=0x1800a000
-CONFIG_FSL_LS_PPA=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x18009ff0
-CONFIG_SPL=y
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_FSL_QIXIS=y
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_SD_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-CONFIG_BOOTCOMMAND="mmc read 0x80200000 0x6800 0x800; fsl_mc apply dpl 0x80200000 && mmc read $kernel_load $kernel_start $kernel_size && bootm $kernel_load"
-CONFIG_RESET_PHY_R=y
-CONFIG_SPL_MAX_SIZE=0x16000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x80100000
-CONFIG_SPL_BSS_MAX_SIZE=0x100000
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_SPL_TARGET="u-boot-with-spl.bin"
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_EMBED=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="DPMAC1@xgmii"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_DYNAMIC_DDR_CLK_FREQ=y
-CONFIG_DIMM_SLOTS_PER_CTLR=2
-CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_FSL_DDR_INTLV_256B=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_EARLY_INIT=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_ESDHC_DETECT_QUIRK=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_MAX_OOBFREE=2
-CONFIG_SYS_NAND_MAX_ECCPOS=256
-CONFIG_DM_SPI_FLASH=y
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_FSL_MEMAC=y
-CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
-CONFIG_RTC_DS3231=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
deleted file mode 100644
index bcd8301..0000000
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,106 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_GIC_V3_ITS=y
-CONFIG_TARGET_LS2080ARDB=y
-CONFIG_TEXT_BASE=0x30100000
-CONFIG_SYS_MALLOC_LEN=0x202000
-CONFIG_NR_DRAM_BANKS=3
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
-CONFIG_FSL_LS_PPA=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_NXP_ESBC=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv"
-CONFIG_VOL_MONITOR_IR36021_READ=y
-CONFIG_VOL_MONITOR_IR36021_SET=y
-CONFIG_FSL_QIXIS=y
-# CONFIG_QIXIS_I2C_ACCESS is not set
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-CONFIG_BOOTCOMMAND="env exists mcinitcmd && env exists secureboot && esbc_validate 0x5806C0000; env exists mcinitcmd && fsl_mc lazyapply dpl 0x580d00000;run distro_bootcmd;run nor_bootcmd; env exists secureboot && esbc_halt;"
-CONFIG_MISC_INIT_R=y
-CONFIG_RESET_PHY_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="DPMAC1@xgmii"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_DDR_CLK_FREQ=133333333
-CONFIG_DIMM_SLOTS_PER_CTLR=2
-CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_FSL_DDR_INTLV_256B=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_MAX_OOBFREE=2
-CONFIG_SYS_NAND_MAX_ECCPOS=256
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_CORTINA=y
-CONFIG_CORTINA_FW_ADDR=0x580980000
-CONFIG_FSL_MEMAC=y
-CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_RTC_DS3231=y
-CONFIG_DM_SCSI=y
-CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
deleted file mode 100644
index 38ec438..0000000
--- a/configs/ls2080ardb_defconfig
+++ /dev/null
@@ -1,107 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_GIC_V3_ITS=y
-CONFIG_TARGET_LS2080ARDB=y
-CONFIG_TEXT_BASE=0x30100000
-CONFIG_SYS_MALLOC_LEN=0x202000
-CONFIG_NR_DRAM_BANKS=3
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
-CONFIG_FSL_LS_PPA=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_ENV_ADDR=0x80300000
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv"
-CONFIG_VOL_MONITOR_IR36021_READ=y
-CONFIG_VOL_MONITOR_IR36021_SET=y
-CONFIG_FSL_QIXIS=y
-# CONFIG_QIXIS_I2C_ACCESS is not set
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-CONFIG_BOOTCOMMAND="env exists mcinitcmd && env exists secureboot && esbc_validate 0x5806C0000; env exists mcinitcmd && fsl_mc lazyapply dpl 0x580d00000;run distro_bootcmd;run nor_bootcmd; env exists secureboot && esbc_halt;"
-CONFIG_MISC_INIT_R=y
-CONFIG_RESET_PHY_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="DPMAC1@xgmii"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
-CONFIG_DDR_CLK_FREQ=133333333
-CONFIG_DIMM_SLOTS_PER_CTLR=2
-CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_FSL_DDR_INTLV_256B=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_MAX_OOBFREE=2
-CONFIG_SYS_NAND_MAX_ECCPOS=256
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_CORTINA=y
-CONFIG_CORTINA_FW_ADDR=0x580980000
-CONFIG_FSL_MEMAC=y
-CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_RTC_DS3231=y
-CONFIG_DM_SCSI=y
-CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index a406bae..efe5080 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -30,13 +30,13 @@
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_BOOTCOMMAND="env exists mcinitcmd && env exists secureboot && esbc_validate 0x5806C0000; env exists mcinitcmd && fsl_mc lazyapply dpl 0x580d00000;run distro_bootcmd;run nor_bootcmd; env exists secureboot && esbc_halt;"
@@ -48,7 +48,7 @@
CONFIG_SPL_BSS_START_ADDR=0x80100000
CONFIG_SPL_BSS_MAX_SIZE=0x100000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig
deleted file mode 100644
index 1ee9283..0000000
--- a/configs/ls2081ardb_defconfig
+++ /dev/null
@@ -1,96 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_GIC_V3_ITS=y
-CONFIG_TARGET_LS2081ARDB=y
-CONFIG_TEXT_BASE=0x20100000
-CONFIG_SYS_MALLOC_LEN=0x202000
-CONFIG_NR_DRAM_BANKS=3
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2081a-rdb"
-CONFIG_FSL_LS_PPA=y
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv"
-CONFIG_VOL_MONITOR_IR36021_READ=y
-CONFIG_VOL_MONITOR_IR36021_SET=y
-CONFIG_FSL_QIXIS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x806c0000 0x6c0000 0x40000; env exists mcinitcmd && env exists secureboot && esbc_validate 0x806C0000; sf read 0x80d00000 0xd00000 0x100000; env exists mcinitcmd && fsl_mc lazyapply dpl 0x80d00000; run distro_bootcmd;run qspi_bootcmd; env exists secureboot && esbc_halt;"
-CONFIG_MISC_INIT_R=y
-CONFIG_RESET_PHY_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="DPMAC1@xgmii"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
-CONFIG_DDR_CLK_FREQ=133333333
-CONFIG_DIMM_SLOTS_PER_CTLR=2
-CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_FSL_DDR_INTLV_256B=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_EARLY_INIT=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_CORTINA=y
-CONFIG_CORTINA_FW_ADDR=0x980000
-CONFIG_FSL_MEMAC=y
-CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_NVME_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_RTC_PCF8563=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig
index aff3c86..2ac4384 100644
--- a/configs/ls2088aqds_tfa_defconfig
+++ b/configs/ls2088aqds_tfa_defconfig
@@ -22,11 +22,11 @@
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_RESET_PHY_R=y
diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
deleted file mode 100644
index 268740c..0000000
--- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,96 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_GIC_V3_ITS=y
-CONFIG_TARGET_LS2080ARDB=y
-CONFIG_TEXT_BASE=0x20100000
-CONFIG_SYS_MALLOC_LEN=0x202000
-CONFIG_NR_DRAM_BANKS=3
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
-CONFIG_FSL_LS_PPA=y
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_NXP_ESBC=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv"
-CONFIG_VOL_MONITOR_IR36021_READ=y
-CONFIG_VOL_MONITOR_IR36021_SET=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x806c0000 0x6c0000 0x40000; env exists mcinitcmd && env exists secureboot && esbc_validate 0x806C0000; sf read 0x80d00000 0xd00000 0x100000; env exists mcinitcmd && fsl_mc lazyapply dpl 0x80d00000; run distro_bootcmd;run qspi_bootcmd; env exists secureboot && esbc_halt;"
-CONFIG_MISC_INIT_R=y
-CONFIG_RESET_PHY_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="DPMAC1@xgmii"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_DDR_CLK_FREQ=133333333
-CONFIG_DIMM_SLOTS_PER_CTLR=2
-CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_FSL_DDR_INTLV_256B=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_EARLY_INIT=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_CORTINA=y
-CONFIG_CORTINA_FW_ADDR=0x980000
-CONFIG_FSL_MEMAC=y
-CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_NVME_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_RTC_DS3231=y
-CONFIG_DM_SCSI=y
-CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig
deleted file mode 100644
index f38f77b..0000000
--- a/configs/ls2088ardb_qspi_defconfig
+++ /dev/null
@@ -1,101 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_GIC_V3_ITS=y
-CONFIG_TARGET_LS2080ARDB=y
-CONFIG_TEXT_BASE=0x20100000
-CONFIG_SYS_MALLOC_LEN=0x202000
-CONFIG_NR_DRAM_BANKS=3
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
-CONFIG_FSL_LS_PPA=y
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_ENV_ADDR=0x20300000
-CONFIG_PCI=y
-CONFIG_AHCI=y
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv"
-CONFIG_VOL_MONITOR_IR36021_READ=y
-CONFIG_VOL_MONITOR_IR36021_SET=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_REMAKE_ELF=y
-CONFIG_MP=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x806c0000 0x6c0000 0x40000; env exists mcinitcmd && env exists secureboot && esbc_validate 0x806C0000; sf read 0x80d00000 0xd00000 0x100000; env exists mcinitcmd && fsl_mc lazyapply dpl 0x80d00000; run distro_bootcmd;run qspi_bootcmd; env exists secureboot && esbc_halt;"
-CONFIG_MISC_INIT_R=y
-CONFIG_RESET_PHY_R=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="DPMAC1@xgmii"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
-CONFIG_DDR_CLK_FREQ=133333333
-CONFIG_DIMM_SLOTS_PER_CTLR=2
-CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_FSL_DDR_INTLV_256B=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_EARLY_INIT=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_CORTINA=y
-CONFIG_CORTINA_FW_ADDR=0x980000
-CONFIG_FSL_MEMAC=y
-CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_NVME_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_RTC_DS3231=y
-CONFIG_DM_SCSI=y
-CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
index 090764c..61e97b9 100644
--- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
@@ -26,11 +26,11 @@
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_MISC_INIT_R=y
diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig
index c4c994b..4d69db1 100644
--- a/configs/ls2088ardb_tfa_defconfig
+++ b/configs/ls2088ardb_tfa_defconfig
@@ -28,11 +28,11 @@
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_MISC_INIT_R=y
diff --git a/configs/lubancat-2-rk3568_defconfig b/configs/lubancat-2-rk3568_defconfig
index b01d3bd..80ae6ec 100644
--- a/configs/lubancat-2-rk3568_defconfig
+++ b/configs/lubancat-2-rk3568_defconfig
@@ -61,6 +61,9 @@
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
# CONFIG_SPI_FLASH is not set
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_SPL_PINCTRL=y
diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
index 3b54ecb4..875b56b 100644
--- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
@@ -27,10 +27,10 @@
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_BOARD_EARLY_INIT_R=y
diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig
index 89bdf1e..56b9260 100644
--- a/configs/lx2160aqds_tfa_defconfig
+++ b/configs/lx2160aqds_tfa_defconfig
@@ -29,11 +29,11 @@
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_BOARD_EARLY_INIT_R=y
diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
index 507ee4f..8cb89ff 100644
--- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
@@ -28,10 +28,10 @@
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_MISC_INIT_R=y
diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig
index a867109..83e3259 100644
--- a/configs/lx2160ardb_tfa_defconfig
+++ b/configs/lx2160ardb_tfa_defconfig
@@ -30,11 +30,11 @@
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_MISC_INIT_R=y
diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig
index 6c668f2..fc584d6 100644
--- a/configs/lx2160ardb_tfa_stmm_defconfig
+++ b/configs/lx2160ardb_tfa_stmm_defconfig
@@ -30,11 +30,11 @@
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_MISC_INIT_R=y
diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
index f5edef7..942cdb7 100644
--- a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
@@ -27,10 +27,10 @@
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_BOARD_EARLY_INIT_R=y
diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig
index c95bb50..e91fccf 100644
--- a/configs/lx2162aqds_tfa_defconfig
+++ b/configs/lx2162aqds_tfa_defconfig
@@ -29,11 +29,11 @@
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_BOARD_EARLY_INIT_R=y
diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig
index bea1859..4bd7ef3 100644
--- a/configs/lx2162aqds_tfa_verified_boot_defconfig
+++ b/configs/lx2162aqds_tfa_verified_boot_defconfig
@@ -29,12 +29,12 @@
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_BOARD_EARLY_INIT_R=y
diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig
index 9f01bf7..ef9e15d 100644
--- a/configs/m53menlo_defconfig
+++ b/configs/m53menlo_defconfig
@@ -23,8 +23,8 @@
CONFIG_ENV_OFFSET_REDUND=0x180000
CONFIG_SYS_LOAD_ADDR=0x70800000
CONFIG_FIT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=1
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttymxc0,115200"
CONFIG_USE_BOOTCOMMAND=y
diff --git a/configs/mangopi_mq_r_defconfig b/configs/mangopi_mq_r_defconfig
new file mode 100644
index 0000000..66ae639
--- /dev/null
+++ b/configs/mangopi_mq_r_defconfig
@@ -0,0 +1,15 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-t113s-mangopi-mq-r-t113"
+CONFIG_SPL=y
+CONFIG_MACH_SUN8I_R528=y
+CONFIG_DRAM_CLK=792
+CONFIG_DRAM_ZQ=8092667
+CONFIG_SUNXI_MINIMUM_DRAM_MB=128
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_DRAM_SUNXI_ODT_EN=0
+CONFIG_DRAM_SUNXI_TPR0=0x004a2195
+CONFIG_DRAM_SUNXI_TPR11=0x340000
+CONFIG_DRAM_SUNXI_TPR12=0x46
+CONFIG_DRAM_SUNXI_TPR13=0x34000100
+CONFIG_CONS_INDEX=4
diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig
index 6afddd2..5e8fbd0 100644
--- a/configs/mccmon6_nor_defconfig
+++ b/configs/mccmon6_nor_defconfig
@@ -24,12 +24,12 @@
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x18000000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x18000000
CONFIG_SYS_OS_BASE=0x8180000
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig
index c95ee25..83f2b1a 100644
--- a/configs/mccmon6_sd_defconfig
+++ b/configs/mccmon6_sd_defconfig
@@ -26,7 +26,7 @@
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SYS_MAXARGS=32
diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig
index 8ed0c7a..df568ff 100644
--- a/configs/medcom-wide_defconfig
+++ b/configs/medcom-wide_defconfig
@@ -18,10 +18,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x90000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra20 (Medcom-Wide) # "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2089
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index 8347a9d..9c03dc8 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -30,7 +30,6 @@
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=532
@@ -53,7 +52,6 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig
index 0e4cdc4..2f92228 100644
--- a/configs/mixtile_loftq_defconfig
+++ b/configs/mixtile_loftq_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=251
-CONFIG_MACPWR="PA21"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB1_VBUS_PIN="PH24"
CONFIG_USB2_VBUS_PIN=""
diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig
index bf851cb..70b1032 100644
--- a/configs/mk808_defconfig
+++ b/configs/mk808_defconfig
@@ -70,7 +70,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
CONFIG_TPL_DM=y
-# CONFIG_DM_WARN is not set
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_TPL_REGMAP=y
diff --git a/configs/msc_sm2s_imx8mp_defconfig b/configs/msc_sm2s_imx8mp_defconfig
index e8b38e2..75b4966 100644
--- a/configs/msc_sm2s_imx8mp_defconfig
+++ b/configs/msc_sm2s_imx8mp_defconfig
@@ -23,8 +23,8 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mp-msc-sm2s.dtb"
CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -34,10 +34,10 @@
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/mt7620_rfb_defconfig b/configs/mt7620_rfb_defconfig
index fe57fd1..954870b 100644
--- a/configs/mt7620_rfb_defconfig
+++ b/configs/mt7620_rfb_defconfig
@@ -54,7 +54,6 @@
CONFIG_SPL_DM=y
# CONFIG_SIMPLE_BUS is not set
# CONFIG_SPL_SIMPLE_BUS is not set
-# CONFIG_SPL_BLK is not set
CONFIG_GPIO_HOG=y
# CONFIG_INPUT is not set
CONFIG_MMC=y
diff --git a/configs/mvebu_ac5_rd_defconfig b/configs/mvebu_ac5_rd_defconfig
index dbf1e31..e8fa22b 100644
--- a/configs/mvebu_ac5_rd_defconfig
+++ b/configs/mvebu_ac5_rd_defconfig
@@ -85,3 +85,4 @@
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
+# CONFIG_SMBIOS is not set
diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig
index 8295670..51518cf 100644
--- a/configs/mvebu_db-88f3720_defconfig
+++ b/configs/mvebu_db-88f3720_defconfig
@@ -69,6 +69,7 @@
CONFIG_MVEBU_COMPHY_SUPPORT=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_37XX=y
+CONFIG_DEFAULT_ENV_IS_RW=y
CONFIG_MVEBU_A3700_UART=y
CONFIG_MVEBU_A3700_SPI=y
CONFIG_USB=y
diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig
index fc394a7..227607a 100644
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -18,8 +18,8 @@
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
@@ -27,7 +27,6 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_SYS_MAXARGS=32
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FUSE=y
@@ -89,6 +88,7 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_37XX=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DEFAULT_ENV_IS_RW=y
CONFIG_MVEBU_A3700_UART=y
CONFIG_MVEBU_A3700_SPI=y
CONFIG_USB=y
diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig
index df0ccea..905766b 100644
--- a/configs/mx28evk_defconfig
+++ b/configs/mx28evk_defconfig
@@ -32,6 +32,7 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT4=y
@@ -65,3 +66,10 @@
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig
index 055dbcb..0dd1bac 100644
--- a/configs/mx53ppd_defconfig
+++ b/configs/mx53ppd_defconfig
@@ -12,8 +12,8 @@
CONFIG_SYS_LOAD_ADDR=0x72000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=1
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run doquiet; run tryboot"
# CONFIG_CONSOLE_MUX is not set
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index b23c789..8b19096 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig
@@ -22,13 +22,13 @@
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
CONFIG_FIT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="if hdmidet; then usb start; setenv stdin serial,usbkbd; setenv stdout serial,vidconsole; setenv stderr serial,vidconsole; else setenv stdin serial; setenv stdout serial; setenv stderr serial; fi;"
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
CONFIG_SPL_I2C=y
diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig
index a488ce4..6dd64b6 100644
--- a/configs/mx6memcal_defconfig
+++ b/configs/mx6memcal_defconfig
@@ -15,7 +15,7 @@
CONFIG_SYS_MEMTEST_START=0x10000000
CONFIG_SYS_MEMTEST_END=0x20000000
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index ee518ca..deb0b65 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -31,7 +31,7 @@
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index 0a8b047..edc92f8 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -31,7 +31,7 @@
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index fee3c6f..8db4576 100644
--- a/configs/mx6slevk_spl_defconfig
+++ b/configs/mx6slevk_spl_defconfig
@@ -27,7 +27,7 @@
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
CONFIG_SPL_I2C=y
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index 0e03660..f727423 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -29,7 +29,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
CONFIG_SPL_I2C=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index 740968d..1e4ec0b 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -29,7 +29,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
CONFIG_SPL_I2C=y
diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index 26e68d3..1c8105f 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -73,6 +73,8 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SOFT_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
@@ -85,4 +87,5 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_IMX_WATCHDOG=y
CONFIG_ERRNO_STR=y
diff --git a/configs/myir_mys_6ulx_defconfig b/configs/myir_mys_6ulx_defconfig
index 8e3938d..456d1b8 100644
--- a/configs/myir_mys_6ulx_defconfig
+++ b/configs/myir_mys_6ulx_defconfig
@@ -20,7 +20,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
diff --git a/configs/n2350_defconfig b/configs/n2350_defconfig
index 109f0e1..0713574 100644
--- a/configs/n2350_defconfig
+++ b/configs/n2350_defconfig
@@ -29,7 +29,8 @@
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_BOOTDELAY=10
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/nanopc-t6-rk3588_defconfig b/configs/nanopc-t6-rk3588_defconfig
new file mode 100644
index 0000000..070399c
--- /dev/null
+++ b/configs/nanopc-t6-rk3588_defconfig
@@ -0,0 +1,108 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rk3588-nanopc-t6"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_NANOPCT6_RK3588=y
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-nanopc-t6.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=5
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHYLIB=y
+CONFIG_RTL8169=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/nanopi-k2_defconfig b/configs/nanopi-k2_defconfig
index ef101cf..41dbf79 100644
--- a/configs/nanopi-k2_defconfig
+++ b/configs/nanopi-k2_defconfig
@@ -15,6 +15,10 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig
index 201b21a..833cff0 100644
--- a/configs/nanopi-r5c-rk3568_defconfig
+++ b/configs/nanopi-r5c-rk3568_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a00000
@@ -17,10 +18,13 @@
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -37,14 +41,16 @@
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_WARN=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
@@ -52,19 +58,20 @@
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_GMAC_ROCKCHIP=y
+CONFIG_RTL8169=y
+CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
-CONFIG_POWER_DOMAIN=y
+CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
@@ -72,7 +79,6 @@
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
-CONFIG_SYSRESET_PSCI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig
index 67b2843..2736d38 100644
--- a/configs/nanopi-r5s-rk3568_defconfig
+++ b/configs/nanopi-r5s-rk3568_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a00000
@@ -17,10 +18,13 @@
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -37,14 +41,16 @@
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_WARN=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
@@ -52,19 +58,24 @@
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_RTL8169=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
-CONFIG_POWER_DOMAIN=y
+CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
@@ -72,7 +83,6 @@
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
-CONFIG_SYSRESET_PSCI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig
index 76655d7..078e98b 100644
--- a/configs/nanopi_m1_plus_defconfig
+++ b/configs/nanopi_m1_plus_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
-CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SUN8I_EMAC=y
diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig
index 924ff38..85ff31c 100644
--- a/configs/nanopi_neo_plus2_defconfig
+++ b/configs/nanopi_neo_plus2_defconfig
@@ -6,7 +6,6 @@
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=3881977
# CONFIG_DRAM_ODT_EN is not set
-CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SUN8I_EMAC=y
diff --git a/configs/nanopi_r1s_h5_defconfig b/configs/nanopi_r1s_h5_defconfig
index 27cf172..2a6f94a 100644
--- a/configs/nanopi_r1s_h5_defconfig
+++ b/configs/nanopi_r1s_h5_defconfig
@@ -6,7 +6,6 @@
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881977
# CONFIG_DRAM_ODT_EN is not set
-CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SUN8I_EMAC=y
diff --git a/configs/neu2-io-rv1126_defconfig b/configs/neu2-io-rv1126_defconfig
index f02c38c..2fb5a84 100644
--- a/configs/neu2-io-rv1126_defconfig
+++ b/configs/neu2-io-rv1126_defconfig
@@ -17,7 +17,6 @@
CONFIG_DEFAULT_FDT_FILE="rv1126-edgeble-neu2-io.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig
index 09729a0..d5301c6 100644
--- a/configs/neu6a-io-rk3588_defconfig
+++ b/configs/neu6a-io-rk3588_defconfig
@@ -53,8 +53,6 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_GMAC_ROCKCHIP=y
CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
diff --git a/configs/neu6b-io-rk3588_defconfig b/configs/neu6b-io-rk3588_defconfig
index c7bc3b1..b13c9b5 100644
--- a/configs/neu6b-io-rk3588_defconfig
+++ b/configs/neu6b-io-rk3588_defconfig
@@ -53,8 +53,6 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_GMAC_ROCKCHIP=y
CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index 3cb0cb8..278e3fd 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -32,7 +32,7 @@
CONFIG_BOOTCOMMAND="run distro_bootcmd ; run net_nfs"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
CONFIG_SPL_I2C=y
diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig
index ff489562..038ef42 100644
--- a/configs/nsa310s_defconfig
+++ b/configs/nsa310s_defconfig
@@ -19,7 +19,8 @@
CONFIG_IDENT_STRING="\nZyXEL NSA310S/320S 1/2-Bay Power Media Server"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
-CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/nsa325_defconfig b/configs/nsa325_defconfig
new file mode 100644
index 0000000..1f05d3b
--- /dev/null
+++ b/configs/nsa325_defconfig
@@ -0,0 +1,80 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_SYS_THUMB_BUILD=y
+CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_SYS_KWD_CONFIG="board/zyxel/nsa325/kwbimage.cfg"
+CONFIG_TEXT_BASE=0x600000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_NSA325=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xC0000
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-nsa325"
+CONFIG_IDENT_STRING="\nZyXEL NSA325 2-Bay Power Media Server"
+CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
+CONFIG_LTO=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_BOOTSTD_BOOTCOMMAND=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTSTAGE=y
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_PREBOOT=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SYS_PROMPT="NSA325> "
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+# CONFIG_CMD_BLOCK_CACHE is not set
+CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x100000(uboot),0x80000(stock_uboot_env),0x80000(key_store),0x80000(info),0xA00000(etc),0xA00000(kernel_1),0x2FC0000(rootfs1),0xA00000(kernel_2),0x2FC0000(rootfs2)"
+CONFIG_CMD_UBI=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_SATA_MV=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
+CONFIG_LBA48=y
+CONFIG_SYS_64BIT_LBA=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_MARVELL=y
+CONFIG_MVGBE=y
+CONFIG_MII=y
+CONFIG_PCI_MVEBU=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF8563=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_NAND=y
+CONFIG_UBIFS_SILENCE_MSG=y
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 6435bad..c144a08 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -20,19 +20,19 @@
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTSTAGE=y
CONFIG_SPL_BOOTSTAGE=y
CONFIG_BOOTSTAGE_STASH=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0xef8100
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra124 (Nyan-big) # "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2087
diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig
index 062f583..1dc7a49 100644
--- a/configs/octeontx2_95xx_defconfig
+++ b/configs/octeontx2_95xx_defconfig
@@ -24,17 +24,16 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_BOOT_RETRY=y
CONFIG_BOOT_RETRY_TIME=-1
CONFIG_BOOT_RETRY_MIN=30
CONFIG_RESET_TO_RETRY=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus=6 rootwait rw root=/dev/mmcblk0p2 coherent_pool=16M"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Marvell> "
CONFIG_SYS_MAXARGS=64
diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig
index de13d0d..e14370b 100644
--- a/configs/octeontx2_96xx_defconfig
+++ b/configs/octeontx2_96xx_defconfig
@@ -24,17 +24,16 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_BOOT_RETRY=y
CONFIG_BOOT_RETRY_TIME=-1
CONFIG_BOOT_RETRY_MIN=30
CONFIG_RESET_TO_RETRY=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus=24 rootwait rw root=/dev/mmcblk0p2 coherent_pool=16M"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Marvell> "
CONFIG_SYS_MAXARGS=64
diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig
index 070c947..3d092f2 100644
--- a/configs/octeontx_81xx_defconfig
+++ b/configs/octeontx_81xx_defconfig
@@ -25,12 +25,12 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_BOOT_RETRY=y
CONFIG_BOOT_RETRY_TIME=-1
CONFIG_BOOT_RETRY_MIN=30
CONFIG_RESET_TO_RETRY=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus=4 rootwait rw root=/dev/sda2 coherent_pool=16M"
# CONFIG_DISPLAY_CPUINFO is not set
diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig
index 6e722d7..d54cb6b 100644
--- a/configs/octeontx_83xx_defconfig
+++ b/configs/octeontx_83xx_defconfig
@@ -23,12 +23,12 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_BOOT_RETRY=y
CONFIG_BOOT_RETRY_TIME=-1
CONFIG_BOOT_RETRY_MIN=30
CONFIG_RESET_TO_RETRY=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus=24 rootwait rw root=/dev/sda2 coherent_pool=16M"
# CONFIG_DISPLAY_CPUINFO is not set
diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
index 9481cbc..5f9f323e 100644
--- a/configs/odroid-c2_defconfig
+++ b/configs/odroid-c2_defconfig
@@ -15,6 +15,10 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
diff --git a/configs/odroid-c4_defconfig b/configs/odroid-c4_defconfig
index 315dc5c..fe1f861 100644
--- a/configs/odroid-c4_defconfig
+++ b/configs/odroid-c4_defconfig
@@ -17,12 +17,17 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=32
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -34,6 +39,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ADC=y
CONFIG_SARADC_MESON=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_MDIO=y
diff --git a/configs/odroid-go-ultra_defconfig b/configs/odroid-go-ultra_defconfig
index fb8ce5c..49d628b 100644
--- a/configs/odroid-go-ultra_defconfig
+++ b/configs/odroid-go-ultra_defconfig
@@ -17,11 +17,16 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_MAXARGS=32
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -37,6 +42,7 @@
CONFIG_BUTTON=y
CONFIG_BUTTON_ADC=y
CONFIG_BUTTON_GPIO=y
+CONFIG_DFU_RAM=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MESON=y
CONFIG_MMC_MESON_GX=y
@@ -57,6 +63,7 @@
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SMBIOS=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/odroid-hc4_defconfig b/configs/odroid-hc4_defconfig
index b250715..4316811 100644
--- a/configs/odroid-hc4_defconfig
+++ b/configs/odroid-hc4_defconfig
@@ -19,12 +19,17 @@
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=32
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -41,6 +46,7 @@
CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/odroid-m1-rk3568_defconfig b/configs/odroid-m1-rk3568_defconfig
index 3dda5c1..96b4e9e 100644
--- a/configs/odroid-m1-rk3568_defconfig
+++ b/configs/odroid-m1-rk3568_defconfig
@@ -82,6 +82,9 @@
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
diff --git a/configs/odroid-n2_defconfig b/configs/odroid-n2_defconfig
index e55de38..9694f04 100644
--- a/configs/odroid-n2_defconfig
+++ b/configs/odroid-n2_defconfig
@@ -17,12 +17,17 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=32
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -34,6 +39,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ADC=y
CONFIG_SARADC_MESON=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_MDIO=y
diff --git a/configs/odroid-n2l_defconfig b/configs/odroid-n2l_defconfig
index 983ac88..673e0cf 100644
--- a/configs/odroid-n2l_defconfig
+++ b/configs/odroid-n2l_defconfig
@@ -17,12 +17,17 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=32
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -34,6 +39,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ADC=y
CONFIG_SARADC_MESON=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_PINCTRL=y
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index 3f03a9d..718ec96 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -72,5 +72,4 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x04e8
CONFIG_USB_GADGET_PRODUCT_NUM=0x6601
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_FUNCTION_THOR=y
CONFIG_ERRNO_STR=y
diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
index 45e2ed8..031c6f9 100644
--- a/configs/odroid_defconfig
+++ b/configs/odroid_defconfig
@@ -74,6 +74,5 @@
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DWC2_OTG_PHY=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_FUNCTION_THOR=y
CONFIG_LIB_HW_RAND=y
CONFIG_ERRNO_STR=y
diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig
index f6652eb..539b0cf 100644
--- a/configs/omap35_logic_defconfig
+++ b/configs/omap35_logic_defconfig
@@ -25,8 +25,8 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
@@ -36,7 +36,7 @@
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SPL_NAND_BASE=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x84000000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x84000000
CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x280000
CONFIG_SPL_FALCON_BOOT_MMCSD=y
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig
index 680b88e..f14ce3d 100644
--- a/configs/omap35_logic_somlv_defconfig
+++ b/configs/omap35_logic_somlv_defconfig
@@ -16,8 +16,8 @@
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL=y
CONFIG_LTO=y
-CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_SYS_MONITOR_BASE=0x10000000
+CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run autoboot"
CONFIG_USE_PREBOOT=y
@@ -26,8 +26,8 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
@@ -37,7 +37,7 @@
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SPL_NAND_BASE=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x84000000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x84000000
CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x280000
CONFIG_SPL_FALCON_BOOT_MMCSD=y
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig
index d475378..cabd365 100644
--- a/configs/omap3_beagle_defconfig
+++ b/configs/omap3_beagle_defconfig
@@ -19,8 +19,8 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_NAND_DRIVERS=y
diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig
index 1aa4850..33ff39f 100644
--- a/configs/omap3_evm_defconfig
+++ b/configs/omap3_evm_defconfig
@@ -19,8 +19,8 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_NAND_DRIVERS=y
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index cc1f418..7d3d602 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -24,8 +24,8 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
@@ -35,7 +35,7 @@
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SPL_NAND_BASE=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x84000000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x84000000
CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x280000
CONFIG_SPL_FALCON_BOOT_MMCSD=y
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig
index 97041b6..0141a42 100644
--- a/configs/omap3_logic_somlv_defconfig
+++ b/configs/omap3_logic_somlv_defconfig
@@ -16,8 +16,8 @@
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL=y
CONFIG_LTO=y
-CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_SYS_MONITOR_BASE=0x10000000
+CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run autoboot"
CONFIG_USE_PREBOOT=y
@@ -26,8 +26,8 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
@@ -37,7 +37,7 @@
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SPL_NAND_BASE=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x84000000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x84000000
CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x280000
CONFIG_SPL_FALCON_BOOT_MMCSD=y
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig
index 5571722..d126d2c 100644
--- a/configs/omap4_panda_defconfig
+++ b/configs/omap4_panda_defconfig
@@ -15,8 +15,8 @@
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_MAX_SIZE=0xbc00
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
# CONFIG_SPL_NAND_SUPPORT is not set
diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig
index 0a8a1c7..5371035 100644
--- a/configs/omap4_sdp4430_defconfig
+++ b/configs/omap4_sdp4430_defconfig
@@ -19,8 +19,8 @@
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_MAX_SIZE=0xbc00
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_SPL_I2C is not set
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SYS_MAXARGS=64
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index dec7a4b..47feff2 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -41,10 +41,10 @@
CONFIG_SPL_MAX_FOOTPRINT=0x8000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xc0f70000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x110000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0f70000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x110000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xb5
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_DRIVERS=y
diff --git a/configs/openpiton_riscv64_spl_defconfig b/configs/openpiton_riscv64_spl_defconfig
index 9272bf6..c0ec9ed 100644
--- a/configs/openpiton_riscv64_spl_defconfig
+++ b/configs/openpiton_riscv64_spl_defconfig
@@ -29,7 +29,7 @@
# CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
# CONFIG_SPL_BANNER_PRINT is not set
CONFIG_SPL_CPU=y
CONFIG_SPL_FS_EXT4=y
diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig
index 19d12c1..6a91b12 100644
--- a/configs/opos6uldev_defconfig
+++ b/configs/opos6uldev_defconfig
@@ -33,7 +33,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_BOARD_INIT=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SPL_YMODEM_SUPPORT=y
diff --git a/configs/orangepi-5-plus-rk3588_defconfig b/configs/orangepi-5-plus-rk3588_defconfig
new file mode 100644
index 0000000..0473699
--- /dev/null
+++ b/configs/orangepi-5-plus-rk3588_defconfig
@@ -0,0 +1,105 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rk3588-orangepi-5-plus"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_EVB_RK3588=y
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-orangepi-5-plus.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_AHCI_PCI=y
+CONFIG_DWC_AHCI=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=5
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_PHYLIB=y
+CONFIG_RTL8169=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/orangepi-5-rk3588s_defconfig b/configs/orangepi-5-rk3588s_defconfig
new file mode 100644
index 0000000..feb45a5
--- /dev/null
+++ b/configs/orangepi-5-rk3588s_defconfig
@@ -0,0 +1,102 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rk3588s-orangepi-5"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_EVB_RK3588=y
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-orangepi-5.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_AHCI_PCI=y
+CONFIG_DWC_AHCI=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=5
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig
index 777af8c..fb6fbaf 100644
--- a/configs/orangepi_pc2_defconfig
+++ b/configs/orangepi_pc2_defconfig
@@ -5,7 +5,6 @@
CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881977
-CONFIG_MACPWR="PD6"
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig
index 138a6a7..5e2cbc4 100644
--- a/configs/orangepi_plus2e_defconfig
+++ b/configs/orangepi_plus2e_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
-CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index 76de72a..adffe38 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -4,10 +4,9 @@
CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
-CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB1_VBUS_PIN="PG13"
-CONFIG_SATAPWR="PG11"
+CONFIG_USB3_VBUS_PIN="PG11"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig
index df11ad8..3ddaf05 100644
--- a/configs/orangepi_win_defconfig
+++ b/configs/orangepi_win_defconfig
@@ -3,7 +3,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win"
CONFIG_SPL=y
CONFIG_MACH_SUN50I=y
-CONFIG_MACPWR="PD14"
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig
index f13735e..98aed84 100644
--- a/configs/orangepi_zero2_defconfig
+++ b/configs/orangepi_zero2_defconfig
@@ -8,6 +8,7 @@
CONFIG_DRAM_SUN50I_H616_TPR10=0xf83438
CONFIG_MACH_SUN50I_H616=y
CONFIG_SUNXI_DRAM_H616_DDR3_1333=y
+CONFIG_USB1_VBUS_PIN="PC16"
CONFIG_R_I2C_ENABLE=y
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -19,6 +20,7 @@
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHY_REALTEK=y
CONFIG_SUN8I_EMAC=y
+CONFIG_AXP305_POWER=y
CONFIG_SPI=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/orangepi_zero3_defconfig b/configs/orangepi_zero3_defconfig
new file mode 100644
index 0000000..5a019fe
--- /dev/null
+++ b/configs/orangepi_zero3_defconfig
@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h618-orangepi-zero3"
+CONFIG_SPL=y
+CONFIG_DRAM_SUN50I_H616_DX_ODT=0x07070707
+CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e
+CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e
+CONFIG_DRAM_SUN50I_H616_ODT_EN=0xaaaaeeee
+CONFIG_DRAM_SUN50I_H616_TPR6=0x44000000
+CONFIG_DRAM_SUN50I_H616_TPR10=0x402f6663
+CONFIG_DRAM_SUN50I_H616_TPR11=0x24242624
+CONFIG_DRAM_SUN50I_H616_TPR12=0x0f0f100f
+CONFIG_MACH_SUN50I_H616=y
+CONFIG_SUNXI_DRAM_H616_LPDDR4=y
+CONFIG_DRAM_CLK=792
+CONFIG_USB1_VBUS_PIN="PC16"
+CONFIG_R_I2C_ENABLE=y
+CONFIG_SPL_SPI_SUNXI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_SUN8I_EMAC=y
+CONFIG_AXP313_POWER=y
+CONFIG_SPI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/origen_defconfig b/configs/origen_defconfig
index 4075ef2..3a71d6e 100644
--- a/configs/origen_defconfig
+++ b/configs/origen_defconfig
@@ -57,4 +57,3 @@
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DWC2_OTG_PHY=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_FUNCTION_THOR=y
diff --git a/configs/p200_defconfig b/configs/p200_defconfig
index 42e7eb8..cd579ef 100644
--- a/configs/p200_defconfig
+++ b/configs/p200_defconfig
@@ -15,6 +15,10 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
diff --git a/configs/p201_defconfig b/configs/p201_defconfig
index 5c98375..b2f0a0c 100644
--- a/configs/p201_defconfig
+++ b/configs/p201_defconfig
@@ -16,6 +16,10 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
diff --git a/configs/p212_defconfig b/configs/p212_defconfig
index 2fcf3b3..b90391d 100644
--- a/configs/p212_defconfig
+++ b/configs/p212_defconfig
@@ -16,6 +16,10 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig
index ad65fa0..9f3893d 100644
--- a/configs/paz00_defconfig
+++ b/configs/paz00_defconfig
@@ -16,10 +16,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x90000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra20 (Paz00) MOD # "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2087
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index 6769634..831a146 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -14,8 +14,8 @@
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="am335x-wega-rdk.dtb"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig
index f8b5872..15ae95e 100644
--- a/configs/pcm058_defconfig
+++ b/configs/pcm058_defconfig
@@ -32,7 +32,7 @@
CONFIG_BOOTCOMMAND="run mmcboot;run nandboot"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_BOARD_INIT=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x18a
CONFIG_SPL_DMA=y
CONFIG_SPL_FS_EXT4=y
diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig
index 8e8e85c..455b439 100644
--- a/configs/pg_wcom_expu1_defconfig
+++ b/configs/pg_wcom_expu1_defconfig
@@ -30,13 +30,13 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_SILENT_CONSOLE=y
diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig
index e012851..269116c 100644
--- a/configs/pg_wcom_expu1_update_defconfig
+++ b/configs/pg_wcom_expu1_update_defconfig
@@ -28,13 +28,13 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_SILENT_CONSOLE=y
diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig
index ccab108..678bc10 100644
--- a/configs/pg_wcom_seli8_defconfig
+++ b/configs/pg_wcom_seli8_defconfig
@@ -30,13 +30,13 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_SILENT_CONSOLE=y
diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig
index 0e26992..7c7b001 100644
--- a/configs/pg_wcom_seli8_update_defconfig
+++ b/configs/pg_wcom_seli8_update_defconfig
@@ -28,13 +28,13 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_SILENT_CONSOLE=y
diff --git a/configs/phycore-am335x-r2-regor_defconfig b/configs/phycore-am335x-r2-regor_defconfig
index d74078c..4bdf882 100644
--- a/configs/phycore-am335x-r2-regor_defconfig
+++ b/configs/phycore-am335x-r2-regor_defconfig
@@ -19,13 +19,14 @@
CONFIG_SPL_PAYLOAD="u-boot.img"
# CONFIG_FIT is not set
CONFIG_OF_BOARD_SETUP=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="am335x-regor-rdk.dtb"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_I2C=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_NAND_DRIVERS=y
@@ -94,5 +95,4 @@
CONFIG_USB_MUSB_TI=y
CONFIG_USB_GADGET=y
CONFIG_USB_ETHER=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig
index 0f75d56..7644fbe 100644
--- a/configs/phycore-am335x-r2-wega_defconfig
+++ b/configs/phycore-am335x-r2-wega_defconfig
@@ -19,13 +19,14 @@
CONFIG_SPL_PAYLOAD="u-boot.img"
# CONFIG_FIT is not set
CONFIG_OF_BOARD_SETUP=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="am335x-wega-rdk.dtb"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_I2C=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_NAND_DRIVERS=y
@@ -95,5 +96,4 @@
CONFIG_USB_MUSB_TI=y
CONFIG_USB_GADGET=y
CONFIG_USB_ETHER=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig
index 3c22322..bff35e7 100644
--- a/configs/phycore-imx8mm_defconfig
+++ b/configs/phycore-imx8mm_defconfig
@@ -33,10 +33,10 @@
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index af6945d..46efe18 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -12,6 +12,7 @@
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-phyboard-pollux-rdk"
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_TARGET_PHYCORE_IMX8MP=y
+CONFIG_PHYTEC_SOM_DETECTION=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
@@ -37,10 +38,10 @@
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig
index 2d06621..11db968 100644
--- a/configs/phycore_pcl063_defconfig
+++ b/configs/phycore_pcl063_defconfig
@@ -19,7 +19,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig
index 327ea56..f0a2398 100644
--- a/configs/phycore_pcl063_ull_defconfig
+++ b/configs/phycore_pcl063_ull_defconfig
@@ -19,7 +19,7 @@
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run mmc_mmc_fit"
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
diff --git a/configs/pico-dwarf-imx6ul_defconfig b/configs/pico-dwarf-imx6ul_defconfig
index 4fd5880..e9a5302 100644
--- a/configs/pico-dwarf-imx6ul_defconfig
+++ b/configs/pico-dwarf-imx6ul_defconfig
@@ -26,7 +26,7 @@
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-dwarf.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTMENU=y
diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig
index 2cd906a..b598d8a 100644
--- a/configs/pico-dwarf-imx7d_defconfig
+++ b/configs/pico-dwarf-imx7d_defconfig
@@ -22,10 +22,11 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb"
+# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL_MAX_SIZE=0xe000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_MAX_SIZE=0x100000
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig
index c430b4d..b3a1023 100644
--- a/configs/pico-hobbit-imx6ul_defconfig
+++ b/configs/pico-hobbit-imx6ul_defconfig
@@ -27,7 +27,7 @@
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-hobbit.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTMENU=y
diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig
index b63281e..93ef6b5 100644
--- a/configs/pico-hobbit-imx7d_defconfig
+++ b/configs/pico-hobbit-imx7d_defconfig
@@ -22,10 +22,11 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-hobbit.dtb"
+# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL_MAX_SIZE=0xe000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_MAX_SIZE=0x100000
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig
index be7b119..39aa63c 100644
--- a/configs/pico-imx6_defconfig
+++ b/configs/pico-imx6_defconfig
@@ -27,7 +27,7 @@
CONFIG_BOOTCOMMAND="run default_boot"
CONFIG_DEFAULT_FDT_FILE="ask"
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index a6cbc51..6f84b6a 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -27,7 +27,7 @@
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="ask"
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTMENU=y
diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig
index 546e1e6..18fb5d2 100644
--- a/configs/pico-imx7d_bl33_defconfig
+++ b/configs/pico-imx7d_bl33_defconfig
@@ -24,10 +24,11 @@
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
+# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL_MAX_SIZE=0xe000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_MAX_SIZE=0x100000
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig
index f11e1f4..44caa8e 100644
--- a/configs/pico-imx7d_defconfig
+++ b/configs/pico-imx7d_defconfig
@@ -22,10 +22,11 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="ask"
+# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL_MAX_SIZE=0xe000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_MAX_SIZE=0x100000
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
diff --git a/configs/pico-imx8mq_defconfig b/configs/pico-imx8mq_defconfig
index 4ee9b88..f2c342e 100644
--- a/configs/pico-imx8mq_defconfig
+++ b/configs/pico-imx8mq_defconfig
@@ -38,10 +38,10 @@
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig
index 2cd906a..b598d8a 100644
--- a/configs/pico-nymph-imx7d_defconfig
+++ b/configs/pico-nymph-imx7d_defconfig
@@ -22,10 +22,11 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb"
+# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL_MAX_SIZE=0xe000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_MAX_SIZE=0x100000
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig
index 3c822d1..3af968d 100644
--- a/configs/pico-pi-imx6ul_defconfig
+++ b/configs/pico-pi-imx6ul_defconfig
@@ -27,7 +27,7 @@
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-pi.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTMENU=y
@@ -70,6 +70,7 @@
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_SPL_USB_HOST=y
diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig
index 3e26aae..5b615da 100644
--- a/configs/pico-pi-imx7d_defconfig
+++ b/configs/pico-pi-imx7d_defconfig
@@ -22,10 +22,11 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb"
+# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL_MAX_SIZE=0xe000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_MAX_SIZE=0x100000
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
@@ -75,6 +76,8 @@
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_SPL_USB_HOST=y
@@ -94,3 +97,4 @@
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_BMP_16BPP=y
+CONFIG_IMX_WATCHDOG=y
diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig
index 6dac609..4712b8e 100644
--- a/configs/pine_h64_defconfig
+++ b/configs/pine_h64_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN50I_H6=y
CONFIG_SUNXI_DRAM_H6_LPDDR3=y
-CONFIG_MACPWR="PC16"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB3_VBUS_PIN="PL5"
CONFIG_SPL_SPI_SUNXI=y
diff --git a/configs/pinebook_defconfig b/configs/pinebook_defconfig
index 26918dd..8d00a4f 100644
--- a/configs/pinebook_defconfig
+++ b/configs/pinebook_defconfig
@@ -10,7 +10,6 @@
CONFIG_R_I2C_ENABLE=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
-CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_PWM=y
CONFIG_PWM_SUNXI=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig
index 568e15c..92f433d 100644
--- a/configs/plutux_defconfig
+++ b/configs/plutux_defconfig
@@ -19,10 +19,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x90000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra20 (Plutux) # "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2084
diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig
index cbbade3..101f20f 100644
--- a/configs/pogo_v4_defconfig
+++ b/configs/pogo_v4_defconfig
@@ -16,7 +16,9 @@
CONFIG_IDENT_STRING="\nPogoplug V4"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_PCI=y
-CONFIG_DISTRO_DEFAULTS=y
+CONFIG_LTO=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_BOOTSTAGE=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=10
@@ -54,7 +56,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
-# CONFIG_DM_WARN is not set
CONFIG_SATA_MV=y
CONFIG_SYS_SATA_MAX_DEVICE=1
CONFIG_LBA48=y
diff --git a/configs/pomelo_defconfig b/configs/pomelo_defconfig
index be0f768..2f93365 100644
--- a/configs/pomelo_defconfig
+++ b/configs/pomelo_defconfig
@@ -14,7 +14,6 @@
CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_SYS_PROMPT="pomelo#"
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=280
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index a426bf1..2ea007d 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -37,9 +37,9 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_BSS_START_ADDR=0x80000000
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80208000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000
CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig
index 5f0746e..de7267e 100644
--- a/configs/qemu-ppce500_defconfig
+++ b/configs/qemu-ppce500_defconfig
@@ -11,17 +11,16 @@
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_USE_UBOOTPATH=y
+CONFIG_SYS_MONITOR_BASE=0x00F00000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_MONITOR_BASE=0x00F00000
CONFIG_BOOTDELAY=1
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdtcontroladdr"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_REGINFO=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig
index 9ace68e..cf74a48 100644
--- a/configs/qemu-riscv32_defconfig
+++ b/configs/qemu-riscv32_defconfig
@@ -12,8 +12,6 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig
index 0c7389e..aeef2f3 100644
--- a/configs/qemu-riscv32_smode_defconfig
+++ b/configs/qemu-riscv32_smode_defconfig
@@ -13,8 +13,6 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig
index 9a81bdd..db9c971 100644
--- a/configs/qemu-riscv32_spl_defconfig
+++ b/configs/qemu-riscv32_spl_defconfig
@@ -18,9 +18,7 @@
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_SPL_MAX_SIZE=0x100000
CONFIG_SPL_BSS_START_ADDR=0x84000000
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_BOOTM_LEN=0x4000000
# CONFIG_CMD_MII is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
index 9a8bbef..9fb40b2 100644
--- a/configs/qemu-riscv64_defconfig
+++ b/configs/qemu-riscv64_defconfig
@@ -12,8 +12,6 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig
index 1d0f021..e3b123c 100644
--- a/configs/qemu-riscv64_smode_defconfig
+++ b/configs/qemu-riscv64_smode_defconfig
@@ -15,8 +15,6 @@
CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig
index bb10145..d6bf313 100644
--- a/configs/qemu-riscv64_spl_defconfig
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -17,9 +17,7 @@
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_SPL_MAX_SIZE=0x100000
CONFIG_SPL_BSS_START_ADDR=0x84000000
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_BOOTM_LEN=0x4000000
# CONFIG_CMD_MII is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig
index f6359ca..2ff49fb 100644
--- a/configs/qemu-x86_64_defconfig
+++ b/configs/qemu-x86_64_defconfig
@@ -18,11 +18,11 @@
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_X86_OFFSET_U_BOOT=0xfff00000
+CONFIG_SYS_MONITOR_BASE=0x01110000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTSTD_FULL=y
CONFIG_BOOTSTD_DEFAULTS=y
-CONFIG_SYS_MONITOR_BASE=0x01110000
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_SHOW_BOOT_PROGRESS=y
@@ -33,7 +33,6 @@
CONFIG_LOGF_FUNC=y
CONFIG_SPL_LOG=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_PCI_INIT_R=y
CONFIG_BLOBLIST=y
CONFIG_BLOBLIST_ADDR=0x10000
@@ -47,7 +46,6 @@
CONFIG_SPL_PCI=y
CONFIG_SPL_PCH=y
CONFIG_SPL_RTC=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 24682a5..246ac6b 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -23,9 +23,7 @@
CONFIG_LOG=y
CONFIG_LOGF_FUNC=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_PCI_INIT_R=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig
index 94bd966..c010c25 100644
--- a/configs/qemu_arm64_defconfig
+++ b/configs/qemu_arm64_defconfig
@@ -27,15 +27,12 @@
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_PCI_INIT_R=y
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_DFU=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
CONFIG_CMD_TPM=y
CONFIG_CMD_MTDPARTS=y
CONFIG_ENV_IS_IN_FLASH=y
@@ -68,7 +65,7 @@
CONFIG_SYSRESET_CMD_POWEROFF=y
CONFIG_SYSRESET_PSCI=y
CONFIG_TPM2_MMIO=y
-CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_PCI=y
+CONFIG_SEMIHOSTING=y
CONFIG_TPM=y
diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig
index 7cb1e9f..9cc1f5f 100644
--- a/configs/qemu_arm_defconfig
+++ b/configs/qemu_arm_defconfig
@@ -28,15 +28,12 @@
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_PCI_INIT_R=y
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_DFU=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
CONFIG_CMD_TPM=y
CONFIG_CMD_MTDPARTS=y
CONFIG_ENV_IS_IN_FLASH=y
@@ -69,7 +66,6 @@
CONFIG_SYSRESET_CMD_POWEROFF=y
CONFIG_SYSRESET_PSCI=y
CONFIG_TPM2_MMIO=y
-CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_PCI=y
CONFIG_TPM=y
diff --git a/configs/quartz64-a-rk3566_defconfig b/configs/quartz64-a-rk3566_defconfig
index d55b224..bf4d4cd 100644
--- a/configs/quartz64-a-rk3566_defconfig
+++ b/configs/quartz64-a-rk3566_defconfig
@@ -52,6 +52,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PMIC=y
@@ -80,6 +81,9 @@
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
diff --git a/configs/quartz64-b-rk3566_defconfig b/configs/quartz64-b-rk3566_defconfig
index b98c81f..358687a 100644
--- a/configs/quartz64-b-rk3566_defconfig
+++ b/configs/quartz64-b-rk3566_defconfig
@@ -50,6 +50,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PMIC=y
@@ -78,6 +79,9 @@
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
diff --git a/configs/quartzpro64-rk3588_defconfig b/configs/quartzpro64-rk3588_defconfig
new file mode 100644
index 0000000..85af4c4
--- /dev/null
+++ b/configs/quartzpro64-rk3588_defconfig
@@ -0,0 +1,71 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_DEFAULT_DEVICE_TREE="rk3588-quartzpro64"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_QUARTZPRO64_RK3588=y
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-quartzpro64.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig
index 55bc303..1f7aa03 100644
--- a/configs/r8a77990_ebisu_defconfig
+++ b/configs/r8a77990_ebisu_defconfig
@@ -17,9 +17,9 @@
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_LTO=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_BASE=0x00000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_MONITOR_BASE=0x00000000
CONFIG_USE_BOOTARGS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77990-ebisu.dtb; booti 0x48080000 - 0x48000000"
diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig
index 1c1b725..22a8042 100644
--- a/configs/r8a77995_draak_defconfig
+++ b/configs/r8a77995_draak_defconfig
@@ -17,9 +17,9 @@
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_LTO=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_BASE=0x00000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_MONITOR_BASE=0x00000000
CONFIG_USE_BOOTARGS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77995-draak.dtb; booti 0x48080000 - 0x48000000"
diff --git a/configs/r8a779f0_spider_defconfig b/configs/r8a779f0_spider_defconfig
index 0edacc4..f250d1a 100644
--- a/configs/r8a779f0_spider_defconfig
+++ b/configs/r8a779f0_spider_defconfig
@@ -31,7 +31,9 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
+CONFIG_CMD_UFS=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
@@ -46,9 +48,13 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
+CONFIG_LBA48=y
+CONFIG_SYS_64BIT_LBA=y
CONFIG_CLK=y
+CONFIG_CLK_GPIO=y
CONFIG_CLK_RENESAS=y
CONFIG_RCAR_GPIO=y
+CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_MMC_IO_VOLTAGE=y
@@ -67,8 +73,13 @@
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
CONFIG_BAUDRATE=1843200
CONFIG_SCIF_CONSOLE=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_RENESAS_RPC_SPI=y
+CONFIG_UFS=y
+CONFIG_UFS_RENESAS=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=131072
diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig
index f897771..4b606dc 100644
--- a/configs/radxa-cm3-io-rk3566_defconfig
+++ b/configs/radxa-cm3-io-rk3566_defconfig
@@ -47,6 +47,7 @@
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
@@ -59,8 +60,9 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_SPL_PINCTRL=y
diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig
index a905100..2dfff6a 100644
--- a/configs/radxa-e25-rk3568_defconfig
+++ b/configs/radxa-e25-rk3568_defconfig
@@ -54,7 +54,6 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
-CONFIG_AHCI_PCI=y
CONFIG_DWC_AHCI=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
diff --git a/configs/radxa-zero2_defconfig b/configs/radxa-zero2_defconfig
index b1aa3c2..b795681 100644
--- a/configs/radxa-zero2_defconfig
+++ b/configs/radxa-zero2_defconfig
@@ -16,12 +16,17 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=32
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -32,6 +37,7 @@
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
@@ -46,6 +52,7 @@
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/radxa-zero_defconfig b/configs/radxa-zero_defconfig
index 23f30f6..103ff8a 100644
--- a/configs/radxa-zero_defconfig
+++ b/configs/radxa-zero_defconfig
@@ -16,12 +16,17 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=32
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -32,6 +37,7 @@
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index 7df30f8..9f538a2 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -37,9 +37,9 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_BSS_START_ADDR=0x80000000
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80208000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000
CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig
index 6aaf24e..e045cf2 100644
--- a/configs/rcar3_salvator-x_defconfig
+++ b/configs/rcar3_salvator-x_defconfig
@@ -16,10 +16,10 @@
CONFIG_PCI=y
CONFIG_LTO=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_BASE=0x00000000
CONFIG_FIT=y
# CONFIG_BOOTSTD is not set
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_MONITOR_BASE=0x00000000
CONFIG_USE_BOOTARGS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77950-salvator-x.dtb; booti 0x48080000 - 0x48000000"
@@ -58,7 +58,6 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_VERSION_VARIABLE=y
CONFIG_REGMAP=y
diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig
index 489e710..acbc314 100644
--- a/configs/rcar3_ulcb_defconfig
+++ b/configs/rcar3_ulcb_defconfig
@@ -16,9 +16,9 @@
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_LTO=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_BASE=0x00000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_MONITOR_BASE=0x00000000
CONFIG_USE_BOOTARGS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77950-ulcb.dtb; booti 0x48080000 - 0x48000000"
diff --git a/configs/renesas_rzg2l_smarc_defconfig b/configs/renesas_rzg2l_smarc_defconfig
new file mode 100644
index 0000000..e17d226
--- /dev/null
+++ b/configs/renesas_rzg2l_smarc_defconfig
@@ -0,0 +1,52 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=16666666
+CONFIG_SYS_INIT_SP_BSS_OFFSET=1048576
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x80000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xFFFE0000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="r9a07g044l2-smarc"
+CONFIG_RZG2L=y
+CONFIG_SYS_MONITOR_LEN=1048576
+CONFIG_SYS_LOAD_ADDR=0x58000000
+CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTARGS=y
+# CONFIG_BOARD_EARLY_INIT_F is not set
+CONFIG_SYS_MALLOC_BOOTPARAMS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_PBSIZE=2068
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_MULTI_DTB_FIT_LZO=y
+CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_VERSION_VARIABLE=y
+CONFIG_REGMAP=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+# CONFIG_CLK_RCAR_GEN3 is not set
+CONFIG_GPIO_HOG=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig
index cdec0c5..b314636 100644
--- a/configs/ringneck-px30_defconfig
+++ b/configs/ringneck-px30_defconfig
@@ -38,11 +38,12 @@
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
@@ -53,6 +54,7 @@
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNZIP is not set
CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
index 98fef09..6ab405d 100644
--- a/configs/riotboard_defconfig
+++ b/configs/riotboard_defconfig
@@ -30,12 +30,12 @@
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
CONFIG_SPL_FS_LOAD_ARGS_NAME="imx6dl-riotboard.dtb"
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x13000000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x13000000
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GPIO=y
diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig
index 9a789b2..7502da5 100644
--- a/configs/roc-cc-rk3308_defconfig
+++ b/configs/roc-cc-rk3308_defconfig
@@ -11,7 +11,6 @@
CONFIG_DEFAULT_DEVICE_TREE="rk3308-roc-cc"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3308=y
-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_ROC_RK3308_CC=y
CONFIG_SPL_STACK_R_ADDR=0xc00000
@@ -24,6 +23,7 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=0
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-roc-cc.dtb"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0x20000
@@ -47,7 +47,7 @@
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_SLEEP is not set
-# CONFIG_DOS_PARTITION is not set
+# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
CONFIG_SPL_OF_CONTROL=y
diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 44ff054..28d157d 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -49,6 +49,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PMIC=y
@@ -76,8 +77,9 @@
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_XTX=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig
index cc3274a..9908a4b 100644
--- a/configs/rock-pi-s-rk3308_defconfig
+++ b/configs/rock-pi-s-rk3308_defconfig
@@ -9,9 +9,9 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000
CONFIG_DEFAULT_DEVICE_TREE="rk3308-rock-pi-s"
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3308=y
-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_EVB_RK3308=y
CONFIG_SPL_STACK_R_ADDR=0xc00000
@@ -24,7 +24,7 @@
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_BOOTDELAY=0
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-rock-pi-s.dtb"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0x20000
@@ -48,7 +48,7 @@
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_SLEEP is not set
-# CONFIG_DOS_PARTITION is not set
+# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
CONFIG_SPL_OF_CONTROL=y
diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig
index 39e3525..a6471a5 100644
--- a/configs/rock5a-rk3588s_defconfig
+++ b/configs/rock5a-rk3588s_defconfig
@@ -39,13 +39,16 @@
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
@@ -58,14 +61,26 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_SPL_PINCTRL=y
-CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_ERRNO_STR=y
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 3fa65cb..0595325 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -26,6 +26,7 @@
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
@@ -35,7 +36,6 @@
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_PCI_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -63,6 +63,8 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
+CONFIG_AHCI_PCI=y
+CONFIG_DWC_AHCI=y
CONFIG_SPL_CLK=y
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
@@ -78,9 +80,9 @@
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_XTX=y
-CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHYLIB=y
CONFIG_RTL8169=y
-CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
@@ -89,6 +91,8 @@
CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
@@ -97,7 +101,6 @@
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
-# CONFIG_USB_XHCI_DWC3_OF_SIMPLE is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig
index ab6e6bc..ac3b40c 100644
--- a/configs/rpi_0_w_defconfig
+++ b/configs/rpi_0_w_defconfig
@@ -13,11 +13,11 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_FDT_SIMPLEFB=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
-CONFIG_FDT_SIMPLEFB=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_GPIO=y
diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig
index 0dea092..b6e06cf 100644
--- a/configs/rpi_2_defconfig
+++ b/configs/rpi_2_defconfig
@@ -14,11 +14,11 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_FDT_SIMPLEFB=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
-CONFIG_FDT_SIMPLEFB=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_GPIO=y
diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig
index 0ccc93d..eadc418 100644
--- a/configs/rpi_3_32b_defconfig
+++ b/configs/rpi_3_32b_defconfig
@@ -13,11 +13,11 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_FDT_SIMPLEFB=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
-CONFIG_FDT_SIMPLEFB=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_GPIO=y
diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig
index 53f7f31..0e2faee 100644
--- a/configs/rpi_3_b_plus_defconfig
+++ b/configs/rpi_3_b_plus_defconfig
@@ -12,11 +12,11 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_FDT_SIMPLEFB=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
-CONFIG_FDT_SIMPLEFB=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_GPIO=y
diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig
index 84b61f8..6890af4 100644
--- a/configs/rpi_3_defconfig
+++ b/configs/rpi_3_defconfig
@@ -12,11 +12,11 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_FDT_SIMPLEFB=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
-CONFIG_FDT_SIMPLEFB=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_GPIO=y
diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
index 766c983..734335c 100644
--- a/configs/rpi_4_32b_defconfig
+++ b/configs/rpi_4_32b_defconfig
@@ -12,12 +12,12 @@
CONFIG_PCI=y
CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_FDT_SIMPLEFB=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="pci enum; usb start;"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
-CONFIG_FDT_SIMPLEFB=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_DFU=y
diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
index 553d47b..2541b83 100644
--- a/configs/rpi_4_defconfig
+++ b/configs/rpi_4_defconfig
@@ -12,12 +12,12 @@
CONFIG_PCI=y
CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_FDT_SIMPLEFB=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="pci enum; usb start;"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
-CONFIG_FDT_SIMPLEFB=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_DFU=y
diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
index 7ff166a..f9dade1 100644
--- a/configs/rpi_arm64_defconfig
+++ b/configs/rpi_arm64_defconfig
@@ -12,12 +12,12 @@
CONFIG_PCI=y
CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_FDT_SIMPLEFB=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="pci enum; usb start;"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
-CONFIG_FDT_SIMPLEFB=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_GPIO=y
diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
index d049d0f..29c1006 100644
--- a/configs/rpi_defconfig
+++ b/configs/rpi_defconfig
@@ -13,11 +13,11 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_FDT_SIMPLEFB=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
-CONFIG_FDT_SIMPLEFB=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_GPIO=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index b4a78f5..ccf2566 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -37,9 +37,9 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_BSS_START_ADDR=0x80000000
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80208000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000
CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/s400_defconfig b/configs/s400_defconfig
index 9a7d520..8e22c95 100644
--- a/configs/s400_defconfig
+++ b/configs/s400_defconfig
@@ -16,12 +16,17 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=32
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -31,6 +36,7 @@
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
diff --git a/configs/s5p4418_nanopi2_defconfig b/configs/s5p4418_nanopi2_defconfig
index e058b67..fe2475f 100644
--- a/configs/s5p4418_nanopi2_defconfig
+++ b/configs/s5p4418_nanopi2_defconfig
@@ -26,8 +26,8 @@
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=1
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="nanopi2# "
diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig
index 80a7f6b..c364f0c 100644
--- a/configs/s5p_goni_defconfig
+++ b/configs/s5p_goni_defconfig
@@ -63,4 +63,3 @@
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DWC2_OTG_PHY=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_FUNCTION_THOR=y
diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig
index d14a589..f585c51 100644
--- a/configs/s5pc210_universal_defconfig
+++ b/configs/s5pc210_universal_defconfig
@@ -62,4 +62,3 @@
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DWC2_OTG_PHY=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_FUNCTION_THOR=y
diff --git a/configs/sam9x60_curiosity_mmc1_defconfig b/configs/sam9x60_curiosity_mmc1_defconfig
index 8f2f6d9..a2453701 100644
--- a/configs/sam9x60_curiosity_mmc1_defconfig
+++ b/configs/sam9x60_curiosity_mmc1_defconfig
@@ -13,6 +13,7 @@
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sam9x60_curiosity"
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -79,6 +80,7 @@
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
+CONFIG_RESET_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
diff --git a/configs/sam9x60_curiosity_mmc_defconfig b/configs/sam9x60_curiosity_mmc_defconfig
index 5999b5d..38ec241 100644
--- a/configs/sam9x60_curiosity_mmc_defconfig
+++ b/configs/sam9x60_curiosity_mmc_defconfig
@@ -13,6 +13,7 @@
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sam9x60_curiosity"
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -22,7 +23,7 @@
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="mem=128M console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait"
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x21000000 at91-sam9x60_curiosity.dtb; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
@@ -38,6 +39,8 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTP_BOOTFILESIZE=y
@@ -50,6 +53,8 @@
CONFIG_ENV_IS_IN_FAT=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_CCF=y
CONFIG_CLK_AT91=y
@@ -60,17 +65,27 @@
CONFIG_AT91_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
+CONFIG_ATMEL_EBI=y
+CONFIG_MFD_ATMEL_SMC=y
CONFIG_I2C_EEPROM=y
CONFIG_MICROCHIP_FLEXCOM=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_DM_NAND_ATMEL=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_PHY_MICREL=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
+CONFIG_RESET_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_AT91=y
CONFIG_TIMER=y
CONFIG_MCHP_PIT64B_TIMER=y
CONFIG_W1=y
diff --git a/configs/sam9x60ek_mmc_defconfig b/configs/sam9x60ek_mmc_defconfig
index 06680ac..7cb4ab1 100644
--- a/configs/sam9x60ek_mmc_defconfig
+++ b/configs/sam9x60ek_mmc_defconfig
@@ -14,6 +14,7 @@
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek"
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -87,6 +88,7 @@
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
+CONFIG_RESET_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
diff --git a/configs/sam9x60ek_nandflash_defconfig b/configs/sam9x60ek_nandflash_defconfig
index fea200d..4bfd0e8 100644
--- a/configs/sam9x60ek_nandflash_defconfig
+++ b/configs/sam9x60ek_nandflash_defconfig
@@ -13,6 +13,7 @@
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek"
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -89,6 +90,7 @@
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
+CONFIG_RESET_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
diff --git a/configs/sam9x60ek_qspiflash_defconfig b/configs/sam9x60ek_qspiflash_defconfig
index a1f8c9f..c7224da 100644
--- a/configs/sam9x60ek_qspiflash_defconfig
+++ b/configs/sam9x60ek_qspiflash_defconfig
@@ -13,6 +13,7 @@
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek"
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -88,6 +89,7 @@
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
+CONFIG_RESET_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
diff --git a/configs/sama5d27_giantboard_defconfig b/configs/sama5d27_giantboard_defconfig
index e58b454..677658d 100644
--- a/configs/sama5d27_giantboard_defconfig
+++ b/configs/sama5d27_giantboard_defconfig
@@ -46,8 +46,8 @@
CONFIG_SPL_BSS_START_ADDR=0x20000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig
index 65466eb..ec82311 100644
--- a/configs/sama5d27_som1_ek_mmc1_defconfig
+++ b/configs/sama5d27_som1_ek_mmc1_defconfig
@@ -43,8 +43,8 @@
CONFIG_SPL_BSS_START_ADDR=0x20000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig
index cb47dc6..f303744 100644
--- a/configs/sama5d27_som1_ek_mmc_defconfig
+++ b/configs/sama5d27_som1_ek_mmc_defconfig
@@ -44,8 +44,8 @@
CONFIG_SPL_BSS_START_ADDR=0x20000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig
index 702495e..eed190d 100644
--- a/configs/sama5d27_som1_ek_qspiflash_defconfig
+++ b/configs/sama5d27_som1_ek_qspiflash_defconfig
@@ -42,8 +42,8 @@
CONFIG_SPL_BSS_START_ADDR=0x20000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig
index 7921009..2b8461d 100644
--- a/configs/sama5d27_wlsom1_ek_mmc_defconfig
+++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig
@@ -43,8 +43,8 @@
CONFIG_SPL_BSS_START_ADDR=0x20000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_DISPLAY_PRINT=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_AT91_MCK_BYPASS=y
diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
index a7c8474..f47183a 100644
--- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
+++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
@@ -43,8 +43,8 @@
CONFIG_SPL_BSS_START_ADDR=0x20000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_DISPLAY_PRINT=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_DM_SPI_FLASH=y
diff --git a/configs/sama5d29_curiosity_mmc1_defconfig b/configs/sama5d29_curiosity_mmc1_defconfig
new file mode 100644
index 0000000..bef7dbe
--- /dev/null
+++ b/configs/sama5d29_curiosity_mmc1_defconfig
@@ -0,0 +1,119 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_AT91=y
+CONFIG_TEXT_BASE=0x26f00000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x40000
+CONFIG_TARGET_SAMA5D29_CURIOSITY=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20044000
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d29_curiosity"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_BASE=0xf801c000
+CONFIG_DEBUG_UART_CLOCK=82000000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_MEMTEST_START=0x20000000
+CONFIG_SYS_MEMTEST_END=0x30000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+# CONFIG_BOOTSTD is not set
+CONFIG_QSPI_BOOT=y
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk1p2 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="fatload mmc 1:1 0x21000000 at91-sama5d29_curiosity.dtb; fatload mmc 1:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
+CONFIG_BOARD_TYPES=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEM_SEARCH=y
+CONFIG_CMD_MX_CYCLIC=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_STRINGS=y
+CONFIG_CMD_DM=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_XXD=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MTDPARTS_SPREAD=y
+CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
+CONFIG_MTDIDS_DEFAULT="nor0=nor0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:256k(bootstrap)ro,1M(u-boot)ro,256k(env)ro,512k(dtb)ro,6M(kernel)ro"
+CONFIG_OF_CONTROL=y
+# CONFIG_OF_TAG_MIGRATE is not set
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_HOSTNAME=y
+CONFIG_HOSTNAME="SAMA5D29"
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_NET is not set
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=2
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SST=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_RESET_AT91=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_AT91=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_TCB_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_VIDEO=y
+CONFIG_ATMEL_HLCD=y
+CONFIG_W1=y
+CONFIG_W1_GPIO=y
+CONFIG_W1_EEPROM=y
+CONFIG_W1_EEPROM_DS24XXX=y
+CONFIG_CMD_DHRYSTONE=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/sama5d29_curiosity_mmc_defconfig b/configs/sama5d29_curiosity_mmc_defconfig
new file mode 100644
index 0000000..c3ccea3
--- /dev/null
+++ b/configs/sama5d29_curiosity_mmc_defconfig
@@ -0,0 +1,118 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_AT91=y
+CONFIG_TEXT_BASE=0x26f00000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x40000
+CONFIG_TARGET_SAMA5D29_CURIOSITY=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20044000
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d29_curiosity"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_BASE=0xf801c000
+CONFIG_DEBUG_UART_CLOCK=82000000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_MEMTEST_START=0x20000000
+CONFIG_SYS_MEMTEST_END=0x30000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+# CONFIG_BOOTSTD is not set
+CONFIG_QSPI_BOOT=y
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x21000000 at91-sama5d29_curiosity.dtb; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
+CONFIG_BOARD_TYPES=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEM_SEARCH=y
+CONFIG_CMD_MX_CYCLIC=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_STRINGS=y
+CONFIG_CMD_DM=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_XXD=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MTDPARTS_SPREAD=y
+CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
+CONFIG_MTDIDS_DEFAULT="nor0=nor0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:256k(bootstrap)ro,1M(u-boot)ro,256k(env)ro,512k(dtb)ro,6M(kernel)ro"
+CONFIG_OF_CONTROL=y
+# CONFIG_OF_TAG_MIGRATE is not set
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_HOSTNAME=y
+CONFIG_HOSTNAME="SAMA5D29"
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_NET is not set
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=2
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SST=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_RESET_AT91=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_AT91=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_TCB_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_VIDEO=y
+CONFIG_ATMEL_HLCD=y
+CONFIG_W1=y
+CONFIG_W1_GPIO=y
+CONFIG_W1_EEPROM=y
+CONFIG_W1_EEPROM_DS24XXX=y
+CONFIG_CMD_DHRYSTONE=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/sama5d29_curiosity_qspiflash_defconfig b/configs/sama5d29_curiosity_qspiflash_defconfig
new file mode 100644
index 0000000..952cc0e
--- /dev/null
+++ b/configs/sama5d29_curiosity_qspiflash_defconfig
@@ -0,0 +1,119 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_AT91=y
+CONFIG_TEXT_BASE=0x26f00000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x40000
+CONFIG_TARGET_SAMA5D29_CURIOSITY=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20044000
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d29_curiosity"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_BASE=0xf801c000
+CONFIG_DEBUG_UART_CLOCK=82000000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_MEMTEST_START=0x20000000
+CONFIG_SYS_MEMTEST_END=0x30000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+# CONFIG_BOOTSTD is not set
+CONFIG_QSPI_BOOT=y
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x21000000 0x180000 0x80000; sf read 0x22000000 0x200000 0x600000; bootz 0x22000000 - 0x21000000"
+CONFIG_BOARD_TYPES=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEM_SEARCH=y
+CONFIG_CMD_MX_CYCLIC=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_STRINGS=y
+CONFIG_CMD_DM=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_XXD=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MTDPARTS_SPREAD=y
+CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
+CONFIG_MTDIDS_DEFAULT="nor0=nor0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:256k(bootstrap)ro,1M(u-boot)ro,256k(env)ro,512k(dtb)ro,6M(kernel)ro"
+CONFIG_OF_CONTROL=y
+# CONFIG_OF_TAG_MIGRATE is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_HOSTNAME=y
+CONFIG_HOSTNAME="SAMA5D29"
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_NET is not set
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=2
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SST=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_RESET_AT91=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_AT91=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_TCB_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_VIDEO=y
+CONFIG_ATMEL_HLCD=y
+CONFIG_W1=y
+CONFIG_W1_GPIO=y
+CONFIG_W1_EEPROM=y
+CONFIG_W1_EEPROM_DS24XXX=y
+CONFIG_FAT_WRITE=y
+CONFIG_CMD_DHRYSTONE=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig
index 9456b9e..7ad94ec 100644
--- a/configs/sama5d2_icp_mmc_defconfig
+++ b/configs/sama5d2_icp_mmc_defconfig
@@ -44,8 +44,8 @@
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_DISPLAY_PRINT=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_RAM_SUPPORT=y
diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig
index 9ef0ff4..7c37336 100644
--- a/configs/sama5d2_xplained_emmc_defconfig
+++ b/configs/sama5d2_xplained_emmc_defconfig
@@ -43,8 +43,8 @@
CONFIG_SPL_BSS_START_ADDR=0x20000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index aed9eda..26b281f 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -45,8 +45,8 @@
CONFIG_SPL_BSS_START_ADDR=0x20000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig
index c9a2072..9ed35e3 100644
--- a/configs/sama5d2_xplained_qspiflash_defconfig
+++ b/configs/sama5d2_xplained_qspiflash_defconfig
@@ -46,8 +46,8 @@
CONFIG_SPL_BSS_START_ADDR=0x20000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index c01a0c4..b87a63f 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -47,8 +47,8 @@
CONFIG_SPL_BSS_START_ADDR=0x20000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index 9b4affe..fc0de8c 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -42,8 +42,8 @@
CONFIG_SPL_BSS_START_ADDR=0x20000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig
index 2fcb2b7..a1b6122 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -39,8 +39,8 @@
CONFIG_SPL_BSS_START_ADDR=0x20000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_BASE=y
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index bfe19e0..631e85e 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -44,8 +44,8 @@
CONFIG_SPL_BSS_START_ADDR=0x20000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig
index 2978a7e..6278a6c 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -41,8 +41,8 @@
CONFIG_SPL_BSS_START_ADDR=0x20000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_BASE=y
diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig
index 1d30843..5f47f8b 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -44,8 +44,8 @@
CONFIG_SPL_BSS_START_ADDR=0x20000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index befe26b..9f0349e 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -44,8 +44,8 @@
CONFIG_SPL_BSS_START_ADDR=0x20000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig
index 749c8ba..d12f749 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -41,8 +41,8 @@
CONFIG_SPL_BSS_START_ADDR=0x20000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_BASE=y
diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index 02a0de3..0d239ef 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -46,8 +46,8 @@
CONFIG_SPL_BSS_START_ADDR=0x20000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index 48607e1..4139fcf 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -44,8 +44,8 @@
CONFIG_SPL_BSS_START_ADDR=0x20000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig
index 60c936b..27bfcdf 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -41,8 +41,8 @@
CONFIG_SPL_BSS_START_ADDR=0x20000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_BASE=y
diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig
index aee8169..f41c4e9 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -44,8 +44,8 @@
CONFIG_SPL_BSS_START_ADDR=0x20000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index 138a99b..6c488ba 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -4,7 +4,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sandbox64"
CONFIG_DM_RESET=y
CONFIG_PRE_CON_BUF_ADDR=0x100000
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_PCI=y
CONFIG_SANDBOX64=y
@@ -14,6 +13,7 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
@@ -29,7 +29,6 @@
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_BOOTEFI_HELLO=y
# CONFIG_CMD_ELF is not set
-CONFIG_CMD_XXD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_ERASEENV=y
@@ -51,7 +50,6 @@
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_LOADM=y
-CONFIG_CMD_MBR=y
CONFIG_CMD_OSD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_READ=y
@@ -59,9 +57,11 @@
CONFIG_CMD_SPI=y
CONFIG_CMD_TEMPERATURE=y
CONFIG_CMD_USB=y
+CONFIG_CMD_RKMTD=y
CONFIG_CMD_WDT=y
CONFIG_CMD_WRITE=y
CONFIG_CMD_CAT=y
+CONFIG_CMD_XXD=y
CONFIG_BOOTP_DNS2=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TFTPSRV=y
@@ -237,6 +237,7 @@
CONFIG_TIMER_EARLY=y
CONFIG_SANDBOX_TIMER=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_EMUL=y
CONFIG_USB_KEYBOARD=y
CONFIG_VIDEO=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 62bc182..bc5bcb2 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -4,7 +4,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_DM_RESET=y
CONFIG_PRE_CON_BUF_ADDR=0xf0000
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
@@ -15,6 +14,7 @@
CONFIG_FIT_CIPHER=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_MEASURED_BOOT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
@@ -48,7 +48,6 @@
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_ABOOTIMG=y
# CONFIG_CMD_ELF is not set
-CONFIG_CMD_XXD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_ERASEENV=y
@@ -75,8 +74,6 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_LOADM=y
CONFIG_CMD_LSBLK=y
-CONFIG_CMD_MBR=y
-CONFIG_CMD_MMC=y
CONFIG_CMD_MUX=y
CONFIG_CMD_OSD=y
CONFIG_CMD_PCI=y
@@ -86,11 +83,13 @@
CONFIG_CMD_SPI=y
CONFIG_CMD_TEMPERATURE=y
CONFIG_CMD_USB=y
+CONFIG_CMD_RKMTD=y
CONFIG_CMD_WDT=y
CONFIG_CMD_WRITE=y
CONFIG_CMD_AXI=y
CONFIG_CMD_CAT=y
CONFIG_CMD_SETEXPR_FMT=y
+CONFIG_CMD_XXD=y
CONFIG_CMD_AB_SELECT=y
CONFIG_CMD_DHCP6=y
CONFIG_BOOTP_DNS2=y
@@ -227,10 +226,12 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_NVMXIP_QSPI=y
CONFIG_MULTIPLEXER=y
CONFIG_MUX_MMIO=y
CONFIG_NVME_PCI=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
+CONFIG_PCI_FTPCI100=y
CONFIG_PCI_SANDBOX=y
CONFIG_PHY=y
CONFIG_PHY_SANDBOX=y
@@ -240,6 +241,7 @@
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_SANDBOX_POWER_DOMAIN=y
+CONFIG_SCMI_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_ACT8846=y
CONFIG_DM_PMIC_PFUZE100=y
@@ -279,6 +281,7 @@
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_SANDBOX_SERIAL=y
+CONFIG_SM=y
CONFIG_SMEM=y
CONFIG_SANDBOX_SMEM=y
CONFIG_SOUND=y
@@ -298,6 +301,7 @@
CONFIG_TIMER_EARLY=y
CONFIG_SANDBOX_TIMER=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_EMUL=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
@@ -334,12 +338,12 @@
CONFIG_ECDSA=y
CONFIG_ECDSA_VERIFY=y
CONFIG_TPM=y
-CONFIG_SHA384=y
CONFIG_ERRNO_STR=y
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_EFI_CAPSULE_AUTHENTICATE=y
+CONFIG_EFI_CAPSULE_ESL_FILE="board/sandbox/capsule_pub_esl_good.esl"
CONFIG_EFI_SECURE_BOOT=y
CONFIG_TEST_FDTDEC=y
CONFIG_UNIT_TEST=y
diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig
index 8aa2956..0b63772 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -3,7 +3,6 @@
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_DM_RESET=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
@@ -44,14 +43,14 @@
CONFIG_CMD_GPT=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_MBR=y
-CONFIG_CMD_MMC=y
CONFIG_CMD_OSD=y
CONFIG_CMD_PCI=y
+CONFIG_CMD_READ=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_TEMPERATURE=y
CONFIG_CMD_USB=y
+CONFIG_CMD_WRITE=y
CONFIG_BOOTP_DNS2=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TFTPSRV=y
@@ -204,6 +203,7 @@
CONFIG_TIMER_EARLY=y
CONFIG_SANDBOX_TIMER=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_EMUL=y
CONFIG_USB_KEYBOARD=y
CONFIG_VIDEO=y
@@ -227,6 +227,7 @@
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
CONFIG_EFI_CAPSULE_AUTHENTICATE=y
+CONFIG_EFI_CAPSULE_ESL_FILE="board/sandbox/capsule_pub_esl_good.esl"
CONFIG_UNIT_TEST=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig
index 2c6aab6..cd412ee 100644
--- a/configs/sandbox_noinst_defconfig
+++ b/configs/sandbox_noinst_defconfig
@@ -4,14 +4,18 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
+CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
-CONFIG_SYS_LOAD_ADDR=0x0
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_PCI=y
CONFIG_SANDBOX_SPL=y
CONFIG_DEBUG_UART=y
@@ -33,9 +37,26 @@
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_HANDOFF=y
CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xa000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x4000000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x0
CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_ETH=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
+CONFIG_SPL_MMC_WRITE=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_RTC=y
+# CONFIG_SPL_SPI_FLASH_TINY is not set
+CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
@@ -59,7 +80,6 @@
CONFIG_CMD_GPT=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_MBR=y
CONFIG_CMD_OSD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_REMOTEPROC=y
@@ -92,10 +112,13 @@
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_OF_PLATDATA=y
+CONFIG_SPL_OF_REAL=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_EXT4=y
CONFIG_ENV_EXT4_INTERFACE="host"
CONFIG_ENV_EXT4_DEVICE_AND_PART="0:0"
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_NETCONSOLE=y
CONFIG_IP_DEFRAG=y
@@ -113,6 +136,7 @@
CONFIG_ADC_SANDBOX=y
CONFIG_AXI=y
CONFIG_AXI_SANDBOX=y
+CONFIG_SPL_BLK_FS=y
CONFIG_SYS_IDE_MAXBUS=1
CONFIG_SYS_ATA_BASE_ADDR=0x100
CONFIG_SYS_ATA_STRIDE=4
@@ -154,6 +178,7 @@
CONFIG_P2SB=y
CONFIG_PWRSEQ=y
CONFIG_SPL_PWRSEQ=y
+CONFIG_FS_LOADER=y
CONFIG_MMC_SANDBOX=y
CONFIG_SPI_FLASH_SANDBOX=y
CONFIG_SPI_FLASH_ATMEL=y
@@ -215,9 +240,11 @@
CONFIG_SPL_SYSRESET=y
CONFIG_DM_THERMAL=y
CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
CONFIG_TIMER_EARLY=y
CONFIG_SANDBOX_TIMER=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_EMUL=y
CONFIG_USB_KEYBOARD=y
CONFIG_VIDEO=y
@@ -236,7 +263,10 @@
CONFIG_TPM=y
CONFIG_LZ4=y
CONFIG_ZSTD=y
+CONFIG_SPL_LZMA=y
CONFIG_ERRNO_STR=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_UNIT_TEST=y
CONFIG_SPL_UNIT_TEST=y
CONFIG_UT_TIME=y
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index 8d50162..eeccee6 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -10,7 +10,6 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_PCI=y
CONFIG_SANDBOX_SPL=y
@@ -33,9 +32,16 @@
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_HANDOFF=y
CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xa000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x4000000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FPGA=y
CONFIG_SPL_I2C=y
+CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_RTC=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
@@ -60,7 +66,6 @@
CONFIG_CMD_GPT=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_MBR=y
CONFIG_CMD_OSD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_REMOTEPROC=y
@@ -224,6 +229,7 @@
CONFIG_TIMER_EARLY=y
CONFIG_SANDBOX_TIMER=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_EMUL=y
CONFIG_USB_KEYBOARD=y
CONFIG_VIDEO=y
@@ -243,8 +249,11 @@
CONFIG_SPL_CRC8=y
CONFIG_LZ4=y
CONFIG_ZSTD=y
+CONFIG_SPL_LZMA=y
CONFIG_ERRNO_STR=y
CONFIG_SPL_HEXDUMP=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_UNIT_TEST=y
CONFIG_SPL_UNIT_TEST=y
CONFIG_UT_TIME=y
diff --git a/configs/sandbox_vpl_defconfig b/configs/sandbox_vpl_defconfig
index f3a0fd1..293e294 100644
--- a/configs/sandbox_vpl_defconfig
+++ b/configs/sandbox_vpl_defconfig
@@ -15,7 +15,6 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_PCI=y
CONFIG_SANDBOX_SPL=y
@@ -75,7 +74,6 @@
CONFIG_CMD_GPT=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_MBR=y
CONFIG_CMD_OSD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_REMOTEPROC=y
@@ -237,6 +235,7 @@
CONFIG_TIMER_EARLY=y
CONFIG_SANDBOX_TIMER=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_EMUL=y
CONFIG_USB_KEYBOARD=y
CONFIG_VIDEO=y
@@ -256,7 +255,10 @@
CONFIG_ZSTD=y
# CONFIG_VPL_LZMA is not set
CONFIG_ERRNO_STR=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_UNIT_TEST=y
CONFIG_SPL_UNIT_TEST=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
+# CONFIG_SPL_UT_LOAD_OS is not set
diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig
index 4fdc46f..5a332b1 100644
--- a/configs/seaboard_defconfig
+++ b/configs/seaboard_defconfig
@@ -17,10 +17,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x90000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2086
diff --git a/configs/seeed_npi_imx6ull_defconfig b/configs/seeed_npi_imx6ull_defconfig
index 9dec10e..d4f2a88 100644
--- a/configs/seeed_npi_imx6ull_defconfig
+++ b/configs/seeed_npi_imx6ull_defconfig
@@ -21,7 +21,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
diff --git a/configs/sei510_defconfig b/configs/sei510_defconfig
index 63e4ebe..c4a49fb 100644
--- a/configs/sei510_defconfig
+++ b/configs/sei510_defconfig
@@ -21,6 +21,10 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run load_logo"
@@ -34,6 +38,7 @@
CONFIG_CMD_ABOOTIMG=y
# CONFIG_CMD_IMI is not set
CONFIG_CMD_BCB=y
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
# CONFIG_CMD_LOADS is not set
@@ -49,6 +54,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_DFU_RAM=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x6000000
CONFIG_FASTBOOT_FLASH=y
diff --git a/configs/sei610_defconfig b/configs/sei610_defconfig
index ff7bcb3..ae254c6 100644
--- a/configs/sei610_defconfig
+++ b/configs/sei610_defconfig
@@ -21,6 +21,10 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run load_logo"
@@ -34,6 +38,7 @@
CONFIG_CMD_ABOOTIMG=y
# CONFIG_CMD_IMI is not set
CONFIG_CMD_BCB=y
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
# CONFIG_CMD_LOADS is not set
@@ -49,6 +54,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_DFU_RAM=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x6000000
CONFIG_FASTBOOT_FLASH=y
diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig
index f9f0346..f99ce30 100644
--- a/configs/sifive_unleashed_defconfig
+++ b/configs/sifive_unleashed_defconfig
@@ -29,7 +29,7 @@
CONFIG_SPL_MAX_SIZE=0x100000
CONFIG_SPL_BSS_START_ADDR=0x85000000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
index 867611b..6a95ab3 100644
--- a/configs/sifive_unmatched_defconfig
+++ b/configs/sifive_unmatched_defconfig
@@ -35,7 +35,7 @@
CONFIG_SPL_MAX_SIZE=0x100000
CONFIG_SPL_BSS_START_ADDR=0x85000000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_SPI_LOAD=y
@@ -47,6 +47,7 @@
CONFIG_CMD_PWM=y
CONFIG_CMD_GPT_RENAME=y
CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
CONFIG_CMD_USB=y
CONFIG_ENV_SPI_BUS=1
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/slimbootloader_defconfig b/configs/slimbootloader_defconfig
index dbfed81..759fa7d 100644
--- a/configs/slimbootloader_defconfig
+++ b/configs/slimbootloader_defconfig
@@ -11,7 +11,6 @@
CONFIG_BOOTCOMMAND="if test ${bootdev} = 'usb'; then ${bootdev} start; fi; if test ${bootdev} = 'scsi'; then ${bootdev} scan; fi; ${bootdev} info; ${bootfsload} ${bootdev} ${bootdevnum}:${bootdevpart} ${loadaddr} ${bootfile}; ${bootfsload} ${bootdev} ${bootdevnum}:${bootdevpart} ${ramdiskaddr} ${ramdiskfile}; zboot ${loadaddr} 0 ${ramdiskaddr} ${filesize}"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_MMC=y
@@ -19,7 +18,6 @@
CONFIG_BOOTP_BOOTFILESIZE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
-CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index 29153de..10cbccb 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -40,8 +40,8 @@
CONFIG_SPL_BSS_START_ADDR=0x20000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x460000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x460000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_RAW_ONLY=y
CONFIG_SPL_NAND_DRIVERS=y
diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index 5cfd3d2..9f2cac7 100644
--- a/configs/smegw01_defconfig
+++ b/configs/smegw01_defconfig
@@ -48,7 +48,6 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
@@ -82,5 +81,8 @@
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
CONFIG_IMX_THERMAL=y
+CONFIG_IMX_WATCHDOG=y
# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig
index 02b9271..3e96daf 100644
--- a/configs/sniper_defconfig
+++ b/configs/sniper_defconfig
@@ -17,9 +17,9 @@
CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_BSS_START_ADDR=0x80000000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80208000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=2
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index 3c43000..32195cf 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -28,6 +28,7 @@
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTMETH_CROS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SILENT_CONSOLE=y
CONFIG_BLOBLIST=y
diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig
index 2377885..7d8b0cc 100644
--- a/configs/socfpga_agilex_atf_defconfig
+++ b/configs/socfpga_agilex_atf_defconfig
@@ -34,10 +34,10 @@
CONFIG_SPL_BSS_START_ADDR=0x3ff00000
CONFIG_SPL_BSS_MAX_SIZE=0x100000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x500000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig
index 8ec32ab..554b2f9 100644
--- a/configs/socfpga_agilex_defconfig
+++ b/configs/socfpga_agilex_defconfig
@@ -32,10 +32,10 @@
CONFIG_SPL_BSS_START_ADDR=0x3ff00000
CONFIG_SPL_BSS_MAX_SIZE=0x100000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x500000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000
diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig
index 0b09bd1..2309441 100644
--- a/configs/socfpga_agilex_vab_defconfig
+++ b/configs/socfpga_agilex_vab_defconfig
@@ -35,10 +35,10 @@
CONFIG_SPL_BSS_START_ADDR=0x3ff00000
CONFIG_SPL_BSS_MAX_SIZE=0x100000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x500000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index 82b1641..c35a360 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -14,8 +14,8 @@
CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
CONFIG_IDENT_STRING="socfpga_arria10"
CONFIG_SPL_FS_FAT=y
-CONFIG_FIT=y
CONFIG_TIMESTAMP=y
+CONFIG_FIT=y
CONFIG_SPL_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_BOOTARGS=y
@@ -30,10 +30,10 @@
CONFIG_SPL_PAD_TO=0x40000
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xffe2b000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x15000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xffe2b000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x15000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FPGA=y
CONFIG_SYS_MAXARGS=32
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 42d563a..8980a65 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -12,8 +12,8 @@
CONFIG_DM_RESET=y
CONFIG_SPL_STACK=0x0
CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
-CONFIG_FIT=y
CONFIG_TIMESTAMP=y
+CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DEFAULT_FDT_FILE="socfpga_arria5_socdk.dtb"
diff --git a/configs/socfpga_chameleonv3_defconfig b/configs/socfpga_chameleonv3_defconfig
index 441942c..457ad4b 100644
--- a/configs/socfpga_chameleonv3_defconfig
+++ b/configs/socfpga_chameleonv3_defconfig
@@ -14,10 +14,10 @@
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_NO_BSS_LIMIT=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xffe2b000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x15000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xffe2b000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x15000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_FPGA=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index fa7904b..0d744f4 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -12,8 +12,8 @@
CONFIG_DM_RESET=y
CONFIG_SPL_STACK=0x0
CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
-CONFIG_FIT=y
CONFIG_TIMESTAMP=y
+CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socdk.dtb"
diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig
index de087fa..2087b6e 100644
--- a/configs/socfpga_dbm_soc1_defconfig
+++ b/configs/socfpga_dbm_soc1_defconfig
@@ -12,8 +12,8 @@
CONFIG_DM_RESET=y
CONFIG_SPL_STACK=0x0
CONFIG_TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1=y
-CONFIG_FIT=y
CONFIG_TIMESTAMP=y
+CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_USE_BOOTCOMMAND=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index 364ae91..646552c 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -12,8 +12,8 @@
CONFIG_DM_RESET=y
CONFIG_SPL_STACK=0x0
CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
-CONFIG_FIT=y
CONFIG_TIMESTAMP=y
+CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de0_nano_soc.dtb"
diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig
index a79073f..3ae28e7 100644
--- a/configs/socfpga_de10_nano_defconfig
+++ b/configs/socfpga_de10_nano_defconfig
@@ -12,8 +12,8 @@
CONFIG_DM_RESET=y
CONFIG_SPL_STACK=0x0
CONFIG_TARGET_SOCFPGA_TERASIC_DE10_NANO=y
-CONFIG_FIT=y
CONFIG_TIMESTAMP=y
+CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de10_nano.dtb"
diff --git a/configs/socfpga_de10_standard_defconfig b/configs/socfpga_de10_standard_defconfig
index 1385b20..f3d86bc 100644
--- a/configs/socfpga_de10_standard_defconfig
+++ b/configs/socfpga_de10_standard_defconfig
@@ -12,8 +12,8 @@
CONFIG_DM_RESET=y
CONFIG_SPL_STACK=0x0
CONFIG_TARGET_SOCFPGA_TERASIC_DE10_STANDARD=y
-CONFIG_FIT=y
CONFIG_TIMESTAMP=y
+CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de10_standard.dtb"
diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig
index 069a253..cc3038e 100644
--- a/configs/socfpga_de1_soc_defconfig
+++ b/configs/socfpga_de1_soc_defconfig
@@ -12,8 +12,8 @@
CONFIG_DM_RESET=y
CONFIG_SPL_STACK=0x0
CONFIG_TARGET_SOCFPGA_TERASIC_DE1_SOC=y
-CONFIG_FIT=y
CONFIG_TIMESTAMP=y
+CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de1_soc.dtb"
diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
index 69eee1c..0551852 100644
--- a/configs/socfpga_is1_defconfig
+++ b/configs/socfpga_is1_defconfig
@@ -14,8 +14,8 @@
CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
CONFIG_SPL_STACK=0xfffffff8
CONFIG_TARGET_SOCFPGA_IS1=y
-CONFIG_FIT=y
CONFIG_TIMESTAMP=y
+CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index f49604b..23ea23d 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -12,8 +12,8 @@
CONFIG_DM_RESET=y
CONFIG_SPL_STACK=0x0
CONFIG_TARGET_SOCFPGA_ARIES_MCVEVK=y
-CONFIG_FIT=y
CONFIG_TIMESTAMP=y
+CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig
index 7af9e00..8868595 100644
--- a/configs/socfpga_n5x_atf_defconfig
+++ b/configs/socfpga_n5x_atf_defconfig
@@ -33,10 +33,10 @@
CONFIG_SPL_BSS_START_ADDR=0x3ff00000
CONFIG_SPL_BSS_MAX_SIZE=0x100000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x500000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig
index 2b1af2f..ee05c1b 100644
--- a/configs/socfpga_n5x_defconfig
+++ b/configs/socfpga_n5x_defconfig
@@ -29,10 +29,10 @@
CONFIG_SPL_BSS_START_ADDR=0x3ff00000
CONFIG_SPL_BSS_MAX_SIZE=0x100000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x500000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000
diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig
index c9bf337..0af212e 100644
--- a/configs/socfpga_n5x_vab_defconfig
+++ b/configs/socfpga_n5x_vab_defconfig
@@ -34,10 +34,10 @@
CONFIG_SPL_BSS_START_ADDR=0x3ff00000
CONFIG_SPL_BSS_MAX_SIZE=0x100000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x500000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig
index 157391a..b8052f1 100644
--- a/configs/socfpga_secu1_defconfig
+++ b/configs/socfpga_secu1_defconfig
@@ -73,7 +73,6 @@
CONFIG_BOOTFILE="zImage"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
-# CONFIG_SPL_BLK is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_DM_BOOTCOUNT_RTC=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index f3d7ecf..33b0c79 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -12,8 +12,8 @@
CONFIG_DM_RESET=y
CONFIG_SPL_STACK=0x0
CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
-CONFIG_FIT=y
CONFIG_TIMESTAMP=y
+CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sockit.dtb"
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index b07e0a3..dc88606 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -18,8 +18,8 @@
CONFIG_ENV_OFFSET_REDUND=0xF0000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x40000000
-CONFIG_FIT=y
CONFIG_TIMESTAMP=y
+CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sr1500.dtb"
diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig
index d1d2ec4..2806b06 100644
--- a/configs/socfpga_stratix10_atf_defconfig
+++ b/configs/socfpga_stratix10_atf_defconfig
@@ -34,10 +34,10 @@
CONFIG_SPL_BSS_START_ADDR=0x3ff00000
CONFIG_SPL_BSS_MAX_SIZE=0x100000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x500000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
CONFIG_SPL_ATF=y
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index 31d1868..c782c81 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -34,10 +34,10 @@
CONFIG_SPL_BSS_START_ADDR=0x3ff00000
CONFIG_SPL_BSS_MAX_SIZE=0x100000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x500000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C00000
CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex"
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index 62caec7..0b9c2a6 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -15,8 +15,8 @@
CONFIG_SPL_STACK=0x0
CONFIG_TARGET_SOCFPGA_SOFTING_VINING_FPGA=y
CONFIG_ENV_OFFSET_REDUND=0x110000
-CONFIG_FIT=y
CONFIG_TIMESTAMP=y
+CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig
index 33092c7..71c03d2 100644
--- a/configs/socrates_defconfig
+++ b/configs/socrates_defconfig
@@ -18,7 +18,6 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=1
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter password to abort autoboot in %d seconds!\n"
@@ -28,6 +27,7 @@
CONFIG_BOOT_RETRY=y
CONFIG_BOOT_RETRY_TIME=120
CONFIG_RESET_TO_RETRY=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run boot_usb;run boot_nor"
CONFIG_USE_PREBOOT=y
diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig
index 4a14913..c190235 100644
--- a/configs/som-db5800-som-6867_defconfig
+++ b/configs/som-db5800-som-6867_defconfig
@@ -27,7 +27,6 @@
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
@@ -48,7 +47,6 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
diff --git a/configs/soquartz-blade-rk3566_defconfig b/configs/soquartz-blade-rk3566_defconfig
index 181c284..1d993a5 100644
--- a/configs/soquartz-blade-rk3566_defconfig
+++ b/configs/soquartz-blade-rk3566_defconfig
@@ -67,6 +67,9 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
diff --git a/configs/soquartz-cm4-rk3566_defconfig b/configs/soquartz-cm4-rk3566_defconfig
index 7e29035..f01aa72 100644
--- a/configs/soquartz-cm4-rk3566_defconfig
+++ b/configs/soquartz-cm4-rk3566_defconfig
@@ -67,6 +67,9 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
diff --git a/configs/soquartz-model-a-rk3566_defconfig b/configs/soquartz-model-a-rk3566_defconfig
index c395857..2f31457 100644
--- a/configs/soquartz-model-a-rk3566_defconfig
+++ b/configs/soquartz-model-a-rk3566_defconfig
@@ -43,6 +43,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PMIC=y
@@ -67,6 +68,9 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index 62c7ae7..7b39a63 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -30,10 +30,11 @@
# CONFIG_OF_BOARD_FIXUP is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTSTAGE=y
CONFIG_QSPI_BOOT=y
CONFIG_SD_BOOT=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi"
CONFIG_USE_PREBOOT=y
@@ -49,10 +50,10 @@
CONFIG_SPL_BSS_START_ADDR=0x8040000
CONFIG_SPL_BSS_MAX_SIZE=0x10000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x400000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x400000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
CONFIG_SPL_I2C=y
@@ -71,7 +72,9 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_NOWHERE=y
@@ -118,6 +121,8 @@
CONFIG_SPL_PINCTRL_STARFIVE_JH7110=y
CONFIG_PINCTRL_STARFIVE=y
# CONFIG_RAM_SIFIVE is not set
+CONFIG_DM_RNG=y
+CONFIG_RNG_JH7110=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_TIMER_EARLY=y
@@ -129,3 +134,7 @@
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_PCI=y
CONFIG_USB_KEYBOARD=y
+# CONFIG_WATCHDOG is not set
+# CONFIG_WATCHDOG_AUTOSTART is not set
+CONFIG_WDT=y
+CONFIG_WDT_STARFIVE=y
diff --git a/configs/stm32746g-eval_spl_defconfig b/configs/stm32746g-eval_spl_defconfig
index 6f2f5ec..3864e21 100644
--- a/configs/stm32746g-eval_spl_defconfig
+++ b/configs/stm32746g-eval_spl_defconfig
@@ -36,7 +36,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_XIP_SUPPORT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x80c0000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x80c0000
CONFIG_SPL_DM_RESET=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_SYS_PBSIZE=1050
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index 1fb30d8..3c3a0d2 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -56,13 +56,13 @@
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_VIDEO=y
+CONFIG_VIDEO_LOGO=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_VIDEO_STM32=y
CONFIG_VIDEO_STM32_MAX_XRES=480
-CONFIG_VIDEO_STM32_MAX_YRES=640
+CONFIG_VIDEO_STM32_MAX_YRES=272
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
-CONFIG_VIDEO_BMP_RLE8=y
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y
diff --git a/configs/stm32f746-disco_spl_defconfig b/configs/stm32f746-disco_spl_defconfig
index 25ea254..b2a7861 100644
--- a/configs/stm32f746-disco_spl_defconfig
+++ b/configs/stm32f746-disco_spl_defconfig
@@ -36,7 +36,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_XIP_SUPPORT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x80c0000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x80c0000
CONFIG_SPL_DM_RESET=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_SYS_PBSIZE=1050
@@ -82,13 +82,13 @@
CONFIG_STM32_QSPI=y
CONFIG_SPL_TIMER=y
CONFIG_VIDEO=y
+CONFIG_VIDEO_LOGO=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_VIDEO_STM32=y
CONFIG_VIDEO_STM32_MAX_XRES=480
-CONFIG_VIDEO_STM32_MAX_YRES=640
+CONFIG_VIDEO_STM32_MAX_YRES=272
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
-CONFIG_VIDEO_BMP_RLE8=y
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y
diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig
index a92032d..3514a78 100644
--- a/configs/stm32f769-disco_defconfig
+++ b/configs/stm32f769-disco_defconfig
@@ -56,6 +56,7 @@
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_VIDEO=y
+CONFIG_VIDEO_LOGO=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
CONFIG_VIDEO_STM32=y
@@ -64,7 +65,6 @@
CONFIG_VIDEO_STM32_MAX_YRES=800
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
-CONFIG_VIDEO_BMP_RLE8=y
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y
diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig
index deb7963..3462203 100644
--- a/configs/stm32f769-disco_spl_defconfig
+++ b/configs/stm32f769-disco_spl_defconfig
@@ -35,7 +35,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_XIP_SUPPORT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x81c0000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x81c0000
CONFIG_SPL_DM_RESET=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_SYS_PBSIZE=1050
@@ -82,6 +82,7 @@
CONFIG_STM32_QSPI=y
CONFIG_SPL_TIMER=y
CONFIG_VIDEO=y
+CONFIG_VIDEO_LOGO=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
CONFIG_VIDEO_STM32=y
@@ -90,7 +91,6 @@
CONFIG_VIDEO_STM32_MAX_YRES=800
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
-CONFIG_VIDEO_BMP_RLE8=y
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y
diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig
index 4e83753..387dc6a 100644
--- a/configs/stm32mp13_defconfig
+++ b/configs/stm32mp13_defconfig
@@ -10,6 +10,7 @@
CONFIG_CMD_STM32KEY=y
CONFIG_TARGET_ST_STM32MP13x=y
CONFIG_ENV_OFFSET_REDUND=0x940000
+CONFIG_CMD_STM32PROG=y
# CONFIG_ARMV7_NONSEC is not set
CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_SYS_MEMTEST_START=0xc0000000
@@ -32,6 +33,8 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_LSBLK=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
@@ -49,6 +52,7 @@
CONFIG_SYS_MMC_ENV_DEV=-1
CONFIG_ENV_MMC_USE_DT=y
CONFIG_CLK_SCMI=y
+CONFIG_SET_DFU_ALT_INFO=y
CONFIG_GPIO_HOG=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_STM32F7=y
@@ -58,6 +62,8 @@
CONFIG_STM32_SDMMC2=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
+CONFIG_PHY=y
+CONFIG_PHY_STM32_USBPHYC=y
CONFIG_PINCONF=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
@@ -65,6 +71,7 @@
CONFIG_DM_REGULATOR_SCMI=y
CONFIG_RESET_SCMI=y
CONFIG_DM_RNG=y
+CONFIG_RNG_STM32=y
CONFIG_DM_RTC=y
CONFIG_RTC_STM32=y
CONFIG_SERIAL_RX_BUFFER=y
@@ -72,6 +79,20 @@
CONFIG_TEE=y
CONFIG_OPTEE=y
# CONFIG_OPTEE_TA_AVB is not set
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_ONBOARD_HUB=y
+CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0483
+CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_ERRNO_STR=y
# CONFIG_LMB_USE_MAX_REGIONS is not set
CONFIG_LMB_MEMORY_REGIONS=2
diff --git a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig
index defe07c..20e4cc3 100644
--- a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig
+++ b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig
@@ -21,10 +21,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x3db00
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xc0300000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1d00000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig
index d12a5ef..ad4355b 100644
--- a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig
+++ b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig
@@ -21,10 +21,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x3db00
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xc0300000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1d00000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig
index fc23a8c..1f2ec0c 100644
--- a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig
+++ b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig
@@ -21,10 +21,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x3db00
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xc0300000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1d00000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig
index a9996e3..8b33fd6 100644
--- a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig
+++ b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig
@@ -21,10 +21,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x3db00
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xc0300000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1d00000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index dc491cf..6df0935 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -25,16 +25,17 @@
CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
+CONFIG_FDT_SIMPLEFB=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SPL_LOG=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x3db00
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xc0300000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1d00000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
CONFIG_SPL_ENV_SUPPORT=y
@@ -44,7 +45,6 @@
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
-CONFIG_FDT_SIMPLEFB=y
CONFIG_SYS_PROMPT="STM32MP> "
CONFIG_SYS_PBSIZE=1050
CONFIG_SYS_BOOTM_LEN=0x2000000
@@ -150,7 +150,7 @@
CONFIG_DM_REGULATOR_STPMIC1=y
CONFIG_REMOTEPROC_STM32_COPRO=y
CONFIG_DM_RNG=y
-CONFIG_RNG_STM32MP1=y
+CONFIG_RNG_STM32=y
CONFIG_DM_RTC=y
CONFIG_RTC_STM32=y
CONFIG_SERIAL_RX_BUFFER=y
diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig
index 4f7dca4..261557b 100644
--- a/configs/stm32mp15_defconfig
+++ b/configs/stm32mp15_defconfig
@@ -19,8 +19,8 @@
CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
-CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_FDT_SIMPLEFB=y
+CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SYS_PROMPT="STM32MP> "
CONFIG_SYS_PBSIZE=1050
CONFIG_SYS_BOOTM_LEN=0x2000000
@@ -123,7 +123,7 @@
CONFIG_REMOTEPROC_STM32_COPRO=y
CONFIG_RESET_SCMI=y
CONFIG_DM_RNG=y
-CONFIG_RNG_STM32MP1=y
+CONFIG_RNG_STM32=y
CONFIG_DM_RTC=y
CONFIG_RTC_STM32=y
CONFIG_SERIAL_RX_BUFFER=y
diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig
index 630c175..1d24152 100644
--- a/configs/stm32mp15_dhcom_basic_defconfig
+++ b/configs/stm32mp15_dhcom_basic_defconfig
@@ -25,6 +25,8 @@
CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_SYS_MEMTEST_END=0xc4000000
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=1441792
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000
@@ -39,10 +41,10 @@
CONFIG_SPL_BOOTCOUNT_LIMIT=y
CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xc0300000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1d00000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
CONFIG_SPL_ENV_SUPPORT=y
@@ -76,7 +78,10 @@
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP6=y
+CONFIG_CMD_TFTPPUT=y
CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_WGET=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
@@ -101,6 +106,8 @@
CONFIG_TFTP_TSIZE=y
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.168.1.1"
+CONFIG_PROT_TCP_SACK=y
+CONFIG_IPV6=y
CONFIG_STM32_ADC=y
CONFIG_SPL_BLOCK_CACHE=y
CONFIG_BOOTCOUNT_LIMIT=y
diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig
index 26924a0..6e0c4a8 100644
--- a/configs/stm32mp15_dhcor_basic_defconfig
+++ b/configs/stm32mp15_dhcor_basic_defconfig
@@ -23,6 +23,8 @@
CONFIG_SPL_SPI=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_SYS_LOAD_ADDR=0xc2000000
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=1441792
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000
@@ -37,10 +39,10 @@
CONFIG_SPL_BOOTCOUNT_LIMIT=y
CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xc0300000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1d00000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
CONFIG_SPL_ENV_SUPPORT=y
@@ -74,7 +76,10 @@
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP6=y
+CONFIG_CMD_TFTPPUT=y
CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_WGET=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
@@ -99,6 +104,8 @@
CONFIG_TFTP_TSIZE=y
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.168.1.1"
+CONFIG_PROT_TCP_SACK=y
+CONFIG_IPV6=y
CONFIG_STM32_ADC=y
CONFIG_SPL_BLOCK_CACHE=y
CONFIG_BOOTCOUNT_LIMIT=y
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index 6f4876f..5a031e7 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -20,8 +20,8 @@
CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
-CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_FDT_SIMPLEFB=y
+CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SYS_PROMPT="STM32MP> "
CONFIG_SYS_PBSIZE=1050
CONFIG_SYS_BOOTM_LEN=0x2000000
@@ -123,7 +123,7 @@
CONFIG_REMOTEPROC_STM32_COPRO=y
CONFIG_RESET_SCMI=y
CONFIG_DM_RNG=y
-CONFIG_RNG_STM32MP1=y
+CONFIG_RNG_STM32=y
CONFIG_DM_RTC=y
CONFIG_RTC_STM32=y
CONFIG_SERIAL_RX_BUFFER=y
diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig
index ec17c55..f0faeda 100644
--- a/configs/stmark2_defconfig
+++ b/configs/stmark2_defconfig
@@ -10,8 +10,8 @@
CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_TARGET_STMARK2=y
CONFIG_SYS_BARGSIZE=256
-CONFIG_TIMESTAMP=y
CONFIG_SYS_MONITOR_BASE=0x47E00400
+CONFIG_TIMESTAMP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 rw rootfstype=ramfs rdinit=/bin/init devtmpfs.mount=1"
CONFIG_USE_BOOTCOMMAND=y
diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
index bf23454..78cbaa7 100644
--- a/configs/syzygy_hub_defconfig
+++ b/configs/syzygy_hub_defconfig
@@ -28,11 +28,11 @@
CONFIG_SPL_BSS_MAX_SIZE=0x100000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x2000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000
CONFIG_SPL_FS_LOAD_ARGS_NAME="system.dtb"
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x10000000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x10000000
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=2071
CONFIG_SYS_BOOTM_LEN=0x3c00000
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index f2c148e..cc57551 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -48,10 +48,10 @@
# CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x20ba0000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x460000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x20ba0000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x460000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_RAW_ONLY=y
CONFIG_SPL_NAND_DRIVERS=y
diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig
index 48ab49b..fdda5e4 100644
--- a/configs/tec-ng_defconfig
+++ b/configs/tec-ng_defconfig
@@ -20,10 +20,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra30 (TEC-NG) # "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2084
diff --git a/configs/tec_defconfig b/configs/tec_defconfig
index bcdd7c1..cc2256b 100644
--- a/configs/tec_defconfig
+++ b/configs/tec_defconfig
@@ -18,10 +18,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x90000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra20 (TEC) # "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2081
diff --git a/configs/ten64_tfa_defconfig b/configs/ten64_tfa_defconfig
index 24282a6..2ac5758 100644
--- a/configs/ten64_tfa_defconfig
+++ b/configs/ten64_tfa_defconfig
@@ -20,9 +20,9 @@
CONFIG_BOOTSTD_FULL=y
CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_BOOTSTD_BOOTCOMMAND=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_LOGLEVEL=7
diff --git a/configs/teres_i_defconfig b/configs/teres_i_defconfig
index e7de85e..b9b22e7 100644
--- a/configs/teres_i_defconfig
+++ b/configs/teres_i_defconfig
@@ -11,7 +11,6 @@
CONFIG_PREBOOT="setenv usb_pgood_delay 2000; usb start"
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
-CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_PWM=y
CONFIG_PWM_SUNXI=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
index 69499e1..5dc9904 100644
--- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
+++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
@@ -26,7 +26,6 @@
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
@@ -49,7 +48,6 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_ISO_PARTITION=y
CONFIG_AMIGA_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig
index e2e64b7..d7b6264 100644
--- a/configs/theadorable-x86-conga-qa3-e3845_defconfig
+++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig
@@ -25,7 +25,6 @@
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
@@ -48,7 +47,6 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig
index 751ae34..861b59f 100644
--- a/configs/theadorable-x86-dfi-bt700_defconfig
+++ b/configs/theadorable-x86-dfi-bt700_defconfig
@@ -24,7 +24,6 @@
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
@@ -46,7 +45,6 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index 8d79e41..116700e 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -37,9 +37,9 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_BSS_START_ADDR=0x80000000
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80208000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000
CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig
index 3f588ea..fa1ff4a 100644
--- a/configs/tools-only_defconfig
+++ b/configs/tools-only_defconfig
@@ -6,8 +6,8 @@
CONFIG_PCI=y
# CONFIG_SANDBOX_SDL is not set
CONFIG_ANDROID_BOOT_IMAGE=y
-CONFIG_FIT=y
CONFIG_TIMESTAMP=y
+CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
# CONFIG_BOOTSTD_FULL is not set
# CONFIG_BOOTMETH_CROS is not set
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index f60b812..8ba29d7 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -32,8 +32,8 @@
CONFIG_SPL_BSS_MAX_SIZE=0x100000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x2000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SYS_PROMPT="zynq-uboot> "
@@ -78,5 +78,4 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_FUNCTION_THOR=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y
diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig
index 5533210..8d37d05 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -32,8 +32,8 @@
CONFIG_SPL_BSS_MAX_SIZE=0x100000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x2000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SYS_PROMPT="zynq-uboot> "
@@ -78,5 +78,4 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_FUNCTION_THOR=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y
diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig
index b9e3fe7..fd89c25 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -32,8 +32,8 @@
CONFIG_SPL_BSS_MAX_SIZE=0x100000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x2000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SYS_PROMPT="zynq-uboot> "
@@ -78,5 +78,4 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_FUNCTION_THOR=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y
diff --git a/configs/tqma6dl_mba6_mmc_defconfig b/configs/tqma6dl_mba6_mmc_defconfig
index e439214..ce30194 100644
--- a/configs/tqma6dl_mba6_mmc_defconfig
+++ b/configs/tqma6dl_mba6_mmc_defconfig
@@ -11,8 +11,8 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run mmcboot; run netboot; run panicboot"
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
diff --git a/configs/tqma6dl_mba6_spi_defconfig b/configs/tqma6dl_mba6_spi_defconfig
index c4509c6..919cec1 100644
--- a/configs/tqma6dl_mba6_spi_defconfig
+++ b/configs/tqma6dl_mba6_spi_defconfig
@@ -14,8 +14,8 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe; run mmcboot; run netboot; run panicboot"
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig
index 64f7160..2910b85 100644
--- a/configs/tqma6q_mba6_mmc_defconfig
+++ b/configs/tqma6q_mba6_mmc_defconfig
@@ -11,8 +11,8 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run mmcboot; run netboot; run panicboot"
CONFIG_DEFAULT_FDT_FILE="imx6q-mba6x.dtb"
diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig
index 8256f53..556e6d6 100644
--- a/configs/tqma6q_mba6_spi_defconfig
+++ b/configs/tqma6q_mba6_spi_defconfig
@@ -14,8 +14,8 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe; run mmcboot; run netboot; run panicboot"
CONFIG_DEFAULT_FDT_FILE="imx6q-mba6x.dtb"
diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig
index cdf0add..853b083 100644
--- a/configs/tqma6s_mba6_mmc_defconfig
+++ b/configs/tqma6s_mba6_mmc_defconfig
@@ -11,8 +11,8 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run mmcboot; run netboot; run panicboot"
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig
index 06fe342..7316056 100644
--- a/configs/tqma6s_mba6_spi_defconfig
+++ b/configs/tqma6s_mba6_spi_defconfig
@@ -14,8 +14,8 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe; run mmcboot; run netboot; run panicboot"
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
diff --git a/configs/transformer_t30_defconfig b/configs/transformer_t30_defconfig
index b7934fd..092c0aa 100644
--- a/configs/transformer_t30_defconfig
+++ b/configs/transformer_t30_defconfig
@@ -15,19 +15,19 @@
CONFIG_TARGET_TRANSFORMER_T30=y
CONFIG_CMD_EBTUPDATE=y
CONFIG_SYS_LOAD_ADDR=0x82000000
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=0
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_KEYED_CTRLC=y
-CONFIG_BOOTCOMMAND="setenv gpio_button 150; if run check_button; then poweroff; fi; setenv gpio_button 131; if run check_button; then bootmenu; fi; run bootcmd_mmc1; run bootcmd_mmc0; poweroff;"
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="setenv skip_boot 0; setenv gpio_button 150; if run check_button; then poweroff; fi; setenv gpio_button 131; if run check_button; then bootmenu; fi; if test ${skip_boot} -eq 1; then; else run bootcmd_usb0; run bootcmd_mmc1; run bootcmd_mmc0; poweroff; fi"
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra30 (Transformer) # "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2084
diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig
index eb8800b..6c4909f 100644
--- a/configs/trats2_defconfig
+++ b/configs/trats2_defconfig
@@ -65,5 +65,4 @@
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DWC2_OTG_PHY=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_FUNCTION_THOR=y
CONFIG_LIB_HW_RAND=y
diff --git a/configs/trats_defconfig b/configs/trats_defconfig
index a747654..78484c0 100644
--- a/configs/trats_defconfig
+++ b/configs/trats_defconfig
@@ -62,5 +62,4 @@
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DWC2_OTG_PHY=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_FUNCTION_THOR=y
CONFIG_LIB_HW_RAND=y
diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig
index f554df1..b84a78b 100644
--- a/configs/trimslice_defconfig
+++ b/configs/trimslice_defconfig
@@ -20,10 +20,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x90000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra20 (TrimSlice) # "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2087
diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig
index 7ea2f17..9ff5d15 100644
--- a/configs/tuge1_defconfig
+++ b/configs/tuge1_defconfig
@@ -96,11 +96,11 @@
CONFIG_LCRR_CLKDIV_2=y
CONFIG_83XX_PCICLK=0x3ef1480
# CONFIG_PCI is not set
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_HWCONFIG is not set
CONFIG_LAST_STAGE_INIT=y
diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig
index 234f1e7..c9815b6 100644
--- a/configs/turris_mox_defconfig
+++ b/configs/turris_mox_defconfig
@@ -21,14 +21,13 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_LAST_STAGE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=32
CONFIG_CMD_SHA1SUM=y
@@ -53,9 +52,10 @@
CONFIG_CMD_BTRFS=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MAC_PARTITION=y
+CONFIG_OF_LIST="armada-3720-turris-mox armada-3720-ripe-atlas"
CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=2
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
CONFIG_NETCONSOLE=y
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index 22aaee2..65d4a29 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -35,9 +35,9 @@
CONFIG_BOARD_SIZE_LIMIT=983040
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig
index 4195c0b..5b33e8f 100644
--- a/configs/tuxx1_defconfig
+++ b/configs/tuxx1_defconfig
@@ -110,11 +110,11 @@
CONFIG_LCRR_CLKDIV_2=y
CONFIG_83XX_PCICLK=0x3ef1480
# CONFIG_PCI is not set
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_HWCONFIG is not set
CONFIG_LAST_STAGE_INIT=y
diff --git a/configs/u200_defconfig b/configs/u200_defconfig
index a841a66..21c90e7 100644
--- a/configs/u200_defconfig
+++ b/configs/u200_defconfig
@@ -16,12 +16,17 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=32
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -31,6 +36,7 @@
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig
index 988f9ed..d3f1466 100644
--- a/configs/uDPU_defconfig
+++ b/configs/uDPU_defconfig
@@ -81,6 +81,7 @@
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
# CONFIG_SCSI is not set
+CONFIG_DEFAULT_ENV_IS_RW=y
CONFIG_MVEBU_A3700_UART=y
CONFIG_MVEBU_A3700_SPI=y
CONFIG_SYSINFO=y
diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig
index ab8cb48..e128a62 100644
--- a/configs/udoo_defconfig
+++ b/configs/udoo_defconfig
@@ -23,7 +23,7 @@
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
CONFIG_SPL_I2C=y
diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig
index e06de7b..853472f 100644
--- a/configs/udoo_neo_defconfig
+++ b/configs/udoo_neo_defconfig
@@ -21,7 +21,7 @@
# CONFIG_CMD_BMODE is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig
index bf70771..a716c05 100644
--- a/configs/uniphier_ld4_sld8_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -15,6 +15,7 @@
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_LOAD_ADDR=0x85000000
CONFIG_TIMESTAMP=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
CONFIG_USE_PREBOOT=y
@@ -81,4 +82,3 @@
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_PANIC_HANG=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig
index 05f1c99..1e030fc 100644
--- a/configs/uniphier_v7_defconfig
+++ b/configs/uniphier_v7_defconfig
@@ -15,6 +15,7 @@
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_LOAD_ADDR=0x85000000
CONFIG_TIMESTAMP=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
CONFIG_USE_PREBOOT=y
@@ -87,4 +88,3 @@
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_UNIPHIER=y
CONFIG_PANIC_HANG=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig
index 9124662..674b781 100644
--- a/configs/uniphier_v8_defconfig
+++ b/configs/uniphier_v8_defconfig
@@ -11,6 +11,7 @@
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_LOAD_ADDR=0x85000000
CONFIG_TIMESTAMP=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
CONFIG_USE_PREBOOT=y
@@ -76,4 +77,3 @@
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_UNIPHIER=y
CONFIG_PANIC_HANG=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig
index 66c969f..b717fc8 100644
--- a/configs/usbarmory_defconfig
+++ b/configs/usbarmory_defconfig
@@ -6,8 +6,6 @@
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x60000
CONFIG_TARGET_USBARMORY=y
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx53-usbarmory"
# CONFIG_CMD_BMODE is not set
@@ -29,7 +27,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_HOSTNAME=y
CONFIG_HOSTNAME="usbarmory"
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_IIM=y
CONFIG_FSL_ESDHC_IMX=y
@@ -39,6 +37,7 @@
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_USB_EHCI_MX5=y
diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig
index 1cfa342..1cf4a8f 100644
--- a/configs/variscite_dart6ul_defconfig
+++ b/configs/variscite_dart6ul_defconfig
@@ -19,7 +19,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run mmc_mmc_fit"
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index bd8ca4d..f01bd7a 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -20,10 +20,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra124 (Venice2) # "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2086
diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig
index ef1c6f3..6f40400 100644
--- a/configs/ventana_defconfig
+++ b/configs/ventana_defconfig
@@ -17,10 +17,10 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x90000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra20 (Ventana) # "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2085
diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig
index fb209b4..7808601 100644
--- a/configs/verdin-am62_a53_defconfig
+++ b/configs/verdin-am62_a53_defconfig
@@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
@@ -36,9 +35,9 @@
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile k3-am625-verdin-${variant}-${fdt_board}.dtb"
CONFIG_LOG=y
diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig
index 878195a..a3febdc 100644
--- a/configs/verdin-am62_r5_defconfig
+++ b/configs/verdin-am62_r5_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x08000000
CONFIG_SYS_MALLOC_F_LEN=0x9000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -38,10 +37,10 @@
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x140000
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig
index 54ea3fb..7644471 100644
--- a/configs/verdin-imx8mm_defconfig
+++ b/configs/verdin-imx8mm_defconfig
@@ -27,9 +27,9 @@
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx8mm-verdin-${variant}-${fdt_board}.dtb"
CONFIG_LOG=y
@@ -42,10 +42,10 @@
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
@@ -69,6 +69,8 @@
CONFIG_CMD_MMC=y
CONFIG_CMD_READ=y
CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
@@ -97,6 +99,12 @@
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MM=y
CONFIG_CLK_IMX8MM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_GPIO_HOG=y
CONFIG_SPL_GPIO_HOG=y
CONFIG_MXC_GPIO=y
@@ -120,6 +128,8 @@
CONFIG_DM_MDIO=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
+CONFIG_SPL_PHY=y
+CONFIG_SPL_NOP_PHY=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
@@ -139,8 +149,18 @@
CONFIG_DM_THERMAL=y
CONFIG_IMX_TMU=y
CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Toradex"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
+CONFIG_CI_UDC=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_IMX_WATCHDOG=y
CONFIG_HEXDUMP=y
diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig
index 6919117..eec1d96 100644
--- a/configs/verdin-imx8mp_defconfig
+++ b/configs/verdin-imx8mp_defconfig
@@ -33,9 +33,9 @@
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx8mp-verdin-${variant}-${fdt_board}.dtb"
CONFIG_LOG=y
@@ -52,10 +52,10 @@
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
@@ -79,6 +79,7 @@
CONFIG_CMD_MMC=y
CONFIG_CMD_READ=y
CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
@@ -108,6 +109,12 @@
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_CLK_IMX8MP=y
CONFIG_FSL_CAAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_GPIO_HOG=y
CONFIG_SPL_GPIO_HOG=y
CONFIG_MXC_GPIO=y
@@ -138,6 +145,7 @@
CONFIG_FEC_MXC=y
CONFIG_RGMII=y
CONFIG_MII=y
+CONFIG_PHY=y
CONFIG_PHY_IMX8MQ_USB=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
@@ -160,14 +168,20 @@
CONFIG_DM_THERMAL=y
CONFIG_IMX_TMU=y
CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
CONFIG_USB_EHCI_HCD=y
-CONFIG_MXC_USB_OTG_HACTIVE=y
+# CONFIG_USB_EHCI_MX7 is not set
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Toradex"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
CONFIG_IMX_WATCHDOG=y
CONFIG_HEXDUMP=y
diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig
index 5cacecc..195b8ad 100644
--- a/configs/vexpress_ca9x4_defconfig
+++ b/configs/vexpress_ca9x4_defconfig
@@ -42,6 +42,7 @@
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
+CONFIG_SYS_FLASH_CFI_WIDTH_32BIT=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_CFI_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/videostrong-kii-pro_defconfig b/configs/videostrong-kii-pro_defconfig
index 4a2ff34..3eda8f1 100644
--- a/configs/videostrong-kii-pro_defconfig
+++ b/configs/videostrong-kii-pro_defconfig
@@ -14,6 +14,10 @@
CONFIG_IDENT_STRING=" kii-pro"
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
index cbb8259..e5d3495 100644
--- a/configs/vining_2000_defconfig
+++ b/configs/vining_2000_defconfig
@@ -33,7 +33,7 @@
CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
CONFIG_SPL_I2C=y
diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig
index 9bca6fe..0ae901a 100644
--- a/configs/vyasa-rk3288_defconfig
+++ b/configs/vyasa-rk3288_defconfig
@@ -32,7 +32,7 @@
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0xffe5000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0xffe5000
CONFIG_SPL_FALCON_BOOT_MMCSD=y
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x8800
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x8000
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index 0493ef2..7c1727f 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -33,7 +33,7 @@
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
diff --git a/configs/wetek-core2_defconfig b/configs/wetek-core2_defconfig
index 324062e..9bf3de9 100644
--- a/configs/wetek-core2_defconfig
+++ b/configs/wetek-core2_defconfig
@@ -16,6 +16,10 @@
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
@@ -23,6 +27,7 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_ADC=y
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
@@ -33,6 +38,7 @@
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SARADC_MESON=y
+CONFIG_DFU_RAM=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/wetek-hub_defconfig b/configs/wetek-hub_defconfig
index 4091a19..fd92b04 100644
--- a/configs/wetek-hub_defconfig
+++ b/configs/wetek-hub_defconfig
@@ -14,6 +14,10 @@
CONFIG_IDENT_STRING=" wetek-hub"
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
diff --git a/configs/wetek-play2_defconfig b/configs/wetek-play2_defconfig
index 3ef4390..b887419 100644
--- a/configs/wetek-play2_defconfig
+++ b/configs/wetek-play2_defconfig
@@ -14,6 +14,10 @@
CONFIG_IDENT_STRING=" wetek-play2"
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
diff --git a/configs/x240_defconfig b/configs/x240_defconfig
index 7d2b860..4b1a761 100644
--- a/configs/x240_defconfig
+++ b/configs/x240_defconfig
@@ -42,7 +42,6 @@
CONFIG_GPIO_HOG=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
-CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
@@ -84,3 +83,4 @@
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
# CONFIG_FAT_WRITE is not set
+# CONFIG_SMBIOS is not set
diff --git a/configs/x3_t30_defconfig b/configs/x3_t30_defconfig
index ea7aecc..a151f58 100644
--- a/configs/x3_t30_defconfig
+++ b/configs/x3_t30_defconfig
@@ -16,19 +16,19 @@
CONFIG_TEGRA_ENABLE_UARTD=y
CONFIG_CMD_EBTUPDATE=y
CONFIG_SYS_LOAD_ADDR=0x82000000
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=0
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="if run check_button; then bootmenu; fi; run bootcmd_mmc1; run bootcmd_mmc0; poweroff;"
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra30 (x3) # "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2084
diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig
index 318951e..42a3b8c 100644
--- a/configs/x96_mate_defconfig
+++ b/configs/x96_mate_defconfig
@@ -19,5 +19,6 @@
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_AXP305_POWER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/xenguest_arm64_defconfig b/configs/xenguest_arm64_defconfig
index b206f71..aab1e7f 100644
--- a/configs/xenguest_arm64_defconfig
+++ b/configs/xenguest_arm64_defconfig
@@ -8,8 +8,8 @@
CONFIG_DEFAULT_DEVICE_TREE="xenguest-arm64"
CONFIG_IDENT_STRING=" xenguest"
CONFIG_SYS_LOAD_ADDR=0x40000000
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=10
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_PROMPT="xenguest# "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=1051
diff --git a/configs/xenguest_arm64_virtio_defconfig b/configs/xenguest_arm64_virtio_defconfig
new file mode 100644
index 0000000..d76b2c1
--- /dev/null
+++ b/configs/xenguest_arm64_virtio_defconfig
@@ -0,0 +1,56 @@
+CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_TARGET_XENGUEST_ARM64=y
+CONFIG_TEXT_BASE=0x40080000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x400
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="xenguest-arm64"
+CONFIG_IDENT_STRING=" xenguest"
+CONFIG_SYS_LOAD_ADDR=0x40000000
+CONFIG_SYS_PCI_64BIT=y
+CONFIG_PCI=y
+CONFIG_BOOTDELAY=10
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_PCI_INIT_R=y
+CONFIG_SYS_PROMPT="xenguest# "
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_PBSIZE=1051
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_BOOTD is not set
+CONFIG_SYS_BOOTM_LEN=0x800000
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_PCI=y
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_SLEEP is not set
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_PARTITION_TYPE_GUID=y
+# CONFIG_NET is not set
+# CONFIG_MMC is not set
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
+CONFIG_PCIE_ECAM_GENERIC=y
+# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_DM_SERIAL=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_PCI=y
+# CONFIG_VIRTIO_PCI_LEGACY is not set
+CONFIG_VIRTIO_BLK=y
diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig
index fdb77b1..222da5a 100644
--- a/configs/xilinx_versal_mini_defconfig
+++ b/configs/xilinx_versal_mini_defconfig
@@ -20,8 +20,6 @@
CONFIG_REMAKE_ELF=y
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_AUTOBOOT is not set
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
@@ -61,7 +59,6 @@
# CONFIG_CMD_SLEEP is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_MMC is not set
CONFIG_ARM_DCC=y
diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig
index ed1d3a5..1d73790 100644
--- a/configs/xilinx_versal_mini_emmc0_defconfig
+++ b/configs/xilinx_versal_mini_emmc0_defconfig
@@ -16,8 +16,6 @@
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
# CONFIG_AUTOBOOT is not set
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
@@ -59,7 +57,6 @@
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig
index bdfa8dc..747f20d 100644
--- a/configs/xilinx_versal_mini_emmc1_defconfig
+++ b/configs/xilinx_versal_mini_emmc1_defconfig
@@ -16,8 +16,6 @@
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
# CONFIG_AUTOBOOT is not set
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
@@ -59,7 +57,6 @@
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig
index 389ca50..96be5b9 100644
--- a/configs/xilinx_versal_mini_ospi_defconfig
+++ b/configs/xilinx_versal_mini_ospi_defconfig
@@ -51,12 +51,12 @@
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+# CONFIG_SPI_FLASH_LOCK is not set
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig
index 39bd267..7181b89 100644
--- a/configs/xilinx_versal_mini_qspi_defconfig
+++ b/configs/xilinx_versal_mini_qspi_defconfig
@@ -16,8 +16,8 @@
CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
# CONFIG_AUTOBOOT is not set
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_LOGLEVEL=0
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
@@ -53,7 +53,6 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG is not set
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_GPIO is not set
# CONFIG_I2C is not set
@@ -61,6 +60,7 @@
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
+# CONFIG_SPI_FLASH_LOCK is not set
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
diff --git a/configs/xilinx_versal_net_mini_defconfig b/configs/xilinx_versal_net_mini_defconfig
index c33d482..7dac1ec 100644
--- a/configs/xilinx_versal_net_mini_defconfig
+++ b/configs/xilinx_versal_net_mini_defconfig
@@ -21,8 +21,8 @@
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
# CONFIG_LEGACY_IMAGE_FORMAT is not set
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
# CONFIG_AUTOBOOT is not set
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
@@ -62,7 +62,6 @@
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_GPIO is not set
# CONFIG_I2C is not set
diff --git a/configs/xilinx_versal_net_mini_emmc_defconfig b/configs/xilinx_versal_net_mini_emmc_defconfig
index 1d79eff..fc88eee 100644
--- a/configs/xilinx_versal_net_mini_emmc_defconfig
+++ b/configs/xilinx_versal_net_mini_emmc_defconfig
@@ -51,7 +51,6 @@
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/xilinx_versal_net_mini_ospi_defconfig b/configs/xilinx_versal_net_mini_ospi_defconfig
index 0656b23..1ba6e08 100644
--- a/configs/xilinx_versal_net_mini_ospi_defconfig
+++ b/configs/xilinx_versal_net_mini_ospi_defconfig
@@ -50,12 +50,12 @@
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+# CONFIG_SPI_FLASH_LOCK is not set
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig
index b8736a5..c9497bb 100644
--- a/configs/xilinx_versal_net_mini_qspi_defconfig
+++ b/configs/xilinx_versal_net_mini_qspi_defconfig
@@ -15,8 +15,8 @@
CONFIG_SYS_LOAD_ADDR=0xBBF80000
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
# CONFIG_AUTOBOOT is not set
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_LOGLEVEL=0
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
@@ -52,7 +52,6 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG is not set
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_GPIO is not set
# CONFIG_I2C is not set
@@ -60,6 +59,7 @@
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
+# CONFIG_SPI_FLASH_LOCK is not set
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig
index 77137db..0553ac6 100644
--- a/configs/xilinx_versal_net_virt_defconfig
+++ b/configs/xilinx_versal_net_virt_defconfig
@@ -15,9 +15,9 @@
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=5
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
@@ -32,6 +32,7 @@
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_SHA1SUM=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_DM=y
@@ -49,8 +50,10 @@
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_CMD_RNG=y
+CONFIG_CMD_KASLRSEED=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_SMC=y
+CONFIG_CMD_TPM=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SQUASHFS=y
CONFIG_CMD_MTDPARTS=y
@@ -77,12 +80,12 @@
CONFIG_ZYNQMP_IPI=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000
CONFIG_MTD=y
@@ -110,7 +113,6 @@
CONFIG_POWER_DOMAIN=y
CONFIG_ZYNQMP_POWER_DOMAIN=y
CONFIG_RESET_ZYNQMP=y
-CONFIG_DM_RNG=y
CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
CONFIG_XILINX_UARTLITE=y
@@ -122,6 +124,7 @@
CONFIG_CADENCE_OSPI_VERSAL=y
CONFIG_ZYNQ_SPI=y
CONFIG_ZYNQMP_GQSPI=y
+CONFIG_TPM2_TIS_SPI=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
@@ -139,3 +142,4 @@
CONFIG_VIRTIO_MMIO=y
CONFIG_VIRTIO_NET=y
CONFIG_VIRTIO_BLK=y
+CONFIG_TPM=y
diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig
index b13bead..6a2c03c 100644
--- a/configs/xilinx_versal_virt_defconfig
+++ b/configs/xilinx_versal_virt_defconfig
@@ -5,6 +5,8 @@
CONFIG_ARCH_VERSAL=y
CONFIG_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x100000
+CONFIG_NR_DRAM_BANKS=36
+CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_DEFAULT_DEVICE_TREE="xilinx-versal-virt"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
@@ -17,9 +19,9 @@
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=5
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_PREBOOT=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CLOCKS=y
@@ -32,6 +34,7 @@
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_SHA1SUM=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_DM=y
@@ -49,8 +52,10 @@
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_CMD_RNG=y
+CONFIG_CMD_KASLRSEED=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_SMC=y
+CONFIG_CMD_TPM=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SQUASHFS=y
CONFIG_CMD_MTDPARTS=y
@@ -114,7 +119,6 @@
CONFIG_POWER_DOMAIN=y
CONFIG_ZYNQMP_POWER_DOMAIN=y
CONFIG_RESET_ZYNQMP=y
-CONFIG_DM_RNG=y
CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
CONFIG_XILINX_UARTLITE=y
@@ -127,6 +131,7 @@
CONFIG_CADENCE_OSPI_VERSAL=y
CONFIG_ZYNQ_SPI=y
CONFIG_ZYNQMP_GQSPI=y
+CONFIG_TPM2_TIS_SPI=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
@@ -144,3 +149,4 @@
CONFIG_VIRTIO_MMIO=y
CONFIG_VIRTIO_NET=y
CONFIG_VIRTIO_BLK=y
+CONFIG_TPM=y
diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig
index 9900577..c3ee9be 100644
--- a/configs/xilinx_zynq_virt_defconfig
+++ b/configs/xilinx_zynq_virt_defconfig
@@ -27,8 +27,8 @@
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
CONFIG_LEGACY_IMAGE_FORMAT=y
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_PREBOOT=y
CONFIG_CLOCKS=y
CONFIG_SPL_MAX_SIZE=0x30000
@@ -37,13 +37,13 @@
CONFIG_SPL_BSS_MAX_SIZE=0x100000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x2000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_FS_LOAD_ARGS_NAME="system.dtb"
CONFIG_SPL_FPGA=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x10000000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x10000000
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SYS_MAXARGS=32
@@ -126,6 +126,8 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
@@ -148,7 +150,6 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_FUNCTION_THOR=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y
CONFIG_SPL_GZIP=y
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig
index fc768b6..694fa11 100644
--- a/configs/xilinx_zynqmp_mini_defconfig
+++ b/configs/xilinx_zynqmp_mini_defconfig
@@ -55,7 +55,6 @@
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_DM_MAILBOX is not set
# CONFIG_MMC is not set
diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig
index cf7c7ed..f81b772 100644
--- a/configs/xilinx_zynqmp_mini_emmc0_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig
@@ -26,10 +26,10 @@
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x20000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x20000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_MAXARGS=64
@@ -66,7 +66,6 @@
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_DM_MAILBOX is not set
diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig
index a4a43b5..6501ec3 100644
--- a/configs/xilinx_zynqmp_mini_emmc1_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig
@@ -26,10 +26,10 @@
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x20000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x20000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_MAXARGS=64
@@ -66,7 +66,6 @@
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_DM_MAILBOX is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig
index ce224f8..bfe93dc 100644
--- a/configs/xilinx_zynqmp_mini_nand_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_defconfig
@@ -51,7 +51,6 @@
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_DM_MAILBOX is not set
# CONFIG_MMC is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig
index ce23cb1..91f5aa2 100644
--- a/configs/xilinx_zynqmp_mini_nand_single_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig
@@ -51,7 +51,6 @@
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_DM_MAILBOX is not set
# CONFIG_MMC is not set
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index e6a9dd3..a6f36fe 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -18,8 +18,8 @@
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
# CONFIG_LEGACY_IMAGE_FORMAT is not set
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
# CONFIG_AUTOBOOT is not set
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_LOGLEVEL=0
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_BOARD_LATE_INIT is not set
@@ -27,10 +27,10 @@
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x20000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x20000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
@@ -67,7 +67,6 @@
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_FIRMWARE is not set
@@ -77,6 +76,7 @@
# CONFIG_DM_MAILBOX is not set
# CONFIG_MMC is not set
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
+# CONFIG_SPI_FLASH_LOCK is not set
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index acab38f..239bb1f 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -11,13 +11,11 @@
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_SPL_STACK=0xfffffffc
CONFIG_SPL_SIZE_LIMIT=0x2a000
-CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x1E80000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_CMD_FRU=y
-CONFIG_ZYNQMP_USB=y
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x00000000
@@ -27,8 +25,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run scsi_init;usb start"
CONFIG_BOARD_EARLY_INIT_R=y
@@ -37,15 +35,15 @@
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x20000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x20000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_FS_LOAD_KERNEL_NAME="atf-uboot.ub"
CONFIG_SPL_FS_LOAD_ARGS_NAME="u-boot.bin"
CONFIG_SPL_FPGA=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x8000000
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x8000000
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_SPI_LOAD=y
@@ -91,6 +89,7 @@
CONFIG_CMD_TIME=y
CONFIG_CMD_GETTIME=y
CONFIG_CMD_RNG=y
+CONFIG_CMD_KASLRSEED=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_SMC=y
@@ -104,7 +103,7 @@
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_BOARD=y
-CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu106-rev1.0 zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-sm-k26-revA zynqmp-smk-k26-revA zynqmp-dlc21-revA"
+CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-e-a2197-00-revB zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu106-rev1.0 zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-sm-k26-revA zynqmp-smk-k26-revA zynqmp-dlc21-revA"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent interrupts iommus power-domains"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_FAT=y
@@ -220,7 +219,6 @@
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
-CONFIG_USB_FUNCTION_THOR=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
CONFIG_VIDEO=y
diff --git a/configs/xtfpga_defconfig b/configs/xtfpga_defconfig
index cbe7cdb..fc5b666 100644
--- a/configs/xtfpga_defconfig
+++ b/configs/xtfpga_defconfig
@@ -32,7 +32,6 @@
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_VERSION_VARIABLE=y
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_DM_STDIO is not set
# CONFIG_DM_SEQ_ALIAS is not set
diff --git a/configs/zeropi_defconfig b/configs/zeropi_defconfig
index 11f3715..7901bff 100644
--- a/configs/zeropi_defconfig
+++ b/configs/zeropi_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
-CONFIG_MACPWR="PD6"
# CONFIG_VIDEO_DE2 is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
index 64cdffb..1d8e5f6 100644
--- a/configs/zynq_cse_nand_defconfig
+++ b/configs/zynq_cse_nand_defconfig
@@ -28,10 +28,10 @@
CONFIG_SPL_BSS_MAX_SIZE=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x2000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
@@ -69,7 +69,6 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_MMC is not set
diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig
index 54620b2..db7cb63 100644
--- a/configs/zynq_cse_nor_defconfig
+++ b/configs/zynq_cse_nor_defconfig
@@ -28,10 +28,10 @@
CONFIG_SPL_BSS_MAX_SIZE=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x2000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
@@ -68,7 +68,6 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_MMC is not set
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index 08c5009..dcb22ed 100644
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -23,8 +23,8 @@
CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
# CONFIG_AUTOBOOT is not set
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_BOARD_LATE_INIT is not set
@@ -35,10 +35,10 @@
CONFIG_SPL_BSS_MAX_SIZE=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x2000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
# CONFIG_CMDLINE_EDITING is not set
@@ -77,7 +77,6 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_MMC is not set
diff --git a/crosvm-aarch64.fragment b/crosvm-aarch64.fragment
index 4145fdf..93d5417 100644
--- a/crosvm-aarch64.fragment
+++ b/crosvm-aarch64.fragment
@@ -3,6 +3,7 @@
CONFIG_INIT_SP_RELATIVE=y
CONFIG_SYS_SDRAM_BASE=0x80000000
CONFIG_SYS_FDT_ADDR=0x80000000
+CONFIG_PRE_CON_BUF_ADDR=0x80100000
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SYS_RAMDISK_ADDR_R=0x84200000
CONFIG_SYS_TEXT_BASE=0x80200000
diff --git a/crosvm-x86_64.fragment b/crosvm-x86_64.fragment
index c25a103..eb06aba 100644
--- a/crosvm-x86_64.fragment
+++ b/crosvm-x86_64.fragment
@@ -1,7 +1,7 @@
# crosvm does not support qemu-fw, therefore it cannot determine the number
# of onlined CPUs, generate an MPTABLE, or use table-loader to generate the
# PIEQ/ACPI tables. Disable these features to boot Linux with SMP.
-# CONFIG_GENERATE_ACPI_TABLE is not set
+# CONFIG_ACPI is not set
# CONFIG_GENERATE_MP_TABLE is not set
# CONFIG_GENERATE_PIRQ_TABLE is not set
# CONFIG_MAX_CPUS is not set
diff --git a/disk/disk-uclass.c b/disk/disk-uclass.c
index d32747e..efe4bf1 100644
--- a/disk/disk-uclass.c
+++ b/disk/disk-uclass.c
@@ -17,227 +17,110 @@
#include <dm/device-internal.h>
#include <dm/lists.h>
-int part_create_block_devices(struct udevice *blk_dev)
+/**
+ * disk_blk_part_validate() - Check whether access to partition is within limits
+ *
+ * @dev: Device (partition udevice)
+ * @start: Start block for the access(from start of partition)
+ * @blkcnt: Number of blocks to access (within the partition)
+ * @return 0 on valid block range, or -ve on error.
+ */
+static int disk_blk_part_validate(struct udevice *dev, lbaint_t start, lbaint_t blkcnt)
{
- int part, count;
- struct blk_desc *desc = dev_get_uclass_plat(blk_dev);
- struct disk_partition info;
- struct disk_part *part_data;
- char devname[32];
- struct udevice *dev;
- int ret;
+ struct disk_part *part = dev_get_uclass_plat(dev);
- if (!CONFIG_IS_ENABLED(PARTITIONS) || !blk_enabled())
- return 0;
+ if (device_get_uclass_id(dev) != UCLASS_PARTITION)
+ return -ENOSYS;
- if (device_get_uclass_id(blk_dev) != UCLASS_BLK)
- return 0;
+ if (start >= part->gpt_part_info.size)
+ return -E2BIG;
- /* Add devices for each partition */
- for (count = 0, part = 1; part <= MAX_SEARCH_PARTITIONS; part++) {
- if (part_get_info(desc, part, &info))
- continue;
- snprintf(devname, sizeof(devname), "%s:%d", blk_dev->name,
- part);
-
- ret = device_bind_driver(blk_dev, "blk_partition",
- strdup(devname), &dev);
- if (ret)
- return ret;
-
- part_data = dev_get_uclass_plat(dev);
- part_data->partnum = part;
- part_data->gpt_part_info = info;
- count++;
-
- ret = device_probe(dev);
- if (ret) {
- debug("Can't probe\n");
- count--;
- device_unbind(dev);
-
- continue;
- }
- }
- debug("%s: %d partitions found in %s\n", __func__, count,
- blk_dev->name);
+ if ((start + blkcnt) > part->gpt_part_info.size)
+ return -ERANGE;
return 0;
}
-static ulong part_blk_read(struct udevice *dev, lbaint_t start,
- lbaint_t blkcnt, void *buffer)
+/**
+ * disk_blk_part_offset() - Compute offset from start of block device
+ *
+ * @dev: Device (partition udevice)
+ * @start: Start block for the access (from start of partition)
+ * @return Start block for the access (from start of block device)
+ */
+static lbaint_t disk_blk_part_offset(struct udevice *dev, lbaint_t start)
{
- struct udevice *parent;
- struct disk_part *part;
- const struct blk_ops *ops;
+ struct disk_part *part = dev_get_uclass_plat(dev);
- parent = dev_get_parent(dev);
- ops = blk_get_ops(parent);
- if (!ops->read)
- return -ENOSYS;
-
- part = dev_get_uclass_plat(dev);
- if (start >= part->gpt_part_info.size)
- return 0;
-
- if ((start + blkcnt) > part->gpt_part_info.size)
- blkcnt = part->gpt_part_info.size - start;
- start += part->gpt_part_info.start;
-
- return ops->read(parent, start, blkcnt, buffer);
+ return start + part->gpt_part_info.start;
}
-static ulong part_blk_write(struct udevice *dev, lbaint_t start,
- lbaint_t blkcnt, const void *buffer)
-{
- struct udevice *parent;
- struct disk_part *part;
- const struct blk_ops *ops;
-
- parent = dev_get_parent(dev);
- ops = blk_get_ops(parent);
- if (!ops->write)
- return -ENOSYS;
-
- part = dev_get_uclass_plat(dev);
- if (start >= part->gpt_part_info.size)
- return 0;
-
- if ((start + blkcnt) > part->gpt_part_info.size)
- blkcnt = part->gpt_part_info.size - start;
- start += part->gpt_part_info.start;
-
- return ops->write(parent, start, blkcnt, buffer);
-}
-
-static ulong part_blk_erase(struct udevice *dev, lbaint_t start,
- lbaint_t blkcnt)
-{
- struct udevice *parent;
- struct disk_part *part;
- const struct blk_ops *ops;
-
- parent = dev_get_parent(dev);
- ops = blk_get_ops(parent);
- if (!ops->erase)
- return -ENOSYS;
-
- part = dev_get_uclass_plat(dev);
- if (start >= part->gpt_part_info.size)
- return 0;
-
- if ((start + blkcnt) > part->gpt_part_info.size)
- blkcnt = part->gpt_part_info.size - start;
- start += part->gpt_part_info.start;
-
- return ops->erase(parent, start, blkcnt);
-}
-
-static const struct blk_ops blk_part_ops = {
- .read = part_blk_read,
- .write = part_blk_write,
- .erase = part_blk_erase,
-};
-
-U_BOOT_DRIVER(blk_partition) = {
- .name = "blk_partition",
- .id = UCLASS_PARTITION,
- .ops = &blk_part_ops,
-};
-
/*
* BLOCK IO APIs
*/
-static struct blk_desc *dev_get_blk(struct udevice *dev)
-{
- struct blk_desc *desc;
-
- switch (device_get_uclass_id(dev)) {
- /*
- * We won't support UCLASS_BLK with dev_* interfaces.
- */
- case UCLASS_PARTITION:
- desc = dev_get_uclass_plat(dev_get_parent(dev));
- break;
- default:
- desc = NULL;
- break;
- }
-
- return desc;
-}
-
+/**
+ * disk_blk_read() - Read from a block device partition
+ *
+ * @dev: Device to read from (partition udevice)
+ * @start: Start block for the read (from start of partition)
+ * @blkcnt: Number of blocks to read (within the partition)
+ * @buffer: Place to put the data
+ * @return number of blocks read (which may be less than @blkcnt),
+ * or -ve on error. This never returns 0 unless @blkcnt is 0
+ */
unsigned long disk_blk_read(struct udevice *dev, lbaint_t start,
lbaint_t blkcnt, void *buffer)
{
- struct blk_desc *desc;
- const struct blk_ops *ops;
- struct disk_part *part;
- lbaint_t start_in_disk;
- ulong blks_read;
+ int ret = disk_blk_part_validate(dev, start, blkcnt);
- desc = dev_get_blk(dev);
- if (!desc)
- return -ENOSYS;
+ if (ret)
+ return ret;
- ops = blk_get_ops(dev);
- if (!ops->read)
- return -ENOSYS;
-
- start_in_disk = start;
- if (device_get_uclass_id(dev) == UCLASS_PARTITION) {
- part = dev_get_uclass_plat(dev);
- start_in_disk += part->gpt_part_info.start;
- }
-
- if (blkcache_read(desc->uclass_id, desc->devnum, start_in_disk, blkcnt,
- desc->blksz, buffer))
- return blkcnt;
- blks_read = ops->read(dev, start, blkcnt, buffer);
- if (blks_read == blkcnt)
- blkcache_fill(desc->uclass_id, desc->devnum, start_in_disk,
- blkcnt, desc->blksz, buffer);
-
- return blks_read;
+ return blk_read(dev_get_parent(dev), disk_blk_part_offset(dev, start),
+ blkcnt, buffer);
}
+/**
+ * disk_blk_write() - Write to a block device
+ *
+ * @dev: Device to write to (partition udevice)
+ * @start: Start block for the write (from start of partition)
+ * @blkcnt: Number of blocks to write (within the partition)
+ * @buffer: Data to write
+ * @return number of blocks written (which may be less than @blkcnt),
+ * or -ve on error. This never returns 0 unless @blkcnt is 0
+ */
unsigned long disk_blk_write(struct udevice *dev, lbaint_t start,
lbaint_t blkcnt, const void *buffer)
{
- struct blk_desc *desc;
- const struct blk_ops *ops;
+ int ret = disk_blk_part_validate(dev, start, blkcnt);
- desc = dev_get_blk(dev);
- if (!desc)
- return -ENOSYS;
+ if (ret)
+ return ret;
- ops = blk_get_ops(dev);
- if (!ops->write)
- return -ENOSYS;
-
- blkcache_invalidate(desc->uclass_id, desc->devnum);
-
- return ops->write(dev, start, blkcnt, buffer);
+ return blk_write(dev_get_parent(dev), disk_blk_part_offset(dev, start),
+ blkcnt, buffer);
}
+/**
+ * disk_blk_erase() - Erase part of a block device
+ *
+ * @dev: Device to erase (partition udevice)
+ * @start: Start block for the erase (from start of partition)
+ * @blkcnt: Number of blocks to erase (within the partition)
+ * @return number of blocks erased (which may be less than @blkcnt),
+ * or -ve on error. This never returns 0 unless @blkcnt is 0
+ */
unsigned long disk_blk_erase(struct udevice *dev, lbaint_t start,
lbaint_t blkcnt)
{
- struct blk_desc *desc;
- const struct blk_ops *ops;
+ int ret = disk_blk_part_validate(dev, start, blkcnt);
- desc = dev_get_blk(dev);
- if (!desc)
- return -ENOSYS;
+ if (ret)
+ return ret;
- ops = blk_get_ops(dev);
- if (!ops->erase)
- return -ENOSYS;
-
- blkcache_invalidate(desc->uclass_id, desc->devnum);
-
- return ops->erase(dev, start, blkcnt);
+ return blk_erase(dev_get_parent(dev), disk_blk_part_offset(dev, start),
+ blkcnt);
}
UCLASS_DRIVER(partition) = {
@@ -245,3 +128,15 @@
.per_device_plat_auto = sizeof(struct disk_part),
.name = "partition",
};
+
+static const struct blk_ops blk_part_ops = {
+ .read = disk_blk_read,
+ .write = disk_blk_write,
+ .erase = disk_blk_erase,
+};
+
+U_BOOT_DRIVER(blk_partition) = {
+ .name = "blk_partition",
+ .id = UCLASS_PARTITION,
+ .ops = &blk_part_ops,
+};
diff --git a/disk/part.c b/disk/part.c
index 26d865d..d1174eb 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -26,6 +26,12 @@
/* Check all partition types */
#define PART_TYPE_ALL -1
+/**
+ * part_driver_get_type() - Get a driver given its type
+ *
+ * @part_type: Partition type to find the driver for
+ * Return: Driver for that type, or NULL if none
+ */
static struct part_driver *part_driver_get_type(int part_type)
{
struct part_driver *drv =
@@ -42,25 +48,41 @@
return NULL;
}
-static struct part_driver *part_driver_lookup_type(struct blk_desc *dev_desc)
+/**
+ * part_driver_lookup_type() - Look up the partition driver for a blk device
+ *
+ * If @desc->part_type is PART_TYPE_UNKNOWN, this checks each parition driver
+ * against the blk device to see if there is a valid partition table acceptable
+ * to that driver.
+ *
+ * If @desc->part_type is already set, it just returns the driver for that
+ * type, without testing if the driver can find a valid partition on the
+ * descriptor.
+ *
+ * On success it updates @desc->part_type if set to PART_TYPE_UNKNOWN on entry
+ *
+ * @dev_desc: Device descriptor
+ * Return: Driver found, or NULL if none
+ */
+static struct part_driver *part_driver_lookup_type(struct blk_desc *desc)
{
struct part_driver *drv =
ll_entry_start(struct part_driver, part_driver);
const int n_ents = ll_entry_count(struct part_driver, part_driver);
struct part_driver *entry;
- if (dev_desc->part_type == PART_TYPE_UNKNOWN) {
+ if (desc->part_type == PART_TYPE_UNKNOWN) {
for (entry = drv; entry != drv + n_ents; entry++) {
int ret;
- ret = entry->test(dev_desc);
+ ret = entry->test(desc);
if (!ret) {
- dev_desc->part_type = entry->part_type;
+ desc->part_type = entry->part_type;
return entry;
}
}
} else {
- return part_driver_get_type(dev_desc->part_type);
+ return part_driver_get_type(desc->part_type);
}
/* Not found */
@@ -83,27 +105,37 @@
return PART_TYPE_UNKNOWN;
}
+/**
+ * get_dev_hwpart() - Get the descriptor for a device with hardware partitions
+ *
+ * @ifname: Interface name (e.g. "ide", "scsi")
+ * @dev: Device number (0 for first device on that interface, 1 for
+ * second, etc.
+ * @hwpart: Hardware partition, or 0 if none (used for MMC)
+ * Return: pointer to the block device, or NULL if not available, or an
+ * error occurred.
+ */
static struct blk_desc *get_dev_hwpart(const char *ifname, int dev, int hwpart)
{
- struct blk_desc *dev_desc;
+ struct blk_desc *desc;
int ret;
if (!blk_enabled())
return NULL;
- dev_desc = blk_get_devnum_by_uclass_idname(ifname, dev);
- if (!dev_desc) {
+ desc = blk_get_devnum_by_uclass_idname(ifname, dev);
+ if (!desc) {
debug("%s: No device for iface '%s', dev %d\n", __func__,
ifname, dev);
return NULL;
}
- ret = blk_dselect_hwpart(dev_desc, hwpart);
+ ret = blk_dselect_hwpart(desc, hwpart);
if (ret) {
debug("%s: Failed to select h/w partition: err-%d\n", __func__,
ret);
return NULL;
}
- return dev_desc;
+ return desc;
}
struct blk_desc *blk_get_dev(const char *ifname, int dev)
@@ -140,29 +172,24 @@
return bc_quot * mul_by + ((bc_rem * mul_by) >> right_shift);
}
-void dev_print(struct blk_desc *dev_desc)
+void dev_print(struct blk_desc *desc)
{
lba512_t lba512; /* number of blocks if 512bytes block size */
- if (dev_desc->type == DEV_TYPE_UNKNOWN) {
+ if (desc->type == DEV_TYPE_UNKNOWN) {
puts ("not available\n");
return;
}
- switch (dev_desc->uclass_id) {
+ switch (desc->uclass_id) {
case UCLASS_SCSI:
- printf ("(%d:%d) Vendor: %s Prod.: %s Rev: %s\n",
- dev_desc->target,dev_desc->lun,
- dev_desc->vendor,
- dev_desc->product,
- dev_desc->revision);
+ printf("(%d:%d) Vendor: %s Prod.: %s Rev: %s\n", desc->target,
+ desc->lun, desc->vendor, desc->product, desc->revision);
break;
case UCLASS_IDE:
case UCLASS_AHCI:
- printf ("Model: %s Firm: %s Ser#: %s\n",
- dev_desc->vendor,
- dev_desc->revision,
- dev_desc->product);
+ printf("Model: %s Firm: %s Ser#: %s\n", desc->vendor,
+ desc->revision, desc->product);
break;
case UCLASS_MMC:
case UCLASS_USB:
@@ -170,28 +197,29 @@
case UCLASS_PVBLOCK:
case UCLASS_HOST:
case UCLASS_BLKMAP:
+ case UCLASS_RKMTD:
printf ("Vendor: %s Rev: %s Prod: %s\n",
- dev_desc->vendor,
- dev_desc->revision,
- dev_desc->product);
+ desc->vendor,
+ desc->revision,
+ desc->product);
break;
case UCLASS_VIRTIO:
- printf("%s VirtIO Block Device\n", dev_desc->vendor);
+ printf("%s VirtIO Block Device\n", desc->vendor);
break;
case UCLASS_EFI_MEDIA:
- printf("EFI media Block Device %d\n", dev_desc->devnum);
+ printf("EFI media Block Device %d\n", desc->devnum);
break;
case UCLASS_INVALID:
puts("device type unknown\n");
return;
default:
- printf("Unhandled device type: %i\n", dev_desc->uclass_id);
+ printf("Unhandled device type: %i\n", desc->uclass_id);
return;
}
puts (" Type: ");
- if (dev_desc->removable)
+ if (desc->removable)
puts ("Removable ");
- switch (dev_desc->type & 0x1F) {
+ switch (desc->type & 0x1F) {
case DEV_TYPE_HARDDISK:
puts ("Hard Disk");
break;
@@ -205,17 +233,17 @@
puts ("Tape");
break;
default:
- printf ("# %02X #", dev_desc->type & 0x1F);
+ printf("# %02X #", desc->type & 0x1F);
break;
}
puts ("\n");
- if (dev_desc->lba > 0L && dev_desc->blksz > 0L) {
+ if (desc->lba > 0L && desc->blksz > 0L) {
ulong mb, mb_quot, mb_rem, gb, gb_quot, gb_rem;
lbaint_t lba;
- lba = dev_desc->lba;
+ lba = desc->lba;
- lba512 = (lba * (dev_desc->blksz/512));
+ lba512 = lba * (desc->blksz / 512);
/* round to 1 digit */
/* 2048 = (1024 * 1024) / 512 MB */
mb = lba512_muldiv(lba512, 10, 11);
@@ -227,7 +255,7 @@
gb_quot = gb / 10;
gb_rem = gb - (10 * gb_quot);
#ifdef CONFIG_LBA48
- if (dev_desc->lba48)
+ if (desc->lba48)
printf (" Supports 48-bit addressing\n");
#endif
#if defined(CONFIG_SYS_64BIT_LBA)
@@ -235,42 +263,42 @@
mb_quot, mb_rem,
gb_quot, gb_rem,
lba,
- dev_desc->blksz);
+ desc->blksz);
#else
printf (" Capacity: %lu.%lu MB = %lu.%lu GB (%lu x %lu)\n",
mb_quot, mb_rem,
gb_quot, gb_rem,
(ulong)lba,
- dev_desc->blksz);
+ desc->blksz);
#endif
} else {
puts (" Capacity: not available\n");
}
}
-void part_init(struct blk_desc *dev_desc)
+void part_init(struct blk_desc *desc)
{
struct part_driver *drv =
ll_entry_start(struct part_driver, part_driver);
const int n_ents = ll_entry_count(struct part_driver, part_driver);
struct part_driver *entry;
- blkcache_invalidate(dev_desc->uclass_id, dev_desc->devnum);
+ blkcache_invalidate(desc->uclass_id, desc->devnum);
- dev_desc->part_type = PART_TYPE_UNKNOWN;
+ desc->part_type = PART_TYPE_UNKNOWN;
for (entry = drv; entry != drv + n_ents; entry++) {
int ret;
- ret = entry->test(dev_desc);
+ ret = entry->test(desc);
debug("%s: try '%s': ret=%d\n", __func__, entry->name, ret);
if (!ret) {
- dev_desc->part_type = entry->part_type;
+ desc->part_type = entry->part_type;
break;
}
}
}
-static void print_part_header(const char *type, struct blk_desc *dev_desc)
+static void print_part_header(const char *type, struct blk_desc *desc)
{
#if CONFIG_IS_ENABLED(MAC_PARTITION) || \
CONFIG_IS_ENABLED(DOS_PARTITION) || \
@@ -278,7 +306,7 @@
CONFIG_IS_ENABLED(AMIGA_PARTITION) || \
CONFIG_IS_ENABLED(EFI_PARTITION)
puts ("\nPartition Map for ");
- switch (dev_desc->uclass_id) {
+ switch (desc->uclass_id) {
case UCLASS_IDE:
puts ("IDE");
break;
@@ -303,61 +331,63 @@
case UCLASS_PVBLOCK:
puts("PV BLOCK");
break;
+ case UCLASS_RKMTD:
+ puts("RKMTD");
+ break;
case UCLASS_VIRTIO:
puts("VirtIO");
break;
case UCLASS_EFI_MEDIA:
puts("EFI");
break;
+ case UCLASS_BLKMAP:
+ puts("BLKMAP");
+ break;
default:
- puts("UNKNOWN");
+ printf("UNKNOWN(%d)", desc->uclass_id);
break;
}
printf (" device %d -- Partition Type: %s\n\n",
- dev_desc->devnum, type);
+ desc->devnum, type);
#endif /* any CONFIG_..._PARTITION */
}
-void part_print(struct blk_desc *dev_desc)
+void part_print(struct blk_desc *desc)
{
struct part_driver *drv;
- drv = part_driver_lookup_type(dev_desc);
+ drv = part_driver_lookup_type(desc);
if (!drv) {
printf("## Unknown partition table type %x\n",
- dev_desc->part_type);
+ desc->part_type);
return;
}
PRINTF("## Testing for valid %s partition ##\n", drv->name);
- print_part_header(drv->name, dev_desc);
+ print_part_header(drv->name, desc);
if (drv->print)
- drv->print(dev_desc);
+ drv->print(desc);
}
-int part_get_info_by_type(struct blk_desc *dev_desc, int part, int part_type,
+int part_get_info_by_type(struct blk_desc *desc, int part, int part_type,
struct disk_partition *info)
{
struct part_driver *drv;
if (blk_enabled()) {
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
/* The common case is no UUID support */
- info->uuid[0] = 0;
-#endif
-#ifdef CONFIG_PARTITION_TYPE_GUID
- info->type_guid[0] = 0;
-#endif
+ disk_partition_clr_uuid(info);
+ disk_partition_clr_type_guid(info);
if (part_type == PART_TYPE_UNKNOWN) {
- drv = part_driver_lookup_type(dev_desc);
+ drv = part_driver_lookup_type(desc);
} else {
drv = part_driver_get_type(part_type);
}
if (!drv) {
debug("## Unknown partition table type %x\n",
- dev_desc->part_type);
+ desc->part_type);
return -EPROTONOSUPPORT;
}
if (!drv->get_info) {
@@ -365,7 +395,7 @@
drv->name);
return -ENOSYS;
}
- if (drv->get_info(dev_desc, part, info) == 0) {
+ if (drv->get_info(desc, part, info) == 0) {
PRINTF("## Valid %s partition found ##\n", drv->name);
return 0;
}
@@ -374,33 +404,29 @@
return -ENOENT;
}
-int part_get_info(struct blk_desc *dev_desc, int part,
+int part_get_info(struct blk_desc *desc, int part,
struct disk_partition *info)
{
- return part_get_info_by_type(dev_desc, part, PART_TYPE_UNKNOWN, info);
+ return part_get_info_by_type(desc, part, PART_TYPE_UNKNOWN, info);
}
-int part_get_info_whole_disk(struct blk_desc *dev_desc,
+int part_get_info_whole_disk(struct blk_desc *desc,
struct disk_partition *info)
{
info->start = 0;
- info->size = dev_desc->lba;
- info->blksz = dev_desc->blksz;
+ info->size = desc->lba;
+ info->blksz = desc->blksz;
info->bootable = 0;
strcpy((char *)info->type, BOOT_PART_TYPE);
strcpy((char *)info->name, "Whole Disk");
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- info->uuid[0] = 0;
-#endif
-#ifdef CONFIG_PARTITION_TYPE_GUID
- info->type_guid[0] = 0;
-#endif
+ disk_partition_clr_uuid(info);
+ disk_partition_clr_type_guid(info);
return 0;
}
int blk_get_device_by_str(const char *ifname, const char *dev_hwpart_str,
- struct blk_desc **dev_desc)
+ struct blk_desc **desc)
{
char *ep;
char *dup_str = NULL;
@@ -436,8 +462,8 @@
}
}
- *dev_desc = get_dev_hwpart(ifname, dev, hwpart);
- if (!(*dev_desc) || ((*dev_desc)->type == DEV_TYPE_UNKNOWN)) {
+ *desc = get_dev_hwpart(ifname, dev, hwpart);
+ if (!(*desc) || ((*desc)->type == DEV_TYPE_UNKNOWN)) {
debug("** Bad device %s %s **\n", ifname, dev_hwpart_str);
dev = -ENODEV;
goto cleanup;
@@ -449,8 +475,8 @@
* Always should be done, otherwise hw partition 0 will return
* stale data after displaying a non-zero hw partition.
*/
- if ((*dev_desc)->uclass_id == UCLASS_MMC)
- part_init(*dev_desc);
+ if ((*desc)->uclass_id == UCLASS_MMC)
+ part_init(*desc);
}
cleanup:
@@ -461,7 +487,7 @@
#define PART_UNSPECIFIED -2
#define PART_AUTO -1
int blk_get_device_part_str(const char *ifname, const char *dev_part_str,
- struct blk_desc **dev_desc,
+ struct blk_desc **desc,
struct disk_partition *info, int allow_whole_dev)
{
int ret;
@@ -474,7 +500,7 @@
int part;
struct disk_partition tmpinfo;
- *dev_desc = NULL;
+ *desc = NULL;
memset(info, 0, sizeof(*info));
#if IS_ENABLED(CONFIG_SANDBOX) || IS_ENABLED(CONFIG_SEMIHOSTING)
@@ -533,7 +559,7 @@
}
/* Look up the device */
- dev = blk_get_device_by_str(ifname, dev_str, dev_desc);
+ dev = blk_get_device_by_str(ifname, dev_str, desc);
if (dev < 0) {
printf("** Bad device specification %s %s **\n",
ifname, dev_str);
@@ -565,9 +591,8 @@
* No partition table on device,
* or user requested partition 0 (entire device).
*/
- if (((*dev_desc)->part_type == PART_TYPE_UNKNOWN) ||
- (part == 0)) {
- if (!(*dev_desc)->lba) {
+ if (((*desc)->part_type == PART_TYPE_UNKNOWN) || !part) {
+ if (!(*desc)->lba) {
printf("** Bad device size - %s %s **\n", ifname,
dev_str);
ret = -EINVAL;
@@ -586,9 +611,9 @@
goto cleanup;
}
- (*dev_desc)->log2blksz = LOG2((*dev_desc)->blksz);
+ (*desc)->log2blksz = LOG2((*desc)->blksz);
- part_get_info_whole_disk(*dev_desc, info);
+ part_get_info_whole_disk(*desc, info);
ret = 0;
goto cleanup;
@@ -606,7 +631,7 @@
* other than "auto", use that partition number directly.
*/
if (part != PART_AUTO) {
- ret = part_get_info(*dev_desc, part, info);
+ ret = part_get_info(*desc, part, info);
if (ret) {
printf("** Invalid partition %d **\n", part);
goto cleanup;
@@ -618,7 +643,7 @@
*/
part = 0;
for (p = 1; p <= MAX_SEARCH_PARTITIONS; p++) {
- ret = part_get_info(*dev_desc, p, info);
+ ret = part_get_info(*desc, p, info);
if (ret)
continue;
@@ -662,7 +687,7 @@
goto cleanup;
}
- (*dev_desc)->log2blksz = LOG2((*dev_desc)->blksz);
+ (*desc)->log2blksz = LOG2((*desc)->blksz);
ret = part;
goto cleanup;
@@ -672,14 +697,14 @@
return ret;
}
-int part_get_info_by_name(struct blk_desc *dev_desc, const char *name,
+int part_get_info_by_name(struct blk_desc *desc, const char *name,
struct disk_partition *info)
{
struct part_driver *part_drv;
int ret;
int i;
- part_drv = part_driver_lookup_type(dev_desc);
+ part_drv = part_driver_lookup_type(desc);
if (!part_drv)
return -1;
@@ -690,7 +715,7 @@
}
for (i = 1; i < part_drv->max_entries; i++) {
- ret = part_drv->get_info(dev_desc, i, info);
+ ret = part_drv->get_info(desc, i, info);
if (ret != 0) {
/* no more entries in table */
break;
@@ -710,18 +735,18 @@
* Parse a device number and partition name string in the form of
* "devicenum.hwpartnum#partition_name", for example "0.1#misc". devicenum and
* hwpartnum are both optional, defaulting to 0. If the partition is found,
- * sets dev_desc and part_info accordingly with the information of the
+ * sets desc and part_info accordingly with the information of the
* partition with the given partition_name.
*
* @param[in] dev_iface Device interface
* @param[in] dev_part_str Input string argument, like "0.1#misc"
- * @param[out] dev_desc Place to store the device description pointer
+ * @param[out] desc Place to store the device description pointer
* @param[out] part_info Place to store the partition information
* Return: 0 on success, or a negative on error
*/
int part_get_info_by_dev_and_name(const char *dev_iface,
const char *dev_part_str,
- struct blk_desc **dev_desc,
+ struct blk_desc **desc,
struct disk_partition *part_info)
{
char *dup_str = NULL;
@@ -743,11 +768,11 @@
return -EINVAL;
}
- ret = blk_get_device_by_str(dev_iface, dev_str, dev_desc);
+ ret = blk_get_device_by_str(dev_iface, dev_str, desc);
if (ret < 0)
goto cleanup;
- ret = part_get_info_by_name(*dev_desc, part_str, part_info);
+ ret = part_get_info_by_name(*desc, part_str, part_info);
if (ret < 0)
printf("Could not find \"%s\" partition\n", part_str);
@@ -758,35 +783,35 @@
int part_get_info_by_dev_and_name_or_num(const char *dev_iface,
const char *dev_part_str,
- struct blk_desc **dev_desc,
+ struct blk_desc **desc,
struct disk_partition *part_info,
int allow_whole_dev)
{
int ret;
/* Split the part_name if passed as "$dev_num#part_name". */
- ret = part_get_info_by_dev_and_name(dev_iface, dev_part_str,
- dev_desc, part_info);
+ ret = part_get_info_by_dev_and_name(dev_iface, dev_part_str, desc,
+ part_info);
if (ret >= 0)
return ret;
/*
* Couldn't lookup by name, try looking up the partition description
* directly.
*/
- ret = blk_get_device_part_str(dev_iface, dev_part_str,
- dev_desc, part_info, allow_whole_dev);
+ ret = blk_get_device_part_str(dev_iface, dev_part_str, desc, part_info,
+ allow_whole_dev);
if (ret < 0)
printf("Couldn't find partition %s %s\n",
dev_iface, dev_part_str);
return ret;
}
-void part_set_generic_name(const struct blk_desc *dev_desc,
- int part_num, char *name)
+void part_set_generic_name(const struct blk_desc *desc, int part_num,
+ char *name)
{
char *devtype;
- switch (dev_desc->uclass_id) {
+ switch (desc->uclass_id) {
case UCLASS_IDE:
case UCLASS_AHCI:
devtype = "hd";
@@ -805,7 +830,7 @@
break;
}
- sprintf(name, "%s%c%d", devtype, 'a' + dev_desc->devnum, part_num);
+ sprintf(name, "%s%c%d", devtype, 'a' + desc->devnum, part_num);
}
int part_get_bootable(struct blk_desc *desc)
diff --git a/disk/part_amiga.c b/disk/part_amiga.c
index 45d3a70..65e30fe 100644
--- a/disk/part_amiga.c
+++ b/disk/part_amiga.c
@@ -125,7 +125,7 @@
* the ID AMIGA_ID_RDISK ('RDSK') and needs to have a valid
* sum-to-zero checksum
*/
-struct rigid_disk_block *get_rdisk(struct blk_desc *dev_desc)
+struct rigid_disk_block *get_rdisk(struct blk_desc *desc)
{
int i;
int limit;
@@ -139,7 +139,7 @@
for (i=0; i<limit; i++)
{
- ulong res = blk_dread(dev_desc, i, 1, (ulong *)block_buffer);
+ ulong res = blk_dread(desc, i, 1, (ulong *)block_buffer);
if (res == 1)
{
struct rigid_disk_block *trdb = (struct rigid_disk_block *)block_buffer;
@@ -165,7 +165,7 @@
* Ridgid disk block
*/
-struct bootcode_block *get_bootcode(struct blk_desc *dev_desc)
+struct bootcode_block *get_bootcode(struct blk_desc *desc)
{
int i;
int limit;
@@ -181,7 +181,7 @@
for (i = 0; i < limit; i++)
{
- ulong res = blk_dread(dev_desc, i, 1, (ulong *)block_buffer);
+ ulong res = blk_dread(desc, i, 1, (ulong *)block_buffer);
if (res == 1)
{
struct bootcode_block *boot = (struct bootcode_block *)block_buffer;
@@ -206,17 +206,17 @@
* Test if the given partition has an Amiga partition table/Rigid
* Disk block
*/
-static int part_test_amiga(struct blk_desc *dev_desc)
+static int part_test_amiga(struct blk_desc *desc)
{
struct rigid_disk_block *rdb;
struct bootcode_block *bootcode;
PRINTF("part_test_amiga: Testing for an Amiga RDB partition\n");
- rdb = get_rdisk(dev_desc);
+ rdb = get_rdisk(desc);
if (rdb)
{
- bootcode = get_bootcode(dev_desc);
+ bootcode = get_bootcode(desc);
if (bootcode)
PRINTF("part_test_amiga: bootable Amiga disk\n");
else
@@ -235,7 +235,7 @@
/*
* Find partition number partnum on the given drive.
*/
-static struct partition_block *find_partition(struct blk_desc *dev_desc,
+static struct partition_block *find_partition(struct blk_desc *desc,
int partnum)
{
struct rigid_disk_block *rdb;
@@ -243,7 +243,7 @@
u32 block;
PRINTF("Trying to find partition block %d\n", partnum);
- rdb = get_rdisk(dev_desc);
+ rdb = get_rdisk(desc);
if (!rdb)
{
PRINTF("find_partition: no rdb found\n");
@@ -257,7 +257,7 @@
while (block != 0xFFFFFFFF)
{
- ulong res = blk_dread(dev_desc, block, 1, (ulong *)block_buffer);
+ ulong res = blk_dread(desc, block, 1, (ulong *)block_buffer);
if (res == 1)
{
p = (struct partition_block *)block_buffer;
@@ -289,10 +289,10 @@
/*
* Get info about a partition
*/
-static int part_get_info_amiga(struct blk_desc *dev_desc, int part,
- struct disk_partition *info)
+static int part_get_info_amiga(struct blk_desc *desc, int part,
+ struct disk_partition *info)
{
- struct partition_block *p = find_partition(dev_desc, part-1);
+ struct partition_block *p = find_partition(desc, part - 1);
struct amiga_part_geometry *g;
u32 disk_type;
@@ -317,7 +317,7 @@
return 0;
}
-static void part_print_amiga(struct blk_desc *dev_desc)
+static void part_print_amiga(struct blk_desc *desc)
{
struct rigid_disk_block *rdb;
struct bootcode_block *boot;
@@ -325,7 +325,7 @@
u32 block;
int i = 1;
- rdb = get_rdisk(dev_desc);
+ rdb = get_rdisk(desc);
if (!rdb)
{
PRINTF("part_print_amiga: no rdb found\n");
@@ -353,7 +353,7 @@
PRINTF("Trying to load block #0x%X\n", block);
- res = blk_dread(dev_desc, block, 1, (ulong *)block_buffer);
+ res = blk_dread(desc, block, 1, (ulong *)block_buffer);
if (res == 1)
{
p = (struct partition_block *)block_buffer;
@@ -370,7 +370,7 @@
} else block = 0xFFFFFFFF;
}
- boot = get_bootcode(dev_desc);
+ boot = get_bootcode(desc);
if (boot)
{
printf("Disk is bootable\n");
diff --git a/disk/part_dos.c b/disk/part_dos.c
index 56e6188..567ead7 100644
--- a/disk/part_dos.c
+++ b/disk/part_dos.c
@@ -98,27 +98,26 @@
return -1;
}
-static int part_test_dos(struct blk_desc *dev_desc)
+static int part_test_dos(struct blk_desc *desc)
{
#ifndef CONFIG_SPL_BUILD
ALLOC_CACHE_ALIGN_BUFFER(legacy_mbr, mbr,
- DIV_ROUND_UP(dev_desc->blksz, sizeof(legacy_mbr)));
+ DIV_ROUND_UP(desc->blksz, sizeof(legacy_mbr)));
- if (blk_dread(dev_desc, 0, 1, (ulong *)mbr) != 1)
+ if (blk_dread(desc, 0, 1, (ulong *)mbr) != 1)
return -1;
if (test_block_type((unsigned char *)mbr) != DOS_MBR)
return -1;
- if (dev_desc->sig_type == SIG_TYPE_NONE &&
- mbr->unique_mbr_signature != 0) {
- dev_desc->sig_type = SIG_TYPE_MBR;
- dev_desc->mbr_sig = mbr->unique_mbr_signature;
+ if (desc->sig_type == SIG_TYPE_NONE && mbr->unique_mbr_signature) {
+ desc->sig_type = SIG_TYPE_MBR;
+ desc->mbr_sig = mbr->unique_mbr_signature;
}
#else
- ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, desc->blksz);
- if (blk_dread(dev_desc, 0, 1, (ulong *)buffer) != 1)
+ if (blk_dread(desc, 0, 1, (ulong *)buffer) != 1)
return -1;
if (test_block_type(buffer) != DOS_MBR)
@@ -130,12 +129,12 @@
/* Print a partition that is relative to its Extended partition table
*/
-static void print_partition_extended(struct blk_desc *dev_desc,
+static void print_partition_extended(struct blk_desc *desc,
lbaint_t ext_part_sector,
lbaint_t relative,
int part_num, unsigned int disksig)
{
- ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, desc->blksz);
dos_partition_t *pt;
int i;
@@ -146,9 +145,9 @@
return;
}
- if (blk_dread(dev_desc, ext_part_sector, 1, (ulong *)buffer) != 1) {
+ if (blk_dread(desc, ext_part_sector, 1, (ulong *)buffer) != 1) {
printf ("** Can't read partition table on %d:" LBAFU " **\n",
- dev_desc->devnum, ext_part_sector);
+ desc->devnum, ext_part_sector);
return;
}
i=test_block_type(buffer);
@@ -189,9 +188,9 @@
lbaint_t lba_start
= get_unaligned_le32 (pt->start4) + relative;
- print_partition_extended(dev_desc, lba_start,
- ext_part_sector == 0 ? lba_start : relative,
- part_num, disksig);
+ print_partition_extended(desc, lba_start,
+ !ext_part_sector ? lba_start :
+ relative, part_num, disksig);
}
}
@@ -201,14 +200,15 @@
/* Print a partition that is relative to its Extended partition table
*/
-static int part_get_info_extended(struct blk_desc *dev_desc,
+static int part_get_info_extended(struct blk_desc *desc,
lbaint_t ext_part_sector, lbaint_t relative,
int part_num, int which_part,
struct disk_partition *info, uint disksig)
{
- ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, desc->blksz);
+ struct disk_partition wdinfo = { 0 };
dos_partition_t *pt;
- int i;
+ int i, ret;
int dos_type;
/* set a maximum recursion level */
@@ -218,9 +218,9 @@
return -1;
}
- if (blk_dread(dev_desc, ext_part_sector, 1, (ulong *)buffer) != 1) {
+ if (blk_dread(desc, ext_part_sector, 1, (ulong *)buffer) != 1) {
printf ("** Can't read partition table on %d:" LBAFU " **\n",
- dev_desc->devnum, ext_part_sector);
+ desc->devnum, ext_part_sector);
return -1;
}
if (buffer[DOS_PART_MAGIC_OFFSET] != 0x55 ||
@@ -231,10 +231,12 @@
return -1;
}
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- if (!ext_part_sector)
+ if (CONFIG_IS_ENABLED(PARTITION_UUIDS) && !ext_part_sector)
disksig = get_unaligned_le32(&buffer[DOS_PART_DISKSIG_OFFSET]);
-#endif
+
+ ret = part_get_info_whole_disk(desc, &wdinfo);
+ if (ret)
+ return ret;
/* Print all primary/logical partitions */
pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET);
@@ -247,18 +249,24 @@
(pt->sys_ind != 0) &&
(part_num == which_part) &&
(ext_part_sector == 0 || is_extended(pt->sys_ind) == 0)) {
- info->blksz = DOS_PART_DEFAULT_SECTOR;
+ if (wdinfo.blksz > DOS_PART_DEFAULT_SECTOR)
+ info->blksz = wdinfo.blksz;
+ else
+ info->blksz = DOS_PART_DEFAULT_SECTOR;
info->start = (lbaint_t)(ext_part_sector +
get_unaligned_le32(pt->start4));
info->size = (lbaint_t)get_unaligned_le32(pt->size4);
- part_set_generic_name(dev_desc, part_num,
+ part_set_generic_name(desc, part_num,
(char *)info->name);
/* sprintf(info->type, "%d, pt->sys_ind); */
strcpy((char *)info->type, "U-Boot");
info->bootable = get_bootable(pt);
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- sprintf(info->uuid, "%08x-%02x", disksig, part_num);
-#endif
+ if (CONFIG_IS_ENABLED(PARTITION_UUIDS)) {
+ char str[12];
+
+ sprintf(str, "%08x-%02x", disksig, part_num);
+ disk_partition_set_uuid(info, str);
+ }
info->sys_ind = pt->sys_ind;
return 0;
}
@@ -277,7 +285,7 @@
lbaint_t lba_start
= get_unaligned_le32 (pt->start4) + relative;
- return part_get_info_extended(dev_desc, lba_start,
+ return part_get_info_extended(desc, lba_start,
ext_part_sector == 0 ? lba_start : relative,
part_num, which_part, info, disksig);
}
@@ -288,29 +296,30 @@
if (dos_type == DOS_PBR) {
info->start = 0;
- info->size = dev_desc->lba;
- info->blksz = DOS_PART_DEFAULT_SECTOR;
+ info->size = desc->lba;
+ if (wdinfo.blksz > DOS_PART_DEFAULT_SECTOR)
+ info->blksz = wdinfo.blksz;
+ else
+ info->blksz = DOS_PART_DEFAULT_SECTOR;
info->bootable = 0;
strcpy((char *)info->type, "U-Boot");
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- info->uuid[0] = 0;
-#endif
+ disk_partition_clr_uuid(info);
return 0;
}
return -1;
}
-static void __maybe_unused part_print_dos(struct blk_desc *dev_desc)
+static void __maybe_unused part_print_dos(struct blk_desc *desc)
{
printf("Part\tStart Sector\tNum Sectors\tUUID\t\tType\n");
- print_partition_extended(dev_desc, 0, 0, 1, 0);
+ print_partition_extended(desc, 0, 0, 1, 0);
}
-static int __maybe_unused part_get_info_dos(struct blk_desc *dev_desc, int part,
- struct disk_partition *info)
+static int __maybe_unused part_get_info_dos(struct blk_desc *desc, int part,
+ struct disk_partition *info)
{
- return part_get_info_extended(dev_desc, 0, 0, 1, part, info, 0);
+ return part_get_info_extended(desc, 0, 0, 1, part, info, 0);
}
int is_valid_dos_buf(void *buf)
@@ -457,7 +466,7 @@
ext = &p[i];
}
- if (count < 4)
+ if (count <= 4)
return 0;
if (!ext) {
@@ -490,20 +499,20 @@
}
#endif
-int write_mbr_sector(struct blk_desc *dev_desc, void *buf)
+int write_mbr_sector(struct blk_desc *desc, void *buf)
{
if (is_valid_dos_buf(buf))
return -1;
/* write MBR */
- if (blk_dwrite(dev_desc, 0, 1, buf) != 1) {
+ if (blk_dwrite(desc, 0, 1, buf) != 1) {
printf("%s: failed writing '%s' (1 blks at 0x0)\n",
__func__, "MBR");
return 1;
}
/* Update the partition table entries*/
- part_init(dev_desc);
+ part_init(desc);
return 0;
}
diff --git a/disk/part_efi.c b/disk/part_efi.c
index 80a44dc..4ce9243 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -9,6 +9,9 @@
* when CONFIG_SYS_64BIT_LBA is not defined, lbaint_t is 32 bits; this
* limits the maximum size of addressable storage to < 2 tebibytes
*/
+
+#define LOG_CATEGORY LOGC_FS
+
#include <common.h>
#include <blk.h>
#include <log.h>
@@ -26,6 +29,7 @@
#include <dm/ofnode.h>
#include <linux/compiler.h>
#include <linux/ctype.h>
+#include <linux/printk.h>
#include <u-boot/crc.h>
/* GUID for basic data partitons */
@@ -51,12 +55,12 @@
static int pmbr_part_valid(struct partition *part);
static int is_pmbr_valid(legacy_mbr * mbr);
-static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba,
- gpt_header *pgpt_head, gpt_entry **pgpt_pte);
-static gpt_entry *alloc_read_gpt_entries(struct blk_desc *dev_desc,
+static int is_gpt_valid(struct blk_desc *desc, u64 lba, gpt_header *pgpt_head,
+ gpt_entry **pgpt_pte);
+static gpt_entry *alloc_read_gpt_entries(struct blk_desc *desc,
gpt_header *pgpt_head);
static int is_pte_valid(gpt_entry * pte);
-static int find_valid_gpt(struct blk_desc *dev_desc, gpt_header *gpt_head,
+static int find_valid_gpt(struct blk_desc *desc, gpt_header *gpt_head,
gpt_entry **pgpt_pte);
static char *print_efiname(gpt_entry *pte)
@@ -195,14 +199,14 @@
* UUID is displayed as 32 hexadecimal digits, in 5 groups,
* separated by hyphens, in the form 8-4-4-4-12 for a total of 36 characters
*/
-int get_disk_guid(struct blk_desc * dev_desc, char *guid)
+int get_disk_guid(struct blk_desc *desc, char *guid)
{
- ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, desc->blksz);
gpt_entry *gpt_pte = NULL;
unsigned char *guid_bin;
/* This function validates AND fills in the GPT header and PTE */
- if (find_valid_gpt(dev_desc, gpt_head, &gpt_pte) != 1)
+ if (find_valid_gpt(desc, gpt_head, &gpt_pte) != 1)
return -EINVAL;
guid_bin = gpt_head->disk_guid.b;
@@ -213,15 +217,15 @@
return 0;
}
-void part_print_efi(struct blk_desc *dev_desc)
+void part_print_efi(struct blk_desc *desc)
{
- ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, desc->blksz);
gpt_entry *gpt_pte = NULL;
int i = 0;
unsigned char *uuid;
/* This function validates AND fills in the GPT header and PTE */
- if (find_valid_gpt(dev_desc, gpt_head, &gpt_pte) != 1)
+ if (find_valid_gpt(desc, gpt_head, &gpt_pte) != 1)
return;
debug("%s: gpt-entry at %p\n", __func__, gpt_pte);
@@ -255,10 +259,10 @@
return;
}
-int part_get_info_efi(struct blk_desc *dev_desc, int part,
+int part_get_info_efi(struct blk_desc *desc, int part,
struct disk_partition *info)
{
- ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, desc->blksz);
gpt_entry *gpt_pte = NULL;
/* "part" argument must be at least 1 */
@@ -268,7 +272,7 @@
}
/* This function validates AND fills in the GPT header and PTE */
- if (find_valid_gpt(dev_desc, gpt_head, &gpt_pte) != 1)
+ if (find_valid_gpt(desc, gpt_head, &gpt_pte) != 1)
return -EINVAL;
if (part > le32_to_cpu(gpt_head->num_partition_entries) ||
@@ -283,20 +287,22 @@
/* The ending LBA is inclusive, to calculate size, add 1 to it */
info->size = (lbaint_t)le64_to_cpu(gpt_pte[part - 1].ending_lba) + 1
- info->start;
- info->blksz = dev_desc->blksz;
+ info->blksz = desc->blksz;
snprintf((char *)info->name, sizeof(info->name), "%s",
print_efiname(&gpt_pte[part - 1]));
strcpy((char *)info->type, "U-Boot");
info->bootable = get_bootable(&gpt_pte[part - 1]);
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b, info->uuid,
- UUID_STR_FORMAT_GUID);
-#endif
-#ifdef CONFIG_PARTITION_TYPE_GUID
- uuid_bin_to_str(gpt_pte[part - 1].partition_type_guid.b,
- info->type_guid, UUID_STR_FORMAT_GUID);
-#endif
+ if (CONFIG_IS_ENABLED(PARTITION_UUIDS)) {
+ uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b,
+ (char *)disk_partition_uuid(info),
+ UUID_STR_FORMAT_GUID);
+ }
+ if (IS_ENABLED(CONFIG_PARTITION_TYPE_GUID)) {
+ uuid_bin_to_str(gpt_pte[part - 1].partition_type_guid.b,
+ (char *)disk_partition_type_guid(info),
+ UUID_STR_FORMAT_GUID);
+ }
log_debug("start 0x" LBAF ", size 0x" LBAF ", name %s\n", info->start,
info->size, info->name);
@@ -306,12 +312,12 @@
return 0;
}
-static int part_test_efi(struct blk_desc *dev_desc)
+static int part_test_efi(struct blk_desc *desc)
{
- ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, legacymbr, 1, dev_desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, legacymbr, 1, desc->blksz);
/* Read legacy MBR from block 0 and validate it */
- if ((blk_dread(dev_desc, 0, 1, (ulong *)legacymbr) != 1)
+ if ((blk_dread(desc, 0, 1, (ulong *)legacymbr) != 1)
|| (is_pmbr_valid(legacymbr) != 1)) {
return -1;
}
@@ -320,23 +326,23 @@
/**
* set_protective_mbr(): Set the EFI protective MBR
- * @param dev_desc - block device descriptor
+ * @param desc - block device descriptor
*
* Return: - zero on success, otherwise error
*/
-static int set_protective_mbr(struct blk_desc *dev_desc)
+static int set_protective_mbr(struct blk_desc *desc)
{
/* Setup the Protective MBR */
- ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, p_mbr, 1, dev_desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, p_mbr, 1, desc->blksz);
if (p_mbr == NULL) {
log_debug("calloc failed!\n");
return -ENOMEM;
}
/* Read MBR to backup boot code if it exists */
- if (blk_dread(dev_desc, 0, 1, p_mbr) != 1) {
+ if (blk_dread(desc, 0, 1, p_mbr) != 1) {
log_debug("** Can't read from device %d **\n",
- dev_desc->devnum);
+ desc->devnum);
return -EIO;
}
@@ -348,27 +354,26 @@
p_mbr->signature = MSDOS_MBR_SIGNATURE;
p_mbr->partition_record[0].sys_ind = EFI_PMBR_OSTYPE_EFI_GPT;
p_mbr->partition_record[0].start_sect = 1;
- p_mbr->partition_record[0].nr_sects = (u32) dev_desc->lba - 1;
+ p_mbr->partition_record[0].nr_sects = (u32)desc->lba - 1;
/* Write MBR sector to the MMC device */
- if (blk_dwrite(dev_desc, 0, 1, p_mbr) != 1) {
- log_debug("** Can't write to device %d **\n", dev_desc->devnum);
+ if (blk_dwrite(desc, 0, 1, p_mbr) != 1) {
+ log_debug("** Can't write to device %d **\n", desc->devnum);
return -EIO;
}
return 0;
}
-int write_gpt_table(struct blk_desc *dev_desc,
- gpt_header *gpt_h, gpt_entry *gpt_e)
+int write_gpt_table(struct blk_desc *desc, gpt_header *gpt_h, gpt_entry *gpt_e)
{
const int pte_blk_cnt = BLOCK_CNT((gpt_h->num_partition_entries
- * sizeof(gpt_entry)), dev_desc);
+ * sizeof(gpt_entry)), desc);
u32 calc_crc32;
- debug("max lba: %x\n", (u32) dev_desc->lba);
+ debug("max lba: %x\n", (u32)desc->lba);
/* Setup the Protective MBR */
- if (set_protective_mbr(dev_desc) < 0)
+ if (set_protective_mbr(desc) < 0)
goto err;
/* Generate CRC for the Primary GPT Header */
@@ -382,20 +387,20 @@
gpt_h->header_crc32 = cpu_to_le32(calc_crc32);
/* Write the First GPT to the block right after the Legacy MBR */
- if (blk_dwrite(dev_desc, 1, 1, gpt_h) != 1)
+ if (blk_dwrite(desc, 1, 1, gpt_h) != 1)
goto err;
- if (blk_dwrite(dev_desc, le64_to_cpu(gpt_h->partition_entry_lba),
+ if (blk_dwrite(desc, le64_to_cpu(gpt_h->partition_entry_lba),
pte_blk_cnt, gpt_e) != pte_blk_cnt)
goto err;
prepare_backup_gpt_header(gpt_h);
- if (blk_dwrite(dev_desc, (lbaint_t)le64_to_cpu(gpt_h->last_usable_lba)
+ if (blk_dwrite(desc, (lbaint_t)le64_to_cpu(gpt_h->last_usable_lba)
+ 1, pte_blk_cnt, gpt_e) != pte_blk_cnt)
goto err;
- if (blk_dwrite(dev_desc, (lbaint_t)le64_to_cpu(gpt_h->my_lba), 1,
+ if (blk_dwrite(desc, (lbaint_t)le64_to_cpu(gpt_h->my_lba), 1,
gpt_h) != 1)
goto err;
@@ -403,11 +408,11 @@
return 0;
err:
- log_debug("** Can't write to device %d **\n", dev_desc->devnum);
+ log_debug("** Can't write to device %d **\n", desc->devnum);
return -EIO;
}
-int gpt_fill_pte(struct blk_desc *dev_desc,
+int gpt_fill_pte(struct blk_desc *desc,
gpt_header *gpt_h, gpt_entry *gpt_e,
struct disk_partition *partitions, int parts)
{
@@ -416,10 +421,7 @@
le64_to_cpu(gpt_h->last_usable_lba);
int i, k;
size_t efiname_len, dosname_len;
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- char *str_uuid;
unsigned char *bin_uuid;
-#endif
#ifdef CONFIG_PARTITION_TYPE_GUID
char *str_type_guid;
unsigned char *bin_type_guid;
@@ -430,7 +432,7 @@
size_t pte_start = gpt_h->partition_entry_lba;
size_t pte_end = pte_start +
gpt_h->num_partition_entries * gpt_h->sizeof_partition_entry /
- dev_desc->blksz;
+ desc->blksz;
for (i = 0; i < parts; i++) {
/* partition starting lba */
@@ -488,16 +490,19 @@
&partition_basic_data_guid, 16);
#endif
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- str_uuid = partitions[i].uuid;
- bin_uuid = gpt_e[i].unique_partition_guid.b;
+ if (CONFIG_IS_ENABLED(PARTITION_UUIDS)) {
+ const char *str_uuid;
- if (uuid_str_to_bin(str_uuid, bin_uuid, UUID_STR_FORMAT_GUID)) {
- log_debug("Partition no. %d: invalid guid: %s\n",
- i, str_uuid);
- return -EINVAL;
+ str_uuid = disk_partition_uuid(&partitions[i]);
+ bin_uuid = gpt_e[i].unique_partition_guid.b;
+
+ if (uuid_str_to_bin(str_uuid, bin_uuid,
+ UUID_STR_FORMAT_GUID)) {
+ log_debug("Partition no. %d: invalid guid: %s\n",
+ i, str_uuid);
+ return -EINVAL;
+ }
}
-#endif
/* partition attributes */
memset(&gpt_e[i].attributes, 0,
@@ -527,7 +532,7 @@
return 0;
}
-static uint32_t partition_entries_offset(struct blk_desc *dev_desc)
+static uint32_t partition_entries_offset(struct blk_desc *desc)
{
uint32_t offset_blks = 2;
uint32_t __maybe_unused offset_bytes;
@@ -543,8 +548,8 @@
* CONFIG_EFI_PARTITION_ENTRIES_OFF.
*/
offset_bytes =
- PAD_TO_BLOCKSIZE(CONFIG_EFI_PARTITION_ENTRIES_OFF, dev_desc);
- offset_blks = offset_bytes / dev_desc->blksz;
+ PAD_TO_BLOCKSIZE(CONFIG_EFI_PARTITION_ENTRIES_OFF, desc);
+ offset_blks = offset_bytes / desc->blksz;
#endif
#if defined(CONFIG_OF_CONTROL)
@@ -556,8 +561,8 @@
config_offset = ofnode_conf_read_int(
"u-boot,efi-partition-entries-offset", -EINVAL);
if (config_offset != -EINVAL) {
- offset_bytes = PAD_TO_BLOCKSIZE(config_offset, dev_desc);
- offset_blks = offset_bytes / dev_desc->blksz;
+ offset_bytes = PAD_TO_BLOCKSIZE(config_offset, desc);
+ offset_blks = offset_bytes / desc->blksz;
}
#endif
@@ -573,17 +578,17 @@
return offset_blks;
}
-int gpt_fill_header(struct blk_desc *dev_desc, gpt_header *gpt_h,
- char *str_guid, int parts_count)
+int gpt_fill_header(struct blk_desc *desc, gpt_header *gpt_h, char *str_guid,
+ int parts_count)
{
gpt_h->signature = cpu_to_le64(GPT_HEADER_SIGNATURE_UBOOT);
gpt_h->revision = cpu_to_le32(GPT_HEADER_REVISION_V1);
gpt_h->header_size = cpu_to_le32(sizeof(gpt_header));
gpt_h->my_lba = cpu_to_le64(1);
- gpt_h->alternate_lba = cpu_to_le64(dev_desc->lba - 1);
- gpt_h->last_usable_lba = cpu_to_le64(dev_desc->lba - 34);
+ gpt_h->alternate_lba = cpu_to_le64(desc->lba - 1);
+ gpt_h->last_usable_lba = cpu_to_le64(desc->lba - 34);
gpt_h->partition_entry_lba =
- cpu_to_le64(partition_entries_offset(dev_desc));
+ cpu_to_le64(partition_entries_offset(desc));
gpt_h->first_usable_lba =
cpu_to_le64(le64_to_cpu(gpt_h->partition_entry_lba) + 32);
gpt_h->num_partition_entries = cpu_to_le32(GPT_ENTRY_NUMBERS);
@@ -597,14 +602,14 @@
return 0;
}
-int gpt_restore(struct blk_desc *dev_desc, char *str_disk_guid,
+int gpt_restore(struct blk_desc *desc, char *str_disk_guid,
struct disk_partition *partitions, int parts_count)
{
gpt_header *gpt_h;
gpt_entry *gpt_e;
int ret, size;
- size = PAD_TO_BLOCKSIZE(sizeof(gpt_header), dev_desc);
+ size = PAD_TO_BLOCKSIZE(sizeof(gpt_header), desc);
gpt_h = malloc_cache_aligned(size);
if (gpt_h == NULL) {
log_debug("calloc failed!\n");
@@ -613,7 +618,7 @@
memset(gpt_h, 0, size);
size = PAD_TO_BLOCKSIZE(GPT_ENTRY_NUMBERS * sizeof(gpt_entry),
- dev_desc);
+ desc);
gpt_e = malloc_cache_aligned(size);
if (gpt_e == NULL) {
log_debug("calloc failed!\n");
@@ -623,17 +628,17 @@
memset(gpt_e, 0, size);
/* Generate Primary GPT header (LBA1) */
- ret = gpt_fill_header(dev_desc, gpt_h, str_disk_guid, parts_count);
+ ret = gpt_fill_header(desc, gpt_h, str_disk_guid, parts_count);
if (ret)
goto err;
/* Generate partition entries */
- ret = gpt_fill_pte(dev_desc, gpt_h, gpt_e, partitions, parts_count);
+ ret = gpt_fill_pte(desc, gpt_h, gpt_e, partitions, parts_count);
if (ret)
goto err;
/* Write GPT partition table */
- ret = write_gpt_table(dev_desc, gpt_h, gpt_e);
+ ret = write_gpt_table(desc, gpt_h, gpt_e);
err:
free(gpt_e);
@@ -664,14 +669,14 @@
}
}
-int gpt_verify_headers(struct blk_desc *dev_desc, gpt_header *gpt_head,
+int gpt_verify_headers(struct blk_desc *desc, gpt_header *gpt_head,
gpt_entry **gpt_pte)
{
/*
* This function validates AND
* fills in the GPT header and PTE
*/
- if (is_gpt_valid(dev_desc,
+ if (is_gpt_valid(desc,
GPT_PRIMARY_PARTITION_TABLE_LBA,
gpt_head, gpt_pte) != 1) {
log_debug("Invalid GPT\n");
@@ -684,12 +689,12 @@
/*
* Check that the alternate_lba entry points to the last LBA
*/
- if (le64_to_cpu(gpt_head->alternate_lba) != (dev_desc->lba - 1)) {
+ if (le64_to_cpu(gpt_head->alternate_lba) != (desc->lba - 1)) {
log_debug("Misplaced Backup GPT\n");
return -1;
}
- if (is_gpt_valid(dev_desc, (dev_desc->lba - 1),
+ if (is_gpt_valid(desc, (desc->lba - 1),
gpt_head, gpt_pte) != 1) {
log_debug("Invalid Backup GPT\n");
return -1;
@@ -698,7 +703,7 @@
return 0;
}
-static void restore_primary_gpt_header(gpt_header *gpt_h, struct blk_desc *dev_desc)
+static void restore_primary_gpt_header(gpt_header *gpt_h, struct blk_desc *desc)
{
u32 calc_crc32;
u64 val;
@@ -707,7 +712,7 @@
val = le64_to_cpu(gpt_h->my_lba);
gpt_h->my_lba = gpt_h->alternate_lba;
gpt_h->alternate_lba = cpu_to_le64(val);
- gpt_h->partition_entry_lba = cpu_to_le64(partition_entries_offset(dev_desc));
+ gpt_h->partition_entry_lba = cpu_to_le64(partition_entries_offset(desc));
gpt_h->header_crc32 = 0;
@@ -716,22 +721,22 @@
gpt_h->header_crc32 = cpu_to_le32(calc_crc32);
}
-static int write_one_gpt_table(struct blk_desc *dev_desc,
- gpt_header *gpt_h, gpt_entry *gpt_e)
+static int write_one_gpt_table(struct blk_desc *desc, gpt_header *gpt_h,
+ gpt_entry *gpt_e)
{
const int pte_blk_cnt = BLOCK_CNT((gpt_h->num_partition_entries
- * sizeof(gpt_entry)), dev_desc);
+ * sizeof(gpt_entry)), desc);
lbaint_t start;
int ret = 0;
start = le64_to_cpu(gpt_h->my_lba);
- if (blk_dwrite(dev_desc, start, 1, gpt_h) != 1) {
+ if (blk_dwrite(desc, start, 1, gpt_h) != 1) {
ret = -1;
goto out;
}
start = le64_to_cpu(gpt_h->partition_entry_lba);
- if (blk_dwrite(dev_desc, start, pte_blk_cnt, gpt_e) != pte_blk_cnt) {
+ if (blk_dwrite(desc, start, pte_blk_cnt, gpt_e) != pte_blk_cnt) {
ret = -1;
goto out;
}
@@ -740,17 +745,17 @@
return ret;
}
-int gpt_repair_headers(struct blk_desc *dev_desc)
+int gpt_repair_headers(struct blk_desc *desc)
{
- ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_h1, 1, dev_desc->blksz);
- ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_h2, 1, dev_desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_h1, 1, desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_h2, 1, desc->blksz);
gpt_entry *gpt_e1 = NULL, *gpt_e2 = NULL;
int is_gpt1_valid, is_gpt2_valid;
int ret = -1;
- is_gpt1_valid = is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
+ is_gpt1_valid = is_gpt_valid(desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
gpt_h1, &gpt_e1);
- is_gpt2_valid = is_gpt_valid(dev_desc, dev_desc->lba - 1,
+ is_gpt2_valid = is_gpt_valid(desc, desc->lba - 1,
gpt_h2, &gpt_e2);
if (is_gpt1_valid && is_gpt2_valid) {
@@ -760,13 +765,13 @@
if (is_gpt1_valid && !is_gpt2_valid) {
prepare_backup_gpt_header(gpt_h1);
- ret = write_one_gpt_table(dev_desc, gpt_h1, gpt_e1);
+ ret = write_one_gpt_table(desc, gpt_h1, gpt_e1);
goto out;
}
if (!is_gpt1_valid && is_gpt2_valid) {
- restore_primary_gpt_header(gpt_h2, dev_desc);
- ret = write_one_gpt_table(dev_desc, gpt_h2, gpt_e2);
+ restore_primary_gpt_header(gpt_h2, desc);
+ ret = write_one_gpt_table(desc, gpt_h2, gpt_e2);
goto out;
}
@@ -784,7 +789,7 @@
return ret;
}
-int gpt_verify_partitions(struct blk_desc *dev_desc,
+int gpt_verify_partitions(struct blk_desc *desc,
struct disk_partition *partitions, int parts,
gpt_header *gpt_head, gpt_entry **gpt_pte)
{
@@ -793,7 +798,7 @@
gpt_entry *gpt_e;
int ret, i;
- ret = gpt_verify_headers(dev_desc, gpt_head, gpt_pte);
+ ret = gpt_verify_headers(desc, gpt_head, gpt_pte);
if (ret)
return ret;
@@ -862,28 +867,27 @@
return 0;
}
-int is_valid_gpt_buf(struct blk_desc *dev_desc, void *buf)
+int is_valid_gpt_buf(struct blk_desc *desc, void *buf)
{
gpt_header *gpt_h;
gpt_entry *gpt_e;
/* determine start of GPT Header in the buffer */
- gpt_h = buf + (GPT_PRIMARY_PARTITION_TABLE_LBA *
- dev_desc->blksz);
+ gpt_h = buf + (GPT_PRIMARY_PARTITION_TABLE_LBA * desc->blksz);
if (validate_gpt_header(gpt_h, GPT_PRIMARY_PARTITION_TABLE_LBA,
- dev_desc->lba))
+ desc->lba))
return -1;
/* determine start of GPT Entries in the buffer */
gpt_e = buf + (le64_to_cpu(gpt_h->partition_entry_lba) *
- dev_desc->blksz);
+ desc->blksz);
if (validate_gpt_entries(gpt_h, gpt_e))
return -1;
return 0;
}
-int write_mbr_and_gpt_partitions(struct blk_desc *dev_desc, void *buf)
+int write_mbr_and_gpt_partitions(struct blk_desc *desc, void *buf)
{
gpt_header *gpt_h;
gpt_entry *gpt_e;
@@ -891,24 +895,22 @@
lbaint_t lba;
int cnt;
- if (is_valid_gpt_buf(dev_desc, buf))
+ if (is_valid_gpt_buf(desc, buf))
return -1;
/* determine start of GPT Header in the buffer */
- gpt_h = buf + (GPT_PRIMARY_PARTITION_TABLE_LBA *
- dev_desc->blksz);
+ gpt_h = buf + (GPT_PRIMARY_PARTITION_TABLE_LBA * desc->blksz);
/* determine start of GPT Entries in the buffer */
- gpt_e = buf + (le64_to_cpu(gpt_h->partition_entry_lba) *
- dev_desc->blksz);
+ gpt_e = buf + (le64_to_cpu(gpt_h->partition_entry_lba) * desc->blksz);
gpt_e_blk_cnt = BLOCK_CNT((le32_to_cpu(gpt_h->num_partition_entries) *
le32_to_cpu(gpt_h->sizeof_partition_entry)),
- dev_desc);
+ desc);
/* write MBR */
lba = 0; /* MBR is always at 0 */
cnt = 1; /* MBR (1 block) */
- if (blk_dwrite(dev_desc, lba, cnt, buf) != cnt) {
+ if (blk_dwrite(desc, lba, cnt, buf) != cnt) {
log_debug("failed writing '%s' (%d blks at 0x" LBAF ")\n",
"MBR", cnt, lba);
return 1;
@@ -917,7 +919,7 @@
/* write Primary GPT */
lba = GPT_PRIMARY_PARTITION_TABLE_LBA;
cnt = 1; /* GPT Header (1 block) */
- if (blk_dwrite(dev_desc, lba, cnt, gpt_h) != cnt) {
+ if (blk_dwrite(desc, lba, cnt, gpt_h) != cnt) {
log_debug("failed writing '%s' (%d blks at 0x" LBAF ")\n",
"Primary GPT Header", cnt, lba);
return 1;
@@ -925,7 +927,7 @@
lba = le64_to_cpu(gpt_h->partition_entry_lba);
cnt = gpt_e_blk_cnt;
- if (blk_dwrite(dev_desc, lba, cnt, gpt_e) != cnt) {
+ if (blk_dwrite(desc, lba, cnt, gpt_e) != cnt) {
log_debug("failed writing '%s' (%d blks at 0x" LBAF ")\n",
"Primary GPT Entries", cnt, lba);
return 1;
@@ -936,7 +938,7 @@
/* write Backup GPT */
lba = le64_to_cpu(gpt_h->partition_entry_lba);
cnt = gpt_e_blk_cnt;
- if (blk_dwrite(dev_desc, lba, cnt, gpt_e) != cnt) {
+ if (blk_dwrite(desc, lba, cnt, gpt_e) != cnt) {
log_debug("failed writing '%s' (%d blks at 0x" LBAF ")\n",
"Backup GPT Entries", cnt, lba);
return 1;
@@ -944,14 +946,14 @@
lba = le64_to_cpu(gpt_h->my_lba);
cnt = 1; /* GPT Header (1 block) */
- if (blk_dwrite(dev_desc, lba, cnt, gpt_h) != cnt) {
+ if (blk_dwrite(desc, lba, cnt, gpt_h) != cnt) {
log_debug("failed writing '%s' (%d blks at 0x" LBAF ")\n",
"Backup GPT Header", cnt, lba);
return 1;
}
/* Update the partition table entries*/
- part_init(dev_desc);
+ part_init(desc);
return 0;
}
@@ -978,17 +980,23 @@
/*
* is_pmbr_valid(): test Protective MBR for validity
*
+ * @mbr: Pointer to Master Boot-Record data
+ *
* Returns: 1 if PMBR is valid, 0 otherwise.
* Validity depends on two things:
* 1) MSDOS signature is in the last two bytes of the MBR
* 2) One partition of type 0xEE is found, checked by pmbr_part_valid()
*/
-static int is_pmbr_valid(legacy_mbr * mbr)
+static int is_pmbr_valid(legacy_mbr *mbr)
{
+ uint sig = le16_to_cpu(mbr->signature);
int i = 0;
- if (!mbr || le16_to_cpu(mbr->signature) != MSDOS_MBR_SIGNATURE)
+ if (sig != MSDOS_MBR_SIGNATURE) {
+ log_debug("Invalid signature %x\n", sig);
return 0;
+ }
+ log_debug("Signature %x valid\n", sig);
for (i = 0; i < 4; i++) {
if (pmbr_part_valid(&mbr->partition_record[i])) {
@@ -1008,25 +1016,25 @@
* Description: returns 1 if valid, 0 on error, 2 if ignored header
* If valid, returns pointers to PTEs.
*/
-static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba,
- gpt_header *pgpt_head, gpt_entry **pgpt_pte)
+static int is_gpt_valid(struct blk_desc *desc, u64 lba, gpt_header *pgpt_head,
+ gpt_entry **pgpt_pte)
{
/* Confirm valid arguments prior to allocation. */
- if (!dev_desc || !pgpt_head) {
+ if (!desc || !pgpt_head) {
log_debug("Invalid Argument(s)\n");
return 0;
}
- ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, mbr, 1, dev_desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, mbr, 1, desc->blksz);
/* Read MBR Header from device */
- if (blk_dread(dev_desc, 0, 1, (ulong *)mbr) != 1) {
+ if (blk_dread(desc, 0, 1, (ulong *)mbr) != 1) {
log_debug("Can't read MBR header\n");
return 0;
}
/* Read GPT Header from device */
- if (blk_dread(dev_desc, (lbaint_t)lba, 1, pgpt_head) != 1) {
+ if (blk_dread(desc, (lbaint_t)lba, 1, pgpt_head) != 1) {
log_debug("Can't read GPT header\n");
return 0;
}
@@ -1037,23 +1045,23 @@
return 2;
}
- if (validate_gpt_header(pgpt_head, (lbaint_t)lba, dev_desc->lba))
+ if (validate_gpt_header(pgpt_head, (lbaint_t)lba, desc->lba))
return 0;
- if (dev_desc->sig_type == SIG_TYPE_NONE) {
+ if (desc->sig_type == SIG_TYPE_NONE) {
efi_guid_t empty = {};
if (memcmp(&pgpt_head->disk_guid, &empty, sizeof(empty))) {
- dev_desc->sig_type = SIG_TYPE_GUID;
- memcpy(&dev_desc->guid_sig, &pgpt_head->disk_guid,
- sizeof(empty));
+ desc->sig_type = SIG_TYPE_GUID;
+ memcpy(&desc->guid_sig, &pgpt_head->disk_guid,
+ sizeof(empty));
} else if (mbr->unique_mbr_signature != 0) {
- dev_desc->sig_type = SIG_TYPE_MBR;
- dev_desc->mbr_sig = mbr->unique_mbr_signature;
+ desc->sig_type = SIG_TYPE_MBR;
+ desc->mbr_sig = mbr->unique_mbr_signature;
}
}
/* Read and allocate Partition Table Entries */
- *pgpt_pte = alloc_read_gpt_entries(dev_desc, pgpt_head);
+ *pgpt_pte = alloc_read_gpt_entries(desc, pgpt_head);
if (!*pgpt_pte)
return 0;
@@ -1075,20 +1083,20 @@
* Description: returns 1 if found a valid gpt, 0 on error.
* If valid, returns pointers to PTEs.
*/
-static int find_valid_gpt(struct blk_desc *dev_desc, gpt_header *gpt_head,
+static int find_valid_gpt(struct blk_desc *desc, gpt_header *gpt_head,
gpt_entry **pgpt_pte)
{
int r;
- r = is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA, gpt_head,
+ r = is_gpt_valid(desc, GPT_PRIMARY_PARTITION_TABLE_LBA, gpt_head,
pgpt_pte);
if (r != 1) {
if (r != 2)
log_debug("Invalid GPT\n");
- if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), gpt_head,
- pgpt_pte) != 1) {
+ if (is_gpt_valid(desc, desc->lba - 1, gpt_head, pgpt_pte)
+ != 1) {
log_debug("Invalid Backup GPT\n");
return 0;
}
@@ -1100,21 +1108,21 @@
/**
* alloc_read_gpt_entries(): reads partition entries from disk
- * @dev_desc
+ * @desc
* @gpt - GPT header
*
* Description: Returns ptes on success, NULL on error.
* Allocates space for PTEs based on information found in @gpt.
* Notes: remember to free pte when you're done!
*/
-static gpt_entry *alloc_read_gpt_entries(struct blk_desc *dev_desc,
+static gpt_entry *alloc_read_gpt_entries(struct blk_desc *desc,
gpt_header *pgpt_head)
{
size_t count = 0, blk_cnt;
lbaint_t blk;
gpt_entry *pte = NULL;
- if (!dev_desc || !pgpt_head) {
+ if (!desc || !pgpt_head) {
log_debug("Invalid Argument(s)\n");
return NULL;
}
@@ -1130,7 +1138,7 @@
/* Allocate memory for PTE, remember to FREE */
if (count != 0) {
pte = memalign(ARCH_DMA_MINALIGN,
- PAD_TO_BLOCKSIZE(count, dev_desc));
+ PAD_TO_BLOCKSIZE(count, desc));
}
if (count == 0 || pte == NULL) {
@@ -1141,8 +1149,8 @@
/* Read GPT Entries from device */
blk = le64_to_cpu(pgpt_head->partition_entry_lba);
- blk_cnt = BLOCK_CNT(count, dev_desc);
- if (blk_dread(dev_desc, blk, (lbaint_t)blk_cnt, pte) != blk_cnt) {
+ blk_cnt = BLOCK_CNT(count, desc);
+ if (blk_dread(desc, blk, (lbaint_t)blk_cnt, pte) != blk_cnt) {
log_debug("Can't read GPT Entries\n");
free(pte);
return NULL;
diff --git a/disk/part_iso.c b/disk/part_iso.c
index 4cd619b..6ac6d95 100644
--- a/disk/part_iso.c
+++ b/disk/part_iso.c
@@ -46,7 +46,7 @@
}
/* only boot records will be listed as valid partitions */
-int part_get_info_iso_verb(struct blk_desc *dev_desc, int part_num,
+int part_get_info_iso_verb(struct blk_desc *desc, int part_num,
struct disk_partition *info, int verb)
{
int i,offset,entry_num;
@@ -58,23 +58,23 @@
iso_val_entry_t *pve = (iso_val_entry_t *)tmpbuf;
iso_init_def_entry_t *pide;
- if ((dev_desc->blksz != CD_SECTSIZE) && (dev_desc->blksz != 512))
+ if (desc->blksz != CD_SECTSIZE && desc->blksz != 512)
return -1;
/* the first sector (sector 0x10) must be a primary volume desc */
blkaddr=PVD_OFFSET;
- if (iso_dread(dev_desc, PVD_OFFSET, 1, (ulong *)tmpbuf) != 1)
+ if (iso_dread(desc, PVD_OFFSET, 1, (ulong *)tmpbuf) != 1)
return -1;
if(ppr->desctype!=0x01) {
if(verb)
printf ("** First descriptor is NOT a primary desc on %d:%d **\n",
- dev_desc->devnum, part_num);
+ desc->devnum, part_num);
return (-1);
}
if(strncmp((char *)ppr->stand_ident,"CD001",5)!=0) {
if(verb)
printf ("** Wrong ISO Ident: %s on %d:%d **\n",
- ppr->stand_ident, dev_desc->devnum, part_num);
+ ppr->stand_ident, desc->devnum, part_num);
return (-1);
}
lastsect = le32_to_cpu(ppr->firstsek_LEpathtab1_LE);
@@ -83,14 +83,14 @@
PRINTF(" Lastsect:%08lx\n",lastsect);
for(i=blkaddr;i<lastsect;i++) {
PRINTF("Reading block %d\n", i);
- if (iso_dread(dev_desc, i, 1, (ulong *)tmpbuf) != 1)
+ if (iso_dread(desc, i, 1, (ulong *)tmpbuf) != 1)
return -1;
if(ppr->desctype==0x00)
break; /* boot entry found */
if(ppr->desctype==0xff) {
if(verb)
printf ("** No valid boot catalog found on %d:%d **\n",
- dev_desc->devnum, part_num);
+ desc->devnum, part_num);
return (-1);
}
}
@@ -98,15 +98,15 @@
if(strncmp(pbr->ident_str,"EL TORITO SPECIFICATION",23)!=0) {
if(verb)
printf ("** Wrong El Torito ident: %s on %d:%d **\n",
- pbr->ident_str, dev_desc->devnum, part_num);
+ pbr->ident_str, desc->devnum, part_num);
return (-1);
}
bootaddr = get_unaligned_le32(pbr->pointer);
PRINTF(" Boot Entry at: %08lX\n",bootaddr);
- if (iso_dread(dev_desc, bootaddr, 1, (ulong *)tmpbuf) != 1) {
+ if (iso_dread(desc, bootaddr, 1, (ulong *)tmpbuf) != 1) {
if(verb)
printf ("** Can't read Boot Entry at %lX on %d:%d **\n",
- bootaddr, dev_desc->devnum, part_num);
+ bootaddr, desc->devnum, part_num);
return (-1);
}
chksum=0;
@@ -116,20 +116,20 @@
if(chksum!=0) {
if(verb)
printf("** Checksum Error in booting catalog validation entry on %d:%d **\n",
- dev_desc->devnum, part_num);
+ desc->devnum, part_num);
return (-1);
}
if((pve->key[0]!=0x55)||(pve->key[1]!=0xAA)) {
if(verb)
printf ("** Key 0x55 0xAA error on %d:%d **\n",
- dev_desc->devnum, part_num);
+ desc->devnum, part_num);
return(-1);
}
#ifdef CHECK_FOR_POWERPC_PLATTFORM
if(pve->platform!=0x01) {
if(verb)
printf ("** No PowerPC platform CD on %d:%d **\n",
- dev_desc->devnum, part_num);
+ desc->devnum, part_num);
return(-1);
}
#endif
@@ -137,7 +137,7 @@
entry_num=1;
offset=0x20;
strcpy((char *)info->type, "U-Boot");
- part_set_generic_name(dev_desc, part_num, (char *)info->name);
+ part_set_generic_name(desc, part_num, (char *)info->name);
/* the bootcatalog (including validation Entry) is limited to 2048Bytes
* (63 boot entries + validation entry) */
while(offset<2048) {
@@ -159,7 +159,7 @@
else {
if(verb)
printf ("** Partition %d not found on device %d **\n",
- part_num, dev_desc->devnum);
+ part_num, desc->devnum);
return(-1);
}
}
@@ -167,13 +167,13 @@
* searched w/o succsess */
if(verb)
printf ("** Partition %d not found on device %d **\n",
- part_num, dev_desc->devnum);
+ part_num, desc->devnum);
return(-1);
found:
if(pide->boot_ind!=0x88) {
if(verb)
printf("** Partition %d is not bootable on device %d **\n",
- part_num, dev_desc->devnum);
+ part_num, desc->devnum);
return (-1);
}
switch(pide->boot_media) {
@@ -189,7 +189,7 @@
newblkaddr = get_unaligned_le32(pide->rel_block_addr);
info->start=newblkaddr;
- if (dev_desc->blksz == 512) {
+ if (desc->blksz == 512) {
info->size *= 4;
info->start *= 4;
info->blksz = 512;
@@ -199,20 +199,20 @@
return 0;
}
-static int part_get_info_iso(struct blk_desc *dev_desc, int part_num,
+static int part_get_info_iso(struct blk_desc *desc, int part_num,
struct disk_partition *info)
{
- return part_get_info_iso_verb(dev_desc, part_num, info, 0);
+ return part_get_info_iso_verb(desc, part_num, info, 0);
}
-static void part_print_iso(struct blk_desc *dev_desc)
+static void part_print_iso(struct blk_desc *desc)
{
struct disk_partition info;
int i;
- if (part_get_info_iso_verb(dev_desc, 1, &info, 0) == -1) {
+ if (part_get_info_iso_verb(desc, 1, &info, 0) == -1) {
printf("** No boot partition found on device %d **\n",
- dev_desc->devnum);
+ desc->devnum);
return;
}
printf("Part Start Sect x Size Type\n");
@@ -221,14 +221,14 @@
printf(" %2d %8" LBAFlength "u %8" LBAFlength "u %6ld %.32s\n",
i, info.start, info.size, info.blksz, info.type);
i++;
- } while (part_get_info_iso_verb(dev_desc, i, &info, 0) != -1);
+ } while (part_get_info_iso_verb(desc, i, &info, 0) != -1);
}
-static int part_test_iso(struct blk_desc *dev_desc)
+static int part_test_iso(struct blk_desc *desc)
{
struct disk_partition info;
- return part_get_info_iso_verb(dev_desc, 1, &info, 0);
+ return part_get_info_iso_verb(desc, 1, &info, 0);
}
U_BOOT_PART_TYPE(iso) = {
diff --git a/disk/part_mac.c b/disk/part_mac.c
index ae8263f..db5e203 100644
--- a/disk/part_mac.c
+++ b/disk/part_mac.c
@@ -31,21 +31,20 @@
#endif
-static int part_mac_read_ddb(struct blk_desc *dev_desc,
- mac_driver_desc_t *ddb_p);
-static int part_mac_read_pdb(struct blk_desc *dev_desc, int part,
+static int part_mac_read_ddb(struct blk_desc *desc, mac_driver_desc_t *ddb_p);
+static int part_mac_read_pdb(struct blk_desc *desc, int part,
mac_partition_t *pdb_p);
/*
* Test for a valid MAC partition
*/
-static int part_test_mac(struct blk_desc *dev_desc)
+static int part_test_mac(struct blk_desc *desc)
{
ALLOC_CACHE_ALIGN_BUFFER(mac_driver_desc_t, ddesc, 1);
ALLOC_CACHE_ALIGN_BUFFER(mac_partition_t, mpart, 1);
ulong i, n;
- if (part_mac_read_ddb (dev_desc, ddesc)) {
+ if (part_mac_read_ddb(desc, ddesc)) {
/*
* error reading Driver Descriptor Block,
* or no valid Signature
@@ -55,8 +54,8 @@
n = 1; /* assuming at least one partition */
for (i=1; i<=n; ++i) {
- if ((blk_dread(dev_desc, i, 1, (ulong *)mpart) != 1) ||
- (mpart->signature != MAC_PARTITION_MAGIC) ) {
+ if ((blk_dread(desc, i, 1, (ulong *)mpart) != 1) ||
+ mpart->signature != MAC_PARTITION_MAGIC) {
return (-1);
}
/* update partition count */
@@ -65,14 +64,14 @@
return (0);
}
-static void part_print_mac(struct blk_desc *dev_desc)
+static void part_print_mac(struct blk_desc *desc)
{
ulong i, n;
ALLOC_CACHE_ALIGN_BUFFER(mac_driver_desc_t, ddesc, 1);
ALLOC_CACHE_ALIGN_BUFFER(mac_partition_t, mpart, 1);
ldiv_t mb, gb;
- if (part_mac_read_ddb (dev_desc, ddesc)) {
+ if (part_mac_read_ddb(desc, ddesc)) {
/*
* error reading Driver Descriptor Block,
* or no valid Signature
@@ -110,15 +109,15 @@
char c;
printf ("%4ld: ", i);
- if (blk_dread(dev_desc, i, 1, (ulong *)mpart) != 1) {
+ if (blk_dread(desc, i, 1, (ulong *)mpart) != 1) {
printf ("** Can't read Partition Map on %d:%ld **\n",
- dev_desc->devnum, i);
+ desc->devnum, i);
return;
}
if (mpart->signature != MAC_PARTITION_MAGIC) {
printf("** Bad Signature on %d:%ld - expected 0x%04x, got 0x%04x\n",
- dev_desc->devnum, i, MAC_PARTITION_MAGIC,
+ desc->devnum, i, MAC_PARTITION_MAGIC,
mpart->signature);
return;
}
@@ -154,10 +153,9 @@
/*
* Read Device Descriptor Block
*/
-static int part_mac_read_ddb(struct blk_desc *dev_desc,
- mac_driver_desc_t *ddb_p)
+static int part_mac_read_ddb(struct blk_desc *desc, mac_driver_desc_t *ddb_p)
{
- if (blk_dread(dev_desc, 0, 1, (ulong *)ddb_p) != 1) {
+ if (blk_dread(desc, 0, 1, (ulong *)ddb_p) != 1) {
debug("** Can't read Driver Descriptor Block **\n");
return (-1);
}
@@ -171,7 +169,7 @@
/*
* Read Partition Descriptor Block
*/
-static int part_mac_read_pdb(struct blk_desc *dev_desc, int part,
+static int part_mac_read_pdb(struct blk_desc *desc, int part,
mac_partition_t *pdb_p)
{
int n = 1;
@@ -182,15 +180,15 @@
* partition 1 first since this is the only way to
* know how many partitions we have.
*/
- if (blk_dread(dev_desc, n, 1, (ulong *)pdb_p) != 1) {
- printf ("** Can't read Partition Map on %d:%d **\n",
- dev_desc->devnum, n);
+ if (blk_dread(desc, n, 1, (ulong *)pdb_p) != 1) {
+ printf("** Can't read Partition Map on %d:%d **\n",
+ desc->devnum, n);
return (-1);
}
if (pdb_p->signature != MAC_PARTITION_MAGIC) {
printf("** Bad Signature on %d:%d: expected 0x%04x, got 0x%04x\n",
- dev_desc->devnum, n, MAC_PARTITION_MAGIC,
+ desc->devnum, n, MAC_PARTITION_MAGIC,
pdb_p->signature);
return (-1);
}
@@ -199,10 +197,9 @@
return (0);
if ((part < 1) || (part > pdb_p->map_count)) {
- printf ("** Invalid partition %d:%d [%d:1...%d:%d only]\n",
- dev_desc->devnum, part,
- dev_desc->devnum,
- dev_desc->devnum, pdb_p->map_count);
+ printf("** Invalid partition %d:%d [%d:1...%d:%d only]\n",
+ desc->devnum, part, desc->devnum, desc->devnum,
+ pdb_p->map_count);
return (-1);
}
@@ -213,21 +210,19 @@
/* NOTREACHED */
}
-static int part_get_info_mac(struct blk_desc *dev_desc, int part,
- struct disk_partition *info)
+static int part_get_info_mac(struct blk_desc *desc, int part,
+ struct disk_partition *info)
{
ALLOC_CACHE_ALIGN_BUFFER(mac_driver_desc_t, ddesc, 1);
ALLOC_CACHE_ALIGN_BUFFER(mac_partition_t, mpart, 1);
- if (part_mac_read_ddb (dev_desc, ddesc)) {
- return (-1);
- }
+ if (part_mac_read_ddb(desc, ddesc))
+ return -1;
info->blksz = ddesc->blk_size;
- if (part_mac_read_pdb (dev_desc, part, mpart)) {
- return (-1);
- }
+ if (part_mac_read_pdb(desc, part, mpart))
+ return -1;
info->start = mpart->start_block;
info->size = mpart->block_count;
diff --git a/doc/README.POST b/doc/README.POST
index 1366f95..c614ea4 100644
--- a/doc/README.POST
+++ b/doc/README.POST
@@ -138,11 +138,6 @@
mode the test is executed in (power-on, normal, power-fail,
manual).
- o) void post_reloc(ulong offset);
-
- This routine will be called from board_init_r() and will
- relocate the POST test table.
-
o) int post_info(char *name);
This routine will print the list of all POST tests that can be
diff --git a/doc/README.davinci b/doc/README.davinci
index f368f99..ea81279 100644
--- a/doc/README.davinci
+++ b/doc/README.davinci
@@ -70,7 +70,7 @@
2) TI OMAP-L138 LCDK
http://focus.ti.com/docs/prod/folders/print/omap-l138.html
-http://www.ti.com/tool/TMDXLCDK138
+https://www.ti.com/tool/TMDXLCDK138
Davinci special defines
=======================
diff --git a/doc/README.omap3 b/doc/README.omap3
index 3a1ac81..d1e6be9 100644
--- a/doc/README.omap3
+++ b/doc/README.omap3
@@ -163,8 +163,8 @@
[1] OMAP3:
-http://www.ti.com/omap3 (high volume) and
-http://www.ti.com/omap35x (broad market)
+https://www.ti.com/omap3 (high volume) and
+https://www.ti.com/omap35x (broad market)
[2] OMAP3530 BeagleBoard:
diff --git a/doc/README.rmobile b/doc/README.rmobile
deleted file mode 100644
index 524d839..0000000
--- a/doc/README.rmobile
+++ /dev/null
@@ -1,99 +0,0 @@
-Summary
-=======
-
-This README is about U-Boot support for Renesas's ARM Cortex-A9 based RMOBILE[1]
-and Cortex-A9/A53/A57 based R-Car[2] family of SoCs. Renesas's RMOBILE/R-Car SoC
-family contains an ARM Cortex-A9/A53/A57.
-
-Currently the following boards are supported:
-
-| SoC | Board | defconfig
-|===============+========================================+===================
-| R8A73A0 | KMC KZM-A9-GT [3] | kzm9g_config
-| R8A7734 | Atmark-Techno Armadillo-800-EVA [4] | armadillo-800eva_config
-|===============+========================================+===================
-| R8A7790 H2 | Renesas Electronics Lager | lager_defconfig
-| | Renesas Electronics Stout | stout_defconfig
-|---------------+----------------------------------------+-------------------
-| R8A7791 M2-W | Renesas Electronics Koelsch | koelsch_defconfig
-| | Renesas Electronics Porter | porter_defconfig
-|---------------+----------------------------------------+-------------------
-| R8A7792 V2H | Renesas Electronics Blanche | blanche_defconfig
-|---------------+----------------------------------------+-------------------
-| R8A7793 M2-N | Renesas Electronics Gose | gose_defconfig
-|---------------+----------------------------------------+-------------------
-| R8A7794 E2 | Renesas Electronics Alt | alt_defconfig
-| | Renesas Electronics Silk | silk_defconfig
-|===============+========================================+===================
-| R8A7795 H3 | Renesas Electronics Salvator-XS ES2.0+ | r8a7795_salvator-x_defconfig
-| R8A7795 H3 | Renesas Electronics ULCB ES2.0+ | r8a7795_ulcb
-|---------------+----------------------------------------+-------------------
-| R8A7796 M3-W | Renesas Electronics Salvator-X | r8a7796_salvator-x_defconfig
-| R8A7796 M3-W | Renesas Electronics ULCB | r8a7796_ulcb
-|---------------+----------------------------------------+-------------------
-| R8A77965 M3-N | Renesas Electronics Salvator-XS | r8a77965_salvator-x_defconfig
-| R8A77965 M3-N | Renesas Electronics ULCB | r8a77965_ulcb
-|---------------+----------------------------------------+-------------------
-| R8A77970 V3M | Renesas Electronics Eagle | r8a77970_eagle_defconfig
-| R8A77970 V3M | Renesas Electronics V3MSK | r8a77970_v3msk_defconfig
-|---------------+----------------------------------------+-------------------
-| R8A77995 D3 | Renesas Electronics Draak | r8a77995_draak_defconfig
-'===============+========================================+===================
-
-Toolchain
-=========
-
-Either ARMv7 toolchain for 32bit Cortex-A9 systems or ARMv8 (aarch64)
-toolchain for 64bit Cortex-A53/A57 systems. Currently we compile the
-32bit systems with -march=armv5 to allow more compilers to work. (For
-U-Boot code this has no performance impact.)
-
-Currently, ELDK[5], Linaro[6], CodeSourcery[7] and Emdebian[8] supports
-ARMv7. Modern distributions also contain ARMv7 and ARMv8 crosstoolchains
-in their package feeds.
-
-Build
-=====
-
-Locate defconfig in the table above. Then apply standard build procedure:
-
- make <board>_defconfig
- make
-
- Note: Armadillo-800-EVA's U-Boot supports booting from SDcard only.
- Please see "B.2 Appendix B Boot Specifications" in hardware manual.
-
-Links
-=====
-
-[1] Renesas RMOBILE:
-
-http://am.renesas.com/products/soc/assp/mobile/r_mobile/index.jsp
-
-[2] Renesas R-Car:
-
-http://am.renesas.com/products/soc/assp/automotive/index.jsp
-
-[3] KZM-A9-GT
-
-http://www.kmckk.co.jp/kzma9-gt/index.html
-
-[4] Armadillo-800-EVA
-
-http://armadillo.atmark-techno.com/armadillo-800-EVA
-
-[5] ELDK
-
-http://www.denx.de/wiki/view/ELDK-5/WebHome#Section_1.6.
-
-[6] Linaro
-
-http://www.linaro.org/downloads/
-
-[7] CodeSourcey
-
-http://www.mentor.com/embedded-software/codesourcery
-
-[8] Emdebian
-
-http://www.emdebian.org/crosstools.html
diff --git a/doc/README.rockchip b/doc/README.rockchip
index 52b5140..84caff8 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -38,16 +38,8 @@
(or you can use another cross compiler if you prefer)
2. To build RK3308 board:
- - Get the rkbin
- => git clone https://github.com/rockchip-linux/rkbin.git
- - Compile U-Boot
- => cd /path/to/u-boot
- => export BL31=/path/to/rkbin/bin/rk33/rk3308_bl31_v2.22.elf
- => make roc-cc-rk3308_defconfig
- => make CROSS_COMPILE=aarch64-linux-gnu- all
- => ./tools/mkimage -n rk3308 -T rksd -d /path/to/rkbin/bin/rk33/rk3308_ddr_589MHz_uart2_m0_v1.26.bin idbloader.img
- => cat spl/u-boot-spl.bin >> idbloader.img
+ See doc/board/rockchip/rockchip.rst
3. To build RK3399 board:
diff --git a/doc/README.serial_dt_baud b/doc/README.serial_dt_baud
new file mode 100644
index 0000000..f8768d0
--- /dev/null
+++ b/doc/README.serial_dt_baud
@@ -0,0 +1,41 @@
+Fetch serial baudrate from DT
+-----------------------------
+
+To support fetching of baudrate from DT, the following is done:-
+
+The baudrate configured in Kconfig symbol CONFIG_BAUDRATE is taken by default by serial.
+If change of baudrate is required then the Kconfig symbol CONFIG_BAUDRATE needs to
+changed and U-Boot recompilation is required or the U-Boot environment needs to be updated.
+
+To avoid this, add support to fetch the baudrate directly from the device tree file and
+update the environment.
+
+The default environment stores the default baudrate value. When default baudrate and dtb
+baudrate are not same glitches are seen on the serial.
+So, the environment also needs to be updated with the dtb baudrate to avoid the glitches on
+the serial which is enabled by OF_SERIAL_BAUD.
+
+The Kconfig SPL_ENV_SUPPORT needs to be enabled to allow patching in SPL.
+
+The Kconfig DEFAULT_ENV_IS_RW which is enabled by OF_SERIAL_BAUD with making the environment
+writable.
+
+The ofnode_read_baud() function parses and fetches the baudrate value from the DT. This value
+is validated and updated to baudrate during serial init. Padding is added at the end of the
+default environment and the dt baudrate is updated with the latest value.
+
+Example:-
+
+The serial port options are of the form "bbbbpnf", where "bbbb" is the baud rate, "p" is parity ("n", "o", or "e"),
+"n" is number of bits, and "f" is flow control ("r" for RTS or omit it). Default is "115200n8".
+
+chosen {
+ bootargs = "earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/ram0 rw init_fatal_sh=1";
+ stdout-path = "serial0:115200n8";
+ };
+
+From the chosen node, stdout-path property is obtained as string.
+
+ stdout-path = "serial0:115200n8";
+
+The string is parsed to get the baudrate 115200. This string is converted to integer and updated to the environment.
diff --git a/doc/README.sha1 b/doc/README.sha1
deleted file mode 100644
index f178f37..0000000
--- a/doc/README.sha1
+++ /dev/null
@@ -1,58 +0,0 @@
-SHA1 usage:
------------
-
-In the U-Boot Image for the pcs440ep board is a SHA1 checksum integrated.
-This SHA1 sum is used, to check, if the U-Boot Image in Flash is not
-corrupted.
-
-The following command is available:
-
-=> help sha1
-sha1 address len [addr] calculate the SHA1 sum [save at addr]
- -p calculate the SHA1 sum from the U-Boot image in flash and print
- -c check the U-Boot image in flash
-
-"sha1 -p"
- calculates and prints the SHA1 sum, from the Image stored in Flash
-
-"sha1 -c"
- check, if the SHA1 sum from the Image stored in Flash is correct
-
-
-It is possible to calculate a SHA1 checksum from a memoryrange with:
-
-"sha1 address len"
-
-If you want to store a new Image in Flash for the pcs440ep board,
-which has no SHA1 sum, you can do the following:
-
-a) cp the new Image on a position in RAM (here 0x300000)
- (for this example we use the Image from Flash, stored at 0xfffa0000 and
- 0x60000 Bytes long)
-
-"cp.b fffa0000 300000 60000"
-
-b) Initialize the SHA1 sum in the Image with 0x00
- The SHA1 sum is stored in Flash at:
- CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + SHA1_SUM_POS
- for the pcs440ep Flash: 0xfffa0000 + 0x60000 + -0x20
- = 0xffffffe0
- for the example in RAM: 0x300000 + 0x60000 + -0x20
- = 0x35ffe0
-
- note: a SHA1 checksum is 20 bytes long.
-
-"mw.b 35ffe0 0 14"
-
-c) now calculate the SHA1 sum from the memoryrange and write
- the calculated checksum at the right place:
-
-"sha1 300000 60000 35ffe0"
-
-Now you have a U-Boot-Image for the pcs440ep board with the correct SHA1 sum.
-
-If you do a "buildman -k pcs440ep" or a "make all" to get the U-Boot image,
-which will be found in ../current/ipam390/ - the correct SHA1 sum will be
-automagically included in the U-Boot image.
-
-Heiko Schocher, 11 Jul 2007
diff --git a/doc/api/index.rst b/doc/api/index.rst
index 2f0218c..51b2013 100644
--- a/doc/api/index.rst
+++ b/doc/api/index.rst
@@ -12,6 +12,7 @@
efi
event
getopt
+ interrupt
linker_lists
lmb
logging
diff --git a/doc/api/interrupt.rst b/doc/api/interrupt.rst
new file mode 100644
index 0000000..5721231
--- /dev/null
+++ b/doc/api/interrupt.rst
@@ -0,0 +1,6 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Interrupt API
+=============
+
+.. kernel-doc:: include/interrupt.h
diff --git a/doc/arch/arm64.ffa.rst b/doc/arch/arm64.ffa.rst
index 4ecdc31..f966f8b 100644
--- a/doc/arch/arm64.ffa.rst
+++ b/doc/arch/arm64.ffa.rst
@@ -40,7 +40,7 @@
- Sandbox FF-A test cases.
FF-A and SMC specifications
--------------------------------------------
+---------------------------
The current implementation of the U-Boot FF-A support relies on
`FF-A v1.0 specification`_ and uses SMC32 calling convention which
@@ -56,12 +56,12 @@
The FF-A support uses 64-bit registers as per `SMC Calling Convention v1.2 specification`_.
Supported hardware
---------------------------------
+------------------
Aarch64 plaforms
Configuration
-----------------------
+-------------
CONFIG_ARM_FFA_TRANSPORT
Enables the FF-A support. Turn this on if you want to use FF-A
@@ -70,7 +70,7 @@
When using sandbox, the sandbox FF-A emulator and FF-A sandbox driver will be used.
FF-A ABIs under the hood
----------------------------------------
+------------------------
Invoking an FF-A ABI involves providing to the secure world/hypervisor the
expected arguments from the ABI.
@@ -89,7 +89,7 @@
This methodology applies to all the FF-A ABIs.
FF-A bus discovery on Arm 64-bit platforms
----------------------------------------------
+------------------------------------------
When CONFIG_ARM_FFA_TRANSPORT is enabled, the FF-A bus is considered as
an architecture feature and discovered using ARM_SMCCC_FEATURES mechanism.
@@ -136,7 +136,7 @@
and can be probed again if needed.
Requirements for clients
--------------------------------------
+------------------------
When using the FF-A bus with EFI, clients must query the SPs they are looking for
during EFI boot-time mode using the service UUID.
@@ -159,13 +159,13 @@
The calling convention between U-Boot and the secure world stays the same: SMC32.
Requirements for user drivers
--------------------------------------
+-----------------------------
Users who want to implement their custom FF-A device driver while reusing the FF-A Uclass can do so
by implementing their own invoke_ffa_fn() in the user driver.
The bus driver layer
-------------------------------
+--------------------
FF-A support comes on top of the SMCCC layer and is implemented by the FF-A Uclass drivers/firmware/arm-ffa/arm-ffa-uclass.c
@@ -210,7 +210,7 @@
- FF-A bus can be compiled and used without EFI
Relationship between the sandbox emulator and the FF-A device
----------------------------------------------------------------
+-------------------------------------------------------------
::
@@ -222,7 +222,7 @@
ffa 0 [ ] sandbox_arm_ffa `-- sandbox-arm-ffa
The armffa command
------------------------------------
+------------------
armffa is a command showcasing how to use the FF-A bus and how to invoke the driver operations.
diff --git a/doc/arch/index.rst b/doc/arch/index.rst
index 2f916f4..60c93b3 100644
--- a/doc/arch/index.rst
+++ b/doc/arch/index.rst
@@ -15,5 +15,5 @@
riscv
sandbox/index
sh
- x86
+ x86/index
xtensa
diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst
index a3631de..5f8db12 100644
--- a/doc/arch/sandbox/sandbox.rst
+++ b/doc/arch/sandbox/sandbox.rst
@@ -424,15 +424,59 @@
VPL (Verifying Program Loader)
------------------------------
-Sandbox provides an example build of vpl called `sandbox_vpl`. This can be run
-using::
+Sandbox provides an example build of vpl called `sandbox_vpl`. To build it:
- /path/to/sandbox_vpl/tpl/u-boot-tpl -D
+.. code-block:: bash
+
+ make sandbox_vpl_defconfig all
+
+This can be run using:
+
+.. code-block:: bash
+
+ ./tpl/u-boot-tpl -d u-boot.dtb
It starts up TPL (first-stage init), then VPL, then runs SPL and finally U-Boot
proper, following the normal flow for a verified boot. At present, no
verification is actually implemented.
+Here is an example trace::
+
+ U-Boot TPL 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700)
+ Trying to boot from sandbox_image
+ Trying to boot from sandbox_file
+
+ U-Boot VPL 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700)
+ Trying to boot from vbe_simple
+ Trying to boot from sandbox_image
+ Trying to boot from sandbox_file
+
+ U-Boot SPL 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700)
+ Trying to boot from vbe_simple
+ Trying to boot from sandbox_image
+ Trying to boot from sandbox_file
+
+
+ U-Boot 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700)
+
+ Reset Status: COLD
+ Model: sandbox
+ DRAM: 256 MiB
+ using memory 0x1b576000-0x1f578000 for malloc()
+
+ Warning: host_lo MAC addresses don't match:
+ Address in ROM is 96:cd:ef:82:78:51
+ Address in environment is 02:00:11:22:33:44
+ Core: 103 devices, 51 uclasses, devicetree: board
+ MMC:
+ Loading Environment from nowhere... OK
+ In: serial,cros-ec-keyb,usbkbd
+ Out: serial,vidconsole
+ Err: serial,vidconsole
+ Model: sandbox
+ Net: eth0: host_lo, eth1: host_enp14s0, eth2: host_eth6, eth3: host_wlp15s0, eth4: host_virbr0, eth5: host_docker0, eth6: eth@10002000
+ Hit any key to stop autoboot: 1
+
Debugging the init sequence
---------------------------
@@ -614,8 +658,8 @@
======= ======================== ===============================
Addr Config Usage
======= ======================== ===============================
- 0 CONFIG_SYS_FDT_LOAD_ADDR Device tree
- c000 CONFIG_BLOBLIST_ADDR Blob list
+ 100 CONFIG_SYS_FDT_LOAD_ADDR Device tree
+ b000 CONFIG_BLOBLIST_ADDR Blob list
10000 CFG_MALLOC_F_ADDR Early memory allocation
f0000 CONFIG_PRE_CON_BUF_ADDR Pre-console buffer
100000 CONFIG_TRACE_EARLY_ADDR Early trace buffer (if enabled). Also used
diff --git a/doc/arch/x86/index.rst b/doc/arch/x86/index.rst
new file mode 100644
index 0000000..69db0a5
--- /dev/null
+++ b/doc/arch/x86/index.rst
@@ -0,0 +1,12 @@
+.. SPDX-License-Identifier: GPL-2.0+ */
+.. Copyright 2023 Google LLC
+.. sectionauthor:: Simon Glass <sjg@chromium.org>
+
+x86
+===
+
+.. toctree::
+ :maxdepth: 2
+
+ x86
+ manual_boot
diff --git a/doc/arch/x86/manual_boot.rst b/doc/arch/x86/manual_boot.rst
new file mode 100644
index 0000000..ec069f2
--- /dev/null
+++ b/doc/arch/x86/manual_boot.rst
@@ -0,0 +1,276 @@
+Booting Ubuntu Manually
+-----------------------
+
+This shows a manual approach to booting Ubuntu without standard boot or the EFI
+interface.
+
+As an example of how to set up your boot flow with U-Boot, here are
+instructions for starting Ubuntu from U-Boot. These instructions have been
+tested on Minnowboard MAX with a SATA drive but are equally applicable on
+other platforms and other media. There are really only four steps and it's a
+very simple script, but a more detailed explanation is provided here for
+completeness.
+
+Note: It is possible to set up U-Boot to boot automatically using syslinux.
+It could also use the grub.cfg file (/efi/ubuntu/grub.cfg) to obtain the
+GUID. If you figure these out, please post patches to this README.
+
+Firstly, you will need Ubuntu installed on an available disk. It should be
+possible to make U-Boot start a USB start-up disk but for now let's assume
+that you used another boot loader to install Ubuntu.
+
+Use the U-Boot command line to find the UUID of the partition you want to
+boot. For example our disk is SCSI device 0::
+
+ => part list scsi 0
+
+ Partition Map for SCSI device 0 -- Partition Type: EFI
+
+ Part Start LBA End LBA Name
+ Attributes
+ Type GUID
+ Partition GUID
+ 1 0x00000800 0x001007ff ""
+ attrs: 0x0000000000000000
+ type: c12a7328-f81f-11d2-ba4b-00a0c93ec93b
+ guid: 9d02e8e4-4d59-408f-a9b0-fd497bc9291c
+ 2 0x00100800 0x037d8fff ""
+ attrs: 0x0000000000000000
+ type: 0fc63daf-8483-4772-8e79-3d69d8477de4
+ guid: 965c59ee-1822-4326-90d2-b02446050059
+ 3 0x037d9000 0x03ba27ff ""
+ attrs: 0x0000000000000000
+ type: 0657fd6d-a4ab-43c4-84e5-0933c84b4f4f
+ guid: 2c4282bd-1e82-4bcf-a5ff-51dedbf39f17
+ =>
+
+This shows that your SCSI disk has three partitions. The really long hex
+strings are called Globally Unique Identifiers (GUIDs). You can look up the
+'type' ones `here`_. On this disk the first partition is for EFI and is in
+VFAT format (DOS/Windows)::
+
+ => fatls scsi 0:1
+ efi/
+
+ 0 file(s), 1 dir(s)
+
+
+Partition 2 is 'Linux filesystem data' so that will be our root disk. It is
+in ext2 format::
+
+ => ext2ls scsi 0:2
+ <DIR> 4096 .
+ <DIR> 4096 ..
+ <DIR> 16384 lost+found
+ <DIR> 4096 boot
+ <DIR> 12288 etc
+ <DIR> 4096 media
+ <DIR> 4096 bin
+ <DIR> 4096 dev
+ <DIR> 4096 home
+ <DIR> 4096 lib
+ <DIR> 4096 lib64
+ <DIR> 4096 mnt
+ <DIR> 4096 opt
+ <DIR> 4096 proc
+ <DIR> 4096 root
+ <DIR> 4096 run
+ <DIR> 12288 sbin
+ <DIR> 4096 srv
+ <DIR> 4096 sys
+ <DIR> 4096 tmp
+ <DIR> 4096 usr
+ <DIR> 4096 var
+ <SYM> 33 initrd.img
+ <SYM> 30 vmlinuz
+ <DIR> 4096 cdrom
+ <SYM> 33 initrd.img.old
+ =>
+
+and if you look in the /boot directory you will see the kernel::
+
+ => ext2ls scsi 0:2 /boot
+ <DIR> 4096 .
+ <DIR> 4096 ..
+ <DIR> 4096 efi
+ <DIR> 4096 grub
+ 3381262 System.map-3.13.0-32-generic
+ 1162712 abi-3.13.0-32-generic
+ 165611 config-3.13.0-32-generic
+ 176500 memtest86+.bin
+ 178176 memtest86+.elf
+ 178680 memtest86+_multiboot.bin
+ 5798112 vmlinuz-3.13.0-32-generic
+ 165762 config-3.13.0-58-generic
+ 1165129 abi-3.13.0-58-generic
+ 5823136 vmlinuz-3.13.0-58-generic
+ 19215259 initrd.img-3.13.0-58-generic
+ 3391763 System.map-3.13.0-58-generic
+ 5825048 vmlinuz-3.13.0-58-generic.efi.signed
+ 28304443 initrd.img-3.13.0-32-generic
+ =>
+
+The 'vmlinuz' files contain a packaged Linux kernel. The format is a kind of
+self-extracting compressed file mixed with some 'setup' configuration data.
+Despite its size (uncompressed it is >10MB) this only includes a basic set of
+device drivers, enough to boot on most hardware types.
+
+The 'initrd' files contain a RAM disk. This is something that can be loaded
+into RAM and will appear to Linux like a disk. Ubuntu uses this to hold lots
+of drivers for whatever hardware you might have. It is loaded before the
+real root disk is accessed.
+
+The numbers after the end of each file are the version. Here it is Linux
+version 3.13. You can find the source code for this in the Linux tree with
+the tag v3.13. The '.0' allows for additional Linux releases to fix problems,
+but normally this is not needed. The '-58' is used by Ubuntu. Each time they
+release a new kernel they increment this number. New Ubuntu versions might
+include kernel patches to fix reported bugs. Stable kernels can exist for
+some years so this number can get quite high.
+
+The '.efi.signed' kernel is signed for EFI's secure boot. U-Boot has its own
+secure boot mechanism - see `this`_ & `that`_. It cannot read .efi files
+at present.
+
+To boot Ubuntu from U-Boot the steps are as follows:
+
+1. Set up the boot arguments. Use the GUID for the partition you want to boot::
+
+ => setenv bootargs root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro
+
+Here root= tells Linux the location of its root disk. The disk is specified
+by its GUID, using '/dev/disk/by-partuuid/', a Linux path to a 'directory'
+containing all the GUIDs Linux has found. When it starts up, there will be a
+file in that directory with this name in it. It is also possible to use a
+device name here, see later.
+
+2. Load the kernel. Since it is an ext2/4 filesystem we can do::
+
+ => ext2load scsi 0:2 03000000 /boot/vmlinuz-3.13.0-58-generic
+
+The address 30000000 is arbitrary, but there seem to be problems with using
+small addresses (sometimes Linux cannot find the ramdisk). This is 48MB into
+the start of RAM (which is at 0 on x86).
+
+3. Load the ramdisk (to 64MB)::
+
+ => ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic
+
+4. Start up the kernel. We need to know the size of the ramdisk, but can use
+ a variable for that. U-Boot sets 'filesize' to the size of the last file it
+ loaded::
+
+ => zboot 03000000 0 04000000 ${filesize}
+
+Type 'help zboot' if you want to see what the arguments are. U-Boot on x86 is
+quite verbose when it boots a kernel. You should see these messages from
+U-Boot::
+
+ Valid Boot Flag
+ Setup Size = 0x00004400
+ Magic signature found
+ Using boot protocol version 2.0c
+ Linux kernel version 3.13.0-58-generic (buildd@allspice) #97-Ubuntu SMP Wed Jul 8 02:56:15 UTC 2015
+ Building boot_params at 0x00090000
+ Loading bzImage at address 100000 (5805728 bytes)
+ Magic signature found
+ Initial RAM disk at linear address 0x04000000, size 19215259 bytes
+ Kernel command line: "root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro"
+
+ Starting kernel ...
+
+U-Boot prints out some bootstage timing. This is more useful if you put the
+above commands into a script since then it will be faster::
+
+ Timer summary in microseconds:
+ Mark Elapsed Stage
+ 0 0 reset
+ 241,535 241,535 board_init_r
+ 2,421,611 2,180,076 id=64
+ 2,421,790 179 id=65
+ 2,428,215 6,425 main_loop
+ 48,860,584 46,432,369 start_kernel
+
+ Accumulated time:
+ 240,329 ahci
+ 1,422,704 vesa display
+
+Now the kernel actually starts (if you want to examine kernel boot up message on
+the serial console, append "console=ttyS0,115200" to the kernel command line)::
+
+ [ 0.000000] Initializing cgroup subsys cpuset
+ [ 0.000000] Initializing cgroup subsys cpu
+ [ 0.000000] Initializing cgroup subsys cpuacct
+ [ 0.000000] Linux version 3.13.0-58-generic (buildd@allspice) (gcc version 4.8.2 (Ubuntu 4.8.2-19ubuntu1) ) #97-Ubuntu SMP Wed Jul 8 02:56:15 UTC 2015 (Ubuntu 3.13.0-58.97-generic 3.13.11-ckt22)
+ [ 0.000000] Command line: root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro console=ttyS0,115200
+
+It continues for a long time. Along the way you will see it pick up your
+ramdisk::
+
+ [ 0.000000] RAMDISK: [mem 0x04000000-0x05253fff]
+ ...
+ [ 0.788540] Trying to unpack rootfs image as initramfs...
+ [ 1.540111] Freeing initrd memory: 18768K (ffff880004000000 - ffff880005254000)
+ ...
+
+Later it actually starts using it::
+
+ Begin: Running /scripts/local-premount ... done.
+
+You should also see your boot disk turn up::
+
+ [ 4.357243] scsi 1:0:0:0: Direct-Access ATA ADATA SP310 5.2 PQ: 0 ANSI: 5
+ [ 4.366860] sd 1:0:0:0: [sda] 62533296 512-byte logical blocks: (32.0 GB/29.8 GiB)
+ [ 4.375677] sd 1:0:0:0: Attached scsi generic sg0 type 0
+ [ 4.381859] sd 1:0:0:0: [sda] Write Protect is off
+ [ 4.387452] sd 1:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
+ [ 4.399535] sda: sda1 sda2 sda3
+
+Linux has found the three partitions (sda1-3). Mercifully it doesn't print out
+the GUIDs. In step 1 above we could have used::
+
+ setenv bootargs root=/dev/sda2 ro
+
+instead of the GUID. However if you add another drive to your board the
+numbering may change whereas the GUIDs will not. So if your boot partition
+becomes sdb2, it will still boot. For embedded systems where you just want to
+boot the first disk, you have that option.
+
+The last thing you will see on the console is mention of plymouth (which
+displays the Ubuntu start-up screen) and a lot of 'Starting' messages::
+
+ * Starting Mount filesystems on boot [ OK ]
+
+After a pause you should see a login screen on your display and you are done.
+
+If you want to put this in a script you can use something like this::
+
+ setenv bootargs root=UUID=b2aaf743-0418-4d90-94cc-3e6108d7d968 ro
+ setenv boot zboot 03000000 0 04000000 \${filesize}
+ setenv bootcmd "ext2load scsi 0:2 03000000 /boot/vmlinuz-3.13.0-58-generic; ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic; run boot"
+ saveenv
+
+The \ is to tell the shell not to evaluate ${filesize} as part of the setenv
+command.
+
+You can also bake this behaviour into your build by hard-coding the
+environment variables if you add this to minnowmax.h:
+
+.. code-block:: c
+
+ #undef CONFIG_BOOTCOMMAND
+ #define CONFIG_BOOTCOMMAND \
+ "ext2load scsi 0:2 03000000 /boot/vmlinuz-3.13.0-58-generic; " \
+ "ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic; " \
+ "run boot"
+
+ #undef CFG_EXTRA_ENV_SETTINGS
+ #define CFG_EXTRA_ENV_SETTINGS "boot=zboot 03000000 0 04000000 ${filesize}"
+
+and change CONFIG_BOOTARGS value in configs/minnowmax_defconfig to::
+
+ CONFIG_BOOTARGS="root=/dev/sda2 ro"
+
+.. _here: https://en.wikipedia.org/wiki/GUID_Partition_Table
+.. _this: http://events.linuxfoundation.org/sites/events/files/slides/chromeos_and_diy_vboot_0.pdf
+.. _that: http://events.linuxfoundation.org/sites/events/files/slides/elce-2014.pdf
diff --git a/doc/arch/x86.rst b/doc/arch/x86/x86.rst
similarity index 64%
rename from doc/arch/x86.rst
rename to doc/arch/x86/x86.rst
index 725a1ae..f67216d 100644
--- a/doc/arch/x86.rst
+++ b/doc/arch/x86/x86.rst
@@ -11,9 +11,9 @@
Status
------
U-Boot supports running as a `coreboot`_ payload on x86. So far only Link
-(Chromebook Pixel) and `QEMU`_ x86 targets have been tested, but it should
-work with minimal adjustments on other x86 boards since coreboot deals with
-most of the low-level details.
+(Chromebook Pixel), Brya (Alder Lake Chromebook) and `QEMU`_ x86 targets have
+been tested, but it should work with minimal adjustments on other x86 boards
+since coreboot deals with most of the low-level details.
U-Boot is a main bootloader on Intel Edison board.
@@ -25,18 +25,21 @@
- Bayley Bay CRB
- Cherry Hill CRB
- Congatec QEVAL 2.0 & conga-QA3/E3845
+ - Coral (Apollo Lake - Chromebook 2017)
- Cougar Canyon 2 CRB
- Crown Bay CRB
- Galileo
- - Link (Chromebook Pixel)
+ - Link (Ivy Bridge - Chromebook Pixel)
- Minnowboard MAX
- - Samus (Chromebook Pixel 2015)
+ - Samus (Broadwell - Chromebook Pixel 2015)
+ - Coral (Apollo Lake Chromebooks circa 2017)
- QEMU x86 (32-bit & 64-bit)
As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit
Linux kernel as part of a FIT image. It also supports a compressed zImage.
U-Boot supports loading an x86 VxWorks kernel. Please check README.vxworks
-for more details.
+for more details. Finally, U-Boot can boot Linux distributions with a UEFI
+interface.
Build Instructions for U-Boot as BIOS replacement (bare mode)
-------------------------------------------------------------
@@ -95,272 +98,9 @@
Booting Ubuntu
--------------
-As an example of how to set up your boot flow with U-Boot, here are
-instructions for starting Ubuntu from U-Boot. These instructions have been
-tested on Minnowboard MAX with a SATA drive but are equally applicable on
-other platforms and other media. There are really only four steps and it's a
-very simple script, but a more detailed explanation is provided here for
-completeness.
-
-Note: It is possible to set up U-Boot to boot automatically using syslinux.
-It could also use the grub.cfg file (/efi/ubuntu/grub.cfg) to obtain the
-GUID. If you figure these out, please post patches to this README.
-
-Firstly, you will need Ubuntu installed on an available disk. It should be
-possible to make U-Boot start a USB start-up disk but for now let's assume
-that you used another boot loader to install Ubuntu.
-
-Use the U-Boot command line to find the UUID of the partition you want to
-boot. For example our disk is SCSI device 0::
-
- => part list scsi 0
-
- Partition Map for SCSI device 0 -- Partition Type: EFI
-
- Part Start LBA End LBA Name
- Attributes
- Type GUID
- Partition GUID
- 1 0x00000800 0x001007ff ""
- attrs: 0x0000000000000000
- type: c12a7328-f81f-11d2-ba4b-00a0c93ec93b
- guid: 9d02e8e4-4d59-408f-a9b0-fd497bc9291c
- 2 0x00100800 0x037d8fff ""
- attrs: 0x0000000000000000
- type: 0fc63daf-8483-4772-8e79-3d69d8477de4
- guid: 965c59ee-1822-4326-90d2-b02446050059
- 3 0x037d9000 0x03ba27ff ""
- attrs: 0x0000000000000000
- type: 0657fd6d-a4ab-43c4-84e5-0933c84b4f4f
- guid: 2c4282bd-1e82-4bcf-a5ff-51dedbf39f17
- =>
-
-This shows that your SCSI disk has three partitions. The really long hex
-strings are called Globally Unique Identifiers (GUIDs). You can look up the
-'type' ones `here`_. On this disk the first partition is for EFI and is in
-VFAT format (DOS/Windows)::
-
- => fatls scsi 0:1
- efi/
-
- 0 file(s), 1 dir(s)
-
-
-Partition 2 is 'Linux filesystem data' so that will be our root disk. It is
-in ext2 format::
-
- => ext2ls scsi 0:2
- <DIR> 4096 .
- <DIR> 4096 ..
- <DIR> 16384 lost+found
- <DIR> 4096 boot
- <DIR> 12288 etc
- <DIR> 4096 media
- <DIR> 4096 bin
- <DIR> 4096 dev
- <DIR> 4096 home
- <DIR> 4096 lib
- <DIR> 4096 lib64
- <DIR> 4096 mnt
- <DIR> 4096 opt
- <DIR> 4096 proc
- <DIR> 4096 root
- <DIR> 4096 run
- <DIR> 12288 sbin
- <DIR> 4096 srv
- <DIR> 4096 sys
- <DIR> 4096 tmp
- <DIR> 4096 usr
- <DIR> 4096 var
- <SYM> 33 initrd.img
- <SYM> 30 vmlinuz
- <DIR> 4096 cdrom
- <SYM> 33 initrd.img.old
- =>
-
-and if you look in the /boot directory you will see the kernel::
-
- => ext2ls scsi 0:2 /boot
- <DIR> 4096 .
- <DIR> 4096 ..
- <DIR> 4096 efi
- <DIR> 4096 grub
- 3381262 System.map-3.13.0-32-generic
- 1162712 abi-3.13.0-32-generic
- 165611 config-3.13.0-32-generic
- 176500 memtest86+.bin
- 178176 memtest86+.elf
- 178680 memtest86+_multiboot.bin
- 5798112 vmlinuz-3.13.0-32-generic
- 165762 config-3.13.0-58-generic
- 1165129 abi-3.13.0-58-generic
- 5823136 vmlinuz-3.13.0-58-generic
- 19215259 initrd.img-3.13.0-58-generic
- 3391763 System.map-3.13.0-58-generic
- 5825048 vmlinuz-3.13.0-58-generic.efi.signed
- 28304443 initrd.img-3.13.0-32-generic
- =>
-
-The 'vmlinuz' files contain a packaged Linux kernel. The format is a kind of
-self-extracting compressed file mixed with some 'setup' configuration data.
-Despite its size (uncompressed it is >10MB) this only includes a basic set of
-device drivers, enough to boot on most hardware types.
-
-The 'initrd' files contain a RAM disk. This is something that can be loaded
-into RAM and will appear to Linux like a disk. Ubuntu uses this to hold lots
-of drivers for whatever hardware you might have. It is loaded before the
-real root disk is accessed.
-
-The numbers after the end of each file are the version. Here it is Linux
-version 3.13. You can find the source code for this in the Linux tree with
-the tag v3.13. The '.0' allows for additional Linux releases to fix problems,
-but normally this is not needed. The '-58' is used by Ubuntu. Each time they
-release a new kernel they increment this number. New Ubuntu versions might
-include kernel patches to fix reported bugs. Stable kernels can exist for
-some years so this number can get quite high.
-
-The '.efi.signed' kernel is signed for EFI's secure boot. U-Boot has its own
-secure boot mechanism - see `this`_ & `that`_. It cannot read .efi files
-at present.
-
-To boot Ubuntu from U-Boot the steps are as follows:
-
-1. Set up the boot arguments. Use the GUID for the partition you want to boot::
-
- => setenv bootargs root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro
-
-Here root= tells Linux the location of its root disk. The disk is specified
-by its GUID, using '/dev/disk/by-partuuid/', a Linux path to a 'directory'
-containing all the GUIDs Linux has found. When it starts up, there will be a
-file in that directory with this name in it. It is also possible to use a
-device name here, see later.
-
-2. Load the kernel. Since it is an ext2/4 filesystem we can do::
-
- => ext2load scsi 0:2 03000000 /boot/vmlinuz-3.13.0-58-generic
-
-The address 30000000 is arbitrary, but there seem to be problems with using
-small addresses (sometimes Linux cannot find the ramdisk). This is 48MB into
-the start of RAM (which is at 0 on x86).
-
-3. Load the ramdisk (to 64MB)::
-
- => ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic
-
-4. Start up the kernel. We need to know the size of the ramdisk, but can use
- a variable for that. U-Boot sets 'filesize' to the size of the last file it
- loaded::
-
- => zboot 03000000 0 04000000 ${filesize}
-
-Type 'help zboot' if you want to see what the arguments are. U-Boot on x86 is
-quite verbose when it boots a kernel. You should see these messages from
-U-Boot::
-
- Valid Boot Flag
- Setup Size = 0x00004400
- Magic signature found
- Using boot protocol version 2.0c
- Linux kernel version 3.13.0-58-generic (buildd@allspice) #97-Ubuntu SMP Wed Jul 8 02:56:15 UTC 2015
- Building boot_params at 0x00090000
- Loading bzImage at address 100000 (5805728 bytes)
- Magic signature found
- Initial RAM disk at linear address 0x04000000, size 19215259 bytes
- Kernel command line: "root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro"
-
- Starting kernel ...
-
-U-Boot prints out some bootstage timing. This is more useful if you put the
-above commands into a script since then it will be faster::
-
- Timer summary in microseconds:
- Mark Elapsed Stage
- 0 0 reset
- 241,535 241,535 board_init_r
- 2,421,611 2,180,076 id=64
- 2,421,790 179 id=65
- 2,428,215 6,425 main_loop
- 48,860,584 46,432,369 start_kernel
-
- Accumulated time:
- 240,329 ahci
- 1,422,704 vesa display
-
-Now the kernel actually starts (if you want to examine kernel boot up message on
-the serial console, append "console=ttyS0,115200" to the kernel command line)::
-
- [ 0.000000] Initializing cgroup subsys cpuset
- [ 0.000000] Initializing cgroup subsys cpu
- [ 0.000000] Initializing cgroup subsys cpuacct
- [ 0.000000] Linux version 3.13.0-58-generic (buildd@allspice) (gcc version 4.8.2 (Ubuntu 4.8.2-19ubuntu1) ) #97-Ubuntu SMP Wed Jul 8 02:56:15 UTC 2015 (Ubuntu 3.13.0-58.97-generic 3.13.11-ckt22)
- [ 0.000000] Command line: root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro console=ttyS0,115200
-
-It continues for a long time. Along the way you will see it pick up your
-ramdisk::
-
- [ 0.000000] RAMDISK: [mem 0x04000000-0x05253fff]
- ...
- [ 0.788540] Trying to unpack rootfs image as initramfs...
- [ 1.540111] Freeing initrd memory: 18768K (ffff880004000000 - ffff880005254000)
- ...
-
-Later it actually starts using it::
-
- Begin: Running /scripts/local-premount ... done.
-
-You should also see your boot disk turn up::
-
- [ 4.357243] scsi 1:0:0:0: Direct-Access ATA ADATA SP310 5.2 PQ: 0 ANSI: 5
- [ 4.366860] sd 1:0:0:0: [sda] 62533296 512-byte logical blocks: (32.0 GB/29.8 GiB)
- [ 4.375677] sd 1:0:0:0: Attached scsi generic sg0 type 0
- [ 4.381859] sd 1:0:0:0: [sda] Write Protect is off
- [ 4.387452] sd 1:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
- [ 4.399535] sda: sda1 sda2 sda3
-
-Linux has found the three partitions (sda1-3). Mercifully it doesn't print out
-the GUIDs. In step 1 above we could have used::
-
- setenv bootargs root=/dev/sda2 ro
-
-instead of the GUID. However if you add another drive to your board the
-numbering may change whereas the GUIDs will not. So if your boot partition
-becomes sdb2, it will still boot. For embedded systems where you just want to
-boot the first disk, you have that option.
-
-The last thing you will see on the console is mention of plymouth (which
-displays the Ubuntu start-up screen) and a lot of 'Starting' messages::
-
- * Starting Mount filesystems on boot [ OK ]
-
-After a pause you should see a login screen on your display and you are done.
-
-If you want to put this in a script you can use something like this::
-
- setenv bootargs root=UUID=b2aaf743-0418-4d90-94cc-3e6108d7d968 ro
- setenv boot zboot 03000000 0 04000000 \${filesize}
- setenv bootcmd "ext2load scsi 0:2 03000000 /boot/vmlinuz-3.13.0-58-generic; ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic; run boot"
- saveenv
-
-The \ is to tell the shell not to evaluate ${filesize} as part of the setenv
-command.
-
-You can also bake this behaviour into your build by hard-coding the
-environment variables if you add this to minnowmax.h:
-
-.. code-block:: c
-
- #undef CONFIG_BOOTCOMMAND
- #define CONFIG_BOOTCOMMAND \
- "ext2load scsi 0:2 03000000 /boot/vmlinuz-3.13.0-58-generic; " \
- "ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic; " \
- "run boot"
-
- #undef CFG_EXTRA_ENV_SETTINGS
- #define CFG_EXTRA_ENV_SETTINGS "boot=zboot 03000000 0 04000000 ${filesize}"
-
-and change CONFIG_BOOTARGS value in configs/minnowmax_defconfig to::
-
- CONFIG_BOOTARGS="root=/dev/sda2 ro"
+Typically U-Boot boots distributions automatically so long an `CONFIG_BOOTSTD`,
+`CONFIG_BOOTSTD_DEFAULTS` and `CONFIG_EFI_LOADER` are enabled. See
+:doc:`manual_boot` for how to do this manually.
Test with SeaBIOS
-----------------
@@ -695,14 +435,15 @@
No controllers found
Hit any key to stop autoboot: 0
-See :doc:`../develop/uefi/u-boot_on_efi` and :doc:`../develop/uefi/uefi` for
-details of EFI support in U-Boot.
+See :doc:`../../develop/uefi/u-boot_on_efi` and :doc:`../../develop/uefi/uefi`
+for details of EFI support in U-Boot.
Chain-loading
-------------
-U-Boot can be chain-loaded from another bootloader, such as coreboot or
-Slim Bootloader. Typically this is done by building for targets 'coreboot' or
-'slimbootloader'.
+U-Boot can be chain-loaded from another bootloader, such as
+:doc:`../../board/coreboot/index` coreboot or
+:doc:`../../board/intel/slimbootloader`. Typically this is done by building for
+targets 'coreboot' or 'slimbootloader'.
For example, at present we have a 'coreboot' target but this runs very
different code from the bare-metal targets, such as coral. There is very little
@@ -732,7 +473,7 @@
To generate SMBIOS tables in U-Boot, for use by the OS, enable the
CONFIG_GENERATE_SMBIOS_TABLE option. The easiest way to provide the values to
use is via the device tree. For details see
-:download:`smbios.txt <../device-tree-bindings/sysinfo/smbios.txt>`.
+:download:`smbios.txt <../../device-tree-bindings/sysinfo/smbios.txt>`.
TODO List
---------
@@ -744,8 +485,5 @@
.. _microcode: http://en.wikipedia.org/wiki/Microcode
.. _SFI: http://simplefirmware.org
.. _MP: http://www.intel.com/design/archives/processors/pro/docs/242016.htm
-.. _here: https://en.wikipedia.org/wiki/GUID_Partition_Table
-.. _this: http://events.linuxfoundation.org/sites/events/files/slides/chromeos_and_diy_vboot_0.pdf
-.. _that: http://events.linuxfoundation.org/sites/events/files/slides/elce-2014.pdf
.. _SeaBIOS: http://www.seabios.org/SeaBIOS
.. _ACPI: http://www.acpi.info
diff --git a/doc/board/AndesTech/ae350.rst b/doc/board/AndesTech/ae350.rst
index 42a2b4d..99622fd 100644
--- a/doc/board/AndesTech/ae350.rst
+++ b/doc/board/AndesTech/ae350.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+
AE350
-======
+=====
AE350 is the mainline SoC produced by Andes Technology using AndesV5 CPU core
based on RISC-V architecture.
diff --git a/doc/board/actions/cubieboard7.rst b/doc/board/actions/cubieboard7.rst
index 74f2b12..1f73fc4 100644
--- a/doc/board/actions/cubieboard7.rst
+++ b/doc/board/actions/cubieboard7.rst
@@ -20,7 +20,7 @@
getting into u-boot prompt is easy.
Enter ADFU Mode
-----------------
+---------------
Before write the firmware, let the development board entering the ADFU mode: insert
one end of the USB cable to the PC, press and hold the ADFU button, and then connect
@@ -28,7 +28,7 @@
the ADFU button, after connecting it will enter the ADFU mode.
Check whether entered ADFU Mode
---------------------------------
+-------------------------------
The user needs to run the following command on the PC side to check if the ADFU
device is detected. ID realted to "Actions Semiconductor Co., Ltd" means that
diff --git a/doc/board/actions/index.rst b/doc/board/actions/index.rst
index c596879..e925fcd 100644
--- a/doc/board/actions/index.rst
+++ b/doc/board/actions/index.rst
@@ -2,7 +2,7 @@
.. Copyright (C) 2020 Amit Singh Tomar <amittomer25@gmail.com>
Actions
-========
+=======
.. toctree::
:maxdepth: 2
diff --git a/doc/board/allwinner/sunxi.rst b/doc/board/allwinner/sunxi.rst
index 797222d..d0c89b9 100644
--- a/doc/board/allwinner/sunxi.rst
+++ b/doc/board/allwinner/sunxi.rst
@@ -251,8 +251,7 @@
# apt-get install mtd-utils
# mtdinfo
- # mtd_debug erase /dev/mtdX 0 0xf0000
- # mtd_debug write /dev/mtdX 0 0xf0000 u-boot-sunxi-with-spl.bin
+ # flashcp -v u-boot-sunxi-with-spl.bin /dev/mtdX
``/dev/mtdX`` needs to be replaced with the respective device name, as listed
in the output of ``mtdinfo``.
diff --git a/doc/board/armltd/index.rst b/doc/board/armltd/index.rst
index fc1d75a..052a969 100644
--- a/doc/board/armltd/index.rst
+++ b/doc/board/armltd/index.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0
Arm Ltd
-=============
+=======
.. toctree::
:maxdepth: 2
diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst
index d660a22..10a251c 100644
--- a/doc/board/coreboot/coreboot.rst
+++ b/doc/board/coreboot/coreboot.rst
@@ -41,15 +41,56 @@
the video information correctly (it always says the resolution is 0x0). This
works correctly for link though.
+You can run via QEMU using::
+
+ qemu-system-x86_64 -bios build/coreboot.rom -serial mon:stdio
+
+The `-serial mon:stdio` part shows both output in the display and on the
+console. It is optional. You can add `nographic` as well to *only* get console
+output.
+
+To run with a SATA drive called `$DISK`::
+
+ qemu-system-x86_64 -bios build/coreboot.rom -serial mon:stdio \
+ -drive id=disk,file=$DISK,if=none \
+ -device ahci,id=ahci \
+ -device ide-hd,drive=disk,bus=ahci.0
+
+Then you can scan it with `scsi scan` and access it normally.
+
+To use 4GB of memory, typically necessary for booting Linux distros, add
+`-m 4GB`.
+
64-bit U-Boot
-------------
In addition to the 32-bit 'coreboot' build there is a 'coreboot64' build. This
produces an image which can be booted from coreboot (32-bit). Internally it
works by using a 32-bit SPL binary to switch to 64-bit for running U-Boot. It
-can be useful for running UEFI applications, for example.
+can be useful for running UEFI applications, for example with the coreboot
+build in `$CBDIR`::
-This has only been lightly tested.
+ DISK=ubuntu-23.04-desktop-amd64.iso
+ CBDIR=~/coreboot/build
+
+ cp $CBDIR/coreboot.rom.in coreboot.rom
+ cbfstool coreboot.rom add-flat-binary -f u-boot-x86-with-spl.bin \
+ -n fallback/payload -c lzma -l 0x1110000 -e 0x1110000
+
+ qemu-system-x86_64 -m 2G -smp 4 -bios coreboot.rom \
+ -drive id=disk,file=$DISK,if=none \
+ -device ahci,id=ahci \
+ -device ide-hd,drive=disk,bus=ahci.0 \
+
+This allows booting and installing various distros, many of which are
+64-bit-only, so cannot work with the 32-bit 'coreboot' build.
+
+USB keyboard
+------------
+
+The `CONFIG_USE_PREBOOT` option is enabled by default, meaning that USB starts
+up just before the command-line starts. This allows user interaction on
+non-laptop devices which use a USB keyboard.
CBFS access
-----------
diff --git a/doc/board/emulation/qemu-arm.rst b/doc/board/emulation/qemu-arm.rst
index 7291fa4..1c91c7f 100644
--- a/doc/board/emulation/qemu-arm.rst
+++ b/doc/board/emulation/qemu-arm.rst
@@ -67,6 +67,10 @@
Additional peripherals that have been tested to work in both U-Boot and Linux
can be enabled with the following command line parameters:
+- To add a video console, remove "-nographic" and add e.g.::
+
+ -serial stdio -device VGA
+
- To add a Serial ATA disk via an Intel ICH9 AHCI controller, pass e.g.::
-drive if=none,file=disk.img,format=raw,id=mydisk \
@@ -80,6 +84,10 @@
-device usb-ehci,id=ehci
+- To add a USB keyboard attached to an emulated xHCI controller, pass e.g.::
+
+ -device qemu-xhci,id=xhci -device usb-kbd,bus=xhci.0
+
- To add an NVMe disk, pass e.g.::
-drive if=none,file=disk.img,id=mydisk -device nvme,drive=mydisk,serial=foo
@@ -90,6 +98,74 @@
These have been tested in QEMU 2.9.0 but should work in at least 2.5.0 as well.
+Booting distros
+---------------
+
+It is possible to install and boot a standard Linux distribution using
+qemu_arm64 by setting up a root disk::
+
+ qemu-img create root.img 20G
+
+then using the installer to install. For example, with Debian 12::
+
+ qemu-system-aarch64 \
+ -machine virt -cpu cortex-a53 -m 4G -smp 4 \
+ -bios u-boot.bin \
+ -serial stdio -device VGA \
+ -nic user,model=virtio-net-pci \
+ -device virtio-rng-pci \
+ -device qemu-xhci,id=xhci \
+ -device usb-kbd -device usb-tablet \
+ -drive if=virtio,file=debian-12.0.0-arm64-netinst.iso,format=raw,readonly=on,media=cdrom \
+ -drive if=virtio,file=root.img,format=raw,media=disk
+
+The output will be something like this::
+
+ U-Boot 2023.10-rc2-00075-gbe8fbe718e35 (Aug 11 2023 - 08:38:49 +0000)
+
+ DRAM: 4 GiB
+ Core: 51 devices, 14 uclasses, devicetree: board
+ Flash: 64 MiB
+ Loading Environment from Flash... *** Warning - bad CRC, using default environment
+
+ In: serial,usbkbd
+ Out: serial,vidconsole
+ Err: serial,vidconsole
+ Bus xhci_pci: Register 8001040 NbrPorts 8
+ Starting the controller
+ USB XHCI 1.00
+ scanning bus xhci_pci for devices... 3 USB Device(s) found
+ Net: eth0: virtio-net#32
+ Hit any key to stop autoboot: 0
+ Scanning for bootflows in all bootdevs
+ Seq Method State Uclass Part Name Filename
+ --- ----------- ------ -------- ---- ------------------------ ----------------
+ Scanning global bootmeth 'efi_mgr':
+ Scanning bootdev 'fw-cfg@9020000.bootdev':
+ fatal: no kernel available
+ scanning bus for devices...
+ Scanning bootdev 'virtio-blk#34.bootdev':
+ 0 efi ready virtio 2 virtio-blk#34.bootdev.par efi/boot/bootaa64.efi
+ ** Booting bootflow 'virtio-blk#34.bootdev.part_2' with efi
+ Using prior-stage device tree
+ Failed to load EFI variables
+ Error: writing contents
+ ** Unable to write file ubootefi.var **
+ Failed to persist EFI variables
+ Missing TPMv2 device for EFI_TCG_PROTOCOL
+ Booting /efi\boot\bootaa64.efi
+ Error: writing contents
+ ** Unable to write file ubootefi.var **
+ Failed to persist EFI variables
+ Welcome to GRUB!
+
+Standard boot looks through various available devices and finds the virtio
+disks, then boots from the first one. After a second or so the grub menu appears
+and you can work through the installer flow normally.
+
+After the installation, you can boot into the installed system by running QEMU
+again without the drive argument corresponding to the installer CD image.
+
Enabling TPMv2 support
----------------------
diff --git a/doc/board/emulation/qemu-x86.rst b/doc/board/emulation/qemu-x86.rst
index 15f56b6..c604e42 100644
--- a/doc/board/emulation/qemu-x86.rst
+++ b/doc/board/emulation/qemu-x86.rst
@@ -193,6 +193,9 @@
The bochs video driver also seems to cause problems before the OS is able to
show a display.
+The QEMU `-cdrom` option is intended to work with the original ISO-format
+images, not the recently invented ISOHybrid image.
+
Finally, the use of `-M accel=kvm` is intended to use the native CPU's
virtual-machine features to accelerate operation, but this causes U-Boot to hang
when jumping 64-bit mode, at least on AMD machines. This may be a bug in U-Boot
diff --git a/doc/board/hisilicon/hikey.rst b/doc/board/hisilicon/hikey.rst
new file mode 100644
index 0000000..8038a24
--- /dev/null
+++ b/doc/board/hisilicon/hikey.rst
@@ -0,0 +1,261 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+HiKey board
+###########
+
+Introduction
+============
+
+HiKey is the first certified 96Boards Consumer Edition board. The board/SoC has:
+
+* HiSilicon Kirin 6220 eight-core ARM Cortex-A53 64-bit SoC running at 1.2GHz.
+* ARM Mali 450-MP4 GPU
+* 1GB 800MHz LPDDR3 DRAM
+* 4GB eMMC Flash Storage
+* microSD
+* 802.11a/b/g/n WiFi, Bluetooth
+
+The HiKey schematic can be found here:
+https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey620/hardware-docs/HiKey_schematics_LeMaker_version_Rev_A1.pdf
+
+The SoC datasheet can be found here:
+https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey620/hardware-docs/Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
+
+Currently the u-boot port supports:
+
+* USB
+* eMMC
+* SD card
+* GPIO
+
+The HiKey U-Boot port has been tested with l-loader, booting ATF, which then
+boots U-Boot as the bl33.bin executable.
+
+Compile from source
+===================
+
+First get all the sources
+
+.. code-block:: bash
+
+ mkdir -p ~/hikey/src ~/hikey/bin
+ cd ~/hikey/src
+ git clone https://github.com/96boards-hikey/edk2 -b testing/hikey960_v2.5
+ git clone https://github.com/ARM-software/arm-trusted-firmware
+ git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
+ git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
+ git clone https://github.com/96boards-hikey/atf-fastboot
+ wget https://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey/release/hisi-idt.py
+
+Get the BL30 mcuimage.bin binary. It is shipped as part of the UEFI source.
+The latest version can be obtained from the OpenPlatformPkg repo.
+
+.. code-block:: bash
+
+ cp OpenPlatformPkg/Platforms/Hisilicon/HiKey/Binary/mcuimage.bin ~/hikey/bin/
+
+Get nvme.img binary
+
+.. code-block:: bash
+
+ wget -P ~/hikey/bin https://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey/release/nvme.img
+
+Compile U-Boot
+==============
+
+.. code-block:: bash
+
+ cd ~/hikey/src/u-boot
+ make CROSS_COMPILE=aarch64-linux-gnu- hikey_config
+ make CROSS_COMPILE=aarch64-linux-gnu-
+ cp u-boot.bin ~/hikey/bin
+
+Compile ARM Trusted Firmware (ATF)
+==================================
+
+.. code-block:: bash
+
+ cd ~/hikey/src/arm-trusted-firmware
+ make CROSS_COMPILE=aarch64-linux-gnu- all fip \
+ SCP_BL2=~/hikey/bin/mcuimage.bin \
+ BL33=~/hikey/bin/u-boot.bin DEBUG=1 PLAT=hikey
+
+Copy the resulting FIP binary
+
+.. code-block:: bash
+
+ cp build/hikey/debug/fip.bin ~/hikey/bin
+
+Compile ATF Fastboot
+====================
+
+.. code-block:: bash
+
+ cd ~/hikey/src/atf-fastboot
+ make CROSS_COMPILE=aarch64-linux-gnu- PLAT=hikey DEBUG=1
+
+Compile l-loader
+================
+
+.. code-block:: bash
+
+ cd ~/hikey/src/l-loader
+ ln -sf ~/hikey/src/arm-trusted-firmware/build/hikey/debug/bl1.bin
+ ln -sf ~/hikey/src/arm-trusted-firmware/build/hikey/debug/bl2.bin
+ ln -sf ~/hikey/src/atf-fastboot/build/hikey/debug/bl1.bin fastboot.bin
+ make hikey PTABLE_LST=aosp-8g
+
+Copy the resulting binaries
+
+.. code-block:: bash
+
+ cp *.img ~/hikey/bin
+ cp l-loader.bin ~/hikey/bin
+ cp recovery.bin ~/hikey/bin
+
+These instructions are adapted from
+https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/plat/hikey.rst
+
+Flashing
+========
+
+1. Connect the second jumper on J15 BOOT SEL, to go into recovery mode and flash l-loader.bin with
+the hisi-idt.py utility. Then connect a USB A to B mini cable from your PC to the USB OTG port of HiKey and execute the below command.
+
+The command below assumes HiKey enumerated as the first USB serial port
+
+.. code-block:: bash
+
+ sudo python ~/hikey/src/hisi-idt.py -d /dev/ttyUSB0 --img1 ~/hikey/bin/recovery.bin
+
+2. Once LED 0 comes on solid, HiKey board should be detected as a fastboot device.
+
+.. code-block::
+
+ sudo fastboot devices
+
+ 0123456789ABCDEF fastboot
+
+3. Flash the images
+
+.. code-block::
+
+ sudo fastboot flash ptable ~/hikey/bin/prm_ptable.img
+ sudo fastboot flash loader ~/hikey/bin/l-loader.bin
+ sudo fastboot flash fastboot ~/hikey/bin/fip.bin
+ sudo fastboot flash nvme ~/hikey/bin/nvme.img
+
+4. Disconnect second jumper on J15 BOOT SEL, and reset the board and you will now (hopefully)
+ have ATF, booting u-boot from eMMC.
+
+ Note: To get USB host working, also disconnect the USB OTG cable used for flashing. Otherwise you
+ will get 'dwc_otg_core_host_init: Timeout!' errors.
+
+See working boot trace below on UART3 available at Low Speed Expansion header::
+
+ NOTICE: BL2: v1.5(debug):v1.5-694-g6d4f6aea
+ NOTICE: BL2: Built : 09:21:42, Aug 29 2018
+ INFO: BL2: Doing platform setup
+ INFO: ddr3 rank1 init pass
+ INFO: succeed to set ddrc 150mhz
+ INFO: ddr3 rank1 init pass
+ INFO: succeed to set ddrc 266mhz
+ INFO: ddr3 rank1 init pass
+ INFO: succeed to set ddrc 400mhz
+ INFO: ddr3 rank1 init pass
+ INFO: succeed to set ddrc 533mhz
+ INFO: ddr3 rank1 init pass
+ INFO: succeed to set ddrc 800mhz
+ INFO: Samsung DDR
+ INFO: ddr test value:0xa5a55a5a
+ INFO: BL2: TrustZone: protecting 16777216 bytes of memory at 0x3f000000
+ INFO: BL2: TrustZone: protecting 4194304 bytes of memory at 0x3e800000
+ INFO: [BDID] [fff91c18] midr: 0x410fd033
+ INFO: init_acpu_dvfs: pmic version 17
+ INFO: init_acpu_dvfs: ACPU_CHIP_MAX_FREQ=0x186a00.
+ INFO: acpu_dvfs_volt_init: success!
+ INFO: acpu_dvfs_set_freq: support freq num is 5
+ INFO: acpu_dvfs_set_freq: start prof is 0x4
+ INFO: acpu_dvfs_set_freq: magic is 0x5a5ac5c5
+ INFO: acpu_dvfs_set_freq: voltage:
+ INFO: - 0: 0x49
+ INFO: - 1: 0x49
+ INFO: - 2: 0x50
+ INFO: - 3: 0x60
+ INFO: - 4: 0x78
+ NOTICE: acpu_dvfs_set_freq: set acpu freq success!INFO: BL2: Loading image id 2
+ INFO: Loading image id=2 at address 0x1000000
+ INFO: Image id=2 loaded: 0x1000000 - 0x1023d00
+ INFO: hisi_mcu_load_image: mcu sections 0:
+ INFO: hisi_mcu_load_image: src = 0x1000200
+ INFO: hisi_mcu_load_image: dst = 0xf6000000
+ INFO: hisi_mcu_load_image: size = 31184
+ INFO: hisi_mcu_load_image: [SRC 0x1000200] 0x8000 0x3701 0x7695 0x7689
+ INFO: hisi_mcu_load_image: [DST 0xf6000000] 0x8000 0x3701 0x7695 0x7689
+ INFO: hisi_mcu_load_image: mcu sections 1:
+ INFO: hisi_mcu_load_image: src = 0x1007bd0
+ INFO: hisi_mcu_load_image: dst = 0x5e00000
+ INFO: hisi_mcu_load_image: size = 93828
+ INFO: hisi_mcu_load_image: [SRC 0x1007bd0] 0xf000b510 0x2103fb3d 0xf0004604 0xf003fb57
+ INFO: hisi_mcu_load_image: [DST 0x5e00000] 0xf000b510 0x2103fb3d 0xf0004604 0xf003fb57
+ INFO: hisi_mcu_load_image: mcu sections 2:
+ INFO: hisi_mcu_load_image: src = 0x101ea54
+ INFO: hisi_mcu_load_image: dst = 0x5e16e84
+ INFO: hisi_mcu_load_image: size = 15428
+ INFO: hisi_mcu_load_image: [SRC 0x101ea54] 0x9 0x1020640 0x10001 0x8f0d180
+ INFO: hisi_mcu_load_image: [DST 0x5e16e84] 0x9 0x1020640 0x10001 0x8f0d180
+ INFO: hisi_mcu_load_image: mcu sections 3:
+ INFO: hisi_mcu_load_image: src = 0x1022698
+ INFO: hisi_mcu_load_image: dst = 0x5e22a10
+ INFO: hisi_mcu_load_image: size = 3060
+ INFO: hisi_mcu_load_image: [SRC 0x1022698] 0x0 0x0 0x0 0x0
+ INFO: hisi_mcu_load_image: [DST 0x5e22a10] 0x0 0x0 0x0 0x0
+ INFO: hisi_mcu_load_image: mcu sections 4:
+ INFO: hisi_mcu_load_image: src = 0x102328c
+ INFO: hisi_mcu_load_image: dst = 0x5e23604
+ INFO: hisi_mcu_load_image: size = 2616
+ INFO: hisi_mcu_load_image: [SRC 0x102328c] 0xf80000a0 0x0 0xf80000ac 0x0
+ INFO: hisi_mcu_load_image: [DST 0x5e23604] 0xf80000a0 0x0 0xf80000ac 0x0
+ INFO: hisi_mcu_start_run: AO_SC_SYS_CTRL2=0
+ INFO: plat_hikey_bl2_handle_scp_bl2: MCU PC is at 0x42933301
+ INFO: plat_hikey_bl2_handle_scp_bl2: AO_SC_PERIPH_CLKSTAT4 is 0x3b018f09
+ WARNING: BL2: Platform setup already done!!
+ INFO: BL2: Loading image id 3
+ INFO: Loading image id=3 at address 0xf9858000
+ INFO: Image id=3 loaded: 0xf9858000 - 0xf9860058
+ INFO: BL2: Loading image id 5
+ INFO: Loading image id=5 at address 0x35000000
+ INFO: Image id=5 loaded: 0x35000000 - 0x35061cd2
+ NOTICE: BL2: Booting BL31
+ INFO: Entry point address = 0xf9858000
+ INFO: SPSR = 0x3cd
+ NOTICE: BL31: v1.5(debug):v1.5-694-g6d4f6aea
+ NOTICE: BL31: Built : 09:21:44, Aug 29 2018
+ WARNING: Using deprecated integer interrupt array in gicv2_driver_data_t
+ WARNING: Please migrate to using an interrupt_prop_t array
+ INFO: ARM GICv2 driver initialized
+ INFO: BL31: Initializing runtime services
+ INFO: BL31: cortex_a53: CPU workaround for disable_non_temporal_hint was applied
+ INFO: BL31: cortex_a53: CPU workaround for 843419 was applied
+ INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
+ INFO: BL31: Preparing for EL3 exit to normal world
+ INFO: Entry point address = 0x35000000
+ INFO: SPSR = 0x3c9
+
+ U-Boot 2018.09-rc1 (Aug 22 2018 - 14:55:49 +0530)hikey
+
+ DRAM: 990 MiB
+ HI6553 PMIC init
+ MMC: config_sd_carddetect: SD card present
+ Hisilicon DWMMC: 0, Hisilicon DWMMC: 1
+ Loading Environment from FAT... Unable to use mmc 1:1... Failed (-5)
+ In: uart@f7113000
+ Out: uart@f7113000
+ Err: uart@f7113000
+ Net: Net Initialization Skipped
+ No ethernet found.
+ Hit any key to stop autoboot: 0
+ starting USB...
+ USB0: scanning bus 0 for devices... 2 USB Device(s) found
+ scanning usb for storage devices... 0 Storage Device(s) found
+ scanning usb for ethernet devices... 0 Ethernet Device(s) found
diff --git a/doc/board/hisilicon/hikey960.rst b/doc/board/hisilicon/hikey960.rst
new file mode 100644
index 0000000..93e983b
--- /dev/null
+++ b/doc/board/hisilicon/hikey960.rst
@@ -0,0 +1,284 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+HiKey960 board
+##############
+
+Introduction
+============
+
+HiKey960 is one of the 96Boards Consumer Edition board from HiSilicon.
+The board/SoC has:
+
+* HiSilicon Kirin960 (HI3660) SoC with 4xCortex-A73 and 4xCortex-A53
+* ARM Mali G71 MP8 GPU
+* 3GB LPDDR4 SDRAM
+* 32GB UFS Flash Storage
+* microSD
+* 802.11a/b/g/n WiFi, Bluetooth
+
+More information about this board can be found in 96Boards website:
+https://www.96boards.org/product/hikey960/
+
+Currently the u-boot port supports:
+
+* SD card
+
+Compile from source
+===================
+
+First get all the sources
+
+.. code-block:: bash
+
+ mkdir -p ~/hikey960/src ~/hikey960/bin
+ cd ~/hikey960/src
+ git clone https://github.com/ARM-software/arm-trusted-firmware
+ git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
+ git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
+ wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/config
+ wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/hisi-sec_usb_xloader.img
+ wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/hisi-sec_uce_boot.img
+ wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/hisi-sec_xloader.img
+ wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/recovery.bin
+ wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/hikey_idt
+
+Get the SCP_BL2 lpm3.img binary. It is shipped as part of the UEFI source.
+The latest version can be obtained from the OpenPlatformPkg repo.
+
+.. code-block:: bash
+
+ cp OpenPlatformPkg/Platforms/Hisilicon/HiKey960/Binary/lpm3.img ~/hikey960/bin/
+
+Compile U-Boot
+==============
+
+.. code-block:: bash
+
+ cd ~/hikey960/src/u-boot
+ make CROSS_COMPILE=aarch64-linux-gnu- hikey960_defconfig
+ make CROSS_COMPILE=aarch64-linux-gnu-
+ cp u-boot.bin ~/hikey960/bin/
+
+Compile ARM Trusted Firmware (ATF)
+==================================
+
+.. code-block:: bash
+
+ cd ~/hikey960/src/arm-trusted-firmware
+ make CROSS_COMPILE=aarch64-linux-gnu- all fip \
+ SCP_BL2=~/hikey960/bin/lpm3.img \
+ BL33=~/hikey960/bin/u-boot.bin DEBUG=1 PLAT=hikey960
+
+Copy the resulting FIP binary
+
+.. code-block:: bash
+
+ cp build/hikey960/debug/fip.bin ~/hikey960/bin
+
+Compile l-loader
+================
+
+.. code-block:: bash
+
+ cd ~/hikey960/src/l-loader
+ ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/bl1.bin
+ ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/bl2.bin
+ ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/fip.bin
+ ln -sf ~/hikey960/bin/u-boot.bin
+ make hikey960 PTABLE_LST=linux-32g NS_BL1U=u-boot.bin
+
+Copy the resulting binaries
+
+.. code-block:: bash
+
+ cp *.img ~/hikey960/bin
+ cp l-loader.bin ~/hikey960/bin
+
+These instructions are adapted from
+https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/plat/hikey960.rst
+
+Setup console
+=============
+
+Install ser2net. Use telnet as the console since UEFI in recovery mode
+output window fails to display in minicom.
+
+.. code-block:: bash
+
+ sudo apt-get install ser2net
+
+Configure ser2net
+
+.. code-block:: bash
+
+ sudo vi /etc/ser2net.conf
+
+Append one line for serial-over-USB in #ser2net.conf
+
+ 2004:telnet:0:/dev/ttyUSB0:115200 8DATABITS NONE 1STOPBIT banner
+
+Start ser2net
+
+.. code-block:: bash
+
+ sudo killall ser2net
+ sudo ser2net -u
+
+Open the console.
+
+.. code-block:: bash
+
+ telnet localhost 2004
+
+And you could open the console remotely, too.
+
+Flashing
+========
+
+1. Boot Hikey960 into recovery mode as per the below document:
+https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey960/installation/board-recovery.md
+
+Once Hikey960 is in recovery mode, flash the recovery binary:
+
+.. code-block:: bash
+
+ cd ~/hikey960/src
+ chmod +x ./hikey_idt
+ sudo ./hikey_idt -c config -p /dev/ttyUSB1
+
+Now move to the Hikey960 console and press `f` during UEFI boot. This
+will allow the board to boot into fastboot mode. Once the board is in
+fastboot mode, you should see the ID of the HiKey960 board using the
+following command
+
+.. code-block:: bash
+
+ sudo fastboot devices
+
+ 1ED3822A018E3372 fastboot
+
+3. Flash the images
+
+Now, the images can be flashed using fastboot:
+
+.. code-block:: bash
+
+ sudo fastboot flash ptable ~/hikey960/bin/prm_ptable.img
+ sudo fastboot flash xloader ~/hikey960/bin/hisi-sec_xloader.img
+ sudo fastboot flash fastboot ~/hikey960/bin/l-loader.bin
+ sudo fastboot flash fip ~/hikey960/bin/fip.bin
+
+4. Set the "Boot Mode" switch to OFF position for normal boot mode.
+Then power on HiKey960
+
+Observe the console traces using UART6 on the Low Speed Expansion header::
+
+ NOTICE: BL2: v2.1(debug):v2.1-531-g3ee48f40
+ NOTICE: BL2: Built : 18:15:58, Aug 2 2019
+ INFO: BL2: Doing platform setup
+ INFO: UFS LUN0 contains 1024 blocks with 4096-byte size
+ INFO: UFS LUN1 contains 1024 blocks with 4096-byte size
+ INFO: UFS LUN2 contains 2048 blocks with 4096-byte size
+ INFO: UFS LUN3 contains 7805952 blocks with 4096-byte size
+ INFO: ufs: change power mode success
+ INFO: BL2: Loading image id 2
+ INFO: Loading image id=2 at address 0x89c80000
+ INFO: Image id=2 loaded: 0x89c80000 - 0x89cb5088
+ INFO: BL2: Initiating SCP_BL2 transfer to SCP
+ INFO: BL2: SCP_BL2: 0x89c80000@0x35088
+ INFO: BL2: SCP_BL2 HEAD:
+ INFO: BL2: SCP_BL2 0x7000 0x179 0x159 0x149
+ INFO: BL2: SCP_BL2 0x189 0x18b 0x18d 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x18f
+ INFO: BL2: SCP_BL2 0x191 0x0 0x193 0x195
+ INFO: BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
+ INFO: BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
+ INFO: BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
+ INFO: BL2: SCP_BL2 0x4d454355 0x43494741 0x424d554e 0x21215245
+ INFO: BL2: SCP_BL2 0x4a054904 0x42912000 0xf841bfbc 0xe7fa0b04
+ INFO: BL2: SCP_BL2 0xb88cf000 0x3b18 0x3d1c 0x6809493e
+ INFO: BL2: SCP_BL2 0x4613680a 0x201f102 0xf0002a04 0x600a804c
+ INFO: BL2: SCP_BL2 0x204f04f 0xf203fb02 0xf102440a 0x60100204
+ INFO: BL2: SCP_BL2 0x160f04f 0xf103fb01 0x68004834 0x61044408
+ INFO: BL2: SCP_BL2 0x61866145 0xf8c061c7 0xf8c08020 0xf8c09024
+ INFO: BL2: SCP_BL2 0xf8c0a028 0xf3efb02c 0xf3ef8208 0x68118309
+ INFO: BL2: SCP_BL2 0xf1026401 0xf0110204 0xbf070f04 0x46113220
+ INFO: BL2: SCP_BL2 TAIL:
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x19cad151 0x19b80040 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 transferred to SCP
+ INFO: start fw loading
+ INFO: fw load success
+ WARNING: BL2: Platform setup already done!!
+ INFO: BL2: Loading image id 3
+ INFO: Loading image id=3 at address 0x1ac58000
+ INFO: Image id=3 loaded: 0x1ac58000 - 0x1ac63024
+ INFO: BL2: Loading image id 5
+ INFO: Loading image id=5 at address 0x1ac98000
+ INFO: Image id=5 loaded: 0x1ac98000 - 0x1ad0819c
+ NOTICE: BL2: Booting BL31
+ INFO: Entry point address = 0x1ac58000
+ INFO: SPSR = 0x3cd
+ NOTICE: BL31: v2.1(debug):v2.1-531-g3ee48f40
+ NOTICE: BL31: Built : 18:16:01, Aug 2 2019
+ INFO: ARM GICv2 driver initialized
+ INFO: BL31: Initializing runtime services
+ INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
+ INFO: plat_setup_psci_ops: sec_entrypoint=0x1ac580fc
+ INFO: BL31: Preparing for EL3 exit to normal world
+ INFO: Entry point address = 0x1ac98000
+ INFO: SPSR = 0x3c9
+
+ U-Boot 2019.07-00628-g286f05a6fc-dirty (Aug 02 2019 - 17:14:05 +0530)
+ Hikey960
+
+ DRAM: 3 GiB
+ PSCI: v1.1
+ MMC: dwmmc1@ff37f000: 0
+ Loading Environment from EXT4... ** File not found /uboot.env **
+
+ ** Unable to read "/uboot.env" from mmc0:2 **
+ In: serial@fff32000
+ Out: serial@fff32000
+ Err: serial@fff32000
+ Net: Net Initialization Skipped
+ No ethernet found.
+ Hit any key to stop autoboot: 0
+ switch to partitions #0, OK
+ mmc0 is current device
+ Scanning mmc 0:1...
+ Found /extlinux/extlinux.conf
+ Retrieving file: /extlinux/extlinux.conf
+ 201 bytes read in 12 ms (15.6 KiB/s)
+ 1: hikey960-kernel
+ Retrieving file: /Image
+ 24689152 bytes read in 4377 ms (5.4 MiB/s)
+ append: earlycon=pl011,mmio32,0xfff32000 console=ttyAMA6,115200 rw root=/dev/mmcblk0p2 rot
+ Retrieving file: /hi3660-hikey960.dtb
+ 35047 bytes read in 14 ms (2.4 MiB/s)
+ ## Flattened Device Tree blob at 10000000
+ Booting using the fdt blob at 0x10000000
+ Using Device Tree in place at 0000000010000000, end 000000001000b8e6
+
+ Starting kernel ...
+
+ [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
+ [ 0.000000] Linux version 5.2.0-03138-gd75da80dce39 (mani@Mani-XPS-13-9360) (gcc versi9
+ [ 0.000000] Machine model: HiKey960
+ [ 0.000000] earlycon: pl11 at MMIO32 0x00000000fff32000 (options '')
+ [ 0.000000] printk: bootconsole [pl11] enabled
+ [ 0.000000] efi: Getting EFI parameters from FDT:
diff --git a/doc/board/hisilicon/index.rst b/doc/board/hisilicon/index.rst
new file mode 100644
index 0000000..5455b76
--- /dev/null
+++ b/doc/board/hisilicon/index.rst
@@ -0,0 +1,11 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+HiSilicon
+=========
+
+.. toctree::
+ :maxdepth: 2
+
+ hikey
+ hikey960
+ poplar
diff --git a/doc/board/hisilicon/poplar.rst b/doc/board/hisilicon/poplar.rst
new file mode 100644
index 0000000..0fccc14
--- /dev/null
+++ b/doc/board/hisilicon/poplar.rst
@@ -0,0 +1,302 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+Poplar board
+############
+
+Board Information
+=================
+
+Developed by HiSilicon, the board features the Hi3798C V200 with an
+integrated quad-core 64-bit ARM Cortex A53 processor and high
+performance Mali T720 GPU, making it capable of running any commercial
+set-top solution based on Linux or Android. Its high performance
+specification also supports a premium user experience with up to H.265
+HEVC decoding of 4K video at 60 frames per second.
+
+* SOC Hisilicon Hi3798CV200
+* CPU Quad-core ARM Cortex-A53 64 bit
+* DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB
+* USB Two USB 2.0 ports One USB 3.0 ports
+* CONSOLE USB-micro port for console support
+* ETHERNET 1 GBe Ethernet
+* PCIE One PCIe 2.0 interfaces
+* JTAG 8-Pin JTAG
+* EXPANSION INTERFACE Linaro 96Boards Low Speed Expansion slot
+* DIMENSION Standard 160×120 mm 96Boards Enterprice Edition form factor
+* WIFI 802.11AC 2*2 with Bluetooth
+* CONNECTORS One connector for Smart Card One connector for TSI
+
+Build instructions
+==================
+
+.. note::
+
+ U-Boot has a **strong** dependency with the l-loader and the ARM trusted
+ firmware repositories.
+
+The boot sequence is::
+
+ l-loader --> arm_trusted_firmware --> U-Boot
+
+U-Boot needs to be aware of the BL31 runtime location and size to avoid writing
+over it. Currently, BL31 is being placed below the kernel text offset (check
+poplar.c) but this could change in the future.
+
+The current version of U-Boot has been tested with
+
+- https://github.com/Linaro/poplar-l-loader.git::
+
+ commit f0988698dcc5c08bd0a8f50aa0457e138a5f438c
+ Author: Alex Elder <elder@linaro.org>
+ Date: Fri Jun 16 08:57:59 2017 -0500
+
+ l-loader: use external memory region definitions
+
+ The ARM Trusted Firmware code now has a header file that collects
+ all the definitions for the memory regions used for its boot stages.
+ Include that file where needed, and use the definitions found therein
+
+ Signed-off-by: Alex Elder <elder@linaro.org>
+
+- https://github.com/Linaro/poplar-arm-trusted-firmware.git::
+
+ commit 6ac42dd3be13c99aa8ce29a15073e2f19d935f68
+ Author: Alex Elder <elder@linaro.org>
+ Date: Fri Jun 16 09:24:50 2017 -0500
+
+ poplar: define memory regions in a separate file
+
+ Separate the definitions for memory regions used for the BL stage
+ images and FIP into a new file. The "l-loader" image uses knowledge
+ of the sizes and locations of these memory regions, and it can now
+ include this (external) header to get these definitions, rather than
+ having to make coordinated changes to both code bases.
+
+ The new file has a complete set of definitions (more than may be
+ required by one or the other user). It also includes a summary of
+ how the boot process works, and how it uses these regions.
+
+ It should now be relatively easy to adjust the sizes and locations
+ of these memory regions, or to add to them (e.g. for TEE).
+
+ Signed-off-by: Alex Elder <elder@linaro.org>
+
+
+Compile from source
+-------------------
+
+Get all the sources
+
+.. code-block:: bash
+
+ mkdir -p ~/poplar/src ~/poplar/bin
+ cd ~/poplar/src
+ git clone https://github.com/Linaro/poplar-l-loader.git l-loader
+ git clone https://github.com/Linaro/poplar-arm-trusted-firmware.git atf
+ git clone https://github.com/Linaro/poplar-U-Boot.git U-Boot
+
+Make sure you are using the correct branch on each one of these repositories.
+The definition of "correct" might change over time (at this moment in time this
+would be the "latest" branch).
+
+Compile U-Boot
+~~~~~~~~~~~~~~
+
+Prerequisite:
+
+.. code-block:: bash
+
+ sudo apt-get install device-tree-compiler
+
+.. code-block:: bash
+
+ cd ~/poplar/src/U-Boot
+ make CROSS_COMPILE=aarch64-linux-gnu- poplar_defconfig
+ make CROSS_COMPILE=aarch64-linux-gnu-
+ cp U-Boot.bin ~/poplar/bin
+
+Compile ARM Trusted Firmware (ATF)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. code-block:: bash
+
+ cd ~/poplar/src/atf
+ make CROSS_COMPILE=aarch64-linux-gnu- all fip \
+ SPD=none BL33=~/poplar/bin/U-Boot.bin DEBUG=1 PLAT=poplar
+
+Copy resulting binaries
+
+.. code-block:: bash
+
+ cp build/hi3798cv200/debug/bl1.bin ~/poplar/src/l-loader/atf/
+ cp build/hi3798cv200/debug/fip.bin ~/poplar/src/l-loader/atf/
+
+Compile l-loader
+~~~~~~~~~~~~~~~~
+
+.. code-block:: bash
+
+ cd ~/poplar/src/l-loader
+ make clean
+ make CROSS_COMPILE=arm-linux-gnueabi-
+
+Due to BootROM requiremets, rename l-loader.bin to fastboot.bin:
+
+.. code-block:: bash
+
+ cp l-loader.bin ~/poplar/bin/fastboot.bin
+
+Flash instructions
+==================
+
+Two methods:
+
+Using USB debrick support
+ Copy fastboot.bin to a FAT partition on the USB drive and reboot the
+ poplar board while pressing S3(usb_boot).
+
+ The system will execute the new U-Boot and boot into a shell which you
+ can then use to write to eMMC.
+
+Using U-BOOT from shell
+ 1) using AXIS usb ethernet dongle and tftp
+ 2) using FAT formated USB drive
+
+Flash using TFTP (USB ethernet dongle)
+--------------------------------------
+
+Plug a USB AXIS ethernet dongle on any of the USB2 ports on the Poplar board.
+Copy fastboot.bin to your tftp server.
+In U-Boot make sure your network is properly setup.
+
+Then::
+
+ => tftp 0x30000000 fastboot.bin
+ starting USB...
+ USB0: USB EHCI 1.00
+ scanning bus 0 for devices... 1 USB Device(s) found
+ USB1: USB EHCI 1.00
+ scanning bus 1 for devices... 3 USB Device(s) found
+ scanning usb for storage devices... 0 Storage Device(s) found
+ scanning usb for ethernet devices... 1 Ethernet Device(s) found
+ Waiting for Ethernet connection... done.
+ Using asx0 device
+ TFTP from server 192.168.1.4; our IP address is 192.168.1.10
+ Filename 'poplar/fastboot.bin'.
+ Load address: 0x30000000
+ Loading: #################################################################
+ #################################################################
+ ###############################################################
+ 2 MiB/s
+ done
+ Bytes transferred = 983040 (f0000 hex)
+
+ => mmc write 0x30000000 0 0x780
+
+ MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK
+ => reset
+
+Flash using USB FAT drive
+-------------------------
+
+Copy fastboot.bin to any partition on a FAT32 formated usb flash drive.
+Enter the uboot prompt::
+
+ => fatls usb 0:2
+ 983040 fastboot.bin
+
+ 1 file(s), 0 dir(s)
+
+ => fatload usb 0:2 0x30000000 fastboot.bin
+ reading fastboot.bin
+ 983040 bytes read in 44 ms (21.3 MiB/s)
+
+ => mmc write 0x30000000 0 0x780
+
+ MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK
+
+Boot trace
+==========
+
+::
+
+ Bootrom start
+ Boot Media: eMMC
+ Decrypt auxiliary code ...OK
+
+ lsadc voltage min: 000000FE, max: 000000FF, aver: 000000FE, index: 00000000
+
+ Entry boot auxiliary code
+
+ Auxiliary code - v1.00
+ DDR code - V1.1.2 20160205
+ Build: Mar 24 2016 - 17:09:44
+ Reg Version: v134
+ Reg Time: 2016/03/18 09:44:55
+ Reg Name: hi3798cv2dmb_hi3798cv200_ddr3_2gbyte_8bitx4_4layers.reg
+
+ Boot auxiliary code success
+ Bootrom success
+
+ LOADER: Switched to aarch64 mode
+ LOADER: Entering ARM TRUSTED FIRMWARE
+ LOADER: CPU0 executes at 0x000ce000
+
+ INFO: BL1: 0xe1000 - 0xe7000 [size = 24576]
+ NOTICE: Booting Trusted Firmware
+ NOTICE: BL1: v1.3(debug):v1.3-372-g1ba9c60
+ NOTICE: BL1: Built : 17:51:33, Apr 30 2017
+ INFO: BL1: RAM 0xe1000 - 0xe7000
+ INFO: BL1: Loading BL2
+ INFO: Loading image id=1 at address 0xe9000
+ INFO: Image id=1 loaded at address 0xe9000, size = 0x5008
+ NOTICE: BL1: Booting BL2
+ INFO: Entry point address = 0xe9000
+ INFO: SPSR = 0x3c5
+ NOTICE: BL2: v1.3(debug):v1.3-372-g1ba9c60
+ NOTICE: BL2: Built : 17:51:33, Apr 30 2017
+ INFO: BL2: Loading BL31
+ INFO: Loading image id=3 at address 0x129000
+ INFO: Image id=3 loaded at address 0x129000, size = 0x8038
+ INFO: BL2: Loading BL33
+ INFO: Loading image id=5 at address 0x37000000
+ INFO: Image id=5 loaded at address 0x37000000, size = 0x58f17
+ NOTICE: BL1: Booting BL31
+ INFO: Entry point address = 0x129000
+ INFO: SPSR = 0x3cd
+ INFO: Boot bl33 from 0x37000000 for 364311 Bytes
+ NOTICE: BL31: v1.3(debug):v1.3-372-g1ba9c60
+ NOTICE: BL31: Built : 17:51:33, Apr 30 2017
+ INFO: BL31: Initializing runtime services
+ INFO: BL31: Preparing for EL3 exit to normal world
+ INFO: Entry point address = 0x37000000
+ INFO: SPSR = 0x3c9
+
+ U-Boot 2017.05-rc2-00130-gd2255b0 (Apr 30 2017 - 17:51:28 +0200)poplar
+
+ Model: HiSilicon Poplar Development Board
+ BOARD: Hisilicon HI3798cv200 Poplar
+ DRAM: 1 GiB
+ MMC: Hisilicon DWMMC: 0
+ In: serial@f8b00000
+ Out: serial@f8b00000
+ Err: serial@f8b00000
+ Net: Net Initialization Skipped
+ No ethernet found.
+
+ Hit any key to stop autoboot: 0
+ starting USB...
+ USB0: USB EHCI 1.00
+ scanning bus 0 for devices... 1 USB Device(s) found
+ USB1: USB EHCI 1.00
+ scanning bus 1 for devices... 4 USB Device(s) found
+ scanning usb for storage devices... 1 Storage Device(s) found
+ scanning usb for ethernet devices... 1 Ethernet Device(s) found
+
+ USB device 0:
+ Device 0: Vendor: SanDisk Rev: 1.00 Prod: Cruzer Blade
+ Type: Removable Hard Disk
+ Capacity: 7632.0 MB = 7.4 GB (15630336 x 512)
+ ... is now current device
+ Scanning usb 0:1...
+ =>
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 35dd3bc..531e547 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -26,6 +26,7 @@
gateworks/index
google/index
highbank/index
+ hisilicon/index
htc/index
intel/index
kontron/index
diff --git a/doc/board/kontron/sl28.rst b/doc/board/kontron/sl28.rst
index 44435d9..2cb8ec6 100644
--- a/doc/board/kontron/sl28.rst
+++ b/doc/board/kontron/sl28.rst
@@ -39,12 +39,12 @@
------------
After the build finished, there will be an update image called
-u-boot.update. This can either be used in the DFU mode (which isn't
+u-boot-update.bin. This can either be used in the DFU mode (which isn't
supported yet) or encapsulated in an EFI UpdateCapsule.
To build the capsule use the following command
- $ tools/mkeficapsule -f u-boot.update -i 1 UpdateUboot
+ $ tools/mkeficapsule -f u-boot-update.bin -i 1 UpdateUboot
Afterward you can copy this file to your ESP into the /EFI/UpdateCapsule/
folder. On the next EFI boot this will automatically update your
diff --git a/doc/board/mediatek/index.rst b/doc/board/mediatek/index.rst
index 38cd8cb..c55d5ae 100644
--- a/doc/board/mediatek/index.rst
+++ b/doc/board/mediatek/index.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+
Mediatek
-=========
+========
.. toctree::
:maxdepth: 2
diff --git a/doc/board/nxp/imx8mm_evk.rst b/doc/board/nxp/imx8mm_evk.rst
index 327ce6e..bb11029 100644
--- a/doc/board/nxp/imx8mm_evk.rst
+++ b/doc/board/nxp/imx8mm_evk.rst
@@ -36,7 +36,7 @@
$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
Build U-Boot for sd card
---------------------------
+------------------------
.. code-block:: bash
@@ -54,8 +54,8 @@
----
Set Boot switch to SD boot
-Build U-Boot for qspi flash card
-------------------------------------
+Build U-Boot for qspi flash card
+--------------------------------
.. code-block:: bash
@@ -81,7 +81,8 @@
$ sf write $loadaddr 0x00 <size_of_flash.bin_in_hex>
Boot from QSPI Flash
------------------------
+--------------------
+
Set Boot Switch to QSPI Flash
Pin configuration for imx8mm_revC evk to boot from qspi flash
diff --git a/doc/board/nxp/ls1046ardb.rst b/doc/board/nxp/ls1046ardb.rst
index 49b4842..8c0bc82 100644
--- a/doc/board/nxp/ls1046ardb.rst
+++ b/doc/board/nxp/ls1046ardb.rst
@@ -54,7 +54,7 @@
- ARM JTAG support
Memory map from core's view
-----------------------------
+---------------------------
================== ================== ================ =====
Start Address End Address Description Size
diff --git a/doc/board/nxp/mx6ul_14x14_evk.rst b/doc/board/nxp/mx6ul_14x14_evk.rst
index 3e57ba1..c135a21 100644
--- a/doc/board/nxp/mx6ul_14x14_evk.rst
+++ b/doc/board/nxp/mx6ul_14x14_evk.rst
@@ -4,7 +4,7 @@
===============
How to use U-Boot on Freescale MX6UL 14x14 EVK
------------------------------------------------
+----------------------------------------------
- Build U-Boot for MX6UL 14x14 EVK:
diff --git a/doc/board/openpiton/riscv64.rst b/doc/board/openpiton/riscv64.rst
index 3a97793..c379fbf 100644
--- a/doc/board/openpiton/riscv64.rst
+++ b/doc/board/openpiton/riscv64.rst
@@ -11,14 +11,14 @@
running full-stack Debian linux.
RISC-V Standard Bootflow
--------------------------
+------------------------
Currently, OpenPiton implements RISC-V standard bootflow in the following steps
mover.S -> u-boot-spl -> opensbi -> u-boot -> Linux
This board supports S-mode u-boot as well as M-mode SPL
Building OpenPition
----------------------
+-------------------
If you'd like to build OpenPiton, please go to OpenPiton github repo
(at https://github.com/PrincetonUniversity/openpiton) to build from the latest
diff --git a/doc/board/purism/librem5.rst b/doc/board/purism/librem5.rst
index fb050c6..a7975e1 100644
--- a/doc/board/purism/librem5.rst
+++ b/doc/board/purism/librem5.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+
Librem5
-==========
+=======
U-Boot for the Purism Librem5 phone
diff --git a/doc/board/qualcomm/sdm845.rst b/doc/board/qualcomm/sdm845.rst
index d3f218e..a65f00d 100644
--- a/doc/board/qualcomm/sdm845.rst
+++ b/doc/board/qualcomm/sdm845.rst
@@ -2,10 +2,11 @@
.. sectionauthor:: Dzmitry Sankouski <dsankouski@gmail.com>
Snapdragon 845
-================
+==============
About this
----------
+
This document describes the information about Qualcomm Snapdragon 845
supported boards and it's usage steps.
@@ -17,8 +18,10 @@
Installation
------------
+
Build
^^^^^
+
Setup ``CROSS_COMPILE`` for aarch64 and build U-Boot for your board::
$ export CROSS_COMPILE=<aarch64 toolchain prefix>
@@ -29,10 +32,12 @@
Generate FIT image
^^^^^^^^^^^^^^^^^^
+
See doc/uImage.FIT for more details
Pack android boot image
^^^^^^^^^^^^^^^^^^^^^^^
+
We'll assemble android boot image with ``u-boot.bin`` instead of linux kernel,
and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel
with appended dtb, so let's mimic linux to satisfy stock bootloader.
diff --git a/doc/board/renesas/renesas.rst b/doc/board/renesas/renesas.rst
index 04dee8d..7d961e8 100644
--- a/doc/board/renesas/renesas.rst
+++ b/doc/board/renesas/renesas.rst
@@ -9,37 +9,230 @@
This document describes the information about Renesas supported boards
and their usage steps.
-Renesas boards
---------------
+Renesas SoC based boards
+------------------------
Renesas is a SoC solutions provider for automotive and industrial applications.
-U-Boot supports several Renesas SoC families:
+.. list-table:: Supported Renesas SoC based boards
+ :widths: 10, 25, 15, 10, 25
+ :header-rows: 1
-* R-Car Gen2 (32-bit)
- - Blanche board
- - Gose board
- - Koelsch board
- - Lager board
- - Silk board
- - Porter board
- - Stout board
-* R-Car Gen3 (64-bit)
- - Condor board
- - Draak board
- - Eagle board
- - Ebisu board
- - Salvator-X and Salvator-XS boards
- - ULCB board
-* R-Car Gen4 (64-bit)
- - Falcon board
- - Spider board
- - Whitehawk board
-* RZ/A1 (32-bit)
- - GR-PEACH board
-* RZ/G
- - Beacon-rzg2 board
- - Hihope-rzg2 board
- - ek874 board
-* RZ/N1 (32-bit)
- - Schneider rzn1-snarc board
+ * - Family
+ - Board
+ - SoC
+ - Arch
+ - defconfig
+
+ * - R2D
+ - R2D-PLUS
+ - SH7751
+ - sh
+ - r2dplus_defconfig
+
+ * - RZ/A1
+ - GR-PEACH
+ - R7S72100 (RZ/A1H)
+ - arm
+ - grpeach_defconfig
+
+ * - R-Car Gen2
+ - Lager
+ - R8A7790 (H2)
+ - arm
+ - lager_defconfig
+
+ * -
+ - Stout
+ - R8A7790 (H2)
+ - arm
+ - stout_defconfig
+
+ * -
+ - Koelsch
+ - R8A7791 (M2-W)
+ - arm
+ - koelsch_defconfig
+
+ * -
+ - Porter
+ - R8A7791 (M2-W)
+ - arm
+ - porter_defconfig
+
+ * -
+ - Blanche
+ - R8A7792 (V2H)
+ - arm
+ - blanche_defconfig
+
+ * -
+ - Gose
+ - R8A7793 (M2-N)
+ - arm
+ - gose_defconfig
+
+ * -
+ - Alt
+ - R8A7794 (E2)
+ - arm
+ - alt_defconfig
+
+ * -
+ - Silk
+ - R8A7794 (E2)
+ - arm
+ - silk_defconfig
+
+ * - R-Car Gen3
+ - Salvator-X(S)
+ - R8A77951 (H3)
+ - arm64
+ - rcar3_salvator-x_defconfig
+
+ * -
+ - ULCB
+ - R8A77951 (H3)
+ - arm64
+ - rcar3_ulcb_defconfig
+
+ * -
+ - Salvator-X(S)
+ - R8A77960 (M3-W)
+ - arm64
+ - rcar3_salvator-x_defconfig
+
+ * -
+ - ULCB
+ - R8A77960 (M3-W)
+ - arm64
+ - rcar3_ulcb_defconfig
+
+ * -
+ - Salvator-X(S)
+ - R8A77965 (M3-N)
+ - arm64
+ - rcar3_salvator-x_defconfig
+
+ * -
+ - ULCB
+ - R8A77965 (M3-N)
+ - arm64
+ - rcar3_ulcb_defconfig
+
+ * -
+ - Eagle
+ - R8A77970 (V3M)
+ - arm64
+ - r8a77970_eagle_defconfig
+
+ * -
+ - V3MSK
+ - R8A77970 (V3M)
+ - arm64
+ - r8a77970_v3msk_defconfig
+
+ * -
+ - Condor
+ - R8A77980 (V3H)
+ - arm64
+ - r8a77980_condor_defconfig
+
+ * -
+ - V3HSK
+ - R8A77980 (V3H)
+ - arm64
+ - r8a77980_v3hsk_defconfig
+
+ * -
+ - Ebisu
+ - R8A77990 (E3)
+ - arm64
+ - r8a77990_ebisu_defconfig
+
+ * -
+ - Draak
+ - R8A77995 (D3)
+ - arm64
+ - r8a77995_draak_defconfig
+
+ * - R-Car Gen4
+ - Falcon
+ - R8A779A0 (V3U)
+ - arm64
+ - r8a779a0_falcon_defconfig
+
+ * -
+ - Spider
+ - R8A779F0 (S4)
+ - arm64
+ - r8a779f0_spider_defconfig
+
+ * -
+ - White Hawk
+ - R8A779G0 (V4H)
+ - arm64
+ - r8a779g0_whitehawk_defconfig
+
+ * - RZ/G2 Family
+ - Beacon EmbeddedWorks RZ/G2M SoM
+ - R8A774A1 (RZ/G2M)
+ - arm64
+ - rzg2_beacon_defconfig
+
+ * -
+ - HopeRun HiHope RZ/G2M
+ - R8A774A1 (RZ/G2M)
+ - arm64
+ - hihope_rzg2_defconfig
+
+ * -
+ - Beacon EmbeddedWorks RZ/G2N SoM
+ - R8A774B1 (RZ/G2N)
+ - arm64
+ - rzg2_beacon_defconfig
+
+ * -
+ - HopeRun HiHope RZ/G2N
+ - R8A774B1 (RZ/G2N)
+ - arm64
+ - hihope_rzg2_defconfig
+
+ * -
+ - Silicon Linux RZ/G2E evaluation kit (EK874)
+ - R8A774C0 (RZ/G2E)
+ - arm64
+ - silinux_ek874_defconfig
+
+ * -
+ - Beacon EmbeddedWorks RZ/G2H SoM
+ - R8A774E1 (RZ/G2H)
+ - arm64
+ - rzg2_beacon_defconfig
+
+ * -
+ - HopeRun HiHope RZ/G2H
+ - R8A774E1 (RZ/G2H)
+ - arm64
+ - hihope_rzg2_defconfig
+
+ * - :doc:`RZ/N1 Family <rzn1>`
+ - Schneider RZ/N1D board
+ - R9A06G032 (RZ/N1D)
+ - arm64
+ - rzn1_snarc_defconfig
+
+ * -
+ - Schneider RZ/N1S board
+ - R9A06G033 (RZ/N1S)
+ - arm64
+ - rzn1_snarc_defconfig
+
+Build
+-----
+
+Locate the appropriate defconfig in the table above. Then apply standard build
+procedure::
+
+ make <board_defconfig>
+ make
diff --git a/doc/board/rockchip/index.rst b/doc/board/rockchip/index.rst
index 0c377e9..9a87a03 100644
--- a/doc/board/rockchip/index.rst
+++ b/doc/board/rockchip/index.rst
@@ -8,3 +8,4 @@
:maxdepth: 2
rockchip
+ rkmtd
diff --git a/doc/board/rockchip/rkmtd.rst b/doc/board/rockchip/rkmtd.rst
new file mode 100644
index 0000000..1481380
--- /dev/null
+++ b/doc/board/rockchip/rkmtd.rst
@@ -0,0 +1,105 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2023 Johan Jonker <jbx6244@gmail.com>
+
+RKMTD
+=====
+
+Info
+----
+
+The command rkmtd creates a virtual block device to transfer
+Rockchip boot block data to and from NAND with block orientated
+tools like "ums" and "rockusb".
+
+It uses the Rockchip MTD driver to scan for boot blocks and copies
+data from the first block in a GPT formatted virtual disk.
+Data must be written in U-boot "idbloader.img" format and start at
+partition "loader1" offset 64. The data header is parsed
+for length and offset. When the last sector is received
+it erases up to 5 erase blocks on NAND and writes boot blocks
+in a pattern depending on the NAND ID. Data is then verified.
+When a block turns out bad the block header is discarded.
+
+Limitations
+-----------
+
+- Support with CONFIG_ROCKCHIP_NAND MTD driver only.
+- Support for Rockchip boot block header type 1 only.
+- Pattern for listed NAND IDs only. (Logic still not disclosed by Rockchip)
+- The MTD framework driver data and NAND ID must be extracted at a lower level.
+
+Available rkmtd commands
+------------------------
+
+.. code-block:: bash
+
+ rkmtd bind <label> - bind RKMTD device
+ rkmtd unbind <label> - unbind RKMTD device
+ rkmtd info [<label>] - show all available RKMTD devices
+ rkmtd dev [<label>] - show or set current RKMTD device
+
+U-boot settings
+---------------
+
+Config to enable Rockchip MTD support:
+
+.. code-block:: bash
+
+ CONFIG_MTD=y
+ CONFIG_MTD_RAW_NAND=y
+ CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT=y
+ CONFIG_SYS_NAND_USE_FLASH_BBT=y
+ CONFIG_ROCKCHIP_NAND=y
+
+Option to keep existing NAND data unchanged:
+
+.. code-block:: bash
+
+ CONFIG_ROCKCHIP_NAND_SKIP_BBTSCAN=y
+
+Commands to enable:
+
+.. code-block:: bash
+
+ CONFIG_CMD_USB=y
+ CONFIG_CMD_RKMTD=y
+ CONFIG_CMD_ROCKUSB=y
+ CONFIG_CMD_USB_MASS_STORAGE=y
+
+Linux Host (PC) tool commands combinations that work
+----------------------------------------------------
+
+.. table::
+ :widths: 20 44
+
+ ==================== ============================================
+ U-boot Linux
+ ==================== ============================================
+ rkmtd bind 0
+ rockusb 0 rkmtd 0
+ upgrade_tool pl
+
+ upgrade_tool rl 64 512 idbloader_backup.img
+
+ upgrade_tool wl 64 idbloader.img
+
+ upgrade_tool rd
+
+ rkdeveloptool ppt
+
+ rkdeveloptool rl 64 512 idbloader_backup.img
+
+ rkdeveloptool wlx loader1 idbloader.img
+
+ rkdeveloptool wl 64 idbloader.img
+
+ rkdeveloptool rd
+
+ rkflashtool r 64 512 > idbloader_backup.img
+
+ rkflashtool w 64 512 < idbloader.img
+ ums 0 rkmtd 0
+ dd if=/dev/sda1 of=idbloader_backup.img
+
+ dd if=idbloader.img of=/dev/sda1
+ ==================== ============================================
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index de9fe8e..18d0b6f 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -53,6 +53,7 @@
- Google Speedy (chromebook_speedy)
- Amarula Vyasa-RK3288 (vyasa-rk3288)
* rk3308
+ - Radxa ROCK Pi S (rock-pi-s-rk3308)
- Rockchip Evb-RK3308 (evb-rk3308)
- Roc-cc-RK3308 (roc-cc-rk3308)
* rk3326
@@ -101,9 +102,11 @@
* rk3568
- Rockchip Evb-RK3568 (evb-rk3568)
+ - Banana Pi BPI-R2 Pro (bpi-r2-pro-rk3568)
- EmbedFire LubanCat 2 (lubancat-2-rk3568)
- FriendlyElec NanoPi R5C (nanopi-r5c-rk3568)
- FriendlyElec NanoPi R5S (nanopi-r5s-rk3568)
+ - Generic RK3566/RK3568 (generic-rk3568)
- Hardkernel ODROID-M1 (odroid-m1-rk3568)
- Radxa E25 Carrier Board (radxa-e25-rk3568)
- Radxa ROCK 3 Model A (rock-3a-rk3568)
@@ -112,8 +115,12 @@
- Rockchip EVB (evb-rk3588)
- Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588)
- Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588)
+ - FriendlyElec NanoPC-T6 (nanopc-t6-rk3588)
+ - Pine64 QuartzPro64 (quartzpro64-rk3588)
- Radxa ROCK 5A (rock5a-rk3588s)
- Radxa ROCK 5B (rock5b-rk3588)
+ - Xunlong Orange Pi 5 (orangepi-5-rk3588s)
+ - Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588)
* rv1108
- Rockchip Evb-rv1108 (evb-rv1108)
@@ -142,6 +149,19 @@
Specify the PLAT= with desired Rockchip platform to build TF-A for.
+For SoCs whose TF-A code is not available as open source, use BL31 binary provided by Rockchip:
+
+.. code-block:: bash
+
+ git clone --depth 1 https://github.com/rockchip-linux/rkbin
+
+TPL
+^^^
+
+For some SoCs U-Boot sources lack of support to inizialize DRAM.
+In these cases, to get a fully functional image following :ref:`PackageWithTPLandSPL`, use DDR binary provided by Rockchip rkbin repository as ROCKCHIP_TPL when building U-Boot.
+Otherwise, follow :ref:`PackageWithRockchipMiniloader`.
+
U-Boot
^^^^^^
@@ -172,6 +192,15 @@
make evb-rk3288_defconfig
make CROSS_COMPILE=arm-linux-gnueabihf-
+To build rk3308 boards:
+
+.. code-block:: bash
+
+ export BL31=../rkbin/bin/rk33/rk3308_bl31_v2.26.elf
+ export ROCKCHIP_TPL=../rkbin/bin/rk33/rk3308_ddr_589MHz_uartX_mY_v2.07.bin
+ make evb-rk3308_defconfig
+ make CROSS_COMPILE=aarch64-linux-gnu-
+
To build rk3328 boards:
.. code-block:: bash
@@ -218,11 +247,13 @@
Flashing
--------
+.. _`PackageWithTPLandSPL`:
+
1. Package the image with U-Boot TPL/SPL
------------------------------------------
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
SD Card
-^^^^^^^
+"""""""
All Rockchip platforms (except rk3128 which doesn't use SPL) are now
supporting a single boot image using binman.
@@ -235,7 +266,7 @@
sync
eMMC
-^^^^
+""""
eMMC flash would probe on mmc0 in most of the Rockchip platforms.
@@ -274,7 +305,7 @@
is u-boot-dtb.img
SPI
-^^^
+"""
Write u-boot-rockchip-spi.bin to offset 0 of SPI flash.
@@ -286,8 +317,10 @@
load mmc 1:1 $kernel_addr_r u-boot-rockchip-spi.bin
sf update $fileaddr 0 $filesize
+.. _`PackageWithRockchipMiniloader`:
+
2. Package the image with Rockchip miniloader
----------------------------------------------
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Image package with Rockchip miniloader requires rkbin [1].
@@ -327,14 +360,14 @@
2. 0x200000 is a load address and is an option for some platforms.
3. Package the RK3066 image with U-Boot TPL/SPL on NAND
--------------------------------------------------------
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Unlike later SoC models the rk3066 BootROM doesn't have SDMMC support.
If all other boot options fail then it enters into a BootROM mode on the USB OTG port.
This method loads TPL/SPL on NAND with U-Boot and kernel on SD card.
SD Card
-^^^^^^^
+"""""""
U-Boot expects a GPT partition map and a boot directory structure with files on the SD card.
@@ -369,7 +402,7 @@
sync
NAND
-^^^^
+""""
Bring device in BootROM mode:
diff --git a/doc/board/samsung/index.rst b/doc/board/samsung/index.rst
index c904372..971805e 100644
--- a/doc/board/samsung/index.rst
+++ b/doc/board/samsung/index.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+
Samsung
-========
+=======
.. toctree::
:maxdepth: 2
diff --git a/doc/board/socionext/developerbox.rst b/doc/board/socionext/developerbox.rst
index aa7080e..46712c3 100644
--- a/doc/board/socionext/developerbox.rst
+++ b/doc/board/socionext/developerbox.rst
@@ -42,9 +42,10 @@
You can build U-Boot without any additinal source code.::
cd u-boot
+ git checkout v2023.07
export ARCH=arm64
export CROSS_COMPILE=aarch64-linux-gnu-
- make SynQuacer_defconfig
+ make synquacer_developerbox_defconfig
make -j `noproc`
Then, expand the binary to 1MB for preparing flash.::
@@ -211,8 +212,8 @@
Once the flasher tool is running we are ready to flash the images.::
Write the FIP image to the Bank-0 & 1 at 6MB and 10MB offset.::
- flash rawwrite 600000 180000
- flash rawwrite a00000 180000
+ flash rawwrite 600000 400000
+ flash rawwrite a00000 400000
>> Send SPI_NOR_NEWFIP.fd via XMODEM (Control-A S in minicom) <<
flash rawwrite 500000 1000
diff --git a/doc/board/st/st-dt.rst b/doc/board/st/st-dt.rst
index 67e16ef..2a285c8 100644
--- a/doc/board/st/st-dt.rst
+++ b/doc/board/st/st-dt.rst
@@ -2,7 +2,7 @@
.. sectionauthor:: Patrick Delaunay <patrick.delaunay@foss.st.com>
U-Boot device tree bindings
-----------------------------
+---------------------------
The U-Boot specific bindings are defined in the U-Boot directory:
doc/device-tree-bindings
diff --git a/doc/board/st/stm32_MCU.rst b/doc/board/st/stm32_MCU.rst
index 7ff7c73..61650bc 100644
--- a/doc/board/st/stm32_MCU.rst
+++ b/doc/board/st/stm32_MCU.rst
@@ -2,7 +2,7 @@
.. sectionauthor:: Patrice Chotard <patrice.chotardy@foss.st.com>
STM32 MCU boards
-=================
+================
This is a quick instruction for setup STM32 MCU boards.
diff --git a/doc/board/starfive/visionfive2.rst b/doc/board/starfive/visionfive2.rst
index 460f23a..6cb033e 100644
--- a/doc/board/starfive/visionfive2.rst
+++ b/doc/board/starfive/visionfive2.rst
@@ -4,7 +4,8 @@
====================
JH7110 RISC-V SoC
----------------------
+-----------------
+
The JH7110 is 4+1 64-bit RISC-V SoC from StarFive.
The StarFive VisionFive2 development platform is based on JH7110 and capable
@@ -67,18 +68,8 @@
make starfive_visionfive2_defconfig
make OPENSBI=$(opensbi_dir)/opensbi/build/platform/generic/firmware/fw_dynamic.bin
-This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
-
-u-boot-spl.bin cannot be used directly on StarFive VisionFive2,we need
-to convert the u-boot-spl.bin to u-boot-spl.bin.normal.out with
-the below command:
-
- ./spl_tool -c -f $(Uboot_PATH)/spl/u-boot-spl.bin
-
-More detailed description of spl_tool,please refer spl_tool documenation.
-(Note: spl_tool git repo is at https://github.com/starfive-tech/Tools/tree/master/spl_tool)
-
-This will generate u-boot-spl.bin.normal.out file.
+This will generate the U-Boot SPL image (spl/u-boot-spl.bin.normal.out) as well
+as the FIT image (u-boot.itb) with OpenSBI and U-Boot.
Flashing
~~~~~~~~
diff --git a/doc/board/thead/index.rst b/doc/board/thead/index.rst
index 41566d3..2c4b3fb 100644
--- a/doc/board/thead/index.rst
+++ b/doc/board/thead/index.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+
T-HEAD
-========
+======
.. toctree::
:maxdepth: 1
diff --git a/doc/board/ti/am335x_evm.rst b/doc/board/ti/am335x_evm.rst
index 2ba651e..7a3125d 100644
--- a/doc/board/ti/am335x_evm.rst
+++ b/doc/board/ti/am335x_evm.rst
@@ -59,7 +59,7 @@
devices are part of a secure development package (SECDEV) that can be
downloaded from:
- http://www.ti.com/mysecuresoftware (login required)
+ https://www.ti.com/mysecuresoftware (login required)
The secure development package is access controlled due to NDA and export
control restrictions. Access must be requested and granted by TI before the
@@ -84,8 +84,7 @@
Within the SECDEV package exists an image creation script:
-.. prompt:: bash
- :prompts: $
+.. prompt:: bash $
${TI_SECURE_DEV_PKG}/scripts/create-boot-image.sh
@@ -97,8 +96,7 @@
The script is basically the only required interface to the TI SECDEV
package for creating a bootable SPL image for secure TI devices.
-.. prompt:: bash
- :prompts: $
+.. prompt:: bash $
create-boot-image.sh \
<IMAGE_FLAG> <INPUT_FILE> <OUTPUT_FILE> <SPL_LOAD_ADDR>
@@ -184,8 +182,7 @@
SECDEV package. Within the SECDEV package exists a script to process
an input binary image:
-.. prompt:: bash
- :prompts: $
+.. prompt:: bash $
${TI_SECURE_DEV_PKG}/scripts/secure-binary-image.sh
@@ -206,8 +203,7 @@
Invoking the secure-binary-image script for Secure Devices
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-.. prompt:: bash
- :prompts: $
+.. prompt:: bash $
secure-binary-image.sh <INPUT_FILE> <OUTPUT_FILE>
@@ -247,8 +243,7 @@
2. Flashing NAND via MMC/SD
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
# select BOOTSEL to MMC/SD boot and boot from MMC/SD card
mmc rescan
@@ -334,8 +329,7 @@
write garbage into the area, you must delete it from the partition table
first.
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
# Ensure we are able to talk with this mmc device
mmc rescan
@@ -366,8 +360,7 @@
afterwards) along with a Falcon Mode aware MLO and the FAT partition has
already been created and marked bootable:
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
mmc rescan
# Load kernel and device tree into memory, perform export
@@ -386,8 +379,7 @@
So then you:
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
fatwrite mmc 0:1 0x80f80000 args 8928
@@ -400,8 +392,7 @@
along with a Falcon Mode aware MLO written to the correct locations for
booting and mtdparts have been configured correctly for the board:
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
nand read ${loadaddr} kernel
load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb
@@ -425,8 +416,7 @@
device, so the user can easily configure their platform differently from
the command line:
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
dm tree
@@ -444,8 +434,7 @@
Typically here any network command performed using the usb_ether
interface would work, while using other gadgets would fail:
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
fastboot usb 0
@@ -462,8 +451,7 @@
use the unbind command specifying the class and index parameters (as
shown above in the 'dm tree' output) to target the driver to unbind:
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
unbind ethernet 1
@@ -471,8 +459,7 @@
first USB device controller, the fastboot gadget will now be able to
bind with it:
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
dm tree
diff --git a/doc/board/ti/am62x_beagleplay.rst b/doc/board/ti/am62x_beagleplay.rst
new file mode 100644
index 0000000..44e728d
--- /dev/null
+++ b/doc/board/ti/am62x_beagleplay.rst
@@ -0,0 +1,322 @@
+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+.. sectionauthor:: Nishanth Menon <nm@ti.com>
+
+AM62x Beagleboard.org Beagleplay
+================================
+
+Introduction:
+-------------
+
+BeagleBoard.org BeaglePlay is an easy to use, affordable open source
+hardware single board computer based on the Texas Instruments AM625
+SoC that allows you to create connected devices that work even at long
+distances using IEEE 802.15.4g LR-WPAN and IEEE 802.3cg 10Base-T1L.
+Expansion is provided over open standards based mikroBUS, Grove and
+QWIIC headers among other interfaces.
+
+Further information can be found at:
+
+* Product Page: https://beagleplay.org/
+* Hardware documentation: https://git.beagleboard.org/beagleplay/beagleplay
+
+Boot Flow:
+----------
+Below is the pictorial representation of boot flow:
+
+.. image:: img/boot_diagram_k3_current.svg
+ :alt: Boot flow diagram
+
+- On this platform, 'TI Foundational Security' (TIFS) functions as the
+ security enclave master while 'Device Manager' (DM), also known as the
+ 'TISCI server' in "TI terminology", offers all the essential services.
+ The A53 or M4F (Aux core) sends requests to TIFS/DM to accomplish these
+ services, as illustrated in the diagram above.
+
+Sources:
+--------
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_boot_sources
+ :end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure:
+----------------
+0. Setup the environment variables:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_desc
+ :end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_board_env_vars_desc
+ :end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_defn
+ :end-before: .. k3_rst_include_end_common_env_vars_defn
+.. prompt:: bash $
+
+ export UBOOT_CFG_CORTEXR="am62x_evm_r5_defconfig beagleplay_r5.config"
+ export UBOOT_CFG_CORTEXA="am62x_evm_a53_defconfig beagleplay_a53.config"
+ export TFA_BOARD=lite
+ # we dont use any extra TFA parameters
+ unset TFA_EXTRA_ARGS
+ export OPTEE_PLATFORM=k3-am62x
+ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
+
+.. include:: am62x_sk.rst
+ :start-after: .. am62x_evm_rst_include_start_build_steps
+ :end-before: .. am62x_evm_rst_include_end_build_steps
+
+Target Images
+-------------
+Copy the below images to an SD card and boot:
+
+* tiboot3-am62x-gp-evm.bin from R5 build as tiboot3.bin
+* tispl.bin_unsigned from Cortex-A build as tispl.bin
+* u-boot.img_unsigned from Cortex-A build as u-boot.img
+
+Image formats
+-------------
+
+- tiboot3.bin
+
+.. image:: img/multi_cert_tiboot3.bin.svg
+ :alt: tiboot3.bin image format
+
+- tispl.bin
+
+.. image:: img/dm_tispl.bin.svg
+ :alt: tispl.bin image format
+
+Additional hardware for U-Boot development
+------------------------------------------
+
+* Serial Console is critical for U-Boot development on BeaglePlay. See
+ `BeaglePlay serial console documentation
+ <https://docs.beagleboard.org/latest/boards/beagleplay/demos-and-tutorials/using-serial-console.html>`_.
+* uSD is preferred option over eMMC, and a SD/MMC reader will be needed.
+* (optionally) JTAG is useful when working with very early stages of boot.
+
+Default storage options
+-----------------------
+
+There are multiple storage media options on BeaglePlay, but primarily:
+
+* Onboard eMMC (default) - reliable, fast and meant for deployment use.
+* SD/MMC card interface (hold 'USR' switch and power on) - Entirely
+ depends on the SD card quality.
+
+Flash to uSD card or how to deal with "bricked" Board
+-----------------------------------------------------
+
+When deploying or working on Linux, it's common to use the onboard
+eMMC. However, avoiding the eMMC and using the uSD card is safer when
+working with U-Boot.
+
+If you choose to hand format your own bootable uSD card, be
+aware that it can be difficult. The following information
+may be helpful, but remember that it is only sometimes
+reliable, and partition options can cause issues. These
+can potentially help:
+
+* https://git.ti.com/cgit/arago-project/tisdk-setup-scripts/tree/create-sdcard.sh
+* https://elinux.org/Beagleboard:Expanding_File_System_Partition_On_A_microSD
+
+The simplest option is to start with a standard distribution
+image like those in `BeagleBoard.org Distros Page
+<https://www.beagleboard.org/distros>`_ and download a disk image for
+BeaglePlay. Pick a 16GB+ uSD card to be on the safer side.
+
+With an SD/MMC Card reader and `Balena Etcher
+<https://etcher.balena.io/>`_, having a functional setup in minutes is
+a trivial matter, and it works on almost all Host Operating Systems.
+Yes Windows users, Windows Subsystem for Linux(WSL) based development
+with U-Boot and update uSD card is practical.
+
+Updating U-Boot is a matter of copying the tiboot3.bin, tispl.bin and
+u-boot.img to the "BOOT" partition of the uSD card. Remember to sync
+and unmount (or Eject - depending on the Operating System) the uSD
+card prior to physically removing from SD card reader.
+
+Also see following section on switch setting used for booting using
+uSD card.
+
+.. note::
+ Great news! If the board has not been damaged physically, there's no
+ need to worry about it being "bricked" on this platform. You only have
+ to flash an uSD card, plug it in, and reinstall the image on eMMC. This
+ means that even if you make a mistake, you can quickly fix it and rest
+ easy.
+
+ If you are frequently working with uSD cards, you might find the
+ following useful:
+
+ * `USB-SD-Mux <https://www.linux-automation.com/en/products/usb-sd-mux.html>`_
+ * `SD-Wire <https://wiki.tizen.org/SDWire>`_
+
+Flash to eMMC
+-------------
+
+The eMMC layout selected is user-friendly for developers. The
+boot hardware partition of the eMMC only contains the fixed-size
+tiboot3.bin image. This is because the contents of the boot partitions
+need to run from the SoC's internal SRAM, which remains a fixed size
+constant. The other components of the boot sequence, such as tispl.bin
+and u-boot.img, are located in the /BOOT partition in the User Defined
+Area (UDA) hardware partition of the eMMC. These components can vary
+significantly in size. The choice of keeping tiboot3.bin in boot0 or
+boot1 partition depends on A/B update requirements.
+
+.. image:: img/beagleplay_emmc.svg
+ :alt: eMMC partitions and boot file organization for BeaglePlay
+
+The following are the steps from Linux shell to program eMMC:
+
+.. prompt:: bash #
+
+ # Enable Boot0 boot
+ mmc bootpart enable 1 2 /dev/mmcblk0
+ mmc bootbus set single_backward x1 x8 /dev/mmcblk0
+ mmc hwreset enable /dev/mmcblk0
+
+ # Clear eMMC boot0
+ echo '0' >> /sys/class/block/mmcblk0boot0/force_ro
+ dd if=/dev/zero of=/dev/mmcblk0boot0 count=32 bs=128k
+ # Write tiboot3.bin
+ dd if=tiboot3.bin of=/dev/mmcblk0boot0 bs=128k
+
+ # Copy the rest of the boot binaries
+ mount /dev/mmcblk0p1 /boot/firmware
+ cp tispl.bin /boot/firmware
+ cp u-boot.img /boot/firmware
+ sync
+
+.. warning ::
+
+ U-Boot is configured to prioritize booting from an SD card if it
+ detects a valid boot partition and boot files on it, even if the
+ system initially booted from eMMC. The boot order is set as follows:
+
+ * SD/MMC
+ * eMMC
+ * USB
+ * PXE
+
+LED patterns during boot
+------------------------
+
+.. list-table:: USR LED status indication
+ :widths: 16 16
+ :header-rows: 1
+
+ * - USR LEDs (012345)
+ - Indicates
+
+ * - 00000
+ - Boot failure or R5 image not started up
+
+ * - 11111
+ - A53 SPL/U-boot has started up
+
+ * - 10101
+ - OS boot process has been initiated
+
+ * - 01010
+ - OS boot process failed and drops to U-Boot shell
+
+.. note ::
+
+ In the table above, 0 indicates LED switched off and 1 indicates LED
+ switched ON.
+
+.. warning ::
+
+ If the "red" power LED is not glowing, the system power supply is not
+ functional. Please refer to `BeaglePlay documentation
+ <https://beagleplay.org/>`_ for further information.
+
+A53 SPL DDR Memory Layout
+-------------------------
+
+.. include:: am62x_sk.rst
+ :start-after: .. am62x_evm_rst_include_start_ddr_mem_layout
+ :end-before: .. am62x_evm_rst_include_end_ddr_mem_layout
+
+Switch Setting for Boot Mode
+----------------------------
+
+The boot time option is configured via "USR" button on the board.
+See `Beagleplay Schematics <https://git.beagleboard.org/beagleplay/beagleplay/-/blob/main/BeaglePlay_sch.pdf>`_
+for details.
+
+.. list-table:: Boot Modes
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - USR Switch Position
+ - Primary Boot
+ - Secondary Boot
+
+ * - Not Pressed
+ - eMMC
+ - UART
+
+ * - Pressed
+ - SD/MMC File System (FS) mode
+ - USB Device Firmware Upgrade (DFU) mode
+
+To switch to SD card boot mode, hold the USR button while powering on
+with Type-C power supply, then release when power LED lights up.
+
+Debugging U-Boot
+----------------
+
+See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
+detailed setup and debugging information.
+
+.. warning::
+
+ **OpenOCD support since**: v0.12.0
+
+ If the default package version of OpenOCD in your development
+ environment's distribution needs to be updated, it might be necessary to
+ build OpenOCD from the source.
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_openocd_connect_tag_connect
+ :end-before: .. k3_rst_include_end_openocd_connect_tag_connect
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_openocd_cfg_external_intro
+ :end-before: .. k3_rst_include_end_openocd_cfg_external_intro
+
+For example, with BeaglePlay (AM62X platform), the openocd_connect.cfg:
+
+.. code-block:: tcl
+
+ # TUMPA example:
+ # http://www.tiaowiki.com/w/TIAO_USB_Multi_Protocol_Adapter_User's_Manual
+ source [find interface/ftdi/tumpa.cfg]
+
+ transport select jtag
+
+ # default JTAG configuration has only SRST and no TRST
+ reset_config srst_only srst_push_pull
+
+ # delay after SRST goes inactive
+ adapter srst delay 20
+
+ if { ![info exists SOC] } {
+ # Set the SoC of interest
+ set SOC am625
+ }
+
+ source [find target/ti_k3.cfg]
+
+ ftdi tdo_sample_edge falling
+
+ # Speeds for FT2232H are in multiples of 2, and 32MHz is tops
+ # max speed we seem to achieve is ~20MHz.. so we pick 16MHz
+ adapter speed 16000
diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst
index d7437c6..b12dc85 100644
--- a/doc/board/ti/am62x_sk.rst
+++ b/doc/board/ti/am62x_sk.rst
@@ -2,7 +2,7 @@
.. sectionauthor:: Vignesh Raghavendra <vigneshr@ti.com>
AM62 Platforms
-===============
+==============
Introduction:
-------------
@@ -76,15 +76,15 @@
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
-.. code-block:: bash
+.. prompt:: bash $
- $ export UBOOT_CFG_CORTEXR=am62x_evm_r5_defconfig
- $ export UBOOT_CFG_CORTEXA=am62x_evm_a53_defconfig
- $ export TFA_BOARD=lite
- $ # we dont use any extra TFA parameters
- $ unset TFA_EXTRA_ARGS
- $ export OPTEE_PLATFORM=k3-am62x
- $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
+ export UBOOT_CFG_CORTEXR=am62x_evm_r5_defconfig
+ export UBOOT_CFG_CORTEXA=am62x_evm_a53_defconfig
+ export TFA_BOARD=lite
+ # we dont use any extra TFA parameters
+ unset TFA_EXTRA_ARGS
+ export OPTEE_PLATFORM=k3-am62x
+ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
.. am62x_evm_rst_include_start_build_steps
@@ -117,7 +117,8 @@
.. am62x_evm_rst_include_end_build_steps
Target Images
---------------
+-------------
+
In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
variant (GP, HS-FS, HS-SE) requires a different source for these files.
@@ -270,6 +271,6 @@
To start OpenOCD and connect to the board
-.. code-block:: bash
+.. prompt:: bash $
openocd -f board/ti_am625evm.cfg
diff --git a/doc/board/ti/am64x_evm.rst b/doc/board/ti/am64x_evm.rst
new file mode 100644
index 0000000..6ae35b3
--- /dev/null
+++ b/doc/board/ti/am64x_evm.rst
@@ -0,0 +1,201 @@
+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+.. sectionauthor:: Nishanth Menon <nm@ti.com>
+
+AM64 Platforms
+==============
+
+Introduction:
+-------------
+The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
+providing advanced system integration to enable applications such as
+Motor Drives, PLC, Remote IO and IoT Gateways.
+
+Some highlights of this SoC are:
+
+* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
+ MCUs, and a single Cortex-M4F.
+* Two Gigabit Industrial Communication Subsystems (ICSSG).
+* Integrated Ethernet switch supporting up to a total of two external
+ ports.
+* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
+ controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
+ peripherals.
+* Centralized System Controller for Security, Power, and Resource
+ Management (DMSC).
+
+More details can be found in the Technical Reference Manual:
+ https://www.ti.com/lit/pdf/spruim2
+
+Platform information:
+
+* AM64-EVM: https://www.ti.com/tool/TMDS64EVM
+* AM64-SK: https://www.ti.com/tool/SK-AM64B
+
+Boot Flow:
+----------
+Below is the pictorial representation of boot flow:
+
+.. image:: img/boot_diagram_am64.svg
+ :alt: Boot flow diagram
+
+- Here TIFS acts as master and provides all the critical services. R5/A53
+ requests TIFS to get these services done as shown in the above diagram.
+
+Sources:
+--------
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_boot_sources
+ :end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure:
+----------------
+0. Setup the environment variables:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_desc
+ :end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_board_env_vars_desc
+ :end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_defn
+ :end-before: .. k3_rst_include_end_common_env_vars_defn
+.. prompt:: bash $
+
+ export UBOOT_CFG_CORTEXR=am64x_evm_r5_defconfig
+ export UBOOT_CFG_CORTEXA=am64x_evm_a53_defconfig
+ export TFA_BOARD=lite
+ # we dont use any extra TFA parameters
+ unset TFA_EXTRA_ARGS
+ export OPTEE_PLATFORM=k3-am64x
+ # we dont use any extra TFA parameters
+ unset OPTEE_EXTRA_ARGS
+
+.. am64x_evm_rst_include_start_build_steps
+
+1. Trusted Firmware-A:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_tfa
+ :end-before: .. k3_rst_include_end_build_steps_tfa
+
+
+2. OP-TEE:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_optee
+ :end-before: .. k3_rst_include_end_build_steps_optee
+
+3. U-Boot:
+
+* 3.1 R5:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_spl_r5
+ :end-before: .. k3_rst_include_end_build_steps_spl_r5
+
+* 3.2 A53:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_uboot
+ :end-before: .. k3_rst_include_end_build_steps_uboot
+.. am64x_evm_rst_include_end_build_steps
+
+Target Images
+-------------
+
+In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
+variant (GP, HS-FS, HS-SE) requires a different source for these files.
+
+ - GP
+
+ * tiboot3-am64x-gp-evm.bin from step 3.1
+ * tispl.bin_unsigned, u-boot.img_unsigned from step 3.2
+
+ - HS-FS
+
+ * tiboot3-am64x-hs-fs-evm.bin from step 3.1
+ * tispl.bin, u-boot.img from step 3.2
+
+ - HS-SE
+
+ * tiboot3-am64x-hs-evm.bin from step 3.1
+ * tispl.bin, u-boot.img from step 3.2
+
+Image formats:
+--------------
+
+- tiboot3.bin
+
+.. image:: img/multi_cert_tiboot3.bin.svg
+ :alt: tiboot3.bin image format
+
+- tispl.bin
+
+.. image:: img/nodm_tispl.bin.svg
+ :alt: tispl.bin image format
+
+Switch Setting for Boot Mode
+----------------------------
+
+Boot Mode pins provide means to select the boot mode and options before the
+device is powered up. After every POR, they are the main source to populate
+the Boot Parameter Tables.
+
+The following table shows some common boot modes used on AM64 platform. More
+details can be found in the Technical Reference Manual:
+https://www.ti.com/lit/pdf/spruim2 under the `Boot Mode Pins` section.
+
+.. list-table:: Boot Modes for AM64x-EVM
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Switch Label
+ - SW2: 12345678
+ - SW3: 12345678
+
+ * - SD/MMC
+ - 11000010
+ - 01000000
+
+ * - xSPI/SFDP (OSPI)
+ - 11001110
+ - 01000000
+
+ * - UART
+ - 11011100
+ - 00000000
+
+.. note ::
+
+ For SW2 and SW3, the switch state in the "ON" position = 1.
+
+.. list-table:: Boot Modes for AM64x-SK
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Switch Label
+ - SW2: 12345678
+ - SW3: 12345678
+
+ * - SD/MMC
+ - 00000010
+ - 01000011
+
+ * - xSPI/SFDP (OSPI)
+ - 00000010
+ - 01110011
+
+ * - UART
+ - 00000000
+ - 00111011
+
+.. note ::
+
+ For SW2 and SW3, the switch state in the "ON" position = 1.
+ Boot bits on SK is reversed bits to the bootmode signals
diff --git a/doc/board/ti/am65x_evm.rst b/doc/board/ti/am65x_evm.rst
index 7cebb1c..89011c0 100644
--- a/doc/board/ti/am65x_evm.rst
+++ b/doc/board/ti/am65x_evm.rst
@@ -22,7 +22,7 @@
3. MAIN domain:
* Quad core 64-bit ARM Cortex-A53
-More info can be found in TRM: http://www.ti.com/lit/pdf/spruid7
+More info can be found in TRM: https://www.ti.com/lit/pdf/spruid7
Platform information:
@@ -75,16 +75,16 @@
.. include:: k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
-.. code-block:: bash
+.. prompt:: bash $
- $ export UBOOT_CFG_CORTEXR=am65x_evm_r5_defconfig
- $ export UBOOT_CFG_CORTEXA=am65x_evm_a53_defconfig
- $ export TFA_BOARD=generic
- $ # we dont use any extra TFA parameters
- $ unset TFA_EXTRA_ARGS
- $ export OPTEE_PLATFORM=k3-am65x
- $ # we dont use any extra OP-TEE parameters
- $ unset OPTEE_EXTRA_ARGS
+ export UBOOT_CFG_CORTEXR=am65x_evm_r5_defconfig
+ export UBOOT_CFG_CORTEXA=am65x_evm_a53_defconfig
+ export TFA_BOARD=generic
+ # we dont use any extra TFA parameters
+ unset TFA_EXTRA_ARGS
+ export OPTEE_PLATFORM=k3-am65x
+ # we dont use any extra OP-TEE parameters
+ unset OPTEE_EXTRA_ARGS
.. am65x_evm_rst_include_start_build_steps
@@ -117,7 +117,8 @@
.. am65x_evm_rst_include_end_build_steps
Target Images
---------------
+-------------
+
In order to boot we need tiboot3.bin, sysfw.itb, tispl.bin and u-boot.img.
Each SoC variant (GP and HS) requires a different source for these files.
@@ -159,32 +160,32 @@
u-boot.img, and sysfw.itb from an SD card and write them to the eMMC boot0
partition at respective addresses.
-.. code-block:: text
+.. prompt:: bash =>
- => mmc dev 0 1
- => fatload mmc 1 ${loadaddr} tiboot3.bin
- => mmc write ${loadaddr} 0x0 0x400
- => fatload mmc 1 ${loadaddr} tispl.bin
- => mmc write ${loadaddr} 0x400 0x1000
- => fatload mmc 1 ${loadaddr} u-boot.img
- => mmc write ${loadaddr} 0x1400 0x2000
- => fatload mmc 1 ${loadaddr} sysfw.itb
- => mmc write ${loadaddr} 0x3600 0x800
+ mmc dev 0 1
+ fatload mmc 1 ${loadaddr} tiboot3.bin
+ mmc write ${loadaddr} 0x0 0x400
+ fatload mmc 1 ${loadaddr} tispl.bin
+ mmc write ${loadaddr} 0x400 0x1000
+ fatload mmc 1 ${loadaddr} u-boot.img
+ mmc write ${loadaddr} 0x1400 0x2000
+ fatload mmc 1 ${loadaddr} sysfw.itb
+ mmc write ${loadaddr} 0x3600 0x800
To give the ROM access to the boot partition, the following commands must be
used for the first time:
-.. code-block:: text
+.. prompt:: bash =>
- => mmc partconf 0 1 1 1
- => mmc bootbus 0 1 0 0
+ mmc partconf 0 1 1 1
+ mmc bootbus 0 1 0 0
To create a software partition for the rootfs, the following command can be
used:
-.. code-block:: text
+.. prompt:: bash =>
- => gpt write mmc 0 ${partitions}
+ gpt write mmc 0 ${partitions}
eMMC layout:
@@ -194,11 +195,11 @@
Kernel image and DT are expected to be present in the /boot folder of rootfs.
To boot kernel from eMMC, use the following commands:
-.. code-block:: text
+.. prompt:: bash =>
- => setenv mmcdev 0
- => setenv bootpart 0
- => boot
+ setenv mmcdev 0
+ setenv bootpart 0
+ boot
OSPI:
-----
@@ -210,17 +211,17 @@
and sysfw.itb over tftp and then flash those to OSPI at their respective
addresses.
-.. code-block:: text
+.. prompt:: bash =>
- => sf probe
- => tftp ${loadaddr} tiboot3.bin
- => sf update $loadaddr 0x0 $filesize
- => tftp ${loadaddr} tispl.bin
- => sf update $loadaddr 0x80000 $filesize
- => tftp ${loadaddr} u-boot.img
- => sf update $loadaddr 0x280000 $filesize
- => tftp ${loadaddr} sysfw.itb
- => sf update $loadaddr 0x6C0000 $filesize
+ sf probe
+ tftp ${loadaddr} tiboot3.bin
+ sf update $loadaddr 0x0 $filesize
+ tftp ${loadaddr} tispl.bin
+ sf update $loadaddr 0x80000 $filesize
+ tftp ${loadaddr} u-boot.img
+ sf update $loadaddr 0x280000 $filesize
+ tftp ${loadaddr} sysfw.itb
+ sf update $loadaddr 0x6C0000 $filesize
Flash layout for OSPI:
@@ -233,10 +234,10 @@
To boot kernel from OSPI, at the U-Boot prompt:
-.. code-block:: text
+.. prompt:: bash =>
- => setenv boot ubi
- => boot
+ setenv boot ubi
+ boot
UART:
-----
@@ -280,19 +281,19 @@
Example bash script sequence for running on a Linux host PC feeding all boot
artifacts needed to the device:
-.. code-block:: text
+.. prompt:: bash $
- MCU_DEV=/dev/ttyUSB1
- MAIN_DEV=/dev/ttyUSB0
+ MCU_DEV=/dev/ttyUSB1
+ MAIN_DEV=/dev/ttyUSB0
- stty -F $MCU_DEV 115200 cs8 -cstopb -parenb
- stty -F $MAIN_DEV 115200 cs8 -cstopb -parenb
+ stty -F $MCU_DEV 115200 cs8 -cstopb -parenb
+ stty -F $MAIN_DEV 115200 cs8 -cstopb -parenb
- sb --xmodem tiboot3.bin > $MCU_DEV < $MCU_DEV
- sb --ymodem sysfw.itb > $MCU_DEV < $MCU_DEV
- sb --ymodem tispl.bin > $MAIN_DEV < $MAIN_DEV
- sleep 1
- sb --xmodem u-boot.img > $MAIN_DEV < $MAIN_DEV
+ sb --xmodem tiboot3.bin > $MCU_DEV < $MCU_DEV
+ sb --ymodem sysfw.itb > $MCU_DEV < $MCU_DEV
+ sb --ymodem tispl.bin > $MAIN_DEV < $MAIN_DEV
+ sleep 1
+ sb --xmodem u-boot.img > $MAIN_DEV < $MAIN_DEV
Debugging U-Boot
----------------
@@ -314,6 +315,6 @@
To start OpenOCD and connect to the board
-.. code-block:: bash
+.. prompt:: bash $
openocd -f board/ti_am654evm.cfg
diff --git a/doc/board/ti/dra7xx_evm.rst b/doc/board/ti/dra7xx_evm.rst
index 4503b5e..8e5d955 100644
--- a/doc/board/ti/dra7xx_evm.rst
+++ b/doc/board/ti/dra7xx_evm.rst
@@ -71,8 +71,7 @@
'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to
set boot0 as the boot device.
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
setenv autoload no
usb start
diff --git a/doc/board/ti/img/beagleplay_emmc.svg b/doc/board/ti/img/beagleplay_emmc.svg
new file mode 100644
index 0000000..c6ff19b
--- /dev/null
+++ b/doc/board/ti/img/beagleplay_emmc.svg
@@ -0,0 +1,697 @@
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diff --git a/doc/board/ti/img/boot_diagram_am64.svg b/doc/board/ti/img/boot_diagram_am64.svg
new file mode 100644
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diff --git a/doc/board/ti/j7200_evm.rst b/doc/board/ti/j7200_evm.rst
index bcf8dc1..d4a823f 100644
--- a/doc/board/ti/j7200_evm.rst
+++ b/doc/board/ti/j7200_evm.rst
@@ -64,16 +64,16 @@
.. include:: k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
-.. code-block:: bash
+.. prompt:: bash $
- $ export UBOOT_CFG_CORTEXR=j7200_evm_r5_defconfig
- $ export UBOOT_CFG_CORTEXA=j7200_evm_a72_defconfig
- $ export TFA_BOARD=generic
- $ # we dont use any extra TFA parameters
- $ unset TFA_EXTRA_ARGS
- $ export OPTEE_PLATFORM=k3-j7200
- $ # we dont use any extra OP-TEE parameters
- $ unset OPTEE_EXTRA_ARGS
+ export UBOOT_CFG_CORTEXR=j7200_evm_r5_defconfig
+ export UBOOT_CFG_CORTEXA=j7200_evm_a72_defconfig
+ export TFA_BOARD=generic
+ # we dont use any extra TFA parameters
+ unset TFA_EXTRA_ARGS
+ export OPTEE_PLATFORM=k3-j7200
+ # we dont use any extra OP-TEE parameters
+ unset OPTEE_EXTRA_ARGS
.. j7200_evm_rst_include_start_build_steps
@@ -106,7 +106,8 @@
.. j7200_evm_rst_include_end_build_steps
Target Images
---------------
+-------------
+
In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
variant (GP, HS-FS, HS-SE) requires a different source for these files.
@@ -225,6 +226,6 @@
To start OpenOCD and connect to the board
-.. code-block:: bash
+.. prompt:: bash $
openocd -f board/ti_j7200evm.cfg
diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst
index cadaac0..113475d 100644
--- a/doc/board/ti/j721e_evm.rst
+++ b/doc/board/ti/j721e_evm.rst
@@ -27,7 +27,7 @@
* 2 x C66x Digital signal processor sub system
* C71x Digital signal processor sub-system with MMA.
-More info can be found in TRM: http://www.ti.com/lit/pdf/spruil1
+More info can be found in TRM: https://www.ti.com/lit/pdf/spruil1
Platform information:
@@ -69,16 +69,16 @@
.. include:: k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
-.. code-block:: bash
+.. prompt:: bash $
- $ export UBOOT_CFG_CORTEXR=j721e_evm_r5_defconfig
- $ export UBOOT_CFG_CORTEXA=j721e_evm_a72_defconfig
- $ export TFA_BOARD=generic
- $ # we dont use any extra TFA parameters
- $ unset TFA_EXTRA_ARGS
- $ export OPTEE_PLATFORM=k3-j721e
- $ # we dont use any extra OP-TEE parameters
- $ unset OPTEE_EXTRA_ARGS
+ export UBOOT_CFG_CORTEXR=j721e_evm_r5_defconfig
+ export UBOOT_CFG_CORTEXA=j721e_evm_a72_defconfig
+ export TFA_BOARD=generic
+ # we dont use any extra TFA parameters
+ unset TFA_EXTRA_ARGS
+ export OPTEE_PLATFORM=k3-j721e
+ # we dont use any extra OP-TEE parameters
+ unset OPTEE_EXTRA_ARGS
.. j721e_evm_rst_include_start_build_steps
@@ -111,7 +111,8 @@
.. j721e_evm_rst_include_end_build_steps
Target Images
---------------
+-------------
+
In order to boot we need tiboot3.bin, sysfw.itb, tispl.bin and u-boot.img.
Each SoC variant (GP, HS-FS and HS-SE) requires a different source for these
files.
@@ -202,17 +203,17 @@
and sysfw.itb over tftp and then flash those to OSPI at their respective
addresses.
-.. code-block:: text
+.. prompt:: bash =>
- => sf probe
- => tftp ${loadaddr} tiboot3.bin
- => sf update $loadaddr 0x0 $filesize
- => tftp ${loadaddr} tispl.bin
- => sf update $loadaddr 0x80000 $filesize
- => tftp ${loadaddr} u-boot.img
- => sf update $loadaddr 0x280000 $filesize
- => tftp ${loadaddr} sysfw.itb
- => sf update $loadaddr 0x6C0000 $filesize
+ sf probe
+ tftp ${loadaddr} tiboot3.bin
+ sf update $loadaddr 0x0 $filesize
+ tftp ${loadaddr} tispl.bin
+ sf update $loadaddr 0x80000 $filesize
+ tftp ${loadaddr} u-boot.img
+ sf update $loadaddr 0x280000 $filesize
+ tftp ${loadaddr} sysfw.itb
+ sf update $loadaddr 0x6C0000 $filesize
Flash layout for OSPI:
@@ -254,6 +255,6 @@
To start OpenOCD and connect to the board
-.. code-block:: bash
+.. prompt:: bash $
openocd -f board/ti_j721eevm.cfg
diff --git a/doc/board/ti/j721s2_evm.rst b/doc/board/ti/j721s2_evm.rst
new file mode 100644
index 0000000..f5c48c9
--- /dev/null
+++ b/doc/board/ti/j721s2_evm.rst
@@ -0,0 +1,345 @@
+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+.. sectionauthor:: Manorit Chawdhry <m-chawdhry@ti.com>
+
+J721S2 and AM68 Platforms
+=========================
+
+Introduction:
+-------------
+
+The J721S2 family of SoCs are part of K3 Multicore SoC architecture platform
+targeting automotive applications. They are designed as a low power, high
+performance and highly integrated device architecture, adding significant
+enhancement on processing power, graphics capability, video and imaging
+processing, virtualization and coherent memory support.
+
+The AM68 Starter Kit/Evaluation Module (EVM) is based on the J721S2 family
+of SoCs. They are designed for machine vision, traffic monitoring, retail
+automation, and factory automation.
+
+The device is partitioned into three functional domains, each containing
+specific processing cores and peripherals:
+
+1. Wake-up (WKUP) domain:
+ * ARM Cortex-M4F processor, runs TI Foundational Security (TIFS)
+
+2. Microcontroller (MCU) domain:
+ * Dual core ARM Cortex-R5F processor, runs device management
+ and SoC early boot
+
+3. MAIN domain:
+ * Dual core 64-bit ARM Cortex-A72, runs HLOS
+
+More info can be found in TRM: https://www.ti.com/lit/pdf/spruj28
+
+Platform information:
+
+* https://www.ti.com/tool/J721S2XSOMXEVM
+* https://www.ti.com/tool/SK-AM68
+
+Boot Flow:
+----------
+
+Below is the pictorial representation of boot flow:
+
+.. image:: img/boot_diagram_k3_current.svg
+
+- On this platform, "TI Foundational Security" (TIFS) functions as the
+ security enclave master while "Device Manager" (DM), also known as the
+ "TISCI server" in TI terminology, offers all the essential services.
+
+- As illustrated in the diagram above, R5 SPL manages power and clock
+ services independently before handing over control to "DM". The A72 or
+ the C7x (Aux core) software components request TIFS/DM to handle
+ security or device management services.
+
+Sources:
+--------
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_boot_sources
+ :end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure:
+----------------
+
+0. Setup the environment variables:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_desc
+ :end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_board_env_vars_desc
+ :end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_defn
+ :end-before: .. k3_rst_include_end_common_env_vars_defn
+.. prompt:: bash $
+
+ export UBOOT_CFG_CORTEXR=j721s2_evm_r5_defconfig
+ export UBOOT_CFG_CORTEXA=j721s2_evm_a72_defconfig
+ export TFA_BOARD=generic
+ export TFA_EXTRA_ARGS="K3_USART=0x8"
+ # The following is not a typo, j784s4 is the OP-TEE platform for j721s2
+ export OPTEE_PLATFORM=k3-j784s4
+ export OPTEE_EXTRA_ARGS="CFG_CONSOLE_UART=0x8"
+
+.. j721s2_evm_rst_include_start_build_steps
+
+1. Trusted Firmware-A:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_tfa
+ :end-before: .. k3_rst_include_end_build_steps_tfa
+
+
+2. OP-TEE:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_optee
+ :end-before: .. k3_rst_include_end_build_steps_optee
+
+3. U-Boot:
+
+.. _j721s2_evm_rst_u_boot_r5:
+
+* 3.1 R5:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_spl_r5
+ :end-before: .. k3_rst_include_end_build_steps_spl_r5
+
+.. _j721s2_evm_rst_u_boot_a72:
+
+* 3.2 A72:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_uboot
+ :end-before: .. k3_rst_include_end_build_steps_uboot
+.. j721s2_evm_rst_include_end_build_steps
+
+Target Images
+-------------
+
+In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
+variant (GP, HS-FS, HS-SE) requires a different source for these files.
+
+ - GP
+
+ * tiboot3-j721s2-gp-evm.bin from :ref:`step 3.1 <j721s2_evm_rst_u_boot_r5>`
+ * tispl.bin_unsigned, u-boot.img_unsigned from :ref:`step 3.2 <j721s2_evm_rst_u_boot_a72>`
+
+ - HS-FS
+
+ * tiboot3-j721s2-hs-fs-evm.bin from :ref:`step 3.1 <j721s2_evm_rst_u_boot_r5>`
+ * tispl.bin, u-boot.img from :ref:`step 3.2 <j721s2_evm_rst_u_boot_a72>`
+
+ - HS-SE
+
+ * tiboot3-j721s2-hs-evm.bin from :ref:`step 3.1 <j721s2_evm_rst_u_boot_r5>`
+ * tispl.bin, u-boot.img from :ref:`step 3.2 <j721s2_evm_rst_u_boot_a72>`
+
+Image formats:
+--------------
+
+- tiboot3.bin
+
+.. image:: img/multi_cert_tiboot3.bin.svg
+
+- tispl.bin
+
+.. image:: img/dm_tispl.bin.svg
+
+R5 Memory Map:
+--------------
+
+.. list-table::
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Region
+ - Start Address
+ - End Address
+
+ * - SPL
+ - 0x41c00000
+ - 0x41c40000
+
+ * - EMPTY
+ - 0x41c40000
+ - 0x41c61f20
+
+ * - STACK
+ - 0x41c65f20
+ - 0x41c61f20
+
+ * - Global data
+ - 0x41c65f20
+ - 0x41c66000
+
+ * - Heap
+ - 0x41c66000
+ - 0x41c76000
+
+ * - BSS
+ - 0x41c76000
+ - 0x41c80000
+
+ * - DM DATA
+ - 0x41c80000
+ - 0x41c84130
+
+ * - EMPTY
+ - 0x41c84130
+ - 0x41cff9fc
+
+ * - MCU Scratchpad
+ - 0x41cff9fc
+ - 0x41cffbfc
+
+ * - ROM DATA
+ - 0x41cffbfc
+ - 0x41cfffff
+
+Switch Setting for Boot Mode
+----------------------------
+
+Boot Mode pins provide means to select the boot mode and options before the
+device is powered up. After every POR, they are the main source to populate
+the Boot Parameter Tables.
+
+Boot Mode Pins for J721S2-EVM
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following table shows some common boot modes used on J721S2 platform.
+More details can be found in the Technical Reference Manual:
+https://www.ti.com/lit/pdf/spruj28 under the `Boot Mode Pins` section.
+
+.. list-table:: Boot Modes
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Switch Label
+ - SW9: 12345678
+ - SW8: 12345678
+
+ * - SD
+ - 00000000
+ - 10000010
+
+ * - EMMC
+ - 01000000
+ - 10000000
+
+ * - OSPI
+ - 01000000
+ - 00000110
+
+ * - UART
+ - 01110000
+ - 00000000
+
+ * - USB DFU
+ - 00100000
+ - 10000000
+
+For SW8 and SW9, the switch state in the "ON" position = 1.
+
+Boot Mode Pins for SK-AM68
+^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following table shows some common boot modes used on AM68-SK platform.
+More details can be found in the User Guide for AM68-SK:
+https://www.ti.com/lit/pdf/spruj68 under the `Bootmode Settings` section.
+
+.. list-table:: Boot Modes
+ :widths: 16 16
+ :header-rows: 1
+
+ * - Switch Label
+ - SW1: 1234
+
+ * - SD
+ - 0000
+
+ * - xSPI
+ - 0010
+
+ * - UART
+ - 1010
+
+ * - Ethernet
+ - 0100
+
+For SW1, the switch state in the "ON" position = 1.
+
+Debugging U-Boot
+----------------
+
+See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
+detailed setup information.
+
+.. warning::
+
+ **OpenOCD support since**: v0.12.0
+
+ If the default package version of OpenOCD in your development
+ environment's distribution needs to be updated, it might be necessary to
+ build OpenOCD from the source.
+
+Debugging U-Boot on J721S2-EVM
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_openocd_connect_XDS110
+ :end-before: .. k3_rst_include_end_openocd_connect_XDS110
+
+To start OpenOCD and connect to the board
+
+.. prompt:: bash $
+
+ openocd -f board/ti_j721s2evm.cfg
+
+Debugging U-Boot on SK-AM68
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_openocd_connect_cti20
+ :end-before: .. k3_rst_include_end_openocd_connect_cti20
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_openocd_cfg_external_intro
+ :end-before: .. k3_rst_include_end_openocd_cfg_external_intro
+
+For SK-AM68, the openocd_connect.cfg is as follows:
+
+.. code-block:: tcl
+
+ # TUMPA example:
+ # http://www.tiaowiki.com/w/TIAO_USB_Multi_Protocol_Adapter_User's_Manual
+ source [find interface/ftdi/tumpa.cfg]
+
+ transport select jtag
+
+ # default JTAG configuration has only SRST and no TRST
+ reset_config srst_only srst_push_pull
+
+ # delay after SRST goes inactive
+ adapter srst delay 20
+
+ if { ![info exists SOC] } {
+ # Set the SoC of interest
+ set SOC j721s2
+ }
+
+ source [find target/ti_k3.cfg]
+
+ ftdi tdo_sample_edge falling
+
+ # Speeds for FT2232H are in multiples of 2, and 32MHz is tops
+ # max speed we seem to achieve is ~20MHz.. so we pick 16MHz
+ adapter speed 16000
diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst
index ec44735..5167925 100644
--- a/doc/board/ti/k3.rst
+++ b/doc/board/ti/k3.rst
@@ -30,11 +30,14 @@
.. toctree::
:maxdepth: 1
+ am62x_beagleplay
am62x_sk
../toradex/verdin-am62
+ am64x_evm
am65x_evm
j7200_evm
j721e_evm
+ j721s2_evm
Boot Flow Overview
------------------
@@ -194,7 +197,7 @@
.. k3_rst_include_end_common_env_vars_desc
.. k3_rst_include_start_common_env_vars_defn
-.. prompt:: bash
+.. prompt:: bash $
export CC32=arm-linux-gnueabihf-
export CC64=aarch64-linux-gnu-
@@ -235,7 +238,7 @@
.. k3_rst_include_end_board_env_vars_desc
Building tiboot3.bin
-^^^^^^^^^^^^^^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^
1. To generate the U-Boot SPL for the wakeup domain, use the following
commands, substituting :code:`{SOC}` for the name of your device (eg:
@@ -244,7 +247,7 @@
uses the split binary flow)
.. k3_rst_include_start_build_steps_spl_r5
-.. prompt:: bash
+.. prompt:: bash $
# inside u-boot source
make $UBOOT_CFG_CORTEXR
@@ -270,7 +273,7 @@
UBoot SPL will only look for and load the files with these names.
Building tispl.bin
-^^^^^^^^^^^^^^^^^^^
+^^^^^^^^^^^^^^^^^^
The `tispl.bin` is a standard fitImage combining the firmware need for
the main domain to function properly as well as Device Management (DM)
@@ -280,7 +283,7 @@
application cores on the main domain.
.. k3_rst_include_start_build_steps_tfa
-.. prompt:: bash
+.. prompt:: bash $
# inside trusted-firmware-a source
make CROSS_COMPILE=$CC64 ARCH=aarch64 PLAT=k3 SPD=opteed $TFA_EXTRA_ARGS \
@@ -296,7 +299,7 @@
using the TrustZone technology built into the core.
.. k3_rst_include_start_build_steps_optee
-.. prompt:: bash
+.. prompt:: bash $
# inside optee_os source
make CROSS_COMPILE=$CC32 CROSS_COMPILE64=$CC64 CFG_ARM64_core=y $OPTEE_EXTRA_ARGS \
@@ -308,7 +311,7 @@
64bit core in the main domain.
.. k3_rst_include_start_build_steps_uboot
-.. prompt:: bash
+.. prompt:: bash $
# inside u-boot source
make $UBOOT_CFG_CORTEXA
@@ -407,14 +410,14 @@
be passing to mkimage for signing the fitImage and embedding the key in
the u-boot dtb.
- .. prompt:: bash
+ .. prompt:: bash $
mkimage -r -f fitImage.its -k $UBOOT_PATH/board/ti/keys -K
$UBOOT_PATH/build/a72/dts/dt.dtb
For signing a secondary platform, pass the -K parameter to that DTB
- .. prompt:: bash
+ .. prompt:: bash $
mkimage -f fitImage.its -k $UBOOT_PATH/board/ti/keys -K
$UBOOT_PATH/build/a72/arch/arm/dts/k3-j721e-sk.dtb
@@ -473,8 +476,7 @@
**Writing to MMC/EMMC**
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
env export -t $loadaddr <list of variables>
fatwrite mmc ${mmcdev} ${loadaddr} ${bootenvfile} ${filesize}
@@ -487,8 +489,7 @@
If manually needs to be done then the environment can be read from the
filesystem and then imported
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}
env import -t ${loadaddr} ${filesize}
@@ -548,7 +549,7 @@
box support by OpenOCD. The board-specific documentation will
cover the details and any adapter/dongle recommendations.
-.. prompt:: bash
+.. prompt:: bash $
openocd -v
@@ -566,7 +567,7 @@
other package managers. Please refer to the `OpenOCD Documentation
<https://openocd.org/>`_ for more recent installation steps.
-.. prompt:: bash
+.. prompt:: bash $
# Check the packages to be installed: needs deb-src in sources.list
sudo apt build-dep openocd
@@ -596,7 +597,7 @@
if building from a source, ensure that the udev rules are installed
correctly to ensure a sane system.
-.. prompt:: bash
+.. prompt:: bash $
# Go to the OpenOCD source directory
cd openocd
@@ -614,7 +615,7 @@
Most systems come with gdb-multiarch package.
-.. prompt:: bash
+.. prompt:: bash $
# Install gdb-multiarch package
sudo apt-get install gdb-multiarch
@@ -830,7 +831,7 @@
.. k3_rst_include_start_openocd_cfg_XDS110
-.. prompt:: bash
+.. prompt:: bash $
openocd -f board/{board_of_choice}.cfg
@@ -844,7 +845,7 @@
<https://github.com/openocd-org/openocd/blob/master/tcl/target/ti_k3.cfg#L59>`_
to decide if the SoC is supported or not.
-.. prompt:: bash
+.. prompt:: bash $
openocd -f openocd_connect.cfg
@@ -919,13 +920,13 @@
GDB-based IDE. To start up GDB in the terminal, run the following
command.
-.. prompt:: bash
+.. prompt:: bash $
gdb-multiarch
To connect to your desired core, run the following command within GDB:
-.. code-block:: bash
+.. prompt:: bash (gdb)
target extended-remote localhost:{port for desired core}
@@ -942,13 +943,13 @@
* Prior to relocation:
-.. code-block:: bash
+.. prompt:: bash (gdb)
symbol-file {path to elf file}
* After relocation:
-.. code-block:: bash
+.. prompt:: bash (gdb)
# Drop old symbol file
symbol-file
@@ -959,7 +960,7 @@
In the above example of AM625,
-.. code-block:: bash
+.. prompt:: bash (gdb)
target extended-remote localhost:3338 <- R5F (Wakeup Domain)
target extended-remote localhost:3334 <- A53 (Main Domain)
@@ -979,7 +980,7 @@
needed and run the following GDB commands to step out of the debug
loop set in the ``board_init_f`` function.
-.. code-block:: bash
+.. prompt:: bash (gdb)
set x = 0
continue
diff --git a/doc/board/ti/ks2_evm.rst b/doc/board/ti/ks2_evm.rst
index 0a78903..16c2e57 100644
--- a/doc/board/ti/ks2_evm.rst
+++ b/doc/board/ti/ks2_evm.rst
@@ -17,17 +17,17 @@
The K2HK board is based on Texas Instruments Keystone2 family of SoCs: K2H, K2K.
More details on these SoCs are available at company websites:
-K2K: http://www.ti.com/product/tci6638k2k
-K2H: http://www.ti.com/product/tci6638k2h
+K2K: https://www.ti.com/product/tci6638k2k
+K2H: https://www.ti.com/product/tci6638k2h
The K2E SoC details are available at
- http://www.ti.com/lit/ds/symlink/66ak2e05.pdf
+ https://www.ti.com/lit/ds/symlink/66ak2e05.pdf
The K2L SoC details are available at
- http://www.ti.com/lit/ds/symlink/tci6630k2l.pdf
+ https://www.ti.com/lit/ds/symlink/tci6630k2l.pdf
The K2G SoC details are available at
- http://www.ti.com/lit/ds/symlink/66ak2g02.pdf
+ https://www.ti.com/lit/ds/symlink/66ak2g02.pdf
Board Configuration
-------------------
@@ -122,8 +122,7 @@
To build u-boot.bin, u-boot-spi.gph, MLO:
-.. prompt:: bash
- :prompts: $
+.. prompt:: bash $
make k2hk_evm_defconfig
make
@@ -197,8 +196,7 @@
4. Free Run the target as described earlier (step 4) to get U-Boot prompt
5. At the U-Boot console type following to setup U-Boot environment variables.
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
setenv addr_uboot 0x87000000
setenv filesize <size in hex of u-boot-spi.gph rounded to hex 0x10000>
@@ -226,8 +224,7 @@
4. Free Run the target as described earlier (step 4) to get U-Boot prompt
5. At the U-Boot console type following to setup U-Boot environment variables.
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
setenv filesize <size in hex of MLO rounded to hex 0x10000>
run burn_uboot_nand
@@ -249,10 +246,10 @@
1. On the regular UART port start xmodem transfer of the u-boot.bin
2. Using BMC terminal set the ARM-UART bootmode and reboot the EVM
-.. prompt:: bash
+.. prompt:: bash BMC>
- BMC> bootmode #4
- MBC> reboot
+ bootmode #4
+ reboot
3. When xmodem is complete you should see the U-Boot starts on the UART port
diff --git a/doc/board/xen/xenguest_arm64.rst b/doc/board/xen/xenguest_arm64.rst
index e9bdaf7..92be9d4 100644
--- a/doc/board/xen/xenguest_arm64.rst
+++ b/doc/board/xen/xenguest_arm64.rst
@@ -23,6 +23,7 @@
- PV block device frontend driver with XenStore based device enumeration and
UCLASS_PVBLOCK class;
- PV serial console device frontend driver;
+- Virtio block device support;
- Xen hypervisor support with minimal set of the essential headers adapted from
the Linux kernel;
- Xen grant table support;
@@ -34,6 +35,7 @@
define any start addresses at compile time which is up to Xen to choose at
run-time;
- new defconfig introduced: xenguest_arm64_defconfig.
+- new defconfig introduced: xenguest_arm64_virtio_defconfig.
Board limitations
diff --git a/doc/board/xilinx/xilinx.rst b/doc/board/xilinx/xilinx.rst
index 8c9afb4..5464625 100644
--- a/doc/board/xilinx/xilinx.rst
+++ b/doc/board/xilinx/xilinx.rst
@@ -2,7 +2,7 @@
.. (C) Copyright 2019 Xilinx, Inc.
U-Boot device tree bindings
-----------------------------
+---------------------------
All the device tree bindings used in U-Boot are specified in Linux
kernel. Please refer dt bindings from below specified paths in Linux
diff --git a/doc/board/xilinx/zynq.rst b/doc/board/xilinx/zynq.rst
index 438912f..76d67bd 100644
--- a/doc/board/xilinx/zynq.rst
+++ b/doc/board/xilinx/zynq.rst
@@ -83,7 +83,7 @@
---------------
- Added basic board configurations support.
-- Added zynq u-boot bsp code - arch/arm/mach-zynq
+- Added zynq U-Boot bsp code - arch/arm/mach-zynq
- Added zynq boards named - zc70x, zed, microzed, zc770_xm010/xm011/xm012/xm013
- Added zynq drivers:
diff --git a/doc/board/xilinx/zynqmp-r5.rst b/doc/board/xilinx/zynqmp-r5.rst
index 2cd368b..266d07d 100644
--- a/doc/board/xilinx/zynqmp-r5.rst
+++ b/doc/board/xilinx/zynqmp-r5.rst
@@ -26,7 +26,7 @@
Notes
^^^^^
-Output fragment is u-boot.
+Output fragment is U-Boot.
Loading
-------
@@ -38,7 +38,7 @@
^^^^^^^
The first way is to use Xilinx FSBL (First stage
-bootloader) to load u-boot and start it. The following bif can be used for boot
+bootloader) to load U-Boot and start it. The following bif can be used for boot
image generation via Xilinx bootgen utility::
diff --git a/doc/build/clang.rst b/doc/build/clang.rst
index cc26550..09bb988 100644
--- a/doc/build/clang.rst
+++ b/doc/build/clang.rst
@@ -11,14 +11,6 @@
supported inline assembly is needed to get and set the r9 or x18 value. This
leads to larger code then strictly necessary, but at least works.
-**NOTE:** target compilation only work for _some_ ARM boards at the moment.
-Also AArch64 is not supported currently due to a lack of private libgcc
-support. Boards which reassign gd in c will also fail to compile, but there is
-in no strict reason to do so in the ARM world, since crt0.S takes care of this.
-These assignments can be avoided by changing the init calls but this is not in
-mainline yet.
-
-
Debian based
------------
@@ -28,14 +20,20 @@
sudo apt-get install clang
-Note that we still use binutils for some tools so we must continue to set
-CROSS_COMPILE. To compile U-Boot with Clang on Linux without IAS use e.g.
+We make use of the CROSS_COMPILE variable to derive the build target which is
+passed as the --target parameter to clang.
+
+The CROSS_COMPILE variable further determines the paths to other build
+tools. As assembler we use the binary pointed to by '$(CROSS_COMPILE)as'
+instead of the LLVM integrated assembler (IAS).
+
+Here is an example demonstrating building U-Boot for the Raspberry Pi 2
+using clang:
.. code-block:: bash
make HOSTCC=clang rpi_2_defconfig
- make HOSTCC=clang CROSS_COMPILE=arm-linux-gnueabi- \
- CC="clang -target arm-linux-gnueabi" -j8
+ make HOSTCC=clang CROSS_COMPILE=arm-linux-gnueabi- CC=clang -j8
It can also be used to compile sandbox:
diff --git a/doc/build/gcc.rst b/doc/build/gcc.rst
index a0650a5..3c64657 100644
--- a/doc/build/gcc.rst
+++ b/doc/build/gcc.rst
@@ -60,8 +60,14 @@
.. code-block:: bash
- apk add alpine-sdk bc bison dtc flex linux-headers ncurses-dev \
- openssl-dev perl python3 py3-setuptools python3-dev sdl2-dev
+ apk add alpine-sdk bc bison dtc flex gnutls-dev linux-headers ncurses-dev \
+ openssl-dev py3-elftools py3-setuptools python3-dev swig util-linux-dev
+
+Depending on the build target further packages may be needed:
+
+* sandbox with lcd: sdl2-dev
+* riscv64 S-mode targets: opensbi
+* some arm64 targets: arm-trusted-firmware
Prerequisites
-------------
diff --git a/doc/build/gen_compile_commands.rst b/doc/build/gen_compile_commands.rst
new file mode 100644
index 0000000..50305ce
--- /dev/null
+++ b/doc/build/gen_compile_commands.rst
@@ -0,0 +1,83 @@
+.. SPDX-License-Identifier: GPL-2.0-only
+
+Create build database for IDEs
+==============================
+
+gen_compile_commands (scripts/gen_compile_commands.py) is a script used to
+generate a compilation database (compile_commands.json). This database consists
+of an array of "command objects" describing how each translation unit was
+compiled.
+
+Example::
+
+ {
+ "command": "gcc -Wp,-MD,arch/x86/cpu/.lapic.o.d -nostdinc -isystem (...)"
+ "directory": "/home/jmcosta/u-boot",
+ "file": "/home/jmcosta/u-boot/arch/x86/cpu/lapic.c"
+ }
+
+Such information comes from parsing the respective .cmd file of each translation
+unit. In the previous example, that would be `arch/x86/cpu/.lapic.o.cmd`.
+
+For more details on the database format, please refer to the official
+documentation at https://clang.llvm.org/docs/JSONCompilationDatabase.html.
+
+The compilation database is quite useful for text editors (and IDEs) that use
+Clangd LSP. It allows jumping to definitions and declarations. Since it relies
+on parsing .cmd files, one needs to have a target (e.g. configs/xxx_defconfig)
+built before running the script.
+
+Example::
+
+ make sandbox_defconfig
+ make
+ ./scripts/gen_compile_commands.py
+
+Beware that depending on the changes you made to the project's source code, you
+may need to run the script again (presuming you recompiled your target, of
+course) to have an up-to-date database.
+
+The database will be in the root of the repository. No further modifications are
+needed for it to be usable by the LSP, unless you set a name for the database
+other than it's default one (compile_commands.json).
+
+Compatible IDEs
+===============
+
+Several popular integrated development environments (IDEs) support the use
+of JSON compilation databases for C/C++ development, making it easier to
+manage build configurations and code analysis. Some of these IDEs include:
+
+1. **Visual Studio Code (VS Code)**: IntelliSense in VS Code can be set up to
+ use compile_commands.json by following the instructions in
+ https://code.visualstudio.com/docs/cpp/faq-cpp#_how-do-i-get-intellisense-to-work-correctly.
+
+2. **CLion**: JetBrains' CLion IDE supports JSON compilation databases out
+ of the box. You can configure your project to use a compile_commands.json
+ file via the project settings. Details on setting up CLion with JSON
+ compilation databases can be found at
+ https://www.jetbrains.com/help/clion/compilation-database.html.
+
+3. **Qt Creator**: Qt Creator, a popular IDE for Qt development, also
+ supports compile_commands.json for C/C++ projects. Instructions on how to
+ use this feature can be found at
+ https://doc.qt.io/qtcreator/creator-clang-codemodel.html#using-compilation-databases.
+
+4. **Eclipse CDT**: Eclipse's C/C++ Development Tools (CDT) can be
+ configured to use JSON compilation databases for better project management.
+ You can find guidance on setting up JSON compilation database support at the
+ wiki: https://wiki.eclipse.org/CDT/User/NewIn910#Build.
+
+For Vim, Neovim, and Emacs, if you are using Clangd as your LSP, placing the
+compile_commands.json in the root of the repository should suffice to enable
+code navigation.
+
+Usage
+=====
+
+For further details on the script's options, please refer to its help message,
+as in the example below.
+
+Help::
+
+ ./scripts/gen_compile_commands.py --help
diff --git a/doc/build/index.rst b/doc/build/index.rst
index 64e6649..7a4507b 100644
--- a/doc/build/index.rst
+++ b/doc/build/index.rst
@@ -14,3 +14,4 @@
tools
buildman
documentation
+ gen_compile_commands
diff --git a/doc/build/source.rst b/doc/build/source.rst
index 470f793..d21ee05 100644
--- a/doc/build/source.rst
+++ b/doc/build/source.rst
@@ -1,5 +1,5 @@
Obtaining the source
-=====================
+====================
The source of the U-Boot project is maintained in a Git repository.
diff --git a/doc/build/tools.rst b/doc/build/tools.rst
index ec017229..5bfa05b 100644
--- a/doc/build/tools.rst
+++ b/doc/build/tools.rst
@@ -45,3 +45,12 @@
$ make tools-only_defconfig
$ make tools-only
+
+
+Building without Python
+-----------------------
+
+The tools-only builds bytes pylibfdt by default. To disable this, use the
+NO_PYTHON variable::
+
+ NO_PYTHON=1 make tools-only_defconfig tools-only
diff --git a/doc/develop/bootstd.rst b/doc/develop/bootstd.rst
index c47de27..496e24b 100644
--- a/doc/develop/bootstd.rst
+++ b/doc/develop/bootstd.rst
@@ -247,7 +247,7 @@
Name of the flattened device tree (FDT) file to load, e.g.
"rockchip/rk3399-rockpro64.dtb"
-fdtaddr_addr_r
+fdt_addr_r
Address at which to load the FDT, e.g. 0x01f00000
fdtoverlay_addr_r (needed if overlays are used)
@@ -464,6 +464,28 @@
======= =======================================================================
+Migrating from distro_boot
+--------------------------
+
+To migrate from distro_boot:
+
+#. Update your board header files to remove the BOOTENV and BOOT_TARGET_xxx
+ defines. Standard boot finds available boot devices automatically.
+
+#. Remove the "boot_targets" variable unless you need it. Standard boot uses a
+ default order from fastest to slowest, which generally matches the order used
+ by boards.
+
+#. Make sure that CONFIG_BOOTSTD_DEFAULTS is enabled by your board, so it can
+ boot common Linux distributions.
+
+An example patch is at migrate_patch_.
+
+If you are using custom boot scripts for your board, consider creating your
+own bootmeth to hold the logic. There are various examples at
+`boot/bootmeth_...`.
+
+
Theory of operation
-------------------
@@ -683,11 +705,12 @@
partition. If that works it tries to detect a file system. If that works then it
calls the bootmeth device once more, this time to read the bootflow.
-Note: At present a filesystem is needed for the bootmeth to be called on block
-devices, simply because we don't have any examples where this is not the case.
-This feature can be added as needed. Note that sandbox is a special case, since
-in that case the host filesystem can be accessed even though the block device
-is NULL.
+Note: Normally a filesystem is needed for the bootmeth to be called on block
+devices, but bootmeths which don't need that can set the BOOTMETHF_ANY_PART
+flag to indicate that they can scan any partition. An example is the ChromiumOS
+bootmeth which can store a kernel in a raw partition. Note also that sandbox is
+a special case, since in that case the host filesystem can be accessed even
+though the block device is NULL.
If we take the example of the `bootmeth_extlinux` driver, this call ends up at
`extlinux_read_bootflow()`. It has the filesystem ready, so tries various
@@ -758,9 +781,7 @@
Some things that need to be done to completely replace the distro-boot scripts:
-- add bootdev drivers for dhcp, sata, scsi, ide, virtio
-- PXE boot for EFI
-- support for loading U-Boot scripts
+- implement extensions (devicetree overlays with add-on boards)
Other ideas:
@@ -774,3 +795,4 @@
.. _BootLoaderSpec: http://www.freedesktop.org/wiki/Specifications/BootLoaderSpec/
.. _distro_boot: https://github.com/u-boot/u-boot/blob/master/boot/distro.c
.. _bootflow_h: https://github.com/u-boot/u-boot/blob/master/include/bootflow.h
+.. _migrate_patch: https://patchwork.ozlabs.org/project/uboot/patch/20230727215433.578830-2-sjg@chromium.org/
diff --git a/doc/develop/cedit.rst b/doc/develop/cedit.rst
new file mode 100644
index 0000000..82305b9
--- /dev/null
+++ b/doc/develop/cedit.rst
@@ -0,0 +1,170 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Configuration Editor
+====================
+
+Introduction
+------------
+
+U-Boot provides a configuration editor which allows settings to be changed in
+a GUI or text environment.
+
+
+This feature is still in development and has a number of limitations. For
+example, cedit only supports menu items (there is no numeric or text entry),
+provides no support for colour text and does not support scrolling. Still it is
+possible to use it for simple applications.
+
+
+Overview
+--------
+
+The configuration editor makes use of :doc:`expo` to build a description of the
+configuration screens and allow user to interact with it.
+
+To create a single-scene cedit for your application:
+
+#. Design the scene, i.e. the objects that need to be present and what their
+ possible values are
+
+#. Enter this in .dts format
+
+#. Create a header file containing the IDs
+
+#. Run the 'expo.py' tool to generate a .dtb file containing the layout, which
+ can be used by U-Boot
+
+#. Use the :doc:`../usage/cmd/cedit` to create the cedit, read the settings,
+ present the cedit to the user and save the settings afterwards.
+
+Each of these is described in a separate section. See :ref:`expo_example` for
+an example file.
+
+
+Design a scene
+--------------
+
+Using a piece of paper or a drawing tool, lay out the objects you want in your
+scene. Typically you will use the default layout engine, which simply puts items
+one after the other from top to bottom. So use a single column and show the
+prompt and value for each object.
+
+For menu items, show one of the values, but keep in mind what else you need.
+
+
+Create an expo-format file
+--------------------------
+
+The description is in the form of a devicetree file, as documented at
+:ref:`expo_format`. Since everything in an expo has an ID number (an integer
+greater than 1) the description is written terms of these IDs. They each have
+an enum value. which is typically taken care of by the `expo.py` tool.
+
+The expo should have a `scenes` node with a named scene as a subnode. Within the
+scene, add properties for the scene, then a subnode for each object in the
+scene.
+
+All object nodes require an `id` value and a `type` property. Other properties
+depend on the type. For example, a menu has a `title` and an `item-label` list
+proving the text for the menu items, as well as an `item-id` list providing the
+ID of each menu item, so it can be selected.
+
+Text properties may have two variants. For example `title` specifies the title
+of a menu, but you can instead use `title-id` to specify the string ID to use as
+the title. String are defined in a separate area, common to the whole expo,
+which contains a subnode for each string. Within that subnode are the ID and the
+`value` (i.e. the text). For now only English is supported, but in future it may
+be possible to append a language identifier to provide other values (e.g.
+'value-es' for Spanish).
+
+
+Create an ID header-file
+------------------------
+
+Expo needs to know the integer value to use for every ID referenced in your
+expo-format file. For example, if you have defined a `cpu-speed` node with an
+id of `ID_CPU_SPEED`, then Expo needs to know the value of `ID_CPU_SPEED`.
+
+When you write C code to use the expo, you may need to know the IDs. For
+example, to find which value the user selected in `cpu-speed` menu, you must
+use the `ID_CPU_SPEED` ID. The ID is the only way to refer to anything in Expo.
+
+Since we need a shared set of IDs, it is best to have a header file containing
+them. Expo supports doing this with an enum, where every ID is listed in the
+enum::
+
+ enum {
+ ZERO,
+
+ ID_PROMPT,
+
+ ID_SCENE1,
+ ID_SCENE1_TITLE,
+ ...
+ };
+
+The C compiler can parse this directly. The `expo.py` tool parses it for expo.
+
+Create a header file containing every ID mentioned in your expo. Try to group
+related things together.
+
+
+Build the expo layout
+---------------------
+
+Use the `expo.py` tool to build a .dtb for your expo::
+
+ ./tools/expo.py -e expo_ids.h -l expo_layout.dts -o expo.dtb
+
+This uses the enum in the provided header file to get the ID numbers, grabs
+the `.dts` file, inserts the ID numbers and then uses the devicetree compiler to
+build a `.dtb` file.
+
+If you get an error::
+
+ Devicetree compiler error:
+ Error: <stdin>:9.19-20 syntax error
+ FATAL ERROR: Unable to parse input tree
+
+that means that something is wrong with your syntax, or perhaps you have an ID
+in the `.dts` file that is not mentioned in your enum. Check both files and try
+again.
+
+
+Use the command interface
+-------------------------
+
+See the :doc:`../usage/cmd/cedit` command for information on available commands.
+Typically you will use `cedit load` to load the `.dtb` file and `cedit run` to
+let the user interact with it.
+
+
+Multiple scenes
+---------------
+
+Expo supports multiple scenes but has no pre-determined way of moving between
+them. You could use selection of a menu item as a signal to change the scene,
+but this is not currently implemented in the cedit code (see `cedit_run()`).
+
+
+Themes
+------
+
+The configuration editor uses simple expo themes. The theme is read from
+`/bootstd/cedit-theme` in the devicetree.
+
+
+Reading and writing settings
+----------------------------
+
+Cedit provides several options for persistent settings:
+
+- Writing an FDT file to a filesystem
+- Writing to U-Boot's environment variables, which are then typically stored in
+ a persistent manner
+- Writing to CMOS RAM registers (common on x86 machines). Note that textline
+ objects do not appear in CMOS RAM registers
+
+For now, reading and writing settings is not automatic. See the
+:doc:`../usage/cmd/cedit` for how to do this on the command line or in a
+script.
diff --git a/doc/develop/cyclic.rst b/doc/develop/cyclic.rst
index 43bedac..6783149 100644
--- a/doc/develop/cyclic.rst
+++ b/doc/develop/cyclic.rst
@@ -8,11 +8,11 @@
blinking etc. The functions that are hooked into this cyclic list should
be small timewise as otherwise the execution of the other code that relies
on a high frequent polling (e.g. UART rx char ready check) might be
-delayed too much. To detect cyclic functions with a too long execution
-time, the Kconfig option `CONFIG_CYCLIC_MAX_CPU_TIME_US` is introduced,
-which configures the max allowed time for such a cyclic function. If it's
-execution time exceeds this time, this cyclic function will get removed
-from the cyclic list.
+delayed too much. To detect cyclic functions with an excessive execution
+time, the Kconfig option `CONFIG_CYCLIC_MAX_CPU_TIME_US` was introduced.
+It defines the maximum allowable execution time for such a cyclic function. The
+first time the execution of a cyclic function exceeds this interval, a warning
+will be displayed indicating the problem to the user.
Registering a cyclic function
-----------------------------
diff --git a/doc/develop/driver-model/debugging.rst b/doc/develop/driver-model/debugging.rst
index bbb2794..e13abdd 100644
--- a/doc/develop/driver-model/debugging.rst
+++ b/doc/develop/driver-model/debugging.rst
@@ -49,7 +49,7 @@
of_to_plat() method in the driver.
If there is no error, you should check if the device is actually bound. Call
-dm_dump_all() just before you locate the device to make sure it exists.
+dm_dump_tree() just before you locate the device to make sure it exists.
If it does not exist, check your device tree compatible strings match up with
what the driver expects (in the struct udevice_id array).
diff --git a/doc/develop/driver-model/ethernet.rst b/doc/develop/driver-model/ethernet.rst
index cdbccca..73c3a72 100644
--- a/doc/develop/driver-model/ethernet.rst
+++ b/doc/develop/driver-model/ethernet.rst
@@ -1,5 +1,5 @@
Ethernet Driver Guide
-=======================
+=====================
The networking stack in Das U-Boot is designed for multiple network devices
to be easily added and controlled at runtime. This guide is meant for people
@@ -14,7 +14,7 @@
the two and hints about porting will be handled at the end.
Driver framework
-------------------
+----------------
A network driver following the driver model must declare itself using
the UCLASS_ETH .id field in the U-Boot driver struct:
@@ -67,7 +67,7 @@
bits for internal PHYs, etc.).
Driver methods
-----------------
+--------------
The real work will be done in the driver method functions the driver provides
by defining the members of struct eth_ops:
@@ -158,7 +158,7 @@
CONFIG_PHYLIB / CONFIG_CMD_MII
---------------------------------
+------------------------------
If your device supports banging arbitrary values on the MII bus (pretty much
every device does), you should add support for the mii command. Doing so is
@@ -193,7 +193,7 @@
................................................................
Legacy network drivers
-------------------------
+----------------------
!!! WARNING !!!
@@ -221,7 +221,7 @@
initialising a network driver is as follows:
Old network driver registration
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
When U-Boot initializes, it will call the common function eth_initialize().
This will in turn call the board-specific board_eth_init() (or if that fails,
diff --git a/doc/develop/driver-model/migration.rst b/doc/develop/driver-model/migration.rst
index fe1ae21..03fea94 100644
--- a/doc/develop/driver-model/migration.rst
+++ b/doc/develop/driver-model/migration.rst
@@ -100,7 +100,7 @@
other base driver model options in time for inclusion in the 2021.10 release.
CFG_SYS_TIMER_RATE and CFG_SYS_TIMER_COUNTER
---------------------------------------------------
+--------------------------------------------
Deadline: 2023.01
These are legacy options which have been replaced by driver model.
diff --git a/doc/develop/driver-model/nvmxip.rst b/doc/develop/driver-model/nvmxip.rst
index e85dc22..4a7650c 100644
--- a/doc/develop/driver-model/nvmxip.rst
+++ b/doc/develop/driver-model/nvmxip.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+
NVM XIP Block Storage Emulation Driver
-=======================================
+======================================
Summary
-------
@@ -54,12 +54,12 @@
The implementation is generic and can be used by different platforms.
Supported hardware
---------------------------------
+------------------
Any plaform supporting readq().
Configuration
-----------------------
+-------------
config NVMXIP
This option allows the emulation of a block storage device
@@ -77,7 +77,7 @@
write their own driver (same as nvmxip_qspi in addition to the custom settings).
Device Tree nodes
---------------------
+-----------------
Multiple QSPI XIP flash devices can be used at the same time by describing them through DT
nodes.
diff --git a/doc/develop/driver-model/remoteproc-framework.rst b/doc/develop/driver-model/remoteproc-framework.rst
index 566495a..03a0bd0 100644
--- a/doc/develop/driver-model/remoteproc-framework.rst
+++ b/doc/develop/driver-model/remoteproc-framework.rst
@@ -1,6 +1,6 @@
.. SPDX-License-Identifier: GPL-2.0+
.. (C) Copyright 2015
-.. Texas Instruments Incorporated - http://www.ti.com/
+.. Texas Instruments Incorporated - https://www.ti.com/
Remote Processor Framework
==========================
diff --git a/doc/develop/driver-model/soc-framework.rst b/doc/develop/driver-model/soc-framework.rst
index 2609fda..357e7fc 100644
--- a/doc/develop/driver-model/soc-framework.rst
+++ b/doc/develop/driver-model/soc-framework.rst
@@ -1,6 +1,6 @@
.. SPDX-License-Identifier: GPL-2.0+
.. (C) Copyright 2020
-.. Texas Instruments Incorporated - http://www.ti.com/
+.. Texas Instruments Incorporated - https://www.ti.com/
SOC ID Framework
================
diff --git a/doc/develop/driver-model/spi-howto.rst b/doc/develop/driver-model/spi-howto.rst
index 97fbf75..9dc3b9b 100644
--- a/doc/develop/driver-model/spi-howto.rst
+++ b/doc/develop/driver-model/spi-howto.rst
@@ -218,7 +218,7 @@
Write of_to_plat() [for device tree only]
--------------------------------------------------
+-----------------------------------------
This method will convert information in the device tree node into a C
structure in your driver (called platform data). If you are not using
diff --git a/doc/develop/event.rst b/doc/develop/event.rst
index cb09e9c..d5043ec 100644
--- a/doc/develop/event.rst
+++ b/doc/develop/event.rst
@@ -21,16 +21,31 @@
To declare a spy, use something like this::
- static int snow_setup_cpus(void *ctx, struct event *event)
+ static int snow_check_temperature(void)
{
/* do something */
return 0;
}
- EVENT_SPY(EVT_DM_POST_INIT_F, snow_setup_cpus);
+ EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, snow_check_temperature);
This function is called when EVT_DM_POST_INIT_F is emitted, i.e. after the
driver model is initialized (in U-Boot proper before and after relocation).
+If you need access to the event data, use `EVENT_SPY_FULL`, like this::
+
+ static int snow_setup_cpus(void *ctx, struct event *event)
+ {
+ /* do something that uses event->data*/
+ return 0;
+ }
+ EVENT_SPY_FULL(EVT_DM_POST_INIT_F, snow_setup_cpus);
+
+Note that the context is always NULL for a static spy. See below for information
+about how to use a dynamic spy.
+
+The return value is handled by the event emitter. If non-zero, then the error
+is returned to the function which emitted the event, i.e. the one that called
+`event_notify()`.
Debugging
---------
@@ -80,6 +95,10 @@
This can be handled by enabling `CONFIG_EVENT_DYNAMIC`. It is then possible to
call `event_register()` to register a new handler for a particular event.
+If some context is need for the spy, you can pass a pointer to
+`event_register()` to provide that. Note that the context is only passed to
+a spy registered with `EVENT_SPY_FULL`.
+
Dynamic event handlers are called after all the static event spy handlers have
been processed. Of course, since dynamic event handlers are created at runtime
it is not possible to use the `event_dump.py` to see them.
diff --git a/doc/develop/expo.rst b/doc/develop/expo.rst
index 2ac4af2..c87b6ec 100644
--- a/doc/develop/expo.rst
+++ b/doc/develop/expo.rst
@@ -63,9 +63,12 @@
within the menu. Items can also have a preview image, which is shown when the
item is highlighted.
-All components have a name. This is purely for debugging, so it is easy to see
-what object is referred to. Of course the ID numbers can help as well, but they
-are less easy to distinguish.
+A `textline object` contains a label and an editable string.
+
+All components have a name. This is mostly for debugging, so it is easy to see
+what object is referred to, although the name is also used for saving values.
+Of course the ID numbers can help as well, but they are less easy to
+distinguish.
While the expo implementation provides support for handling keypresses and
rendering on the display or serial port, it does not actually deal with reading
@@ -136,7 +139,9 @@
sequences into keys. However, expo has some special menu-key codes for
navigating the interface. These are defined in `enum bootmenu_key` and include
`BKEY_UP` for moving up and `BKEY_SELECT` for selecting an item. You can use
-`bootmenu_conv_key()` to convert an ASCII key into one of these.
+`bootmenu_conv_key()` to convert an ASCII key into one of these, but if it
+returns a value >= `BKEY_FIRST_EXTRA` then you should pass the unmodified ASCII
+key to the expo, since it may be used by textline objects.
Once a keypress is decoded, call `expo_send_key()` to send it to the expo. This
may cause an update to the expo state and may produce an action.
@@ -312,11 +317,26 @@
"menu"
Menu containing items which can be selected by the user
+ "textline"
+ A line of text which can be edited
+
id
type: u32, required
Specifies the ID of the object. This is used when referring to the object.
+Where CMOS RAM is used for reading and writing settings, the following
+additional properties are required:
+
+start-bit
+ Specifies the first bit in the CMOS RAM to use for this setting. For a RAM
+ with 0x100 bytes, there are 0x800 bit locations. For example, register 0x80
+ holds bits 0x400 to 0x407.
+
+bit-length
+ Specifies the number of CMOS RAM bits to use for this setting. The bits
+ extend from `start-bit` to `start-bit + bit-length - 1`. Note that the bits
+ must be contiguous.
Menu nodes have the following additional properties:
@@ -350,6 +370,26 @@
Specifies the description for each item in the menu. These are currently
only intended for use in simple mode.
+Textline nodes have the following additional properties:
+
+label / label-id
+ type: string / u32, required
+
+ Specifies the label of the textline. This is shown to the left of the area
+ for this textline.
+
+edit-id
+ type: u32, required
+
+ Specifies the ID of the of the editable text object. This can be used to
+ obtain the text from the textline
+
+max-chars:
+ type: u32, required
+
+ Specifies the maximum number of characters permitted to be in the textline.
+ The user will be prevented from adding more.
+
Expo layout
~~~~~~~~~~~
@@ -358,6 +398,9 @@
suitable manner. For each scene it puts the title at the top, the prompt at the
bottom and the objects in order from top to bottom.
+
+.. _expo_example:
+
Expo format example
~~~~~~~~~~~~~~~~~~~
@@ -367,22 +410,30 @@
::
- #define ID_PROMPT 1
- #define ID_SCENE1 2
- #define ID_SCENE1_TITLE 3
+ /* this comment is parsed by the expo.py tool to insert the values below
- #define ID_CPU_SPEED 4
- #define ID_CPU_SPEED_TITLE 5
- #define ID_CPU_SPEED_1 6
- #define ID_CPU_SPEED_2 7
- #define ID_CPU_SPEED_3 8
+ enum {
+ ZERO,
+ ID_PROMPT,
+ ID_SCENE1,
+ ID_SCENE1_TITLE,
- #define ID_POWER_LOSS 9
- #define ID_AC_OFF 10
- #define ID_AC_ON 11
- #define ID_AC_MEMORY 12
+ ID_CPU_SPEED,
+ ID_CPU_SPEED_TITLE,
+ ID_CPU_SPEED_1,
+ ID_CPU_SPEED_2,
+ ID_CPU_SPEED_3,
- #define ID_DYNAMIC_START 13
+ ID_POWER_LOSS,
+ ID_AC_OFF,
+ ID_AC_ON,
+ ID_AC_MEMORY,
+
+ ID_MACHINE_NAME,
+ ID_MACHINE_NAME_EDIT,
+
+ ID_DYNAMIC_START,
+ */
&cedit {
dynamic-start = <ID_DYNAMIC_START>;
@@ -427,6 +478,13 @@
item-id = <ID_AC_OFF ID_AC_ON ID_AC_MEMORY>;
};
+
+ machine-name {
+ id = <ID_MACHINE_NAME>;
+ type = "textline";
+ max-chars = <20>;
+ title = "Machine name";
+ edit-id = <ID_MACHINE_NAME_EDIT>;
};
};
@@ -454,7 +512,7 @@
- Image formats other than BMP
- Use of ANSI sequences to control a serial terminal
- Colour selection
-- Support for more widgets, e.g. text, numeric, radio/option
+- Support for more widgets, e.g. numeric, radio/option
- Mouse support
- Integrate Nuklear, NxWidgets or some other library for a richer UI
- Optimise rendering by only updating the display with changes since last render
@@ -465,7 +523,7 @@
- Support unicode
- Support curses for proper serial-terminal menus
- Add support for large menus which need to scroll
-- Add support for reading and writing configuration settings with cedit
+- Update expo.py tool to check for overlapping names and CMOS locations
.. Simon Glass <sjg@chromium.org>
.. 7-Oct-22
diff --git a/doc/develop/falcon.rst b/doc/develop/falcon.rst
index a569d1a..8a46c0e 100644
--- a/doc/develop/falcon.rst
+++ b/doc/develop/falcon.rst
@@ -63,7 +63,7 @@
Enable the "spl export" command.
The command "spl export" is then available in U-Boot mode.
-CONFIG_SYS_SPL_ARGS_ADDR
+CONFIG_SPL_PAYLOAD_ARGS_ADDR
Address in RAM where the parameters must be copied by SPL.
In most cases, it is <start_of_ram> + 0x100.
@@ -220,7 +220,7 @@
The kernel is loaded directly by the SPL without passing through U-Boot.
Example with FDT: a3m071 board
--------------------------------
+------------------------------
To boot the Linux kernel from the SPL, the DT blob (fdt) needs to get
prepared/patched first. U-Boot usually inserts some dynamic values into
diff --git a/doc/develop/ide_integration.rst b/doc/develop/ide_integration.rst
new file mode 100644
index 0000000..455e099
--- /dev/null
+++ b/doc/develop/ide_integration.rst
@@ -0,0 +1,12 @@
+Integration with IDEs
+=====================
+
+IDEs and text editors (e.g., VSCode, Emacs, Vim, Neovim) typically offer
+plugins to enhance the development experience, such as Clangd LSP. These
+plugins provide features like code navigation (i.e., jumping to definitions
+and declarations), code completion, and code formatting.
+
+U-Boot provides a script (i.e., scripts/gen_compile_commands.py) that
+generates a compilation database to be utilized by Clangd LSP for code
+navigation. For detailed usage instructions, please refer to the script's
+documentation: :doc:`../build/gen_compile_commands`.
diff --git a/doc/develop/index.rst b/doc/develop/index.rst
index 5b230d0..f82e148 100644
--- a/doc/develop/index.rst
+++ b/doc/develop/index.rst
@@ -19,6 +19,7 @@
security
sending_patches
system_configuration
+ ide_integration
Implementation
--------------
@@ -38,6 +39,7 @@
driver-model/index
environment
expo
+ cedit
event
global_data
logging
@@ -87,7 +89,7 @@
checkpatch
coccinelle
- moveconfig
+ qconfig
Code quality
------------
diff --git a/doc/develop/moveconfig.rst b/doc/develop/moveconfig.rst
deleted file mode 100644
index ad8596e..0000000
--- a/doc/develop/moveconfig.rst
+++ /dev/null
@@ -1,302 +0,0 @@
-.. SPDX-License-Identifier: GPL-2.0+
-
-moveconfig - Migrating and querying CONFIG options
-==================================================
-
-Since Kconfig was introduced to U-Boot, we have worked on moving
-config options from headers to Kconfig (defconfig).
-
-This tool intends to help this tremendous work.
-
-Installing
-----------
-
-You may need to install 'python3-asteval' for the 'asteval' module.
-
-Usage
------
-
-First, you must edit the Kconfig to add the menu entries for the configs
-you are moving.
-
-Then run this tool giving CONFIG names you want to move.
-For example, if you want to move CONFIG_CMD_USB and CONFIG_TEXT_BASE,
-simply type as follows::
-
- $ tools/moveconfig.py CONFIG_CMD_USB CONFIG_TEXT_BASE
-
-The tool walks through all the defconfig files and move the given CONFIGs.
-
-The log is also displayed on the terminal.
-
-The log is printed for each defconfig as follows::
-
- <defconfig_name>
- <action1>
- <action2>
- <action3>
- ...
-
-`<defconfig_name>` is the name of the defconfig.
-
-`<action*>` shows what the tool did for that defconfig.
-It looks like one of the following:
-
- - Move 'CONFIG\_... '
- This config option was moved to the defconfig
-
- - CONFIG\_... is not defined in Kconfig. Do nothing.
- The entry for this CONFIG was not found in Kconfig. The option is not
- defined in the config header, either. So, this case can be just skipped.
-
- - CONFIG\_... is not defined in Kconfig (suspicious). Do nothing.
- This option is defined in the config header, but its entry was not found
- in Kconfig.
- There are two common cases:
-
- - You forgot to create an entry for the CONFIG before running
- this tool, or made a typo in a CONFIG passed to this tool.
- - The entry was hidden due to unmet 'depends on'.
-
- The tool does not know if the result is reasonable, so please check it
- manually.
-
- - 'CONFIG\_...' is the same as the define in Kconfig. Do nothing.
- The define in the config header matched the one in Kconfig.
- We do not need to touch it.
-
- - Compiler is missing. Do nothing.
- The compiler specified for this architecture was not found
- in your PATH environment.
- (If -e option is passed, the tool exits immediately.)
-
- - Failed to process.
- An error occurred during processing this defconfig. Skipped.
- (If -e option is passed, the tool exits immediately on error.)
-
-Finally, you will be asked, Clean up headers? [y/n]:
-
-If you say 'y' here, the unnecessary config defines are removed
-from the config headers (include/configs/\*.h).
-It just uses the regex method, so you should not rely on it.
-Just in case, please do 'git diff' to see what happened.
-
-
-How does it work?
------------------
-
-This tool runs configuration and builds include/autoconf.mk for every
-defconfig. The config options defined in Kconfig appear in the .config
-file (unless they are hidden because of unmet dependency.)
-On the other hand, the config options defined by board headers are seen
-in include/autoconf.mk. The tool looks for the specified options in both
-of them to decide the appropriate action for the options. If the given
-config option is found in the .config, but its value does not match the
-one from the board header, the config option in the .config is replaced
-with the define in the board header. Then, the .config is synced by
-"make savedefconfig" and the defconfig is updated with it.
-
-For faster processing, this tool handles multi-threading. It creates
-separate build directories where the out-of-tree build is run. The
-temporary build directories are automatically created and deleted as
-needed. The number of threads are chosen based on the number of the CPU
-cores of your system although you can change it via -j (--jobs) option.
-
-
-Toolchains
-----------
-
-Appropriate toolchain are necessary to generate include/autoconf.mk
-for all the architectures supported by U-Boot. Most of them are available
-at the kernel.org site, some are not provided by kernel.org. This tool uses
-the same tools as buildman, so see that tool for setup (e.g. --fetch-arch).
-
-
-Tips and trips
---------------
-
-To sync only X86 defconfigs::
-
- ./tools/moveconfig.py -s -d <(grep -l X86 configs/*)
-
-or::
-
- grep -l X86 configs/* | ./tools/moveconfig.py -s -d -
-
-To process CONFIG_CMD_FPGAD only for a subset of configs based on path match::
-
- ls configs/{hrcon*,iocon*,strider*} | \
- ./tools/moveconfig.py -Cy CONFIG_CMD_FPGAD -d -
-
-
-Finding boards with particular CONFIG combinations
---------------------------------------------------
-
-You can use `moveconfig.py` to figure out which boards have a CONFIG enabled, or
-which do not. To use it, first build a database::
-
- ./tools/moveconfig.py -b
-
-Then you can run queries using the `-f` flag followed by a list of CONFIG terms.
-Each term is CONFIG name, with or without a tilde (~) prefix. The tool searches
-for boards which match the CONFIG name, or do not match if tilde is used. For
-example, to find boards which enabled CONFIG_SCSI but not CONFIG_BLK::
-
- tools/moveconfig.py -f SCSI ~BLK
- 3 matches
- pg_wcom_seli8_defconfig highbank_defconfig pg_wcom_expu1_defconfig
-
-
-Finding implied CONFIGs
------------------------
-
-Some CONFIG options can be implied by others and this can help to reduce
-the size of the defconfig files. For example, CONFIG_X86 implies
-CONFIG_CMD_IRQ, so we can put 'imply CMD_IRQ' under 'config X86' and
-all x86 boards will have that option, avoiding adding CONFIG_CMD_IRQ to
-each of the x86 defconfig files.
-
-This tool can help find such configs. To use it, first build a database::
-
- ./tools/moveconfig.py -b
-
-Then try to query it::
-
- ./tools/moveconfig.py -i CONFIG_I8042_KEYB
- CONFIG_I8042_KEYB found in 33/5155 defconfigs
- 28 : CONFIG_X86
- 28 : CONFIG_SA_PCIEX_LENGTH
- 28 : CONFIG_HPET_ADDRESS
- 28 : CONFIG_MAX_PIRQ_LINKS
- 28 : CONFIG_I8254_TIMER
- 28 : CONFIG_I8259_PIC
- 28 : CONFIG_RAMBASE
- 28 : CONFIG_IRQ_SLOT_COUNT
- 28 : CONFIG_PCIE_ECAM_SIZE
- 28 : CONFIG_APIC
- ...
-
-This shows a list of config options which might imply CONFIG_I8042_KEYB along
-with how many defconfigs they cover. From this you can see that CONFIG_X86
-generally implies CONFIG_I8042_KEYB but not always (28 out of 35). Therefore,
-instead of adding CONFIG_I8042_KEYB to
-the defconfig of every x86 board, you could add a single imply line to the
-Kconfig file::
-
- config X86
- bool "x86 architecture"
- ...
- imply CMD_EEPROM
-
-That will cover 28 defconfigs and you can perhaps find another condition that
-indicates that CONFIG_I8042_KEYB is not needed for the remaining 5 boards. Many
-of the options listed are not suitable as they are not related. E.g. it would be
-odd for CONFIG_RAMBASE to imply CONFIG_I8042_KEYB.
-
-Using this search you can reduce the size of moveconfig patches.
-
-You can automatically add 'imply' statements in the Kconfig with the -a
-option::
-
- ./tools/moveconfig.py -s -i CONFIG_SCSI \
- -a CONFIG_ARCH_LS1021A,CONFIG_ARCH_LS1043A
-
-This will add 'imply SCSI' to the two CONFIG options mentioned, assuming that
-the database indicates that they do actually imply CONFIG_SCSI and do not
-already have an 'imply SCSI'.
-
-The output shows where the imply is added::
-
- 18 : CONFIG_ARCH_LS1021A arch/arm/cpu/armv7/ls102xa/Kconfig:1
- 13 : CONFIG_ARCH_LS1043A arch/arm/cpu/armv8/fsl-layerscape/Kconfig:11
- 12 : CONFIG_ARCH_LS1046A arch/arm/cpu/armv8/fsl-layerscape/Kconfig:31
-
-The first number is the number of boards which can avoid having a special
-CONFIG_SCSI option in their defconfig file if this 'imply' is added.
-The location at the right is the Kconfig file and line number where the config
-appears. For example, adding 'imply CONFIG_SCSI' to the 'config ARCH_LS1021A'
-in arch/arm/cpu/armv7/ls102xa/Kconfig at line 1 will help 18 boards to reduce
-the size of their defconfig files.
-
-If you want to add an 'imply' to every imply config in the list, you can use::
-
- ./tools/moveconfig.py -s -i CONFIG_SCSI -a all
-
-To control which ones are displayed, use -I <list> where list is a list of
-options (use '-I help' to see possible options and their meaning).
-
-To skip showing you options that already have an 'imply' attached, use -A.
-
-When you have finished adding 'imply' options you can regenerate the
-defconfig files for affected boards with something like::
-
- git show --stat | ./tools/moveconfig.py -s -d -
-
-This will regenerate only those defconfigs changed in the current commit.
-If you start with (say) 100 defconfigs being changed in the commit, and add
-a few 'imply' options as above, then regenerate, hopefully you can reduce the
-number of defconfigs changed in the commit.
-
-
-Available options
------------------
-
- -c, --color
- Surround each portion of the log with escape sequences to display it
- in color on the terminal.
-
- -C, --commit
- Create a git commit with the changes when the operation is complete. A
- standard commit message is used which may need to be edited.
-
- -d, --defconfigs
- Specify a file containing a list of defconfigs to move. The defconfig
- files can be given with shell-style wildcards. Use '-' to read from stdin.
-
- -f, --find
- Find boards with a given config combination
-
- -n, --dry-run
- Perform a trial run that does not make any changes. It is useful to
- see what is going to happen before one actually runs it.
-
- -e, --exit-on-error
- Exit immediately if Make exits with a non-zero status while processing
- a defconfig file.
-
- -s, --force-sync
- Do "make savedefconfig" forcibly for all the defconfig files.
- If not specified, "make savedefconfig" only occurs for cases
- where at least one CONFIG was moved.
-
- -S, --spl
- Look for moved config options in spl/include/autoconf.mk instead of
- include/autoconf.mk. This is useful for moving options for SPL build
- because SPL related options (mostly prefixed with CONFIG_SPL\_) are
- sometimes blocked by CONFIG_SPL_BUILD ifdef conditionals.
-
- -H, --headers-only
- Only cleanup the headers; skip the defconfig processing
-
- -j, --jobs
- Specify the number of threads to run simultaneously. If not specified,
- the number of threads is the same as the number of CPU cores.
-
- -r, --git-ref
- Specify the git ref to clone for building the autoconf.mk. If unspecified
- use the CWD. This is useful for when changes to the Kconfig affect the
- default values and you want to capture the state of the defconfig from
- before that change was in effect. If in doubt, specify a ref pre-Kconfig
- changes (use HEAD if Kconfig changes are not committed). Worst case it will
- take a bit longer to run, but will always do the right thing.
-
- -v, --verbose
- Show any build errors as boards are built
-
- -y, --yes
- Instead of prompting, automatically go ahead with all operations. This
- includes cleaning up headers, the config whitelist and the README.
-
-To see the complete list of supported options, run::
-
- tools/moveconfig.py -h
diff --git a/doc/develop/qconfig.rst b/doc/develop/qconfig.rst
new file mode 100644
index 0000000..8efb1eb
--- /dev/null
+++ b/doc/develop/qconfig.rst
@@ -0,0 +1,234 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+qconfig - Querying CONFIG options
+=================================
+
+It is not possible to see all the CONFIG options used by a board without
+building its `.config` file. This tool allows this to be done efficiently for
+all boards, or a subset, writing the results to a unified database file.
+
+This database can be queried, to find boards which used a certain combination
+of options, to aid in discovering Kconfig options which imply others.
+
+The tool also permits syncing of defconfigs, which corrects the ordering and
+drops options which are implied by others.
+
+Finally, it allows scanning the source code to look for inconsistencies in the
+use of Kconfig options.
+
+Installation
+------------
+
+You may need to install 'python3-asteval' for the 'asteval' module.
+
+How does it work?
+-----------------
+
+When building a database (`-b`), this tool runs configuration and builds
+include/autoconf.mk for every defconfig. The config options defined in Kconfig
+appear in the .config file (unless they are hidden because of unmet dependency.)
+On the other hand, the config options defined by board headers are seen
+in include/autoconf.mk.
+
+When resyncing defconfigs (`-s`) the .config is synced by "make savedefconfig"
+and the defconfig is updated with it.
+
+For faster processing, this tool is multi-threaded. It creates
+separate build directories where the out-of-tree build is run. The
+temporary build directories are automatically created and deleted as
+needed. The number of threads are chosen based on the number of the CPU
+cores of your system although you can change it via -j (--jobs) option.
+
+Note that `*.config` fragments are not supported.
+
+Toolchains
+----------
+
+Appropriate toolchains are necessary to generate include/autoconf.mk
+for all the architectures supported by U-Boot. Most of them are available
+at the kernel.org site. This tool uses the same tools as
+:doc:`../build/buildman`, so you can use `buildman --fetch-arch` to fetch
+toolchains.
+
+
+Examples
+--------
+
+To sync only X86 defconfigs::
+
+ ./tools/qconfig.py -s -d <(grep -l X86 configs/*)
+
+or::
+
+ grep -l X86 configs/* | ./tools/qconfig.py -s -d -
+
+To process CONFIG_CMD_FPGAD only for a subset of configs based on path match::
+
+ ls configs/{hrcon*,iocon*,strider*} | \
+ ./tools/qconfig.py -C CONFIG_CMD_FPGAD -d -
+
+
+Finding boards with particular CONFIG combinations
+--------------------------------------------------
+
+You can use `qconfig.py` to figure out which boards have a CONFIG enabled, or
+which do not. To use it, first build a database::
+
+ ./tools/qconfig.py -b
+
+Then you can run queries using the `-f` flag followed by a list of CONFIG terms.
+Each term is CONFIG name, with or without a tilde (~) prefix. The tool searches
+for boards which match the CONFIG name, or do not match if tilde is used. For
+example, to find boards which enabled CONFIG_SCSI but not CONFIG_BLK::
+
+ tools/qconfig.py -f SCSI ~BLK
+ 3 matches
+ pg_wcom_seli8_defconfig highbank_defconfig pg_wcom_expu1_defconfig
+
+
+Finding implied CONFIGs
+-----------------------
+
+Some CONFIG options can be implied by others and this can help to reduce
+the size of the defconfig files. For example, CONFIG_X86 implies
+CONFIG_CMD_IRQ, so we can put 'imply CMD_IRQ' under 'config X86' and
+all x86 boards will have that option, avoiding adding CONFIG_CMD_IRQ to
+each of the x86 defconfig files.
+
+This tool can help find such configs. To use it, first build a database::
+
+ ./tools/qconfig.py -b
+
+Then try to query it::
+
+ ./tools/qconfig.py -i CONFIG_I8042_KEYB
+ CONFIG_I8042_KEYB found in 33/5155 defconfigs
+ 28 : CONFIG_X86
+ 28 : CONFIG_SA_PCIEX_LENGTH
+ 28 : CONFIG_HPET_ADDRESS
+ 28 : CONFIG_MAX_PIRQ_LINKS
+ 28 : CONFIG_I8254_TIMER
+ 28 : CONFIG_I8259_PIC
+ 28 : CONFIG_RAMBASE
+ 28 : CONFIG_IRQ_SLOT_COUNT
+ 28 : CONFIG_PCIE_ECAM_SIZE
+ 28 : CONFIG_APIC
+ ...
+
+This shows a list of config options which might imply CONFIG_I8042_KEYB along
+with how many defconfigs they cover. From this you can see that CONFIG_X86
+generally implies CONFIG_I8042_KEYB but not always (28 out of 35). Therefore,
+instead of adding CONFIG_I8042_KEYB to
+the defconfig of every x86 board, you could add a single imply line to the
+Kconfig file::
+
+ config X86
+ bool "x86 architecture"
+ ...
+ imply CMD_EEPROM
+
+That will cover 28 defconfigs and you can perhaps find another condition that
+indicates that CONFIG_I8042_KEYB is not needed for the remaining 5 boards. Many
+of the options listed are not suitable as they are not related. E.g. it would be
+odd for CONFIG_RAMBASE to imply CONFIG_I8042_KEYB.
+
+Using this search you can reduce the size of qconfig patches.
+
+You can automatically add 'imply' statements in the Kconfig with the -a
+option::
+
+ ./tools/qconfig.py -s -i CONFIG_SCSI \
+ -a CONFIG_ARCH_LS1021A,CONFIG_ARCH_LS1043A
+
+This will add 'imply SCSI' to the two CONFIG options mentioned, assuming that
+the database indicates that they do actually imply CONFIG_SCSI and do not
+already have an 'imply SCSI'.
+
+The output shows where the imply is added::
+
+ 18 : CONFIG_ARCH_LS1021A arch/arm/cpu/armv7/ls102xa/Kconfig:1
+ 13 : CONFIG_ARCH_LS1043A arch/arm/cpu/armv8/fsl-layerscape/Kconfig:11
+ 12 : CONFIG_ARCH_LS1046A arch/arm/cpu/armv8/fsl-layerscape/Kconfig:31
+
+The first number is the number of boards which can avoid having a special
+CONFIG_SCSI option in their defconfig file if this 'imply' is added.
+The location at the right is the Kconfig file and line number where the config
+appears. For example, adding 'imply CONFIG_SCSI' to the 'config ARCH_LS1021A'
+in arch/arm/cpu/armv7/ls102xa/Kconfig at line 1 will help 18 boards to reduce
+the size of their defconfig files.
+
+If you want to add an 'imply' to every imply config in the list, you can use::
+
+ ./tools/qconfig.py -s -i CONFIG_SCSI -a all
+
+To control which ones are displayed, use -I <list> where list is a list of
+options (use '-I help' to see possible options and their meaning).
+
+To skip showing you options that already have an 'imply' attached, use -A.
+
+When you have finished adding 'imply' options you can regenerate the
+defconfig files for affected boards with something like::
+
+ git show --stat | ./tools/qconfig.py -s -d -
+
+This will regenerate only those defconfigs changed in the current commit.
+If you start with (say) 100 defconfigs being changed in the commit, and add
+a few 'imply' options as above, then regenerate, hopefully you can reduce the
+number of defconfigs changed in the commit.
+
+
+Available options
+-----------------
+
+ --nocolour
+ Disables colouring of output. This is normally used when writing to a
+ terminal.
+
+ -C, --commit
+ Create a git commit with the changes when the operation is complete. A
+ standard commit message is used which may need to be edited.
+
+ -d, --defconfigs
+ Specify a file containing a list of defconfigs to move. The defconfig
+ files can be given with shell-style wildcards. Use '-' to read from stdin.
+
+ -f, --find
+ Find boards with a given config combination
+
+ -n, --dry-run
+ Perform a trial run that does not make any changes. It is useful to
+ see what is going to happen before one actually runs it.
+
+ -e, --exit-on-error
+ Exit immediately if Make exits with a non-zero status while processing
+ a defconfig file.
+
+ -s, --force-sync
+ Do "make savedefconfig" forcibly for all the defconfig files.
+ If not specified, "make savedefconfig" only occurs for cases
+ where at least one CONFIG was moved.
+
+ -S, --spl
+ Look for moved config options in spl/include/autoconf.mk instead of
+ include/autoconf.mk. This is useful for moving options for SPL build
+ because SPL related options (mostly prefixed with CONFIG_SPL\_) are
+ sometimes blocked by CONFIG_SPL_BUILD ifdef conditionals.
+
+ -j, --jobs
+ Specify the number of threads to run simultaneously. If not specified,
+ the number of threads is the same as the number of CPU cores.
+
+ -r, --git-ref
+ Specify the git ref to clone for building the autoconf.mk. If unspecified
+ use the CWD. This is useful for when changes to the Kconfig affect the
+ default values and you want to capture the state of the defconfig from
+ before that change was in effect. If in doubt, specify a ref pre-Kconfig
+ changes (use HEAD if Kconfig changes are not committed). Worst case it will
+ take a bit longer to run, but will always do the right thing.
+
+ -v, --verbose
+ Show any build errors as boards are built
+
+To see the complete list of supported options, run::
+
+ tools/qconfig.py -h
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index 7234338..2773313 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -48,14 +48,14 @@
Current Status
--------------
-* U-Boot v2023.10 was released on Mon 02 October 2023.
+* U-Boot v2024.01 was released on Mon 08 January 2024.
-* The Merge Window for the next release (v2024.01) is **open** until the -rc1
- release on Mon 23 October 2023.
+* The Merge Window for the next release (v2024.04) is **open** until the -rc1
+ release on Mon 29 January 2024.
* The next branch is now **closed**.
-* Release "v2024.01" is scheduled for 08 January 2024.
+* Release "v2024.04" is scheduled for 02 April 2024.
Future Releases
---------------
@@ -65,29 +65,27 @@
.. For the next scheduled release, release candidates were made on::
-.. * U-Boot v2024.01-rc1 was released on Mon 23 October 2023.
+.. * U-Boot v2024.01-rc1 was released on Mon 29 January 2024.
-.. * U-Boot v2024.01-rc2 was released on Mon 06 November 2023.
+.. * U-Boot v2024.01-rc2 was released on Mon 12 February 2024.
-.. * U-Boot v2024.01-rc3 was released on Mon 20 November 2023.
+.. * U-Boot v2024.01-rc3 was released on Mon 26 February 2024.
-.. * U-Boot v2024.01-rc4 was released on Mon 04 December 2023.
+.. * U-Boot v2024.01-rc4 was released on Mon 11 March 2024.
-.. * U-Boot v2024.01-rc5 was released on Mon 18 December 2023.
-
-.. * U-Boot v2024.01-rc6 was released on Tue 02 January 2024.
+.. * U-Boot v2024.01-rc5 was released on Mon 25 March 2024.
Please note that the following dates are planned only and may be deviated from
as needed.
-* "v2024.01": end of MW = Mon, Oct 23, 2023; release = Mon, Jan 08, 2024
-
* "v2024.04": end of MW = Mon, Jan 29, 2024; release = Tue, Apr 02, 2024
* "v2024.07": end of MW = Mon, Apr 22, 2024; release = Mon, Jul 01, 2024
* "v2024.10": end of MW = Mon, Jul 22, 2024; release = Mon, Oct 07, 2024
+* "v2025.01": end of MW = Mon, Oct 21, 2024; release = Mon, Jan 06, 2025
+
Previous Releases
-----------------
@@ -95,6 +93,8 @@
<https://source.denx.de/u-boot/gitdm>`_, which was originally created by
Jonathan Corbet.
+* :doc:`statistics/u-boot-stats-v2024.01` which was released on 08 January 2024.
+
* :doc:`statistics/u-boot-stats-v2023.10` which was released on 02 October 2023.
* :doc:`statistics/u-boot-stats-v2023.07` which was released on 10 July 2023.
diff --git a/doc/develop/sending_patches.rst b/doc/develop/sending_patches.rst
index ba73d0d..5a6962f 100644
--- a/doc/develop/sending_patches.rst
+++ b/doc/develop/sending_patches.rst
@@ -363,7 +363,7 @@
* Awaiting Upstream
- * Superseeded
+ * Superseded
* Deferred
@@ -399,7 +399,7 @@
and has not merged yet to master, or has queued the patch up to be submitted
to be merged, but has not yet.
-* Superseeded: Patches are marked as 'superseeded' when the poster submits a
+* Superseded: Patches are marked as 'superseded' when the poster submits a
new version of these patches.
* Deferred: Deferred usually means the patch depends on something else that
diff --git a/doc/develop/statistics/u-boot-stats-v2024.01.rst b/doc/develop/statistics/u-boot-stats-v2024.01.rst
new file mode 100644
index 0000000..4beb21f
--- /dev/null
+++ b/doc/develop/statistics/u-boot-stats-v2024.01.rst
@@ -0,0 +1,844 @@
+:orphan:
+
+Release Statistics for U-Boot v2024.01
+======================================
+
+* Processed 1564 changesets from 191 developers
+
+* 25 employers found
+
+* A total of 100266 lines added, 38766 removed (delta 61500)
+
+.. table:: Developers with the most changesets
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Simon Glass 273 (17.5%)
+ Marek Vasut 194 (12.4%)
+ Michal Simek 64 (4.1%)
+ Heinrich Schuchardt 51 (3.3%)
+ Tom Rini 50 (3.2%)
+ Jonas Karlman 46 (2.9%)
+ Sean Anderson 38 (2.4%)
+ Svyatoslav Ryhel 36 (2.3%)
+ Nishanth Menon 35 (2.2%)
+ Andre Przywara 33 (2.1%)
+ Paul Barker 32 (2.0%)
+ Venkatesh Yadav Abbarapu 28 (1.8%)
+ Bryan Brattlof 26 (1.7%)
+ Sughosh Ganu 21 (1.3%)
+ AKASHI Takahiro 20 (1.3%)
+ Bin Meng 19 (1.2%)
+ Alexey Romanov 19 (1.2%)
+ Chanho Park 18 (1.2%)
+ Dario Binacchi 16 (1.0%)
+ Sam Protsenko 15 (1.0%)
+ Dan Carpenter 15 (1.0%)
+ Tim Harvey 14 (0.9%)
+ Fabio Estevam 14 (0.9%)
+ Roger Quadros 13 (0.8%)
+ Rasmus Villemoes 13 (0.8%)
+ Randolph 11 (0.7%)
+ Tony Dinh 11 (0.7%)
+ Alexander Dahl 11 (0.7%)
+ Igor Prusov 9 (0.6%)
+ Ilias Apalodimas 9 (0.6%)
+ Hector Martin 9 (0.6%)
+ Samuel Holland 9 (0.6%)
+ Johan Jonker 9 (0.6%)
+ Matthias Schiffer 9 (0.6%)
+ Neha Malcom Francis 8 (0.5%)
+ Chris Packham 8 (0.5%)
+ Joao Marcos Costa 8 (0.5%)
+ Jan Kiszka 7 (0.4%)
+ Jim Liu 7 (0.4%)
+ Yang Xiwen 7 (0.4%)
+ Marcel Ziswiler 7 (0.4%)
+ Siddharth Vadapalli 7 (0.4%)
+ Gatien Chevallier 7 (0.4%)
+ Neil Armstrong 6 (0.4%)
+ Masahisa Kojima 6 (0.4%)
+ Udit Kumar 6 (0.4%)
+ Eddie James 6 (0.4%)
+ Sam Edwards 6 (0.4%)
+ Teresa Remmet 6 (0.4%)
+ Manorit Chawdhry 6 (0.4%)
+ Laurentiu Tudor 6 (0.4%)
+ Joshua Watt 6 (0.4%)
+ Mattijs Korpershoek 5 (0.3%)
+ Shantur Rathore 5 (0.3%)
+ Patrick Delaunay 5 (0.3%)
+ Artur Rojek 5 (0.3%)
+ Mikhail Kshevetskiy 5 (0.3%)
+ FUKAUMI Naoki 5 (0.3%)
+ Ashok Reddy Soma 5 (0.3%)
+ Mark Kettenis 4 (0.3%)
+ John Clark 4 (0.3%)
+ Philip Oberfichtner 4 (0.3%)
+ Milan P. Stanić 4 (0.3%)
+ Tom Fitzhenry 4 (0.3%)
+ Josua Mayer 4 (0.3%)
+ Elaine Zhang 4 (0.3%)
+ Sébastien Szymanski 4 (0.3%)
+ Andrew Davis 4 (0.3%)
+ Manoj Sai 4 (0.3%)
+ Alper Nebi Yasak 4 (0.3%)
+ Emanuele Ghidoli 3 (0.2%)
+ Alexander Gendin 3 (0.2%)
+ Hiago De Franco 3 (0.2%)
+ Andrejs Cainikovs 3 (0.2%)
+ Yu Chien Peter Lin 3 (0.2%)
+ Quentin Schulz 3 (0.2%)
+ Tim Lunn 3 (0.2%)
+ Patrice Chotard 3 (0.2%)
+ Algapally Santosh Sagar 3 (0.2%)
+ Abdellatif El Khlifi 3 (0.2%)
+ Fedor Ross 3 (0.2%)
+ Reid Tonking 3 (0.2%)
+ Massimo Pegorer 3 (0.2%)
+ Frank Wunderlich 3 (0.2%)
+ Fabrice Gasnier 3 (0.2%)
+ Thomas Mittelstaedt 3 (0.2%)
+ Baruch Siach 2 (0.1%)
+ Peter Robinson 2 (0.1%)
+ Hugo Villeneuve 2 (0.1%)
+ Janne Grunau 2 (0.1%)
+ Simon Holesch 2 (0.1%)
+ Dylan Corrales 2 (0.1%)
+ Oleksandr Suvorov 2 (0.1%)
+ Tejas Bhumkar 2 (0.1%)
+ Amit Kumar Mahapatra 2 (0.1%)
+ Robert Marko 2 (0.1%)
+ Sean Edmond 2 (0.1%)
+ Maksim Kiselev 2 (0.1%)
+ Wei Chen 2 (0.1%)
+ Francois Berder 2 (0.1%)
+ Lukas Funke 2 (0.1%)
+ Lars Feyaerts 2 (0.1%)
+ Love Kumar 2 (0.1%)
+ Suman Anna 2 (0.1%)
+ Laurent Pinchart 2 (0.1%)
+ Harald Seiler 2 (0.1%)
+ Neal Frager 2 (0.1%)
+ Shiji Yang 2 (0.1%)
+ Anthony Loiseau 1 (0.1%)
+ Moritz Fischer 1 (0.1%)
+ Miquel Raynal 1 (0.1%)
+ Mikhail Kalashnikov 1 (0.1%)
+ Stephen Graf 1 (0.1%)
+ Chukun Pan 1 (0.1%)
+ Weizhao Ouyang 1 (0.1%)
+ Stefan Roese 1 (0.1%)
+ Cong Dang 1 (0.1%)
+ Jonathan Corbet 1 (0.1%)
+ Nikita Yushchenko 1 (0.1%)
+ John Keeping 1 (0.1%)
+ Ludwig Kormann 1 (0.1%)
+ Igor Opaniuk 1 (0.1%)
+ Bhupesh Sharma 1 (0.1%)
+ Ibai Erkiaga 1 (0.1%)
+ Piyush Mehta 1 (0.1%)
+ Linus Walleij 1 (0.1%)
+ Dmitry Rokosov 1 (0.1%)
+ Frank de Brabander 1 (0.1%)
+ Dylan Hung 1 (0.1%)
+ Ley Foon Tan 1 (0.1%)
+ Caleb Connolly 1 (0.1%)
+ Maxim Cournoyer 1 (0.1%)
+ Yong-Xuan Wang 1 (0.1%)
+ Eugen Hristev 1 (0.1%)
+ Nathan Barrett-Morrison 1 (0.1%)
+ Emekcan Aras 1 (0.1%)
+ Vishal Mahaveer 1 (0.1%)
+ Wojciech Nizinski 1 (0.1%)
+ Michel Alex 1 (0.1%)
+ Martin Fäcknitz 1 (0.1%)
+ Marek Behún 1 (0.1%)
+ Andrey Skvortsov 1 (0.1%)
+ Yurii Monakov 1 (0.1%)
+ Ricardo Pardini 1 (0.1%)
+ Matwey V. Kornilov 1 (0.1%)
+ Guochun Huang 1 (0.1%)
+ Okhunjon Sobirjonov 1 (0.1%)
+ Mayuresh Chitale 1 (0.1%)
+ Guillaume La Roque 1 (0.1%)
+ Ye Li 1 (0.1%)
+ Alice Guo 1 (0.1%)
+ Joao Paulo Goncalves 1 (0.1%)
+ Eduard Strehlau 1 (0.1%)
+ Andrej Rosano 1 (0.1%)
+ Ricardo Salveti 1 (0.1%)
+ Michael Scott 1 (0.1%)
+ Dominik Haller 1 (0.1%)
+ Nikhil M Jain 1 (0.1%)
+ Roman Azarenko 1 (0.1%)
+ Nicolò Veronese 1 (0.1%)
+ Andrii Chepurnyi 1 (0.1%)
+ Han Xu 1 (0.1%)
+ Patryk Biel 1 (0.1%)
+ Polak, Leszek 1 (0.1%)
+ Tanmay Shah 1 (0.1%)
+ shengfei Xu 1 (0.1%)
+ Joseph Chen 1 (0.1%)
+ Anatolij Gustschin 1 (0.1%)
+ Kuan Lim Lee 1 (0.1%)
+ Roger Knecht 1 (0.1%)
+ Jesse Taube 1 (0.1%)
+ Rong Tao 1 (0.1%)
+ Andy Shevchenko 1 (0.1%)
+ Troy Kisky 1 (0.1%)
+ Thippeswamy Havalige 1 (0.1%)
+ Srinivas Neeli 1 (0.1%)
+ Saeed Nowshadi 1 (0.1%)
+ Maxim Kochetkov 1 (0.1%)
+ Christian Taedcke 1 (0.1%)
+ Trevor Woerner 1 (0.1%)
+ Nicolas Frattaroli 1 (0.1%)
+ Li Hua Qian 1 (0.1%)
+ Robert Nelson 1 (0.1%)
+ Łukasz Stelmach 1 (0.1%)
+ Elena Popa 1 (0.1%)
+ Naveen Kumar Chaudhary 1 (0.1%)
+ Kevin Chen 1 (0.1%)
+ Sergei Antonov 1 (0.1%)
+ Jason Kacines 1 (0.1%)
+ Ilya Lukin 1 (0.1%)
+ Mihai Sain 1 (0.1%)
+ ==================================== =====
+
+
+.. table:: Developers with the most changed lines
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Simon Glass 11496 (9.8%)
+ Marek Vasut 8067 (6.8%)
+ Michal Simek 7518 (6.4%)
+ Laurentiu Tudor 6213 (5.3%)
+ Paul Barker 5361 (4.5%)
+ Andre Przywara 4529 (3.8%)
+ Tim Harvey 4234 (3.6%)
+ Nishanth Menon 3762 (3.2%)
+ Jonas Karlman 3755 (3.2%)
+ Dario Binacchi 3615 (3.1%)
+ AKASHI Takahiro 3492 (3.0%)
+ Robert Nelson 3243 (2.8%)
+ FUKAUMI Naoki 2908 (2.5%)
+ Roger Quadros 2836 (2.4%)
+ Neha Malcom Francis 2822 (2.4%)
+ Svyatoslav Ryhel 2768 (2.3%)
+ Manorit Chawdhry 2699 (2.3%)
+ Tom Rini 2320 (2.0%)
+ Sean Anderson 2224 (1.9%)
+ Johan Jonker 1984 (1.7%)
+ Heinrich Schuchardt 1886 (1.6%)
+ Sughosh Ganu 1824 (1.5%)
+ Igor Prusov 1710 (1.5%)
+ Eddie James 1481 (1.3%)
+ Bryan Brattlof 1357 (1.2%)
+ Tom Fitzhenry 1323 (1.1%)
+ Reid Tonking 1209 (1.0%)
+ John Clark 1202 (1.0%)
+ Tony Dinh 1163 (1.0%)
+ Alexey Romanov 1159 (1.0%)
+ Sébastien Szymanski 1129 (1.0%)
+ Frank Wunderlich 1035 (0.9%)
+ Mikhail Kshevetskiy 926 (0.8%)
+ Chanho Park 880 (0.7%)
+ Teresa Remmet 781 (0.7%)
+ Mihai Sain 781 (0.7%)
+ Yang Xiwen 652 (0.6%)
+ Patrice Chotard 605 (0.5%)
+ Artur Rojek 595 (0.5%)
+ Alexander Gendin 516 (0.4%)
+ Yu Chien Peter Lin 421 (0.4%)
+ Randolph 379 (0.3%)
+ Andrew Davis 354 (0.3%)
+ Joshua Watt 343 (0.3%)
+ Joao Marcos Costa 334 (0.3%)
+ Alexander Dahl 305 (0.3%)
+ Mikhail Kalashnikov 294 (0.2%)
+ Sam Edwards 288 (0.2%)
+ Neil Armstrong 282 (0.2%)
+ Venkatesh Yadav Abbarapu 277 (0.2%)
+ Samuel Holland 266 (0.2%)
+ Philip Oberfichtner 266 (0.2%)
+ Gatien Chevallier 264 (0.2%)
+ Janne Grunau 231 (0.2%)
+ Matthias Schiffer 230 (0.2%)
+ Bin Meng 201 (0.2%)
+ Andrii Chepurnyi 181 (0.2%)
+ Marek Behún 180 (0.2%)
+ Jan Kiszka 179 (0.2%)
+ Algapally Santosh Sagar 174 (0.1%)
+ Linus Walleij 170 (0.1%)
+ Udit Kumar 165 (0.1%)
+ Patrick Delaunay 142 (0.1%)
+ Rasmus Villemoes 128 (0.1%)
+ Fabio Estevam 126 (0.1%)
+ Shiji Yang 123 (0.1%)
+ Elaine Zhang 111 (0.1%)
+ Oleksandr Suvorov 108 (0.1%)
+ Siddharth Vadapalli 107 (0.1%)
+ Fabrice Gasnier 103 (0.1%)
+ Sergei Antonov 103 (0.1%)
+ Kuan Lim Lee 102 (0.1%)
+ Alper Nebi Yasak 99 (0.1%)
+ Marcel Ziswiler 97 (0.1%)
+ Christian Taedcke 95 (0.1%)
+ Tim Lunn 93 (0.1%)
+ Hector Martin 90 (0.1%)
+ Emanuele Ghidoli 89 (0.1%)
+ Nicolas Frattaroli 89 (0.1%)
+ Mark Kettenis 88 (0.1%)
+ Fedor Ross 86 (0.1%)
+ Chris Packham 84 (0.1%)
+ Love Kumar 84 (0.1%)
+ Robert Marko 80 (0.1%)
+ Sam Protsenko 78 (0.1%)
+ Vishal Mahaveer 75 (0.1%)
+ Ilias Apalodimas 70 (0.1%)
+ Ashok Reddy Soma 64 (0.1%)
+ Andrejs Cainikovs 59 (0.1%)
+ Peter Robinson 58 (0.0%)
+ Jesse Taube 57 (0.0%)
+ Quentin Schulz 55 (0.0%)
+ Tejas Bhumkar 54 (0.0%)
+ Suman Anna 51 (0.0%)
+ Ibai Erkiaga 49 (0.0%)
+ Masahisa Kojima 45 (0.0%)
+ Sean Edmond 45 (0.0%)
+ Maxim Cournoyer 45 (0.0%)
+ Laurent Pinchart 44 (0.0%)
+ Jim Liu 43 (0.0%)
+ Lars Feyaerts 42 (0.0%)
+ Massimo Pegorer 41 (0.0%)
+ Manoj Sai 40 (0.0%)
+ Joseph Chen 40 (0.0%)
+ Simon Holesch 39 (0.0%)
+ Josua Mayer 35 (0.0%)
+ Hiago De Franco 35 (0.0%)
+ Tanmay Shah 33 (0.0%)
+ Frank de Brabander 32 (0.0%)
+ Shantur Rathore 31 (0.0%)
+ Igor Opaniuk 30 (0.0%)
+ Dan Carpenter 28 (0.0%)
+ Ludwig Kormann 27 (0.0%)
+ Maxim Kochetkov 26 (0.0%)
+ Neal Frager 23 (0.0%)
+ Mattijs Korpershoek 22 (0.0%)
+ Baruch Siach 22 (0.0%)
+ Ley Foon Tan 20 (0.0%)
+ Andy Shevchenko 20 (0.0%)
+ shengfei Xu 19 (0.0%)
+ Eduard Strehlau 16 (0.0%)
+ Yurii Monakov 14 (0.0%)
+ Ye Li 13 (0.0%)
+ Dylan Hung 12 (0.0%)
+ Michel Alex 12 (0.0%)
+ Matwey V. Kornilov 12 (0.0%)
+ Milan P. Stanić 11 (0.0%)
+ Li Hua Qian 11 (0.0%)
+ Wei Chen 10 (0.0%)
+ Mayuresh Chitale 10 (0.0%)
+ Polak, Leszek 9 (0.0%)
+ Dylan Corrales 8 (0.0%)
+ Andrey Skvortsov 8 (0.0%)
+ Troy Kisky 8 (0.0%)
+ Naveen Kumar Chaudhary 8 (0.0%)
+ Okhunjon Sobirjonov 7 (0.0%)
+ Roman Azarenko 7 (0.0%)
+ Han Xu 7 (0.0%)
+ Anatolij Gustschin 7 (0.0%)
+ Thomas Mittelstaedt 6 (0.0%)
+ Amit Kumar Mahapatra 6 (0.0%)
+ Eugen Hristev 6 (0.0%)
+ Abdellatif El Khlifi 5 (0.0%)
+ Harald Seiler 5 (0.0%)
+ Anthony Loiseau 5 (0.0%)
+ Chukun Pan 5 (0.0%)
+ Weizhao Ouyang 5 (0.0%)
+ Roger Knecht 5 (0.0%)
+ Trevor Woerner 5 (0.0%)
+ Ilya Lukin 5 (0.0%)
+ Hugo Villeneuve 4 (0.0%)
+ Lukas Funke 4 (0.0%)
+ Jonathan Corbet 4 (0.0%)
+ Ricardo Salveti 4 (0.0%)
+ Nicolò Veronese 4 (0.0%)
+ Saeed Nowshadi 4 (0.0%)
+ Maksim Kiselev 3 (0.0%)
+ Caleb Connolly 3 (0.0%)
+ Guillaume La Roque 3 (0.0%)
+ Jason Kacines 3 (0.0%)
+ Francois Berder 2 (0.0%)
+ Stephen Graf 2 (0.0%)
+ Nikita Yushchenko 2 (0.0%)
+ Bhupesh Sharma 2 (0.0%)
+ Piyush Mehta 2 (0.0%)
+ Wojciech Nizinski 2 (0.0%)
+ Alice Guo 2 (0.0%)
+ Joao Paulo Goncalves 2 (0.0%)
+ Andrej Rosano 2 (0.0%)
+ Srinivas Neeli 2 (0.0%)
+ Łukasz Stelmach 2 (0.0%)
+ Moritz Fischer 1 (0.0%)
+ Miquel Raynal 1 (0.0%)
+ Stefan Roese 1 (0.0%)
+ Cong Dang 1 (0.0%)
+ John Keeping 1 (0.0%)
+ Dmitry Rokosov 1 (0.0%)
+ Yong-Xuan Wang 1 (0.0%)
+ Nathan Barrett-Morrison 1 (0.0%)
+ Emekcan Aras 1 (0.0%)
+ Martin Fäcknitz 1 (0.0%)
+ Ricardo Pardini 1 (0.0%)
+ Guochun Huang 1 (0.0%)
+ Michael Scott 1 (0.0%)
+ Dominik Haller 1 (0.0%)
+ Nikhil M Jain 1 (0.0%)
+ Patryk Biel 1 (0.0%)
+ Rong Tao 1 (0.0%)
+ Thippeswamy Havalige 1 (0.0%)
+ Elena Popa 1 (0.0%)
+ Kevin Chen 1 (0.0%)
+ ==================================== =====
+
+
+.. table:: Developers with the most lines removed
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Laurentiu Tudor 5975 (15.4%)
+ Dario Binacchi 3012 (7.8%)
+ Tom Rini 1059 (2.7%)
+ Andrew Davis 346 (0.9%)
+ Tim Harvey 83 (0.2%)
+ Chris Packham 58 (0.1%)
+ Peter Robinson 58 (0.1%)
+ Ilias Apalodimas 21 (0.1%)
+ Jesse Taube 21 (0.1%)
+ Ibai Erkiaga 16 (0.0%)
+ Eduard Strehlau 16 (0.0%)
+ Bin Meng 12 (0.0%)
+ Matwey V. Kornilov 10 (0.0%)
+ Andy Shevchenko 9 (0.0%)
+ Ilya Lukin 5 (0.0%)
+ Trevor Woerner 4 (0.0%)
+ Maxim Kochetkov 2 (0.0%)
+ Piyush Mehta 2 (0.0%)
+ Joao Paulo Goncalves 2 (0.0%)
+ Abdellatif El Khlifi 1 (0.0%)
+ Stephen Graf 1 (0.0%)
+ ==================================== =====
+
+
+.. table:: Developers with the most signoffs (total 215)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Michal Simek 55 (25.6%)
+ Neil Armstrong 29 (13.5%)
+ Minkyu Kang 13 (6.0%)
+ Heinrich Schuchardt 9 (4.2%)
+ Peng Fan 7 (3.3%)
+ Ilias Apalodimas 6 (2.8%)
+ Dario Binacchi 5 (2.3%)
+ Bin Meng 5 (2.3%)
+ Frieder Schrempf 5 (2.3%)
+ Marc Kleine-Budde 5 (2.3%)
+ Alexandre Torgue 5 (2.3%)
+ Mattijs Korpershoek 4 (1.9%)
+ Ashok Reddy Soma 4 (1.9%)
+ Patrice Chotard 4 (1.9%)
+ Marek Vasut 4 (1.9%)
+ Simon Glass 4 (1.9%)
+ Tom Rini 3 (1.4%)
+ Oleksandr Suvorov 3 (1.4%)
+ Venkatesh Yadav Abbarapu 3 (1.4%)
+ Jonas Karlman 3 (1.4%)
+ Andre Przywara 3 (1.4%)
+ Miquel Raynal 2 (0.9%)
+ Francesco Dolcini 2 (0.9%)
+ Rui Miguel Silva 2 (0.9%)
+ Qi Feng 2 (0.9%)
+ Suniel Mahesh 2 (0.9%)
+ Siddharth Vadapalli 2 (0.9%)
+ Neha Malcom Francis 2 (0.9%)
+ Alexey Romanov 2 (0.9%)
+ Sébastien Szymanski 2 (0.9%)
+ Roger Quadros 2 (0.9%)
+ Nishanth Menon 2 (0.9%)
+ Andy Shevchenko 1 (0.5%)
+ Abdellatif El Khlifi 1 (0.5%)
+ Jon Mason 1 (0.5%)
+ Martin Kurbanov 1 (0.5%)
+ Jakub Klama 1 (0.5%)
+ Marcin Jabrzyk 1 (0.5%)
+ Valerio 'ftp21' Mancini 1 (0.5%)
+ Lee Jones 1 (0.5%)
+ Geert Uytterhoeven 1 (0.5%)
+ Hiago De Franco 1 (0.5%)
+ Patrick Delaunay 1 (0.5%)
+ Elaine Zhang 1 (0.5%)
+ Fabio Estevam 1 (0.5%)
+ Manorit Chawdhry 1 (0.5%)
+ ==================================== =====
+
+
+.. table:: Developers with the most reviews (total 990)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Simon Glass 251 (25.4%)
+ Kever Yang 67 (6.8%)
+ Tom Rini 66 (6.7%)
+ Nishanth Menon 55 (5.6%)
+ Marek Vasut 50 (5.1%)
+ Mattijs Korpershoek 47 (4.7%)
+ Bin Meng 38 (3.8%)
+ Patrice Chotard 33 (3.3%)
+ Fabio Estevam 33 (3.3%)
+ Leo Yu-Chi Liang 33 (3.3%)
+ Heinrich Schuchardt 24 (2.4%)
+ Stefan Roese 23 (2.3%)
+ Patrick Delaunay 20 (2.0%)
+ Biju Das 17 (1.7%)
+ Neil Armstrong 16 (1.6%)
+ Lad Prabhakar 16 (1.6%)
+ Sean Anderson 16 (1.6%)
+ Ilias Apalodimas 15 (1.5%)
+ Etienne Carriere 14 (1.4%)
+ Jaehoon Chung 12 (1.2%)
+ Andre Przywara 11 (1.1%)
+ Neha Malcom Francis 9 (0.9%)
+ Ramon Fried 9 (0.9%)
+ Bhupesh Sharma 7 (0.7%)
+ Jernej Skrabec 6 (0.6%)
+ Yannic Moog 6 (0.6%)
+ Samuel Holland 6 (0.6%)
+ Heiko Schocher 5 (0.5%)
+ Sam Edwards 5 (0.5%)
+ Manorit Chawdhry 4 (0.4%)
+ Mark Kettenis 4 (0.4%)
+ Peng Fan 3 (0.3%)
+ Roger Quadros 3 (0.3%)
+ Yoshihiro Shimoda 3 (0.3%)
+ Heiko Stuebner 3 (0.3%)
+ Michael Trimarchi 3 (0.3%)
+ Marcel Ziswiler 3 (0.3%)
+ Paul Barker 3 (0.3%)
+ Frieder Schrempf 2 (0.2%)
+ Weizhao Ouyang 2 (0.2%)
+ Xavier Drudis Ferran 2 (0.2%)
+ Angelo Dureghello 2 (0.2%)
+ Christopher Obbard 2 (0.2%)
+ Mike Frysinger 2 (0.2%)
+ Dhruva Gole 2 (0.2%)
+ Qu Wenruo 2 (0.2%)
+ Linus Walleij 2 (0.2%)
+ Svyatoslav Ryhel 2 (0.2%)
+ Jonas Karlman 1 (0.1%)
+ Andrew Davis 1 (0.1%)
+ Nikhil M Jain 1 (0.1%)
+ Eric Curtin 1 (0.1%)
+ Neal Gompa 1 (0.1%)
+ Dragan Simic 1 (0.1%)
+ Daniel Schwierzeck 1 (0.1%)
+ Ryan Chen 1 (0.1%)
+ Lukasz Majewski 1 (0.1%)
+ Rick Chen 1 (0.1%)
+ Anup Patel 1 (0.1%)
+ Kristian Amlie 1 (0.1%)
+ Sebastian Reichel 1 (0.1%)
+ Martyn Welch 1 (0.1%)
+ Grzegorz Szymaszek 1 (0.1%)
+ Raphaël Gallais-Pou 1 (0.1%)
+ Wei Liang Lim 1 (0.1%)
+ Adam Ford 1 (0.1%)
+ Alexander Graf 1 (0.1%)
+ Devarsh Thakkar 1 (0.1%)
+ Michal Suchánek 1 (0.1%)
+ Rafał Miłecki 1 (0.1%)
+ Weijie Gao 1 (0.1%)
+ Jan Kiszka 1 (0.1%)
+ Sam Protsenko 1 (0.1%)
+ Ye Li 1 (0.1%)
+ Marek Behún 1 (0.1%)
+ Bryan Brattlof 1 (0.1%)
+ Mikhail Kalashnikov 1 (0.1%)
+ Randolph 1 (0.1%)
+ Tony Dinh 1 (0.1%)
+ ==================================== =====
+
+
+.. table:: Developers with the most test credits (total 131)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Tom Rini 29 (22.1%)
+ Mattijs Korpershoek 22 (16.8%)
+ Joao Paulo Goncalves 8 (6.1%)
+ Bhupesh Sharma 6 (4.6%)
+ Yannic Moog 6 (4.6%)
+ Samuel Holland 5 (3.8%)
+ Svyatoslav Ryhel 5 (3.8%)
+ Simon Glass 4 (3.1%)
+ Nishanth Menon 4 (3.1%)
+ Ivan T.Ivanov 4 (3.1%)
+ Milan P. Stanić 4 (3.1%)
+ Thuan Nguyen Hong 3 (2.3%)
+ Marek Vasut 2 (1.5%)
+ Ilias Apalodimas 2 (1.5%)
+ Sam Edwards 2 (1.5%)
+ Michal Simek 2 (1.5%)
+ Andreas Westman Dorcsak 2 (1.5%)
+ Sean Anderson 1 (0.8%)
+ Jaehoon Chung 1 (0.8%)
+ Neha Malcom Francis 1 (0.8%)
+ Marcel Ziswiler 1 (0.8%)
+ Paul Barker 1 (0.8%)
+ Christopher Obbard 1 (0.8%)
+ Mikhail Kalashnikov 1 (0.8%)
+ Andy Shevchenko 1 (0.8%)
+ Stephen Graf 1 (0.8%)
+ Bob McChesney 1 (0.8%)
+ Piotr Oniszczuk 1 (0.8%)
+ Maksim Kurnosenko 1 (0.8%)
+ Henrik Grimler 1 (0.8%)
+ Bao Cheng Su 1 (0.8%)
+ Kevin Amadiva 1 (0.8%)
+ Chris Paterson 1 (0.8%)
+ Masahisa Kojima 1 (0.8%)
+ Maksim Kiselev 1 (0.8%)
+ Shantur Rathore 1 (0.8%)
+ Chanho Park 1 (0.8%)
+ FUKAUMI Naoki 1 (0.8%)
+ ==================================== =====
+
+
+.. table:: Developers who gave the most tested-by credits (total 131)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Bryan Brattlof 26 (19.8%)
+ Nishanth Menon 18 (13.7%)
+ Marek Vasut 17 (13.0%)
+ Andre Przywara 10 (7.6%)
+ Joao Marcos Costa 8 (6.1%)
+ Svyatoslav Ryhel 7 (5.3%)
+ Simon Glass 6 (4.6%)
+ Teresa Remmet 6 (4.6%)
+ Roger Quadros 5 (3.8%)
+ Jonas Karlman 5 (3.8%)
+ Heinrich Schuchardt 4 (3.1%)
+ Paul Barker 3 (2.3%)
+ Tom Rini 2 (1.5%)
+ Sam Edwards 2 (1.5%)
+ Andrew Davis 2 (1.5%)
+ Ilias Apalodimas 1 (0.8%)
+ Sean Anderson 1 (0.8%)
+ Mikhail Kalashnikov 1 (0.8%)
+ Jan Kiszka 1 (0.8%)
+ Lukas Funke 1 (0.8%)
+ Guillaume La Roque 1 (0.8%)
+ Wojciech Nizinski 1 (0.8%)
+ Massimo Pegorer 1 (0.8%)
+ Eddie James 1 (0.8%)
+ Robert Nelson 1 (0.8%)
+ ==================================== =====
+
+
+.. table:: Developers with the most report credits (total 25)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Nishanth Menon 3 (12.0%)
+ Tom Rini 2 (8.0%)
+ Sean Anderson 2 (8.0%)
+ Date Huang 2 (8.0%)
+ Vincent Stehlé 2 (8.0%)
+ Andre Przywara 1 (4.0%)
+ Roger Quadros 1 (4.0%)
+ Jonas Karlman 1 (4.0%)
+ Heinrich Schuchardt 1 (4.0%)
+ Mikhail Kalashnikov 1 (4.0%)
+ Bao Cheng Su 1 (4.0%)
+ Fabio Estevam 1 (4.0%)
+ Weizhao Ouyang 1 (4.0%)
+ Martin Liška 1 (4.0%)
+ Peter Hoyes 1 (4.0%)
+ Madushan Nishantha 1 (4.0%)
+ Ivan Ivanov 1 (4.0%)
+ Jayantajit Gogoi 1 (4.0%)
+ Suman Anna 1 (4.0%)
+ ==================================== =====
+
+
+.. table:: Developers who gave the most report credits (total 25)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Simon Glass 6 (24.0%)
+ Nishanth Menon 3 (12.0%)
+ Marek Vasut 3 (12.0%)
+ Andre Przywara 2 (8.0%)
+ Heinrich Schuchardt 2 (8.0%)
+ Siddharth Vadapalli 2 (8.0%)
+ Roger Quadros 1 (4.0%)
+ Jan Kiszka 1 (4.0%)
+ Massimo Pegorer 1 (4.0%)
+ Samuel Holland 1 (4.0%)
+ Jonathan Corbet 1 (4.0%)
+ Rasmus Villemoes 1 (4.0%)
+ Udit Kumar 1 (4.0%)
+ ==================================== =====
+
+
+.. table:: Top changeset contributors by employer
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ (Unknown) 515 (32.9%)
+ Google LLC 274 (17.5%)
+ Renesas Electronics 177 (11.3%)
+ AMD 114 (7.3%)
+ Texas Instruments 100 (6.4%)
+ Linaro 95 (6.1%)
+ DENX Software Engineering 72 (4.6%)
+ Konsulko Group 50 (3.2%)
+ ARM 39 (2.5%)
+ Amarula Solutions 20 (1.3%)
+ Samsung 19 (1.2%)
+ ST Microelectronics 18 (1.2%)
+ Toradex 17 (1.1%)
+ NXP 10 (0.6%)
+ Siemens 8 (0.5%)
+ Phytec 7 (0.4%)
+ Rockchip 7 (0.4%)
+ BayLibre SAS 6 (0.4%)
+ IBM 6 (0.4%)
+ Bosch 3 (0.2%)
+ Weidmüller Interface GmbH & Co. KG 3 (0.2%)
+ Bootlin 1 (0.1%)
+ Collabora Ltd. 1 (0.1%)
+ Intel 1 (0.1%)
+ LWN.net 1 (0.1%)
+ ==================================== =====
+
+
+.. table:: Top lines changed by employer
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ (Unknown) 43854 (37.2%)
+ Texas Instruments 12605 (10.7%)
+ Renesas Electronics 11595 (9.8%)
+ Google LLC 11497 (9.8%)
+ AMD 8291 (7.0%)
+ NXP 6236 (5.3%)
+ Linaro 5994 (5.1%)
+ ARM 4545 (3.9%)
+ Amarula Solutions 3655 (3.1%)
+ Konsulko Group 2320 (2.0%)
+ DENX Software Engineering 2239 (1.9%)
+ IBM 1481 (1.3%)
+ ST Microelectronics 1114 (0.9%)
+ Samsung 882 (0.7%)
+ Phytec 782 (0.7%)
+ Toradex 282 (0.2%)
+ Siemens 190 (0.2%)
+ Rockchip 171 (0.1%)
+ Weidmüller Interface GmbH & Co. KG 99 (0.1%)
+ BayLibre SAS 25 (0.0%)
+ Intel 20 (0.0%)
+ Bosch 6 (0.0%)
+ Collabora Ltd. 6 (0.0%)
+ LWN.net 4 (0.0%)
+ Bootlin 1 (0.0%)
+ ==================================== =====
+
+
+.. table:: Employers with the most signoffs (total 215)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ AMD 62 (28.8%)
+ Linaro 37 (17.2%)
+ (Unknown) 28 (13.0%)
+ Samsung 13 (6.0%)
+ ST Microelectronics 10 (4.7%)
+ Canonical 9 (4.2%)
+ Texas Instruments 7 (3.3%)
+ NXP 7 (3.3%)
+ ARM 7 (3.3%)
+ Amarula Solutions 7 (3.3%)
+ Pengutronix 5 (2.3%)
+ Google LLC 4 (1.9%)
+ DENX Software Engineering 4 (1.9%)
+ BayLibre SAS 4 (1.9%)
+ Konsulko Group 3 (1.4%)
+ Toradex 3 (1.4%)
+ Bootlin 2 (0.9%)
+ Renesas Electronics 1 (0.5%)
+ Rockchip 1 (0.5%)
+ Intel 1 (0.5%)
+ ==================================== =====
+
+
+.. table:: Employers with the most hackers (total 192)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ (Unknown) 104 (54.2%)
+ AMD 14 (7.3%)
+ Texas Instruments 12 (6.2%)
+ Linaro 10 (5.2%)
+ DENX Software Engineering 6 (3.1%)
+ NXP 5 (2.6%)
+ Toradex 5 (2.6%)
+ ST Microelectronics 4 (2.1%)
+ ARM 4 (2.1%)
+ Rockchip 4 (2.1%)
+ Renesas Electronics 3 (1.6%)
+ Samsung 2 (1.0%)
+ Amarula Solutions 2 (1.0%)
+ Google LLC 2 (1.0%)
+ BayLibre SAS 2 (1.0%)
+ Phytec 2 (1.0%)
+ Siemens 2 (1.0%)
+ Weidmüller Interface GmbH & Co. KG 2 (1.0%)
+ Konsulko Group 1 (0.5%)
+ Bootlin 1 (0.5%)
+ Intel 1 (0.5%)
+ IBM 1 (0.5%)
+ Bosch 1 (0.5%)
+ Collabora Ltd. 1 (0.5%)
+ LWN.net 1 (0.5%)
+ ==================================== =====
diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst
index a7a41f2..fb16ac7 100644
--- a/doc/develop/uefi/uefi.rst
+++ b/doc/develop/uefi/uefi.rst
@@ -318,6 +318,9 @@
--guid <image GUID> \
<capsule_file_name>
+Capsule with firmware version
+*****************************
+
The UEFI specification does not define the firmware versioning mechanism.
EDK II reference implementation inserts the FMP Payload Header right before
the payload. It coutains the fw_version and lowest supported version,
@@ -345,6 +348,60 @@
If the --fw-version option is not set, FMP Payload Header is not inserted
and fw_version is set as 0.
+Capsule Generation through binman
+*********************************
+
+Support has also been added to generate capsules during U-Boot build
+through binman. This requires the platform's DTB to be populated with
+the capsule entry nodes for binman. The capsules then can be generated
+by specifying the capsule parameters as properties in the capsule
+entry node.
+
+Check the test/py/tests/test_efi_capsule/capsule_gen_binman.dts file
+as reference for how a typical binman node for capsule generation
+looks like. For generating capsules as part of the platform's build, a
+capsule node would then have to be included into the platform's
+devicetree.
+
+A typical binman node for generating a capsule would look like::
+
+ capsule {
+ filename = "u-boot.capsule";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = "09d7cf52-0720-4710-91d1-08469b7fe9c8";
+
+ u-boot {
+ };
+ };
+ };
+
+In the above example, a capsule file named u-boot.capsule will be
+generated with u-boot.bin as it's input payload. The capsule
+generation parameters like image-index and image-guid are being
+specified as properties. Similarly, other properties like the private
+and public key certificate can be specified for generating signed
+capsules. Refer :ref:`etype_efi_capsule` for documentation about the
+efi-capsule binman entry type, which describes all the properties that
+can be specified.
+
+Dumping capsule headers
+***********************
+
+The mkeficapsule tool also provides a command-line option to dump the
+contents of the capsule header. This is a useful functionality when
+trying to understand the structure of a capsule and is also used in
+capsule verification. This feature is used in testing the capsule
+contents in binman's test framework.
+
+To check the contents of the capsule headers, the mkeficapsule command
+can be used.
+
+.. code-block:: console
+
+ $ mkeficapsule --dump-capsule \
+ <capsule_file_name>
+
Performing the update
*********************
@@ -522,20 +579,11 @@
...
}
-You can do step-4 manually with
-
-.. code-block:: console
-
- $ dtc -@ -I dts -O dtb -o signature.dtbo signature.dts
- $ fdtoverlay -i orig.dtb -o new.dtb -v signature.dtbo
-
-where signature.dts looks like::
-
- &{/} {
- signature {
- capsule-key = /incbin/("CRT.esl");
- };
- };
+You can perform step-4 through the Kconfig symbol
+CONFIG_EFI_CAPSULE_ESL_FILE. This symbol points to the esl file
+generated in step-2. Once the symbol has been populated with the path
+to the esl file, it will automatically get embedded into the
+platform's dtb as part of U-Boot build.
Anti-rollback Protection
************************
@@ -563,10 +611,10 @@
.. code-block:: console
- $ dtc -@ -I dts -O dtb -o version.dtbo version.dts
+ $ dtc -@ -I dts -O dtb -o version.dtbo version.dtso
$ fdtoverlay -i orig.dtb -o new.dtb -v version.dtbo
-where version.dts looks like::
+where version.dtso looks like::
/dts-v1/;
/plugin/;
diff --git a/doc/device-tree-bindings/clock/ti,cdce9xx.txt b/doc/device-tree-bindings/clock/ti,cdce9xx.txt
index 0d01f2d..62701d2 100644
--- a/doc/device-tree-bindings/clock/ti,cdce9xx.txt
+++ b/doc/device-tree-bindings/clock/ti,cdce9xx.txt
@@ -4,10 +4,10 @@
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] http://www.ti.com/product/cdce913
-[3] http://www.ti.com/product/cdce925
-[4] http://www.ti.com/product/cdce937
-[5] http://www.ti.com/product/cdce949
+[2] https://www.ti.com/product/cdce913
+[3] https://www.ti.com/product/cdce925
+[4] https://www.ti.com/product/cdce937
+[5] https://www.ti.com/product/cdce949
The driver provides clock sources for each output Y1 through Y5.
diff --git a/doc/device-tree-bindings/pmic/max77663.txt b/doc/device-tree-bindings/pmic/max77663.txt
new file mode 100644
index 0000000..ddb7d3e
--- /dev/null
+++ b/doc/device-tree-bindings/pmic/max77663.txt
@@ -0,0 +1,84 @@
+MAXIM, MAX77663 PMIC
+
+This device uses two drivers:
+- drivers/power/pmic/max77663.c (for parent device)
+- drivers/power/regulator/max77663_regulator.c (for child regulators)
+
+This chapter describes the binding info for the PMIC driver and regulators.
+
+Required properties for PMIC:
+- compatible: "maxim,max77663"
+- reg: usually 0x1c or 0x3c
+
+With those two properties, the pmic device can be used for read/write only.
+To bind each regulator, the optional regulators subnode should exists.
+
+Optional subnode:
+- name: regulators (subnode list of each device's regulator)
+
+Regulators subnode contains set on supported regulators.
+
+Required properties:
+- regulator-name: used for regulator uclass platform data '.name',
+
+List of supported regulator nodes names for max77663:
+- sd0, sd1, sd2, sd3, ldo0, ldo1, ldo2, ldo3, ldo4, ldo5, ldo6, ldo7, ldo8
+
+Optional:
+- regulator-min-microvolt: minimum allowed Voltage to set
+- regulator-max-microvolt: minimum allowed Voltage to set
+- regulator-always-on: regulator should be never disabled
+- regulator-boot-on: regulator should be enabled by the bootloader
+
+Linux driver binding for this driver is compatible.
+
+Example:
+
+max77663@1c {
+ compatible = "maxim,max77663";
+ reg = <0x1c>;
+
+ regulators {
+ sd0 {
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ...
+
+ ldo0 {
+ regulator-name = "avdd_pll";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ...
+
+ ldo2 {
+ regulator-name = "avdd_usb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo3 {
+ regulator-name = "vdd_sdmmc3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ...
+
+ ldo8 {
+ regulator-name = "avdd_dsi_csi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ };
+};
diff --git a/doc/device-tree-bindings/pmic/tps65911.txt b/doc/device-tree-bindings/pmic/tps65911.txt
new file mode 100644
index 0000000..29270ef
--- /dev/null
+++ b/doc/device-tree-bindings/pmic/tps65911.txt
@@ -0,0 +1,78 @@
+Texas Instruments, TPS65911 PMIC
+
+This device uses two drivers:
+- drivers/power/pmic/tps65910.c (for parent device)
+- drivers/power/regulator/tps65911_regulator.c (for child regulators)
+
+This chapter describes the binding info for the PMIC driver and regulators.
+
+Required properties for PMIC:
+- compatible: "ti,tps65911"
+- reg: 0x2d
+
+With those two properties, the pmic device can be used for read/write only.
+To bind each regulator, the optional regulators subnode should exists.
+
+Optional subnode:
+- name: regulators (subnode list of each device's regulator)
+
+Regulators subnode contains set on supported regulators.
+
+Required properties:
+- regulator-name: used for regulator uclass platform data '.name',
+
+List of supported regulator nodes names for tps65911:
+- vdd1, vdd2, vddctrl, vddio
+- ldo1, ldo2, ldo3, ldo4, ldo5, ldo6, ldo7, ldo8
+
+vddio in datasheet is referred as vio, but for reduction of code and
+unification of smps regulators it is named vddio.
+
+Optional:
+- regulator-min-microvolt: minimum allowed Voltage to set
+- regulator-max-microvolt: minimum allowed Voltage to set
+- regulator-always-on: regulator should be never disabled
+- regulator-boot-on: regulator should be enabled by the bootloader
+
+Example:
+
+tps65911@2d {
+ compatible = "ti,tps65911";
+ reg = <0x2d>;
+
+ regulators {
+ vdd1 {
+ regulator-name = "vdd_1v2_backlight";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ...
+
+ vddio {
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo1 {
+ regulator-name = "vdd_emmc_core";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ...
+
+ ldo8 {
+ regulator-name = "vdd_ddr_hs";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+ };
+};
diff --git a/doc/device-tree-bindings/pmic/tps80031.txt b/doc/device-tree-bindings/pmic/tps80031.txt
new file mode 100644
index 0000000..577e6de
--- /dev/null
+++ b/doc/device-tree-bindings/pmic/tps80031.txt
@@ -0,0 +1,76 @@
+Texas Instruments, TPS80031/TPS80032 PMIC
+
+This device uses two drivers:
+- drivers/power/pmic/tps80031.c (for parent device)
+- drivers/power/regulator/tps80031_regulator.c (for child regulators)
+
+This chapter describes the binding info for the PMIC driver and regulators.
+
+Required properties for PMIC:
+- compatible: "ti,tps80031" or "ti,tps80032"
+- reg: 0x48
+
+With those two properties, the pmic device can be used for read/write only.
+To bind each regulator, the optional regulators subnode should exists.
+
+Optional subnode:
+- name: regulators (subnode list of each device's regulator)
+
+Regulators subnode contains set on supported regulators.
+
+Required properties:
+- regulator-name: used for regulator uclass platform data '.name',
+
+List of supported regulator nodes names for tps80031/tps80032:
+- smps1, smps2, smps3, smps4, smps5
+- ldo1, ldo2, ldo3, ldo4, ldo5, ldo6, ldo7, ldoln, ldousb
+
+SMPS5 in Linux 3.1.10 is referred as vio, but datasheet clearly names it SMPS5.
+
+Optional:
+- regulator-min-microvolt: minimum allowed Voltage to set
+- regulator-max-microvolt: minimum allowed Voltage to set
+- regulator-always-on: regulator should be never disabled
+- regulator-boot-on: regulator should be enabled by the bootloader
+
+Example:
+
+tps80032@48 {
+ compatible = "ti,tps80032";
+ reg = <0x48>;
+
+ regulators {
+ smps1 {
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ...
+
+ smps5 {
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo1 {
+ regulator-name = "avdd_dsi_csi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
+ };
+
+ ...
+
+ ldousb {
+ regulator-name = "avdd_usb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+};
diff --git a/doc/device-tree-bindings/video/tilcdc/tilcdc.txt b/doc/device-tree-bindings/video/tilcdc/tilcdc.txt
index 7bf1bb4..7600801 100644
--- a/doc/device-tree-bindings/video/tilcdc/tilcdc.txt
+++ b/doc/device-tree-bindings/video/tilcdc/tilcdc.txt
@@ -46,7 +46,7 @@
crossed and LCD_DATA[0:4] is for Red[3:7] and LCD_DATA[11:15] is
for Blue[3-7]. For more details see section 3.1.1 in AM335x
Silicon Errata:
- http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360
+ https://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360
Example:
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf.sh b/doc/imx/habv4/csf_examples/mx8m/csf.sh
index 65c1430..cd3b261 100644
--- a/doc/imx/habv4/csf_examples/mx8m/csf.sh
+++ b/doc/imx/habv4/csf_examples/mx8m/csf.sh
@@ -75,5 +75,18 @@
# Generate CSF blob
cst -i csf_fit.tmp -o csf_fit.bin
+
+# When loading flash.bin via USB, we must ensure that the file being
+# served is as large as the target expects (see
+# board_spl_fit_size_align()), otherwise the target will hang in
+# rom_api_download_image() waiting for the remaining bytes.
+#
+# Note that in order for dd to actually extend the file, one must not
+# pass conv=notrunc here. With a non-zero seek= argument, dd is
+# documented to preserve the contents of the file seeked past; in
+# particular, dd does not open the file with O_TRUNC.
+CSF_SIZE=$(sed -n "/CONFIG_CSF_SIZE=/ s@.*=@@p" .config)
+dd if=/dev/null of=csf_fit.bin bs=1 seek=$((CSF_SIZE - 0x20)) count=0
+
# Patch CSF blob into flash.bin
dd if=csf_fit.bin of=flash.bin bs=1 seek=${csf_block_offset} conv=notrunc
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt
index 3d79edf..97f3eea 100644
--- a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt
+++ b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt
@@ -27,4 +27,4 @@
Verification index = 2
# FIXME:
# Line 1 -- fitImage
- Blocks = 0x401fcdc0 0x57c00 0xffff "flash.bin"
+ Blocks = CONFIG_SPL_LOAD_FIT_ADDRESS 0x57c00 0xffff "flash.bin"
diff --git a/doc/imx/mkimage/imximage.txt b/doc/imx/mkimage/imximage.txt
index f2cf23c..fa4e486 100644
--- a/doc/imx/mkimage/imximage.txt
+++ b/doc/imx/mkimage/imximage.txt
@@ -213,7 +213,7 @@
Device Boot Start End Blocks Id System
/dev/mmcblk0p1 3 16 112455 83 Linux
-I have set 100MB, leaving the first 2 sectors free. I will copy u-boot
+I have set 100MB, leaving the first 2 sectors free. I will copy U-Boot
there.
8. Write the partition table and exit.
diff --git a/doc/learn/talks.rst b/doc/learn/talks.rst
index 0bb44ae..d65e3b9 100644
--- a/doc/learn/talks.rst
+++ b/doc/learn/talks.rst
@@ -15,6 +15,9 @@
<https://www.youtube.com/watch?v=YlJBsVZJkDI>`__
from Embedded Linux Conference 2023.
+* `Introduction to U-Boot for beginners
+ <https://www.youtube.com/watch?v=rVaiLgXccSE>`__
+
See elinux_talks_ for a more comprehensive list.
.. _elinux_talks: https://elinux.org/Boot_Loaders#U-Boot
diff --git a/doc/mkimage.1 b/doc/mkimage.1
index 76c7859..d0a038a 100644
--- a/doc/mkimage.1
+++ b/doc/mkimage.1
@@ -860,6 +860,25 @@
\-K u\-boot.dtb -r kernel.itb
.EE
.RE
+.P
+Convert an existing FIT image from any of the three types of data storage
+(internal, external data-offset or external data-position) to another type
+of data storage.
+.RS
+.P
+.EX
+\fB// convert FIT from internal data to data-position
+\fBmkimage -p 0x20000 -F internal_data.itb
+.EE
+.EX
+\fB// convert FIT from data-position to data-offset
+\fBmkimage -E -F external_data-position.itb
+.EE
+.EX
+\fB// convert FIT from data-offset to internal data
+\fBmkimage -F external_data-offset.itb
+.EE
+.RE
.
.SH SEE ALSO
.BR dtc (1),
diff --git a/doc/sphinx/load_config.py b/doc/sphinx/load_config.py
index eeb394b..8b416bf 100644
--- a/doc/sphinx/load_config.py
+++ b/doc/sphinx/load_config.py
@@ -3,7 +3,7 @@
import os
import sys
-from sphinx.util.pycompat import execfile_
+from sphinx.util.osutil import fs_encoding
# ------------------------------------------------------------------------------
def loadConfig(namespace):
@@ -48,7 +48,9 @@
sys.stdout.write("load additional sphinx-config: %s\n" % config_file)
config = namespace.copy()
config['__file__'] = config_file
- execfile_(config_file, config)
+ with open(config_file, 'rb') as f:
+ code = compile(f.read(), fs_encoding, 'exec')
+ exec(code, config)
del config['__file__']
namespace.update(config)
else:
diff --git a/doc/sphinx/requirements.txt b/doc/sphinx/requirements.txt
index 6ccbe52..39ececb 100644
--- a/doc/sphinx/requirements.txt
+++ b/doc/sphinx/requirements.txt
@@ -23,4 +23,4 @@
sphinxcontrib-jsmath==1.0.1
sphinxcontrib-qthelp==1.0.3
sphinxcontrib-serializinghtml==1.1.5
-urllib3==1.26.9
+urllib3==2.0.7
diff --git a/doc/usage/cmd/askenv.rst b/doc/usage/cmd/askenv.rst
index 347bd59..b85cefa 100644
--- a/doc/usage/cmd/askenv.rst
+++ b/doc/usage/cmd/askenv.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+:
askenv command
-===============
+==============
Synopsis
--------
diff --git a/doc/usage/cmd/bdinfo.rst b/doc/usage/cmd/bdinfo.rst
index b287d0f..5261085 100644
--- a/doc/usage/cmd/bdinfo.rst
+++ b/doc/usage/cmd/bdinfo.rst
@@ -106,7 +106,7 @@
Early malloc usage
amount of memory used in the early malloc memory and its maximum size
- as defined by CONFIGSYS_MALLOC_F_LEN
+ as defined by CONFIG_SYS_MALLOC_F_LEN
Configuration
-------------
diff --git a/doc/usage/cmd/bootdev.rst b/doc/usage/cmd/bootdev.rst
index 6c68d0b..fb638b5 100644
--- a/doc/usage/cmd/bootdev.rst
+++ b/doc/usage/cmd/bootdev.rst
@@ -76,7 +76,7 @@
bootdev select
-~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~
Use this to select a particular bootdev. You can select it by the sequence
number or name, as shown in `bootdev list`.
@@ -89,7 +89,7 @@
bootdev info
-~~~~~~~~~~~~~~~
+~~~~~~~~~~~~
This shows information on the current bootdev, with the format looking like
this:
diff --git a/doc/usage/cmd/bootflow.rst b/doc/usage/cmd/bootflow.rst
index 65e3777..2198ff6 100644
--- a/doc/usage/cmd/bootflow.rst
+++ b/doc/usage/cmd/bootflow.rst
@@ -11,9 +11,11 @@
bootflow scan [-abelGH] [bootdev]
bootflow list [-e]
bootflow select [<num|name>]
- bootflow info [-d]
+ bootflow info [-ds]
+ bootflow read
bootflow boot
bootflow cmdline [set|get|clear|delete|auto] <param> [<value>]
+ bootfloe menu [-t]
Description
-----------
@@ -23,6 +25,9 @@
See :doc:`../../develop/bootstd` for more information.
+Note that `CONFIG_BOOTSTD_FULL` (which enables `CONFIG_CMD_BOOTFLOW_FULL) must
+be enabled to obtain full functionality with this command. Otherwise, it only
+supports `bootflow scan` which scans and boots the first available bootflow.
bootflow scan
~~~~~~~~~~~~~
@@ -191,11 +196,29 @@
Use the `-d` flag to dump out the contents of the bootfile file.
+The `-s` flag shows any x86 setup block, instead of the above.
+
+
+bootflow read
+~~~~~~~~~~~~~
+
+This reads any files related to the bootflow. Some bootflows with large files
+avoid doing this when the bootflow is scanned, since it uses a lot of memory
+and takes extra time. The files are then automatically read when `bootflow boot`
+is used.
+
+This command reads these files immediately. Typically this fills in the bootflow
+`buf` property, which can be used to examine the bootflow.
+
+Note that reading the files does not result in any extra parsing, nor loading of
+images in the files. This is purely used to read in the data ready for
+booting, or examination.
+
bootflow boot
~~~~~~~~~~~~~
-This boots the current bootflow.
+This boots the current bootflow, reading any required files first.
bootflow cmdline
@@ -228,6 +251,16 @@
output appears on the serial port. This is only supported by the 16550 serial
driver so far.
+bootflow menu
+~~~~~~~~~~~~~
+
+This shows a menu with available bootflows. The user can select a particular
+bootflow, which then becomes the current one.
+
+The `-t` flag requests a text menu. Otherwise, if a display is available, a
+graphical menu is shown.
+
+
Example
-------
@@ -522,6 +555,172 @@
[ 0.000000] Command line: loglevel=7 ... usb-storage.quirks=13fe:6500:u earlycon=uart8250,mmio32,0xfe03e000,115200n8
[ 0.000000] x86/split lock detection: warning about user-space split_locks
+This shows looking at x86 setup information::
+
+ => bootfl sel 0
+ => bootfl i -s
+ Setup located at 77b56010:
+
+ ACPI RSDP addr : 0
+ E820: 2 entries
+ Addr Size Type
+ 0 1000 RAM
+ fffff000 1000 Reserved
+ Setup sectors : 1e
+ Root flags : 1
+ Sys size : 63420
+ RAM size : 0
+ Video mode : ffff
+ Root dev : 0
+ Boot flag : 0
+ Jump : 66eb
+ Header : 53726448
+ Kernel V2
+ Version : 20d
+ Real mode switch : 0
+ Start sys seg : 1000
+ Kernel version : 38cc
+ @00003acc:
+ Type of loader : ff
+ unknown
+ Load flags : 1
+ : loaded-high
+ Setup move size : 8000
+ Code32 start : 100000
+ Ramdisk image : 0
+ Ramdisk size : 0
+ Bootsect kludge : 0
+ Heap end ptr : 5160
+ Ext loader ver : 0
+ Ext loader type : 0
+ Command line ptr : 735000
+ Initrd addr max : 7fffffff
+ Kernel alignment : 200000
+ Relocatable kernel : 1
+ Min alignment : 15
+ : 200000
+ Xload flags : 3
+ : 64-bit-entry can-load-above-4gb
+ Cmdline size : 7ff
+ Hardware subarch : 0
+ HW subarch data : 0
+ Payload offset : 26e
+ Payload length : 612045
+ Setup data : 0
+ Pref address : 1000000
+ Init size : 1383000
+ Handover offset : 0
+
+This shows reading a bootflow to examine the kernel::
+
+ => bootfl i 0
+ Name:
+ Device: emmc@1c,0.bootdev
+ Block dev: emmc@1c,0.blk
+ Method: cros
+ State: ready
+ Partition: 2
+ Subdir: (none)
+ Filename: <NULL>
+ Buffer: 0
+ Size: 63ee00 (6548992 bytes)
+ OS: ChromeOS
+ Cmdline: console= loglevel=7 init=/sbin/init cros_secure oops=panic panic=-1 root=PARTUUID=35c775e7-3735-d745-93e5-d9e0238f7ed0/PARTNROFF=1 rootwait rw dm_verity.error_behavior=3 dm_verity.max_bios=-1 dm_verity.dev_wait=0 dm="1 vroot none rw 1,0 3788800 verity payload=ROOT_DEV hashtree=HASH_DEV hashstart=3788800 alg=sha1 root_hexdigest=55052b629d3ac889f25a9583ea12cdcd3ea15ff8 salt=a2d4d9e574069f4fed5e3961b99054b7a4905414b60a25d89974a7334021165c" noinitrd vt.global_cursor_default=0 kern_guid=35c775e7-3735-d745-93e5-d9e0238f7ed0 add_efi_memmap boot=local noresume noswap i915.modeset=1 tpm_tis.force=1 tpm_tis.interrupts=0 nmi_watchdog=panic,lapic disablevmx=off
+ X86 setup: 77b56010
+ Logo: (none)
+ FDT: <NULL>
+ Error: 0
+
+Note that `Buffer` is 0 so it has not be read yet. Using `bootflow read`::
+
+ => bootfl read
+ => bootfl info
+ Name:
+ Device: emmc@1c,0.bootdev
+ Block dev: emmc@1c,0.blk
+ Method: cros
+ State: ready
+ Partition: 2
+ Subdir: (none)
+ Filename: <NULL>
+ Buffer: 77b7e400
+ Size: 63ee00 (6548992 bytes)
+ OS: ChromeOS
+ Cmdline: console= loglevel=7 init=/sbin/init cros_secure oops=panic panic=-1 root=PARTUUID=35c775e7-3735-d745-93e5-d9e0238f7ed0/PARTNROFF=1 rootwait rw dm_verity.error_behavior=3 dm_verity.max_bios=-1 dm_verity.dev_wait=0 dm="1 vroot none rw 1,0 3788800 verity payload=ROOT_DEV hashtree=HASH_DEV hashstart=3788800 alg=sha1 root_hexdigest=55052b629d3ac889f25a9583ea12cdcd3ea15ff8 salt=a2d4d9e574069f4fed5e3961b99054b7a4905414b60a25d89974a7334021165c" noinitrd vt.global_cursor_default=0 kern_guid=35c775e7-3735-d745-93e5-d9e0238f7ed0 add_efi_memmap boot=local noresume noswap i915.modeset=1 tpm_tis.force=1 tpm_tis.interrupts=0 nmi_watchdog=panic,lapic disablevmx=off
+ X86 setup: 781b4400
+ Logo: (none)
+ FDT: <NULL>
+ Error: 0
+
+Now the buffer can be accessed::
+
+ => md 77b7e400
+ 77b7e400: 1186f6fc 40000002 b8fa0c75 00000018 .......@u.......
+ 77b7e410: c08ed88e a68dd08e 000001e8 000000e8 ................
+ 77b7e420: ed815d00 00000021 62c280b8 89e80100 .]..!......b....
+ 77b7e430: 22f7e8c4 c0850061 22ec850f eb890061 ..."a......"a...
+ 77b7e440: 0230868b 01480000 21d0f7c3 00fb81c3 ..0...H....!....
+ 77b7e450: 7d010000 0000bb05 c3810100 00d4f000 ...}............
+ 77b7e460: 8130858d 85890061 00618132 3095010f ..0.a...2.a....0
+ 77b7e470: 0f006181 c883e020 e0220f20 e000bb8d .a.. ... .".....
+ 77b7e480: c0310062 001800b9 8dabf300 62e000bb b.1............b
+ 77b7e490: 07878d00 89000010 00bb8d07 8d0062f0 .............b..
+ 77b7e4a0: 00100787 0004b900 07890000 00100005 ................
+ 77b7e4b0: 08c78300 8df37549 630000bb 0183b800 ....Iu.....c....
+ 77b7e4c0: 00b90000 89000008 00000507 c7830020 ............ ...
+ 77b7e4d0: f3754908 e000838d 220f0062 0080b9d8 .Iu.....b.."....
+ 77b7e4e0: 320fc000 08e8ba0f c031300f b8d0000f ...2.....01.....
+ 77b7e4f0: 00000020 6ad8000f 00858d10 50000002 ......j.......P
+
+This shows using a text menu to boot an OS::
+
+ => bootflow scan
+ => bootfl list
+ => bootfl menu -t
+ U-Boot : Boot Menu
+
+ UP and DOWN to choose, ENTER to select
+
+ > 0 mmc1 mmc1.bootdev.whole
+ 1 mmc1 Fedora-Workstation-armhfp-31-1.9 (5.3.7-301.fc31.armv7hl)
+ 2 mmc1 mmc1.bootdev.part_1
+ 3 mmc4 mmc4.bootdev.whole
+ 4 mmc4 Armbian
+ 5 mmc4 mmc4.bootdev.part_1
+ 6 mmc5 mmc5.bootdev.whole
+ 7 mmc5 ChromeOS
+ 8 mmc5 ChromeOS
+ U-Boot : Boot Menu
+
+ UP and DOWN to choose, ENTER to select
+
+ 0 mmc1 mmc1.bootdev.whole
+ > 1 mmc1 Fedora-Workstation-armhfp-31-1.9 (5.3.7-301.fc31.armv7hl)
+ 2 mmc1 mmc1.bootdev.part_1
+ 3 mmc4 mmc4.bootdev.whole
+ 4 mmc4 Armbian
+ 5 mmc4 mmc4.bootdev.part_1
+ 6 mmc5 mmc5.bootdev.whole
+ 7 mmc5 ChromeOS
+ 8 mmc5 ChromeOS
+ U-Boot : Boot Menu
+
+ Selected: Fedora-Workstation-armhfp-31-1.9 (5.3.7-301.fc31.armv7hl)
+ => bootfl boot
+ ** Booting bootflow 'mmc1.bootdev.part_1' with extlinux
+ Ignoring unknown command: ui
+ Ignoring malformed menu command: autoboot
+ Ignoring malformed menu command: hidden
+ Ignoring unknown command: totaltimeout
+ Fedora-Workstation-armhfp-31-1.9 Boot Options.
+ 1: Fedora-Workstation-armhfp-31-1.9 (5.3.7-301.fc31.armv7hl)
+ Enter choice: 1
+ 1: Fedora-Workstation-armhfp-31-1.9 (5.3.7-301.fc31.armv7hl)
+ Retrieving file: /vmlinuz-5.3.7-301.fc31.armv7hl
+ Retrieving file: /initramfs-5.3.7-301.fc31.armv7hl.img
+ append: ro root=UUID=9732b35b-4cd5-458b-9b91-80f7047e0b8a rhgb quiet LANG=en_US.UTF-8 cma=192MB cma=256MB
+ Retrieving file: /dtb-5.3.7-301.fc31.armv7hl/sandbox.dtb
+ ...
Return value
@@ -532,6 +731,9 @@
return value $? is 1. If the boot succeeds but for some reason the Operating
System returns, then $? is 0, indicating success.
+For `bootflow menu` the return value is $? is 0 (true) if an option was choses,
+else 1.
+
For other subcommands, the return value $? is always 0 (true).
diff --git a/doc/usage/cmd/cat.rst b/doc/usage/cmd/cat.rst
index 5ef4731..5aaf497 100644
--- a/doc/usage/cmd/cat.rst
+++ b/doc/usage/cmd/cat.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+:
cat command
-===============
+===========
Synopsis
--------
diff --git a/doc/usage/cmd/cedit.rst b/doc/usage/cmd/cedit.rst
index 8e1110c..f415b48 100644
--- a/doc/usage/cmd/cedit.rst
+++ b/doc/usage/cmd/cedit.rst
@@ -10,6 +10,11 @@
cedit load <interface> <dev[:part]> <filename>
cedit run
+ cedit write_fdt <dev[:part]> <filename>
+ cedit read_fdt <dev[:part]> <filename>
+ cedit write_env [-v]
+ cedit read_env [-v]
+ cedit write_cmos [-v] [dev]
Description
-----------
@@ -22,6 +27,69 @@
The description is in the form of a devicetree file, as documented at
:ref:`expo_format`.
+See :doc:`../../develop/cedit` for information about the configuration editor.
+
+cedit load
+~~~~~~~~~~
+
+Loads a configuration-editor description from a file. It creates a new cedit
+structure ready for use. Initially no settings are read, so default values are
+used for each object.
+
+cedit run
+~~~~~~~~~
+
+Runs the default configuration-editor event loop. This is very simple, just
+accepting character input and moving through the objects under user control.
+The implementation is at `cedit_run()`.
+
+cedit write_fdt
+~~~~~~~~~~~~~~~
+
+Writes the current user settings to a devicetree file. For each menu item the
+selected ID and its text string are written.
+
+cedit read_fdt
+~~~~~~~~~~~~~~
+
+Reads the user settings from a devicetree file and updates the cedit with those
+settings.
+
+cedit read_env
+~~~~~~~~~~~~~~
+
+Reads the settings from the environment variables. For each menu item `<name>`,
+cedit looks for a variable called `c.<name>` with the ID of the selected menu
+item.
+
+The `-v` flag enables verbose mode, where each variable is printed after it is
+read.
+
+cedit write_env
+~~~~~~~~~~~~~~~
+
+Writes the settings to environment variables. For each menu item the selected
+ID and its text string are written, similar to:
+
+ setenv c.<name> <selected_id>
+ setenv c.<name>-str <selected_id's text string>
+
+The `-v` flag enables verbose mode, where each variable is printed before it is
+set.
+
+cedit write_cmos
+~~~~~~~~~~~~~~~~
+
+Writes the settings to locations in the CMOS RAM. The locations used are
+specified by the schema. See `expo_format_`.
+
+The `-v` flag enables verbose mode, which shows which CMOS locations were
+updated.
+
+Normally the first RTC device is used to hold the data. You can specify a
+different device by name using the `dev` parameter.
+
+
Example
-------
@@ -29,3 +97,52 @@
=> cedit load hostfs - fred.dtb
=> cedit run
+ => cedit write_fdt hostfs - settings.dtb
+
+That results in::
+
+ / {
+ cedit-values {
+ cpu-speed = <0x00000006>;
+ cpu-speed-str = "2 GHz";
+ power-loss = <0x0000000a>;
+ power-loss-str = "Always Off";
+ };
+ }
+
+ => cedit read_fdt hostfs - settings.dtb
+
+This shows settings being stored in the environment::
+
+ => cedit write_env -v
+ c.cpu-speed=7
+ c.cpu-speed-str=2.5 GHz
+ c.power-loss=12
+ c.power-loss-str=Memory
+ => print
+ ...
+ c.cpu-speed=6
+ c.cpu-speed-str=2 GHz
+ c.power-loss=10
+ c.power-loss-str=Always Off
+ ...
+
+ => cedit read_env -v
+ c.cpu-speed=7
+ c.power-loss=12
+
+This shows writing to CMOS RAM. Notice that the bytes at 80 and 84 change::
+
+ => rtc read 80 8
+ 00000080: 00 00 00 00 00 2f 2a 08 ...../*.
+ => cedit write_cmos -v
+ Write 2 bytes from offset 80 to 84
+ => rtc read 80 8
+ 00000080: 01 00 00 00 08 2f 2a 08 ...../*.
+ => cedit read_cmos -v
+ Read 2 bytes from offset 80 to 84
+
+Here is an example with the device specified::
+
+ => cedit write_cmos rtc@43
+ =>
diff --git a/doc/usage/cmd/coninfo.rst b/doc/usage/cmd/coninfo.rst
index f913148..76cb6c3 100644
--- a/doc/usage/cmd/coninfo.rst
+++ b/doc/usage/cmd/coninfo.rst
@@ -21,7 +21,7 @@
list of device names.
Example
---------
+-------
.. code-block:: console
diff --git a/doc/usage/cmd/dm.rst b/doc/usage/cmd/dm.rst
index 74c6b01..12b7ede 100644
--- a/doc/usage/cmd/dm.rst
+++ b/doc/usage/cmd/dm.rst
@@ -12,8 +12,8 @@
dm devres
dm drivers
dm static
- dm tree [-s]
- dm uclass
+ dm tree [-s][-e] [uclass name]
+ dm uclass [-e] [udevice name]
Description
-----------
@@ -127,6 +127,12 @@
device) are shown sorted in order of uclass ID, so it is easier to find a
particular device type.
+If -e is given, forward-matching against existing devices is
+made and only the matched devices are shown.
+
+If a device name is given, forward-matching against existing devices is
+made and only the matched devices are shown.
+
dm uclass
~~~~~~~~~
@@ -140,6 +146,11 @@
where `n` is the index within the uclass, `a` is the address of the device in
memory and `s` is the sequence number of the device.
+If -e is given, forward-matching against existing uclasses is
+made and only the matched uclasses are shown.
+
+If no uclass name is given, all the uclasses are shown.
+
Examples
--------
@@ -409,6 +420,15 @@
nop 8 [ ] scmi_voltage_domain `-- regulators
regulator 5 [ ] scmi_regulator |-- reg@0
regulator 6 [ ] scmi_regulator `-- reg@1
+ => dm tree pinc
+ pinctrl 0 [ + ] sandbox_pinctrl_gpio pinctrl-gpio
+ gpio 1 [ + ] sandbox_gpio |-- base-gpios
+ nop 0 [ + ] gpio_hog | |-- hog_input_active_low
+ nop 1 [ + ] gpio_hog | |-- hog_input_active_high
+ nop 2 [ + ] gpio_hog | |-- hog_output_low
+ nop 3 [ + ] gpio_hog | `-- hog_output_high
+ gpio 2 [ ] sandbox_gpio |-- extra-gpios
+ gpio 3 [ ] sandbox_gpio `-- pinmux-gpios
=>
@@ -487,4 +507,10 @@
0 * gpio-wdt @ 0301c070, seq 0
1 * wdt@0 @ 03021710, seq 1
+ => dm uclass blk
+ uclass 22: blk
+ 0 mmc2.blk @ 0301ca00, seq 0
+ 1 mmc1.blk @ 0301cee0, seq 1
+ 2 mmc0.blk @ 0301d380, seq 2
+
=>
diff --git a/doc/usage/cmd/gpt.rst b/doc/usage/cmd/gpt.rst
index 6387c81..cbbe44a 100644
--- a/doc/usage/cmd/gpt.rst
+++ b/doc/usage/cmd/gpt.rst
@@ -13,8 +13,10 @@
gpt read <interface> <dev> [<varname>]
gpt rename <interface> <dev> <part> <name>
gpt repair <interface> <dev>
+ gpt set-bootable <interface> <dev> <partition list>
gpt setenv <interface> <dev> <partition name>
gpt swap <interface> <dev> <name1> <name2>
+ gpt transpose <interface> <dev> <part1> <part2>
gpt verify <interface> <dev> [<partition string>]
gpt write <interface> <dev> <partition string>
@@ -90,6 +92,13 @@
Repairs the GPT partition tables if it they become corrupted.
+gpt set-bootable
+~~~~~~~~~~~~~~~~
+
+Sets the bootable flag for all partitions in the table. If the partition name
+is in 'partition list' (separated by ','), the bootable flag is set, otherwise
+it is cleared. CONFIG_CMD_GPT_RENAME=y is required.
+
gpt setenv
~~~~~~~~~~
@@ -108,6 +117,9 @@
gpt_partition_entry
the partition number in the table, e.g. 1, 2, 3, etc.
+gpt_partition_bootable
+ 1 if the partition is marked as bootable, 0 if not
+
gpt swap
~~~~~~~~
@@ -115,6 +127,13 @@
all partitions named 'name2' to be 'name1'. CONFIG_CMD_GPT_RENAME=y is
required.
+gpt transpose
+~~~~~~~~~~~~~
+
+Swaps the order of two partition table entries with indexes 'part1' and 'part2'
+in the partition table, but otherwise leaves the actual partition data
+untouched.
+
gpt verify
~~~~~~~~~~
@@ -137,6 +156,7 @@
Examples
~~~~~~~~
+
Create 6 partitions on a disk::
=> setenv gpt_parts 'uuid_disk=bec9fc2a-86c1-483d-8a0e-0109732277d7;
@@ -167,14 +187,15 @@
rootfs
=> echo ${gpt_partition_entry}
2
+ => echo ${gpt_partition_bootable}
+ 0
Get the list of partition names on the disk::
=> gpt enumerate
- => echo gpt_partition_list
+ => echo ${gpt_partition_list}
boot rootfs system-data [ext] user modules ramdisk
-
Get the GUID for a disk::
=> gpt guid mmc 0
@@ -182,3 +203,25 @@
=> gpt guid mmc gpt_disk_uuid
=> echo ${gpt_disk_uuid}
bec9fc2a-86c1-483d-8a0e-0109732277d7
+
+Set the bootable flag for the 'boot' partition and clear it for all others::
+
+ => gpt set-bootable mmc 0 boot
+
+Swap the order of the 'boot' and 'rootfs' partition table entries::
+
+ => gpt setenv mmc 0 rootfs
+ => echo ${gpt_partition_entry}
+ 2
+ => gpt setenv mmc 0 boot
+ => echo ${gpt_partition_entry}
+ 1
+
+ => gpt transpose mmc 0 1 2
+
+ => gpt setenv mmc 0 rootfs
+ => echo ${gpt_partition_entry}
+ 1
+ => gpt setenv mmc 0 boot
+ => echo ${gpt_partition_entry}
+ 2
diff --git a/doc/usage/cmd/history.rst b/doc/usage/cmd/history.rst
new file mode 100644
index 0000000..33d3fcd
--- /dev/null
+++ b/doc/usage/cmd/history.rst
@@ -0,0 +1,67 @@
+.. SPDX-License-Identifier: GPL-2.0+:
+
+history command
+===============
+
+Synopis
+-------
+
+::
+
+ history
+
+Description
+-----------
+
+The *history* command shows a list of previously entered commands on the
+command line. When U-Boot starts, this it is initially empty. Each new command
+entered is added to the list.
+
+Normally these commands can be accessed by pressing the `up arrow` and
+`down arrow` keys, which cycle through the list. The `history` command provides
+a simple way to view the list.
+
+Example
+-------
+
+This example shows entering three commands, then `history`. Note that `history`
+itself is added to the list.
+
+::
+
+ => bootflow scan -l
+ Scanning for bootflows in all bootdevs
+ Seq Method State Uclass Part Name Filename
+ --- ----------- ------ -------- ---- ------------------------ ----------------
+ Scanning global bootmeth 'firmware0':
+ Hunting with: simple_bus
+ Found 2 extension board(s).
+ Scanning bootdev 'mmc2.bootdev':
+ Scanning bootdev 'mmc1.bootdev':
+ 0 extlinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf
+ No more bootdevs
+ --- ----------- ------ -------- ---- ------------------------ ----------------
+ (1 bootflow, 1 valid)
+ => bootflow select 0
+ => bootflow info
+ Name: mmc1.bootdev.part_1
+ Device: mmc1.bootdev
+ Block dev: mmc1.blk
+ Method: extlinux
+ State: ready
+ Partition: 1
+ Subdir: (none)
+ Filename: /extlinux/extlinux.conf
+ Buffer: aebdea0
+ Size: 253 (595 bytes)
+ OS: Fedora-Workstation-armhfp-31-1.9 (5.3.7-301.fc31.armv7hl)
+ Cmdline: (none)
+ Logo: (none)
+ FDT: <NULL>
+ Error: 0
+ => history
+ bootflow scan -l
+ bootflow select 0
+ bootflow info
+ history
+ =>
diff --git a/doc/usage/cmd/mmc.rst b/doc/usage/cmd/mmc.rst
index 71a0303..8394f64 100644
--- a/doc/usage/cmd/mmc.rst
+++ b/doc/usage/cmd/mmc.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+:
mmc command
-============
+===========
Synopsis
--------
@@ -21,6 +21,7 @@
mmc bootpart-resize <dev> <dev part size MB> <RPMB part size MB>
mmc partconf <dev> [[varname] | [<boot_ack> <boot_partition> <partition_access>]]
mmc rst-function <dev> <value>
+ mmc reg read <reg> <offset> [env]
Description
-----------
@@ -183,6 +184,31 @@
0x3
Reserved
+The 'mmc reg read <reg> <offset> [env]' reads eMMC card register and
+either print it to standard output, or store the value in environment
+variable.
+
+<reg> with
+optional offset <offset> into the register array, and print it to
+standard output or store it into environment variable [env].
+
+ reg
+ cid
+ The Device IDentification (CID) register. Uses offset.
+ csd
+ The Device-Specific Data (CSD) register. Uses offset.
+ dsr
+ The driver stage register (DSR).
+ ocr
+ The operation conditions register (OCR).
+ rca
+ The relative Device address (RCA) register.
+ extcsd
+ The Extended CSD register. Uses offset.
+ offset
+ For 'cid'/'csd' 128 bit registers '[0..3]' in 32-bit increments. For 'extcsd' 512 bit register '[0..512,all]' in 8-bit increments, or 'all' to read the entire register.
+ env
+ Optional environment variable into which 32-bit value read from register should be stored.
Examples
--------
diff --git a/doc/usage/cmd/part.rst b/doc/usage/cmd/part.rst
index 8a594aa..eee5225 100644
--- a/doc/usage/cmd/part.rst
+++ b/doc/usage/cmd/part.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+:
part command
-===============
+============
Synopis
-------
diff --git a/doc/usage/cmd/qfw.rst b/doc/usage/cmd/qfw.rst
index ec13e09..e734b26 100644
--- a/doc/usage/cmd/qfw.rst
+++ b/doc/usage/cmd/qfw.rst
@@ -15,7 +15,7 @@
Description
-----------
-The *qfw* command is used to retrieve information form the QEMU firmware.
+The *qfw* command is used to retrieve information from the QEMU firmware.
The *qfw list* sub-command displays the QEMU firmware files.
diff --git a/doc/usage/cmd/wdt.rst b/doc/usage/cmd/wdt.rst
index 8d80433..8bb8b36 100644
--- a/doc/usage/cmd/wdt.rst
+++ b/doc/usage/cmd/wdt.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+:
wdt command
-============
+===========
Synopsis
--------
diff --git a/doc/usage/cmd/wget.rst b/doc/usage/cmd/wget.rst
index e1e7f8d..8e7383b 100644
--- a/doc/usage/cmd/wget.rst
+++ b/doc/usage/cmd/wget.rst
@@ -16,7 +16,8 @@
The wget command is used to download a file from an HTTP server.
wget command will use HTTP over TCP to download files from an HTTP server.
-Currently it can only download image from an HTTP server hosted on port 80.
+By default the destination port is 80 and the source port is pseudo-random.
+The environment variable *httpdstp* can be used to set the destination port.
address
memory address for the data downloaded
diff --git a/doc/usage/cmd/xxd.rst b/doc/usage/cmd/xxd.rst
index 0de1223..13bb438 100644
--- a/doc/usage/cmd/xxd.rst
+++ b/doc/usage/cmd/xxd.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+:
xxd command
-===============
+===========
Synopsis
--------
diff --git a/doc/usage/dfu.rst b/doc/usage/dfu.rst
index 68cacbb..8845a71 100644
--- a/doc/usage/dfu.rst
+++ b/doc/usage/dfu.rst
@@ -121,6 +121,11 @@
with
+ offset
+ is the offset in the device (hexadecimal without "0x")
+ size
+ is the size of the access area (hexadecimal without "0x")
+ or 0 which means whole device
partid
being the GPT or DOS partition index,
num
diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst
index c6439dd..82b6ea7 100644
--- a/doc/usage/environment.rst
+++ b/doc/usage/environment.rst
@@ -216,7 +216,7 @@
0xffffffffffffffff (64-bit machines) then
the fdt will not be copied at all on boot. For this
to work it must reside in writable memory, have
- sufficient padding on the end of it for u-boot to
+ sufficient padding on the end of it for U-Boot to
add the information it needs into it, and the memory
must be accessible by the kernel. This usage is strongly discouraged
however as it also stops U-Boot from ensuring the device tree starting
@@ -306,6 +306,10 @@
anything other than "no", U-Boot does go through all
available network interfaces.
+httpdstp
+ If this is set, the value is used for HTTP's TCP
+ destination port instead of the default port 80.
+
netretry
When set to "no" each network operation will
either succeed or fail without retrying.
diff --git a/doc/usage/fdt_overlays.rst b/doc/usage/fdt_overlays.rst
index 7f113ed..81d0d37 100644
--- a/doc/usage/fdt_overlays.rst
+++ b/doc/usage/fdt_overlays.rst
@@ -43,7 +43,7 @@
$ dtc -@ -I dts -O dtb -o base.dtb base.dts
-**overlay.dts**
+**overlay.dtso**
::
@@ -63,7 +63,7 @@
.. code-block:: console
- $ dtc -@ -I dts -O dtb -o overlay.dtbo overlay.dts
+ $ dtc -@ -I dts -O dtb -o overlay.dtbo overlay.dtso
Ways to Utilize Overlays in U-Boot
----------------------------------
diff --git a/doc/usage/fit/beaglebone_vboot.rst b/doc/usage/fit/beaglebone_vboot.rst
index 0580ee1..a102be1 100644
--- a/doc/usage/fit/beaglebone_vboot.rst
+++ b/doc/usage/fit/beaglebone_vboot.rst
@@ -86,7 +86,7 @@
Step 2: Build Linux
---------------------
+-------------------
a. Find the kernel image ('Image') and device tree (.dtb) file you plan to
use. In our case it is am335x-boneblack.dtb and it is built with the kernel.
diff --git a/doc/usage/index.rst b/doc/usage/index.rst
index fa70292..d8e23fc 100644
--- a/doc/usage/index.rst
+++ b/doc/usage/index.rst
@@ -14,6 +14,7 @@
partitions
cmdline
semihosting
+ measured_boot
Shell commands
--------------
@@ -37,8 +38,8 @@
cmd/bootm
cmd/bootmenu
cmd/bootmeth
- cmd/button
cmd/bootz
+ cmd/button
cmd/cat
cmd/cbsysinfo
cmd/cedit
@@ -56,8 +57,8 @@
cmd/env
cmd/event
cmd/exception
- cmd/extension
cmd/exit
+ cmd/extension
cmd/false
cmd/fatinfo
cmd/fatload
@@ -67,6 +68,7 @@
cmd/fwu_mdata
cmd/gpio
cmd/gpt
+ cmd/history
cmd/host
cmd/imxtract
cmd/load
@@ -92,15 +94,15 @@
cmd/rng
cmd/saves
cmd/sbi
- cmd/sf
cmd/scp03
cmd/seama
cmd/setexpr
+ cmd/sf
cmd/size
cmd/sleep
+ cmd/sm
cmd/sound
cmd/source
- cmd/sm
cmd/temperature
cmd/tftpput
cmd/trace
diff --git a/doc/usage/measured_boot.rst b/doc/usage/measured_boot.rst
new file mode 100644
index 0000000..9691904
--- /dev/null
+++ b/doc/usage/measured_boot.rst
@@ -0,0 +1,31 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Measured Boot
+=============
+
+U-Boot can perform a measured boot, the process of hashing various components
+of the boot process, extending the results in the TPM and logging the
+component's measurement in memory for the operating system to consume.
+
+By default, U-Boot will measure the operating system (linux) image, the
+initrd image, and the "bootargs" environment variable. By enabling
+CONFIG_MEASURE_DEVICETREE, U-Boot will also measure the devicetree image.
+
+The operating system typically would verify that the hashes found in the
+TPM PCRs match the contents of the event log. This can further be checked
+against the hash results of previous boots.
+
+Requirements
+------------
+
+* A hardware TPM 2.0 supported by the U-Boot drivers
+* CONFIG_TPM=y
+* CONFIG_MEASURED_BOOT=y
+* Device-tree configuration of the TPM device to specify the memory area
+ for event logging. The TPM device node must either contain a phandle to
+ a reserved memory region or "linux,sml-base" and "linux,sml-size"
+ indicating the address and size of the memory region. An example can be
+ found in arch/sandbox/dts/test.dts
+* The operating system must also be configured to use the memory regions
+ specified in the U-Boot device-tree in order to make use of the event
+ log.
diff --git a/doc/usage/semihosting.rst b/doc/usage/semihosting.rst
index 6a280b4..9303a63 100644
--- a/doc/usage/semihosting.rst
+++ b/doc/usage/semihosting.rst
@@ -23,7 +23,7 @@
There are two main ARM virtual Fixed Virtual Platform (FVP) models,
`Versatile Express (VE) FVP and BASE FVP
<http://www.arm.com/products/tools/models/fast-models/foundation-model.php>`_.
-The initial vexpress64 u-boot board created here runs on the VE virtual
+The initial vexpress64 U-Boot board created here runs on the VE virtual
platform using the license-free Foundation_v8 simulator. Fortunately,
the Foundation_v8 simulator also supports the BASE_FVP model which
companies can purchase licenses for and contain much more functionality.
diff --git a/drivers/Kconfig b/drivers/Kconfig
index a25f6ae..a073230 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -118,6 +118,8 @@
source "drivers/serial/Kconfig"
+source "drivers/sm/Kconfig"
+
source "drivers/smem/Kconfig"
source "drivers/sound/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index efc2a4a..bf73b77 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -35,6 +35,7 @@
obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox/
obj-$(CONFIG_$(SPL_)REMOTEPROC) += remoteproc/
obj-$(CONFIG_$(SPL_)SYSINFO) += sysinfo/
+obj-$(CONFIG_$(SPL_TPL_)SM) += sm/
obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/
obj-$(CONFIG_$(SPL_)NVME) += nvme/
obj-$(CONFIG_XEN) += xen/
@@ -56,6 +57,7 @@
obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/
obj-$(CONFIG_IMX8ULP_DRAM) += ddr/imx/imx8ulp/
obj-$(CONFIG_ARCH_IMX9) += ddr/imx/imx9/
+obj-$(CONFIG_DRAM_SUN20I_D1) += ram/
obj-$(CONFIG_SPL_DM_RESET) += reset/
obj-$(CONFIG_SPL_MUSB_NEW) += usb/musb-new/
obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/
diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig
index 4336732..a01d738 100644
--- a/drivers/adc/Kconfig
+++ b/drivers/adc/Kconfig
@@ -66,6 +66,7 @@
config ADC_IMX93
bool "Enable NXP IMX93 ADC driver"
+ depends on ADC
help
This enables basic driver for NXP IMX93 ADC.
It provides:
diff --git a/drivers/adc/adc-uclass.c b/drivers/adc/adc-uclass.c
index 9646e4d..1b35bf2 100644
--- a/drivers/adc/adc-uclass.c
+++ b/drivers/adc/adc-uclass.c
@@ -15,6 +15,7 @@
#include <dm/uclass-internal.h>
#include <adc.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <power/regulator.h>
#define ADC_UCLASS_PLATDATA_SIZE sizeof(struct adc_uclass_plat)
@@ -51,23 +52,21 @@
static int adc_supply_enable(struct udevice *dev)
{
struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
- const char *supply_type;
- int ret = 0;
+ int ret;
- if (uc_pdata->vdd_supply) {
- supply_type = "vdd";
- ret = regulator_set_enable(uc_pdata->vdd_supply, true);
+ ret = regulator_set_enable_if_allowed(uc_pdata->vdd_supply, true);
+ if (ret && ret != -ENOSYS) {
+ pr_err("%s: can't enable vdd-supply!", dev->name);
+ return ret;
}
- if (!ret && uc_pdata->vss_supply) {
- supply_type = "vss";
- ret = regulator_set_enable(uc_pdata->vss_supply, true);
+ ret = regulator_set_enable_if_allowed(uc_pdata->vss_supply, true);
+ if (ret && ret != -ENOSYS) {
+ pr_err("%s: can't enable vss-supply!", dev->name);
+ return ret;
}
- if (ret)
- pr_err("%s: can't enable %s-supply!", dev->name, supply_type);
-
- return ret;
+ return 0;
}
int adc_data_mask(struct udevice *dev, unsigned int *data_mask)
diff --git a/drivers/adc/exynos-adc.c b/drivers/adc/exynos-adc.c
index 6589817..2bda733 100644
--- a/drivers/adc/exynos-adc.c
+++ b/drivers/adc/exynos-adc.c
@@ -8,6 +8,7 @@
#include <dm.h>
#include <adc.h>
#include <asm/arch/adc.h>
+#include <linux/printk.h>
struct exynos_adc_priv {
int active_channel;
diff --git a/drivers/adc/meson-saradc.c b/drivers/adc/meson-saradc.c
index 3702351..c15c7fe 100644
--- a/drivers/adc/meson-saradc.c
+++ b/drivers/adc/meson-saradc.c
@@ -18,6 +18,7 @@
#include <linux/delay.h>
#include <linux/math64.h>
#include <linux/bitfield.h>
+#include <linux/printk.h>
#include <power/regulator.h>
#define MESON_SAR_ADC_REG0 0x00
diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c
index 809486e..03caca7 100644
--- a/drivers/adc/rockchip-saradc.c
+++ b/drivers/adc/rockchip-saradc.c
@@ -13,6 +13,7 @@
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/err.h>
+#include <linux/printk.h>
#include <power/regulator.h>
#define SARADC_CTRL_CHN_MASK GENMASK(2, 0)
diff --git a/drivers/adc/sandbox.c b/drivers/adc/sandbox.c
index 6e43546..43cad34 100644
--- a/drivers/adc/sandbox.c
+++ b/drivers/adc/sandbox.c
@@ -8,6 +8,7 @@
#include <dm.h>
#include <adc.h>
#include <sandbox-adc.h>
+#include <linux/printk.h>
/**
* struct sandbox_adc_priv - sandbox ADC device's operation status and data
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 6e30180..0b6f910 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -10,7 +10,7 @@
obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
obj-$(CONFIG_FSL_SATA) += fsl_sata.o
obj-$(CONFIG_LIBATA) += libata.o
-obj-$(CONFIG_SATA) += sata.o
+obj-$(CONFIG_SATA) += sata.o sata_bootdev.o
obj-$(CONFIG_SATA_CEVA) += sata_ceva.o
obj-$(CONFIG_SATA_MV) += sata_mv.o
obj-$(CONFIG_SATA_SIL) += sata_sil.o
diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
index 94a3379..9064774 100644
--- a/drivers/ata/ahci_sunxi.c
+++ b/drivers/ata/ahci_sunxi.c
@@ -7,6 +7,7 @@
#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/delay.h>
+#include <power/regulator.h>
#define AHCI_PHYCS0R 0x00c0
#define AHCI_PHYCS1R 0x00c4
@@ -74,6 +75,7 @@
static int sunxi_sata_probe(struct udevice *dev)
{
+ struct udevice *reg_dev;
ulong base;
u8 *reg;
int ret;
@@ -89,6 +91,13 @@
debug("%s: Failed to init phy (err=%d)\n", __func__, ret);
return ret;
}
+
+ ret = device_get_supply_regulator(dev, "target-supply", ®_dev);
+ if (ret == 0) {
+ regulator_set_enable(reg_dev, true);
+ mdelay(500);
+ }
+
ret = ahci_probe_scsi(dev, base);
if (ret) {
debug("%s: Failed to probe (err=%d)\n", __func__, ret);
diff --git a/drivers/ata/dwc_ahci.c b/drivers/ata/dwc_ahci.c
index 1dc91e7..15fd3e3 100644
--- a/drivers/ata/dwc_ahci.c
+++ b/drivers/ata/dwc_ahci.c
@@ -18,6 +18,7 @@
#endif
#include <asm/io.h>
#include <generic-phy.h>
+#include <linux/printk.h>
struct dwc_ahci_priv {
void *base;
diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c
index 6a4d861..b4d4e39 100644
--- a/drivers/ata/dwc_ahsata.c
+++ b/drivers/ata/dwc_ahsata.c
@@ -880,7 +880,8 @@
device_find_first_child(dev, &blk);
if (!blk) {
ret = blk_create_devicef(dev, "dwc_ahsata_blk", "blk",
- UCLASS_AHCI, -1, 512, 0, &blk);
+ UCLASS_AHCI, -1, DEFAULT_BLKSZ,
+ 0, &blk);
if (ret) {
debug("Can't create device\n");
return ret;
diff --git a/drivers/ata/fsl_sata.c b/drivers/ata/fsl_sata.c
index 972101b..969bc19 100644
--- a/drivers/ata/fsl_sata.c
+++ b/drivers/ata/fsl_sata.c
@@ -888,7 +888,8 @@
for (i = 0; i < nr_ports; i++) {
snprintf(sata_name, sizeof(sata_name), "fsl_sata%d", i);
ret = blk_create_devicef(dev, "sata_fsl_blk", sata_name,
- UCLASS_AHCI, -1, 512, 0, &blk);
+ UCLASS_AHCI, -1, DEFAULT_BLKSZ,
+ 0, &blk);
if (ret) {
debug("Can't create device\n");
return ret;
diff --git a/drivers/ata/sata.c b/drivers/ata/sata.c
index ce3e9b5..64fc078 100644
--- a/drivers/ata/sata.c
+++ b/drivers/ata/sata.c
@@ -15,6 +15,8 @@
#include <dm.h>
#include <part.h>
#include <sata.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
#ifndef CONFIG_AHCI
struct blk_desc sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
@@ -50,6 +52,42 @@
return ops->scan(dev);
}
+int sata_rescan(bool verbose)
+{
+ int ret;
+ struct udevice *dev;
+
+ if (verbose)
+ printf("Removing devices on SATA bus...\n");
+
+ blk_unbind_all(UCLASS_AHCI);
+
+ ret = uclass_find_first_device(UCLASS_AHCI, &dev);
+ if (ret || !dev) {
+ printf("Cannot find SATA device (err=%d)\n", ret);
+ return -ENOENT;
+ }
+
+ ret = device_remove(dev, DM_REMOVE_NORMAL);
+ if (ret) {
+ printf("Cannot remove SATA device '%s' (err=%d)\n", dev->name, ret);
+ return -ENOSYS;
+ }
+
+ if (verbose)
+ printf("Rescanning SATA bus for devices...\n");
+
+ ret = uclass_probe_all(UCLASS_AHCI);
+
+ if (ret == -ENODEV) {
+ if (verbose)
+ printf("No SATA block device found\n");
+ return 0;
+ }
+
+ return ret;
+}
+
#ifndef CONFIG_AHCI
#ifdef CONFIG_PARTITIONS
struct blk_desc *sata_get_dev(int dev)
diff --git a/drivers/ata/sata_bootdev.c b/drivers/ata/sata_bootdev.c
new file mode 100644
index 0000000..f638493
--- /dev/null
+++ b/drivers/ata/sata_bootdev.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Bootdev for sata
+ *
+ * Copyright 2023 Tony Dinh <mibodhi@gmail.com>
+ */
+
+#include <common.h>
+#include <ahci.h>
+#include <bootdev.h>
+#include <dm.h>
+#include <init.h>
+#include <sata.h>
+
+static int sata_bootdev_bind(struct udevice *dev)
+{
+ struct bootdev_uc_plat *ucp = dev_get_uclass_plat(dev);
+
+ ucp->prio = BOOTDEVP_4_SCAN_FAST;
+
+ return 0;
+}
+
+static int sata_bootdev_hunt(struct bootdev_hunter *info, bool show)
+{
+ int ret;
+
+ if (IS_ENABLED(CONFIG_PCI)) {
+ ret = pci_init();
+ if (ret)
+ return ret;
+ }
+
+ ret = sata_rescan(true);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+struct bootdev_ops sata_bootdev_ops = {
+};
+
+static const struct udevice_id sata_bootdev_ids[] = {
+ { .compatible = "u-boot,bootdev-sata" },
+ { }
+};
+
+U_BOOT_DRIVER(sata_bootdev) = {
+ .name = "sata_bootdev",
+ .id = UCLASS_BOOTDEV,
+ .ops = &sata_bootdev_ops,
+ .bind = sata_bootdev_bind,
+ .of_match = sata_bootdev_ids,
+};
+
+BOOTDEV_HUNTER(sata_bootdev_hunter) = {
+ .prio = BOOTDEVP_4_SCAN_FAST,
+ .uclass = UCLASS_AHCI,
+ .hunt = sata_bootdev_hunt,
+ .drv = DM_DRIVER_REF(sata_bootdev),
+};
diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c
index 4736643..7769d4f 100644
--- a/drivers/ata/sata_ceva.c
+++ b/drivers/ata/sata_ceva.c
@@ -217,7 +217,7 @@
}
}
- if (phy.dev) {
+ if (generic_phy_valid(&phy)) {
dev_dbg(dev, "Perform PHY power on\n");
ret = generic_phy_power_on(&phy);
if (ret) {
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index 18c7a66..94d7369 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -34,6 +34,7 @@
#include <common.h>
#include <ahci.h>
#include <blk.h>
+#include <bootdev.h>
#include <cpu_func.h>
#include <dm.h>
#include <log.h>
@@ -1076,7 +1077,8 @@
for (i = 0; i < nr_ports; i++) {
ret = blk_create_devicef(dev, "sata_mv_blk", "blk",
- UCLASS_AHCI, -1, 512, 0, &blk);
+ UCLASS_AHCI, -1, DEFAULT_BLKSZ,
+ 0, &blk);
if (ret) {
debug("Can't create device\n");
continue;
@@ -1104,6 +1106,12 @@
/* TODO: undo create */
continue;
+ ret = bootdev_setup_for_sibling_blk(blk, "sata_bootdev");
+ if (ret) {
+ printf("%s: Failed to create bootdev\n", __func__);
+ continue;
+ }
+
/* If we got here, the current SATA port was probed
* successfully, so set the probe status to successful.
*/
@@ -1116,7 +1124,6 @@
static int sata_mv_scan(struct udevice *dev)
{
/* Nothing to do here */
-
return 0;
}
diff --git a/drivers/ata/sata_sil.c b/drivers/ata/sata_sil.c
index b5e150d..43a91a7 100644
--- a/drivers/ata/sata_sil.c
+++ b/drivers/ata/sata_sil.c
@@ -730,7 +730,8 @@
for (i = sata_info.portbase; i < sata_info.maxport; i++) {
snprintf(sata_name, sizeof(sata_name), "sil_sata%d", i);
ret = blk_create_devicef(dev, "sata_sil_blk", sata_name,
- UCLASS_AHCI, -1, 512, 0, &blk);
+ UCLASS_AHCI, -1, DEFAULT_BLKSZ,
+ 0, &blk);
if (ret) {
debug("Can't create device\n");
return ret;
diff --git a/drivers/bios_emulator/include/x86emu/debug.h b/drivers/bios_emulator/include/x86emu/debug.h
index 4962a2a..859b54d 100644
--- a/drivers/bios_emulator/include/x86emu/debug.h
+++ b/drivers/bios_emulator/include/x86emu/debug.h
@@ -43,6 +43,7 @@
/* checks to be enabled for "runtime" */
+#include <linux/printk.h>
#define CHECK_IP_FETCH_F 0x1
#define CHECK_SP_ACCESS_F 0x2
#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */
diff --git a/drivers/bios_emulator/include/x86emu/regs.h b/drivers/bios_emulator/include/x86emu/regs.h
index 2934129..4b4c590 100644
--- a/drivers/bios_emulator/include/x86emu/regs.h
+++ b/drivers/bios_emulator/include/x86emu/regs.h
@@ -41,6 +41,7 @@
/*---------------------- Macros and type definitions ----------------------*/
+#include <linux/printk.h>
#pragma pack(1)
/*
diff --git a/drivers/bios_emulator/x86emu/debug.c b/drivers/bios_emulator/x86emu/debug.c
index 27e90e4..95f3cc0 100644
--- a/drivers/bios_emulator/x86emu/debug.c
+++ b/drivers/bios_emulator/x86emu/debug.c
@@ -40,6 +40,7 @@
#include <stdarg.h>
#include <common.h>
#include <linux/ctype.h>
+#include <linux/printk.h>
#include "x86emu/x86emui.h"
/*----------------------------- Implementation ----------------------------*/
diff --git a/drivers/bios_emulator/x86emu/decode.c b/drivers/bios_emulator/x86emu/decode.c
index a9a01b5..e2028ea 100644
--- a/drivers/bios_emulator/x86emu/decode.c
+++ b/drivers/bios_emulator/x86emu/decode.c
@@ -37,6 +37,7 @@
*
****************************************************************************/
#include <common.h>
+#include <linux/printk.h>
#include "x86emu/x86emui.h"
/*----------------------------- Implementation ----------------------------*/
diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c
index ba18135..8c1a146 100644
--- a/drivers/bios_emulator/x86emu/ops.c
+++ b/drivers/bios_emulator/x86emu/ops.c
@@ -73,6 +73,7 @@
****************************************************************************/
#include <common.h>
+#include <linux/printk.h>
#include "x86emu/x86emui.h"
/*----------------------------- Implementation ----------------------------*/
diff --git a/drivers/bios_emulator/x86emu/ops2.c b/drivers/bios_emulator/x86emu/ops2.c
index be4ef36..6cd1ac3 100644
--- a/drivers/bios_emulator/x86emu/ops2.c
+++ b/drivers/bios_emulator/x86emu/ops2.c
@@ -43,6 +43,7 @@
#include <common.h>
#include <linux/compiler.h>
+#include <linux/printk.h>
#include "x86emu/x86emui.h"
/*----------------------------- Implementation ----------------------------*/
diff --git a/drivers/bios_emulator/x86emu/sys.c b/drivers/bios_emulator/x86emu/sys.c
index 882a8a3..f966524 100644
--- a/drivers/bios_emulator/x86emu/sys.c
+++ b/drivers/bios_emulator/x86emu/sys.c
@@ -40,6 +40,7 @@
****************************************************************************/
#include <common.h>
+#include <linux/printk.h>
#include "x86emu/x86emui.h"
/*------------------------- Global Variables ------------------------------*/
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index 6baaa6f..048a6ca 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -167,7 +167,7 @@
config SYS_ATA_BASE_ADDR
hex "Base address of IDE controller"
- default 0
+ default 0x0
help
This is the address of the IDE controller, from which other addresses
are calculated. Each bus is at a fixed offset from this address,
@@ -262,3 +262,10 @@
help
Make the block subsystem use 64bit sector addresses, rather than the
default of 32bit.
+
+config RKMTD
+ bool "Rockchip rkmtd virtual block device"
+ help
+ Enable "rkmtd" class and driver to create a virtual block device
+ to transfer Rockchip boot block data to and from NAND with block
+ orientate tools like "ums" and "rockusb".
diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index a161d14..fdcba5c 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -11,6 +11,7 @@
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_IDE) += ide.o
+obj-$(CONFIG_RKMTD) += rkmtd.o
endif
obj-$(CONFIG_SANDBOX) += sandbox.o host-uclass.o host_dev.o
obj-$(CONFIG_$(SPL_TPL_)BLOCK_CACHE) += blkcache.o
@@ -19,3 +20,4 @@
obj-$(CONFIG_EFI_MEDIA) += efi-media-uclass.o
obj-$(CONFIG_EFI_MEDIA_SANDBOX) += sb_efi_media.o
obj-$(CONFIG_EFI_MEDIA_BLK) += efi_blk.o
+
diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index 614b975..77066da 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -17,6 +17,8 @@
#include <dm/uclass-internal.h>
#include <linux/err.h>
+#define blk_get_ops(dev) ((struct blk_ops *)(dev)->driver->ops)
+
static struct {
enum uclass_id id;
const char *name;
@@ -34,6 +36,7 @@
{ UCLASS_VIRTIO, "virtio" },
{ UCLASS_PVBLOCK, "pvblock" },
{ UCLASS_BLKMAP, "blkmap" },
+ { UCLASS_RKMTD, "rkmtd" },
};
static enum uclass_id uclass_name_to_iftype(const char *uclass_idname)
@@ -176,17 +179,7 @@
return NULL;
}
-/**
- * get_desc() - Get the block device descriptor for the given device number
- *
- * @uclass_id: Interface type
- * @devnum: Device number (0 = first)
- * @descp: Returns block device descriptor on success
- * Return: 0 on success, -ENODEV if there is no such device and no device
- * with a higher device number, -ENOENT if there is no such device but there
- * is one with a higher number, or other -ve on other error.
- */
-static int get_desc(enum uclass_id uclass_id, int devnum, struct blk_desc **descp)
+int blk_get_desc(enum uclass_id uclass_id, int devnum, struct blk_desc **descp)
{
bool found_more = false;
struct udevice *dev;
@@ -238,7 +231,7 @@
int ret;
for (ok = 0, devnum = 0;; ++devnum) {
- ret = get_desc(uclass_id, devnum, &desc);
+ ret = blk_get_desc(uclass_id, devnum, &desc);
if (ret == -ENODEV)
break;
else if (ret)
@@ -261,7 +254,7 @@
struct blk_desc *desc;
int ret;
- ret = get_desc(uclass_id, devnum, &desc);
+ ret = blk_get_desc(uclass_id, devnum, &desc);
if (ret)
return ret;
if (desc->type == DEV_TYPE_UNKNOWN)
@@ -278,7 +271,7 @@
int i;
for (i = 0;; ++i) {
- ret = get_desc(uclass_id, i, &desc);
+ ret = blk_get_desc(uclass_id, i, &desc);
if (ret == -ENODEV)
break;
else if (ret)
@@ -295,7 +288,7 @@
struct blk_desc *desc;
int ret;
- ret = get_desc(uclass_id, devnum, &desc);
+ ret = blk_get_desc(uclass_id, devnum, &desc);
if (ret)
return ret;
printf("\nIDE device %d: ", devnum);
@@ -310,7 +303,7 @@
int ret;
printf("\nDevice %d: ", devnum);
- ret = get_desc(uclass_id, devnum, &desc);
+ ret = blk_get_desc(uclass_id, devnum, &desc);
if (ret == -ENODEV || ret == -ENOENT) {
printf("unknown device\n");
return -ENODEV;
@@ -325,35 +318,6 @@
return 0;
}
-ulong blk_read_devnum(enum uclass_id uclass_id, int devnum, lbaint_t start,
- lbaint_t blkcnt, void *buffer)
-{
- struct blk_desc *desc;
- ulong n;
- int ret;
-
- ret = get_desc(uclass_id, devnum, &desc);
- if (ret)
- return ret;
- n = blk_dread(desc, start, blkcnt, buffer);
- if (IS_ERR_VALUE(n))
- return n;
-
- return n;
-}
-
-ulong blk_write_devnum(enum uclass_id uclass_id, int devnum, lbaint_t start,
- lbaint_t blkcnt, const void *buffer)
-{
- struct blk_desc *desc;
- int ret;
-
- ret = get_desc(uclass_id, devnum, &desc);
- if (ret)
- return ret;
- return blk_dwrite(desc, start, blkcnt, buffer);
-}
-
int blk_select_hwpart(struct udevice *dev, int hwpart)
{
const struct blk_ops *ops = blk_get_ops(dev);
@@ -444,6 +408,26 @@
return device_probe(*devp);
}
+struct blk_bounce_buffer {
+ struct udevice *dev;
+ struct bounce_buffer state;
+};
+
+static int blk_buffer_aligned(struct bounce_buffer *state)
+{
+#if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
+ struct blk_bounce_buffer *bbstate =
+ container_of(state, struct blk_bounce_buffer, state);
+ struct udevice *dev = bbstate->dev;
+ const struct blk_ops *ops = blk_get_ops(dev);
+
+ if (ops->buffer_aligned)
+ return ops->buffer_aligned(dev, state);
+#endif /* CONFIG_BOUNCE_BUFFER */
+
+ return 1; /* Default, any buffer is OK */
+}
+
long blk_read(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *buf)
{
struct blk_desc *desc = dev_get_uclass_plat(dev);
@@ -456,7 +440,25 @@
if (blkcache_read(desc->uclass_id, desc->devnum,
start, blkcnt, desc->blksz, buf))
return blkcnt;
- blks_read = ops->read(dev, start, blkcnt, buf);
+
+ if (IS_ENABLED(CONFIG_BOUNCE_BUFFER) && desc->bb) {
+ struct blk_bounce_buffer bbstate = { .dev = dev };
+ int ret;
+
+ ret = bounce_buffer_start_extalign(&bbstate.state, buf,
+ blkcnt * desc->blksz,
+ GEN_BB_WRITE, desc->blksz,
+ blk_buffer_aligned);
+ if (ret)
+ return ret;
+
+ blks_read = ops->read(dev, start, blkcnt, bbstate.state.bounce_buffer);
+
+ bounce_buffer_stop(&bbstate.state);
+ } else {
+ blks_read = ops->read(dev, start, blkcnt, buf);
+ }
+
if (blks_read == blkcnt)
blkcache_fill(desc->uclass_id, desc->devnum, start, blkcnt,
desc->blksz, buf);
@@ -469,13 +471,33 @@
{
struct blk_desc *desc = dev_get_uclass_plat(dev);
const struct blk_ops *ops = blk_get_ops(dev);
+ long blks_written;
if (!ops->write)
return -ENOSYS;
blkcache_invalidate(desc->uclass_id, desc->devnum);
- return ops->write(dev, start, blkcnt, buf);
+ if (IS_ENABLED(CONFIG_BOUNCE_BUFFER) && desc->bb) {
+ struct blk_bounce_buffer bbstate = { .dev = dev };
+ int ret;
+
+ ret = bounce_buffer_start_extalign(&bbstate.state, (void *)buf,
+ blkcnt * desc->blksz,
+ GEN_BB_READ, desc->blksz,
+ blk_buffer_aligned);
+ if (ret)
+ return ret;
+
+ blks_written = ops->write(dev, start, blkcnt,
+ bbstate.state.bounce_buffer);
+
+ bounce_buffer_stop(&bbstate.state);
+ } else {
+ blks_written = ops->write(dev, start, blkcnt, buf);
+ }
+
+ return blks_written;
}
long blk_erase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt)
@@ -766,6 +788,54 @@
return 0;
}
+static int part_create_block_devices(struct udevice *blk_dev)
+{
+ int part, count;
+ struct blk_desc *desc = dev_get_uclass_plat(blk_dev);
+ struct disk_partition info;
+ struct disk_part *part_data;
+ char devname[32];
+ struct udevice *dev;
+ int ret;
+
+ if (!CONFIG_IS_ENABLED(PARTITIONS) || !blk_enabled())
+ return 0;
+
+ if (device_get_uclass_id(blk_dev) != UCLASS_BLK)
+ return 0;
+
+ /* Add devices for each partition */
+ for (count = 0, part = 1; part <= MAX_SEARCH_PARTITIONS; part++) {
+ if (part_get_info(desc, part, &info))
+ continue;
+ snprintf(devname, sizeof(devname), "%s:%d", blk_dev->name,
+ part);
+
+ ret = device_bind_driver(blk_dev, "blk_partition",
+ strdup(devname), &dev);
+ if (ret)
+ return ret;
+
+ part_data = dev_get_uclass_plat(dev);
+ part_data->partnum = part;
+ part_data->gpt_part_info = info;
+ count++;
+
+ ret = device_probe(dev);
+ if (ret) {
+ debug("Can't probe\n");
+ count--;
+ device_unbind(dev);
+
+ continue;
+ }
+ }
+ debug("%s: %d partitions found in %s\n", __func__, count,
+ blk_dev->name);
+
+ return 0;
+}
+
static int blk_post_probe(struct udevice *dev)
{
if (CONFIG_IS_ENABLED(PARTITIONS) && blk_enabled()) {
diff --git a/drivers/block/blkcache.c b/drivers/block/blkcache.c
index f99465a..26bcbea 100644
--- a/drivers/block/blkcache.c
+++ b/drivers/block/blkcache.c
@@ -13,10 +13,6 @@
#include <linux/ctype.h>
#include <linux/list.h>
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
struct block_cache_node {
struct list_head lh;
int iftype;
@@ -34,18 +30,6 @@
.max_entries = 32
};
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
-int blkcache_init(void)
-{
- struct list_head *head = &block_cache;
-
- head->next = (uintptr_t)head->next + gd->reloc_off;
- head->prev = (uintptr_t)head->prev + gd->reloc_off;
-
- return 0;
-}
-#endif
-
static struct block_cache_node *cache_find(int iftype, int devnum,
lbaint_t start, lbaint_t blkcnt,
unsigned long blksz)
diff --git a/drivers/block/blkmap.c b/drivers/block/blkmap.c
index 2bb0acc..149a4ca 100644
--- a/drivers/block/blkmap.c
+++ b/drivers/block/blkmap.c
@@ -171,11 +171,11 @@
bd = dev_get_uclass_plat(bm->blk);
lbd = dev_get_uclass_plat(lblk);
- if (lbd->blksz != bd->blksz)
- /* We could support block size translation, but we
- * don't yet.
- */
- return -EINVAL;
+ if (lbd->blksz != bd->blksz) {
+ /* update to match the mapped device */
+ bd->blksz = lbd->blksz;
+ bd->log2blksz = LOG2(bd->blksz);
+ }
linear = malloc(sizeof(*linear));
if (!linear)
@@ -383,14 +383,14 @@
.ops = &blkmap_blk_ops,
};
-int blkmap_dev_bind(struct udevice *dev)
+static int blkmap_dev_bind(struct udevice *dev)
{
struct blkmap *bm = dev_get_plat(dev);
struct blk_desc *bd;
int err;
err = blk_create_devicef(dev, "blkmap_blk", "blk", UCLASS_BLKMAP,
- dev_seq(dev), 512, 0, &bm->blk);
+ dev_seq(dev), DEFAULT_BLKSZ, 0, &bm->blk);
if (err)
return log_msg_ret("blk", err);
@@ -410,7 +410,7 @@
return 0;
}
-int blkmap_dev_unbind(struct udevice *dev)
+static int blkmap_dev_unbind(struct udevice *dev)
{
struct blkmap *bm = dev_get_plat(dev);
struct blkmap_slice *bms, *tmp;
diff --git a/drivers/block/host-uclass.c b/drivers/block/host-uclass.c
index 6460d96..b3647e3 100644
--- a/drivers/block/host-uclass.c
+++ b/drivers/block/host-uclass.c
@@ -13,6 +13,7 @@
#include <blk.h>
#include <dm.h>
#include <malloc.h>
+#include <part.h>
#include <sandbox_host.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
@@ -29,7 +30,8 @@
struct udevice *cur_dev;
};
-int host_create_device(const char *label, bool removable, struct udevice **devp)
+int host_create_device(const char *label, bool removable, unsigned long blksz,
+ struct udevice **devp)
{
char dev_name[30], *str, *label_new;
struct host_sb_plat *plat;
@@ -68,6 +70,12 @@
struct blk_desc *desc = dev_get_uclass_plat(blk);
desc->removable = removable;
+
+ /* update blk device's block size with the provided one */
+ if (blksz != desc->blksz) {
+ desc->blksz = blksz;
+ desc->log2blksz = LOG2(desc->blksz);
+ }
}
plat = dev_get_plat(dev);
@@ -95,12 +103,13 @@
}
int host_create_attach_file(const char *label, const char *filename,
- bool removable, struct udevice **devp)
+ bool removable, unsigned long blksz,
+ struct udevice **devp)
{
struct udevice *dev;
int ret;
- ret = host_create_device(label, removable, &dev);
+ ret = host_create_device(label, removable, blksz, &dev);
if (ret)
return log_msg_ret("cre", ret);
diff --git a/drivers/block/host_dev.c b/drivers/block/host_dev.c
index 6442241..30c7415 100644
--- a/drivers/block/host_dev.c
+++ b/drivers/block/host_dev.c
@@ -58,6 +58,11 @@
size = os_filesize(fd);
desc = dev_get_uclass_plat(blk);
+ if (size % desc->blksz) {
+ printf("The size of host backing file '%s' is not multiple of "
+ "the device block size\n", filename);
+ goto err_fname;
+ }
desc->lba = size / desc->blksz;
/* write this in last, when nothing can go wrong */
@@ -73,7 +78,7 @@
return ret;
}
-int host_sb_detach_file(struct udevice *dev)
+static int host_sb_detach_file(struct udevice *dev)
{
struct host_sb_plat *plat = dev_get_plat(dev);
int ret;
@@ -105,7 +110,7 @@
int ret;
ret = blk_create_devicef(dev, "sandbox_host_blk", "blk", UCLASS_HOST,
- dev_seq(dev), 512, 0, &blk);
+ dev_seq(dev), DEFAULT_BLKSZ, 0, &blk);
if (ret)
return log_msg_ret("blk", ret);
@@ -123,7 +128,7 @@
return 0;
}
-struct host_ops host_sb_ops = {
+static struct host_ops host_sb_ops = {
.attach_file = host_sb_attach_file,
.detach_file = host_sb_detach_file,
};
diff --git a/drivers/block/rkmtd.c b/drivers/block/rkmtd.c
new file mode 100644
index 0000000..c55f052
--- /dev/null
+++ b/drivers/block/rkmtd.c
@@ -0,0 +1,1152 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Some functions are derived from:
+ * https://github.com/rockchip-linux/u-boot/blob/next-dev/drivers/rknand/rk_ftl_arm_v7.S
+ * Copyright (c) 2016-2018, Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * Driver interface derived from:
+ * /drivers/block/host_dev.c
+ * /drivers/block/host-uclass.c
+ * Copyright 2022 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * Copyright (C) 2023 Johan Jonker <jbx6244@gmail.com>
+ */
+
+#include <blk.h>
+#include <dm.h>
+#include <nand.h>
+#include <part.h>
+#include <rkmtd.h>
+#include <stddef.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <dm/device-internal.h>
+#include <dm/devres.h>
+#include <dm/lists.h>
+#include <dm/root.h>
+#include <dm/uclass-internal.h>
+#include <linux/mtd/mtd.h>
+#if !IS_ENABLED(CONFIG_SANDBOX)
+#include <linux/mtd/rawnand.h>
+#endif
+#include <u-boot/crc.h>
+
+struct nand_para_info nand_para_tbl[] = {
+ {6, {0x2c, 0x64, 0x44, 0x4b, 0xa9, 0x00}, 4, 1, 16, 256, 2, 2, 2048, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x2c, 0x44, 0x44, 0x4b, 0xa9, 0x00}, 4, 1, 16, 256, 2, 2, 1064, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x2c, 0x68, 0x04, 0x4a, 0xa9, 0x00}, 4, 1, 8, 256, 2, 2, 2048, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {5, {0x2c, 0x88, 0x04, 0x4b, 0xa9, 0x00}, 4, 1, 16, 256, 2, 2, 2048, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x2c, 0xa8, 0x05, 0xcb, 0xa9, 0x00}, 4, 2, 16, 256, 2, 2, 2048, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x2c, 0x68, 0x04, 0x46, 0x89, 0x00}, 4, 1, 8, 256, 2, 2, 2048, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x2c, 0x48, 0x04, 0x4a, 0xa5, 0x00}, 4, 1, 8, 256, 2, 2, 1024, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x2c, 0x84, 0x64, 0x3c, 0xa5, 0x00}, 4, 1, 32, 512, 2, 2, 1024, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {5, {0x2c, 0x84, 0x64, 0x54, 0xa9, 0x00}, 4, 1, 32, 512, 2, 2, 1024, 0x01df, 4, 18, 60, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x2c, 0xd7, 0x94, 0x3e, 0x84, 0x00}, 4, 1, 8, 128, 2, 2, 4096, 0x0117, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x2c, 0x48, 0x04, 0x46, 0x85, 0x00}, 4, 1, 8, 256, 2, 2, 1024, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x2c, 0x88, 0x05, 0xc6, 0x89, 0x00}, 4, 2, 8, 256, 2, 2, 2048, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {5, {0x2c, 0x88, 0x24, 0x4b, 0xa9, 0x00}, 4, 1, 16, 256, 2, 2, 2048, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x2c, 0x68, 0x00, 0x27, 0xa9, 0x00}, 4, 1, 16, 128, 1, 2, 2048, 0x011f, 0, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {5, {0x2c, 0x64, 0x64, 0x56, 0xa5, 0x00}, 4, 1, 24, 512, 2, 2, 700, 0x01df, 4, 18, 60, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x2c, 0x84, 0xc5, 0x4b, 0xa9, 0x00}, 4, 2, 16, 256, 2, 2, 2048, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x2c, 0xd5, 0xd1, 0xa6, 0x68, 0x00}, 4, 2, 8, 64, 1, 2, 2048, 0x0117, 0, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x2c, 0xdc, 0x90, 0xa6, 0x54, 0x00}, 4, 1, 8, 64, 1, 2, 1024, 0x0117, 0, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {5, {0x2c, 0x64, 0x64, 0x54, 0xa4, 0x00}, 4, 1, 32, 512, 2, 1, 1024, 0x01df, 4, 18, 60, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {5, {0x2c, 0x84, 0x44, 0x32, 0xaa, 0x00}, 4, 1, 32, 512, 2, 1, 2184, 0x05c7, 5, 19, 60, 32, 1, 0, 1, 0, 1, {0, 0, 0, 0, 0}},
+ {5, {0x2c, 0x64, 0x44, 0x32, 0xa5, 0x00}, 4, 1, 32, 512, 2, 1, 1048, 0x05c7, 5, 19, 60, 32, 1, 0, 1, 0, 1, {0, 0, 0, 0, 0}},
+ {5, {0x2c, 0x64, 0x64, 0x3c, 0xa5, 0x00}, 4, 1, 32, 512, 2, 1, 1044, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {5, {0x2c, 0x84, 0x44, 0x32, 0xaa, 0x00}, 4, 1, 32, 512, 2, 1, 2184, 0x05c7, 5, 19, 60, 32, 1, 0, 4, 0, 1, {0, 0, 0, 0, 0}},
+ {5, {0x2c, 0x84, 0x44, 0x34, 0xaa, 0x00}, 4, 1, 32, 512, 2, 1, 2184, 0x05c7, 5, 19, 60, 32, 1, 0, 4, 0, 1, {0, 0, 0, 0, 0}},
+ {5, {0x2c, 0x84, 0xc4, 0x34, 0xaa, 0x00}, 4, 1, 32, 512, 2, 1, 2184, 0x05c7, 5, 19, 60, 32, 1, 0, 1, 0, 1, {0, 0, 0, 0, 0}},
+ {5, {0x2c, 0x84, 0x44, 0x34, 0xa4, 0x00}, 4, 1, 32, 512, 2, 1, 2184, 0x05c7, 5, 19, 60, 32, 1, 0, 1, 0, 1, {0, 0, 0, 0, 0}},
+ {5, {0x2c, 0x84, 0x64, 0x3c, 0xa9, 0x00}, 4, 1, 32, 512, 2, 2, 1024, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x2c, 0xa4, 0x64, 0x32, 0xaa, 0x04}, 4, 1, 32, 1024, 2, 1, 2192, 0x05c7, 10, 19, 60, 32, 1, 0, 4, 0, 1, {0, 0, 0, 0, 0}},
+ {6, {0xad, 0xde, 0x94, 0xd2, 0x04, 0x43}, 2, 1, 16, 256, 2, 2, 2048, 0x01d9, 1, 1, 24, 32, 4, 0, 3, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0xad, 0xd7, 0x94, 0xda, 0x74, 0xc3}, 2, 1, 16, 256, 2, 2, 1024, 0x01d9, 1, 2, 40, 32, 4, 0, 3, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0xad, 0xd7, 0x94, 0x91, 0x60, 0x44}, 2, 1, 16, 256, 2, 2, 1046, 0x01d9, 1, 3, 40, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4}, 2, 1, 16, 256, 2, 2, 2090, 0x01d9, 1, 4, 40, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0xad, 0xde, 0x94, 0xeb, 0x74, 0x44}, 2, 1, 32, 256, 2, 2, 1066, 0x01d9, 1, 7, 40, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0xad, 0xd5, 0x94, 0xda, 0x74, 0xc4}, 2, 1, 16, 256, 2, 2, 530, 0x01d9, 1, 3, 40, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0xad, 0xd7, 0x94, 0x9a, 0x74, 0x42}, 2, 1, 16, 256, 2, 2, 1024, 0x0119, 1, 0, 24, 32, 4, 0, 3, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0xad, 0xde, 0x14, 0xa7, 0x42, 0x4a}, 2, 1, 32, 256, 2, 2, 1060, 0x01d9, 2, 5, 40, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0xad, 0xd7, 0x14, 0x9e, 0x34, 0x4a}, 2, 1, 16, 256, 2, 2, 1056, 0x01d9, 2, 5, 40, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0xad, 0xde, 0x94, 0xa7, 0x42, 0x48}, 2, 1, 32, 256, 2, 2, 1060, 0x01d9, 2, 5, 40, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0xad, 0xde, 0x14, 0xab, 0x42, 0x4a}, 2, 1, 32, 256, 2, 2, 1056, 0x01d9, 2, 6, 40, 32, 3, 1, 3, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0xad, 0x3a, 0x14, 0xab, 0x42, 0x4a}, 2, 1, 32, 256, 2, 2, 2092, 0x01d9, 2, 5, 40, 32, 3, 1, 3, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0xad, 0xd5, 0x94, 0x9a, 0x74, 0x42}, 2, 1, 16, 256, 2, 1, 1024, 0x0111, 1, 0, 24, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0xad, 0x3a, 0x14, 0x03, 0x08, 0x50}, 2, 1, 32, 388, 2, 2, 1362, 0x01d9, 9, 8, 40, 32, 3, 1, 3, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x89, 0x64, 0x44, 0x4b, 0xa9, 0x00}, 7, 1, 16, 256, 2, 2, 2048, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x89, 0x88, 0x24, 0x4b, 0xa9, 0x84}, 7, 1, 16, 256, 2, 2, 2048, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x89, 0x88, 0x24, 0x4b, 0xa9, 0x00}, 7, 1, 16, 256, 2, 2, 2048, 0x0117, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x89, 0x68, 0x24, 0x4a, 0xa9, 0x00}, 7, 1, 8, 256, 2, 2, 2048, 0x0117, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x89, 0x68, 0x04, 0x4a, 0xa9, 0x00}, 7, 1, 8, 256, 2, 2, 2048, 0x0117, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x89, 0xd7, 0x94, 0x3e, 0x84, 0x00}, 7, 1, 8, 256, 2, 2, 2048, 0x0117, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x89, 0x68, 0x04, 0x46, 0xa9, 0x00}, 7, 1, 8, 256, 2, 2, 2048, 0x0117, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {5, {0x89, 0x64, 0x64, 0x3c, 0xa1, 0x00}, 7, 1, 32, 512, 2, 1, 1024, 0x01c7, 4, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {5, {0x89, 0x84, 0x64, 0x3c, 0xa5, 0x00}, 7, 1, 32, 512, 2, 2, 1024, 0x01c7, 4, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x89, 0x88, 0x24, 0x3b, 0xa9, 0x00}, 7, 1, 16, 192, 2, 2, 2048, 0x0117, 12, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x98, 0xd7, 0x84, 0x93, 0x72, 0x57}, 1, 1, 32, 256, 2, 1, 1060, 0x05c1, 2, 33, 40, 32, 2, 1, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x98, 0xde, 0x84, 0x93, 0x72, 0x57}, 1, 1, 32, 256, 2, 1, 2092, 0x05c1, 2, 33, 40, 32, 2, 1, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x98, 0x3a, 0x85, 0x93, 0x76, 0x57}, 1, 2, 32, 256, 2, 1, 2092, 0x05e1, 2, 33, 40, 32, 2, 1, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x98, 0xd5, 0x84, 0x32, 0x72, 0x56}, 1, 1, 16, 128, 2, 1, 2056, 0x05c1, 2, 33, 40, 32, 2, 1, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x98, 0xd7, 0x94, 0x32, 0x76, 0x56}, 1, 1, 16, 128, 2, 2, 2058, 0x05d1, 2, 33, 40, 32, 2, 1, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x98, 0xde, 0x94, 0x82, 0x76, 0x56}, 1, 1, 16, 256, 2, 2, 2062, 0x05d1, 1, 33, 40, 32, 2, 1, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x98, 0xde, 0x94, 0x93, 0x76, 0x50}, 1, 1, 32, 256, 2, 2, 1066, 0x05d9, 2, 34, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x98, 0x3a, 0x95, 0x93, 0x7a, 0x50}, 1, 2, 32, 256, 2, 2, 1066, 0x05d9, 2, 34, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x98, 0xd7, 0x94, 0x32, 0x76, 0x55}, 1, 1, 16, 128, 2, 2, 2050, 0x0191, 2, 0, 24, 32, 1, 1, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x98, 0xde, 0x94, 0x93, 0x76, 0x57}, 1, 1, 32, 256, 2, 2, 1058, 0x05d9, 2, 33, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x98, 0xd7, 0x84, 0x93, 0x72, 0x50}, 1, 1, 32, 256, 2, 1, 1060, 0x05c1, 2, 34, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x98, 0xde, 0x94, 0x93, 0x76, 0x51}, 1, 1, 32, 256, 2, 2, 1074, 0x05d9, 2, 35, 40, 32, 3, 1, 4, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x98, 0x3a, 0x94, 0x93, 0x76, 0x51}, 1, 1, 32, 256, 2, 2, 2106, 0x05d9, 2, 35, 40, 32, 3, 1, 4, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x98, 0xd7, 0x84, 0x93, 0x72, 0x51}, 1, 1, 32, 256, 2, 1, 1056, 0x05d9, 2, 35, 40, 32, 3, 1, 4, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x98, 0xde, 0x94, 0x93, 0x76, 0xd1}, 1, 1, 32, 256, 2, 2, 1074, 0x05d9, 2, 35, 40, 32, 3, 1, 4, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x45, 0xde, 0x94, 0x93, 0x76, 0x57}, 8, 1, 32, 256, 2, 2, 1058, 0x05d9, 2, 66, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x45, 0xd7, 0x84, 0x93, 0x72, 0x57}, 8, 1, 32, 256, 2, 1, 1060, 0x05c1, 2, 66, 40, 32, 2, 1, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x45, 0xde, 0xa4, 0x82, 0x76, 0x56}, 8, 1, 16, 256, 2, 2, 2082, 0x01d9, 1, 65, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x45, 0xde, 0x94, 0x93, 0x76, 0x50}, 8, 1, 32, 256, 2, 2, 1066, 0x05d9, 2, 67, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x45, 0xd7, 0x84, 0x93, 0x72, 0x50}, 8, 1, 32, 256, 2, 1, 1060, 0x05c1, 2, 67, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x45, 0xde, 0xa4, 0x82, 0x76, 0xd7}, 8, 1, 16, 256, 2, 2, 2090, 0x04d9, 1, 66, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x45, 0xde, 0x84, 0x93, 0x72, 0x57}, 8, 1, 32, 256, 2, 1, 2092, 0x05c1, 2, 66, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x45, 0x3a, 0x94, 0x93, 0x76, 0x51}, 8, 1, 32, 256, 2, 2, 2106, 0x01d9, 2, 68, 40, 32, 3, 1, 4, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x45, 0xde, 0x94, 0x93, 0x76, 0x51}, 8, 1, 32, 256, 2, 2, 1074, 0x01d9, 2, 68, 40, 32, 3, 1, 4, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x45, 0x3a, 0xa4, 0x93, 0x7a, 0x50}, 8, 1, 32, 256, 2, 2, 2138, 0x05d9, 2, 0, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x45, 0xde, 0x94, 0x82, 0x76, 0x56}, 8, 1, 16, 256, 2, 2, 2062, 0x01d9, 1, 0, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0x45, 0xde, 0x94, 0x93, 0x76, 0xd7}, 8, 1, 32, 256, 2, 2, 1058, 0x05d9, 2, 66, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0xec, 0xd7, 0x94, 0x7e, 0x64, 0x44}, 0, 1, 16, 128, 2, 2, 2048, 0x01d9, 2, 49, 60, 36, 3, 0, 3, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0xec, 0xde, 0xd5, 0x7e, 0x68, 0x44}, 0, 2, 16, 128, 2, 2, 2048, 0x01f9, 2, 49, 60, 36, 3, 0, 3, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0xec, 0xd7, 0x94, 0x7a, 0x54, 0x43}, 0, 1, 16, 128, 2, 2, 2076, 0x0199, 2, 0, 40, 36, 3, 1, 3, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0xec, 0xde, 0xd5, 0x7a, 0x58, 0x43}, 0, 2, 16, 128, 2, 2, 2076, 0x01b9, 2, 0, 40, 36, 3, 1, 3, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0xec, 0xd5, 0x94, 0x76, 0x54, 0x43}, 0, 1, 16, 128, 2, 2, 1038, 0x0119, 2, 0, 24, 36, 3, 1, 3, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0xec, 0xd7, 0x14, 0x76, 0x54, 0xc2}, 0, 1, 16, 128, 2, 2, 2076, 0x0491, 2, 0, 24, 40, 3, 1, 3, 0, 0, {0, 0, 0, 0, 0}},
+ {6, {0xec, 0xde, 0x94, 0xc3, 0xa4, 0xca}, 0, 1, 32, 792, 2, 1, 688, 0x04c1, 11, 50, 40, 32, 3, 1, 1, 0, 1, {0, 0, 0, 0, 0}},
+};
+
+#if !IS_ENABLED(CONFIG_SANDBOX)
+static int rkmtd_write_oob(struct rkmtd_dev *plat, ulong off, u_char *datbuf, u_char *oobbuf)
+{
+ struct mtd_info *mtd = plat->mtd;
+ struct mtd_oob_ops ops;
+ loff_t addr;
+ int ret;
+
+ off &= ~(mtd->writesize - 1);
+ addr = (loff_t)off;
+
+ memset(&ops, 0, sizeof(ops));
+ ops.datbuf = datbuf;
+ ops.oobbuf = oobbuf;
+ ops.len = mtd->writesize;
+ ops.ooblen = mtd->oobsize;
+ ops.mode = MTD_OPS_PLACE_OOB;
+ ret = mtd_write_oob(mtd, addr, &ops);
+ if (ret < 0) {
+ debug("Error (%d) writing page %08lx\n", ret, off);
+ return 1;
+ }
+
+ return 0;
+}
+
+static int rkmtd_read_oob(struct rkmtd_dev *plat, ulong off, u_char *datbuf, u_char *oobbuf)
+{
+ struct mtd_info *mtd = plat->mtd;
+ struct mtd_oob_ops ops;
+ loff_t addr;
+ int ret;
+
+ off &= ~(mtd->writesize - 1);
+ addr = (loff_t)off;
+
+ memset(&ops, 0, sizeof(ops));
+ ops.datbuf = datbuf;
+ ops.oobbuf = oobbuf;
+ ops.len = mtd->writesize;
+ ops.ooblen = mtd->oobsize;
+ ops.mode = MTD_OPS_PLACE_OOB;
+ ret = mtd_read_oob(mtd, addr, &ops);
+ if (ret < 0) {
+ debug("Error (%d) reading page %08lx\n", ret, off);
+ return 1;
+ }
+
+ return 0;
+}
+
+static int rkmtd_erase(struct rkmtd_dev *plat, ulong off)
+{
+ struct mtd_info *mtd = plat->mtd;
+ struct erase_info info;
+ loff_t addr;
+ int ret;
+
+ off &= ~(mtd->writesize - 1);
+ addr = (loff_t)off;
+
+ memset(&info, 0, sizeof(info));
+ info.mtd = mtd;
+ info.addr = addr;
+ info.len = mtd->erasesize;
+ info.scrub = 1;
+ ret = mtd_erase(mtd, &info);
+ if (ret) {
+ debug("Error (%d) erasing page %08lx\n", ret, off);
+ return 1;
+ }
+
+ return 0;
+}
+#endif
+void rkmtd_scan_block(struct rkmtd_dev *plat)
+{
+ plat->blk_counter = 0;
+
+#if !IS_ENABLED(CONFIG_SANDBOX)
+ u32 blk;
+
+ for (blk = 0; blk < plat->boot_blks; blk++) {
+ rkmtd_read_oob(plat, blk * plat->mtd->erasesize, plat->datbuf, plat->oobbuf);
+ if (*(u32 *)plat->datbuf == RK_TAG) {
+ struct sector0 *sec0 = (struct sector0 *)plat->datbuf;
+
+ rkmtd_rc4(plat->datbuf, 512);
+
+ plat->idblock[plat->blk_counter].blk = blk;
+ plat->idblock[plat->blk_counter].offset = sec0->boot_code1_offset;
+ plat->idblock[plat->blk_counter].boot_size = sec0->flash_boot_size;
+
+ debug("\nblk : %d\n", plat->idblock[plat->blk_counter].blk);
+ debug("offset : %d\n", plat->idblock[plat->blk_counter].offset);
+ debug("boot_size : %d\n", plat->idblock[plat->blk_counter].boot_size);
+
+ plat->blk_counter += 1;
+
+ if (plat->blk_counter >= ARRAY_SIZE(plat->idblock))
+ return;
+ }
+ }
+#endif
+}
+
+void rkmtd_read_block(struct rkmtd_dev *plat, u32 idx, u8 *buf)
+{
+#if !IS_ENABLED(CONFIG_SANDBOX)
+ ulong off = plat->idblock[idx].blk * plat->mtd->erasesize;
+ struct nand_chip *chip = mtd_to_nand(plat->mtd);
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int counter = 0;
+ u32 spare0 = 0;
+ u32 *p_spare;
+ int sector;
+ int page;
+
+ rkmtd_read_oob(plat, off,
+ plat->datbuf, plat->oobbuf);
+
+ memcpy(buf, plat->datbuf, BLK_SIZE);
+
+ while (counter < plat->idblock[idx].boot_size) {
+ if (spare0)
+ page = (plat->idblock[idx].offset + spare0) / 4;
+ else
+ page = (plat->idblock[idx].offset + counter) / 4;
+
+ rkmtd_read_oob(plat,
+ off + page * plat->mtd->writesize,
+ plat->datbuf, plat->oobbuf);
+
+ sector = plat->idblock[idx].offset + counter;
+
+ memcpy(&buf[(sector / 4) * BLK_SIZE], plat->datbuf, BLK_SIZE);
+
+ p_spare = (u32 *)&plat->oobbuf[(ecc->steps - 1) * NFC_SYS_DATA_SIZE];
+
+ spare0 = *p_spare;
+ if (spare0 == -1)
+ break;
+
+ counter += 4;
+ }
+#endif
+}
+
+void rkmtd_write_block(struct rkmtd_dev *plat, u32 idx, u8 *buf)
+{
+#if !IS_ENABLED(CONFIG_SANDBOX)
+ ulong off = plat->idblock[idx].blk * plat->mtd->erasesize;
+ struct nand_chip *chip = mtd_to_nand(plat->mtd);
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int counter = 0;
+ u32 *p_spare;
+ int sector;
+ int page;
+ int j, w, r;
+
+ rkmtd_erase(plat, off);
+
+ memset(plat->datbuf, 0xff, plat->mtd->writesize);
+ memcpy(plat->datbuf, buf, BLK_SIZE);
+ memset(plat->oobbuf, 0xff, plat->mtd->oobsize);
+
+ rkmtd_write_oob(plat, off,
+ plat->datbuf, plat->oobbuf);
+
+ while (counter < plat->idblock[idx].boot_size) {
+ sector = plat->idblock[idx].offset + counter;
+
+ memset(plat->datbuf, 0xff, plat->mtd->writesize);
+ memcpy(plat->datbuf, &buf[(sector / 4) * BLK_SIZE], BLK_SIZE);
+ memset(plat->oobbuf, 0xff, plat->mtd->oobsize);
+
+ p_spare = (u32 *)&plat->oobbuf[(ecc->steps - 1) * NFC_SYS_DATA_SIZE];
+
+ *p_spare = (plat->page_table[sector / 4 + 1] - 1) * 4;
+
+ page = plat->page_table[sector / 4];
+
+ rkmtd_write_oob(plat,
+ off + page * plat->mtd->writesize,
+ plat->datbuf, plat->oobbuf);
+
+ counter += 4;
+ }
+
+ memset(plat->check, 0, BUF_SIZE);
+ rkmtd_read_block(plat, idx, plat->check);
+
+ for (j = 0; j < BLK_SIZE; j++) {
+ w = *(buf + j);
+ r = *(plat->check + j);
+
+ if (r != w)
+ goto dumpblock;
+ }
+
+ for (j = 0; j < (plat->idblock[idx].boot_size * 512); j++) {
+ w = *(buf + plat->idblock[idx].offset * 512 + j);
+ r = *(plat->check + plat->idblock[idx].offset * 512 + j);
+
+ if (r != w)
+ goto dumpblock;
+ }
+
+ debug("write OK\n");
+ return;
+
+dumpblock:
+ debug("write and check error:%x r=%x w=%x\n", j, r, w);
+
+ plat->idblock[idx].offset = 0;
+ plat->idblock[idx].boot_size = 0;
+
+ memset(plat->datbuf, 0xff, plat->mtd->writesize);
+ memset(plat->datbuf, 0, BLK_SIZE);
+ memset(plat->oobbuf, 0xff, plat->mtd->oobsize);
+
+ rkmtd_write_oob(plat, off, plat->datbuf, plat->oobbuf);
+#endif
+}
+
+ulong rkmtd_bread(struct udevice *udev, lbaint_t start,
+ lbaint_t blkcnt, void *dst)
+{
+ struct blk_desc *block_dev = dev_get_uclass_plat(udev);
+ struct udevice *parent_dev = dev_get_parent(udev);
+ struct rkmtd_dev *plat = dev_get_plat(parent_dev);
+ char *buf = dst;
+ int i;
+
+ if (blkcnt == 0)
+ return 0;
+
+ if (start > (block_dev->lba - 1) ||
+ (start + blkcnt) > block_dev->lba)
+ return 0;
+
+ memset(dst, 0, blkcnt * block_dev->blksz);
+
+ for (i = start; i < (start + blkcnt); i++) {
+ if (i == 0) {
+ debug("mbr : %d\n", i);
+
+ memcpy(&buf[(i - start) * block_dev->blksz],
+ plat->mbr, sizeof(legacy_mbr));
+ } else if (i == 1) {
+ debug("gpt_h : %d\n", i);
+
+ memcpy(&buf[(i - start) * block_dev->blksz],
+ plat->gpt_h, sizeof(gpt_header));
+ } else if (i == (block_dev->lba - 1)) {
+ debug("gpt_h2 : %d\n", i);
+
+ memcpy(&buf[(i - start) * block_dev->blksz],
+ plat->gpt_h2, sizeof(gpt_header));
+ } else if (i == 2 || i == (block_dev->lba - 33)) {
+ debug("gpt_e : %d\n", i);
+
+ memcpy(&buf[(i - start) * block_dev->blksz],
+ plat->gpt_e, sizeof(gpt_entry));
+ } else if (i >= 64 && i < (block_dev->lba - 33)) {
+ debug("rd : %d\n", i);
+
+ memcpy(&buf[(i - start) * block_dev->blksz],
+ &plat->idb[(i - 64) * block_dev->blksz], block_dev->blksz);
+ }
+ }
+
+ return blkcnt;
+}
+
+ulong rkmtd_bwrite(struct udevice *udev, lbaint_t start,
+ lbaint_t blkcnt, const void *src)
+{
+ struct blk_desc *block_dev = dev_get_uclass_plat(udev);
+ struct udevice *parent_dev = dev_get_parent(udev);
+ struct rkmtd_dev *plat = dev_get_plat(parent_dev);
+ struct sector0 *sec0;
+ int i, j;
+
+ if (blkcnt == 0)
+ return 0;
+
+ if (start > (block_dev->lba - 1) ||
+ (start + blkcnt) > block_dev->lba)
+ return 0;
+
+ for (i = start; i < (start + blkcnt); i++) {
+ debug("wr : %d\n", i);
+
+ if (i >= 64 && i < (block_dev->lba - 33)) {
+ if (i == 64) {
+ debug("first block\n");
+
+ plat->idb_need_write_back = 1;
+ memset(plat->idb, 0, BUF_SIZE);
+ }
+
+ if (plat->idb_need_write_back) {
+ char *buf = (char *)src;
+
+ memcpy(&plat->idb[(i - 64) * block_dev->blksz],
+ &buf[(i - start) * block_dev->blksz],
+ block_dev->blksz);
+
+ if (i == 64) {
+ memcpy(plat->check, plat->idb, 512);
+
+ if (*(u32 *)plat->check == RK_TAG) {
+ rkmtd_rc4(plat->check, 512);
+
+ sec0 = (struct sector0 *)plat->check;
+ plat->offset = sec0->boot_code1_offset;
+ plat->boot_size = sec0->flash_boot_size;
+
+ if (plat->offset + plat->boot_size > 512) {
+ debug("max size limit\n");
+ plat->idb_need_write_back = 0;
+ }
+ } else {
+ debug("no IDB block found\n");
+ plat->idb_need_write_back = 0;
+ }
+ }
+
+ if (i == (64 + plat->offset + plat->boot_size - 1)) {
+ debug("last block\n");
+
+ plat->idb_need_write_back = 0;
+
+ if (!plat->blk_counter) {
+ plat->idblock[0].blk = 2;
+ plat->idblock[1].blk = 3;
+ plat->idblock[2].blk = 4;
+ plat->idblock[3].blk = 5;
+ plat->idblock[4].blk = 6;
+ plat->blk_counter = 5;
+ }
+
+ for (j = 0; j < plat->blk_counter; j++) {
+ if (plat->idblock[j].blk < plat->boot_blks) {
+ plat->idblock[j].offset = plat->offset;
+ plat->idblock[j].boot_size = plat->boot_size;
+ rkmtd_write_block(plat, j, plat->idb);
+ }
+ }
+
+ rkmtd_scan_block(plat);
+
+ if (!IS_ENABLED(CONFIG_SANDBOX))
+ memset(plat->idb, 0, BUF_SIZE);
+
+ if (plat->blk_counter)
+ rkmtd_read_block(plat, 0, plat->idb);
+ }
+ }
+ } else if (plat->idb_need_write_back) {
+ plat->idb_need_write_back = 0;
+
+ memset(plat->idb, 0, BUF_SIZE);
+
+ if (plat->blk_counter)
+ rkmtd_read_block(plat, 0, plat->idb);
+ }
+ }
+
+ return blkcnt;
+}
+
+static const struct blk_ops rkmtd_blk_ops = {
+ .read = rkmtd_bread,
+ .write = rkmtd_bwrite,
+};
+
+U_BOOT_DRIVER(rkmtd_blk) = {
+ .name = "rkmtd_blk",
+ .id = UCLASS_BLK,
+ .ops = &rkmtd_blk_ops,
+};
+
+void rkmtd_build_page_table(struct rkmtd_dev *plat)
+{
+ u32 counter;
+ u32 counter2;
+
+ switch (plat->lsb_mode) {
+ case 0:
+ counter = 0;
+ do {
+ u16 val = counter;
+
+ plat->page_table[counter++] = val;
+ } while (counter != 512);
+ break;
+ case 1:
+ counter = 0;
+ do {
+ u16 val = counter;
+
+ if (counter > 3) {
+ u16 offset;
+
+ if (counter & 1)
+ offset = 3;
+ else
+ offset = 2;
+ val = 2 * counter - offset;
+ }
+ plat->page_table[counter++] = val;
+ } while (counter != 512);
+ break;
+ case 2:
+ counter = 0;
+ do {
+ u16 val = counter;
+
+ if (counter > 1)
+ val = 2 * counter - 1;
+ plat->page_table[counter++] = val;
+ } while (counter != 512);
+ break;
+ case 3:
+ counter = 0;
+ do {
+ u16 val = counter;
+
+ if (counter > 5) {
+ u16 offset;
+
+ if (counter & 1)
+ offset = 5;
+ else
+ offset = 4;
+ val = 2 * counter - offset;
+ }
+ plat->page_table[counter++] = val;
+ } while (counter != 512);
+ break;
+ case 4:
+ counter = 8;
+ plat->page_table[0] = 0;
+ plat->page_table[1] = 1;
+ plat->page_table[2] = 2;
+ plat->page_table[3] = 3;
+ plat->page_table[4] = 4;
+ plat->page_table[5] = 5;
+ plat->page_table[6] = 7;
+ plat->page_table[7] = 8;
+ do {
+ u32 offset;
+ u32 val;
+
+ if (counter & 1)
+ offset = 7;
+ else
+ offset = 6;
+ val = 2 * counter - offset;
+ plat->page_table[counter++] = val;
+ } while (counter != 512);
+ break;
+ case 5:
+ counter = 0;
+ counter2 = 16;
+ do {
+ u16 val = counter;
+
+ plat->page_table[counter++] = val;
+ } while (counter != 16);
+ do {
+ plat->page_table[counter++] = counter2;
+ counter2 = counter2 + 2;
+ } while (counter != 512);
+ break;
+ case 6:
+ counter = 0;
+ counter2 = 0;
+ do {
+ u16 val = counter;
+
+ if (counter > 5) {
+ u16 offset;
+
+ if (counter & 1)
+ offset = 12;
+ else
+ offset = 10;
+ val = counter2 - offset;
+ }
+ plat->page_table[counter++] = val;
+ counter2 = counter2 + 3;
+ } while (counter != 512);
+ break;
+ case 9:
+ counter = 3;
+ counter2 = 3;
+ plat->page_table[0] = 0;
+ plat->page_table[1] = 1;
+ plat->page_table[2] = 2;
+ do {
+ plat->page_table[counter++] = counter2;
+ counter2 = counter2 + 2;
+ } while (counter != 512);
+ break;
+ case 10:
+ counter = 0;
+ counter2 = 63;
+ do {
+ u16 val = counter;
+
+ plat->page_table[counter++] = val;
+ } while (counter != 63);
+ do {
+ plat->page_table[counter++] = counter2;
+ counter2 = counter2 + 2;
+ } while (counter != 512);
+ break;
+ case 11:
+ counter = 0;
+ do {
+ u16 val = counter;
+
+ plat->page_table[counter++] = val;
+ } while (counter != 8);
+ do {
+ u32 offset;
+ u32 val;
+
+ if (counter & 1)
+ offset = 7;
+ else
+ offset = 6;
+ val = 2 * counter - offset;
+ plat->page_table[counter++] = val;
+ } while (counter != 512);
+ break;
+ case 12:
+ counter = 4;
+ plat->page_table[0] = 0;
+ plat->page_table[1] = 1;
+ plat->page_table[2] = 2;
+ plat->page_table[3] = 3;
+ do {
+ u32 val = counter - 1 + (counter >> 1);
+
+ plat->page_table[counter++] = val;
+ } while (counter != 512);
+ break;
+ }
+}
+
+static inline u32 efi_crc32(const void *buf, u32 len)
+{
+ return crc32(0, buf, len);
+}
+
+int rkmtd_init_plat(struct udevice *dev)
+{
+ static const efi_guid_t partition_basic_data_guid = PARTITION_BASIC_DATA_GUID;
+ struct rkmtd_dev *plat = dev_get_plat(dev);
+ size_t efiname_len, dosname_len;
+ uchar name[] = "loader1";
+ u32 calc_crc32;
+ int k;
+
+ gen_rand_uuid_str(plat->uuid_disk_str, UUID_STR_FORMAT_GUID);
+ gen_rand_uuid_str(plat->uuid_part_str, UUID_STR_FORMAT_GUID);
+
+ debug("uuid_part_str : %s\n", plat->uuid_part_str);
+ debug("uuid_disk_str : %s\n", plat->uuid_disk_str);
+
+ plat->idb = devm_kzalloc(plat->dev, BUF_SIZE, GFP_KERNEL);
+ if (!plat->idb)
+ return -ENOMEM;
+
+ plat->check = devm_kzalloc(plat->dev, BUF_SIZE, GFP_KERNEL);
+ if (!plat->check)
+ return -ENOMEM;
+
+ plat->mbr = devm_kzalloc(plat->dev, sizeof(legacy_mbr), GFP_KERNEL);
+ if (!plat->mbr)
+ return -ENOMEM;
+
+ plat->gpt_e = devm_kzalloc(plat->dev, sizeof(gpt_entry), GFP_KERNEL);
+ if (!plat->gpt_e)
+ return -ENOMEM;
+
+ plat->gpt_h = devm_kzalloc(plat->dev, sizeof(gpt_header), GFP_KERNEL);
+ if (!plat->gpt_h)
+ return -ENOMEM;
+
+ plat->gpt_h2 = devm_kzalloc(plat->dev, sizeof(gpt_header), GFP_KERNEL);
+ if (!plat->gpt_h2)
+ return -ENOMEM;
+
+ /* Init mbr */
+ plat->mbr->signature = MSDOS_MBR_SIGNATURE;
+ plat->mbr->partition_record[0].sys_ind = EFI_PMBR_OSTYPE_EFI_GPT;
+ plat->mbr->partition_record[0].start_sect = 1;
+ plat->mbr->partition_record[0].nr_sects = LBA - 1;
+
+ /* Init gpt_e */
+ plat->gpt_e->starting_lba = cpu_to_le64(64);
+ plat->gpt_e->ending_lba = cpu_to_le64(LBA - 34);
+
+ debug("starting_lba : %llu\n", le64_to_cpu(plat->gpt_e->starting_lba));
+ debug("ending_lba : %llu\n", le64_to_cpu(plat->gpt_e->ending_lba));
+
+ memcpy(plat->gpt_e->partition_type_guid.b, &partition_basic_data_guid, 16);
+
+ uuid_str_to_bin(plat->uuid_part_str, plat->gpt_e->unique_partition_guid.b,
+ UUID_STR_FORMAT_GUID);
+
+ efiname_len = sizeof(plat->gpt_e->partition_name) / sizeof(efi_char16_t);
+ dosname_len = sizeof(name);
+
+ for (k = 0; k < min(dosname_len, efiname_len); k++)
+ plat->gpt_e->partition_name[k] = (efi_char16_t)(name[k]);
+
+ /* Init gpt_h */
+ plat->gpt_h->signature = cpu_to_le64(GPT_HEADER_SIGNATURE_UBOOT);
+ plat->gpt_h->revision = cpu_to_le32(GPT_HEADER_REVISION_V1);
+ plat->gpt_h->header_size = cpu_to_le32(sizeof(gpt_header));
+ plat->gpt_h->first_usable_lba = cpu_to_le64(64);
+ plat->gpt_h->last_usable_lba = cpu_to_le64(LBA - 34);
+ plat->gpt_h->num_partition_entries = cpu_to_le32(1);
+ plat->gpt_h->sizeof_partition_entry = cpu_to_le32(sizeof(gpt_entry));
+
+ uuid_str_to_bin(plat->uuid_disk_str, plat->gpt_h->disk_guid.b,
+ UUID_STR_FORMAT_GUID);
+
+ plat->gpt_h->partition_entry_array_crc32 = 0;
+ calc_crc32 = efi_crc32((const unsigned char *)plat->gpt_e,
+ le32_to_cpu(plat->gpt_h->num_partition_entries) *
+ le32_to_cpu(plat->gpt_h->sizeof_partition_entry));
+ plat->gpt_h->partition_entry_array_crc32 = cpu_to_le32(calc_crc32);
+
+ debug("partition crc32 : 0x%08x\n", calc_crc32);
+
+ plat->gpt_h->my_lba = cpu_to_le64(1);
+ plat->gpt_h->partition_entry_lba = cpu_to_le64(2);
+ plat->gpt_h->alternate_lba = cpu_to_le64(LBA - 1);
+
+ plat->gpt_h->header_crc32 = 0;
+ calc_crc32 = efi_crc32((const unsigned char *)plat->gpt_h,
+ le32_to_cpu(plat->gpt_h->header_size));
+ plat->gpt_h->header_crc32 = cpu_to_le32(calc_crc32);
+
+ debug("header h1 crc32 : 0x%08x\n", calc_crc32);
+
+ /* Init gpt_h2 */
+ memcpy(plat->gpt_h2, plat->gpt_h, sizeof(gpt_header));
+
+ plat->gpt_h2->my_lba = cpu_to_le64(LBA - 1);
+ plat->gpt_h2->partition_entry_lba =
+ cpu_to_le64(le64_to_cpu(plat->gpt_h2->last_usable_lba) + 1);
+ plat->gpt_h2->alternate_lba = cpu_to_le64(1);
+
+ plat->gpt_h2->header_crc32 = 0;
+ calc_crc32 = efi_crc32((const unsigned char *)plat->gpt_h2,
+ le32_to_cpu(plat->gpt_h2->header_size));
+ plat->gpt_h2->header_crc32 = cpu_to_le32(calc_crc32);
+
+ debug("header h2 crc32 : 0x%08x\n", calc_crc32);
+
+ part_init(plat->desc);
+
+ return 0;
+}
+
+static void rkmtd_blk_kmalloc_release(struct udevice *dev, void *res)
+{
+ /* noop */
+}
+
+static int rkmtd_bind(struct udevice *dev)
+{
+ struct rkmtd_dev *plat = dev_get_plat(dev);
+ char dev_name[30], *str;
+ struct blk_desc *desc;
+ struct udevice *bdev;
+ int ret;
+
+ snprintf(dev_name, sizeof(dev_name), "%s.%s", dev->name, "blk");
+
+ str = devres_alloc(rkmtd_blk_kmalloc_release, strlen(dev_name) + 1, GFP_KERNEL);
+ if (unlikely(!str))
+ return -ENOMEM;
+
+ strcpy(str, dev_name);
+
+ ret = blk_create_device(dev, "rkmtd_blk", str, UCLASS_RKMTD,
+ -1, 512, LBA, &bdev);
+ if (ret) {
+ free(str);
+ return log_msg_ret("blk", ret);
+ }
+
+ devres_add(dev, str);
+
+ desc = dev_get_uclass_plat(bdev);
+ sprintf(desc->vendor, "0x%.4x", 0x2207);
+ memcpy(desc->product, "RKMTD", sizeof("RKMTD"));
+ memcpy(desc->revision, "V1.00", sizeof("V1.00"));
+ plat->desc = desc;
+
+ return 0;
+}
+
+static int rkmtd_attach_mtd(struct udevice *dev)
+{
+ struct rkmtd_dev *plat = dev_get_plat(dev);
+ struct mtd_info *mtd;
+ struct udevice *blk;
+ int ret;
+
+ plat->dev = dev;
+
+ /* Sanity check that rkmtd_bind() has been used */
+ ret = blk_find_from_parent(dev, &blk);
+ if (ret)
+ return ret;
+
+#if IS_ENABLED(CONFIG_SANDBOX)
+ plat->mtd = devm_kzalloc(dev, sizeof(struct mtd_info), GFP_KERNEL);
+ if (!plat->mtd)
+ return -ENOMEM;
+
+ mtd = plat->mtd;
+ mtd->erasesize = 2 ^ 3 * BLK_SIZE;
+ mtd->writesize = BLK_SIZE;
+ mtd->oobsize = BLK_SIZE / STEP_SIZE * NFC_SYS_DATA_SIZE;
+ plat->boot_blks = 0;
+ plat->lsb_mode = 0;
+#else
+ struct nand_chip *chip;
+ u8 id[6];
+ int i, j;
+ u32 tmp;
+
+ mtd = get_nand_dev_by_index(0);
+ if (!mtd)
+ return -ENOSYS;
+
+ chip = mtd_to_nand(mtd);
+
+ ret = ofnode_read_u32(chip->flash_node, "rockchip,boot-blks", &tmp);
+ plat->boot_blks = ret ? 0 : tmp;
+ plat->mtd = mtd;
+
+ if (chip->select_chip)
+ chip->select_chip(mtd, 0);
+
+ nand_readid_op(chip, 0, id, 6);
+
+ if (chip->select_chip)
+ chip->select_chip(mtd, -1);
+
+ for (i = 0; i < ARRAY_SIZE(nand_para_tbl); i++) {
+ plat->info = (struct nand_para_info *)&nand_para_tbl[i];
+ for (j = 0; j < plat->info->id_bytes; j++) {
+ if (plat->info->nand_id[j] != id[j])
+ break;
+ if (j == plat->info->id_bytes - 1)
+ goto valid;
+ }
+ }
+
+ debug("no nand_para_info found\n");
+ return -ENODEV;
+valid:
+ plat->lsb_mode = plat->info->lsb_mode;
+
+ debug("FLASH ID :");
+
+ for (j = 0; j < plat->info->id_bytes; j++)
+ debug(" %x", id[j]);
+
+ debug("\n");
+#endif
+
+ rkmtd_build_page_table(plat);
+
+ plat->datbuf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);
+ if (!plat->datbuf)
+ return -ENOMEM;
+
+ plat->oobbuf = devm_kzalloc(dev, mtd->oobsize, GFP_KERNEL);
+ if (!plat->oobbuf)
+ return -ENOMEM;
+
+ debug("erasesize %8d\n", mtd->erasesize);
+ debug("writesize %8d\n", mtd->writesize);
+ debug("oobsize %8d\n", mtd->oobsize);
+ debug("boot_blks %8d\n", plat->boot_blks);
+ debug("lsb_mode %8d\n", plat->lsb_mode);
+
+ ret = rkmtd_init_plat(dev);
+ if (ret) {
+ debug("rkmtd_init_plat failed\n");
+ return -ENOENT;
+ }
+
+ rkmtd_scan_block(plat);
+
+ memset(plat->idb, 0, BUF_SIZE);
+
+ if (plat->blk_counter)
+ rkmtd_read_block(plat, 0, plat->idb);
+
+ return 0;
+}
+
+int rkmtd_detach_mtd(struct udevice *dev)
+{
+ int ret;
+
+ ret = device_remove(dev, DM_REMOVE_NORMAL);
+ if (ret)
+ return log_msg_ret("rem", ret);
+
+ ret = device_chld_unbind(dev, NULL);
+ if (ret)
+ return log_msg_ret("unb", ret);
+
+ return 0;
+}
+
+struct rkmtd_ops rkmtd_ops = {
+ .attach_mtd = rkmtd_attach_mtd,
+ .detach_mtd = rkmtd_detach_mtd,
+};
+
+U_BOOT_DRIVER(rkmtd_drv) = {
+ .name = "rkmtd_drv",
+ .id = UCLASS_RKMTD,
+ .ops = &rkmtd_ops,
+ .bind = rkmtd_bind,
+ .plat_auto = sizeof(struct rkmtd_dev),
+};
+
+struct rkmtd_priv {
+ struct udevice *cur_dev;
+};
+
+void rkmtd_rc4(u8 *buf, u32 len)
+{
+ u8 S[256], K[256], temp;
+ u32 i, j, t, x;
+ u8 key[16] = { 124, 78, 3, 4, 85, 5, 9, 7, 45, 44, 123, 56, 23, 13, 23, 17};
+
+ j = 0;
+ for (i = 0; i < 256; i++) {
+ S[i] = (u8)i;
+ j &= 0x0f;
+ K[i] = key[j];
+ j++;
+ }
+
+ j = 0;
+ for (i = 0; i < 256; i++) {
+ j = (j + S[i] + K[i]) % 256;
+ temp = S[i];
+ S[i] = S[j];
+ S[j] = temp;
+ }
+
+ i = 0;
+ j = 0;
+ for (x = 0; x < len; x++) {
+ i = (i + 1) % 256;
+ j = (j + S[i]) % 256;
+ temp = S[i];
+ S[i] = S[j];
+ S[j] = temp;
+ t = (S[i] + (S[j] % 256)) % 256;
+ buf[x] = buf[x] ^ S[t];
+ }
+}
+
+struct udevice *rkmtd_get_cur_dev(void)
+{
+ struct uclass *uc = uclass_find(UCLASS_RKMTD);
+
+ if (uc) {
+ struct rkmtd_priv *priv = uclass_get_priv(uc);
+
+ return priv->cur_dev;
+ }
+
+ return NULL;
+}
+
+void rkmtd_set_cur_dev(struct udevice *dev)
+{
+ struct uclass *uc = uclass_find(UCLASS_RKMTD);
+
+ if (uc) {
+ struct rkmtd_priv *priv = uclass_get_priv(uc);
+
+ priv->cur_dev = dev;
+ }
+}
+
+struct udevice *rkmtd_find_by_label(const char *label)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+
+ uclass_id_foreach_dev(UCLASS_RKMTD, dev, uc) {
+ struct rkmtd_dev *plat = dev_get_plat(dev);
+
+ if (plat->label && !strcmp(label, plat->label))
+ return dev;
+ }
+
+ return NULL;
+}
+
+int rkmtd_attach(struct udevice *dev)
+{
+ struct rkmtd_ops *ops = rkmtd_get_ops(dev);
+
+ if (!ops->attach_mtd)
+ return -ENOSYS;
+
+ return ops->attach_mtd(dev);
+}
+
+int rkmtd_detach(struct udevice *dev)
+{
+ struct rkmtd_ops *ops = rkmtd_get_ops(dev);
+
+ if (!ops->detach_mtd)
+ return -ENOSYS;
+
+ if (dev == rkmtd_get_cur_dev())
+ rkmtd_set_cur_dev(NULL);
+
+ return ops->detach_mtd(dev);
+}
+
+static void rkmtd_drv_kmalloc_release(struct udevice *dev, void *res)
+{
+ /* noop */
+}
+
+int rkmtd_create_device(const char *label, struct udevice **devp)
+{
+ char dev_name[30], *str, *label_new;
+ struct udevice *dev, *blk;
+ struct rkmtd_dev *plat;
+ int ret;
+
+ /* unbind any existing device with this label */
+ dev = rkmtd_find_by_label(label);
+ if (dev) {
+ ret = rkmtd_detach(dev);
+ if (ret)
+ return log_msg_ret("det", ret);
+
+ ret = device_unbind(dev);
+ if (ret)
+ return log_msg_ret("unb", ret);
+ }
+
+ snprintf(dev_name, sizeof(dev_name), "rkmtd-%s", label);
+
+ str = devres_alloc(rkmtd_drv_kmalloc_release, strlen(dev_name) + 1, GFP_KERNEL);
+ if (unlikely(!str))
+ return -ENOMEM;
+
+ strcpy(str, dev_name);
+
+ ret = device_bind_driver(dm_root(), "rkmtd_drv", str, &dev);
+ if (ret) {
+ free(str);
+ return log_msg_ret("drv", ret);
+ }
+
+ devres_add(dev, str);
+
+ if (!blk_find_from_parent(dev, &blk)) {
+ struct blk_desc *desc = dev_get_uclass_plat(blk);
+
+ desc->removable = true;
+ }
+
+ label_new = devm_kzalloc(dev, strlen(label) + 1, GFP_KERNEL);
+ if (!label_new)
+ return -ENOMEM;
+
+ strcpy(label_new, label);
+
+ plat = dev_get_plat(dev);
+ plat->label = label_new;
+ *devp = dev;
+
+ return 0;
+}
+
+int rkmtd_create_attach_mtd(const char *label, struct udevice **devp)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = rkmtd_create_device(label, &dev);
+ if (ret)
+ return log_msg_ret("cre", ret);
+
+ ret = rkmtd_attach(dev);
+ if (ret) {
+ device_unbind(dev);
+ return log_msg_ret("att", ret);
+ }
+ *devp = dev;
+
+ return 0;
+}
+
+UCLASS_DRIVER(rkmtd) = {
+ .name = "rkmtd",
+ .id = UCLASS_RKMTD,
+ .post_bind = dm_scan_fdt_dev,
+ .priv_auto = sizeof(struct rkmtd_priv),
+};
diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig
index 570252d..3c56253 100644
--- a/drivers/bootcount/Kconfig
+++ b/drivers/bootcount/Kconfig
@@ -79,14 +79,6 @@
Store the bootcount in DRAM protected against bit errors
due to short power loss or holding a system in RESET.
-config BOOTCOUNT_I2C
- bool "Boot counter on I2C device"
- help
- Enable support for the bootcounter on an i2c (like RTC) device.
- CFG_SYS_I2C_RTC_ADDR = i2c chip address
- CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for
- the bootcounter.
-
config BOOTCOUNT_AT91
bool "Boot counter for Atmel AT91SAM9XE"
depends on AT91SAM9XE
@@ -117,6 +109,16 @@
Accesses to the backing store are performed using the write16
and read16 ops of DM RTC devices.
+config DM_BOOTCOUNT_I2C
+ bool "Driver Model boot counter on I2C device"
+ depends on DM_I2C
+ help
+ Enable support for the bootcounter on a generic i2c device, like a RTC
+ or PMIC. The bootcounter is configured in the device tree using the
+ "u-boot,bootcount-i2c" compatible string. It requires a phandle
+ 'i2cbcdev' for the i2c device and an 'offset' property used within the
+ device.
+
config DM_BOOTCOUNT_I2C_EEPROM
bool "Support i2c eeprom devices as a backing store for bootcount"
depends on I2C_EEPROM
@@ -175,14 +177,6 @@
counter being cleared.
If set to 0, do not set a boot limit in the environment.
-config BOOTCOUNT_ALEN
- int "I2C address length"
- default 1
- depends on BOOTCOUNT_I2C
- help
- Length of the the I2C address at SYS_BOOTCOUNT_ADDR for storing
- the boot counter.
-
config SYS_BOOTCOUNT_SINGLEWORD
bool "Use single word to pack boot count and magic value"
depends on BOOTCOUNT_GENERIC
@@ -218,7 +212,7 @@
default 0x44E3E000 if BOOTCOUNT_AM33XX || BOOTCOUNT_AM33XX_NVMEM
default 0xE0115FF8 if ARCH_LS1043A || ARCH_LS1021A
depends on BOOTCOUNT_AM33XX || BOOTCOUNT_GENERIC || BOOTCOUNT_EXT || \
- BOOTCOUNT_I2C || BOOTCOUNT_AM33XX_NVMEM
+ BOOTCOUNT_AM33XX_NVMEM
help
Set the address used for reading and writing the boot counter.
@@ -226,13 +220,11 @@
hex "Magic value for the boot counter"
default 0xB001C041 if BOOTCOUNT_GENERIC || BOOTCOUNT_EXT || \
BOOTCOUNT_AM33XX || BOOTCOUNT_ENV || \
- BOOTCOUNT_RAM || BOOTCOUNT_I2C || \
- BOOTCOUNT_AT91 || DM_BOOTCOUNT
+ BOOTCOUNT_RAM || BOOTCOUNT_AT91 || DM_BOOTCOUNT
default 0xB0 if BOOTCOUNT_AM33XX_NVMEM
depends on BOOTCOUNT_GENERIC || BOOTCOUNT_EXT || \
BOOTCOUNT_AM33XX || BOOTCOUNT_ENV || \
- BOOTCOUNT_RAM || BOOTCOUNT_I2C || \
- BOOTCOUNT_AT91 || DM_BOOTCOUNT || \
+ BOOTCOUNT_RAM || BOOTCOUNT_AT91 || DM_BOOTCOUNT || \
BOOTCOUNT_AM33XX_NVMEM
help
Set the magic value used for the boot counter.
diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile
index b65959a..e7771f5 100644
--- a/drivers/bootcount/Makefile
+++ b/drivers/bootcount/Makefile
@@ -6,7 +6,6 @@
obj-$(CONFIG_BOOTCOUNT_AM33XX) += bootcount_davinci.o
obj-$(CONFIG_BOOTCOUNT_RAM) += bootcount_ram.o
obj-$(CONFIG_BOOTCOUNT_ENV) += bootcount_env.o
-obj-$(CONFIG_BOOTCOUNT_I2C) += bootcount_i2c.o
obj-$(CONFIG_BOOTCOUNT_EXT) += bootcount_ext.o
obj-$(CONFIG_BOOTCOUNT_AM33XX_NVMEM) += bootcount_nvmem.o
@@ -14,5 +13,6 @@
obj-$(CONFIG_DM_BOOTCOUNT_PMIC_PFUZE100) += pmic_pfuze100.o
obj-$(CONFIG_DM_BOOTCOUNT_RTC) += rtc.o
obj-$(CONFIG_DM_BOOTCOUNT_I2C_EEPROM) += i2c-eeprom.o
+obj-$(CONFIG_DM_BOOTCOUNT_I2C) += bootcount_dm_i2c.o
obj-$(CONFIG_DM_BOOTCOUNT_SPI_FLASH) += spi-flash.o
obj-$(CONFIG_DM_BOOTCOUNT_SYSCON) += bootcount_syscon.o
diff --git a/drivers/bootcount/bootcount-uclass.c b/drivers/bootcount/bootcount-uclass.c
index c747c9a..5a369c8 100644
--- a/drivers/bootcount/bootcount-uclass.c
+++ b/drivers/bootcount/bootcount-uclass.c
@@ -10,6 +10,7 @@
#include <errno.h>
#include <bootcount.h>
#include <log.h>
+#include <linux/printk.h>
int dm_bootcount_get(struct udevice *dev, u32 *bootcount)
{
diff --git a/drivers/bootcount/bootcount_dm_i2c.c b/drivers/bootcount/bootcount_dm_i2c.c
new file mode 100644
index 0000000..e27034c
--- /dev/null
+++ b/drivers/bootcount/bootcount_dm_i2c.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023
+ * Philip Richard Oberfichtner <pro@denx.de>
+ *
+ * Based on previous work from Heiko Schocher (legacy bootcount_i2c.c driver)
+ */
+
+#include <bootcount.h>
+#include <dm.h>
+#include <i2c.h>
+
+#define BC_MAGIC 0x55
+
+struct bootcount_i2c_priv {
+ struct udevice *bcdev;
+ unsigned int offset;
+};
+
+static int bootcount_i2c_set(struct udevice *dev, const u32 val)
+{
+ int ret;
+ struct bootcount_i2c_priv *priv = dev_get_priv(dev);
+
+ ret = dm_i2c_reg_write(priv->bcdev, priv->offset, BC_MAGIC);
+ if (ret < 0)
+ goto err_exit;
+
+ ret = dm_i2c_reg_write(priv->bcdev, priv->offset + 1, val & 0xff);
+ if (ret < 0)
+ goto err_exit;
+
+ return 0;
+
+err_exit:
+ log_debug("%s: Error writing to I2C device (%d)\n", __func__, ret);
+ return ret;
+}
+
+static int bootcount_i2c_get(struct udevice *dev, u32 *val)
+{
+ int ret;
+ struct bootcount_i2c_priv *priv = dev_get_priv(dev);
+
+ ret = dm_i2c_reg_read(priv->bcdev, priv->offset);
+ if (ret < 0)
+ goto err_exit;
+
+ if ((ret & 0xff) != BC_MAGIC) {
+ log_debug("%s: Invalid Magic, reset bootcounter.\n", __func__);
+ *val = 0;
+ return bootcount_i2c_set(dev, 0);
+ }
+
+ ret = dm_i2c_reg_read(priv->bcdev, priv->offset + 1);
+ if (ret < 0)
+ goto err_exit;
+
+ *val = ret;
+ return 0;
+
+err_exit:
+ log_debug("%s: Error reading from I2C device (%d)\n", __func__, ret);
+ return ret;
+}
+
+static int bootcount_i2c_probe(struct udevice *dev)
+{
+ struct bootcount_i2c_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = dev_read_u32(dev, "offset", &priv->offset);
+ if (ret)
+ goto exit;
+
+ ret = i2c_get_chip_by_phandle(dev, "i2cbcdev", &priv->bcdev);
+
+exit:
+ if (ret)
+ log_debug("%s failed, ret = %d\n", __func__, ret);
+
+ return ret;
+}
+
+static const struct bootcount_ops bootcount_i2c_ops = {
+ .get = bootcount_i2c_get,
+ .set = bootcount_i2c_set,
+};
+
+static const struct udevice_id bootcount_i2c_ids[] = {
+ { .compatible = "u-boot,bootcount-i2c" },
+ { }
+};
+
+U_BOOT_DRIVER(bootcount_i2c) = {
+ .name = "bootcount-i2c",
+ .id = UCLASS_BOOTCOUNT,
+ .priv_auto = sizeof(struct bootcount_i2c_priv),
+ .probe = bootcount_i2c_probe,
+ .of_match = bootcount_i2c_ids,
+ .ops = &bootcount_i2c_ops,
+};
diff --git a/drivers/bootcount/bootcount_i2c.c b/drivers/bootcount/bootcount_i2c.c
deleted file mode 100644
index b3ac67e..0000000
--- a/drivers/bootcount/bootcount_i2c.c
+++ /dev/null
@@ -1,43 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- */
-
-#include <bootcount.h>
-#include <linux/compiler.h>
-#include <i2c.h>
-
-#define BC_MAGIC 0xbc
-
-void bootcount_store(ulong a)
-{
- unsigned char buf[3];
- int ret;
-
- buf[0] = BC_MAGIC;
- buf[1] = (a & 0xff);
- ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR,
- CONFIG_BOOTCOUNT_ALEN, buf, 2);
- if (ret != 0)
- puts("Error writing bootcount\n");
-}
-
-ulong bootcount_load(void)
-{
- unsigned char buf[3];
- int ret;
-
- ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR,
- CONFIG_BOOTCOUNT_ALEN, buf, 2);
- if (ret != 0) {
- puts("Error loading bootcount\n");
- return 0;
- }
- if (buf[0] == BC_MAGIC)
- return buf[1];
-
- bootcount_store(0);
-
- return 0;
-}
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 29859cd..bfd23a9 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -83,6 +83,19 @@
Enable this option if you want to (re-)use the Linux kernel's Common
Clock Framework [CCF] composite code in U-Boot's clock driver.
+config CLK_GPIO
+ bool "GPIO-controlled clock gate driver"
+ depends on CLK
+ help
+ Enable this option to add GPIO-controlled clock gate driver.
+
+config SPL_CLK_GPIO
+ bool "GPIO-controlled clock gate driver in SPL"
+ depends on SPL_CLK
+ help
+ Enable this option to add GPIO-controlled clock gate driver
+ in U-Boot SPL.
+
config CLK_BCM6345
bool "Clock controller driver for BCM6345"
depends on CLK && ARCH_BMIPS
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index e22c8cf..af27ceb 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@
obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-divider.o clk-mux.o clk-gate.o
obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-fixed-factor.o
obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_GPIO) += clk-gpio.o
obj-y += analogbits/
obj-y += imx/
@@ -26,7 +27,6 @@
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
obj-$(CONFIG_ARCH_STM32) += stm32/
obj-$(CONFIG_ARCH_STM32MP) += stm32/
-obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_CLK_AT91) += at91/
obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
@@ -42,6 +42,7 @@
obj-$(CONFIG_CLK_RENESAS) += renesas/
obj-$(CONFIG_$(SPL_TPL_)CLK_SCMI) += clk_scmi.o
obj-$(CONFIG_CLK_SIFIVE) += sifive/
+obj-$(CONFIG_CLK_SUNXI) += sunxi/
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
diff --git a/drivers/clk/analogbits/wrpll-cln28hpc.c b/drivers/clk/analogbits/wrpll-cln28hpc.c
index 776ead3..a3cb109 100644
--- a/drivers/clk/analogbits/wrpll-cln28hpc.c
+++ b/drivers/clk/analogbits/wrpll-cln28hpc.c
@@ -26,6 +26,7 @@
#include <linux/log2.h>
#include <linux/math64.h>
#include <linux/clk/analogbits-wrpll-cln28hpc.h>
+#include <linux/printk.h>
/* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
#define MIN_INPUT_FREQ 7000000
diff --git a/drivers/clk/clk-cdce9xx.c b/drivers/clk/clk-cdce9xx.c
index f23465d..b8700f5 100644
--- a/drivers/clk/clk-cdce9xx.c
+++ b/drivers/clk/clk-cdce9xx.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments CDCE913/925/937/949 clock synthesizer driver
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* Tero Kristo <t-kristo@ti.com>
*
* Based on Linux kernel clk-cdce925.c.
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index 6eb2b81..d2e5a1a 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -66,7 +66,7 @@
const struct clk_ops *rate_ops = composite->rate_ops;
struct clk *clk_rate = composite->rate;
- if (rate && rate_ops)
+ if (rate && rate_ops && rate_ops->set_rate)
return rate_ops->set_rate(clk_rate, rate);
else
return clk_get_rate(clk);
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 6ab137a..2ad682b 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -28,6 +28,7 @@
#include <linux/log2.h>
#include <div64.h>
#include <clk.h>
+#include <linux/printk.h>
#include "clk.h"
#define UBOOT_DM_CLK_CCF_DIVIDER "ccf_clk_divider"
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index a8775c7..cfd90b7 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -21,6 +21,7 @@
#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
+#include <linux/printk.h>
#include "clk.h"
diff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c
new file mode 100644
index 0000000..26d795b
--- /dev/null
+++ b/drivers/clk/clk-gpio.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Marek Vasut <marek.vasut+renesas@mailbox.org>
+ */
+
+#include <asm/gpio.h>
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+
+struct clk_gpio_priv {
+ struct gpio_desc enable;
+};
+
+static int clk_gpio_enable(struct clk *clk)
+{
+ struct clk_gpio_priv *priv = dev_get_priv(clk->dev);
+
+ dm_gpio_set_value(&priv->enable, 1);
+
+ return 0;
+}
+
+static int clk_gpio_disable(struct clk *clk)
+{
+ struct clk_gpio_priv *priv = dev_get_priv(clk->dev);
+
+ dm_gpio_set_value(&priv->enable, 0);
+
+ return 0;
+}
+
+const struct clk_ops clk_gpio_ops = {
+ .enable = clk_gpio_enable,
+ .disable = clk_gpio_disable,
+};
+
+static int clk_gpio_probe(struct udevice *dev)
+{
+ struct clk_gpio_priv *priv = dev_get_priv(dev);
+
+ return gpio_request_by_name(dev, "enable-gpios", 0,
+ &priv->enable, GPIOD_IS_OUT);
+}
+
+/*
+ * When implementing clk-mux-clock, use gpio_request_list_by_name
+ * and implement get_rate/set_rate/set_parent ops. This should be
+ * in a separate driver and with separate Kconfig option to enable
+ * that driver, since unlike Linux implementation, the U-Boot DM
+ * integration would be orthogonal to this driver.
+ */
+static const struct udevice_id clk_gpio_match[] = {
+ { .compatible = "gpio-gate-clock" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(gpio_gate_clock) = {
+ .name = "gpio_clock",
+ .id = UCLASS_CLK,
+ .of_match = clk_gpio_match,
+ .probe = clk_gpio_probe,
+ .priv_auto = sizeof(struct clk_gpio_priv),
+ .ops = &clk_gpio_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index e28543e..85074f1 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -19,6 +19,7 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <asm/arcregs.h>
+#include <linux/printk.h>
#include <dt-bindings/clock/snps,hsdk-cgu.h>
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 017f25f..f410518 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -36,6 +36,7 @@
#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
+#include <linux/printk.h>
#include "clk.h"
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index dc3e9d6..3e9d68f 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -329,7 +329,13 @@
dev_dbg(dev,
"could not get assigned clock %d (err = %d)\n",
index, ret);
- continue;
+ /* Skip if it is empty */
+ if (ret == -ENOENT) {
+ ret = 0;
+ continue;
+ }
+
+ return ret;
}
/* This is clk provider device trying to program itself
@@ -416,12 +422,13 @@
return clk_get_by_index_nodev(node, index, clk);
}
-int clk_release_all(struct clk *clk, int count)
+int clk_release_all(struct clk *clk, unsigned int count)
{
- int i, ret;
+ unsigned int i;
+ int ret;
for (i = 0; i < count; i++) {
- debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
+ debug("%s(clk[%u]=%p)\n", __func__, i, &clk[i]);
/* check if clock has been previously requested */
if (!clk[i].dev)
@@ -471,7 +478,7 @@
ulong clk_get_rate(struct clk *clk)
{
const struct clk_ops *ops;
- int ret;
+ ulong ret;
debug("%s(clk=%p)\n", __func__, clk);
if (!clk_valid(clk))
@@ -633,6 +640,7 @@
if (CONFIG_IS_ENABLED(CLK_CCF)) {
/* Take id 0 as a non-valid clk, such as dummy */
if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
+ ops = clk_dev_ops(clkp->dev);
if (clkp->enable_count) {
clkp->enable_count++;
return 0;
@@ -649,7 +657,7 @@
}
if (ops->enable) {
- ret = ops->enable(clk);
+ ret = ops->enable(clkp ? clkp : clk);
if (ret) {
printf("Enable %s failed\n", clk->dev->name);
return ret;
@@ -692,6 +700,7 @@
if (CONFIG_IS_ENABLED(CLK_CCF)) {
if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
+ ops = clk_dev_ops(clkp->dev);
if (clkp->flags & CLK_IS_CRITICAL)
return 0;
@@ -706,7 +715,7 @@
}
if (ops->disable) {
- ret = ops->disable(clk);
+ ret = ops->disable(clkp ? clkp : clk);
if (ret)
return ret;
}
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index a5a3461..6ede1b4 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -18,17 +18,19 @@
int clk_register(struct clk *clk, const char *drv_name,
const char *name, const char *parent_name)
{
- struct udevice *parent;
+ struct udevice *parent = NULL;
struct driver *drv;
int ret;
- ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent);
- if (ret) {
- log_err("%s: failed to get %s device (parent of %s)\n",
- __func__, parent_name, name);
- } else {
- log_debug("%s: name: %s parent: %s [0x%p]\n", __func__, name,
- parent->name, parent);
+ if (parent_name) {
+ ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent);
+ if (ret) {
+ log_err("%s: failed to get %s device (parent of %s)\n",
+ __func__, parent_name, name);
+ } else {
+ log_debug("%s: name: %s parent: %s [0x%p]\n", __func__, name,
+ parent->name, parent);
+ }
}
drv = lists_driver_lookup_name(drv_name);
diff --git a/drivers/clk/clk_boston.c b/drivers/clk/clk_boston.c
index 2e81777..4bcf911 100644
--- a/drivers/clk/clk_boston.c
+++ b/drivers/clk/clk_boston.c
@@ -10,6 +10,7 @@
#include <regmap.h>
#include <syscon.h>
#include <linux/bitops.h>
+#include <linux/printk.h>
struct clk_boston {
struct regmap *regmap;
diff --git a/drivers/clk/clk_sandbox_ccf.c b/drivers/clk/clk_sandbox_ccf.c
index fedcdd4..38184e2 100644
--- a/drivers/clk/clk_sandbox_ccf.c
+++ b/drivers/clk/clk_sandbox_ccf.c
@@ -284,6 +284,7 @@
U_BOOT_DRIVER(sandbox_clk_ccf) = {
.name = "sandbox_clk_ccf",
.id = UCLASS_CLK,
+ .ops = &ccf_clk_ops,
.probe = sandbox_clk_ccf_probe,
.of_match = sandbox_clk_ccf_test_ids,
};
diff --git a/drivers/clk/clk_sandbox_test.c b/drivers/clk/clk_sandbox_test.c
index 5807a45..c695b69 100644
--- a/drivers/clk/clk_sandbox_test.c
+++ b/drivers/clk/clk_sandbox_test.c
@@ -15,6 +15,7 @@
[SANDBOX_CLK_TEST_ID_FIXED] = "fixed",
[SANDBOX_CLK_TEST_ID_SPI] = "spi",
[SANDBOX_CLK_TEST_ID_I2C] = "i2c",
+ [SANDBOX_CLK_TEST_ID_I2C_ROOT] = "i2c_root",
};
int sandbox_clk_test_get(struct udevice *dev)
diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c
index d172fed..34a4936 100644
--- a/drivers/clk/clk_scmi.c
+++ b/drivers/clk/clk_scmi.c
@@ -13,17 +13,8 @@
#include <asm/types.h>
#include <linux/clk-provider.h>
-/**
- * struct scmi_clk_priv - Private data for SCMI clocks
- * @channel: Reference to the SCMI channel to use
- */
-struct scmi_clk_priv {
- struct scmi_channel *channel;
-};
-
static int scmi_clk_get_num_clock(struct udevice *dev, size_t *num_clocks)
{
- struct scmi_clk_priv *priv = dev_get_priv(dev);
struct scmi_clk_protocol_attr_out out;
struct scmi_msg msg = {
.protocol_id = SCMI_PROTOCOL_ID_CLOCK,
@@ -33,7 +24,7 @@
};
int ret;
- ret = devm_scmi_process_msg(dev, priv->channel, &msg);
+ ret = devm_scmi_process_msg(dev, &msg);
if (ret)
return ret;
@@ -44,7 +35,6 @@
static int scmi_clk_get_attibute(struct udevice *dev, int clkid, char **name)
{
- struct scmi_clk_priv *priv = dev_get_priv(dev);
struct scmi_clk_attribute_in in = {
.clock_id = clkid,
};
@@ -59,7 +49,7 @@
};
int ret;
- ret = devm_scmi_process_msg(dev, priv->channel, &msg);
+ ret = devm_scmi_process_msg(dev, &msg);
if (ret)
return ret;
@@ -70,7 +60,6 @@
static int scmi_clk_gate(struct clk *clk, int enable)
{
- struct scmi_clk_priv *priv = dev_get_priv(clk->dev);
struct scmi_clk_state_in in = {
.clock_id = clk->id,
.attributes = enable,
@@ -81,7 +70,7 @@
in, out);
int ret;
- ret = devm_scmi_process_msg(clk->dev, priv->channel, &msg);
+ ret = devm_scmi_process_msg(clk->dev, &msg);
if (ret)
return ret;
@@ -100,7 +89,6 @@
static ulong scmi_clk_get_rate(struct clk *clk)
{
- struct scmi_clk_priv *priv = dev_get_priv(clk->dev);
struct scmi_clk_rate_get_in in = {
.clock_id = clk->id,
};
@@ -110,7 +98,7 @@
in, out);
int ret;
- ret = devm_scmi_process_msg(clk->dev, priv->channel, &msg);
+ ret = devm_scmi_process_msg(clk->dev, &msg);
if (ret < 0)
return ret;
@@ -123,7 +111,6 @@
static ulong scmi_clk_set_rate(struct clk *clk, ulong rate)
{
- struct scmi_clk_priv *priv = dev_get_priv(clk->dev);
struct scmi_clk_rate_set_in in = {
.clock_id = clk->id,
.flags = SCMI_CLK_RATE_ROUND_CLOSEST,
@@ -136,7 +123,7 @@
in, out);
int ret;
- ret = devm_scmi_process_msg(clk->dev, priv->channel, &msg);
+ ret = devm_scmi_process_msg(clk->dev, &msg);
if (ret < 0)
return ret;
@@ -149,12 +136,11 @@
static int scmi_clk_probe(struct udevice *dev)
{
- struct scmi_clk_priv *priv = dev_get_priv(dev);
struct clk *clk;
size_t num_clocks, i;
int ret;
- ret = devm_scmi_of_get_channel(dev, &priv->channel);
+ ret = devm_scmi_of_get_channel(dev);
if (ret)
return ret;
@@ -205,5 +191,4 @@
.id = UCLASS_CLK,
.ops = &scmi_clk_ops,
.probe = scmi_clk_probe,
- .priv_auto = sizeof(struct scmi_clk_priv *),
};
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index b3b3333..c473643 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -68,6 +68,13 @@
#define CLOCK_NODE_TYPE_DIV 4
#define CLOCK_NODE_TYPE_GATE 6
+#define PM_CLK_REF_CLK (0x830c06aU)
+#define PM_CLK_PL_ALT_REF_CLK (0x830c06bU)
+#define PM_CLK_MUXED_IRO (0x830c06cU)
+#define PM_CLK_EMIO (0x830c071U)
+
+#define TOPOLOGY_TYPE_FIXEDFACTOR 0x3
+
enum clk_type {
CLK_TYPE_OUTPUT,
CLK_TYPE_EXTERNAL,
@@ -365,48 +372,37 @@
return div;
}
-static u64 versal_clock_ref(u32 clk_id)
+static u64 versal_clock_get_ref_rate(u32 clk_id)
{
- u32 ret_payload[PAYLOAD_ARG_CNT];
- int ref;
-
- xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload);
- ref = ret_payload[0];
- if (!(ref & 1))
+ if (clk_id == PM_CLK_REF_CLK || clk_id == PM_CLK_MUXED_IRO || clk_id == PM_CLK_EMIO)
return ref_clk;
- if (ref & 2)
+ else if (clk_id == PM_CLK_PL_ALT_REF_CLK)
return pl_alt_ref_clk;
- return 0;
+ else
+ return 0;
}
-static u64 versal_clock_get_pll_rate(u32 clk_id)
+static int versal_clock_get_fixed_factor_rate(u32 clock_id, u32 parent_id)
{
+ struct versal_pm_query_data qdata = {0};
u32 ret_payload[PAYLOAD_ARG_CNT];
- u32 fbdiv;
- u32 res;
- u32 frac;
- u64 freq;
- u32 parent_rate, parent_id;
- u32 id = clk_id & 0xFFF;
+ u32 mult, div;
+ u32 parent_rate;
+ int ret;
- xilinx_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
- res = ret_payload[1];
- if (!res) {
- printf("0%x PLL not enabled\n", clk_id);
- return 0;
- }
+ qdata.qid = PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS;
+ qdata.arg1 = clock_id;
- parent_id = clock[clock[id].parent[0].id].clk_id;
- parent_rate = versal_clock_ref(parent_id);
+ ret = versal_pm_query(qdata, ret_payload);
+ if (ret)
+ return ret;
- xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
- fbdiv = ret_payload[1];
- xilinx_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
- frac = ret_payload[1];
+ mult = ret_payload[1];
+ div = ret_payload[2];
- freq = (fbdiv * parent_rate) >> (1 << frac);
+ parent_rate = versal_clock_get_ref_rate(parent_id);
+ return parent_rate * mult / div;
- return freq;
}
static u32 versal_clock_mux(u32 clk_id)
@@ -437,6 +433,37 @@
return clock[clock[id].parent[parent_id].id].clk_id;
}
+static u64 versal_clock_get_pll_rate(u32 clk_id)
+{
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ u32 fbdiv;
+ u32 res;
+ u32 frac;
+ u64 freq;
+ u32 parent_rate, parent_id, parent_ref_clk_id;
+ u32 id = clk_id & 0xFFF;
+
+ xilinx_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
+ res = ret_payload[1];
+ if (!res) {
+ printf("0%x PLL not enabled\n", clk_id);
+ return 0;
+ }
+
+ parent_id = clock[clock[id].parent[0].id].clk_id;
+ parent_ref_clk_id = versal_clock_get_parentid(parent_id);
+ parent_rate = versal_clock_get_ref_rate(parent_ref_clk_id);
+
+ xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
+ fbdiv = ret_payload[1];
+ xilinx_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
+ frac = ret_payload[1];
+
+ freq = (fbdiv * parent_rate) >> (1 << frac);
+
+ return freq;
+}
+
static u32 versal_clock_gate(u32 clk_id)
{
u32 id = clk_id & 0xFFF;
@@ -479,14 +506,19 @@
u32 parent_id;
u64 clk_rate;
u32 div;
+ struct clock_topology topology;
if (versal_clock_pll(clk_id, &clk_rate))
return clk_rate;
parent_id = versal_clock_get_parentid(clk_id);
if (((parent_id >> NODE_SUBCLASS_SHIFT) &
- NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF)
- return versal_clock_ref(clk_id);
+ NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF) {
+ topology = clock[clk_id & 0x3FF].node[0];
+ if (topology.type == TOPOLOGY_TYPE_FIXEDFACTOR)
+ return versal_clock_get_fixed_factor_rate(clk_id, parent_id);
+ return versal_clock_get_ref_rate(parent_id);
+ }
if (!parent_id)
return 0;
@@ -505,7 +537,7 @@
{
if (((clk_id >> NODE_SUBCLASS_SHIFT) &
NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF)
- *clk_rate = versal_clock_ref(clk_id);
+ *clk_rate = versal_clock_get_ref_rate(clk_id);
if (versal_clock_pll(clk_id, clk_rate))
return 0;
@@ -741,7 +773,6 @@
static const struct udevice_id versal_clk_ids[] = {
{ .compatible = "xlnx,versal-clk" },
- { .compatible = "xlnx,versal-net-clk" },
{ }
};
diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h
index c79aac4..7b7af5e 100644
--- a/drivers/clk/exynos/clk-pll.h
+++ b/drivers/clk/exynos/clk-pll.h
@@ -5,4 +5,9 @@
* Thomas Abraham <thomas.ab@samsung.com>
*/
+#ifndef __EXYNOS_CLK_PLL_H
+#define __EXYNOS_CLK_PLL_H
+
unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);
+
+#endif /* __EXYNOS_CLK_PLL_H */
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index abcb19c..56d893e 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -89,6 +89,24 @@
help
This enables support clock driver for i.MX8MQ platforms.
+config SPL_CLK_IMX93
+ bool "SPL clock support for i.MX93"
+ depends on ARCH_IMX9 && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ select SPL_CLK_COMPOSITE_CCF
+ help
+ This enables SPL DM/DTS support for clock driver in i.MX93
+
+config CLK_IMX93
+ bool "Clock support for i.MX93"
+ depends on ARCH_IMX9
+ select CLK
+ select CLK_CCF
+ select CLK_COMPOSITE_CCF
+ help
+ This enables support for clock driver in i.MX93
+
config SPL_CLK_IMXRT1020
bool "SPL clock support for i.MXRT1020"
depends on ARCH_IMXRT && SPL
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index b9c197f..6d4bcd3 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -18,6 +18,8 @@
clk-composite-8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MQ) += clk-imx8mq.o clk-pll14xx.o \
clk-composite-8m.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMX93) += clk-imx93.o clk-fracn-gppll.o \
+ clk-gate-93.o clk-composite-93.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
diff --git a/drivers/clk/imx/clk-composite-93.c b/drivers/clk/imx/clk-composite-93.c
new file mode 100644
index 0000000..6d71c0c
--- /dev/null
+++ b/drivers/clk/imx/clk-composite-93.c
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+#include <common.h>
+#include <log.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <dm/devres.h>
+#include <linux/iopoll.h>
+#include <linux/clk-provider.h>
+#include <clk.h>
+#include "clk.h"
+#include <linux/err.h>
+
+#define TIMEOUT_US 500U
+
+#define CCM_DIV_SHIFT 0
+#define CCM_DIV_WIDTH 8
+#define CCM_MUX_SHIFT 8
+#define CCM_MUX_MASK 3
+#define CCM_OFF_SHIFT 24
+#define CCM_BUSY_SHIFT 28
+
+#define STAT_OFFSET 0x4
+#define AUTHEN_OFFSET 0x30
+#define TZ_NS_SHIFT 9
+#define TZ_NS_MASK BIT(9)
+
+#define WHITE_LIST_SHIFT 16
+
+#define readl_poll_timeout_atomic readl_poll_timeout
+
+static int imx93_clk_composite_wait_ready(struct clk *clk, void __iomem *reg)
+{
+ int ret;
+ u32 val;
+
+ ret = readl_poll_timeout_atomic(reg + STAT_OFFSET, val, !(val & BIT(CCM_BUSY_SHIFT)),
+ TIMEOUT_US);
+ if (ret)
+ pr_err("Slice[%s] busy timeout\n", "TODO");
+
+ return ret;
+}
+
+static void imx93_clk_composite_gate_endisable(struct clk *clk, int enable)
+{
+ struct clk_gate *gate = to_clk_gate(clk);
+ u32 reg;
+
+ reg = readl(gate->reg);
+
+ if (enable)
+ reg &= ~BIT(gate->bit_idx);
+ else
+ reg |= BIT(gate->bit_idx);
+
+ writel(reg, gate->reg);
+
+ imx93_clk_composite_wait_ready(clk, gate->reg);
+}
+
+static int imx93_clk_composite_gate_enable(struct clk *clk)
+{
+ imx93_clk_composite_gate_endisable(clk, 1);
+
+ return 0;
+}
+
+static int imx93_clk_composite_gate_disable(struct clk *clk)
+{
+ imx93_clk_composite_gate_endisable(clk, 0);
+
+ return 0;
+}
+
+static const struct clk_ops imx93_clk_composite_gate_ops = {
+ .enable = imx93_clk_composite_gate_enable,
+ .disable = imx93_clk_composite_gate_disable,
+};
+
+struct clk *imx93_clk_composite_flags(const char *name,
+ const char * const *parent_names,
+ int num_parents, void __iomem *reg, u32 domain_id,
+ unsigned long flags)
+{
+ struct clk *clk = ERR_PTR(-ENOMEM);
+ struct clk_divider *div = NULL;
+ struct clk_gate *gate = NULL;
+ struct clk_mux *mux = NULL;
+
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ goto fail;
+
+ mux->reg = reg;
+ mux->shift = CCM_MUX_SHIFT;
+ mux->mask = CCM_MUX_MASK;
+ mux->num_parents = num_parents;
+ mux->parent_names = parent_names;
+ mux->flags = flags;
+
+ div = kzalloc(sizeof(*div), GFP_KERNEL);
+ if (!div)
+ goto fail;
+
+ div->reg = reg;
+ div->shift = CCM_DIV_SHIFT;
+ div->width = CCM_DIV_WIDTH;
+ div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
+
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ goto fail;
+
+ gate->reg = reg;
+ gate->bit_idx = CCM_OFF_SHIFT;
+ gate->flags = flags;
+
+ clk = clk_register_composite(NULL, name,
+ parent_names, num_parents,
+ &mux->clk, &clk_mux_ops,
+ &div->clk, &clk_divider_ops,
+ &gate->clk, &imx93_clk_composite_gate_ops,
+ flags);
+
+ if (IS_ERR(clk))
+ goto fail;
+
+ return clk;
+
+fail:
+ kfree(gate);
+ kfree(div);
+ kfree(mux);
+ return ERR_CAST(clk);
+}
diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
new file mode 100644
index 0000000..9228f27
--- /dev/null
+++ b/drivers/clk/imx/clk-fracn-gppll.c
@@ -0,0 +1,382 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2021 NXP
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <dm/devres.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/iopoll.h>
+#include <clk.h>
+#include <div64.h>
+
+#include "clk.h"
+
+#define UBOOT_DM_CLK_IMX_FRACN_GPPLL "imx_clk_fracn_gppll"
+
+#define PLL_CTRL 0x0
+#define HW_CTRL_SEL BIT(16)
+#define CLKMUX_BYPASS BIT(2)
+#define CLKMUX_EN BIT(1)
+#define POWERUP_MASK BIT(0)
+
+#define PLL_ANA_PRG 0x10
+#define PLL_SPREAD_SPECTRUM 0x30
+
+#define PLL_NUMERATOR 0x40
+#define PLL_MFN_MASK GENMASK(31, 2)
+
+#define PLL_DENOMINATOR 0x50
+#define PLL_MFD_MASK GENMASK(29, 0)
+
+#define PLL_DIV 0x60
+#define PLL_MFI_MASK GENMASK(24, 16)
+#define PLL_RDIV_MASK GENMASK(15, 13)
+#define PLL_ODIV_MASK GENMASK(7, 0)
+
+#define PLL_DFS_CTRL(x) (0x70 + (x) * 0x10)
+
+#define PLL_STATUS 0xF0
+#define LOCK_STATUS BIT(0)
+
+#define DFS_STATUS 0xF4
+
+#define LOCK_TIMEOUT_US 200
+
+#define PLL_FRACN_GP(_rate, _mfi, _mfn, _mfd, _rdiv, _odiv) \
+ { \
+ .rate = (_rate), \
+ .mfi = (_mfi), \
+ .mfn = (_mfn), \
+ .mfd = (_mfd), \
+ .rdiv = (_rdiv), \
+ .odiv = (_odiv), \
+ }
+
+#define PLL_FRACN_GP_INTEGER(_rate, _mfi, _rdiv, _odiv) \
+ { \
+ .rate = (_rate), \
+ .mfi = (_mfi), \
+ .mfn = 0, \
+ .mfd = 0, \
+ .rdiv = (_rdiv), \
+ .odiv = (_odiv), \
+ }
+
+struct clk_fracn_gppll {
+ struct clk clk;
+ void __iomem *base;
+ const struct imx_fracn_gppll_rate_table *rate_table;
+ int rate_count;
+ u32 flags;
+};
+
+/*
+ * Fvco = (Fref / rdiv) * (MFI + MFN / MFD)
+ * Fout = Fvco / odiv
+ * The (Fref / rdiv) should be in range 20MHz to 40MHz
+ * The Fvco should be in range 2.5Ghz to 5Ghz
+ */
+static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
+ PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6),
+ PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
+ PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),
+ PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
+ PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
+ PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
+ PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
+ PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
+ PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12)
+};
+
+struct imx_fracn_gppll_clk imx_fracn_gppll = {
+ .rate_table = fracn_tbl,
+ .rate_count = ARRAY_SIZE(fracn_tbl),
+};
+
+/*
+ * Fvco = (Fref / rdiv) * MFI
+ * Fout = Fvco / odiv
+ * The (Fref / rdiv) should be in range 20MHz to 40MHz
+ * The Fvco should be in range 2.5Ghz to 5Ghz
+ */
+static const struct imx_fracn_gppll_rate_table int_tbl[] = {
+ PLL_FRACN_GP_INTEGER(1700000000U, 141, 1, 2),
+ PLL_FRACN_GP_INTEGER(1400000000U, 175, 1, 3),
+ PLL_FRACN_GP_INTEGER(900000000U, 150, 1, 4),
+};
+
+struct imx_fracn_gppll_clk imx_fracn_gppll_integer = {
+ .rate_table = int_tbl,
+ .rate_count = ARRAY_SIZE(int_tbl),
+};
+
+#define to_clk_fracn_gppll(_clk) container_of(_clk, struct clk_fracn_gppll, clk)
+
+static const struct imx_fracn_gppll_rate_table *
+imx_get_pll_settings(struct clk_fracn_gppll *pll, unsigned long rate)
+{
+ const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
+ int i;
+
+ for (i = 0; i < pll->rate_count; i++)
+ if (rate == rate_table[i].rate)
+ return &rate_table[i];
+
+ return NULL;
+}
+
+static unsigned long clk_fracn_gppll_round_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk_fracn_gppll *pll = to_clk_fracn_gppll(clk);
+ const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
+ int i;
+
+ /* Assuming rate_table is in descending order */
+ for (i = 0; i < pll->rate_count; i++)
+ if (rate >= rate_table[i].rate)
+ return rate_table[i].rate;
+
+ /* return minimum supported value */
+ return rate_table[pll->rate_count - 1].rate;
+}
+
+static unsigned long clk_fracn_gppll_recalc_rate(struct clk *clk)
+{
+ struct clk_fracn_gppll *pll = to_clk_fracn_gppll(clk);
+ const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
+ u32 pll_numerator, pll_denominator, pll_div;
+ u32 mfi, mfn, mfd, rdiv, odiv;
+ u64 fvco = clk_get_parent_rate(clk);
+ long rate = 0;
+ int i;
+
+ pll_numerator = readl_relaxed(pll->base + PLL_NUMERATOR);
+ mfn = FIELD_GET(PLL_MFN_MASK, pll_numerator);
+
+ pll_denominator = readl_relaxed(pll->base + PLL_DENOMINATOR);
+ mfd = FIELD_GET(PLL_MFD_MASK, pll_denominator);
+
+ pll_div = readl_relaxed(pll->base + PLL_DIV);
+ mfi = FIELD_GET(PLL_MFI_MASK, pll_div);
+
+ rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div);
+ odiv = FIELD_GET(PLL_ODIV_MASK, pll_div);
+
+ /*
+ * Sometimes, the recalculated rate has deviation due to
+ * the frac part. So find the accurate pll rate from the table
+ * first, if no match rate in the table, use the rate calculated
+ * from the equation below.
+ */
+ for (i = 0; i < pll->rate_count; i++) {
+ if (rate_table[i].mfn == mfn && rate_table[i].mfi == mfi &&
+ rate_table[i].mfd == mfd && rate_table[i].rdiv == rdiv &&
+ rate_table[i].odiv == odiv)
+ rate = rate_table[i].rate;
+ }
+
+ if (rate)
+ return (unsigned long)rate;
+
+ if (!rdiv)
+ rdiv = rdiv + 1;
+
+ switch (odiv) {
+ case 0:
+ odiv = 2;
+ break;
+ case 1:
+ odiv = 3;
+ break;
+ default:
+ break;
+ }
+
+ if (pll->flags & CLK_FRACN_GPPLL_INTEGER) {
+ /* Fvco = (Fref / rdiv) * MFI */
+ fvco = fvco * mfi;
+ do_div(fvco, rdiv * odiv);
+ } else {
+ /* Fvco = (Fref / rdiv) * (MFI + MFN / MFD) */
+ fvco = fvco * mfi * mfd + fvco * mfn;
+ do_div(fvco, mfd * rdiv * odiv);
+ }
+
+ return (unsigned long)fvco;
+}
+
+static int clk_fracn_gppll_wait_lock(struct clk_fracn_gppll *pll)
+{
+ u32 val;
+
+ return readl_poll_timeout(pll->base + PLL_STATUS, val,
+ val & LOCK_STATUS, LOCK_TIMEOUT_US);
+}
+
+static ulong clk_fracn_gppll_set_rate(struct clk *clk, unsigned long drate)
+{
+ struct clk_fracn_gppll *pll = to_clk_fracn_gppll(clk);
+ const struct imx_fracn_gppll_rate_table *rate;
+ u32 tmp, pll_div, ana_mfn;
+ int ret;
+
+ rate = imx_get_pll_settings(pll, drate);
+
+ /* Hardware control select disable. PLL is control by register */
+ tmp = readl_relaxed(pll->base + PLL_CTRL);
+ tmp &= ~HW_CTRL_SEL;
+ writel_relaxed(tmp, pll->base + PLL_CTRL);
+
+ /* Disable output */
+ tmp = readl_relaxed(pll->base + PLL_CTRL);
+ tmp &= ~CLKMUX_EN;
+ writel_relaxed(tmp, pll->base + PLL_CTRL);
+
+ /* Power Down */
+ tmp &= ~POWERUP_MASK;
+ writel_relaxed(tmp, pll->base + PLL_CTRL);
+
+ /* Disable BYPASS */
+ tmp &= ~CLKMUX_BYPASS;
+ writel_relaxed(tmp, pll->base + PLL_CTRL);
+
+ pll_div = FIELD_PREP(PLL_RDIV_MASK, rate->rdiv) | rate->odiv |
+ FIELD_PREP(PLL_MFI_MASK, rate->mfi);
+ writel_relaxed(pll_div, pll->base + PLL_DIV);
+ if (pll->flags & CLK_FRACN_GPPLL_FRACN) {
+ writel_relaxed(rate->mfd, pll->base + PLL_DENOMINATOR);
+ writel_relaxed(FIELD_PREP(PLL_MFN_MASK, rate->mfn), pll->base + PLL_NUMERATOR);
+ }
+
+ /* Wait for 5us according to fracn mode pll doc */
+ udelay(5);
+
+ /* Enable Powerup */
+ tmp |= POWERUP_MASK;
+ writel_relaxed(tmp, pll->base + PLL_CTRL);
+
+ /* Wait Lock */
+ ret = clk_fracn_gppll_wait_lock(pll);
+ if (ret)
+ return ret;
+
+ /* Enable output */
+ tmp |= CLKMUX_EN;
+ writel_relaxed(tmp, pll->base + PLL_CTRL);
+
+ ana_mfn = readl_relaxed(pll->base + PLL_STATUS);
+ ana_mfn = FIELD_GET(PLL_MFN_MASK, ana_mfn);
+
+ WARN(ana_mfn != rate->mfn, "ana_mfn != rate->mfn\n");
+
+ return 0;
+}
+
+static int clk_fracn_gppll_prepare(struct clk *clk)
+{
+ struct clk_fracn_gppll *pll = to_clk_fracn_gppll(clk);
+ u32 val;
+ int ret;
+
+ val = readl_relaxed(pll->base + PLL_CTRL);
+ if (val & POWERUP_MASK)
+ return 0;
+
+ val |= CLKMUX_BYPASS;
+ writel_relaxed(val, pll->base + PLL_CTRL);
+
+ val |= POWERUP_MASK;
+ writel_relaxed(val, pll->base + PLL_CTRL);
+
+ val |= CLKMUX_EN;
+ writel_relaxed(val, pll->base + PLL_CTRL);
+
+ ret = clk_fracn_gppll_wait_lock(pll);
+ if (ret)
+ return ret;
+
+ val &= ~CLKMUX_BYPASS;
+ writel_relaxed(val, pll->base + PLL_CTRL);
+
+ return 0;
+}
+
+static int clk_fracn_gppll_unprepare(struct clk *clk)
+{
+ struct clk_fracn_gppll *pll = to_clk_fracn_gppll(dev_get_clk_ptr(clk->dev));
+ u32 val;
+
+ val = readl_relaxed(pll->base + PLL_CTRL);
+ val &= ~POWERUP_MASK;
+ writel_relaxed(val, pll->base + PLL_CTRL);
+
+ return 0;
+}
+
+static const struct clk_ops clk_fracn_gppll_ops = {
+ .enable = clk_fracn_gppll_prepare,
+ .disable = clk_fracn_gppll_unprepare,
+ .get_rate = clk_fracn_gppll_recalc_rate,
+ .set_rate = clk_fracn_gppll_set_rate,
+ .round_rate = clk_fracn_gppll_round_rate,
+};
+
+static struct clk *_imx_clk_fracn_gppll(const char *name, const char *parent_name,
+ void __iomem *base,
+ const struct imx_fracn_gppll_clk *pll_clk,
+ u32 pll_flags)
+{
+ struct clk_fracn_gppll *pll;
+ struct clk *clk;
+ int ret;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ pll->base = base;
+ pll->rate_table = pll_clk->rate_table;
+ pll->rate_count = pll_clk->rate_count;
+ pll->flags = pll_flags;
+
+ clk = &pll->clk;
+
+ ret = clk_register(clk, UBOOT_DM_CLK_IMX_FRACN_GPPLL,
+ name, parent_name);
+ if (ret) {
+ pr_err("%s: failed to register pll %s %d\n", __func__, name, ret);
+ kfree(pll);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+struct clk *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base,
+ const struct imx_fracn_gppll_clk *pll_clk)
+{
+ return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_FRACN);
+}
+
+struct clk *imx_clk_fracn_gppll_integer(const char *name, const char *parent_name,
+ void __iomem *base,
+ const struct imx_fracn_gppll_clk *pll_clk)
+{
+ return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_INTEGER);
+}
+
+U_BOOT_DRIVER(clk_fracn_gppll) = {
+ .name = UBOOT_DM_CLK_IMX_FRACN_GPPLL,
+ .id = UCLASS_CLK,
+ .ops = &clk_fracn_gppll_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/imx/clk-gate-93.c b/drivers/clk/imx/clk-gate-93.c
new file mode 100644
index 0000000..bc85741
--- /dev/null
+++ b/drivers/clk/imx/clk-gate-93.c
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <dm/devres.h>
+#include <linux/bug.h>
+#include <linux/clk-provider.h>
+#include <clk.h>
+#include "clk.h"
+#include <linux/err.h>
+
+#define UBOOT_DM_CLK_IMX_GATE93 "imx_clk_gate93"
+
+#define DIRECT_OFFSET 0x0
+
+/*
+ * 0b000 - LPCG will be OFF in any CPU mode.
+ * 0b100 - LPCG will be ON in any CPU mode.
+ */
+#define LPM_SETTING_OFF 0x0
+#define LPM_SETTING_ON 0x4
+
+#define LPM_CUR_OFFSET 0x1c
+
+#define AUTHEN_OFFSET 0x30
+#define CPULPM_EN BIT(2)
+#define TZ_NS_SHIFT 9
+#define TZ_NS_MASK BIT(9)
+
+#define WHITE_LIST_SHIFT 16
+
+struct imx93_clk_gate {
+ struct clk clk;
+ void __iomem *reg;
+ u32 bit_idx;
+ u32 val;
+ u32 mask;
+ unsigned int *share_count;
+};
+
+#define to_imx93_clk_gate(_clk) container_of(_clk, struct imx93_clk_gate, clk)
+
+static void imx93_clk_gate_do_hardware(struct clk *clk, bool enable)
+{
+ struct imx93_clk_gate *gate = to_imx93_clk_gate(clk);
+ u32 val;
+
+ val = readl(gate->reg + AUTHEN_OFFSET);
+ if (val & CPULPM_EN) {
+ val = enable ? LPM_SETTING_ON : LPM_SETTING_OFF;
+ writel(val, gate->reg + LPM_CUR_OFFSET);
+ } else {
+ val = readl(gate->reg + DIRECT_OFFSET);
+ val &= ~(gate->mask << gate->bit_idx);
+ if (enable)
+ val |= (gate->val & gate->mask) << gate->bit_idx;
+ writel(val, gate->reg + DIRECT_OFFSET);
+ }
+}
+
+static int imx93_clk_gate_enable(struct clk *clk)
+{
+ struct imx93_clk_gate *gate = to_imx93_clk_gate(clk);
+
+ if (gate->share_count && (*gate->share_count)++ > 0)
+ return 0;
+
+ imx93_clk_gate_do_hardware(clk, true);
+
+ return 0;
+}
+
+static int imx93_clk_gate_disable(struct clk *clk)
+{
+ struct imx93_clk_gate *gate = to_imx93_clk_gate(clk);
+
+ if (gate->share_count) {
+ if (WARN_ON(*gate->share_count == 0))
+ return 0;
+ else if (--(*gate->share_count) > 0)
+ return 0;
+ }
+
+ imx93_clk_gate_do_hardware(clk, false);
+
+ return 0;
+}
+
+static ulong imx93_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk *parent = clk_get_parent(clk);
+
+ if (parent)
+ return clk_set_rate(parent, rate);
+
+ return -ENODEV;
+}
+
+static const struct clk_ops imx93_clk_gate_ops = {
+ .enable = imx93_clk_gate_enable,
+ .disable = imx93_clk_gate_disable,
+ .get_rate = clk_generic_get_rate,
+ .set_rate = imx93_clk_set_rate,
+};
+
+struct clk *imx93_clk_gate(struct device *dev, const char *name, const char *parent_name,
+ unsigned long flags, void __iomem *reg, u32 bit_idx, u32 val,
+ u32 mask, u32 domain_id, unsigned int *share_count)
+{
+ struct imx93_clk_gate *gate;
+ struct clk *clk;
+ int ret;
+
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ return ERR_PTR(-ENOMEM);
+
+ gate->reg = reg;
+ gate->bit_idx = bit_idx;
+ gate->val = val;
+ gate->mask = mask;
+ gate->share_count = share_count;
+
+ clk = &gate->clk;
+
+ ret = clk_register(clk, UBOOT_DM_CLK_IMX_GATE93, name, parent_name);
+ if (ret) {
+ kfree(gate);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(clk_gate93) = {
+ .name = UBOOT_DM_CLK_IMX_GATE93,
+ .id = UCLASS_CLK,
+ .ops = &imx93_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c
new file mode 100644
index 0000000..ce10d79
--- /dev/null
+++ b/drivers/clk/imx/clk-imx93.c
@@ -0,0 +1,343 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2021 NXP.
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <log.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <dt-bindings/clock/imx93-clock.h>
+
+#include "clk.h"
+
+enum clk_sel {
+ LOW_SPEED_IO_SEL,
+ NON_IO_SEL,
+ FAST_SEL,
+ AUDIO_SEL,
+ VIDEO_SEL,
+ TPM_SEL,
+ CKO1_SEL,
+ CKO2_SEL,
+ MISC_SEL,
+ MAX_SEL
+};
+
+static u32 share_count_sai1;
+static u32 share_count_sai2;
+static u32 share_count_sai3;
+static u32 share_count_mub;
+
+static const char * const a55_core_sels[] = {"a55_alt", "arm_pll"};
+static const char *parent_names[MAX_SEL][4] = {
+ {"clock-osc-24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "video_pll"},
+ {"clock-osc-24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "sys_pll_pfd2_div2"},
+ {"clock-osc-24m", "sys_pll_pfd0", "sys_pll_pfd1", "sys_pll_pfd2"},
+ {"clock-osc-24m", "audio_pll", "video_pll", "clk_ext1"},
+ {"clock-osc-24m", "audio_pll", "video_pll", "sys_pll_pfd0"},
+ {"clock-osc-24m", "sys_pll_pfd0", "audio_pll", "clk_ext1"},
+ {"clock-osc-24m", "sys_pll_pfd0", "sys_pll_pfd1", "audio_pll"},
+ {"clock-osc-24m", "sys_pll_pfd0", "sys_pll_pfd1", "video_pll"},
+ {"clock-osc-24m", "audio_pll", "video_pll", "sys_pll_pfd2"},
+};
+
+static const struct imx93_clk_root {
+ u32 clk;
+ char *name;
+ u32 off;
+ enum clk_sel sel;
+ unsigned long flags;
+} root_array[] = {
+ /* a55/m33/bus critical clk for system run */
+ { IMX93_CLK_A55_PERIPH, "a55_periph_root", 0x0000, FAST_SEL, CLK_IS_CRITICAL },
+ { IMX93_CLK_A55_MTR_BUS, "a55_mtr_bus_root", 0x0080, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
+ { IMX93_CLK_A55, "a55_alt_root", 0x0100, FAST_SEL, CLK_IS_CRITICAL },
+ { IMX93_CLK_M33, "m33_root", 0x0180, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
+ { IMX93_CLK_BUS_WAKEUP, "bus_wakeup_root", 0x0280, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
+ { IMX93_CLK_BUS_AON, "bus_aon_root", 0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
+ { IMX93_CLK_WAKEUP_AXI, "wakeup_axi_root", 0x0380, FAST_SEL, CLK_IS_CRITICAL },
+ { IMX93_CLK_SWO_TRACE, "swo_trace_root", 0x0400, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_FLEXIO1, "flexio1_root", 0x0500, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_FLEXIO2, "flexio2_root", 0x0580, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPTMR1, "lptmr1_root", 0x0700, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPTMR2, "lptmr2_root", 0x0780, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_TPM2, "tpm2_root", 0x0880, TPM_SEL, },
+ { IMX93_CLK_TPM4, "tpm4_root", 0x0980, TPM_SEL, },
+ { IMX93_CLK_TPM5, "tpm5_root", 0x0a00, TPM_SEL, },
+ { IMX93_CLK_TPM6, "tpm6_root", 0x0a80, TPM_SEL, },
+ { IMX93_CLK_FLEXSPI1, "flexspi1_root", 0x0b00, FAST_SEL, },
+ { IMX93_CLK_CAN1, "can1_root", 0x0b80, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_CAN2, "can2_root", 0x0c00, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPUART1, "lpuart1_root", 0x0c80, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPUART2, "lpuart2_root", 0x0d00, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPUART3, "lpuart3_root", 0x0d80, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPUART4, "lpuart4_root", 0x0e00, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPUART5, "lpuart5_root", 0x0e80, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPUART6, "lpuart6_root", 0x0f00, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPUART7, "lpuart7_root", 0x0f80, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPUART8, "lpuart8_root", 0x1000, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPI2C1, "lpi2c1_root", 0x1080, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPI2C2, "lpi2c2_root", 0x1100, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPI2C3, "lpi2c3_root", 0x1180, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPI2C4, "lpi2c4_root", 0x1200, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPI2C5, "lpi2c5_root", 0x1280, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPI2C6, "lpi2c6_root", 0x1300, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPI2C7, "lpi2c7_root", 0x1380, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPI2C8, "lpi2c8_root", 0x1400, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPSPI1, "lpspi1_root", 0x1480, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPSPI2, "lpspi2_root", 0x1500, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPSPI3, "lpspi3_root", 0x1580, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPSPI4, "lpspi4_root", 0x1600, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPSPI5, "lpspi5_root", 0x1680, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPSPI6, "lpspi6_root", 0x1700, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPSPI7, "lpspi7_root", 0x1780, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_LPSPI8, "lpspi8_root", 0x1800, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_I3C1, "i3c1_root", 0x1880, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_I3C2, "i3c2_root", 0x1900, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_USDHC1, "usdhc1_root", 0x1980, FAST_SEL, },
+ { IMX93_CLK_USDHC2, "usdhc2_root", 0x1a00, FAST_SEL, },
+ { IMX93_CLK_USDHC3, "usdhc3_root", 0x1a80, FAST_SEL, },
+ { IMX93_CLK_SAI1, "sai1_root", 0x1b00, AUDIO_SEL, },
+ { IMX93_CLK_SAI2, "sai2_root", 0x1b80, AUDIO_SEL, },
+ { IMX93_CLK_SAI3, "sai3_root", 0x1c00, AUDIO_SEL, },
+ { IMX93_CLK_CCM_CKO1, "ccm_cko1_root", 0x1c80, CKO1_SEL, },
+ { IMX93_CLK_CCM_CKO2, "ccm_cko2_root", 0x1d00, CKO2_SEL, },
+ { IMX93_CLK_CCM_CKO3, "ccm_cko3_root", 0x1d80, CKO1_SEL, },
+ { IMX93_CLK_CCM_CKO4, "ccm_cko4_root", 0x1e00, CKO2_SEL, },
+ /*
+ * Critical because clk is used for handshake between HSIOMIX and NICMIX when
+ * NICMIX power down/on during system suspend/resume
+ */
+ { IMX93_CLK_HSIO, "hsio_root", 0x1e80, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL},
+ { IMX93_CLK_HSIO_USB_TEST_60M, "hsio_usb_test_60m_root", 0x1f00, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_HSIO_ACSCAN_80M, "hsio_acscan_80m_root", 0x1f80, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_HSIO_ACSCAN_480M, "hsio_acscan_480m_root", 0x2000, MISC_SEL, },
+ { IMX93_CLK_NIC_AXI, "nic_axi_root", 0x2080, FAST_SEL, CLK_IS_CRITICAL, },
+ { IMX93_CLK_ML_APB, "ml_apb_root", 0x2180, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_ML, "ml_root", 0x2200, FAST_SEL, },
+ { IMX93_CLK_MEDIA_AXI, "media_axi_root", 0x2280, FAST_SEL, },
+ { IMX93_CLK_MEDIA_APB, "media_apb_root", 0x2300, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_MEDIA_LDB, "media_ldb_root", 0x2380, VIDEO_SEL, },
+ { IMX93_CLK_MEDIA_DISP_PIX, "media_disp_pix_root", 0x2400, VIDEO_SEL, },
+ { IMX93_CLK_CAM_PIX, "cam_pix_root", 0x2480, VIDEO_SEL, },
+ { IMX93_CLK_MIPI_TEST_BYTE, "mipi_test_byte_root", 0x2500, VIDEO_SEL, },
+ { IMX93_CLK_MIPI_PHY_CFG, "mipi_phy_cfg_root", 0x2580, VIDEO_SEL, },
+ { IMX93_CLK_ADC, "adc_root", 0x2700, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_PDM, "pdm_root", 0x2780, AUDIO_SEL, },
+ { IMX93_CLK_TSTMR1, "tstmr1_root", 0x2800, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_TSTMR2, "tstmr2_root", 0x2880, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_MQS1, "mqs1_root", 0x2900, AUDIO_SEL, },
+ { IMX93_CLK_MQS2, "mqs2_root", 0x2980, AUDIO_SEL, },
+ { IMX93_CLK_AUDIO_XCVR, "audio_xcvr_root", 0x2a00, NON_IO_SEL, },
+ { IMX93_CLK_SPDIF, "spdif_root", 0x2a80, AUDIO_SEL, },
+ { IMX93_CLK_ENET, "enet_root", 0x2b00, NON_IO_SEL, },
+ { IMX93_CLK_ENET_TIMER1, "enet_timer1_root", 0x2b80, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_ENET_TIMER2, "enet_timer2_root", 0x2c00, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_ENET_REF, "enet_ref_root", 0x2c80, NON_IO_SEL, },
+ { IMX93_CLK_ENET_REF_PHY, "enet_ref_phy_root", 0x2d00, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_I3C1_SLOW, "i3c1_slow_root", 0x2d80, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_I3C2_SLOW, "i3c2_slow_root", 0x2e00, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_USB_PHY_BURUNIN, "usb_phy_root", 0x2e80, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_PAL_CAME_SCAN, "pal_came_scan_root", 0x2f00, MISC_SEL, }
+};
+
+static const struct imx93_clk_ccgr {
+ u32 clk;
+ char *name;
+ char *parent_name;
+ u32 off;
+ unsigned long flags;
+ u32 *shared_count;
+} ccgr_array[] = {
+ { IMX93_CLK_A55_GATE, "a55_alt", "a55_alt_root", 0x8000, },
+ /* M33 critical clk for system run */
+ { IMX93_CLK_CM33_GATE, "cm33", "m33_root", 0x8040, CLK_IS_CRITICAL },
+ { IMX93_CLK_ADC1_GATE, "adc1", "adc_root", 0x82c0, },
+ { IMX93_CLK_WDOG1_GATE, "wdog1", "clock-osc-24m", 0x8300, },
+ { IMX93_CLK_WDOG2_GATE, "wdog2", "clock-osc-24m", 0x8340, },
+ { IMX93_CLK_WDOG3_GATE, "wdog3", "clock-osc-24m", 0x8380, },
+ { IMX93_CLK_WDOG4_GATE, "wdog4", "clock-osc-24m", 0x83c0, },
+ { IMX93_CLK_WDOG5_GATE, "wdog5", "clock-osc-24m", 0x8400, },
+ { IMX93_CLK_SEMA1_GATE, "sema1", "bus_aon_root", 0x8440, },
+ { IMX93_CLK_SEMA2_GATE, "sema2", "bus_wakeup_root", 0x8480, },
+ { IMX93_CLK_MU1_A_GATE, "mu1_a", "bus_aon_root", 0x84c0, CLK_IGNORE_UNUSED },
+ { IMX93_CLK_MU2_A_GATE, "mu2_a", "bus_wakeup_root", 0x84c0, CLK_IGNORE_UNUSED },
+ { IMX93_CLK_MU1_B_GATE, "mu1_b", "bus_aon_root", 0x8500, 0, &share_count_mub },
+ { IMX93_CLK_MU2_B_GATE, "mu2_b", "bus_wakeup_root", 0x8500, 0, &share_count_mub },
+ { IMX93_CLK_EDMA1_GATE, "edma1", "m33_root", 0x8540, },
+ { IMX93_CLK_EDMA2_GATE, "edma2", "wakeup_axi_root", 0x8580, },
+ { IMX93_CLK_FLEXSPI1_GATE, "flexspi1", "flexspi1_root", 0x8640, },
+ { IMX93_CLK_GPIO1_GATE, "gpio1", "m33_root", 0x8880, },
+ { IMX93_CLK_GPIO2_GATE, "gpio2", "bus_wakeup_root", 0x88c0, },
+ { IMX93_CLK_GPIO3_GATE, "gpio3", "bus_wakeup_root", 0x8900, },
+ { IMX93_CLK_GPIO4_GATE, "gpio4", "bus_wakeup_root", 0x8940, },
+ { IMX93_CLK_FLEXIO1_GATE, "flexio1", "flexio1_root", 0x8980, },
+ { IMX93_CLK_FLEXIO2_GATE, "flexio2", "flexio2_root", 0x89c0, },
+ { IMX93_CLK_LPIT1_GATE, "lpit1", "bus_aon_root", 0x8a00, },
+ { IMX93_CLK_LPIT2_GATE, "lpit2", "bus_wakeup_root", 0x8a40, },
+ { IMX93_CLK_LPTMR1_GATE, "lptmr1", "lptmr1_root", 0x8a80, },
+ { IMX93_CLK_LPTMR2_GATE, "lptmr2", "lptmr2_root", 0x8ac0, },
+ { IMX93_CLK_TPM1_GATE, "tpm1", "bus_aon_root", 0x8b00, },
+ { IMX93_CLK_TPM2_GATE, "tpm2", "tpm2_root", 0x8b40, },
+ { IMX93_CLK_TPM3_GATE, "tpm3", "bus_wakeup_root", 0x8b80, },
+ { IMX93_CLK_TPM4_GATE, "tpm4", "tpm4_root", 0x8bc0, },
+ { IMX93_CLK_TPM5_GATE, "tpm5", "tpm5_root", 0x8c00, },
+ { IMX93_CLK_TPM6_GATE, "tpm6", "tpm6_root", 0x8c40, },
+ { IMX93_CLK_CAN1_GATE, "can1", "can1_root", 0x8c80, },
+ { IMX93_CLK_CAN2_GATE, "can2", "can2_root", 0x8cc0, },
+ { IMX93_CLK_LPUART1_GATE, "lpuart1", "lpuart1_root", 0x8d00, },
+ { IMX93_CLK_LPUART2_GATE, "lpuart2", "lpuart2_root", 0x8d40, },
+ { IMX93_CLK_LPUART3_GATE, "lpuart3", "lpuart3_root", 0x8d80, },
+ { IMX93_CLK_LPUART4_GATE, "lpuart4", "lpuart4_root", 0x8dc0, },
+ { IMX93_CLK_LPUART5_GATE, "lpuart5", "lpuart5_root", 0x8e00, },
+ { IMX93_CLK_LPUART6_GATE, "lpuart6", "lpuart6_root", 0x8e40, },
+ { IMX93_CLK_LPUART7_GATE, "lpuart7", "lpuart7_root", 0x8e80, },
+ { IMX93_CLK_LPUART8_GATE, "lpuart8", "lpuart8_root", 0x8ec0, },
+ { IMX93_CLK_LPI2C1_GATE, "lpi2c1", "lpi2c1_root", 0x8f00, },
+ { IMX93_CLK_LPI2C2_GATE, "lpi2c2", "lpi2c2_root", 0x8f40, },
+ { IMX93_CLK_LPI2C3_GATE, "lpi2c3", "lpi2c3_root", 0x8f80, },
+ { IMX93_CLK_LPI2C4_GATE, "lpi2c4", "lpi2c4_root", 0x8fc0, },
+ { IMX93_CLK_LPI2C5_GATE, "lpi2c5", "lpi2c5_root", 0x9000, },
+ { IMX93_CLK_LPI2C6_GATE, "lpi2c6", "lpi2c6_root", 0x9040, },
+ { IMX93_CLK_LPI2C7_GATE, "lpi2c7", "lpi2c7_root", 0x9080, },
+ { IMX93_CLK_LPI2C8_GATE, "lpi2c8", "lpi2c8_root", 0x90c0, },
+ { IMX93_CLK_LPSPI1_GATE, "lpspi1", "lpspi1_root", 0x9100, },
+ { IMX93_CLK_LPSPI2_GATE, "lpspi2", "lpspi2_root", 0x9140, },
+ { IMX93_CLK_LPSPI3_GATE, "lpspi3", "lpspi3_root", 0x9180, },
+ { IMX93_CLK_LPSPI4_GATE, "lpspi4", "lpspi4_root", 0x91c0, },
+ { IMX93_CLK_LPSPI5_GATE, "lpspi5", "lpspi5_root", 0x9200, },
+ { IMX93_CLK_LPSPI6_GATE, "lpspi6", "lpspi6_root", 0x9240, },
+ { IMX93_CLK_LPSPI7_GATE, "lpspi7", "lpspi7_root", 0x9280, },
+ { IMX93_CLK_LPSPI8_GATE, "lpspi8", "lpspi8_root", 0x92c0, },
+ { IMX93_CLK_I3C1_GATE, "i3c1", "i3c1_root", 0x9300, },
+ { IMX93_CLK_I3C2_GATE, "i3c2", "i3c2_root", 0x9340, },
+ { IMX93_CLK_USDHC1_GATE, "usdhc1", "usdhc1_root", 0x9380, },
+ { IMX93_CLK_USDHC2_GATE, "usdhc2", "usdhc2_root", 0x93c0, },
+ { IMX93_CLK_USDHC3_GATE, "usdhc3", "usdhc3_root", 0x9400, },
+ { IMX93_CLK_SAI1_GATE, "sai1", "sai1_root", 0x9440, 0, &share_count_sai1},
+ { IMX93_CLK_SAI1_IPG, "sai1_ipg_clk", "bus_aon_root", 0x9440, 0, &share_count_sai1},
+ { IMX93_CLK_SAI2_GATE, "sai2", "sai2_root", 0x9480, 0, &share_count_sai2},
+ { IMX93_CLK_SAI2_IPG, "sai2_ipg_clk", "bus_wakeup_root", 0x9480, 0, &share_count_sai2},
+ { IMX93_CLK_SAI3_GATE, "sai3", "sai3_root", 0x94c0, 0, &share_count_sai3},
+ { IMX93_CLK_SAI3_IPG, "sai3_ipg_clk", "bus_wakeup_root", 0x94c0, 0, &share_count_sai3},
+ { IMX93_CLK_MIPI_CSI_GATE, "mipi_csi", "media_apb_root", 0x9580, },
+ { IMX93_CLK_MIPI_DSI_GATE, "mipi_dsi", "media_apb_root", 0x95c0, },
+ { IMX93_CLK_LVDS_GATE, "lvds", "media_ldb_root", 0x9600, },
+ { IMX93_CLK_LCDIF_GATE, "lcdif", "media_apb_root", 0x9640, },
+ { IMX93_CLK_PXP_GATE, "pxp", "media_apb_root", 0x9680, },
+ { IMX93_CLK_ISI_GATE, "isi", "media_apb_root", 0x96c0, },
+ { IMX93_CLK_NIC_MEDIA_GATE, "nic_media", "media_axi_root", 0x9700, },
+ { IMX93_CLK_USB_CONTROLLER_GATE, "usb_controller", "hsio_root", 0x9a00, },
+ { IMX93_CLK_USB_TEST_60M_GATE, "usb_test_60m", "hsio_usb_test_60m_root", 0x9a40, },
+ { IMX93_CLK_HSIO_TROUT_24M_GATE, "hsio_trout_24m", "clock-osc-24m", 0x9a80, },
+ { IMX93_CLK_PDM_GATE, "pdm", "pdm_root", 0x9ac0, },
+ { IMX93_CLK_MQS1_GATE, "mqs1", "sai1_root", 0x9b00, },
+ { IMX93_CLK_MQS2_GATE, "mqs2", "sai3_root", 0x9b40, },
+ { IMX93_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, },
+ { IMX93_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, },
+ { IMX93_CLK_HSIO_32K_GATE, "hsio_32k", "clock-osc-24m", 0x9dc0, },
+ { IMX93_CLK_ENET1_GATE, "enet1", "wakeup_axi_root", 0x9e00, },
+ { IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, },
+ /* Critical because clk accessed during CPU idle */
+ { IMX93_CLK_SYS_CNT_GATE, "sys_cnt", "clock-osc-24m", 0x9e80, CLK_IS_CRITICAL},
+ { IMX93_CLK_TSTMR1_GATE, "tstmr1", "bus_aon_root", 0x9ec0, },
+ { IMX93_CLK_TSTMR2_GATE, "tstmr2", "bus_wakeup_root", 0x9f00, },
+ { IMX93_CLK_TMC_GATE, "tmc", "clock-osc-24m", 0x9f40, },
+ { IMX93_CLK_PMRO_GATE, "pmro", "clock-osc-24m", 0x9f80, }
+};
+
+static int imx93_clk_probe(struct udevice *dev)
+{
+ const struct imx93_clk_root *root;
+ const struct imx93_clk_ccgr *ccgr;
+ struct clk osc_24m_clk, osc_32k_clk, ext1_clk;
+ void __iomem *base, *anatop_base;
+ int i, ret;
+
+ clk_dm(IMX93_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0UL));
+
+ ret = clk_get_by_name(dev, "osc_24m", &osc_24m_clk);
+ if (ret)
+ return ret;
+ clk_dm(IMX93_CLK_24M, dev_get_clk_ptr(osc_24m_clk.dev));
+
+ ret = clk_get_by_name(dev, "osc_32k", &osc_32k_clk);
+ if (ret)
+ return ret;
+ clk_dm(IMX93_CLK_32K, dev_get_clk_ptr(osc_32k_clk.dev));
+
+ ret = clk_get_by_name(dev, "clk_ext1", &ext1_clk);
+ if (ret)
+ return ret;
+ clk_dm(IMX93_CLK_EXT1, dev_get_clk_ptr(ext1_clk.dev));
+
+ clk_dm(IMX93_CLK_SYS_PLL_PFD0,
+ clk_register_fixed_rate(NULL, "sys_pll_pfd0", 1000000000));
+ clk_dm(IMX93_CLK_SYS_PLL_PFD0_DIV2,
+ imx_clk_fixed_factor("sys_pll_pfd0_div2", "sys_pll_pfd0", 1, 2));
+ clk_dm(IMX93_CLK_SYS_PLL_PFD1,
+ clk_register_fixed_rate(NULL, "sys_pll_pfd1", 800000000));
+ clk_dm(IMX93_CLK_SYS_PLL_PFD1_DIV2,
+ imx_clk_fixed_factor("sys_pll_pfd1_div2", "sys_pll_pfd1", 1, 2));
+ clk_dm(IMX93_CLK_SYS_PLL_PFD2,
+ clk_register_fixed_rate(NULL, "sys_pll_pfd2", 625000000));
+ clk_dm(IMX93_CLK_SYS_PLL_PFD2_DIV2,
+ imx_clk_fixed_factor("sys_pll_pfd2_div2", "sys_pll_pfd2", 1, 2));
+
+ base = (void *)ANATOP_BASE_ADDR;
+
+ clk_dm(IMX93_CLK_ARM_PLL,
+ imx_clk_fracn_gppll_integer("arm_pll", "clock-osc-24m",
+ anatop_base + 0x1000,
+ &imx_fracn_gppll_integer));
+ clk_dm(IMX93_CLK_AUDIO_PLL,
+ imx_clk_fracn_gppll("audio_pll", "clock-osc-24m",
+ anatop_base + 0x1200, &imx_fracn_gppll));
+ clk_dm(IMX93_CLK_VIDEO_PLL,
+ imx_clk_fracn_gppll("video_pll", "clock-osc-24m",
+ anatop_base + 0x1400, &imx_fracn_gppll));
+
+ base = dev_read_addr_ptr(dev);
+ if (!base)
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(root_array); i++) {
+ root = &root_array[i];
+ clk_dm(root->clk, imx93_clk_composite_flags(root->name,
+ parent_names[root->sel],
+ 4, base + root->off, 3,
+ root->flags));
+ }
+
+ for (i = 0; i < ARRAY_SIZE(ccgr_array); i++) {
+ ccgr = &ccgr_array[i];
+ clk_dm(ccgr->clk, imx93_clk_gate(NULL, ccgr->name, ccgr->parent_name,
+ ccgr->flags, base + ccgr->off, 0, 1, 1, 3,
+ ccgr->shared_count));
+ }
+
+ clk_dm(IMX93_CLK_A55_SEL,
+ imx_clk_mux2("a55_sel", base + 0x4820, 0, 1,
+ a55_core_sels, ARRAY_SIZE(a55_core_sels)));
+
+ return 0;
+}
+
+static const struct udevice_id imx93_clk_ids[] = {
+ { .compatible = "fsl,imx93-ccm" },
+ { /* Sentinel */ },
+};
+
+U_BOOT_DRIVER(imx93_clk) = {
+ .name = "clk_imx93",
+ .id = UCLASS_CLK,
+ .of_match = imx93_clk_ids,
+ .ops = &ccf_clk_ops,
+ .probe = imx93_clk_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
index b93c0bc..1cb685e 100644
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -18,6 +18,7 @@
#include <linux/iopoll.h>
#include <clk.h>
#include <div64.h>
+#include <linux/printk.h>
#include "clk.h"
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 11f5dca..27a53ae 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -46,6 +46,34 @@
extern struct imx_pll14xx_clk imx_1443x_pll;
extern struct imx_pll14xx_clk imx_1443x_dram_pll;
+#define CLK_FRACN_GPPLL_INTEGER BIT(0)
+#define CLK_FRACN_GPPLL_FRACN BIT(1)
+
+/* NOTE: Rate table should be kept sorted in descending order. */
+struct imx_fracn_gppll_rate_table {
+ unsigned int rate;
+ unsigned int mfi;
+ unsigned int mfn;
+ unsigned int mfd;
+ unsigned int rdiv;
+ unsigned int odiv;
+};
+
+struct imx_fracn_gppll_clk {
+ const struct imx_fracn_gppll_rate_table *rate_table;
+ int rate_count;
+ int flags;
+};
+
+struct clk *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base,
+ const struct imx_fracn_gppll_clk *pll_clk);
+struct clk *imx_clk_fracn_gppll_integer(const char *name, const char *parent_name,
+ void __iomem *base,
+ const struct imx_fracn_gppll_clk *pll_clk);
+
+extern struct imx_fracn_gppll_clk imx_fracn_gppll;
+extern struct imx_fracn_gppll_clk imx_fracn_gppll_integer;
+
struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
void __iomem *base,
const struct imx_pll14xx_clk *pll_clk);
@@ -224,4 +252,18 @@
#define imx8m_clk_composite_critical(name, parent_names, reg) \
__imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
+struct clk *imx93_clk_composite_flags(const char *name,
+ const char * const *parent_names,
+ int num_parents,
+ void __iomem *reg,
+ u32 domain_id,
+ unsigned long flags);
+#define imx93_clk_composite(name, parent_names, num_parents, reg, domain_id) \
+ imx93_clk_composite_flags(name, parent_names, num_parents, reg, domain_id \
+ CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
+
+struct clk *imx93_clk_gate(struct device *dev, const char *name, const char *parent_name,
+ unsigned long flags, void __iomem *reg, u32 bit_idx, u32 val,
+ u32 mask, u32 domain_id, unsigned int *share_count);
+
#endif /* __MACH_IMX_CLK_H */
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 994b44a..cdc9d6f 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -21,3 +21,11 @@
help
Enable clock support for the Amlogic G12A SoC family, such as
the S905X/D2
+
+config CLK_MESON_A1
+ bool "Enable clock support for Amlogic A1"
+ depends on CLK && ARCH_MESON
+ default MESON_A1
+ help
+ Enable clock support for the Amlogic A1 SoC family, such as
+ the A113L
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index a486b13..d975f07 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -8,3 +8,4 @@
obj-$(CONFIG_CLK_MESON_AXG) += axg-ao.o
obj-$(CONFIG_CLK_MESON_G12A) += g12a.o
obj-$(CONFIG_CLK_MESON_G12A) += g12a-ao.o
+obj-$(CONFIG_CLK_MESON_A1) += a1.o
diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c
new file mode 100644
index 0000000..d0f5bb3
--- /dev/null
+++ b/drivers/clk/meson/a1.c
@@ -0,0 +1,735 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023 SberDevices, Inc.
+ * Author: Igor Prusov <ivprusov@salutedevices.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <regmap.h>
+#include <asm/arch/clock-a1.h>
+#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
+#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
+#include "clk_meson.h"
+
+/*
+ * This driver supports both PLL and peripherals clock sources.
+ * Following operations are supported:
+ * - calculating clock frequency on a limited tree
+ * - reading muxes and dividers
+ * - enabling/disabling gates without propagation
+ * - reparenting without rate propagation, only on muxes
+ * - setting rates with limited reparenting, only on dividers with mux parent
+ */
+
+#define NR_CLKS 154
+#define NR_PLL_CLKS 11
+
+/* External clock IDs. Those should not overlap with regular IDs */
+#define EXTERNAL_XTAL (NR_CLKS + 0)
+#define EXTERNAL_FCLK_DIV2 (NR_CLKS + 1)
+#define EXTERNAL_FCLK_DIV3 (NR_CLKS + 2)
+#define EXTERNAL_FCLK_DIV5 (NR_CLKS + 3)
+#define EXTERNAL_FCLK_DIV7 (NR_CLKS + 4)
+
+#define EXTERNAL_FIXPLL_IN (NR_PLL_CLKS + 1)
+
+#define SET_PARM_VALUE(_priv, _parm, _val) \
+ regmap_update_bits((_priv)->map, (_parm)->reg_off, \
+ SETPMASK((_parm)->width, (_parm)->shift), \
+ (_val) << (_parm)->shift)
+
+#define GET_PARM_VALUE(_priv, _parm) \
+({ \
+ uint _reg; \
+ regmap_read((_priv)->map, (_parm)->reg_off, &_reg); \
+ PARM_GET((_parm)->width, (_parm)->shift, _reg); \
+})
+
+struct meson_clk {
+ struct regmap *map;
+};
+
+/**
+ * enum meson_clk_type - The type of clock
+ * @MESON_CLK_ANY: Special value that matches any clock type
+ * @MESON_CLK_GATE: This clock is a gate
+ * @MESON_CLK_MUX: This clock is a multiplexer
+ * @MESON_CLK_DIV: This clock is a configurable divider
+ * @MESON_CLK_FIXED_DIV: This clock is a configurable divider
+ * @MESON_CLK_EXTERNAL: This is an external clock from different clock provider
+ * @MESON_CLK_PLL: This is a PLL
+ */
+enum meson_clk_type {
+ MESON_CLK_ANY = 0,
+ MESON_CLK_GATE,
+ MESON_CLK_MUX,
+ MESON_CLK_DIV,
+ MESON_CLK_FIXED_DIV,
+ MESON_CLK_EXTERNAL,
+ MESON_CLK_PLL,
+};
+
+/**
+ * struct meson_clk_info - The parameters defining a clock
+ * @name: Name of the clock
+ * @parm: Register bits description for muxes and dividers
+ * @div: Fixed divider value
+ * @parents: List of parent clock IDs
+ * @type: Clock type
+ */
+struct meson_clk_info {
+ const char *name;
+ union {
+ const struct parm *parm;
+ u8 div;
+ };
+ const unsigned int *parents;
+ const enum meson_clk_type type;
+};
+
+/**
+ * struct meson_clk_data - Clocks supported by clock provider
+ * @num_clocks: Number of clocks
+ * @clocks: Array of clock descriptions
+ *
+ */
+struct meson_clk_data {
+ const u8 num_clocks;
+ const struct meson_clk_info **clocks;
+};
+
+/* Clock description initialization macros */
+
+/* A multiplexer */
+#define CLK_MUX(_name, _reg, _shift, _width, ...) \
+ (&(struct meson_clk_info){ \
+ .parents = (const unsigned int[])__VA_ARGS__, \
+ .parm = &(struct parm) { \
+ .reg_off = (_reg), \
+ .shift = (_shift), \
+ .width = (_width), \
+ }, \
+ .name = (_name), \
+ .type = MESON_CLK_MUX, \
+ })
+
+/* A divider with an integral divisor */
+#define CLK_DIV(_name, _reg, _shift, _width, _parent) \
+ (&(struct meson_clk_info){ \
+ .parents = (const unsigned int[]) { (_parent) }, \
+ .parm = &(struct parm) { \
+ .reg_off = (_reg), \
+ .shift = (_shift), \
+ .width = (_width), \
+ }, \
+ .name = (_name), \
+ .type = MESON_CLK_DIV, \
+ })
+
+/* A fixed divider */
+#define CLK_DIV_FIXED(_name, _div, _parent) \
+ (&(struct meson_clk_info){ \
+ .parents = (const unsigned int[]) { (_parent) }, \
+ .div = (_div), \
+ .name = (_name), \
+ .type = MESON_CLK_FIXED_DIV, \
+ })
+
+/* An external clock */
+#define CLK_EXTERNAL(_name) \
+ (&(struct meson_clk_info){ \
+ .name = (_name), \
+ .parents = (const unsigned int[]) { -ENOENT }, \
+ .type = MESON_CLK_EXTERNAL, \
+ })
+
+/* A clock gate */
+#define CLK_GATE(_name, _reg, _shift, _parent) \
+ (&(struct meson_clk_info){ \
+ .parents = (const unsigned int[]) { (_parent) }, \
+ .parm = &(struct parm) { \
+ .reg_off = (_reg), \
+ .shift = (_shift), \
+ .width = 1, \
+ }, \
+ .name = (_name), \
+ .type = MESON_CLK_GATE, \
+ })
+
+/* A PLL clock */
+#define CLK_PLL(_name, _parent, ...) \
+ (&(struct meson_clk_info){ \
+ .name = (_name), \
+ .parents = (const unsigned int[]) { (_parent) }, \
+ .parm = (const struct parm[])__VA_ARGS__, \
+ .type = MESON_CLK_PLL, \
+ })
+
+/* A1 peripherals clocks */
+static const struct meson_clk_info *meson_clocks[] = {
+ [CLKID_SPIFC_SEL] = CLK_MUX("spifc_sel", A1_SPIFC_CLK_CTRL, 9, 2, {
+ EXTERNAL_FCLK_DIV2,
+ EXTERNAL_FCLK_DIV3,
+ EXTERNAL_FCLK_DIV5,
+ -ENOENT,
+ }),
+ [CLKID_SPIFC_SEL2] = CLK_MUX("spifc_sel2", A1_SPIFC_CLK_CTRL, 15, 1, {
+ CLKID_SPIFC_DIV,
+ EXTERNAL_XTAL,
+ }),
+ [CLKID_USB_BUS_SEL] = CLK_MUX("usb_bus_sel", A1_USB_BUSCLK_CTRL, 9, 2, {
+ -ENOENT,
+ CLKID_SYS,
+ EXTERNAL_FCLK_DIV3,
+ EXTERNAL_FCLK_DIV5,
+ }),
+ [CLKID_SYS] = CLK_MUX("sys", A1_SYS_CLK_CTRL0, 31, 1, {
+ CLKID_SYS_A,
+ CLKID_SYS_B,
+ }),
+ [CLKID_SYS_A_SEL] = CLK_MUX("sys_a_sel", A1_SYS_CLK_CTRL0, 10, 3, {
+ -ENOENT,
+ EXTERNAL_FCLK_DIV2,
+ EXTERNAL_FCLK_DIV3,
+ EXTERNAL_FCLK_DIV5,
+ -ENOENT,
+ -ENOENT,
+ -ENOENT,
+ -ENOENT,
+ }),
+ [CLKID_SYS_B_SEL] = CLK_MUX("sys_b_sel", A1_SYS_CLK_CTRL0, 26, 3, {
+ -ENOENT,
+ EXTERNAL_FCLK_DIV2,
+ EXTERNAL_FCLK_DIV3,
+ EXTERNAL_FCLK_DIV5,
+ -ENOENT,
+ -ENOENT,
+ -ENOENT,
+ -ENOENT,
+ }),
+
+ [CLKID_SPIFC_DIV] = CLK_DIV("spifc_div", A1_SPIFC_CLK_CTRL, 0, 8,
+ CLKID_SPIFC_SEL
+ ),
+ [CLKID_USB_BUS_DIV] = CLK_DIV("usb_bus_div", A1_USB_BUSCLK_CTRL, 0, 8,
+ CLKID_USB_BUS_SEL
+ ),
+ [CLKID_SYS_A_DIV] = CLK_DIV("sys_a_div", A1_SYS_CLK_CTRL0, 0, 10,
+ CLKID_SYS_A_SEL
+ ),
+ [CLKID_SYS_B_DIV] = CLK_DIV("sys_b_div", A1_SYS_CLK_CTRL0, 16, 10,
+ CLKID_SYS_B_SEL
+ ),
+
+ [CLKID_SPIFC] = CLK_GATE("spifc", A1_SPIFC_CLK_CTRL, 8,
+ CLKID_SPIFC_SEL2
+ ),
+ [CLKID_USB_BUS] = CLK_GATE("usb_bus", A1_USB_BUSCLK_CTRL, 8,
+ CLKID_USB_BUS_DIV
+ ),
+ [CLKID_SYS_A] = CLK_GATE("sys_a", A1_SYS_CLK_CTRL0, 13,
+ CLKID_SYS_A_DIV
+ ),
+ [CLKID_SYS_B] = CLK_GATE("sys_b", A1_SYS_CLK_CTRL0, 29,
+ CLKID_SYS_B_DIV
+ ),
+ [CLKID_FIXPLL_IN] = CLK_GATE("fixpll_in", A1_SYS_OSCIN_CTRL, 1,
+ EXTERNAL_XTAL
+ ),
+ [CLKID_USB_PHY_IN] = CLK_GATE("usb_phy_in", A1_SYS_OSCIN_CTRL, 2,
+ EXTERNAL_XTAL
+ ),
+ [CLKID_USB_CTRL_IN] = CLK_GATE("usb_ctrl_in", A1_SYS_OSCIN_CTRL, 3,
+ EXTERNAL_XTAL
+ ),
+ [CLKID_USB_CTRL] = CLK_GATE("usb_ctrl", A1_SYS_CLK_EN0, 28,
+ CLKID_SYS
+ ),
+ [CLKID_USB_PHY] = CLK_GATE("usb_phy", A1_SYS_CLK_EN0, 27,
+ CLKID_SYS
+ ),
+ [CLKID_SARADC] = CLK_GATE("saradc", A1_SAR_ADC_CLK_CTR, 8,
+ -ENOENT
+ ),
+ [CLKID_SARADC_EN] = CLK_GATE("saradc_en", A1_SYS_CLK_EN0, 13,
+ CLKID_SYS
+ ),
+
+ [EXTERNAL_XTAL] = CLK_EXTERNAL("xtal"),
+ [EXTERNAL_FCLK_DIV2] = CLK_EXTERNAL("fclk_div2"),
+ [EXTERNAL_FCLK_DIV3] = CLK_EXTERNAL("fclk_div3"),
+ [EXTERNAL_FCLK_DIV5] = CLK_EXTERNAL("fclk_div5"),
+ [EXTERNAL_FCLK_DIV7] = CLK_EXTERNAL("fclk_div7"),
+};
+
+/* A1 PLL clocks */
+static const struct meson_clk_info *meson_pll_clocks[] = {
+ [EXTERNAL_FIXPLL_IN] = CLK_EXTERNAL("fixpll_in"),
+
+ [CLKID_FIXED_PLL_DCO] = CLK_PLL("fixed_pll_dco", EXTERNAL_FIXPLL_IN, {
+ {A1_ANACTRL_FIXPLL_CTRL0, 0, 8},
+ {A1_ANACTRL_FIXPLL_CTRL0, 10, 5},
+ }),
+
+ [CLKID_FCLK_DIV2_DIV] = CLK_DIV_FIXED("fclk_div2_div", 2,
+ CLKID_FIXED_PLL
+ ),
+ [CLKID_FCLK_DIV3_DIV] = CLK_DIV_FIXED("fclk_div3_div", 3,
+ CLKID_FIXED_PLL
+ ),
+ [CLKID_FCLK_DIV5_DIV] = CLK_DIV_FIXED("fclk_div5_div", 5,
+ CLKID_FIXED_PLL
+ ),
+ [CLKID_FCLK_DIV7_DIV] = CLK_DIV_FIXED("fclk_div7_div", 7,
+ CLKID_FIXED_PLL
+ ),
+
+ [CLKID_FIXED_PLL] = CLK_GATE("fixed_pll", A1_ANACTRL_FIXPLL_CTRL0, 20,
+ CLKID_FIXED_PLL_DCO
+ ),
+ [CLKID_FCLK_DIV2] = CLK_GATE("fclk_div2", A1_ANACTRL_FIXPLL_CTRL0, 21,
+ CLKID_FCLK_DIV2_DIV
+ ),
+ [CLKID_FCLK_DIV3] = CLK_GATE("fclk_div3", A1_ANACTRL_FIXPLL_CTRL0, 22,
+ CLKID_FCLK_DIV3_DIV
+ ),
+ [CLKID_FCLK_DIV5] = CLK_GATE("fclk_div5", A1_ANACTRL_FIXPLL_CTRL0, 23,
+ CLKID_FCLK_DIV5_DIV
+ ),
+ [CLKID_FCLK_DIV7] = CLK_GATE("fclk_div7", A1_ANACTRL_FIXPLL_CTRL0, 24,
+ CLKID_FCLK_DIV7_DIV
+ ),
+};
+
+static const struct meson_clk_info *meson_clk_get_info(struct clk *clk, ulong id,
+ enum meson_clk_type type)
+{
+ struct meson_clk_data *data;
+ const struct meson_clk_info *info;
+
+ data = (struct meson_clk_data *)dev_get_driver_data(clk->dev);
+ if (id >= data->num_clocks)
+ return ERR_PTR(-EINVAL);
+
+ info = data->clocks[id];
+ if (!info)
+ return ERR_PTR(-ENOENT);
+
+ if (type != MESON_CLK_ANY && type != info->type)
+ return ERR_PTR(-EINVAL);
+
+ return info;
+}
+
+static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
+
+static int meson_set_gate(struct clk *clk, bool on)
+{
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ const struct meson_clk_info *info;
+
+ debug("%s: %sabling %lu\n", __func__, on ? "en" : "dis", clk->id);
+
+ info = meson_clk_get_info(clk, clk->id, MESON_CLK_ANY);
+ if (IS_ERR(info))
+ return PTR_ERR(info);
+
+ SET_PARM_VALUE(priv, info->parm, on);
+
+ return 0;
+}
+
+static int meson_clk_enable(struct clk *clk)
+{
+ return meson_set_gate(clk, true);
+}
+
+static int meson_clk_disable(struct clk *clk)
+{
+ return meson_set_gate(clk, false);
+}
+
+static ulong meson_div_get_rate(struct clk *clk, unsigned long id)
+{
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ u16 n;
+ ulong rate;
+ const struct meson_clk_info *info;
+
+ info = meson_clk_get_info(clk, id, MESON_CLK_DIV);
+ if (IS_ERR(info))
+ return PTR_ERR(info);
+
+ /* Actual divider value is (field value + 1), hence the increment */
+ n = GET_PARM_VALUE(priv, info->parm) + 1;
+
+ rate = meson_clk_get_rate_by_id(clk, info->parents[0]);
+
+ return rate / n;
+}
+
+static int meson_clk_get_parent(struct clk *clk, unsigned long id)
+{
+ uint reg = 0;
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ const struct meson_clk_info *info;
+
+ info = meson_clk_get_info(clk, id, MESON_CLK_ANY);
+ if (IS_ERR(info))
+ return PTR_ERR(info);
+
+ /* For muxes we read currently selected parent from register,
+ * for other types there is always only one element in parents array.
+ */
+ if (info->type == MESON_CLK_MUX) {
+ reg = GET_PARM_VALUE(priv, info->parm);
+ if (IS_ERR_VALUE(reg))
+ return reg;
+ }
+
+ return info->parents[reg];
+}
+
+static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
+{
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ const struct meson_clk_info *info;
+ const struct parm *pm, *pn;
+ ulong parent_rate_mhz;
+ unsigned int parent;
+ u16 n, m;
+
+ info = meson_clk_get_info(clk, id, MESON_CLK_ANY);
+ if (IS_ERR(info))
+ return PTR_ERR(info);
+
+ pm = &info->parm[0];
+ pn = &info->parm[1];
+
+ n = GET_PARM_VALUE(priv, pn);
+ m = GET_PARM_VALUE(priv, pm);
+
+ if (n == 0)
+ return -EINVAL;
+
+ parent = info->parents[0];
+ parent_rate_mhz = meson_clk_get_rate_by_id(clk, parent) / 1000000;
+
+ return parent_rate_mhz * m / n * 1000000;
+}
+
+static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
+{
+ ulong rate, parent;
+ const struct meson_clk_info *info;
+
+ if (IS_ERR_VALUE(id))
+ return id;
+
+ info = meson_clk_get_info(clk, id, MESON_CLK_ANY);
+ if (IS_ERR(info))
+ return PTR_ERR(info);
+
+ switch (info->type) {
+ case MESON_CLK_PLL:
+ rate = meson_pll_get_rate(clk, id);
+ break;
+ case MESON_CLK_GATE:
+ case MESON_CLK_MUX:
+ parent = meson_clk_get_parent(clk, id);
+ rate = meson_clk_get_rate_by_id(clk, parent);
+ break;
+ case MESON_CLK_DIV:
+ rate = meson_div_get_rate(clk, id);
+ break;
+ case MESON_CLK_FIXED_DIV:
+ parent = meson_clk_get_parent(clk, id);
+ rate = meson_clk_get_rate_by_id(clk, parent) / info->div;
+ break;
+ case MESON_CLK_EXTERNAL: {
+ int ret;
+ struct clk external_clk;
+
+ ret = clk_get_by_name(clk->dev, info->name, &external_clk);
+ if (ret)
+ return ret;
+
+ rate = clk_get_rate(&external_clk);
+ break;
+ }
+ default:
+ rate = -EINVAL;
+ break;
+ }
+
+ return rate;
+}
+
+static ulong meson_clk_get_rate(struct clk *clk)
+{
+ return meson_clk_get_rate_by_id(clk, clk->id);
+}
+
+/* This implements rate propagation for dividers placed after multiplexer:
+ * ---------|\
+ * ..... | |---DIV--
+ * ---------|/
+ */
+static ulong meson_composite_set_rate(struct clk *clk, ulong id, ulong rate)
+{
+ unsigned int i, best_div_val;
+ unsigned long best_delta, best_parent;
+ const struct meson_clk_info *div;
+ const struct meson_clk_info *mux;
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+
+ div = meson_clk_get_info(clk, id, MESON_CLK_DIV);
+ if (IS_ERR(div))
+ return PTR_ERR(div);
+
+ mux = meson_clk_get_info(clk, div->parents[0], MESON_CLK_MUX);
+ if (IS_ERR(mux))
+ return PTR_ERR(mux);
+
+ best_parent = -EINVAL;
+ best_delta = ULONG_MAX;
+ for (i = 0; i < (1 << mux->parm->width); i++) {
+ unsigned long parent_rate, delta;
+ unsigned int div_val;
+
+ parent_rate = meson_clk_get_rate_by_id(clk, mux->parents[i]);
+ if (IS_ERR_VALUE(parent_rate))
+ continue;
+
+ /* If overflow, try to use max divider value */
+ div_val = min(DIV_ROUND_CLOSEST(parent_rate, rate),
+ (1UL << div->parm->width));
+
+ delta = abs(rate - (parent_rate / div_val));
+ if (delta < best_delta) {
+ best_delta = delta;
+ best_div_val = div_val;
+ best_parent = i;
+ }
+ }
+
+ if (IS_ERR_VALUE(best_parent))
+ return best_parent;
+
+ SET_PARM_VALUE(priv, mux->parm, best_parent);
+ /* Divider is set to (field value + 1), hence the decrement */
+ SET_PARM_VALUE(priv, div->parm, best_div_val - 1);
+
+ return 0;
+}
+
+static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned int id, ulong rate);
+
+static ulong meson_mux_set_rate(struct clk *clk, unsigned long id, ulong rate)
+{
+ int i;
+ ulong ret = -EINVAL;
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ const struct meson_clk_info *info;
+
+ info = meson_clk_get_info(clk, id, MESON_CLK_MUX);
+ if (IS_ERR(info))
+ return PTR_ERR(info);
+
+ for (i = 0; i < (1 << info->parm->width); i++) {
+ ret = meson_clk_set_rate_by_id(clk, info->parents[i], rate);
+ if (!ret) {
+ SET_PARM_VALUE(priv, info->parm, i);
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/* Rate propagation is implemented for a subcection of a clock tree, that is
+ * required at boot stage.
+ */
+static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned int id, ulong rate)
+{
+ switch (id) {
+ case CLKID_SPIFC_DIV:
+ case CLKID_USB_BUS_DIV:
+ return meson_composite_set_rate(clk, id, rate);
+ case CLKID_SPIFC:
+ case CLKID_USB_BUS: {
+ unsigned long parent = meson_clk_get_parent(clk, id);
+
+ return meson_clk_set_rate_by_id(clk, parent, rate);
+ }
+ case CLKID_SPIFC_SEL2:
+ return meson_mux_set_rate(clk, id, rate);
+ }
+
+ return -EINVAL;
+}
+
+static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
+{
+ return meson_clk_set_rate_by_id(clk, clk->id, rate);
+}
+
+static int meson_mux_set_parent_by_id(struct clk *clk, unsigned int parent_id)
+{
+ unsigned int i, parent_index;
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ const struct meson_clk_info *info;
+
+ info = meson_clk_get_info(clk, clk->id, MESON_CLK_MUX);
+ if (IS_ERR(info))
+ return PTR_ERR(info);
+
+ parent_index = -EINVAL;
+ for (i = 0; i < (1 << info->parm->width); i++) {
+ if (parent_id == info->parents[i]) {
+ parent_index = i;
+ break;
+ }
+ }
+
+ if (IS_ERR_VALUE(parent_index))
+ return parent_index;
+
+ SET_PARM_VALUE(priv, info->parm, parent_index);
+
+ return 0;
+}
+
+static int meson_clk_set_parent(struct clk *clk, struct clk *parent_clk)
+{
+ return meson_mux_set_parent_by_id(clk, parent_clk->id);
+}
+
+static struct clk_ops meson_clk_ops = {
+ .disable = meson_clk_disable,
+ .enable = meson_clk_enable,
+ .get_rate = meson_clk_get_rate,
+ .set_rate = meson_clk_set_rate,
+ .set_parent = meson_clk_set_parent,
+};
+
+static int meson_clk_probe(struct udevice *dev)
+{
+ struct meson_clk *priv = dev_get_priv(dev);
+
+ return regmap_init_mem(dev_ofnode(dev), &priv->map);
+}
+
+struct meson_clk_data meson_a1_peripherals_info = {
+ .clocks = meson_clocks,
+ .num_clocks = ARRAY_SIZE(meson_clocks),
+};
+
+struct meson_clk_data meson_a1_pll_info = {
+ .clocks = meson_pll_clocks,
+ .num_clocks = ARRAY_SIZE(meson_pll_clocks),
+};
+
+static const struct udevice_id meson_clk_ids[] = {
+ {
+ .compatible = "amlogic,a1-peripherals-clkc",
+ .data = (ulong)&meson_a1_peripherals_info,
+ },
+ {
+ .compatible = "amlogic,a1-pll-clkc",
+ .data = (ulong)&meson_a1_pll_info,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(meson_clk) = {
+ .name = "meson-clk-a1",
+ .id = UCLASS_CLK,
+ .of_match = meson_clk_ids,
+ .priv_auto = sizeof(struct meson_clk),
+ .ops = &meson_clk_ops,
+ .probe = meson_clk_probe,
+};
+
+static const char *meson_clk_get_name(struct clk *clk, int id)
+{
+ const struct meson_clk_info *info;
+
+ info = meson_clk_get_info(clk, id, MESON_CLK_ANY);
+
+ return IS_ERR(info) ? "unknown" : info->name;
+}
+
+static int meson_clk_dump(struct clk *clk)
+{
+ const struct meson_clk_info *info;
+ struct meson_clk *priv;
+ unsigned long rate;
+ char *state, frequency[80];
+ int parent;
+
+ priv = dev_get_priv(clk->dev);
+
+ info = meson_clk_get_info(clk, clk->id, MESON_CLK_ANY);
+ if (IS_ERR(info) || !info->name)
+ return -EINVAL;
+
+ rate = clk_get_rate(clk);
+ if (IS_ERR_VALUE(rate))
+ sprintf(frequency, "unknown");
+ else
+ sprintf(frequency, "%lu", rate);
+
+ if (info->type == MESON_CLK_GATE)
+ state = GET_PARM_VALUE(priv, info->parm) ? "enabled" : "disabled";
+ else
+ state = "N/A";
+
+ parent = meson_clk_get_parent(clk, clk->id);
+ printf("%15s%20s%20s%15s\n",
+ info->name,
+ frequency,
+ meson_clk_get_name(clk, parent),
+ state);
+
+ return 0;
+}
+
+static int meson_clk_dump_dev(struct udevice *dev)
+{
+ int i;
+ struct meson_clk_data *data;
+ const char *sep = "--------------------";
+
+ printf("%s:\n", dev->name);
+ printf("%.15s%s%s%.15s\n", sep, sep, sep, sep);
+ printf("%15s%20s%20s%15s\n", "clk", "frequency", "parent", "state");
+ printf("%.15s%s%s%.15s\n", sep, sep, sep, sep);
+
+ data = (struct meson_clk_data *)dev_get_driver_data(dev);
+ for (i = 0; i < data->num_clocks; i++) {
+ meson_clk_dump(&(struct clk){
+ .dev = dev,
+ .id = i
+ });
+ }
+
+ return 0;
+}
+
+int soc_clk_dump(void)
+{
+ struct udevice *dev;
+ int i = 0;
+
+ while (!uclass_get_device(UCLASS_CLK, i++, &dev)) {
+ if (dev->driver == DM_DRIVER_GET(meson_clk)) {
+ meson_clk_dump_dev(dev);
+ printf("\n");
+ }
+ }
+
+ return 0;
+}
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 437a82c..927d62c 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -156,3 +156,12 @@
depends on CLK_RENESAS
help
Enable this to support the clocks on Renesas R9A06G032 SoC.
+
+config CLK_RZG2L
+ bool "Renesas RZ/G2L family clock support"
+ depends on CLK_RENESAS
+ select DM_RESET
+
+config CLK_R9A07G044
+ bool "RZ/G2L (R9A07G044L) clock support"
+ depends on CLK_RZG2L
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 48373e6..df7e225 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -23,3 +23,5 @@
obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
+obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o
+obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index 1f76d6b..6280061 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -47,7 +47,7 @@
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a774a1_core_clks[] = {
+static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -121,7 +121,7 @@
DEF_BASE("r", R8A774A1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
-static const struct mssr_mod_clk r8a774a1_mod_clks[] = {
+static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
DEF_MOD("tmu4", 121, R8A774A1_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A774A1_CLK_S3D2),
DEF_MOD("tmu2", 123, R8A774A1_CLK_S3D2),
@@ -276,7 +276,7 @@
(((md) & BIT(19)) >> 18) | \
(((md) & BIT(17)) >> 17))
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
{ 1, 192, 1, 192, 1, 16, },
{ 1, 192, 1, 128, 1, 16, },
diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
index b5927c7..60f4f1d 100644
--- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
@@ -46,7 +46,7 @@
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a774b1_core_clks[] = {
+static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -118,7 +118,7 @@
DEF_BASE("r", R8A774B1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
-static const struct mssr_mod_clk r8a774b1_mod_clks[] = {
+static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
DEF_MOD("tmu4", 121, R8A774B1_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A774B1_CLK_S3D2),
DEF_MOD("tmu2", 123, R8A774B1_CLK_S3D2),
@@ -272,7 +272,7 @@
(((md) & BIT(19)) >> 18) | \
(((md) & BIT(17)) >> 17))
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
{ 1, 192, 1, 192, 1, 16, },
{ 1, 192, 1, 128, 1, 16, },
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index 802a9c0..4768ceb 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -52,7 +52,7 @@
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a774c0_core_clks[] = {
+static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
@@ -131,7 +131,7 @@
DEF_GEN3_RCKSEL("r", R8A774C0_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
};
-static const struct mssr_mod_clk r8a774c0_mod_clks[] = {
+static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
DEF_MOD("tmu4", 121, R8A774C0_CLK_S0D6C),
DEF_MOD("tmu3", 122, R8A774C0_CLK_S3D2C),
DEF_MOD("tmu2", 123, R8A774C0_CLK_S3D2C),
@@ -259,7 +259,7 @@
*/
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div */
{ 1, 100, 3, 100, 3, },
{ 1, 100, 3, 58, 3, },
diff --git a/drivers/clk/renesas/r8a774e1-cpg-mssr.c b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
index 617fa76..28d8a88 100644
--- a/drivers/clk/renesas/r8a774e1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
@@ -48,7 +48,7 @@
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a774e1_core_clks[] = {
+static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -123,7 +123,7 @@
DEF_BASE("r", R8A774E1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
-static const struct mssr_mod_clk r8a774e1_mod_clks[] = {
+static const struct mssr_mod_clk r8a774e1_mod_clks[] __initconst = {
DEF_MOD("fdp1-1", 118, R8A774E1_CLK_S0D1),
DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A774E1_CLK_S0D6),
@@ -286,7 +286,7 @@
(((md) & BIT(19)) >> 18) | \
(((md) & BIT(17)) >> 17))
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
{ 1, 192, 1, 192, 1, 16, },
{ 1, 192, 1, 128, 1, 16, },
diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c b/drivers/clk/renesas/r8a7790-cpg-mssr.c
index 1f3477f..686f2af 100644
--- a/drivers/clk/renesas/r8a7790-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c
@@ -38,7 +38,7 @@
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a7790_core_clks[] = {
+static const struct cpg_core_clk r8a7790_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
@@ -88,7 +88,7 @@
DEF_DIV6P1("ssprs", R8A7790_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
};
-static const struct mssr_mod_clk r8a7790_mod_clks[] = {
+static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = {
DEF_MOD("msiof0", 0, R8A7790_CLK_MP),
DEF_MOD("vcp1", 100, R8A7790_CLK_ZS),
DEF_MOD("vcp0", 101, R8A7790_CLK_ZS),
@@ -230,7 +230,7 @@
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
{ 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
{ 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
};
diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c b/drivers/clk/renesas/r8a7791-cpg-mssr.c
index fcca7be..dcb0fd8 100644
--- a/drivers/clk/renesas/r8a7791-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c
@@ -1,10 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Renesas R8A7791 CPG MSSR driver
- *
- * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
- *
- * Based on the following driver from Linux kernel:
* r8a7791 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2015-2017 Glider bvba
@@ -43,7 +38,7 @@
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a7791_core_clks[] = {
+static struct cpg_core_clk r8a7791_core_clks[] __initdata = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
@@ -89,7 +84,7 @@
DEF_DIV6P1("ssprs", R8A7791_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
};
-static const struct mssr_mod_clk r8a7791_mod_clks[] = {
+static const struct mssr_mod_clk r8a7791_mod_clks[] __initconst = {
DEF_MOD("msiof0", 0, R8A7791_CLK_MP),
DEF_MOD("vcp0", 101, R8A7791_CLK_ZS),
DEF_MOD("vpc0", 103, R8A7791_CLK_ZS),
@@ -232,7 +227,7 @@
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
{ 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
{ 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
};
diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c
index 5b33363..496e51a 100644
--- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
@@ -37,7 +37,7 @@
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a7792_core_clks[] = {
+static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
@@ -76,7 +76,7 @@
DEF_FIXED("osc", R8A7792_CLK_OSC, CLK_PLL1, 12288, 1),
};
-static const struct mssr_mod_clk r8a7792_mod_clks[] = {
+static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
DEF_MOD("msiof0", 0, R8A7792_CLK_MP),
DEF_MOD("jpu", 106, R8A7792_CLK_M2),
DEF_MOD("tmu1", 111, R8A7792_CLK_P),
@@ -174,7 +174,7 @@
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
{ 1, 208, 106, 200 },
{ 1, 208, 88, 200 },
{ 1, 156, 80, 150 },
diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c
index b9dd88d..f1828a6 100644
--- a/drivers/clk/renesas/r8a7794-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
@@ -38,7 +38,7 @@
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a7794_core_clks[] = {
+static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
@@ -83,7 +83,7 @@
DEF_DIV6P1("mmc0", R8A7794_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
};
-static const struct mssr_mod_clk r8a7794_mod_clks[] = {
+static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
DEF_MOD("msiof0", 0, R8A7794_CLK_MP),
DEF_MOD("vcp0", 101, R8A7794_CLK_ZS),
DEF_MOD("vpc0", 103, R8A7794_CLK_ZS),
@@ -205,7 +205,7 @@
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))
-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] = {
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = {
{ 1, 208, 88, 200 },
{ 1, 156, 66, 150 },
{ 2, 240, 102, 230 },
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index 005f6a9..0e9b9cc 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -50,7 +50,7 @@
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a7795_core_clks[] = {
+static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -126,8 +126,7 @@
DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
-static const struct mssr_mod_clk r8a7795_mod_clks[] = {
- DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */
+static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A7795_CLK_S0D6),
@@ -161,7 +160,6 @@
DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1),
- DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */
DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1),
DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
@@ -186,28 +184,21 @@
DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
DEF_MOD("thermal", 522, R8A7795_CLK_CP),
DEF_MOD("pwm", 523, R8A7795_CLK_S0D12),
- DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */
DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2),
DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2),
DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2),
DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1),
DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1),
- DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */
DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1),
DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1),
- DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */
DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1),
DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1),
- DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */
- DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */
DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1),
- DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */
DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2),
DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2),
DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2),
DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1),
DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1),
- DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
DEF_MOD("ehci3", 700, R8A7795_CLK_S3D2),
@@ -220,7 +211,6 @@
DEF_MOD("cmm2", 709, R8A7795_CLK_S2D1),
DEF_MOD("cmm1", 710, R8A7795_CLK_S2D1),
DEF_MOD("cmm0", 711, R8A7795_CLK_S2D1),
- DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
DEF_MOD("csi40", 716, R8A7795_CLK_CSI0),
@@ -324,7 +314,7 @@
(((md) & BIT(19)) >> 18) | \
(((md) & BIT(17)) >> 17))
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
{ 1, 192, 1, 192, 1, 16, },
{ 1, 192, 1, 128, 1, 16, },
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 27cf62e..ea1f6d6 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -52,7 +52,7 @@
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a7796_core_clks[] = {
+static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -128,7 +128,7 @@
DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
-static const struct mssr_mod_clk r8a7796_mod_clks[] = {
+static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A7796_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A7796_CLK_S3D2),
@@ -299,7 +299,7 @@
(((md) & BIT(19)) >> 18) | \
(((md) & BIT(17)) >> 17))
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
{ 1, 192, 1, 192, 1, 16, },
{ 1, 192, 1, 128, 1, 16, },
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index 58e557a..8a5c152 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -50,7 +50,7 @@
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a77965_core_clks[] = {
+static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -124,7 +124,7 @@
DEF_BASE("r", R8A77965_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
-static const struct mssr_mod_clk r8a77965_mod_clks[] = {
+static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A77965_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A77965_CLK_S3D2),
@@ -302,7 +302,7 @@
(((md) & BIT(19)) >> 18) | \
(((md) & BIT(17)) >> 17))
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
{ 1, 192, 1, 192, 1, 16, },
{ 1, 192, 1, 128, 1, 16, },
diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c
index f5d77df..32923b4 100644
--- a/drivers/clk/renesas/r8a77970-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c
@@ -1,13 +1,12 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: GPL-2.0
/*
- * Renesas R8A77970 CPG MSSR driver
+ * r8a77970 Clock Pulse Generator / Module Standby and Software Reset
*
- * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2017-2018 Cogent Embedded Inc.
*
- * Based on the following driver from Linux kernel:
- * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
+ * Based on r8a7795-cpg-mssr.c
*
- * Copyright (C) 2016 Glider bvba
+ * Copyright (C) 2015 Glider bvba
*/
#include <common.h>
@@ -42,7 +41,7 @@
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a77970_core_clks[] = {
+static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -57,6 +56,7 @@
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
/* Core Clock Outputs */
+ DEF_FIXED("z2", R8A77970_CLK_Z2, CLK_PLL1_DIV4, 1, 1),
DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -87,7 +87,7 @@
DEF_FIXED("r", R8A77970_CLK_R, CLK_EXTALR, 1, 1),
};
-static const struct mssr_mod_clk r8a77970_mod_clks[] = {
+static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
DEF_MOD("tmu4", 121, R8A77970_CLK_S2D2),
DEF_MOD("tmu3", 122, R8A77970_CLK_S2D2),
DEF_MOD("tmu2", 123, R8A77970_CLK_S2D2),
@@ -166,7 +166,7 @@
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div */
{ 1, 192, 1, 96, 1, },
{ 1, 192, 1, 80, 1, },
diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c
index f29727d..f35032b 100644
--- a/drivers/clk/renesas/r8a77980-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -47,7 +47,7 @@
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a77980_core_clks[] = {
+static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -71,6 +71,7 @@
DEF_RATE(".oco", CLK_OCO, 32768),
/* Core Clock Outputs */
+ DEF_FIXED("z2", R8A77980_CLK_Z2, CLK_PLL2, 4, 1),
DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A77980_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -110,7 +111,7 @@
DEF_GEN3_MDSEL("r", R8A77980_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
};
-static const struct mssr_mod_clk r8a77980_mod_clks[] = {
+static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
DEF_MOD("tmu4", 121, R8A77980_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A77980_CLK_S0D6),
DEF_MOD("tmu2", 123, R8A77980_CLK_S0D6),
@@ -149,11 +150,27 @@
DEF_MOD("imp-ocv3", 529, R8A77980_CLK_S1D1),
DEF_MOD("imp-ocv2", 531, R8A77980_CLK_S1D1),
DEF_MOD("fcpvd0", 603, R8A77980_CLK_S3D1),
+ DEF_MOD("vin15", 604, R8A77980_CLK_S2D1),
+ DEF_MOD("vin14", 605, R8A77980_CLK_S2D1),
+ DEF_MOD("vin13", 608, R8A77980_CLK_S2D1),
+ DEF_MOD("vin12", 612, R8A77980_CLK_S2D1),
+ DEF_MOD("vin11", 618, R8A77980_CLK_S2D1),
DEF_MOD("vspd0", 623, R8A77980_CLK_S3D1),
+ DEF_MOD("vin10", 625, R8A77980_CLK_S2D1),
+ DEF_MOD("vin9", 627, R8A77980_CLK_S2D1),
+ DEF_MOD("vin8", 628, R8A77980_CLK_S2D1),
DEF_MOD("csi41", 715, R8A77980_CLK_CSI0),
DEF_MOD("csi40", 716, R8A77980_CLK_CSI0),
DEF_MOD("du0", 724, R8A77980_CLK_S2D1),
DEF_MOD("lvds", 727, R8A77980_CLK_S2D1),
+ DEF_MOD("vin7", 804, R8A77980_CLK_S2D1),
+ DEF_MOD("vin6", 805, R8A77980_CLK_S2D1),
+ DEF_MOD("vin5", 806, R8A77980_CLK_S2D1),
+ DEF_MOD("vin4", 807, R8A77980_CLK_S2D1),
+ DEF_MOD("vin3", 808, R8A77980_CLK_S2D1),
+ DEF_MOD("vin2", 809, R8A77980_CLK_S2D1),
+ DEF_MOD("vin1", 810, R8A77980_CLK_S2D1),
+ DEF_MOD("vin0", 811, R8A77980_CLK_S2D1),
DEF_MOD("etheravb", 812, R8A77980_CLK_S3D2),
DEF_MOD("gether", 813, R8A77980_CLK_S3D2),
DEF_MOD("imp3", 824, R8A77980_CLK_S1D1),
@@ -172,6 +189,7 @@
DEF_MOD("gpio0", 912, R8A77980_CLK_CP),
DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2),
DEF_MOD("rpc-if", 917, R8A77980_CLK_RPCD2),
+ DEF_MOD("i2c5", 919, R8A77980_CLK_S0D6),
DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6),
DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6),
DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2),
@@ -195,7 +213,7 @@
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
{ 1, 192, 1, 192, 1, 16, },
{ 1, 160, 1, 160, 1, 19, },
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index 1864af3..e5710b0 100644
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -52,7 +52,7 @@
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a77990_core_clks[] = {
+static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
@@ -132,7 +132,7 @@
DEF_GEN3_RCKSEL("r", R8A77990_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
};
-static const struct mssr_mod_clk r8a77990_mod_clks[] = {
+static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
DEF_MOD("tmu4", 121, R8A77990_CLK_S0D6C),
DEF_MOD("tmu3", 122, R8A77990_CLK_S3D2C),
DEF_MOD("tmu2", 123, R8A77990_CLK_S3D2C),
@@ -273,7 +273,7 @@
*/
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div */
{ 1, 100, 3, 100, 3, },
{ 1, 100, 3, 58, 3, },
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index 03ae863..0ef1c1d 100644
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -50,7 +50,7 @@
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a77995_core_clks[] = {
+static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
@@ -118,7 +118,7 @@
DEF_GEN3_RCKSEL("r", R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
};
-static const struct mssr_mod_clk r8a77995_mod_clks[] = {
+static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
DEF_MOD("tmu4", 121, R8A77995_CLK_S1D4C),
DEF_MOD("tmu3", 122, R8A77995_CLK_S3D2C),
DEF_MOD("tmu2", 123, R8A77995_CLK_S3D2C),
@@ -167,7 +167,7 @@
DEF_MOD("du0", 724, R8A77995_CLK_S1D1),
DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
DEF_MOD("mlp", 802, R8A77995_CLK_S2D1),
- DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
+ DEF_MOD("vin4", 807, R8A77995_CLK_S3D1),
DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4),
@@ -209,7 +209,7 @@
*/
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div */
{ 1, 100, 3, 100, 3, },
{ 1, 100, 3, 58, 3, },
diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index 6b7ec36..652bfe4 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -56,7 +56,7 @@
DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \
.offset = _offset)
-static const struct cpg_core_clk r8a779a0_core_clks[] = {
+static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -127,7 +127,7 @@
DEF_GEN4_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
};
-static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
+static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
DEF_MOD("avb0", 211, R8A779A0_CLK_S3D2),
DEF_MOD("avb1", 212, R8A779A0_CLK_S3D2),
DEF_MOD("avb2", 213, R8A779A0_CLK_S3D2),
@@ -165,14 +165,15 @@
DEF_MOD("msi3", 621, R8A779A0_CLK_MSO),
DEF_MOD("msi4", 622, R8A779A0_CLK_MSO),
DEF_MOD("msi5", 623, R8A779A0_CLK_MSO),
+ DEF_MOD("pwm0", 628, R8A779A0_CLK_S1D8),
DEF_MOD("rpc-if", 629, R8A779A0_CLK_RPCD2),
DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8),
DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8),
DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8),
DEF_MOD("scif4", 705, R8A779A0_CLK_S1D8),
DEF_MOD("sdhi0", 706, R8A779A0_CLK_SD0),
- DEF_MOD("sydm1", 709, R8A779A0_CLK_S1D2),
- DEF_MOD("sydm2", 710, R8A779A0_CLK_S1D2),
+ DEF_MOD("sys-dmac1", 709, R8A779A0_CLK_S1D2),
+ DEF_MOD("sys-dmac2", 710, R8A779A0_CLK_S1D2),
DEF_MOD("tmu0", 713, R8A779A0_CLK_CL16MCK),
DEF_MOD("tmu1", 714, R8A779A0_CLK_S1D4),
DEF_MOD("tmu2", 715, R8A779A0_CLK_S1D4),
diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
index 7aac28e..643e8b8 100644
--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -47,7 +47,7 @@
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a779f0_core_clks[] = {
+static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -123,7 +123,7 @@
DEF_GEN4_MDSEL("r", R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
};
-static const struct mssr_mod_clk r8a779f0_mod_clks[] = {
+static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
DEF_MOD("hscif0", 514, R8A779F0_CLK_SASYNCPERD1),
DEF_MOD("hscif1", 515, R8A779F0_CLK_SASYNCPERD1),
DEF_MOD("hscif2", 516, R8A779F0_CLK_SASYNCPERD1),
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 8625e8a..219024a 100644
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -56,7 +56,7 @@
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a779g0_core_clks[] = {
+static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -142,6 +142,7 @@
DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
DEF_DIV6P1("canfd", R8A779G0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
+ DEF_DIV6P1("csi", R8A779G0_CLK_CSI, CLK_PLL5_DIV4, 0x880),
DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1),
DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884),
@@ -156,11 +157,13 @@
DEF_GEN4_MDSEL("r", R8A779G0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
};
-static const struct mssr_mod_clk r8a779g0_mod_clks[] = {
+static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC),
DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC),
DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC),
DEF_MOD("canfd0", 328, R8A779G0_CLK_SASYNCPERD2),
+ DEF_MOD("csi40", 331, R8A779G0_CLK_CSI),
+ DEF_MOD("csi41", 400, R8A779G0_CLK_CSI),
DEF_MOD("dis0", 411, R8A779G0_CLK_VIOBUSD2),
DEF_MOD("dsitxlink0", 415, R8A779G0_CLK_VIOBUSD2),
DEF_MOD("dsitxlink1", 416, R8A779G0_CLK_VIOBUSD2),
@@ -177,6 +180,8 @@
DEF_MOD("i2c4", 522, R8A779G0_CLK_S0D6_PER),
DEF_MOD("i2c5", 523, R8A779G0_CLK_S0D6_PER),
DEF_MOD("irqc", 611, R8A779G0_CLK_CL16M),
+ DEF_MOD("ispcs0", 612, R8A779G0_CLK_S0D2_VIO),
+ DEF_MOD("ispcs1", 613, R8A779G0_CLK_S0D2_VIO),
DEF_MOD("msi0", 618, R8A779G0_CLK_MSO),
DEF_MOD("msi1", 619, R8A779G0_CLK_MSO),
DEF_MOD("msi2", 620, R8A779G0_CLK_MSO),
@@ -198,6 +203,22 @@
DEF_MOD("tmu3", 716, R8A779G0_CLK_SASYNCPERD2),
DEF_MOD("tmu4", 717, R8A779G0_CLK_SASYNCPERD2),
DEF_MOD("tpu0", 718, R8A779G0_CLK_SASYNCPERD4),
+ DEF_MOD("vin00", 730, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin01", 731, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin02", 800, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin03", 801, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin04", 802, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin05", 803, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin06", 804, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin07", 805, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin10", 806, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin11", 807, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin12", 808, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin13", 809, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin14", 810, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin15", 811, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin16", 812, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin17", 813, R8A779G0_CLK_S0D4_VIO),
DEF_MOD("vspd0", 830, R8A779G0_CLK_VIOBUSD2),
DEF_MOD("vspd1", 831, R8A779G0_CLK_VIOBUSD2),
DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R),
@@ -209,6 +230,9 @@
DEF_MOD("pfc1", 916, R8A779G0_CLK_CL16M),
DEF_MOD("pfc2", 917, R8A779G0_CLK_CL16M),
DEF_MOD("pfc3", 918, R8A779G0_CLK_CL16M),
+ DEF_MOD("tsc", 919, R8A779G0_CLK_CL16M),
+ DEF_MOD("ssiu", 2926, R8A779G0_CLK_S0D6_PER),
+ DEF_MOD("ssi", 2927, R8A779G0_CLK_S0D6_PER),
};
/*
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
new file mode 100644
index 0000000..c8baad1
--- /dev/null
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -0,0 +1,383 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/G2L CPG driver
+ *
+ * Copyright (C) 2021-2023 Renesas Electronics Corp.
+ */
+
+#include <dm/device.h>
+#include <dt-bindings/clock/r9a07g044-cpg.h>
+#include <linux/clk-provider.h>
+
+#include "rzg2l-cpg.h"
+
+/* Divider tables */
+static const struct clk_div_table dtable_1_8[] = {
+ {0, 1},
+ {1, 2},
+ {2, 4},
+ {3, 8},
+ {0, 0},
+};
+
+static const struct clk_div_table dtable_1_32[] = {
+ {0, 1},
+ {1, 2},
+ {2, 4},
+ {3, 8},
+ {4, 32},
+ {0, 0},
+};
+
+static const struct clk_div_table dtable_16_128[] = {
+ {0, 16},
+ {1, 32},
+ {2, 64},
+ {3, 128},
+ {0, 0},
+};
+
+/* Mux clock tables */
+static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
+static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" };
+static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
+static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
+static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
+
+static const struct {
+ struct cpg_core_clk common[56];
+} core_clks = {
+ .common = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
+ DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
+ DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
+ DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
+ DEF_FIXED(".pll2_533", CLK_PLL2_533, CLK_PLL2, 1, 3),
+ DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
+ DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),
+ DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
+
+ DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
+ DEF_FIXED(".pll5_fout3", CLK_PLL5_FOUT3, CLK_PLL5, 1, 6),
+
+ DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
+
+ DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
+ DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2),
+ DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3),
+ DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2),
+ DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2),
+
+ DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
+ DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),
+
+ DEF_FIXED(".pll2_533_div2", CLK_PLL2_533_DIV2, CLK_PLL2_533, 1, 2),
+
+ DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
+ DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2),
+ DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
+ DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
+ DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3),
+ DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32),
+
+ DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),
+ DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
+ DEF_MUX_RO(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2, sel_gpu2),
+ DEF_PLL5_FOUTPOSTDIV(".pll5_foutpostdiv", CLK_PLL5_FOUTPOSTDIV, CLK_EXTAL),
+ DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2),
+ DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4, sel_pll5_4),
+ DEF_DIV(".div_dsi_lpclk", CLK_DIV_DSI_LPCLK, CLK_PLL2_533_DIV2,
+ DIVDSILPCLK, dtable_16_128),
+
+ /* Core output clk */
+ DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8),
+ DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32),
+ DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
+ DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),
+ DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32),
+ DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),
+ DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32),
+ DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
+ DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
+ DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, sel_pll6_2),
+ DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
+ DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
+ DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, sel_shdi),
+ DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, sel_shdi),
+ DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
+ DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
+ DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8),
+ DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1),
+ DEF_FIXED("M2", R9A07G044_CLK_M2, CLK_PLL3_533, 1, 2),
+ DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G044_CLK_M2, 1, 2),
+ DEF_DSI_DIV("DSI_DIV", CLK_DSI_DIV, CLK_SEL_PLL5_4, CLK_SET_RATE_PARENT),
+ DEF_FIXED("M3", R9A07G044_CLK_M3, CLK_DSI_DIV, 1, 1),
+ DEF_FIXED("M4", R9A07G044_CLK_M4, CLK_DIV_DSI_LPCLK, 1, 1),
+ },
+};
+
+static const struct {
+ struct rzg2l_mod_clk common[79];
+} mod_clks = {
+ .common = {
+ DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
+ 0x514, 0),
+ DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
+ 0x518, 0),
+ DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
+ 0x518, 1),
+ DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1,
+ 0x52c, 0),
+ DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
+ 0x52c, 1),
+ DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0,
+ 0x534, 0),
+ DEF_MOD("ostm1_pclk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0,
+ 0x534, 1),
+ DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
+ 0x534, 2),
+ DEF_MOD("mtu_x_mck", R9A07G044_MTU_X_MCK_MTU3, R9A07G044_CLK_P0,
+ 0x538, 0),
+ DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0,
+ 0x540, 0),
+ DEF_MOD("poeg_a_clkp", R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0,
+ 0x544, 0),
+ DEF_MOD("poeg_b_clkp", R9A07G044_POEG_B_CLKP, R9A07G044_CLK_P0,
+ 0x544, 1),
+ DEF_MOD("poeg_c_clkp", R9A07G044_POEG_C_CLKP, R9A07G044_CLK_P0,
+ 0x544, 2),
+ DEF_MOD("poeg_d_clkp", R9A07G044_POEG_D_CLKP, R9A07G044_CLK_P0,
+ 0x544, 3),
+ DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,
+ 0x548, 0),
+ DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
+ 0x548, 1),
+ DEF_MOD("wdt1_pclk", R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0,
+ 0x548, 2),
+ DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK,
+ 0x548, 3),
+ DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1,
+ 0x550, 0),
+ DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0,
+ 0x550, 1),
+ DEF_MOD("sdhi0_imclk", R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4,
+ 0x554, 0),
+ DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4,
+ 0x554, 1),
+ DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0,
+ 0x554, 2),
+ DEF_MOD("sdhi0_aclk", R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1,
+ 0x554, 3),
+ DEF_MOD("sdhi1_imclk", R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4,
+ 0x554, 4),
+ DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4,
+ 0x554, 5),
+ DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1,
+ 0x554, 6),
+ DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1,
+ 0x554, 7),
+ DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G,
+ 0x558, 0),
+ DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1,
+ 0x558, 1),
+ DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
+ 0x558, 2),
+ DEF_MOD("cru_sysclk", R9A07G044_CRU_SYSCLK, CLK_M2_DIV2,
+ 0x564, 0),
+ DEF_MOD("cru_vclk", R9A07G044_CRU_VCLK, R9A07G044_CLK_M2,
+ 0x564, 1),
+ DEF_MOD("cru_pclk", R9A07G044_CRU_PCLK, R9A07G044_CLK_ZT,
+ 0x564, 2),
+ DEF_MOD("cru_aclk", R9A07G044_CRU_ACLK, R9A07G044_CLK_M0,
+ 0x564, 3),
+ DEF_MOD("dsi_pll_clk", R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1,
+ 0x568, 0),
+ DEF_MOD("dsi_sys_clk", R9A07G044_MIPI_DSI_SYSCLK, CLK_M2_DIV2,
+ 0x568, 1),
+ DEF_MOD("dsi_aclk", R9A07G044_MIPI_DSI_ACLK, R9A07G044_CLK_P1,
+ 0x568, 2),
+ DEF_MOD("dsi_pclk", R9A07G044_MIPI_DSI_PCLK, R9A07G044_CLK_P2,
+ 0x568, 3),
+ DEF_MOD("dsi_vclk", R9A07G044_MIPI_DSI_VCLK, R9A07G044_CLK_M3,
+ 0x568, 4),
+ DEF_MOD("dsi_lpclk", R9A07G044_MIPI_DSI_LPCLK, R9A07G044_CLK_M4,
+ 0x568, 5),
+ DEF_COUPLED("lcdc_a", R9A07G044_LCDC_CLK_A, R9A07G044_CLK_M0,
+ 0x56c, 0),
+ DEF_COUPLED("lcdc_p", R9A07G044_LCDC_CLK_P, R9A07G044_CLK_ZT,
+ 0x56c, 0),
+ DEF_MOD("lcdc_clk_d", R9A07G044_LCDC_CLK_D, R9A07G044_CLK_M3,
+ 0x56c, 1),
+ DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
+ 0x570, 0),
+ DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
+ 0x570, 1),
+ DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0,
+ 0x570, 2),
+ DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0,
+ 0x570, 3),
+ DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0,
+ 0x570, 4),
+ DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0,
+ 0x570, 5),
+ DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0,
+ 0x570, 6),
+ DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0,
+ 0x570, 7),
+ DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1,
+ 0x578, 0),
+ DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1,
+ 0x578, 1),
+ DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1,
+ 0x578, 2),
+ DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1,
+ 0x578, 3),
+ DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0,
+ 0x57c, 0),
+ DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT,
+ 0x57c, 0),
+ DEF_COUPLED("eth1_axi", R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0,
+ 0x57c, 1),
+ DEF_COUPLED("eth1_chi", R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT,
+ 0x57c, 1),
+ DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0,
+ 0x580, 0),
+ DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0,
+ 0x580, 1),
+ DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0,
+ 0x580, 2),
+ DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0,
+ 0x580, 3),
+ DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
+ 0x584, 0),
+ DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
+ 0x584, 1),
+ DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0,
+ 0x584, 2),
+ DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0,
+ 0x584, 3),
+ DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0,
+ 0x584, 4),
+ DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
+ 0x588, 0),
+ DEF_MOD("sci1", R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0,
+ 0x588, 1),
+ DEF_MOD("rspi0", R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0,
+ 0x590, 0),
+ DEF_MOD("rspi1", R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0,
+ 0x590, 1),
+ DEF_MOD("rspi2", R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0,
+ 0x590, 2),
+ DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,
+ 0x594, 0),
+ DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
+ 0x598, 0),
+ DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU,
+ 0x5a8, 0),
+ DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0,
+ 0x5a8, 1),
+ DEF_MOD("tsu_pclk", R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU,
+ 0x5ac, 0),
+ },
+};
+
+static const struct rzg2l_reset r9a07g044_resets[] = {
+ DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
+ DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
+ DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
+ DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
+ DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
+ DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
+ DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
+ DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
+ DEF_RST(R9A07G044_MTU_X_PRESET_MTU3, 0x838, 0),
+ DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0),
+ DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0),
+ DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1),
+ DEF_RST(R9A07G044_POEG_C_RST, 0x844, 2),
+ DEF_RST(R9A07G044_POEG_D_RST, 0x844, 3),
+ DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
+ DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
+ DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
+ DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
+ DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
+ DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
+ DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
+ DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
+ DEF_RST(R9A07G044_CRU_CMN_RSTB, 0x864, 0),
+ DEF_RST(R9A07G044_CRU_PRESETN, 0x864, 1),
+ DEF_RST(R9A07G044_CRU_ARESETN, 0x864, 2),
+ DEF_RST(R9A07G044_MIPI_DSI_CMN_RSTB, 0x868, 0),
+ DEF_RST(R9A07G044_MIPI_DSI_ARESET_N, 0x868, 1),
+ DEF_RST(R9A07G044_MIPI_DSI_PRESET_N, 0x868, 2),
+ DEF_RST(R9A07G044_LCDC_RESET_N, 0x86c, 0),
+ DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
+ DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
+ DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
+ DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3),
+ DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0),
+ DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),
+ DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),
+ DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3),
+ DEF_RST(R9A07G044_ETH0_RST_HW_N, 0x87c, 0),
+ DEF_RST(R9A07G044_ETH1_RST_HW_N, 0x87c, 1),
+ DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0),
+ DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1),
+ DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2),
+ DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3),
+ DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
+ DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
+ DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
+ DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
+ DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
+ DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
+ DEF_RST(R9A07G044_SCI1_RST, 0x888, 1),
+ DEF_RST(R9A07G044_RSPI0_RST, 0x890, 0),
+ DEF_RST(R9A07G044_RSPI1_RST, 0x890, 1),
+ DEF_RST(R9A07G044_RSPI2_RST, 0x890, 2),
+ DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0),
+ DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1),
+ DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),
+ DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1),
+ DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),
+ DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
+ DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
+ DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0),
+};
+
+const struct rzg2l_cpg_info r9a07g044_cpg_info = {
+ /* Core Clocks */
+ .core_clks = core_clks.common,
+ .num_core_clks = ARRAY_SIZE(core_clks.common),
+
+ /* Module Clocks */
+ .mod_clks = mod_clks.common,
+ .num_mod_clks = ARRAY_SIZE(mod_clks.common),
+ .num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
+
+ /* Resets */
+ .resets = r9a07g044_resets,
+ .num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
+
+ .has_clk_mon_regs = true,
+};
+
+static const struct udevice_id r9a07g044_cpg_ids[] = {
+ {
+ .compatible = "renesas,r9a07g044-cpg",
+ .data = (unsigned long)&r9a07g044_cpg_info,
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(r9a07g044_cpg) = {
+ .name = "r9a07g044-cpg",
+ .id = UCLASS_NOP,
+ .of_match = r9a07g044_cpg_ids,
+ .bind = rzg2l_cpg_bind,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
new file mode 100644
index 0000000..e54508c
--- /dev/null
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -0,0 +1,504 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/G2L Clock Pulse Generator
+ *
+ * Copyright (C) 2021-2023 Renesas Electronics Corp.
+ *
+ * Based on renesas-cpg-mssr.c
+ *
+ * Copyright (C) 2015 Glider bvba
+ * Copyright (C) 2013 Ideas On Board SPRL
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ */
+
+#include <asm/io.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
+#include <dm/lists.h>
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+#include <linux/clk-provider.h>
+#include <linux/iopoll.h>
+#include <reset-uclass.h>
+#include <reset.h>
+
+#include "rzg2l-cpg.h"
+
+#define CLK_MON_R(reg) (0x180 + (reg))
+
+static ulong rzg2l_cpg_clk_get_rate_by_id(struct udevice *dev, unsigned int id);
+static ulong rzg2l_cpg_clk_get_rate_by_name(struct udevice *dev, const char *name);
+
+struct rzg2l_cpg_data {
+ void __iomem *base;
+ struct rzg2l_cpg_info *info;
+};
+
+/*
+ * The top 16 bits of the clock ID are used to identify if it is a core clock or
+ * a module clock.
+ */
+#define CPG_CLK_TYPE_SHIFT 16
+#define CPG_CLK_ID_MASK 0xffff
+#define CPG_CLK_ID(x) ((x) & CPG_CLK_ID_MASK)
+#define CPG_CLK_PACK(type, id) (((type) << CPG_CLK_TYPE_SHIFT) | CPG_CLK_ID(id))
+
+static inline bool is_mod_clk(unsigned int id)
+{
+ return (id >> CPG_CLK_TYPE_SHIFT) == CPG_MOD;
+}
+
+static int rzg2l_cpg_clk_set(struct clk *clk, bool enable)
+{
+ struct rzg2l_cpg_data *data =
+ (struct rzg2l_cpg_data *)dev_get_driver_data(clk->dev);
+ const unsigned int cpg_clk_id = CPG_CLK_ID(clk->id);
+ const struct rzg2l_mod_clk *mod_clk = NULL;
+ u32 value;
+ unsigned int i;
+
+ dev_dbg(clk->dev, "%s %s clock %u\n", enable ? "enable" : "disable",
+ is_mod_clk(clk->id) ? "module" : "core", cpg_clk_id);
+ if (!is_mod_clk(clk->id)) {
+ dev_err(clk->dev, "ID %lu is not a module clock\n", clk->id);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < data->info->num_mod_clks; i++) {
+ if (data->info->mod_clks[i].id == cpg_clk_id) {
+ mod_clk = &data->info->mod_clks[i];
+ break;
+ }
+ }
+
+ if (!mod_clk) {
+ dev_err(clk->dev, "Module clock %u not found\n", cpg_clk_id);
+ return -ENODEV;
+ }
+
+ value = BIT(mod_clk->bit) << 16;
+ if (enable)
+ value |= BIT(mod_clk->bit);
+ writel(value, data->base + mod_clk->off);
+
+ if (enable && readl_poll_timeout(data->base + CLK_MON_R(mod_clk->off),
+ value, (value & BIT(mod_clk->bit)),
+ 10)) {
+ dev_err(clk->dev, "Timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int rzg2l_cpg_clk_enable(struct clk *clk)
+{
+ return rzg2l_cpg_clk_set(clk, true);
+}
+
+static int rzg2l_cpg_clk_disable(struct clk *clk)
+{
+ return rzg2l_cpg_clk_set(clk, false);
+}
+
+static int rzg2l_cpg_clk_of_xlate(struct clk *clk,
+ struct ofnode_phandle_args *args)
+{
+ struct rzg2l_cpg_data *data =
+ (struct rzg2l_cpg_data *)dev_get_driver_data(clk->dev);
+ u32 cpg_clk_type, cpg_clk_id;
+ bool found = false;
+ unsigned int i;
+
+ if (args->args_count != 2) {
+ dev_dbg(clk->dev, "Invalid args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ cpg_clk_type = args->args[0];
+ cpg_clk_id = args->args[1];
+
+ switch (cpg_clk_type) {
+ case CPG_CORE:
+ for (i = 0; i < data->info->num_core_clks; i++) {
+ if (data->info->core_clks[i].id == cpg_clk_id) {
+ found = true;
+ break;
+ }
+ }
+ if (!found) {
+ dev_dbg(clk->dev,
+ "Invalid second argument %u: Must be a valid core clock ID\n",
+ cpg_clk_id);
+ return -EINVAL;
+ }
+ break;
+ case CPG_MOD:
+ for (i = 0; i < data->info->num_mod_clks; i++) {
+ if (data->info->mod_clks[i].id == cpg_clk_id) {
+ found = true;
+ break;
+ }
+ }
+ if (!found) {
+ dev_dbg(clk->dev,
+ "Invalid second argument %u: Must be a valid module clock ID\n",
+ cpg_clk_id);
+ return -EINVAL;
+ }
+ break;
+ default:
+ dev_dbg(clk->dev,
+ "Invalid first argument %u: Must be CPG_CORE or CPG_MOD\n",
+ cpg_clk_type);
+ return -EINVAL;
+ }
+
+ clk->id = CPG_CLK_PACK(cpg_clk_type, cpg_clk_id);
+
+ return 0;
+}
+
+static ulong rzg2l_sdhi_clk_get_rate(struct udevice *dev, const struct cpg_core_clk *cc)
+{
+ struct rzg2l_cpg_data *data =
+ (struct rzg2l_cpg_data *)dev_get_driver_data(dev);
+ const ulong offset = CPG_CONF_OFFSET(cc->conf);
+ const int shift = CPG_CONF_BITPOS(cc->conf);
+ const u32 mask = CPG_CONF_BITMASK(cc->conf);
+ unsigned int sel;
+
+ sel = (readl(data->base + offset) >> shift) & mask;
+
+ if (!sel || sel > cc->num_parents) {
+ dev_err(dev, "Invalid SEL_SDHI%d_SET value %u\n", shift / 4, sel);
+ return -EIO;
+ }
+ return rzg2l_cpg_clk_get_rate_by_name(dev, cc->parent_names[sel - 1]);
+}
+
+static ulong rzg2l_div_clk_get_rate(struct udevice *dev, const struct cpg_core_clk *cc)
+{
+ struct rzg2l_cpg_data *data =
+ (struct rzg2l_cpg_data *)dev_get_driver_data(dev);
+ const ulong offset = CPG_CONF_OFFSET(cc->conf);
+ const int shift = CPG_CONF_BITPOS(cc->conf);
+ const u32 mask = CPG_CONF_BITMASK(cc->conf);
+ unsigned int sel, i;
+
+ sel = (readl(data->base + offset) >> shift) & mask;
+
+ for (i = 0; cc->dtable[i].div; i++) {
+ if (cc->dtable[i].val == sel)
+ return rzg2l_cpg_clk_get_rate_by_id(dev, cc->parent) / cc->dtable[i].div;
+ }
+ dev_err(dev, "Invalid selector value %u for clock %s\n", sel, cc->name);
+ return -EINVAL;
+}
+
+static ulong rzg2l_core_clk_get_rate(struct udevice *dev, const struct cpg_core_clk *cc)
+{
+ switch (cc->type) {
+ case CLK_TYPE_FF:
+ const ulong parent_rate = rzg2l_cpg_clk_get_rate_by_id(dev, cc->parent);
+ return parent_rate * cc->mult / cc->div;
+ case CLK_TYPE_IN:
+ struct clk clk_in;
+ clk_get_by_name(dev, cc->name, &clk_in);
+ return clk_get_rate(&clk_in);
+ case CLK_TYPE_SD_MUX:
+ return rzg2l_sdhi_clk_get_rate(dev, cc);
+ case CLK_TYPE_DIV:
+ return rzg2l_div_clk_get_rate(dev, cc);
+ default:
+ dev_err(dev, "get_rate needed for clock %u, type %d\n", cc->id, cc->type);
+ return -ENOSYS;
+ }
+}
+
+static ulong rzg2l_cpg_clk_get_rate_by_id(struct udevice *dev, unsigned int id)
+{
+ struct rzg2l_cpg_data *data =
+ (struct rzg2l_cpg_data *)dev_get_driver_data(dev);
+ const unsigned int cpg_clk_id = CPG_CLK_ID(id);
+ unsigned int i;
+
+ if (is_mod_clk(id)) {
+ for (i = 0; i < data->info->num_mod_clks; i++) {
+ if (data->info->mod_clks[i].id == cpg_clk_id)
+ return rzg2l_cpg_clk_get_rate_by_id(dev,
+ data->info->mod_clks[i].parent);
+ }
+
+ dev_err(dev, "Module clock ID %u not found\n", cpg_clk_id);
+ return -ENODEV;
+ }
+
+ for (i = 0; i < data->info->num_core_clks; i++) {
+ if (data->info->core_clks[i].id == cpg_clk_id)
+ return rzg2l_core_clk_get_rate(dev, &data->info->core_clks[i]);
+ }
+
+ dev_err(dev, "Core clock ID %u not found\n", cpg_clk_id);
+ return -ENODEV;
+}
+
+static ulong rzg2l_cpg_clk_get_rate_by_name(struct udevice *dev, const char *name)
+{
+ struct rzg2l_cpg_data *data =
+ (struct rzg2l_cpg_data *)dev_get_driver_data(dev);
+ unsigned int i;
+
+ for (i = 0; i < data->info->num_mod_clks; i++) {
+ if (!strcmp(name, data->info->mod_clks[i].name))
+ return rzg2l_cpg_clk_get_rate_by_id(dev, data->info->mod_clks[i].parent);
+ }
+ for (i = 0; i < data->info->num_core_clks; i++) {
+ if (!strcmp(name, data->info->core_clks[i].name))
+ return rzg2l_core_clk_get_rate(dev, &data->info->core_clks[i]);
+ }
+
+ dev_err(dev, "Clock name %s not found\n", name);
+ return -EINVAL;
+}
+
+static ulong rzg2l_cpg_clk_get_rate(struct clk *clk)
+{
+ return rzg2l_cpg_clk_get_rate_by_id(clk->dev, clk->id);
+}
+
+static ulong rzg2l_sdhi_clk_set_rate(struct udevice *dev, const struct cpg_core_clk *cc, ulong rate)
+{
+ struct rzg2l_cpg_data *data =
+ (struct rzg2l_cpg_data *)dev_get_driver_data(dev);
+ const ulong offset = CPG_CONF_OFFSET(cc->conf);
+ const int shift = CPG_CONF_BITPOS(cc->conf);
+ int channel, new_sel, prev_sel;
+ ulong target_rate;
+ unsigned int i;
+ u32 value;
+
+ prev_sel = (readl(data->base + offset) >> shift) & 0x3;
+ channel = shift / 4;
+
+ /*
+ * Round the requested rate down, unless it is below the minimum
+ * supported rate. Assume that the parent clock names are listed in
+ * order of descending rate.
+ */
+ for (i = 0; i < cc->num_parents; i++) {
+ target_rate = rzg2l_cpg_clk_get_rate_by_name(dev, cc->parent_names[i]);
+ if (rate >= target_rate) {
+ new_sel = i + 1;
+ break;
+ }
+ }
+ if (!new_sel)
+ new_sel = cc->num_parents - 1;
+
+ if (new_sel == prev_sel)
+ return target_rate;
+ dev_dbg(dev, "sdhi set_rate rate=%lu target_rate=%lu sel=%d\n",
+ rate, target_rate, new_sel);
+
+ /*
+ * As per the HW manual, we should not directly switch from 533 MHz to
+ * 400 MHz and vice versa. To change the setting from 2’b01 (533 MHz)
+ * to 2’b10 (400 MHz) or vice versa, Switch to 2’b11 (266 MHz) first,
+ * and then switch to the target setting (2’b01 (533 MHz) or 2’b10
+ * (400 MHz)).
+ */
+ if (new_sel != SEL_SDHI_266MHz && prev_sel != SEL_SDHI_266MHz) {
+ u32 waitbit;
+ int ret;
+
+ dev_dbg(dev, "sdhi set_rate via 266MHz\n");
+ value = (SEL_SDHI_WRITE_ENABLE | SEL_SDHI_266MHz) << shift;
+ writel(value, data->base + offset);
+
+ /* Wait for the switch to complete. */
+ waitbit = channel ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS;
+ ret = readl_poll_timeout(data->base + CPG_CLKSTATUS, value,
+ !(value & waitbit),
+ CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
+ if (ret) {
+ dev_err(dev, "Failed to switch SDHI%d clock source\n", channel);
+ return -EIO;
+ }
+ }
+
+ value = (SEL_SDHI_WRITE_ENABLE | new_sel) << shift;
+ writel(value, data->base + offset);
+
+ return target_rate;
+}
+
+static ulong rzg2l_core_clk_set_rate(struct udevice *dev, const struct cpg_core_clk *cc, ulong rate)
+{
+ if (cc->type == CLK_TYPE_SD_MUX)
+ return rzg2l_sdhi_clk_set_rate(dev, cc, rate);
+
+ /*
+ * The sdhi driver calls clk_set_rate for SD0_DIV4 and SD1_DIV4, even
+ * though they're in a fixed relationship with SD0 and SD1 respectively.
+ * To allow the driver to proceed, simply return the current rates
+ * without making any change.
+ */
+ if (cc->id == CLK_SD0_DIV4 || cc->id == CLK_SD1_DIV4)
+ return rzg2l_core_clk_get_rate(dev, cc);
+
+ dev_err(dev, "set_rate needed for clock %u, type %d\n", cc->id, cc->type);
+ return -ENOSYS;
+}
+
+static ulong rzg2l_cpg_clk_set_rate_by_id(struct udevice *dev, unsigned int id, ulong rate)
+{
+ struct rzg2l_cpg_data *data =
+ (struct rzg2l_cpg_data *)dev_get_driver_data(dev);
+ const unsigned int cpg_clk_id = CPG_CLK_ID(id);
+ unsigned int i;
+
+ if (is_mod_clk(id)) {
+ for (i = 0; i < data->info->num_mod_clks; i++) {
+ if (data->info->mod_clks[i].id == cpg_clk_id)
+ return rzg2l_cpg_clk_set_rate_by_id(dev,
+ data->info->mod_clks[i].parent,
+ rate);
+ }
+
+ dev_err(dev, "Module clock ID %u not found\n", cpg_clk_id);
+ return -ENODEV;
+ }
+
+ for (i = 0; i < data->info->num_core_clks; i++) {
+ if (data->info->core_clks[i].id == cpg_clk_id)
+ return rzg2l_core_clk_set_rate(dev, &data->info->core_clks[i], rate);
+ }
+
+ dev_err(dev, "Core clock ID %u not found\n", cpg_clk_id);
+ return -ENODEV;
+}
+
+static ulong rzg2l_cpg_clk_set_rate(struct clk *clk, ulong rate)
+{
+ return rzg2l_cpg_clk_set_rate_by_id(clk->dev, clk->id, rate);
+}
+
+static const struct clk_ops rzg2l_cpg_clk_ops = {
+ .enable = rzg2l_cpg_clk_enable,
+ .disable = rzg2l_cpg_clk_disable,
+ .of_xlate = rzg2l_cpg_clk_of_xlate,
+ .get_rate = rzg2l_cpg_clk_get_rate,
+ .set_rate = rzg2l_cpg_clk_set_rate,
+};
+
+U_BOOT_DRIVER(rzg2l_cpg_clk) = {
+ .name = "rzg2l-cpg-clk",
+ .id = UCLASS_CLK,
+ .ops = &rzg2l_cpg_clk_ops,
+ .flags = DM_FLAG_VITAL,
+};
+
+static int rzg2l_cpg_rst_set(struct reset_ctl *reset_ctl, bool asserted)
+{
+ struct rzg2l_cpg_data *data =
+ (struct rzg2l_cpg_data *)dev_get_driver_data(reset_ctl->dev);
+ const struct rzg2l_reset *rst;
+ u32 value;
+
+ dev_dbg(reset_ctl->dev, "%s %lu\n", asserted ? "assert" : "deassert", reset_ctl->id);
+ if (reset_ctl->id >= data->info->num_resets) {
+ dev_err(reset_ctl->dev, "Invalid reset id %lu\n", reset_ctl->id);
+ return -EINVAL;
+ }
+ rst = &data->info->resets[reset_ctl->id];
+
+ value = BIT(rst->bit) << 16;
+ if (!asserted)
+ value |= BIT(rst->bit);
+ writel(value, data->base + rst->off);
+
+ return 0;
+}
+
+static int rzg2l_cpg_rst_assert(struct reset_ctl *reset_ctl)
+{
+ return rzg2l_cpg_rst_set(reset_ctl, true);
+}
+
+static int rzg2l_cpg_rst_deassert(struct reset_ctl *reset_ctl)
+{
+ return rzg2l_cpg_rst_set(reset_ctl, false);
+}
+
+static int rzg2l_cpg_rst_of_xlate(struct reset_ctl *reset_ctl,
+ struct ofnode_phandle_args *args)
+{
+ struct rzg2l_cpg_data *data =
+ (struct rzg2l_cpg_data *)dev_get_driver_data(reset_ctl->dev);
+
+ if (args->args[0] >= data->info->num_resets)
+ return -EINVAL;
+
+ reset_ctl->id = args->args[0];
+ return 0;
+}
+
+static const struct reset_ops rzg2l_cpg_rst_ops = {
+ .rst_assert = rzg2l_cpg_rst_assert,
+ .rst_deassert = rzg2l_cpg_rst_deassert,
+ .of_xlate = rzg2l_cpg_rst_of_xlate,
+};
+
+U_BOOT_DRIVER(rzg2l_cpg_rst) = {
+ .name = "rzg2l-cpg-rst",
+ .id = UCLASS_RESET,
+ .ops = &rzg2l_cpg_rst_ops,
+ .flags = DM_FLAG_VITAL,
+};
+
+int rzg2l_cpg_bind(struct udevice *parent)
+{
+ struct udevice *cdev, *rdev;
+ struct rzg2l_cpg_data *data;
+ struct driver *drv;
+ int ret;
+
+ data = devm_kmalloc(parent, sizeof(*data), 0);
+ if (!data)
+ return -ENOMEM;
+
+ data->base = dev_read_addr_ptr(parent);
+ if (!data->base)
+ return -EINVAL;
+
+ data->info = (struct rzg2l_cpg_info *)dev_get_driver_data(parent);
+ if (!data->info)
+ return -EINVAL;
+
+ drv = lists_driver_lookup_name("rzg2l-cpg-clk");
+ if (!drv)
+ return -ENOENT;
+
+ ret = device_bind_with_driver_data(parent, drv, parent->name,
+ (ulong)data, dev_ofnode(parent),
+ &cdev);
+ if (ret)
+ return ret;
+
+ drv = lists_driver_lookup_name("rzg2l-cpg-rst");
+ if (!drv) {
+ device_unbind(cdev);
+ return -ENOENT;
+ }
+
+ ret = device_bind_with_driver_data(parent, drv, parent->name,
+ (ulong)data, dev_ofnode(parent),
+ &rdev);
+ if (ret)
+ device_unbind(cdev);
+
+ return ret;
+}
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
new file mode 100644
index 0000000..7cb6c48
--- /dev/null
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -0,0 +1,319 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * RZ/G2L Clock Pulse Generator
+ *
+ * Copyright (C) 2021-2023 Renesas Electronics Corp.
+ *
+ */
+
+#ifndef __RENESAS_RZG2L_CPG_H__
+#define __RENESAS_RZG2L_CPG_H__
+
+#define CPG_SIPLL5_STBY 0x140
+#define CPG_SIPLL5_CLK1 0x144
+#define CPG_SIPLL5_CLK3 0x14C
+#define CPG_SIPLL5_CLK4 0x150
+#define CPG_SIPLL5_CLK5 0x154
+#define CPG_SIPLL5_MON 0x15C
+#define CPG_PL1_DDIV 0x200
+#define CPG_PL2_DDIV 0x204
+#define CPG_PL3A_DDIV 0x208
+#define CPG_PL6_DDIV 0x210
+#define CPG_PL2SDHI_DSEL 0x218
+#define CPG_CLKSTATUS 0x280
+#define CPG_PL3_SSEL 0x408
+#define CPG_PL6_SSEL 0x414
+#define CPG_PL6_ETH_SSEL 0x418
+#define CPG_PL5_SDIV 0x420
+#define CPG_RST_MON 0x680
+#define CPG_OTHERFUNC1_REG 0xBE8
+
+#define CPG_SIPLL5_STBY_RESETB BIT(0)
+#define CPG_SIPLL5_STBY_RESETB_WEN BIT(16)
+#define CPG_SIPLL5_STBY_SSCG_EN_WEN BIT(18)
+#define CPG_SIPLL5_STBY_DOWNSPREAD_WEN BIT(20)
+#define CPG_SIPLL5_CLK4_RESV_LSB 0xFF
+#define CPG_SIPLL5_MON_PLL5_LOCK BIT(4)
+
+#define CPG_OTHERFUNC1_REG_RES0_ON_WEN BIT(16)
+
+#define CPG_PL5_SDIV_DIV_DSI_A_WEN BIT(16)
+#define CPG_PL5_SDIV_DIV_DSI_B_WEN BIT(24)
+
+#define CPG_CLKSTATUS_SELSDHI0_STS BIT(28)
+#define CPG_CLKSTATUS_SELSDHI1_STS BIT(29)
+
+#define CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US 20000
+
+/* n = 0/1/2 for PLL1/4/6 */
+#define CPG_SAMPLL_CLK1(n) (0x04 + (16 * (n)))
+#define CPG_SAMPLL_CLK2(n) (0x08 + (16 * (n)))
+
+#define PLL146_CONF(n) (CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12)
+
+#define DDIV_PACK(offset, bitpos, size) \
+ (((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
+#define DIVPL1A DDIV_PACK(CPG_PL1_DDIV, 0, 2)
+#define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3)
+#define DIVDSILPCLK DDIV_PACK(CPG_PL2_DDIV, 12, 2)
+#define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3)
+#define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3)
+#define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3)
+#define DIVGPU DDIV_PACK(CPG_PL6_DDIV, 0, 2)
+
+#define SEL_PLL_PACK(offset, bitpos, size) \
+ (((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
+
+#define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1)
+#define SEL_PLL5_4 SEL_PLL_PACK(CPG_OTHERFUNC1_REG, 0, 1)
+#define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1)
+#define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1)
+
+#define SEL_SDHI0 DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2)
+#define SEL_SDHI1 DDIV_PACK(CPG_PL2SDHI_DSEL, 4, 2)
+
+#define SEL_SDHI_533MHz 1
+#define SEL_SDHI_400MHz 2
+#define SEL_SDHI_266MHz 3
+#define SEL_SDHI_WRITE_ENABLE 0x10000
+
+/* Unpack CPG conf value create by DDIV_PACK() or SEL_PLL_PACK(). */
+#define CPG_CONF_OFFSET(x) ((x) >> 20)
+#define CPG_CONF_BITPOS(x) (((x) >> 12) & 0xff)
+#define CPG_CONF_SIZE(x) (((x) >> 8) & 0xf)
+#define CPG_CONF_BITMASK(x) GENMASK(CPG_CONF_SIZE(x) - 1, 0)
+
+#define EXTAL_FREQ_IN_MEGA_HZ 24
+
+/**
+ * Definitions of CPG Core Clocks
+ *
+ * These include:
+ * - Clock outputs exported to DT
+ * - External input clocks
+ * - Internal CPG clocks
+ */
+struct cpg_core_clk {
+ const char *name;
+ unsigned int id;
+ unsigned int parent;
+ unsigned int div;
+ unsigned int mult;
+ unsigned int type;
+ unsigned int conf;
+ const struct clk_div_table *dtable;
+ const char * const *parent_names;
+ int flag;
+ int mux_flags;
+ int num_parents;
+};
+
+enum clk_types {
+ /* Generic */
+ CLK_TYPE_IN, /* External Clock Input */
+ CLK_TYPE_FF, /* Fixed Factor Clock */
+ CLK_TYPE_SAM_PLL,
+
+ /* Clock with divider */
+ CLK_TYPE_DIV,
+
+ /* Clock with clock source selector */
+ CLK_TYPE_MUX,
+
+ /* Clock with SD clock source selector */
+ CLK_TYPE_SD_MUX,
+
+ /* Clock for SIPLL5 */
+ CLK_TYPE_SIPLL5,
+
+ /* Clock for PLL5_4 clock source selector */
+ CLK_TYPE_PLL5_4_MUX,
+
+ /* Clock for DSI divider */
+ CLK_TYPE_DSI_DIV,
+
+};
+
+#define DEF_TYPE(_name, _id, _type...) \
+ { .name = _name, .id = _id, .type = _type }
+#define DEF_BASE(_name, _id, _type, _parent...) \
+ DEF_TYPE(_name, _id, _type, .parent = _parent)
+#define DEF_SAMPLL(_name, _id, _parent, _conf) \
+ DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf)
+#define DEF_INPUT(_name, _id) \
+ DEF_TYPE(_name, _id, CLK_TYPE_IN)
+#define DEF_FIXED(_name, _id, _parent, _mult, _div) \
+ DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
+#define DEF_DIV(_name, _id, _parent, _conf, _dtable) \
+ DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
+ .parent = _parent, .dtable = _dtable, \
+ .flag = CLK_DIVIDER_HIWORD_MASK)
+#define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \
+ DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
+ .parent = _parent, .dtable = _dtable, \
+ .flag = CLK_DIVIDER_READ_ONLY)
+#define DEF_MUX(_name, _id, _conf, _parent_names) \
+ DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
+ .parent_names = _parent_names, \
+ .num_parents = ARRAY_SIZE(_parent_names), \
+ .mux_flags = CLK_MUX_HIWORD_MASK)
+#define DEF_MUX_RO(_name, _id, _conf, _parent_names) \
+ DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
+ .parent_names = _parent_names, \
+ .num_parents = ARRAY_SIZE(_parent_names), \
+ .mux_flags = CLK_MUX_READ_ONLY)
+#define DEF_SD_MUX(_name, _id, _conf, _parent_names) \
+ DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \
+ .parent_names = _parent_names, \
+ .num_parents = ARRAY_SIZE(_parent_names))
+#define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \
+ DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent)
+#define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names) \
+ DEF_TYPE(_name, _id, CLK_TYPE_PLL5_4_MUX, .conf = _conf, \
+ .parent_names = _parent_names, \
+ .num_parents = ARRAY_SIZE(_parent_names))
+#define DEF_DSI_DIV(_name, _id, _parent, _flag) \
+ DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent = _parent, .flag = _flag)
+
+/**
+ * struct rzg2l_mod_clk - Module Clocks definitions
+ *
+ * @name: handle between common and hardware-specific interfaces
+ * @id: clock index in array containing all Core and Module Clocks
+ * @parent: id of parent clock
+ * @off: register offset
+ * @bit: ON/MON bit
+ * @is_coupled: flag to indicate coupled clock
+ */
+struct rzg2l_mod_clk {
+ const char *name;
+ unsigned int id;
+ unsigned int parent;
+ u16 off;
+ u8 bit;
+ bool is_coupled;
+};
+
+#define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled) \
+ { \
+ .name = (_name), \
+ .id = (_id), \
+ .parent = (_parent), \
+ .off = (_off), \
+ .bit = (_bit), \
+ .is_coupled = (_is_coupled), \
+ }
+
+#define DEF_MOD(_name, _id, _parent, _off, _bit) \
+ DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false)
+
+#define DEF_COUPLED(_name, _id, _parent, _off, _bit) \
+ DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true)
+
+/**
+ * struct rzg2l_reset - Reset definitions
+ *
+ * @off: register offset
+ * @bit: reset bit
+ * @monbit: monitor bit in CPG_RST_MON register, -1 if none
+ */
+struct rzg2l_reset {
+ u16 off;
+ u8 bit;
+ s8 monbit;
+};
+
+#define DEF_RST_MON(_id, _off, _bit, _monbit) \
+ [_id] = { \
+ .off = (_off), \
+ .bit = (_bit), \
+ .monbit = (_monbit) \
+ }
+#define DEF_RST(_id, _off, _bit) \
+ DEF_RST_MON(_id, _off, _bit, -1)
+
+/**
+ * struct rzg2l_cpg_info - SoC-specific CPG Description
+ *
+ * @core_clks: Array of Core Clock definitions
+ * @num_core_clks: Number of entries in core_clks[]
+ *
+ * @mod_clks: Array of Module Clock definitions
+ * @num_mod_clks: Number of entries in mod_clks[]
+ * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
+ *
+ * @resets: Array of Module Reset definitions
+ * @num_resets: Number of entries in resets[]
+ *
+ * @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers
+ */
+struct rzg2l_cpg_info {
+ /* Core Clocks */
+ const struct cpg_core_clk *core_clks;
+ unsigned int num_core_clks;
+
+ /* Module Clocks */
+ const struct rzg2l_mod_clk *mod_clks;
+ unsigned int num_mod_clks;
+ unsigned int num_hw_mod_clks;
+
+ /* Resets */
+ const struct rzg2l_reset *resets;
+ unsigned int num_resets;
+
+ bool has_clk_mon_regs;
+};
+
+extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
+
+int rzg2l_cpg_bind(struct udevice *parent);
+
+/*
+ * Clock IDs start at an offset to avoid overlapping with core & module clock
+ * IDs defined in the dt-bindings headers.
+ */
+enum clk_ids {
+ /* External Input Clocks */
+ CLK_EXTAL = 0x100,
+
+ /* Internal Core Clocks */
+ CLK_OSC_DIV1000 = 0x200,
+ CLK_PLL1,
+ CLK_PLL2,
+ CLK_PLL2_DIV2,
+ CLK_PLL2_DIV2_8,
+ CLK_PLL2_DIV2_10,
+ CLK_PLL3,
+ CLK_PLL3_400,
+ CLK_PLL3_533,
+ CLK_M2_DIV2,
+ CLK_PLL3_DIV2,
+ CLK_PLL3_DIV2_2,
+ CLK_PLL3_DIV2_4,
+ CLK_PLL3_DIV2_4_2,
+ CLK_SEL_PLL3_3,
+ CLK_DIV_PLL3_C,
+ CLK_PLL4,
+ CLK_PLL5,
+ CLK_PLL5_FOUTPOSTDIV,
+ CLK_PLL5_FOUT1PH0,
+ CLK_PLL5_FOUT3,
+ CLK_PLL5_250,
+ CLK_PLL6,
+ CLK_PLL6_250,
+ CLK_P1_DIV2,
+ CLK_PLL2_800,
+ CLK_PLL2_SDHI_533,
+ CLK_PLL2_SDHI_400,
+ CLK_PLL2_SDHI_266,
+ CLK_SD0_DIV4,
+ CLK_SD1_DIV4,
+ CLK_SEL_GPU2,
+ CLK_SEL_PLL5_4,
+ CLK_DSI_DIV,
+ CLK_PLL2_533,
+ CLK_PLL2_533_DIV2,
+ CLK_DIV_DSI_LPCLK,
+};
+
+#endif
diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c
index d657ef3..1bb31b3 100644
--- a/drivers/clk/rockchip/clk_pll.c
+++ b/drivers/clk/rockchip/clk_pll.c
@@ -168,13 +168,71 @@
return rate_table;
}
+static u32
+rockchip_rk3588_pll_k_get(u32 m, u32 p, u32 s, u64 fin_hz, u64 fvco)
+{
+ u64 fref, fout, ffrac;
+ u32 k = 0;
+
+ fref = fin_hz / p;
+ ffrac = fvco - (m * fref);
+ fout = ffrac * 65536;
+ k = fout / fref;
+ if (k > 32767) {
+ fref = fin_hz / p;
+ ffrac = ((m + 1) * fref) - fvco;
+ fout = ffrac * 65536;
+ k = ((fout * 10 / fref) + 7) / 10;
+ if (k > 32767)
+ k = 0;
+ else
+ k = ~k + 1;
+ }
+ return k;
+}
+
+static struct rockchip_pll_rate_table *
+rockchip_rk3588_pll_frac_by_auto(unsigned long fin_hz, unsigned long fout_hz)
+{
+ struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table;
+ u32 p, m, s, k;
+ u64 fvco;
+
+ for (s = 0; s <= 6; s++) {
+ fvco = (u64)fout_hz << s;
+ if (fvco < RK3588_VCO_MIN_HZ || fvco > RK3588_VCO_MAX_HZ)
+ continue;
+ for (p = 1; p <= 4; p++) {
+ for (m = 64; m <= 1023; m++) {
+ if ((fvco >= m * fin_hz / p) &&
+ (fvco < (m + 1) * fin_hz / p)) {
+ k = rockchip_rk3588_pll_k_get(m, p, s,
+ fin_hz,
+ fvco);
+ if (!k)
+ continue;
+ rate_table->p = p;
+ rate_table->s = s;
+ rate_table->k = k;
+ if (k > 32767)
+ rate_table->m = m + 1;
+ else
+ rate_table->m = m;
+ return rate_table;
+ }
+ }
+ }
+ }
+ return NULL;
+}
+
static struct rockchip_pll_rate_table *
rk3588_pll_clk_set_by_auto(unsigned long fin_hz,
unsigned long fout_hz)
{
struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table;
u32 p, m, s;
- ulong fvco, fref, fout, ffrac;
+ ulong fvco;
if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
return NULL;
@@ -202,27 +260,12 @@
}
pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz);
} else {
- for (s = 0; s <= 6; s++) {
- fvco = fout_hz << s;
- if (fvco < RK3588_VCO_MIN_HZ ||
- fvco > RK3588_VCO_MAX_HZ)
- continue;
- for (p = 1; p <= 4; p++) {
- for (m = 64; m <= 1023; m++) {
- if ((fvco >= m * fin_hz / p) && (fvco < (m + 1) * fin_hz / p)) {
- rate_table->p = p;
- rate_table->m = m;
- rate_table->s = s;
- fref = fin_hz / p;
- ffrac = fvco - (m * fref);
- fout = ffrac * 65536;
- rate_table->k = fout / fref;
- return rate_table;
- }
- }
- }
- }
- pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz);
+ rate_table = rockchip_rk3588_pll_frac_by_auto(fin_hz, fout_hz);
+ if (!rate_table)
+ pr_err("CANNOT FIND Fout by auto,fout = %lu\n",
+ fout_hz);
+ else
+ return rate_table;
}
return NULL;
}
@@ -533,11 +576,22 @@
rate = OSC_HZ / p;
rate *= m;
- if (k) {
+ if (k & BIT(15)) {
+ /* fractional mode */
+ u64 frac_rate64;
+
+ k = (~(k - 1)) & RK3588_PLLCON2_K_MASK;
+ frac_rate64 = OSC_HZ * k;
+ postdiv = p;
+ postdiv *= 65536;
+ do_div(frac_rate64, postdiv);
+ rate -= frac_rate64;
+ } else {
/* fractional mode */
u64 frac_rate64 = OSC_HZ * k;
- postdiv = p * 65536;
+ postdiv = p;
+ postdiv *= 65536;
do_div(frac_rate64, postdiv);
rate += frac_rate64;
}
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index a47c431..3406ff5 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -23,6 +23,7 @@
#include <dm/lists.h>
#include <dt-bindings/clock/rk3368-cru.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <linux/stringify.h>
#if CONFIG_IS_ENABLED(OF_PLATDATA)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index f748fb5..c37e8a5 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -24,6 +24,7 @@
#include <dt-bindings/clock/rk3399-cru.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <linux/printk.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
index 599b7b1..68f5bbb 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -1838,7 +1838,7 @@
rockchip_pll_set_rate(&rk3568_pll_clks[VPLL],
priv->cru, VPLL, div * rate);
} else {
- for (i = 0; i <= DCLK_VOP_SEL_CPLL; i++) {
+ for (i = sel; i <= DCLK_VOP_SEL_CPLL; i++) {
switch (i) {
case DCLK_VOP_SEL_GPLL:
pll_rate = priv->gpll_hz;
@@ -2785,9 +2785,15 @@
if (parent->id == PLL_VPLL) {
rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK,
DCLK_VOP_SEL_VPLL << DCLK0_VOP_SEL_SHIFT);
- } else {
+ } else if (parent->id == PLL_HPLL) {
rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK,
DCLK_VOP_SEL_HPLL << DCLK0_VOP_SEL_SHIFT);
+ } else if (parent->id == PLL_CPLL) {
+ rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK,
+ DCLK_VOP_SEL_CPLL << DCLK0_VOP_SEL_SHIFT);
+ } else {
+ rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK,
+ DCLK_VOP_SEL_GPLL << DCLK0_VOP_SEL_SHIFT);
}
return 0;
diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c
index 119b133..a995dd5 100644
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -36,6 +36,7 @@
RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
RK3588_PLL_RATE(786432000, 2, 262, 2, 9437),
RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
+ RK3588_PLL_RATE(742500000, 4, 495, 2, 0),
RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
@@ -305,12 +306,18 @@
switch (clk_id) {
case ACLK_TOP_ROOT:
- src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ if (!(priv->cpll_hz % rate)) {
+ src_clk = ACLK_TOP_ROOT_SRC_SEL_CPLL;
+ src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else {
+ src_clk = ACLK_TOP_ROOT_SRC_SEL_GPLL;
+ src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
assert(src_clk_div - 1 <= 31);
rk_clrsetreg(&cru->clksel_con[8],
ACLK_TOP_ROOT_DIV_MASK |
ACLK_TOP_ROOT_SRC_SEL_MASK,
- (ACLK_TOP_ROOT_SRC_SEL_GPLL <<
+ (src_clk <<
ACLK_TOP_ROOT_SRC_SEL_SHIFT) |
(src_clk_div - 1) << ACLK_TOP_ROOT_DIV_SHIFT);
break;
@@ -1123,13 +1130,23 @@
}
if (sel == DCLK_VOP_SRC_SEL_V0PLL) {
- div = DIV_ROUND_UP(RK3588_VOP_PLL_LIMIT_FREQ, rate);
- rk_clrsetreg(&cru->clksel_con[conid],
- mask,
- DCLK_VOP_SRC_SEL_V0PLL << sel_shift |
- ((div - 1) << div_shift));
- rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL],
- priv->cru, V0PLL, div * rate);
+ pll_rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL],
+ priv->cru, V0PLL);
+ if (pll_rate >= RK3588_VOP_PLL_LIMIT_FREQ && pll_rate % rate == 0) {
+ div = DIV_ROUND_UP(pll_rate, rate);
+ rk_clrsetreg(&cru->clksel_con[conid],
+ mask,
+ DCLK_VOP_SRC_SEL_V0PLL << sel_shift |
+ ((div - 1) << div_shift));
+ } else {
+ div = DIV_ROUND_UP(RK3588_VOP_PLL_LIMIT_FREQ, rate);
+ rk_clrsetreg(&cru->clksel_con[conid],
+ mask,
+ DCLK_VOP_SRC_SEL_V0PLL << sel_shift |
+ ((div - 1) << div_shift));
+ rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL],
+ priv->cru, V0PLL, div * rate);
+ }
} else {
for (i = 0; i <= DCLK_VOP_SRC_SEL_AUPLL; i++) {
switch (i) {
diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c
index 31aaf33..a386948 100644
--- a/drivers/clk/starfive/clk-jh7110.c
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -434,6 +434,15 @@
starfive_clk_gate(priv->reg,
"i2c5_apb", "apb0",
OFFSET(JH7110_SYSCLK_I2C5_APB)));
+ /* Watchdog clocks */
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_APB),
+ starfive_clk_gate(priv->reg,
+ "wdt_apb", "apb0",
+ OFFSET(JH7110_SYSCLK_WDT_APB)));
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_CORE),
+ starfive_clk_gate(priv->reg,
+ "wdt_core", "oscillator",
+ OFFSET(JH7110_SYSCLK_WDT_CORE)));
/* enable noc_bus_stg_axi clock */
if (!clk_get_by_id(JH7110_SYSCLK_NOC_BUS_STG_AXI, &pclk))
@@ -539,6 +548,16 @@
"pcie1_tl", "stg_axiahb",
OFFSET(JH7110_STGCLK_PCIE1_TL)));
+ /* Security clocks */
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_HCLK),
+ starfive_clk_gate(priv->reg,
+ "sec_ahb", "stg_axiahb",
+ OFFSET(JH7110_STGCLK_SEC_HCLK)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISCAHB),
+ starfive_clk_gate(priv->reg,
+ "sec_misc_ahb", "stg_axiahb",
+ OFFSET(JH7110_STGCLK_SEC_MISCAHB)));
+
return 0;
}
diff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c
index 6150287..f3ac8c7 100644
--- a/drivers/clk/stm32/clk-stm32mp1.c
+++ b/drivers/clk/stm32/clk-stm32mp1.c
@@ -72,6 +72,7 @@
#define RCC_PLL2CSGR 0xA4
#define RCC_I2C46CKSELR 0xC0
#define RCC_SPI6CKSELR 0xC4
+#define RCC_UART1CKSELR 0xC8
#define RCC_CPERCKSELR 0xD0
#define RCC_STGENCKSELR 0xD4
#define RCC_DDRITFCR 0xD8
@@ -317,6 +318,7 @@
_SPI45_SEL,
_SPI6_SEL,
_RTC_SEL,
+ _UART1_SEL,
_PARENT_SEL_NB,
_UNKNOWN_SEL = 0xff,
};
@@ -557,6 +559,7 @@
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 16, BSEC, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
@@ -602,6 +605,8 @@
static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
+static const u8 uart1_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER,
+ _PLL4_Q, _HSE_KER};
static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
_HSE_KER};
static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
@@ -659,6 +664,7 @@
STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
(RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
rtc_parents),
+ STM32MP1_CLK_PARENT(_UART1_SEL, RCC_UART1CKSELR, 0, 0x7, uart1_parents),
};
#ifdef STM32MP1_CLOCK_TREE_INIT
@@ -786,6 +792,7 @@
[_SPI1_SEL] = "SPI1",
[_SPI45_SEL] = "SPI45",
[_RTC_SEL] = "RTC",
+ [_UART1_SEL] = "UART1",
};
static const struct stm32mp1_clk_data stm32mp1_data = {
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index bf11fad..8bdc094 100644
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -87,6 +87,13 @@
This enables common clock driver support for platforms based
on Allwinner H3/H5 SoC.
+config CLK_SUN20I_D1
+ bool "Clock driver for Allwinner D1"
+ default MACH_SUN8I_R528
+ help
+ This enables common clock driver support for platforms based
+ on Allwinner D1 SoC.
+
config CLK_SUN50I_H6
bool "Clock driver for Allwinner H6"
default MACH_SUN50I_H6
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 895da02..90a2774 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -19,6 +19,7 @@
obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
+obj-$(CONFIG_CLK_SUN20I_D1) += clk_d1.o
obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
diff --git a/drivers/clk/sunxi/clk_d1.c b/drivers/clk/sunxi/clk_d1.c
new file mode 100644
index 0000000..9dae761
--- /dev/null
+++ b/drivers/clk/sunxi/clk_d1.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <clk/sunxi.h>
+#include <dt-bindings/clock/sun20i-d1-ccu.h>
+#include <dt-bindings/reset/sun20i-d1-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate d1_gates[] = {
+ [CLK_APB0] = GATE_DUMMY,
+
+ [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
+ [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
+ [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
+ [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
+ [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
+ [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
+ [CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
+ [CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
+ [CLK_BUS_UART5] = GATE(0x90c, BIT(5)),
+ [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
+ [CLK_SPI0] = GATE(0x940, BIT(31)),
+ [CLK_SPI1] = GATE(0x944, BIT(31)),
+ [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
+ [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
+
+ [CLK_BUS_EMAC] = GATE(0x97c, BIT(0)),
+
+ [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
+ [CLK_USB_OHCI1] = GATE(0xa74, BIT(31)),
+ [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
+ [CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)),
+ [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
+ [CLK_BUS_EHCI1] = GATE(0xa8c, BIT(5)),
+ [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
+ [CLK_BUS_LRADC] = GATE(0xa9c, BIT(0)),
+
+ [CLK_RISCV] = GATE(0xd04, BIT(31)),
+};
+
+static struct ccu_reset d1_resets[] = {
+ [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
+ [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
+ [RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
+ [RST_BUS_UART0] = RESET(0x90c, BIT(16)),
+ [RST_BUS_UART1] = RESET(0x90c, BIT(17)),
+ [RST_BUS_UART2] = RESET(0x90c, BIT(18)),
+ [RST_BUS_UART3] = RESET(0x90c, BIT(19)),
+ [RST_BUS_UART4] = RESET(0x90c, BIT(20)),
+ [RST_BUS_UART5] = RESET(0x90c, BIT(21)),
+ [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
+ [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
+ [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
+ [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
+ [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
+ [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
+
+ [RST_BUS_EMAC] = RESET(0x97c, BIT(16)),
+
+ [RST_USB_PHY0] = RESET(0xa70, BIT(30)),
+ [RST_USB_PHY1] = RESET(0xa74, BIT(30)),
+ [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
+ [RST_BUS_OHCI1] = RESET(0xa8c, BIT(17)),
+ [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
+ [RST_BUS_EHCI1] = RESET(0xa8c, BIT(21)),
+ [RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
+ [RST_BUS_LRADC] = RESET(0xa9c, BIT(16)),
+};
+
+const struct ccu_desc d1_ccu_desc = {
+ .gates = d1_gates,
+ .resets = d1_resets,
+ .num_gates = ARRAY_SIZE(d1_gates),
+ .num_resets = ARRAY_SIZE(d1_resets),
+};
diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c
index ec02a2d..1782cff 100644
--- a/drivers/clk/sunxi/clk_sunxi.c
+++ b/drivers/clk/sunxi/clk_sunxi.c
@@ -118,6 +118,7 @@
extern const struct ccu_desc a80_ccu_desc;
extern const struct ccu_desc a80_mmc_clk_desc;
extern const struct ccu_desc a83t_ccu_desc;
+extern const struct ccu_desc d1_ccu_desc;
extern const struct ccu_desc f1c100s_ccu_desc;
extern const struct ccu_desc h3_ccu_desc;
extern const struct ccu_desc h6_ccu_desc;
@@ -195,6 +196,10 @@
{ .compatible = "allwinner,sun50i-h5-ccu",
.data = (ulong)&h3_ccu_desc },
#endif
+#ifdef CONFIG_CLK_SUN20I_D1
+ { .compatible = "allwinner,sun20i-d1-ccu",
+ .data = (ulong)&d1_ccu_desc },
+#endif
#ifdef CONFIG_CLK_SUN50I_H6
{ .compatible = "allwinner,sun50i-h6-ccu",
.data = (ulong)&h6_ccu_desc },
diff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c
index bf762c5..8323e6e 100644
--- a/drivers/clk/ti/clk-k3-pll.c
+++ b/drivers/clk/ti/clk-k3-pll.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments K3 SoC PLL clock driver
*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
* Tero Kristo <t-kristo@ti.com>
*/
@@ -25,6 +25,23 @@
#define PLL_16FFT_FREQ_CTRL0 0x30
#define PLL_16FFT_FREQ_CTRL1 0x34
#define PLL_16FFT_DIV_CTRL 0x38
+#define PLL_16FFT_CAL_CTRL 0x60
+#define PLL_16FFT_CAL_STAT 0x64
+
+/* CAL STAT register bits */
+#define PLL_16FFT_CAL_STAT_CAL_LOCK BIT(31)
+
+/* CFG register bits */
+#define PLL_16FFT_CFG_PLL_TYPE_SHIFT (0)
+#define PLL_16FFT_CFG_PLL_TYPE_MASK (0x3 << 0)
+#define PLL_16FFT_CFG_PLL_TYPE_FRACF 1
+
+/* CAL CTRL register bits */
+#define PLL_16FFT_CAL_CTRL_CAL_EN BIT(31)
+#define PLL_16FFT_CAL_CTRL_FAST_CAL BIT(20)
+#define PLL_16FFT_CAL_CTRL_CAL_BYP BIT(15)
+#define PLL_16FFT_CAL_CTRL_CAL_CNT_SHIFT 16
+#define PLL_16FFT_CAL_CTRL_CAL_CNT_MASK (0x7 << 16)
/* CTRL register bits */
#define PLL_16FFT_CTRL_BYPASS_EN BIT(31)
@@ -40,9 +57,14 @@
/* DIV CTRL register bits */
#define PLL_16FFT_DIV_CTRL_REF_DIV_MASK 0x3f
-#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS 24
+/* HSDIV register bits*/
#define PLL_16FFT_HSDIV_CTRL_CLKOUT_EN BIT(15)
+/* FREQ_CTRL1 bits */
+#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS 24
+#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_MASK 0xffffff
+#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_SHIFT 0
+
/* KICK register magic values */
#define PLL_KICK0_VALUE 0x68ef3490
#define PLL_KICK1_VALUE 0xd172bc5a
@@ -63,18 +85,65 @@
{
struct ti_pll_clk *pll = to_clk_pll(clk);
u32 stat;
+ u32 cfg;
+ u32 cal;
+ u32 freq_ctrl1;
int i;
+ u32 pllfm;
+ u32 pll_type;
+ int success;
for (i = 0; i < 100000; i++) {
stat = readl(pll->reg + PLL_16FFT_STAT);
- if (stat & PLL_16FFT_STAT_LOCK)
- return 0;
+ if (stat & PLL_16FFT_STAT_LOCK) {
+ success = 1;
+ break;
+ }
}
- printf("%s: pll (%s) failed to lock\n", __func__,
- clk->dev->name);
+ /* Enable calibration if not in fractional mode of the FRACF PLL */
+ freq_ctrl1 = readl(pll->reg + PLL_16FFT_FREQ_CTRL1);
+ pllfm = freq_ctrl1 & PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_MASK;
+ pllfm >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_SHIFT;
+ cfg = readl(pll->reg + PLL_16FFT_CFG);
+ pll_type = (cfg & PLL_16FFT_CFG_PLL_TYPE_MASK) >> PLL_16FFT_CFG_PLL_TYPE_SHIFT;
- return -EBUSY;
+ if (success && pll_type == PLL_16FFT_CFG_PLL_TYPE_FRACF && pllfm == 0) {
+ cal = readl(pll->reg + PLL_16FFT_CAL_CTRL);
+
+ /* Enable calibration for FRACF */
+ cal |= PLL_16FFT_CAL_CTRL_CAL_EN;
+
+ /* Enable fast cal mode */
+ cal |= PLL_16FFT_CAL_CTRL_FAST_CAL;
+
+ /* Disable calibration bypass */
+ cal &= ~PLL_16FFT_CAL_CTRL_CAL_BYP;
+
+ /* Set CALCNT to 2 */
+ cal &= ~PLL_16FFT_CAL_CTRL_CAL_CNT_MASK;
+ cal |= 2 << PLL_16FFT_CAL_CTRL_CAL_CNT_SHIFT;
+
+ /* Note this register does not readback the written value. */
+ writel(cal, pll->reg + PLL_16FFT_CAL_CTRL);
+
+ success = 0;
+ for (i = 0; i < 100000; i++) {
+ stat = readl(pll->reg + PLL_16FFT_CAL_STAT);
+ if (stat & PLL_16FFT_CAL_STAT_CAL_LOCK) {
+ success = 1;
+ break;
+ }
+ }
+ }
+
+ if (success == 0) {
+ printf("%s: pll (%s) failed to lock\n", __func__,
+ clk->dev->name);
+ return -EBUSY;
+ } else {
+ return 0;
+ }
}
static ulong ti_pll_clk_get_rate(struct clk *clk)
diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c
index ba925fa..eb76195 100644
--- a/drivers/clk/ti/clk-k3.c
+++ b/drivers/clk/ti/clk-k3.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments K3 clock driver
*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
* Tero Kristo <t-kristo@ti.com>
*/
@@ -11,6 +11,7 @@
#include <errno.h>
#include <soc.h>
#include <clk-uclass.h>
+#include <k3-avs.h>
#include "k3-clk.h"
#define PLL_MIN_FREQ 800000000
@@ -242,7 +243,11 @@
const struct clk_ops *ops;
ulong new_rate, rem;
ulong diff, new_diff;
+ int freq_scale_up = rate >= ti_clk_get_rate(clk) ? 1 : 0;
+ if (IS_ENABLED(CONFIG_K3_AVS0) && freq_scale_up)
+ k3_avs_notify_freq(data->map[clk->id].dev_id,
+ data->map[clk->id].clk_id, rate);
/*
* We must propagate rate change to parent if current clock type
* does not allow setting it.
@@ -339,6 +344,10 @@
}
}
+ if (IS_ENABLED(CONFIG_K3_AVS0) && !freq_scale_up)
+ k3_avs_notify_freq(data->map[clk->id].dev_id,
+ data->map[clk->id].clk_id, rate);
+
return new_rate;
}
diff --git a/drivers/clk/ti/clk-sci.c b/drivers/clk/ti/clk-sci.c
index 74df5a3..9e5760d 100644
--- a/drivers/clk/ti/clk-sci.c
+++ b/drivers/clk/ti/clk-sci.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments System Control Interface (TI SCI) clock driver
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Andreas Dannenberg <dannenberg@ti.com>
*
* Loosely based on Linux kernel sci-clk.c...
@@ -91,12 +91,12 @@
const struct ti_sci_handle *sci = data->sci;
const struct ti_sci_clk_ops *cops = &sci->ops.clk_ops;
int ret;
+ int freq_scale_up = rate >= ti_sci_clk_get_rate(clk) ? 1 : 0;
debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
-#ifdef CONFIG_K3_AVS0
- k3_avs_notify_freq(clk->id, clk->data, rate);
-#endif
+ if (IS_ENABLED(CONFIG_K3_AVS0) && freq_scale_up)
+ k3_avs_notify_freq(clk->id, clk->data, rate);
ret = cops->set_freq(sci, clk->id, clk->data, 0, rate, ULONG_MAX);
if (ret) {
@@ -104,6 +104,9 @@
return ret;
}
+ if (IS_ENABLED(CONFIG_K3_AVS0) && !freq_scale_up)
+ k3_avs_notify_freq(clk->id, clk->data, rate);
+
return rate;
}
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index f0d848f..737d459 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -14,7 +14,7 @@
help
Enable driver model in SPL. You will need to provide a
suitable malloc() implementation. If you are not using the
- full malloc() enabled by CFG_SYS_SPL_MALLOC_START,
+ full malloc() enabled by CFG_SPL_SYS_MALLOC_START,
consider using CONFIG_SPL_SYS_MALLOC_SIMPLE. In that case you
must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size.
In most cases driver model will only allocate a few uclasses
@@ -27,12 +27,12 @@
help
Enable driver model in TPL. You will need to provide a
suitable malloc() implementation. If you are not using the
- full malloc() enabled by CFG_SYS_SPL_MALLOC_START,
+ full malloc() enabled by CFG_TPL_SYS_MALLOC_START,
consider using CONFIG_TPL_SYS_MALLOC_SIMPLE. In that case you
- must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size.
+ must provide CONFIG_TPL_SYS_MALLOC_F_LEN to set the size.
In most cases driver model will only allocate a few uclasses
- and devices in SPL, so 1KB should be enough. See
- CONFIG_SPL_SYS_MALLOC_F_LEN for more details on how to enable it.
+ and devices in TPL, so 1KB should be enough. See
+ CONFIG_TPL_SYS_MALLOC_F_LEN for more details on how to enable it.
Disable this for very small implementations.
config VPL_DM
@@ -42,13 +42,12 @@
help
Enable driver model in VPL. You will need to provide a
suitable malloc() implementation. If you are not using the
- full malloc() enabled by CFG_SYS_SPL_MALLOC_START,
- consider using CONFIG_SPL_SYS_MALLOC_SIMPLE.
+ full malloc() enabled by CFG_TPL_SYS_MALLOC_START,
+ consider using CONFIG_TPL_SYS_MALLOC_SIMPLE.
config DM_WARN
bool "Enable warnings in driver model"
depends on DM
- default y
help
Enable this to see warnings related to driver model.
diff --git a/drivers/core/Makefile b/drivers/core/Makefile
index bce0a3f..acbd2bf 100644
--- a/drivers/core/Makefile
+++ b/drivers/core/Makefile
@@ -15,6 +15,7 @@
ifndef CONFIG_DM_DEV_READ_INLINE
obj-$(CONFIG_OF_CONTROL) += read.o
endif
+obj-$(CONFIG_$(SPL_)OF_PLATDATA) += read.o
obj-$(CONFIG_OF_CONTROL) += of_extra.o ofnode.o read_extra.o
ccflags-$(CONFIG_DM_DEBUG) += -DDEBUG
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 6e26b64..bf7f261 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -33,6 +33,7 @@
#include <linux/err.h>
#include <linux/list.h>
#include <power-domain.h>
+#include <linux/printk.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -598,9 +599,10 @@
ret = device_notify(dev, EVT_DM_POST_PROBE);
if (ret)
- return ret;
+ goto fail_event;
return 0;
+fail_event:
fail_uclass:
if (device_remove(dev, DM_REMOVE_NORMAL)) {
dm_warn("%s: Device '%s' failed to remove on error path\n",
diff --git a/drivers/core/dump.c b/drivers/core/dump.c
index 3e77832..8411248 100644
--- a/drivers/core/dump.c
+++ b/drivers/core/dump.c
@@ -85,29 +85,64 @@
}
}
-void dm_dump_tree(bool sort)
+static void dm_dump_tree_single(struct udevice *dev, bool sort)
+{
+ int dev_count, uclasses;
+ struct udevice **devs = NULL;
+
+ if (sort) {
+ dm_get_stats(&dev_count, &uclasses);
+ devs = calloc(dev_count, sizeof(struct udevice *));
+ if (!devs) {
+ printf("(out of memory)\n");
+ return;
+ }
+ }
+ show_devices(dev, -1, 0, devs);
+ free(devs);
+}
+
+static void dm_dump_tree_recursive(struct udevice *dev, char *dev_name,
+ bool extended, bool sort)
+{
+ struct udevice *child;
+ size_t len;
+
+ len = strlen(dev_name);
+
+ device_foreach_child(child, dev) {
+ if (extended) {
+ if (!strncmp(child->name, dev_name, len)) {
+ dm_dump_tree_single(child, sort);
+ continue;
+ }
+ } else {
+ if (!strcmp(child->name, dev_name)) {
+ dm_dump_tree_single(child, sort);
+ continue;
+ }
+ }
+ dm_dump_tree_recursive(child, dev_name, extended, sort);
+ }
+}
+
+void dm_dump_tree(char *dev_name, bool extended, bool sort)
{
struct udevice *root;
+ printf(" Class Index Probed Driver Name\n");
+ printf("-----------------------------------------------------------\n");
+
root = dm_root();
- if (root) {
- int dev_count, uclasses;
- struct udevice **devs = NULL;
+ if (!root)
+ return;
- dm_get_stats(&dev_count, &uclasses);
-
- printf(" Class Index Probed Driver Name\n");
- printf("-----------------------------------------------------------\n");
- if (sort) {
- devs = calloc(dev_count, sizeof(struct udevice *));
- if (!devs) {
- printf("(out of memory)\n");
- return;
- }
- }
- show_devices(root, -1, 0, devs);
- free(devs);
+ if (!dev_name || !strcmp(dev_name, "root")) {
+ dm_dump_tree_single(root, sort);
+ return;
}
+
+ dm_dump_tree_recursive(root, dev_name, extended, sort);
}
/**
@@ -127,26 +162,50 @@
puts("\n");
}
-void dm_dump_uclass(void)
+static void dm_dump_uclass_single(enum uclass_id id)
{
struct uclass *uc;
+ struct udevice *dev;
+ int i = 0, ret;
+
+ ret = uclass_get(id, &uc);
+ if (ret)
+ return;
+
+ printf("uclass %d: %s\n", id, uc->uc_drv->name);
+ uclass_foreach_dev(dev, uc) {
+ dm_display_line(dev, i);
+ i++;
+ }
+ puts("\n");
+}
+
+void dm_dump_uclass(char *uclass, bool extended)
+{
+ struct uclass *uc;
+ enum uclass_id id;
+ bool matching;
int ret;
- int id;
+
+ matching = !!(uclass && strcmp(uclass, "root"));
for (id = 0; id < UCLASS_COUNT; id++) {
- struct udevice *dev;
- int i = 0;
-
ret = uclass_get(id, &uc);
if (ret)
continue;
- printf("uclass %d: %s\n", id, uc->uc_drv->name);
- uclass_foreach_dev(dev, uc) {
- dm_display_line(dev, i);
- i++;
+ if (matching) {
+ if (extended) {
+ if (!strncmp(uc->uc_drv->name, uclass,
+ strlen(uclass)))
+ dm_dump_uclass_single(id);
+ } else {
+ if (!strcmp(uc->uc_drv->name, uclass))
+ dm_dump_uclass_single(id);
+ }
+ } else {
+ dm_dump_uclass_single(id);
}
- puts("\n");
}
}
diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c
index 546db67..8e774d4 100644
--- a/drivers/core/fdtaddr.c
+++ b/drivers/core/fdtaddr.c
@@ -145,7 +145,7 @@
index = fdt_stringlist_search(gd->fdt_blob, dev_of_offset(dev),
"reg-names", name);
if (index < 0)
- return index;
+ return FDT_ADDR_T_NONE;
return devfdt_get_addr_index(dev, index);
#else
@@ -153,6 +153,16 @@
#endif
}
+void *devfdt_get_addr_name_ptr(const struct udevice *dev, const char *name)
+{
+ fdt_addr_t addr = devfdt_get_addr_name(dev, name);
+
+ if (addr == FDT_ADDR_T_NONE)
+ return NULL;
+
+ return map_sysmem(addr, 0);
+}
+
fdt_addr_t devfdt_get_addr_size_name(const struct udevice *dev,
const char *name, fdt_size_t *size)
{
@@ -162,7 +172,7 @@
index = fdt_stringlist_search(gd->fdt_blob, dev_of_offset(dev),
"reg-names", name);
if (index < 0)
- return index;
+ return FDT_ADDR_T_NONE;
return devfdt_get_addr_size_index(dev, index, size);
#else
@@ -170,6 +180,17 @@
#endif
}
+void *devfdt_get_addr_size_name_ptr(const struct udevice *dev,
+ const char *name, fdt_size_t *size)
+{
+ fdt_addr_t addr = devfdt_get_addr_size_name(dev, name, size);
+
+ if (addr == FDT_ADDR_T_NONE)
+ return NULL;
+
+ return map_sysmem(addr, 0);
+}
+
fdt_addr_t devfdt_get_addr(const struct udevice *dev)
{
return devfdt_get_addr_index(dev, 0);
@@ -215,7 +236,7 @@
return map_physmem(addr, size, MAP_NOCACHE);
}
-fdt_addr_t devfdt_get_addr_pci(const struct udevice *dev)
+fdt_addr_t devfdt_get_addr_pci(const struct udevice *dev, fdt_size_t *sizep)
{
ulong addr;
@@ -226,12 +247,12 @@
int ret;
ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_MEM32,
- "reg", &pci_addr);
+ "reg", &pci_addr, sizep);
if (ret) {
/* try if there is any i/o-mapped register */
ret = ofnode_read_pci_addr(dev_ofnode(dev),
FDT_PCI_SPACE_IO, "reg",
- &pci_addr);
+ &pci_addr, sizep);
if (ret)
return FDT_ADDR_T_NONE;
}
diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c
index 57f1044..c8db743 100644
--- a/drivers/core/of_access.c
+++ b/drivers/core/of_access.c
@@ -570,26 +570,34 @@
return 0;
}
-int of_read_u64(const struct device_node *np, const char *propname, u64 *outp)
+int of_read_u64_index(const struct device_node *np, const char *propname,
+ int index, u64 *outp)
{
const __be64 *val;
debug("%s: %s: ", __func__, propname);
if (!np)
return -EINVAL;
- val = of_find_property_value_of_size(np, propname, sizeof(*outp));
+
+ val = of_find_property_value_of_size(np, propname,
+ sizeof(*outp) * (index + 1));
if (IS_ERR(val)) {
debug("(not found)\n");
return PTR_ERR(val);
}
- *outp = be64_to_cpup(val);
+ *outp = be64_to_cpup(val + index);
debug("%#llx (%lld)\n", (unsigned long long)*outp,
- (unsigned long long)*outp);
+ (unsigned long long)*outp);
return 0;
}
+int of_read_u64(const struct device_node *np, const char *propname, u64 *outp)
+{
+ return of_read_u64_index(np, propname, 0, outp);
+}
+
int of_property_match_string(const struct device_node *np, const char *propname,
const char *string)
{
@@ -1032,3 +1040,68 @@
return 0;
}
+
+int __of_remove_property(struct device_node *np, struct property *prop)
+{
+ struct property **next;
+
+ for (next = &np->properties; *next; next = &(*next)->next) {
+ if (*next == prop)
+ break;
+ }
+ if (!*next)
+ return -ENODEV;
+
+ /* found the node */
+ *next = prop->next;
+
+ return 0;
+}
+
+int of_remove_property(struct device_node *np, struct property *prop)
+{
+ int rc;
+
+ mutex_lock(&of_mutex);
+
+ rc = __of_remove_property(np, prop);
+
+ mutex_unlock(&of_mutex);
+
+ return rc;
+}
+
+int of_remove_node(struct device_node *to_remove)
+{
+ struct device_node *parent = to_remove->parent;
+ struct device_node *np, *prev;
+
+ if (!parent)
+ return -EPERM;
+ prev = NULL;
+ __for_each_child_of_node(parent, np) {
+ if (np == to_remove)
+ break;
+ prev = np;
+ }
+ if (!np)
+ return -EFAULT;
+
+ /* if there is a previous node, link it to this one's sibling */
+ if (prev)
+ prev->sibling = np->sibling;
+ else
+ parent->child = np->sibling;
+
+ /*
+ * don't free it, since if this is an unflattened tree, all the memory
+ * was alloced in one block; this pointer will be somewhere in the
+ * middle of that
+ *
+ * TODO(sjg@chromium.org): Consider marking nodes as 'allocated'?
+ *
+ * free(np);
+ */
+
+ return 0;
+}
diff --git a/drivers/core/of_addr.c b/drivers/core/of_addr.c
index 431dd4e..b3b3d7c 100644
--- a/drivers/core/of_addr.c
+++ b/drivers/core/of_addr.c
@@ -14,6 +14,7 @@
#include <dm/of_addr.h>
#include <linux/err.h>
#include <linux/ioport.h>
+#include <linux/printk.h>
/* Max address size we deal with */
#define OF_MAX_ADDR_CELLS 4
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 8df16e5..f72ea41 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -47,6 +47,17 @@
return -1;
}
+static int check_tree_count(void)
+{
+ if (oftree_count == CONFIG_OFNODE_MULTI_TREE_MAX) {
+ log_warning("Too many registered device trees (max %d)\n",
+ CONFIG_OFNODE_MULTI_TREE_MAX);
+ return -E2BIG;
+ }
+
+ return 0;
+}
+
static oftree oftree_ensure(void *fdt)
{
oftree tree;
@@ -69,11 +80,8 @@
if (gd->flags & GD_FLG_RELOC) {
i = oftree_find(fdt);
if (i == -1) {
- if (oftree_count == CONFIG_OFNODE_MULTI_TREE_MAX) {
- log_warning("Too many registered device trees (max %d)\n",
- CONFIG_OFNODE_MULTI_TREE_MAX);
+ if (check_tree_count())
return oftree_null();
- }
/* register the new tree */
i = oftree_count++;
@@ -92,6 +100,41 @@
return tree;
}
+int oftree_new(oftree *treep)
+{
+ oftree tree = oftree_null();
+ int ret;
+
+ if (of_live_active()) {
+ struct device_node *root;
+
+ ret = of_live_create_empty(&root);
+ if (ret)
+ return log_msg_ret("liv", ret);
+ tree = oftree_from_np(root);
+ } else {
+ const int size = 1024;
+ void *fdt;
+
+ ret = check_tree_count();
+ if (ret)
+ return log_msg_ret("fla", ret);
+
+ /* register the new tree with a small size */
+ fdt = malloc(size);
+ if (!fdt)
+ return log_msg_ret("fla", -ENOMEM);
+ ret = fdt_create_empty_tree(fdt, size);
+ if (ret)
+ return log_msg_ret("fla", -EINVAL);
+ oftree_list[oftree_count++] = fdt;
+ tree.fdt = fdt;
+ }
+ *treep = tree;
+
+ return 0;
+}
+
void oftree_dispose(oftree tree)
{
if (of_live_active())
@@ -103,7 +146,7 @@
if (gd->flags & GD_FLG_RELOC) {
uint i = OFTREE_TREE_ID(node.of_offset);
- if (i > oftree_count) {
+ if (i >= oftree_count) {
log_debug("Invalid tree ID %x\n", i);
return NULL;
}
@@ -193,8 +236,31 @@
return 0;
}
+int oftree_new(oftree *treep)
+{
+ return -ENOSYS;
+}
+
#endif /* OFNODE_MULTI_TREE */
+int oftree_to_fdt(oftree tree, struct abuf *buf)
+{
+ int ret;
+
+ if (of_live_active()) {
+ ret = of_live_flatten(ofnode_to_np(oftree_root(tree)), buf);
+ if (ret)
+ return log_msg_ret("flt", ret);
+ } else {
+ void *fdt = oftree_lookup_fdt(tree);
+
+ abuf_init(buf);
+ abuf_set(buf, fdt, fdt_totalsize(fdt));
+ }
+
+ return 0;
+}
+
/**
* ofnode_from_tree_offset() - get an ofnode from a tree offset (flat tree)
*
@@ -344,6 +410,36 @@
return 0;
}
+int ofnode_read_u64_index(ofnode node, const char *propname, int index,
+ u64 *outp)
+{
+ const fdt64_t *cell;
+ int len;
+
+ assert(ofnode_valid(node));
+
+ if (ofnode_is_np(node))
+ return of_read_u64_index(ofnode_to_np(node), propname, index,
+ outp);
+
+ cell = fdt_getprop(ofnode_to_fdt(node), ofnode_to_offset(node),
+ propname, &len);
+ if (!cell) {
+ debug("(not found)\n");
+ return -EINVAL;
+ }
+
+ if (len < (sizeof(u64) * (index + 1))) {
+ debug("(not large enough)\n");
+ return -EOVERFLOW;
+ }
+
+ *outp = fdt64_to_cpu(cell[index]);
+ debug("%#llx (%lld)\n", *outp, *outp);
+
+ return 0;
+}
+
u32 ofnode_read_u32_index_default(ofnode node, const char *propname, int index,
u32 def)
{
@@ -395,12 +491,12 @@
bool ofnode_read_bool(ofnode node, const char *propname)
{
- const void *prop;
+ bool prop;
assert(ofnode_valid(node));
debug("%s: %s: ", __func__, propname);
- prop = ofnode_get_property(node, propname, NULL);
+ prop = ofnode_has_property(node, propname);
debug("%s\n", prop ? "true" : "false");
@@ -895,6 +991,24 @@
return ofnode_path(prop);
}
+int ofnode_read_baud(void)
+{
+ const char *str, *p;
+ u32 baud;
+
+ str = ofnode_read_chosen_string("stdout-path");
+ if (!str)
+ return -EINVAL;
+
+ /* Parse string serial0:115200n8 */
+ p = strchr(str, ':');
+ if (!p)
+ return -EINVAL;
+
+ baud = dectoul(p + 1, NULL);
+ return baud;
+}
+
const void *ofnode_read_aliases_prop(const char *propname, int *sizep)
{
ofnode node;
@@ -1072,6 +1186,14 @@
propname, lenp);
}
+bool ofnode_has_property(ofnode node, const char *propname)
+{
+ if (ofnode_is_np(node))
+ return of_find_property(ofnode_to_np(node), propname, NULL);
+ else
+ return ofnode_get_property(node, propname, NULL);
+}
+
int ofnode_first_property(ofnode node, struct ofprop *prop)
{
prop->node = node;
@@ -1166,7 +1288,8 @@
}
int ofnode_read_pci_addr(ofnode node, enum fdt_pci_space type,
- const char *propname, struct fdt_pci_addr *addr)
+ const char *propname, struct fdt_pci_addr *addr,
+ fdt_size_t *size)
{
const fdt32_t *cell;
int len;
@@ -1194,14 +1317,18 @@
(ulong)fdt32_to_cpu(cell[1]),
(ulong)fdt32_to_cpu(cell[2]));
if ((fdt32_to_cpu(*cell) & type) == type) {
+ const unaligned_fdt64_t *ptr;
+
addr->phys_hi = fdt32_to_cpu(cell[0]);
addr->phys_mid = fdt32_to_cpu(cell[1]);
addr->phys_lo = fdt32_to_cpu(cell[2]);
+ ptr = (const unaligned_fdt64_t *)(cell + 3);
+ if (size)
+ *size = fdt64_to_cpu(*ptr);
break;
}
- cell += (FDT_PCI_ADDR_CELLS +
- FDT_PCI_SIZE_CELLS);
+ cell += FDT_PCI_ADDR_CELLS + FDT_PCI_SIZE_CELLS;
}
if (i == num) {
@@ -1353,7 +1480,7 @@
*/
if (ofnode_read_bool(node, "bootph-pre-ram") ||
ofnode_read_bool(node, "bootph-pre-sram"))
- return true;
+ return gd->flags & GD_FLG_RELOC;
if (IS_ENABLED(CONFIG_OF_TAG_MIGRATE)) {
/* detect and handle old tags */
@@ -1517,7 +1644,46 @@
return -ENOMEM;
*val = cpu_to_fdt32(value);
- return ofnode_write_prop(node, propname, val, sizeof(value), false);
+ return ofnode_write_prop(node, propname, val, sizeof(value), true);
+}
+
+int ofnode_write_u64(ofnode node, const char *propname, u64 value)
+{
+ fdt64_t *val;
+
+ assert(ofnode_valid(node));
+
+ log_debug("%s = %llx", propname, (unsigned long long)value);
+ val = malloc(sizeof(*val));
+ if (!val)
+ return -ENOMEM;
+ *val = cpu_to_fdt64(value);
+
+ return ofnode_write_prop(node, propname, val, sizeof(value), true);
+}
+
+int ofnode_write_bool(ofnode node, const char *propname, bool value)
+{
+ if (value)
+ return ofnode_write_prop(node, propname, NULL, 0, false);
+ else
+ return ofnode_delete_prop(node, propname);
+}
+
+int ofnode_delete_prop(ofnode node, const char *propname)
+{
+ if (ofnode_is_np(node)) {
+ struct property *prop;
+ int len;
+
+ prop = of_find_property(ofnode_to_np(node), propname, &len);
+ if (prop)
+ return of_remove_property(ofnode_to_np(node), prop);
+ return 0;
+ } else {
+ return fdt_delprop(ofnode_to_fdt(node), ofnode_to_offset(node),
+ propname);
+ }
}
int ofnode_set_enabled(ofnode node, bool value)
@@ -1563,6 +1729,65 @@
return ofnode_read_string(node, prop_name);
}
+int ofnode_read_bootscript_address(u64 *bootscr_address, u64 *bootscr_offset)
+{
+ int ret;
+ ofnode uboot;
+
+ *bootscr_address = 0;
+ *bootscr_offset = 0;
+
+ uboot = ofnode_path("/options/u-boot");
+ if (!ofnode_valid(uboot)) {
+ debug("%s: Missing /u-boot node\n", __func__);
+ return -EINVAL;
+ }
+
+ ret = ofnode_read_u64(uboot, "bootscr-address", bootscr_address);
+ if (ret) {
+ ret = ofnode_read_u64(uboot, "bootscr-ram-offset",
+ bootscr_offset);
+ if (ret)
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int ofnode_read_bootscript_flash(u64 *bootscr_flash_offset,
+ u64 *bootscr_flash_size)
+{
+ int ret;
+ ofnode uboot;
+
+ *bootscr_flash_offset = 0;
+ *bootscr_flash_size = 0;
+
+ uboot = ofnode_path("/options/u-boot");
+ if (!ofnode_valid(uboot)) {
+ debug("%s: Missing /u-boot node\n", __func__);
+ return -EINVAL;
+ }
+
+ ret = ofnode_read_u64(uboot, "bootscr-flash-offset",
+ bootscr_flash_offset);
+ if (ret)
+ return -EINVAL;
+
+ ret = ofnode_read_u64(uboot, "bootscr-flash-size",
+ bootscr_flash_size);
+ if (ret)
+ return -EINVAL;
+
+ if (!bootscr_flash_size) {
+ debug("bootscr-flash-size is zero. Ignoring properties!\n");
+ *bootscr_flash_offset = 0;
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
ofnode ofnode_get_phy_node(ofnode node)
{
/* DT node properties that reference a PHY node */
@@ -1642,7 +1867,30 @@
return ret; /* 0 or -EEXIST */
}
-int ofnode_copy_props(ofnode src, ofnode dst)
+int ofnode_delete(ofnode *nodep)
+{
+ ofnode node = *nodep;
+ int ret;
+
+ assert(ofnode_valid(node));
+ if (ofnode_is_np(node)) {
+ ret = of_remove_node(ofnode_to_np(node));
+ } else {
+ void *fdt = ofnode_to_fdt(node);
+ int offset = ofnode_to_offset(node);
+
+ ret = fdt_del_node(fdt, offset);
+ if (ret)
+ ret = -EFAULT;
+ }
+ if (ret)
+ return ret;
+ *nodep = ofnode_null();
+
+ return 0;
+}
+
+int ofnode_copy_props(ofnode dst, ofnode src)
{
struct ofprop prop;
@@ -1665,3 +1913,23 @@
return 0;
}
+
+int ofnode_copy_node(ofnode dst_parent, const char *name, ofnode src,
+ ofnode *nodep)
+{
+ ofnode node;
+ int ret;
+
+ ret = ofnode_add_subnode(dst_parent, name, &node);
+ if (ret) {
+ if (ret == -EEXIST)
+ *nodep = node;
+ return log_msg_ret("add", ret);
+ }
+ ret = ofnode_copy_props(node, src);
+ if (ret)
+ return log_msg_ret("cpy", ret);
+ *nodep = node;
+
+ return 0;
+}
diff --git a/drivers/core/read.c b/drivers/core/read.c
index 49066b5..1a4a95c 100644
--- a/drivers/core/read.c
+++ b/drivers/core/read.c
@@ -181,6 +181,16 @@
return dev_read_addr_index(dev, index);
}
+void *dev_read_addr_name_ptr(const struct udevice *dev, const char *name)
+{
+ fdt_addr_t addr = dev_read_addr_name(dev, name);
+
+ if (addr == FDT_ADDR_T_NONE)
+ return NULL;
+
+ return map_sysmem(addr, 0);
+}
+
fdt_addr_t dev_read_addr_size_name(const struct udevice *dev, const char *name,
fdt_size_t *size)
{
@@ -192,6 +202,17 @@
return dev_read_addr_size_index(dev, index, size);
}
+void *dev_read_addr_size_name_ptr(const struct udevice *dev, const char *name,
+ fdt_size_t *size)
+{
+ fdt_addr_t addr = dev_read_addr_size_name(dev, name, size);
+
+ if (addr == FDT_ADDR_T_NONE)
+ return NULL;
+
+ return map_sysmem(addr, 0);
+}
+
void *dev_remap_addr_name(const struct udevice *dev, const char *name)
{
fdt_addr_t addr = dev_read_addr_name(dev, name);
@@ -405,13 +426,15 @@
return fdtdec_get_alias_highest_id(gd->fdt_blob, stem);
}
-fdt_addr_t dev_read_addr_pci(const struct udevice *dev)
+fdt_addr_t dev_read_addr_pci(const struct udevice *dev, fdt_size_t *sizep)
{
ulong addr;
addr = dev_read_addr(dev);
+ if (sizep)
+ *sizep = 0;
if (addr == FDT_ADDR_T_NONE && !of_live_active())
- addr = devfdt_get_addr_pci(dev);
+ addr = devfdt_get_addr_pci(dev, sizep);
return addr;
}
diff --git a/drivers/core/root.c b/drivers/core/root.c
index bdb099e..a628dcc 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -29,6 +29,7 @@
#include <dm/uclass-internal.h>
#include <dm/util.h>
#include <linux/list.h>
+#include <linux/printk.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -55,81 +56,6 @@
}
}
-void fix_drivers(void)
-{
- struct driver *drv =
- ll_entry_start(struct driver, driver);
- const int n_ents = ll_entry_count(struct driver, driver);
- struct driver *entry;
-
- for (entry = drv; entry != drv + n_ents; entry++) {
- if (entry->of_match)
- entry->of_match = (const struct udevice_id *)
- ((ulong)entry->of_match + gd->reloc_off);
- if (entry->bind)
- entry->bind += gd->reloc_off;
- if (entry->probe)
- entry->probe += gd->reloc_off;
- if (entry->remove)
- entry->remove += gd->reloc_off;
- if (entry->unbind)
- entry->unbind += gd->reloc_off;
- if (entry->of_to_plat)
- entry->of_to_plat += gd->reloc_off;
- if (entry->child_post_bind)
- entry->child_post_bind += gd->reloc_off;
- if (entry->child_pre_probe)
- entry->child_pre_probe += gd->reloc_off;
- if (entry->child_post_remove)
- entry->child_post_remove += gd->reloc_off;
- /* OPS are fixed in every uclass post_probe function */
- if (entry->ops)
- entry->ops += gd->reloc_off;
- }
-}
-
-void fix_uclass(void)
-{
- struct uclass_driver *uclass =
- ll_entry_start(struct uclass_driver, uclass_driver);
- const int n_ents = ll_entry_count(struct uclass_driver, uclass_driver);
- struct uclass_driver *entry;
-
- for (entry = uclass; entry != uclass + n_ents; entry++) {
- if (entry->post_bind)
- entry->post_bind += gd->reloc_off;
- if (entry->pre_unbind)
- entry->pre_unbind += gd->reloc_off;
- if (entry->pre_probe)
- entry->pre_probe += gd->reloc_off;
- if (entry->post_probe)
- entry->post_probe += gd->reloc_off;
- if (entry->pre_remove)
- entry->pre_remove += gd->reloc_off;
- if (entry->child_post_bind)
- entry->child_post_bind += gd->reloc_off;
- if (entry->child_pre_probe)
- entry->child_pre_probe += gd->reloc_off;
- if (entry->init)
- entry->init += gd->reloc_off;
- if (entry->destroy)
- entry->destroy += gd->reloc_off;
- }
-}
-
-void fix_devices(void)
-{
- struct driver_info *dev =
- ll_entry_start(struct driver_info, driver_info);
- const int n_ents = ll_entry_count(struct driver_info, driver_info);
- struct driver_info *entry;
-
- for (entry = dev; entry != dev + n_ents; entry++) {
- if (entry->plat)
- entry->plat += gd->reloc_off;
- }
-}
-
static int dm_setup_inst(void)
{
DM_ROOT_NON_CONST = DM_DEVICE_GET(root);
@@ -181,12 +107,6 @@
INIT_LIST_HEAD(DM_UCLASS_ROOT_NON_CONST);
}
- if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC)) {
- fix_drivers();
- fix_uclass();
- fix_devices();
- }
-
if (CONFIG_IS_ENABLED(OF_PLATDATA_INST)) {
ret = dm_setup_inst();
if (ret) {
@@ -507,7 +427,7 @@
stats->tag_size;
}
-#ifdef CONFIG_ACPIGEN
+#if CONFIG_IS_ENABLED(ACPIGEN)
static int root_acpi_get_name(const struct udevice *dev, char *out_name)
{
return acpi_copy_name(out_name, "\\_SB");
diff --git a/drivers/core/util.c b/drivers/core/util.c
index aa60fdd..81497df 100644
--- a/drivers/core/util.c
+++ b/drivers/core/util.c
@@ -30,7 +30,7 @@
/* Extract the devfn from fdt_pci_addr */
ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG,
- "reg", &addr);
+ "reg", &addr, NULL);
if (ret) {
if (ret != -ENOENT)
return -EINVAL;
diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c
index a754832..9772578 100644
--- a/drivers/cpu/cpu-uclass.c
+++ b/drivers/cpu/cpu-uclass.c
@@ -127,36 +127,9 @@
return ret;
}
-static int uclass_cpu_post_bind(struct udevice *dev)
-{
- if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC) &&
- (gd->flags & GD_FLG_RELOC)) {
- struct cpu_ops *ops = cpu_get_ops(dev);
- static int reloc_done;
-
- if (!reloc_done) {
- if (ops->get_desc)
- MANUAL_RELOC(ops->get_desc);
- if (ops->get_info)
- MANUAL_RELOC(ops->get_info);
- if (ops->get_count)
- MANUAL_RELOC(ops->get_count);
- if (ops->get_vendor)
- MANUAL_RELOC(ops->get_vendor);
- if (ops->is_current)
- MANUAL_RELOC(ops->is_current);
-
- reloc_done++;
- }
- }
-
- return 0;
-}
-
UCLASS_DRIVER(cpu) = {
.id = UCLASS_CPU,
.name = "cpu",
.flags = DM_UC_FLAG_SEQ_ALIAS,
.init = uclass_cpu_init,
- .post_bind = uclass_cpu_post_bind,
};
diff --git a/drivers/cpu/microblaze_cpu.c b/drivers/cpu/microblaze_cpu.c
index c97a89f..a229f69 100644
--- a/drivers/cpu/microblaze_cpu.c
+++ b/drivers/cpu/microblaze_cpu.c
@@ -19,7 +19,7 @@
ci = tmp; \
}
-static int microblaze_cpu_probe_all(void *ctx, struct event *event)
+static int microblaze_cpu_probe_all(void)
{
int ret;
@@ -29,7 +29,7 @@
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, microblaze_cpu_probe_all);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, microblaze_cpu_probe_all);
static void microblaze_set_cpuinfo_pvr(struct microblaze_cpuinfo *ci)
{
diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
index 91a51cc..eaad196 100644
--- a/drivers/crypto/fsl/Kconfig
+++ b/drivers/crypto/fsl/Kconfig
@@ -77,7 +77,6 @@
config FSL_DCP_RNG
bool "Enable Random Number Generator support"
depends on DM_RNG
- default n
help
Enable support for the hardware based random number generator
module of the DCP. It uses the True Random Number Generator (TRNG)
diff --git a/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c b/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c
index 6a4d235..057cc74 100644
--- a/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c
+++ b/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c
@@ -16,24 +16,11 @@
#include <asm/io.h>
#include <linux/list.h>
-#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC)
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
int rsa_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t sig_len,
struct key_prop *node, uint8_t *out)
{
struct mod_exp_ops *ops = (struct mod_exp_ops *)device_get_ops(dev);
-#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC)
- static bool done;
-
- if (!done) {
- done = true;
- ops->mod_exp += gd->reloc_off;
- }
-#endif
-
if (!ops->mod_exp)
return -ENOSYS;
diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c
index fd8b411..45e1a70 100644
--- a/drivers/ddr/imx/phy/ddrphy_utils.c
+++ b/drivers/ddr/imx/phy/ddrphy_utils.c
@@ -111,11 +111,16 @@
dram_pll_init(MHZ(1000));
dram_disable_bypass();
break;
+ case 3734:
case 3733:
case 3732:
dram_pll_init(MHZ(933));
dram_disable_bypass();
break;
+ case 3600:
+ dram_pll_init(MHZ(900));
+ dram_disable_bypass();
+ break;
case 3200:
dram_pll_init(MHZ(800));
dram_disable_bypass();
diff --git a/drivers/ddr/imx/phy/helper.c b/drivers/ddr/imx/phy/helper.c
index 8cd4387..855a874 100644
--- a/drivers/ddr/imx/phy/helper.c
+++ b/drivers/ddr/imx/phy/helper.c
@@ -46,13 +46,13 @@
u32 error = 0;
unsigned long pr_to32, pr_from32;
uint32_t fw_offset = type ? IMEM_2D_OFFSET : 0;
- unsigned long imem_start = (unsigned long)&_end + fw_offset;
+ unsigned long imem_start = (unsigned long)_end + fw_offset;
unsigned long dmem_start;
unsigned long imem_len = IMEM_LEN, dmem_len = DMEM_LEN;
#ifdef CONFIG_SPL_OF_CONTROL
if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) {
- imem_start = roundup((unsigned long)&_end +
+ imem_start = roundup((unsigned long)_end +
fdt_totalsize(gd->fdt_blob), 4) +
fw_offset;
}
diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c
index b2ee5f1..2adf26e 100644
--- a/drivers/dfu/dfu.c
+++ b/drivers/dfu/dfu.c
@@ -17,6 +17,7 @@
#include <hash.h>
#include <linux/list.h>
#include <linux/compiler.h>
+#include <linux/printk.h>
LIST_HEAD(dfu_list);
static int dfu_alt_num;
diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c
index f583208..12c54e9 100644
--- a/drivers/dfu/dfu_mmc.c
+++ b/drivers/dfu/dfu_mmc.c
@@ -17,6 +17,7 @@
#include <mmc.h>
#include <part.h>
#include <command.h>
+#include <linux/printk.h>
static unsigned char *dfu_file_buf;
static u64 dfu_file_buf_len;
@@ -386,6 +387,16 @@
dfu->data.mmc.lba_blk_size = mmc->read_bl_len;
/*
+ * In case the size is zero (i.e. mmc raw 0x10 0),
+ * assume the user intends to use whole device.
+ */
+ if (third_arg == 0) {
+ struct blk_desc *blk_dev = mmc_get_blk_desc(mmc);
+
+ dfu->data.mmc.lba_size = blk_dev->lba;
+ }
+
+ /*
* Check for an extra entry at dfu_alt_info env variable
* specifying the mmc HW defined partition number
*/
diff --git a/drivers/dfu/dfu_mtd.c b/drivers/dfu/dfu_mtd.c
index 75e2f6a..4855869 100644
--- a/drivers/dfu/dfu_mtd.c
+++ b/drivers/dfu/dfu_mtd.c
@@ -85,27 +85,41 @@
while (remaining) {
if (erase_op.addr + remaining > lim) {
- printf("Limit reached 0x%llx while erasing at offset 0x%llx\n",
- lim, off);
+ printf("Limit reached 0x%llx while erasing at offset 0x%llx, remaining 0x%llx\n",
+ lim, erase_op.addr, remaining);
return -EIO;
}
+ /* Skip the block if it is bad, don't erase it again */
+ ret = mtd_block_isbad(mtd, erase_op.addr);
+ if (ret) {
+ printf("Skipping %s at 0x%08llx\n",
+ ret == 1 ? "bad block" : "bbt reserved",
+ erase_op.addr);
+ erase_op.addr += mtd->erasesize;
+ continue;
+ }
+
ret = mtd_erase(mtd, &erase_op);
if (ret) {
- /* Abort if its not a bad block error */
- if (ret != -EIO) {
- printf("Failure while erasing at offset 0x%llx\n",
- erase_op.fail_addr);
- return 0;
+ /* If this is not -EIO, we have no idea what to do. */
+ if (ret == -EIO) {
+ printf("Marking bad block at 0x%08llx (%d)\n",
+ erase_op.fail_addr, ret);
+ ret = mtd_block_markbad(mtd, erase_op.addr);
}
- printf("Skipping bad block at 0x%08llx\n",
- erase_op.addr);
+ /* Abort if it is not -EIO or can't mark bad */
+ if (ret) {
+ printf("Failure while erasing at offset 0x%llx (%d)\n",
+ erase_op.fail_addr, ret);
+ return ret;
+ }
} else {
remaining -= mtd->erasesize;
}
- /* Continue erase behind bad block */
+ /* Continue erase behind the current block */
erase_op.addr += mtd->erasesize;
}
}
diff --git a/drivers/dfu/dfu_ram.c b/drivers/dfu/dfu_ram.c
index 9d10303..c4f4bd2 100644
--- a/drivers/dfu/dfu_ram.c
+++ b/drivers/dfu/dfu_ram.c
@@ -13,6 +13,7 @@
#include <mapmem.h>
#include <errno.h>
#include <dfu.h>
+#include <linux/printk.h>
static int dfu_transfer_medium_ram(enum dfu_op op, struct dfu_entity *dfu,
u64 offset, void *buf, long *len)
diff --git a/drivers/dma/bcm6348-iudma.c b/drivers/dma/bcm6348-iudma.c
index 4fc6502..d4cfe0c 100644
--- a/drivers/dma/bcm6348-iudma.c
+++ b/drivers/dma/bcm6348-iudma.c
@@ -28,6 +28,7 @@
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#define DMA_RX_DESC 6
#define DMA_TX_DESC 1
diff --git a/drivers/dma/dma-uclass.c b/drivers/dma/dma-uclass.c
index 34f72fa..0c1d88e 100644
--- a/drivers/dma/dma-uclass.c
+++ b/drivers/dma/dma-uclass.c
@@ -22,6 +22,7 @@
#include <linux/dma-mapping.h>
#include <dt-structs.h>
#include <errno.h>
+#include <linux/printk.h>
#ifdef CONFIG_DMA_CHANNELS
static inline struct dma_ops *dma_dev_ops(struct udevice *dev)
diff --git a/drivers/dma/lpc32xx_dma.c b/drivers/dma/lpc32xx_dma.c
index ab58e97..0efdfd0 100644
--- a/drivers/dma/lpc32xx_dma.c
+++ b/drivers/dma/lpc32xx_dma.c
@@ -17,6 +17,7 @@
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <linux/printk.h>
/* DMA controller channel register structure */
struct dmac_chan_reg {
diff --git a/drivers/dma/sandbox-dma-test.c b/drivers/dma/sandbox-dma-test.c
index 2b8259a..a19e5e3 100644
--- a/drivers/dma/sandbox-dma-test.c
+++ b/drivers/dma/sandbox-dma-test.c
@@ -15,6 +15,7 @@
#include <dma-uclass.h>
#include <dt-structs.h>
#include <errno.h>
+#include <linux/printk.h>
#define SANDBOX_DMA_CH_CNT 3
#define SANDBOX_DMA_BUF_SIZE 1024
diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c
index 1ad3b92..31ffff0 100644
--- a/drivers/dma/ti-edma3.c
+++ b/drivers/dma/ti-edma3.c
@@ -16,6 +16,7 @@
#include <linux/dma-mapping.h>
#include <asm/omap_common.h>
#include <asm/ti-common/ti-edma3.h>
+#include <linux/printk.h>
#define EDMA3_SL_BASE(slot) (0x4000 + ((slot) << 5))
#define EDMA3_SL_MAX_NUM 512
diff --git a/drivers/dma/ti/k3-psil-am64.c b/drivers/dma/ti/k3-psil-am64.c
index 15742c3..6180e2a 100644
--- a/drivers/dma/ti/k3-psil-am64.c
+++ b/drivers/dma/ti/k3-psil-am64.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
*/
diff --git a/drivers/dma/ti/k3-psil-am654.c b/drivers/dma/ti/k3-psil-am654.c
index d16c075..ce86600 100644
--- a/drivers/dma/ti/k3-psil-am654.c
+++ b/drivers/dma/ti/k3-psil-am654.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
*/
diff --git a/drivers/dma/ti/k3-psil-j721e.c b/drivers/dma/ti/k3-psil-j721e.c
index 105ffd9..8e57e86 100644
--- a/drivers/dma/ti/k3-psil-j721e.c
+++ b/drivers/dma/ti/k3-psil-j721e.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019-2023 Texas Instruments Incorporated - https://www.ti.com
* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
*/
@@ -21,13 +21,15 @@
/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
static struct psil_ep j721e_src_ep_map[] = {
- /* CPSW0 */
+ /* MCU_CPSW0 */
PSIL_ETHERNET(0x7000),
+ /* MAIN_CPSW0 */
+ PSIL_ETHERNET(0x4a00),
};
/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
static struct psil_ep j721e_dst_ep_map[] = {
- /* CPSW0 */
+ /* MCU_CPSW0 */
PSIL_ETHERNET(0xf000),
PSIL_ETHERNET(0xf001),
PSIL_ETHERNET(0xf002),
@@ -36,6 +38,15 @@
PSIL_ETHERNET(0xf005),
PSIL_ETHERNET(0xf006),
PSIL_ETHERNET(0xf007),
+ /* MAIN_CPSW0 */
+ PSIL_ETHERNET(0xca00),
+ PSIL_ETHERNET(0xca01),
+ PSIL_ETHERNET(0xca02),
+ PSIL_ETHERNET(0xca03),
+ PSIL_ETHERNET(0xca04),
+ PSIL_ETHERNET(0xca05),
+ PSIL_ETHERNET(0xca06),
+ PSIL_ETHERNET(0xca07),
};
struct psil_ep_map j721e_ep_map = {
diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h
index 28078c6..563bc57 100644
--- a/drivers/dma/ti/k3-psil-priv.h
+++ b/drivers/dma/ti/k3-psil-priv.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*/
#ifndef K3_PSIL_PRIV_H_
diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c
index f23c8ca..963321a 100644
--- a/drivers/dma/ti/k3-psil.c
+++ b/drivers/dma/ti/k3-psil.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
*/
diff --git a/drivers/dma/ti/k3-psil.h b/drivers/dma/ti/k3-psil.h
index 1e0fe06..af60a99 100644
--- a/drivers/dma/ti/k3-psil.h
+++ b/drivers/dma/ti/k3-psil.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*/
#ifndef K3_PSIL_H_
diff --git a/drivers/dma/ti/k3-udma-hwdef.h b/drivers/dma/ti/k3-udma-hwdef.h
index 5d50bbc..3d6b4d1 100644
--- a/drivers/dma/ti/k3-udma-hwdef.h
+++ b/drivers/dma/ti/k3-udma-hwdef.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
*
*
* This program is free software; you can redistribute it and/or modify
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 05c3a43..8a62d63 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
*/
#define pr_fmt(fmt) "udma: " fmt
@@ -25,6 +25,7 @@
#include <linux/delay.h>
#include <linux/bitmap.h>
#include <linux/err.h>
+#include <linux/printk.h>
#include <linux/soc/ti/k3-navss-ringacc.h>
#include <linux/soc/ti/cppi5.h>
#include <linux/soc/ti/ti-udma.h>
@@ -1286,7 +1287,7 @@
u32 cap2, cap3, cap4;
int i;
- ud->mmrs[MMR_GCFG] = (uint32_t *)devfdt_get_addr_name(dev, mmr_names[MMR_GCFG]);
+ ud->mmrs[MMR_GCFG] = dev_read_addr_name_ptr(dev, mmr_names[MMR_GCFG]);
if (!ud->mmrs[MMR_GCFG])
return -EINVAL;
@@ -1324,8 +1325,7 @@
if (i == MMR_RCHANRT && ud->rchan_cnt == 0)
continue;
- ud->mmrs[i] = (uint32_t *)devfdt_get_addr_name(dev,
- mmr_names[i]);
+ ud->mmrs[i] = dev_read_addr_name_ptr(dev, mmr_names[i]);
if (!ud->mmrs[i])
return -EINVAL;
}
diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
index 4bf31ab..39b409c 100644
--- a/drivers/fastboot/Kconfig
+++ b/drivers/fastboot/Kconfig
@@ -56,7 +56,7 @@
ROCKCHIP_RK3399
default 0x280000 if ROCKCHIP_RK3368
default 0x100000 if ARCH_ZYNQMP
- default 0 if SANDBOX
+ default 0x0 if SANDBOX
help
The fastboot protocol requires a large memory buffer for
downloads. Define this to the starting RAM address to use for
diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c
index 4a0467d..2f3e25a 100644
--- a/drivers/fastboot/fb_command.c
+++ b/drivers/fastboot/fb_command.c
@@ -14,6 +14,7 @@
#include <fb_nand.h>
#include <part.h>
#include <stdlib.h>
+#include <linux/printk.h>
/**
* image_size - final fastboot image size
diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c
index 02c472e..2969444 100644
--- a/drivers/fastboot/fb_getvar.c
+++ b/drivers/fastboot/fb_getvar.c
@@ -13,6 +13,7 @@
#include <fs.h>
#include <part.h>
#include <version.h>
+#include <linux/printk.h>
static void getvar_version(char *var_parameter, char *response);
static void getvar_version_bootloader(char *var_parameter, char *response);
@@ -189,7 +190,7 @@
/* part_name_wslot = part_name + "_a" */
len = strlcpy(part_name_wslot, part_name, PART_NAME_LEN - 3);
- if (len > PART_NAME_LEN - 3)
+ if (len >= PART_NAME_LEN - 3)
goto fail;
strcat(part_name_wslot, "_a");
diff --git a/drivers/fastboot/fb_nand.c b/drivers/fastboot/fb_nand.c
index 6d3a900..bbe26dd 100644
--- a/drivers/fastboot/fb_nand.c
+++ b/drivers/fastboot/fb_nand.c
@@ -11,6 +11,7 @@
#include <fastboot.h>
#include <image-sparse.h>
+#include <linux/printk.h>
#include <linux/mtd/mtd.h>
#include <jffs2/jffs2.h>
#include <nand.h>
diff --git a/drivers/firmware/arm-ffa/arm-ffa-uclass.c b/drivers/firmware/arm-ffa/arm-ffa-uclass.c
index 8c17b19..f1e91d1 100644
--- a/drivers/firmware/arm-ffa/arm-ffa-uclass.c
+++ b/drivers/firmware/arm-ffa/arm-ffa-uclass.c
@@ -144,8 +144,6 @@
return -EINVAL;
abi_idx = FFA_ID_TO_ERRMAP_ID(ffa_id);
- if (abi_idx < 0 || abi_idx >= FFA_ERRMAP_COUNT)
- return -EINVAL;
if (!err_msg_map[abi_idx].err_str[err_idx])
return -EINVAL;
diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c
index ab4c4f1..8ea15c7 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -195,6 +195,21 @@
return ret;
}
+int zynqmp_pm_feature(const u32 api_id)
+{
+ int ret;
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+
+ /* Check feature check API version */
+ ret = xilinx_pm_request(PM_FEATURE_CHECK, api_id, 0, 0, 0,
+ ret_payload);
+ if (ret)
+ return ret;
+
+ /* Return feature check version */
+ return ret_payload[1] & FIRMWARE_VERSION_MASK;
+}
+
int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
{
int ret;
diff --git a/drivers/firmware/scmi/Makefile b/drivers/firmware/scmi/Makefile
index b2ff483..dae4286 100644
--- a/drivers/firmware/scmi/Makefile
+++ b/drivers/firmware/scmi/Makefile
@@ -1,6 +1,8 @@
obj-y += scmi_agent-uclass.o
+obj-y += base.o
obj-y += smt.o
obj-$(CONFIG_SCMI_AGENT_SMCCC) += smccc_agent.o
obj-$(CONFIG_SCMI_AGENT_MAILBOX) += mailbox_agent.o
obj-$(CONFIG_SCMI_AGENT_OPTEE) += optee_agent.o
+obj-$(CONFIG_SCMI_POWER_DOMAIN) += pwdom.o
obj-$(CONFIG_SANDBOX) += sandbox-scmi_agent.o sandbox-scmi_devices.o
diff --git a/drivers/firmware/scmi/base.c b/drivers/firmware/scmi/base.c
new file mode 100644
index 0000000..1d41a8a
--- /dev/null
+++ b/drivers/firmware/scmi/base.c
@@ -0,0 +1,664 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * SCMI Base protocol as U-Boot device
+ *
+ * Copyright (C) 2023 Linaro Limited
+ * author: AKASHI Takahiro <takahiro.akashi@linaro.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <scmi_agent.h>
+#include <scmi_protocols.h>
+#include <stdlib.h>
+#include <string.h>
+#include <asm/types.h>
+#include <dm/device_compat.h>
+#include <linux/kernel.h>
+
+/**
+ * scmi_generic_protocol_version - get protocol version
+ * @dev: SCMI device
+ * @id: SCMI protocol ID
+ * @version: Pointer to SCMI protocol version
+ *
+ * Obtain the protocol version number in @version.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int scmi_generic_protocol_version(struct udevice *dev,
+ enum scmi_std_protocol id, u32 *version)
+{
+ struct scmi_protocol_version_out out;
+ struct scmi_msg msg = {
+ .protocol_id = id,
+ .message_id = SCMI_PROTOCOL_VERSION,
+ .out_msg = (u8 *)&out,
+ .out_msg_sz = sizeof(out),
+ };
+ int ret;
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret)
+ return ret;
+ if (out.status)
+ return scmi_to_linux_errno(out.status);
+
+ *version = out.version;
+
+ return 0;
+}
+
+/**
+ * scmi_base_protocol_version_int - get Base protocol version
+ * @dev: SCMI device
+ * @version: Pointer to SCMI protocol version
+ *
+ * Obtain the protocol version number in @version for Base protocol.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int scmi_base_protocol_version_int(struct udevice *dev, u32 *version)
+{
+ return scmi_generic_protocol_version(dev, SCMI_PROTOCOL_ID_BASE,
+ version);
+}
+
+/**
+ * scmi_protocol_attrs_int - get protocol attributes
+ * @dev: SCMI device
+ * @num_agents: Number of SCMI agents
+ * @num_protocols: Number of SCMI protocols
+ *
+ * Obtain the protocol attributes, the number of agents and the number
+ * of protocols, in @num_agents and @num_protocols respectively, that
+ * the device provides.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int scmi_protocol_attrs_int(struct udevice *dev, u32 *num_agents,
+ u32 *num_protocols)
+{
+ struct scmi_protocol_attrs_out out;
+ struct scmi_msg msg = {
+ .protocol_id = SCMI_PROTOCOL_ID_BASE,
+ .message_id = SCMI_PROTOCOL_ATTRIBUTES,
+ .out_msg = (u8 *)&out,
+ .out_msg_sz = sizeof(out),
+ };
+ int ret;
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret)
+ return ret;
+ if (out.status)
+ return scmi_to_linux_errno(out.status);
+
+ *num_agents = SCMI_PROTOCOL_ATTRS_NUM_AGENTS(out.attributes);
+ *num_protocols = SCMI_PROTOCOL_ATTRS_NUM_PROTOCOLS(out.attributes);
+
+ return 0;
+}
+
+/**
+ * scmi_protocol_message_attrs_int - get message-specific attributes
+ * @dev: SCMI device
+ * @message_id: SCMI message ID
+ * @attributes: Message-specific attributes
+ *
+ * Obtain the message-specific attributes in @attributes.
+ * This command succeeds if the message is implemented and available.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int scmi_protocol_message_attrs_int(struct udevice *dev, u32 message_id,
+ u32 *attributes)
+{
+ struct scmi_protocol_msg_attrs_out out;
+ struct scmi_msg msg = {
+ .protocol_id = SCMI_PROTOCOL_ID_BASE,
+ .message_id = SCMI_PROTOCOL_MESSAGE_ATTRIBUTES,
+ .in_msg = (u8 *)&message_id,
+ .in_msg_sz = sizeof(message_id),
+ .out_msg = (u8 *)&out,
+ .out_msg_sz = sizeof(out),
+ };
+ int ret;
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret)
+ return ret;
+ if (out.status)
+ return scmi_to_linux_errno(out.status);
+
+ *attributes = out.attributes;
+
+ return 0;
+}
+
+/**
+ * scmi_base_discover_vendor_int - get vendor name
+ * @dev: SCMI device
+ * @vendor: Pointer to vendor name
+ *
+ * Obtain the vendor's name in @vendor.
+ * It is a caller's responsibility to free @vendor.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int scmi_base_discover_vendor_int(struct udevice *dev, u8 **vendor)
+{
+ struct scmi_base_discover_vendor_out out;
+ struct scmi_msg msg = {
+ .protocol_id = SCMI_PROTOCOL_ID_BASE,
+ .message_id = SCMI_BASE_DISCOVER_VENDOR,
+ .out_msg = (u8 *)&out,
+ .out_msg_sz = sizeof(out),
+ };
+ int ret;
+
+ if (!vendor)
+ return -EINVAL;
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret)
+ return ret;
+ if (out.status)
+ return scmi_to_linux_errno(out.status);
+
+ *vendor = strdup(out.vendor_identifier);
+ if (!*vendor)
+ return -ENOMEM;
+
+ return 0;
+}
+
+/**
+ * scmi_base_discover_sub_vendor_int - get sub-vendor name
+ * @dev: SCMI device
+ * @sub_vendor: Pointer to sub-vendor name
+ *
+ * Obtain the sub-vendor's name in @sub_vendor.
+ * It is a caller's responsibility to free @sub_vendor.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int scmi_base_discover_sub_vendor_int(struct udevice *dev,
+ u8 **sub_vendor)
+{
+ struct scmi_base_discover_vendor_out out;
+ struct scmi_msg msg = {
+ .protocol_id = SCMI_PROTOCOL_ID_BASE,
+ .message_id = SCMI_BASE_DISCOVER_SUB_VENDOR,
+ .out_msg = (u8 *)&out,
+ .out_msg_sz = sizeof(out),
+ };
+ int ret;
+
+ if (!sub_vendor)
+ return -EINVAL;
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret)
+ return ret;
+ if (out.status)
+ return scmi_to_linux_errno(out.status);
+
+ *sub_vendor = strdup(out.vendor_identifier);
+ if (!*sub_vendor)
+ return -ENOMEM;
+
+ return 0;
+}
+
+/**
+ * scmi_base_discover_impl_version_int - get implementation version
+ * @dev: SCMI device
+ * @impl_version: Pointer to implementation version
+ *
+ * Obtain the implementation version number in @impl_version.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int scmi_base_discover_impl_version_int(struct udevice *dev,
+ u32 *impl_version)
+{
+ struct scmi_base_discover_impl_version_out out;
+ struct scmi_msg msg = {
+ .protocol_id = SCMI_PROTOCOL_ID_BASE,
+ .message_id = SCMI_BASE_DISCOVER_IMPL_VERSION,
+ .out_msg = (u8 *)&out,
+ .out_msg_sz = sizeof(out),
+ };
+ int ret;
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret)
+ return ret;
+ if (out.status)
+ return scmi_to_linux_errno(out.status);
+
+ *impl_version = out.impl_version;
+
+ return 0;
+}
+
+/**
+ * scmi_base_discover_list_protocols_int - get list of protocols
+ * @dev: SCMI device
+ * @protocols: Pointer to array of SCMI protocols
+ *
+ * Obtain the list of protocols provided in @protocols.
+ * The number of elements in @protocols always match to the number of
+ * protocols returned by smci_protocol_attrs() when this function succeeds.
+ * It is a caller's responsibility to free @protocols.
+ *
+ * Return: the number of protocols in @protocols on success, error code on
+ * failure
+ */
+static int scmi_base_discover_list_protocols_int(struct udevice *dev,
+ u8 **protocols)
+{
+ struct scmi_base_discover_list_protocols_out out;
+ int cur;
+ struct scmi_msg msg = {
+ .protocol_id = SCMI_PROTOCOL_ID_BASE,
+ .message_id = SCMI_BASE_DISCOVER_LIST_PROTOCOLS,
+ .in_msg = (u8 *)&cur,
+ .in_msg_sz = sizeof(cur),
+ .out_msg = (u8 *)&out,
+ .out_msg_sz = sizeof(out),
+ };
+ u32 num_agents, num_protocols;
+ u8 *buf;
+ int i, ret;
+
+ ret = scmi_base_protocol_attrs(dev, &num_agents, &num_protocols);
+ if (ret)
+ return ret;
+
+ buf = calloc(sizeof(u8), num_protocols);
+ if (!buf)
+ return -ENOMEM;
+
+ cur = 0;
+ do {
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret)
+ goto err;
+ if (out.status) {
+ ret = scmi_to_linux_errno(out.status);
+ goto err;
+ }
+
+ for (i = 0; i < out.num_protocols; i++, cur++)
+ buf[cur] = out.protocols[i / 4] >> ((i % 4) * 8);
+ } while (cur < num_protocols);
+
+ *protocols = buf;
+
+ return num_protocols;
+err:
+ free(buf);
+
+ return ret;
+}
+
+/**
+ * scmi_base_discover_agent_int - identify agent
+ * @dev: SCMI device
+ * @agent_id: SCMI agent ID
+ * @ret_agent_id: Pointer to SCMI agent ID
+ * @name: Pointer to SCMI agent name
+ *
+ * Obtain the agent's name in @name. If @agent_id is equal to 0xffffffff,
+ * this function returns the caller's agent id in @ret_agent_id.
+ * It is a caller's responsibility to free @name.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int scmi_base_discover_agent_int(struct udevice *dev, u32 agent_id,
+ u32 *ret_agent_id, u8 **name)
+{
+ struct scmi_base_discover_agent_out out;
+ struct scmi_msg msg = {
+ .protocol_id = SCMI_PROTOCOL_ID_BASE,
+ .message_id = SCMI_BASE_DISCOVER_AGENT,
+ .in_msg = (u8 *)&agent_id,
+ .in_msg_sz = sizeof(agent_id),
+ .out_msg = (u8 *)&out,
+ .out_msg_sz = sizeof(out),
+ };
+ int ret;
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret)
+ return ret;
+ if (out.status)
+ return scmi_to_linux_errno(out.status);
+
+ if (ret_agent_id)
+ *ret_agent_id = out.agent_id;
+ if (name) {
+ *name = strdup(out.name);
+ if (!*name)
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+/**
+ * scmi_base_set_device_permissions_int - configure access permission to device
+ * @dev: SCMI device
+ * @agent_id: SCMI agent ID
+ * @device_id: ID of device to access
+ * @flags: A set of flags
+ *
+ * Ask for allowing or denying access permission to the device, @device_id.
+ * The meaning of @flags is defined in SCMI specification.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int scmi_base_set_device_permissions_int(struct udevice *dev, u32 agent_id,
+ u32 device_id, u32 flags)
+{
+ struct scmi_base_set_device_permissions_in in = {
+ .agent_id = agent_id,
+ .device_id = device_id,
+ .flags = flags,
+ };
+ s32 status;
+ struct scmi_msg msg = {
+ .protocol_id = SCMI_PROTOCOL_ID_BASE,
+ .message_id = SCMI_BASE_SET_DEVICE_PERMISSIONS,
+ .in_msg = (u8 *)&in,
+ .in_msg_sz = sizeof(in),
+ .out_msg = (u8 *)&status,
+ .out_msg_sz = sizeof(status),
+ };
+ int ret;
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret)
+ return ret;
+ if (status)
+ return scmi_to_linux_errno(status);
+
+ return 0;
+}
+
+/**
+ * scmi_base_set_protocol_permissions_int - configure access permission to
+ * protocol on device
+ * @dev: SCMI device
+ * @agent_id: SCMI agent ID
+ * @device_id: ID of device to access
+ * @command_id: SCMI command ID
+ * @flags: A set of flags
+ *
+ * Ask for allowing or denying access permission to the protocol, @command_id,
+ * on the device, @device_id.
+ * The meaning of @flags is defined in SCMI specification.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int scmi_base_set_protocol_permissions_int(struct udevice *dev,
+ u32 agent_id, u32 device_id,
+ u32 command_id, u32 flags)
+{
+ struct scmi_base_set_protocol_permissions_in in = {
+ .agent_id = agent_id,
+ .device_id = device_id,
+ .command_id = command_id,
+ .flags = flags,
+ };
+ s32 status;
+ struct scmi_msg msg = {
+ .protocol_id = SCMI_PROTOCOL_ID_BASE,
+ .message_id = SCMI_BASE_SET_PROTOCOL_PERMISSIONS,
+ .in_msg = (u8 *)&in,
+ .in_msg_sz = sizeof(in),
+ .out_msg = (u8 *)&status,
+ .out_msg_sz = sizeof(status),
+ };
+ int ret;
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret)
+ return ret;
+ if (status)
+ return scmi_to_linux_errno(status);
+
+ return 0;
+}
+
+/**
+ * scmi_base_reset_agent_configuration_int - reset resource settings
+ * @dev: SCMI device
+ * @agent_id: SCMI agent ID
+ * @flags: A set of flags
+ *
+ * Reset all the resource settings against @agent_id.
+ * The meaning of @flags is defined in SCMI specification.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int scmi_base_reset_agent_configuration_int(struct udevice *dev,
+ u32 agent_id, u32 flags)
+{
+ struct scmi_base_reset_agent_configuration_in in = {
+ .agent_id = agent_id,
+ .flags = flags,
+ };
+ s32 status;
+ struct scmi_msg msg = {
+ .protocol_id = SCMI_PROTOCOL_ID_BASE,
+ .message_id = SCMI_BASE_RESET_AGENT_CONFIGURATION,
+ .in_msg = (u8 *)&in,
+ .in_msg_sz = sizeof(in),
+ .out_msg = (u8 *)&status,
+ .out_msg_sz = sizeof(status),
+ };
+ int ret;
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret)
+ return ret;
+ if (status)
+ return scmi_to_linux_errno(status);
+
+ return 0;
+}
+
+/**
+ * scmi_base_probe - probe base protocol device
+ * @dev: SCMI device
+ *
+ * Probe the device for SCMI base protocol and initialize the private data.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int scmi_base_probe(struct udevice *dev)
+{
+ u32 version;
+ int ret;
+
+ ret = devm_scmi_of_get_channel(dev);
+ if (ret) {
+ dev_err(dev, "get_channel failed\n");
+ return ret;
+ }
+ ret = scmi_base_protocol_version_int(dev, &version);
+ if (ret) {
+ dev_err(dev, "getting protocol version failed\n");
+ return ret;
+ }
+ if (version < SCMI_BASE_PROTOCOL_VERSION)
+ return -EINVAL;
+
+ return ret;
+}
+
+static struct scmi_base_ops scmi_base_ops = {
+ /* Commands */
+ .protocol_version = scmi_base_protocol_version_int,
+ .protocol_attrs = scmi_protocol_attrs_int,
+ .protocol_message_attrs = scmi_protocol_message_attrs_int,
+ .base_discover_vendor = scmi_base_discover_vendor_int,
+ .base_discover_sub_vendor = scmi_base_discover_sub_vendor_int,
+ .base_discover_impl_version = scmi_base_discover_impl_version_int,
+ .base_discover_list_protocols = scmi_base_discover_list_protocols_int,
+ .base_discover_agent = scmi_base_discover_agent_int,
+ .base_notify_errors = NULL,
+ .base_set_device_permissions = scmi_base_set_device_permissions_int,
+ .base_set_protocol_permissions = scmi_base_set_protocol_permissions_int,
+ .base_reset_agent_configuration =
+ scmi_base_reset_agent_configuration_int,
+};
+
+int scmi_base_protocol_version(struct udevice *dev, u32 *version)
+{
+ const struct scmi_base_ops *ops = device_get_ops(dev);
+
+ if (ops->protocol_version)
+ return (*ops->protocol_version)(dev, version);
+
+ return -EOPNOTSUPP;
+}
+
+int scmi_base_protocol_attrs(struct udevice *dev, u32 *num_agents,
+ u32 *num_protocols)
+{
+ const struct scmi_base_ops *ops = device_get_ops(dev);
+
+ if (ops->protocol_attrs)
+ return (*ops->protocol_attrs)(dev, num_agents, num_protocols);
+
+ return -EOPNOTSUPP;
+}
+
+int scmi_base_protocol_message_attrs(struct udevice *dev, u32 message_id,
+ u32 *attributes)
+{
+ const struct scmi_base_ops *ops = device_get_ops(dev);
+
+ if (ops->protocol_message_attrs)
+ return (*ops->protocol_message_attrs)(dev, message_id,
+ attributes);
+
+ return -EOPNOTSUPP;
+}
+
+int scmi_base_discover_vendor(struct udevice *dev, u8 **vendor)
+{
+ const struct scmi_base_ops *ops = device_get_ops(dev);
+
+ if (ops->base_discover_vendor)
+ return (*ops->base_discover_vendor)(dev, vendor);
+
+ return -EOPNOTSUPP;
+}
+
+int scmi_base_discover_sub_vendor(struct udevice *dev, u8 **sub_vendor)
+{
+ const struct scmi_base_ops *ops = device_get_ops(dev);
+
+ if (ops->base_discover_sub_vendor)
+ return (*ops->base_discover_sub_vendor)(dev, sub_vendor);
+
+ return -EOPNOTSUPP;
+}
+
+int scmi_base_discover_impl_version(struct udevice *dev, u32 *impl_version)
+{
+ const struct scmi_base_ops *ops = device_get_ops(dev);
+
+ if (ops->base_discover_impl_version)
+ return (*ops->base_discover_impl_version)(dev, impl_version);
+
+ return -EOPNOTSUPP;
+}
+
+int scmi_base_discover_list_protocols(struct udevice *dev, u8 **protocols)
+{
+ const struct scmi_base_ops *ops = device_get_ops(dev);
+
+ if (ops->base_discover_list_protocols)
+ return (*ops->base_discover_list_protocols)(dev, protocols);
+
+ return -EOPNOTSUPP;
+}
+
+int scmi_base_discover_agent(struct udevice *dev, u32 agent_id,
+ u32 *ret_agent_id, u8 **name)
+{
+ const struct scmi_base_ops *ops = device_get_ops(dev);
+
+ if (ops->base_discover_agent)
+ return (*ops->base_discover_agent)(dev, agent_id, ret_agent_id,
+ name);
+
+ return -EOPNOTSUPP;
+}
+
+int scmi_base_notify_errors(struct udevice *dev, u32 enable)
+{
+ const struct scmi_base_ops *ops = device_get_ops(dev);
+
+ if (ops->base_notify_errors)
+ return (*ops->base_notify_errors)(dev, enable);
+
+ return -EOPNOTSUPP;
+}
+
+int scmi_base_set_device_permissions(struct udevice *dev, u32 agent_id,
+ u32 device_id, u32 flags)
+{
+ const struct scmi_base_ops *ops = device_get_ops(dev);
+
+ if (ops->base_set_device_permissions)
+ return (*ops->base_set_device_permissions)(dev, agent_id,
+ device_id, flags);
+
+ return -EOPNOTSUPP;
+}
+
+int scmi_base_set_protocol_permissions(struct udevice *dev,
+ u32 agent_id, u32 device_id,
+ u32 command_id, u32 flags)
+{
+ const struct scmi_base_ops *ops = device_get_ops(dev);
+
+ if (ops->base_set_protocol_permissions)
+ return (*ops->base_set_protocol_permissions)(dev, agent_id,
+ device_id,
+ command_id,
+ flags);
+
+ return -EOPNOTSUPP;
+}
+
+int scmi_base_reset_agent_configuration(struct udevice *dev, u32 agent_id,
+ u32 flags)
+{
+ const struct scmi_base_ops *ops = device_get_ops(dev);
+
+ if (ops->base_reset_agent_configuration)
+ return (*ops->base_reset_agent_configuration)(dev, agent_id,
+ flags);
+
+ return -EOPNOTSUPP;
+}
+
+U_BOOT_DRIVER(scmi_base_drv) = {
+ .id = UCLASS_SCMI_BASE,
+ .name = "scmi_base_drv",
+ .ops = &scmi_base_ops,
+ .probe = scmi_base_probe,
+};
+
+UCLASS_DRIVER(scmi_base) = {
+ .id = UCLASS_SCMI_BASE,
+ .name = "scmi_base",
+};
diff --git a/drivers/firmware/scmi/mailbox_agent.c b/drivers/firmware/scmi/mailbox_agent.c
index 8277c18..7ad3e8d 100644
--- a/drivers/firmware/scmi/mailbox_agent.c
+++ b/drivers/firmware/scmi/mailbox_agent.c
@@ -94,13 +94,14 @@
}
static int scmi_mbox_get_channel(struct udevice *dev,
+ struct udevice *protocol,
struct scmi_channel **channel)
{
struct scmi_mbox_channel *base_chan = dev_get_plat(dev);
struct scmi_mbox_channel *chan;
int ret;
- if (!dev_read_prop(dev, "shmem", NULL)) {
+ if (!dev_read_prop(protocol, "shmem", NULL)) {
/* Uses agent base channel */
*channel = container_of(base_chan, struct scmi_channel, ref);
@@ -112,7 +113,7 @@
return -ENOMEM;
/* Setup a dedicated channel for the protocol */
- ret = setup_channel(dev, chan);
+ ret = setup_channel(protocol, chan);
if (ret) {
free(chan);
return ret;
diff --git a/drivers/firmware/scmi/optee_agent.c b/drivers/firmware/scmi/optee_agent.c
index db927fb..48dbb88 100644
--- a/drivers/firmware/scmi/optee_agent.c
+++ b/drivers/firmware/scmi/optee_agent.c
@@ -149,7 +149,7 @@
struct tee_param param[1] = { };
int ret;
- memset(sess, 0, sizeof(sess));
+ memset(sess, 0, sizeof(*sess));
sess->tee = tee_find_device(NULL, NULL, NULL, NULL);
if (!sess->tee)
@@ -324,6 +324,7 @@
}
static int scmi_optee_get_channel(struct udevice *dev,
+ struct udevice *protocol,
struct scmi_channel **channel)
{
struct scmi_optee_channel *base_chan = dev_get_plat(dev);
@@ -331,7 +332,7 @@
u32 channel_id;
int ret;
- if (dev_read_u32(dev, "linaro,optee-channel-id", &channel_id)) {
+ if (dev_read_u32(protocol, "linaro,optee-channel-id", &channel_id)) {
/* Uses agent base channel */
*channel = container_of(base_chan, struct scmi_channel, ref);
@@ -343,7 +344,7 @@
if (!chan)
return -ENOMEM;
- ret = setup_channel(dev, chan);
+ ret = setup_channel(protocol, chan);
if (ret) {
free(chan);
return ret;
diff --git a/drivers/firmware/scmi/pwdom.c b/drivers/firmware/scmi/pwdom.c
new file mode 100644
index 0000000..de2ba47
--- /dev/null
+++ b/drivers/firmware/scmi/pwdom.c
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * SCMI Power domain management protocol
+ *
+ * Copyright (C) 2023 Linaro Limited
+ * author: AKASHI Takahiro <takahiro.akashi@linaro.org>
+ */
+
+#include <dm.h>
+#include <malloc.h>
+#include <scmi_agent.h>
+#include <scmi_protocols.h>
+#include <string.h>
+#include <asm/types.h>
+
+int scmi_pwd_protocol_attrs(struct udevice *dev, int *num_pwdoms,
+ u64 *stats_addr, size_t *stats_len)
+{
+ struct scmi_pwd_protocol_attrs_out out;
+ struct scmi_msg msg = {
+ .protocol_id = SCMI_PROTOCOL_ID_POWER_DOMAIN,
+ .message_id = SCMI_PROTOCOL_ATTRIBUTES,
+ .out_msg = (u8 *)&out,
+ .out_msg_sz = sizeof(out),
+ };
+ int ret;
+
+ if (!dev || !num_pwdoms || !stats_addr || !stats_len)
+ return -EINVAL;
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret)
+ return ret;
+ if (out.status)
+ return scmi_to_linux_errno(out.status);
+
+ *num_pwdoms = SCMI_PWD_PROTO_ATTRS_NUM_PWD(out.attributes);
+ *stats_addr = ((u64)out.stats_addr_high << 32) + out.stats_addr_low;
+ *stats_len = out.stats_len;
+
+ return 0;
+}
+
+int scmi_pwd_protocol_message_attrs(struct udevice *dev, s32 message_id,
+ u32 *attributes)
+{
+ struct scmi_pwd_protocol_msg_attrs_out out;
+ struct scmi_msg msg = {
+ .protocol_id = SCMI_PROTOCOL_ID_POWER_DOMAIN,
+ .message_id = SCMI_PROTOCOL_MESSAGE_ATTRIBUTES,
+ .in_msg = (u8 *)&message_id,
+ .in_msg_sz = sizeof(message_id),
+ .out_msg = (u8 *)&out,
+ .out_msg_sz = sizeof(out),
+ };
+ int ret;
+
+ if (!dev || !attributes)
+ return -EINVAL;
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret)
+ return ret;
+ if (out.status)
+ return scmi_to_linux_errno(out.status);
+
+ *attributes = out.attributes;
+
+ return 0;
+}
+
+int scmi_pwd_attrs(struct udevice *dev, u32 domain_id, u32 *attributes,
+ u8 **name)
+{
+ struct scmi_pwd_attrs_out out;
+ struct scmi_msg msg = {
+ .protocol_id = SCMI_PROTOCOL_ID_POWER_DOMAIN,
+ .message_id = SCMI_PWD_ATTRIBUTES,
+ .in_msg = (u8 *)&domain_id,
+ .in_msg_sz = sizeof(domain_id),
+ .out_msg = (u8 *)&out,
+ .out_msg_sz = sizeof(out),
+ };
+ int ret;
+
+ if (!dev || !attributes || !name)
+ return -EINVAL;
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret)
+ return ret;
+ if (out.status)
+ return scmi_to_linux_errno(out.status);
+
+ *name = strdup(out.name);
+ if (!*name)
+ return -ENOMEM;
+
+ *attributes = out.attributes;
+
+ return 0;
+}
+
+int scmi_pwd_state_set(struct udevice *dev, u32 flags, u32 domain_id,
+ u32 pstate)
+{
+ struct scmi_pwd_state_set_in in;
+ s32 status;
+ struct scmi_msg msg = {
+ .protocol_id = SCMI_PROTOCOL_ID_POWER_DOMAIN,
+ .message_id = SCMI_PWD_STATE_SET,
+ .in_msg = (u8 *)&in,
+ .in_msg_sz = sizeof(in),
+ .out_msg = (u8 *)&status,
+ .out_msg_sz = sizeof(status),
+ };
+ int ret;
+
+ if (!dev)
+ return -EINVAL;
+
+ in.flags = flags;
+ in.domain_id = domain_id;
+ in.pstate = pstate;
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret)
+ return ret;
+ if (status)
+ return scmi_to_linux_errno(status);
+
+ return 0;
+}
+
+int scmi_pwd_state_get(struct udevice *dev, u32 domain_id, u32 *pstate)
+{
+ struct scmi_pwd_state_get_out out;
+ struct scmi_msg msg = {
+ .protocol_id = SCMI_PROTOCOL_ID_POWER_DOMAIN,
+ .message_id = SCMI_PWD_STATE_GET,
+ .in_msg = (u8 *)&domain_id,
+ .in_msg_sz = sizeof(domain_id),
+ .out_msg = (u8 *)&out,
+ .out_msg_sz = sizeof(out),
+ };
+ int ret;
+
+ if (!dev || !pstate)
+ return -EINVAL;
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret)
+ return ret;
+ if (out.status)
+ return scmi_to_linux_errno(out.status);
+
+ *pstate = out.pstate;
+
+ return 0;
+}
+
+int scmi_pwd_name_get(struct udevice *dev, u32 domain_id, u8 **name)
+{
+ struct scmi_pwd_name_get_out out;
+ struct scmi_msg msg = {
+ .protocol_id = SCMI_PROTOCOL_ID_POWER_DOMAIN,
+ .message_id = SCMI_PWD_NAME_GET,
+ .in_msg = (u8 *)&domain_id,
+ .in_msg_sz = sizeof(domain_id),
+ .out_msg = (u8 *)&out,
+ .out_msg_sz = sizeof(out),
+ };
+ int ret;
+
+ if (!dev || !name)
+ return -EINVAL;
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret)
+ return ret;
+ if (out.status)
+ return scmi_to_linux_errno(out.status);
+
+ *name = strdup(out.extended_name);
+ if (!*name)
+ return -ENOMEM;
+
+ return 0;
+}
diff --git a/drivers/firmware/scmi/sandbox-scmi_agent.c b/drivers/firmware/scmi/sandbox-scmi_agent.c
index 0318829..d131809 100644
--- a/drivers/firmware/scmi/sandbox-scmi_agent.c
+++ b/drivers/firmware/scmi/sandbox-scmi_agent.c
@@ -14,11 +14,14 @@
#include <asm/io.h>
#include <asm/scmi_test.h>
#include <dm/device_compat.h>
+#include <linux/bitfield.h>
+#include <linux/kernel.h>
/*
* The sandbox SCMI agent driver simulates to some extend a SCMI message
* processing. It simulates few of the SCMI services for some of the
* SCMI protocols embedded in U-Boot. Currently:
+ * - SCMI base protocol
* - SCMI clock protocol emulates an agent exposing 2 clocks
* - SCMI reset protocol emulates an agent exposing a reset controller
* - SCMI voltage domain protocol emulates an agent exposing 2 regulators
@@ -33,6 +36,50 @@
* various uclass devices, as clocks and reset controllers.
*/
+#define SANDBOX_SCMI_BASE_PROTOCOL_VERSION SCMI_BASE_PROTOCOL_VERSION
+#define SANDBOX_SCMI_VENDOR "U-Boot"
+#define SANDBOX_SCMI_SUB_VENDOR "Sandbox"
+#define SANDBOX_SCMI_IMPL_VERSION 0x1
+#define SANDBOX_SCMI_AGENT_NAME "OSPM"
+#define SANDBOX_SCMI_PLATFORM_NAME "platform"
+
+#define SANDBOX_SCMI_PWD_PROTOCOL_VERSION SCMI_PWD_PROTOCOL_VERSION
+
+/**
+ * struct sandbox_channel - Description of sandbox transport
+ * @channel_id: Channel identifier
+ *
+ * Dummy channel. This will be used to test if a protocol-specific
+ * channel is properly used.
+ * Id 0 means a channel for the sandbox agent.
+ */
+struct sandbox_channel {
+ unsigned int channel_id;
+};
+
+/**
+ * struct scmi_channel - Channel instance referenced in SCMI drivers
+ * @ref: Reference to local channel instance
+ **/
+struct scmi_channel {
+ struct sandbox_channel ref;
+};
+
+static u8 protocols[] = {
+ SCMI_PROTOCOL_ID_POWER_DOMAIN,
+ SCMI_PROTOCOL_ID_CLOCK,
+ SCMI_PROTOCOL_ID_RESET_DOMAIN,
+ SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN,
+};
+
+#define NUM_PROTOCOLS ARRAY_SIZE(protocols)
+
+static struct sandbox_scmi_pwd scmi_pwdom[] = {
+ { .id = 0 },
+ { .id = 1 },
+ { .id = 2 },
+};
+
static struct sandbox_scmi_clk scmi_clk[] = {
{ .rate = 333 },
{ .rate = 200 },
@@ -48,11 +95,9 @@
{ .id = 1, .voltage_uv = 1800000 },
};
-static struct sandbox_scmi_service sandbox_scmi_service_state;
-
-struct sandbox_scmi_service *sandbox_scmi_service_ctx(void)
+struct sandbox_scmi_agent *sandbox_scmi_agent_ctx(struct udevice *dev)
{
- return &sandbox_scmi_service_state;
+ return dev_get_priv(dev);
}
static void debug_print_agent_state(struct udevice *dev, char *str)
@@ -114,6 +159,548 @@
* Sandbox SCMI agent ops
*/
+/* Base Protocol */
+
+/**
+ * sandbox_scmi_base_protocol_version - implement SCMI_BASE_PROTOCOL_VERSION
+ * @dev: SCMI device
+ * @msg: SCMI message
+ *
+ * Implement SCMI_BASE_PROTOCOL_VERSION command.
+ */
+static int sandbox_scmi_base_protocol_version(struct udevice *dev,
+ struct scmi_msg *msg)
+{
+ struct scmi_protocol_version_out *out = NULL;
+
+ if (!msg->out_msg || msg->out_msg_sz < sizeof(*out))
+ return -EINVAL;
+
+ out = (struct scmi_protocol_version_out *)msg->out_msg;
+ out->version = SANDBOX_SCMI_BASE_PROTOCOL_VERSION;
+ out->status = SCMI_SUCCESS;
+
+ return 0;
+}
+
+/**
+ * sandbox_scmi_base_protocol_attrs - implement SCMI_BASE_PROTOCOL_ATTRIBUTES
+ * @dev: SCMI device
+ * @msg: SCMI message
+ *
+ * Implement SCMI_BASE_PROTOCOL_ATTRIBUTES command.
+ */
+static int sandbox_scmi_base_protocol_attrs(struct udevice *dev,
+ struct scmi_msg *msg)
+{
+ struct scmi_protocol_attrs_out *out = NULL;
+
+ if (!msg->out_msg || msg->out_msg_sz < sizeof(*out))
+ return -EINVAL;
+
+ out = (struct scmi_protocol_attrs_out *)msg->out_msg;
+ out->attributes = FIELD_PREP(0xff00, 2) | NUM_PROTOCOLS;
+ out->status = SCMI_SUCCESS;
+
+ return 0;
+}
+
+/**
+ * sandbox_scmi_base_message_attrs - implement
+ * SCMI_BASE_PROTOCOL_MESSAGE_ATTRIBUTES
+ * @dev: SCMI device
+ * @msg: SCMI message
+ *
+ * Implement SCMI_BASE_PROTOCOL_MESSAGE_ATTRIBUTES command.
+ */
+static int sandbox_scmi_base_message_attrs(struct udevice *dev,
+ struct scmi_msg *msg)
+{
+ u32 message_id;
+ struct scmi_protocol_msg_attrs_out *out = NULL;
+
+ if (!msg->in_msg || msg->in_msg_sz < sizeof(message_id) ||
+ !msg->out_msg || msg->out_msg_sz < sizeof(*out))
+ return -EINVAL;
+
+ message_id = *(u32 *)msg->in_msg;
+ out = (struct scmi_protocol_msg_attrs_out *)msg->out_msg;
+
+ if (message_id >= SCMI_PROTOCOL_VERSION &&
+ message_id <= SCMI_BASE_RESET_AGENT_CONFIGURATION &&
+ message_id != SCMI_BASE_NOTIFY_ERRORS) {
+ out->attributes = 0;
+ out->status = SCMI_SUCCESS;
+ } else {
+ out->status = SCMI_NOT_FOUND;
+ }
+
+ return 0;
+}
+
+/**
+ * sandbox_scmi_base_discover_vendor - implement SCMI_BASE_DISCOVER_VENDOR
+ * @dev: SCMI device
+ * @msg: SCMI message
+ *
+ * Implement SCMI_BASE_DISCOVER_VENDOR command
+ */
+static int sandbox_scmi_base_discover_vendor(struct udevice *dev,
+ struct scmi_msg *msg)
+{
+ struct scmi_base_discover_vendor_out *out = NULL;
+
+ if (!msg->out_msg || msg->out_msg_sz < sizeof(*out))
+ return -EINVAL;
+
+ out = (struct scmi_base_discover_vendor_out *)msg->out_msg;
+ strcpy(out->vendor_identifier, SANDBOX_SCMI_VENDOR);
+ out->status = SCMI_SUCCESS;
+
+ return 0;
+}
+
+/**
+ * sandbox_scmi_base_discover_sub_vendor - implement
+ * SCMI_BASE_DISCOVER_SUB_VENDOR
+ * @dev: SCMI device
+ * @msg: SCMI message
+ *
+ * Implement SCMI_BASE_DISCOVER_SUB_VENDOR command
+ */
+static int sandbox_scmi_base_discover_sub_vendor(struct udevice *dev,
+ struct scmi_msg *msg)
+{
+ struct scmi_base_discover_vendor_out *out = NULL;
+
+ if (!msg->out_msg || msg->out_msg_sz < sizeof(*out))
+ return -EINVAL;
+
+ out = (struct scmi_base_discover_vendor_out *)msg->out_msg;
+ strcpy(out->vendor_identifier, SANDBOX_SCMI_SUB_VENDOR);
+ out->status = SCMI_SUCCESS;
+
+ return 0;
+}
+
+/**
+ * sandbox_scmi_base_discover_impl_version - implement
+ * SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION
+ * @dev: SCMI device
+ * @msg: SCMI message
+ *
+ * Implement SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION command
+ */
+static int sandbox_scmi_base_discover_impl_version(struct udevice *dev,
+ struct scmi_msg *msg)
+{
+ struct scmi_base_discover_impl_version_out *out = NULL;
+
+ if (!msg->out_msg || msg->out_msg_sz < sizeof(*out))
+ return -EINVAL;
+
+ out = (struct scmi_base_discover_impl_version_out *)msg->out_msg;
+ out->impl_version = SANDBOX_SCMI_IMPL_VERSION;
+ out->status = SCMI_SUCCESS;
+
+ return 0;
+}
+
+/**
+ * sandbox_scmi_base_discover_list_protocols - implement
+ * SCMI_BASE_DISCOVER_LIST_PROTOCOLS
+ * @dev: SCMI device
+ * @msg: SCMI message
+ *
+ * Implement SCMI_BASE_DISCOVER_LIST_PROTOCOLS command
+ */
+static int sandbox_scmi_base_discover_list_protocols(struct udevice *dev,
+ struct scmi_msg *msg)
+{
+ struct scmi_base_discover_list_protocols_out *out = NULL;
+
+ if (!msg->out_msg || msg->out_msg_sz < sizeof(*out))
+ return -EINVAL;
+
+ out = (struct scmi_base_discover_list_protocols_out *)msg->out_msg;
+ memcpy(out->protocols, protocols, sizeof(protocols));
+ out->num_protocols = NUM_PROTOCOLS;
+ out->status = SCMI_SUCCESS;
+
+ return 0;
+}
+
+/**
+ * sandbox_scmi_base_discover_agent - implement SCMI_BASE_DISCOVER_AGENT
+ * @dev: SCMI device
+ * @msg: SCMI message
+ *
+ * Implement SCMI_BASE_DISCOVER_AGENT command
+ */
+static int sandbox_scmi_base_discover_agent(struct udevice *dev,
+ struct scmi_msg *msg)
+{
+ u32 agent_id;
+ struct scmi_base_discover_agent_out *out = NULL;
+
+ if (!msg->in_msg || msg->in_msg_sz < sizeof(agent_id) ||
+ !msg->out_msg || msg->out_msg_sz < sizeof(*out))
+ return -EINVAL;
+
+ agent_id = *(u32 *)msg->in_msg;
+ out = (struct scmi_base_discover_agent_out *)msg->out_msg;
+ out->status = SCMI_SUCCESS;
+ if (agent_id == 0xffffffff || agent_id == 1) {
+ out->agent_id = 1;
+ strcpy(out->name, SANDBOX_SCMI_AGENT_NAME);
+ } else if (!agent_id) {
+ out->agent_id = agent_id;
+ strcpy(out->name, SANDBOX_SCMI_PLATFORM_NAME);
+ } else {
+ out->status = SCMI_NOT_FOUND;
+ }
+
+ return 0;
+}
+
+/**
+ * sandbox_scmi_base_set_device_permissions - implement
+ * SCMI_BASE_SET_DEVICE_PERMISSIONS
+ * @dev: SCMI device
+ * @msg: SCMI message
+ *
+ * Implement SCMI_BASE_SET_DEVICE_PERMISSIONS command
+ */
+static int sandbox_scmi_base_set_device_permissions(struct udevice *dev,
+ struct scmi_msg *msg)
+{
+ struct scmi_base_set_device_permissions_in *in = NULL;
+ u32 *status;
+
+ if (!msg->in_msg || msg->in_msg_sz < sizeof(*in) ||
+ !msg->out_msg || msg->out_msg_sz < sizeof(*status))
+ return -EINVAL;
+
+ in = (struct scmi_base_set_device_permissions_in *)msg->in_msg;
+ status = (u32 *)msg->out_msg;
+
+ if (in->agent_id != 1 || in->device_id != 0)
+ *status = SCMI_NOT_FOUND;
+ else if (in->flags & ~SCMI_BASE_SET_DEVICE_PERMISSIONS_ACCESS)
+ *status = SCMI_INVALID_PARAMETERS;
+ else if (in->flags & SCMI_BASE_SET_DEVICE_PERMISSIONS_ACCESS)
+ *status = SCMI_SUCCESS;
+ else
+ /* unset not allowed */
+ *status = SCMI_DENIED;
+
+ return 0;
+}
+
+/**
+ * sandbox_scmi_base_set_protocol_permissions - implement
+ * SCMI_BASE_SET_PROTOCOL_PERMISSIONS
+ * @dev: SCMI device
+ * @msg: SCMI message
+ *
+ * Implement SCMI_BASE_SET_PROTOCOL_PERMISSIONS command
+ */
+static int sandbox_scmi_base_set_protocol_permissions(struct udevice *dev,
+ struct scmi_msg *msg)
+{
+ struct scmi_base_set_protocol_permissions_in *in = NULL;
+ u32 *status;
+ int i;
+
+ if (!msg->in_msg || msg->in_msg_sz < sizeof(*in) ||
+ !msg->out_msg || msg->out_msg_sz < sizeof(*status))
+ return -EINVAL;
+
+ in = (struct scmi_base_set_protocol_permissions_in *)msg->in_msg;
+ status = (u32 *)msg->out_msg;
+
+ for (i = 0; i < ARRAY_SIZE(protocols); i++)
+ if (protocols[i] == in->command_id)
+ break;
+ if (in->agent_id != 1 || in->device_id != 0 ||
+ i == ARRAY_SIZE(protocols))
+ *status = SCMI_NOT_FOUND;
+ else if (in->flags & ~SCMI_BASE_SET_PROTOCOL_PERMISSIONS_ACCESS)
+ *status = SCMI_INVALID_PARAMETERS;
+ else if (in->flags & SCMI_BASE_SET_PROTOCOL_PERMISSIONS_ACCESS)
+ *status = SCMI_SUCCESS;
+ else
+ /* unset not allowed */
+ *status = SCMI_DENIED;
+
+ return 0;
+}
+
+/**
+ * sandbox_scmi_base_reset_agent_configuration - implement
+ * SCMI_BASE_RESET_AGENT_CONFIGURATION
+ * @dev: SCMI device
+ * @msg: SCMI message
+ *
+ * Implement SCMI_BASE_RESET_AGENT_CONFIGURATION command
+ */
+static int sandbox_scmi_base_reset_agent_configuration(struct udevice *dev,
+ struct scmi_msg *msg)
+{
+ struct scmi_base_reset_agent_configuration_in *in = NULL;
+ u32 *status;
+
+ if (!msg->in_msg || msg->in_msg_sz < sizeof(*in) ||
+ !msg->out_msg || msg->out_msg_sz < sizeof(*status))
+ return -EINVAL;
+
+ in = (struct scmi_base_reset_agent_configuration_in *)msg->in_msg;
+ status = (u32 *)msg->out_msg;
+
+ if (in->agent_id != 1)
+ *status = SCMI_NOT_FOUND;
+ else if (in->flags & ~SCMI_BASE_RESET_ALL_ACCESS_PERMISSIONS)
+ *status = SCMI_INVALID_PARAMETERS;
+ else
+ *status = SCMI_DENIED;
+
+ return 0;
+}
+
+/* Power Domain Management Protocol */
+
+/**
+ * sandbox_scmi_pwd_protocol_version - implement SCMI_PROTOCOL_VERSION
+ * @dev: SCMI device
+ * @msg: SCMI message
+ *
+ * Implement SCMI_PROTOCOL_VERSION command.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int sandbox_scmi_pwd_protocol_version(struct udevice *dev,
+ struct scmi_msg *msg)
+{
+ struct scmi_protocol_version_out *out = NULL;
+
+ if (!msg->out_msg || msg->out_msg_sz < sizeof(*out))
+ return -EINVAL;
+
+ out = (struct scmi_protocol_version_out *)msg->out_msg;
+ out->version = SANDBOX_SCMI_PWD_PROTOCOL_VERSION;
+ out->status = SCMI_SUCCESS;
+
+ return 0;
+}
+
+/**
+ * sandbox_scmi_pwd_protocol_attribs - implement SCMI_PWD_PROTOCOL_ATTRS
+ * @dev: SCMI device
+ * @msg: SCMI message
+ *
+ * Implement SCMI_PWD_PROTOCOL_ATTRS command.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int sandbox_scmi_pwd_protocol_attribs(struct udevice *dev,
+ struct scmi_msg *msg)
+{
+ struct scmi_pwd_protocol_attrs_out *out;
+
+ if (!msg->out_msg || msg->out_msg_sz < sizeof(*out))
+ return -EINVAL;
+
+ out = (struct scmi_pwd_protocol_attrs_out *)msg->out_msg;
+
+ out->attributes = ARRAY_SIZE(scmi_pwdom);
+ out->stats_addr_low = 0;
+ out->stats_addr_high = 0;
+ out->stats_len = 0;
+ out->status = SCMI_SUCCESS;
+
+ return 0;
+}
+
+/**
+ * sandbox_scmi_pwd_protocol_msg_attribs - implement
+ SCMI_PWD_PROTOCOL_MESSAGE_ATTRS
+ * @dev: SCMI device
+ * @msg: SCMI message
+ *
+ * Implement SCMI_PWD_PROTOCOL_MESSAGE_ATTRS command.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int sandbox_scmi_pwd_protocol_msg_attribs(struct udevice *dev,
+ struct scmi_msg *msg)
+{
+ u32 message_id;
+ struct scmi_pwd_protocol_msg_attrs_out *out;
+
+ if (!msg->in_msg || msg->in_msg_sz < sizeof(message_id) ||
+ !msg->out_msg || msg->out_msg_sz < sizeof(*out))
+ return -EINVAL;
+
+ message_id = *(u32 *)msg->in_msg;
+
+ out = (struct scmi_pwd_protocol_msg_attrs_out *)msg->out_msg;
+ if (message_id <= SCMI_PWD_STATE_GET ||
+ message_id == SCMI_PWD_NAME_GET) {
+ out->attributes = 0;
+ out->status = SCMI_SUCCESS;
+ } else {
+ out->status = SCMI_NOT_FOUND;
+ }
+
+ return 0;
+}
+
+/**
+ * sandbox_scmi_pwd_attribs - implement SCMI_PWD_ATTRS
+ * @dev: SCMI device
+ * @msg: SCMI message
+ *
+ * Implement SCMI_PWD_ATTRS command.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int sandbox_scmi_pwd_attribs(struct udevice *dev, struct scmi_msg *msg)
+{
+ u32 domain_id;
+ struct scmi_pwd_attrs_out *out;
+
+ if (!msg->in_msg || msg->in_msg_sz < sizeof(domain_id) ||
+ !msg->out_msg || msg->out_msg_sz < sizeof(*out))
+ return -EINVAL;
+
+ domain_id = *(u32 *)msg->in_msg;
+ out = (struct scmi_pwd_attrs_out *)msg->out_msg;
+
+ if (domain_id >= ARRAY_SIZE(scmi_pwdom)) {
+ out->status = SCMI_NOT_FOUND;
+
+ return 0;
+ }
+
+ out->attributes =
+ SCMI_PWD_ATTR_PSTATE_SYNC | SCMI_PWD_ATTR_EXTENDED_NAME;
+ /* just 15-char + NULL */
+ snprintf(out->name, SCMI_PWD_NAME_LENGTH_MAX, "power-domain--%d",
+ domain_id);
+ out->status = SCMI_SUCCESS;
+
+ return 0;
+}
+
+/**
+ * sandbox_scmi_pwd_state_set - implement SCMI_PWD_STATE_SET
+ * @dev: SCMI device
+ * @msg: SCMI message
+ *
+ * Implement SCMI_PWD_STATE_SET command.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int sandbox_scmi_pwd_state_set(struct udevice *dev, struct scmi_msg *msg)
+{
+ struct scmi_pwd_state_set_in *in;
+ s32 *status;
+
+ if (!msg->in_msg || msg->in_msg_sz < sizeof(in) ||
+ !msg->out_msg || msg->out_msg_sz < sizeof(*status))
+ return -EINVAL;
+
+ in = (struct scmi_pwd_state_set_in *)msg->in_msg;
+ status = (s32 *)msg->out_msg;
+
+ if (in->domain_id >= ARRAY_SIZE(scmi_pwdom)) {
+ *status = SCMI_NOT_FOUND;
+
+ return 0;
+ }
+
+ if ((in->flags & SCMI_PWD_SET_FLAGS_ASYNC) ||
+ (in->pstate != SCMI_PWD_PSTATE_TYPE_LOST && in->pstate)) {
+ *status = SCMI_INVALID_PARAMETERS;
+
+ return 0;
+ }
+
+ scmi_pwdom[in->domain_id].pstate = in->pstate;
+ *status = SCMI_SUCCESS;
+
+ return 0;
+}
+
+/**
+ * sandbox_scmi_pwd_state_get - implement SCMI_PWD_STATE_GET
+ * @dev: SCMI device
+ * @msg: SCMI message
+ *
+ * Implement SCMI_PWD_STATE_GET command.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int sandbox_scmi_pwd_state_get(struct udevice *dev, struct scmi_msg *msg)
+{
+ u32 domain_id;
+ struct scmi_pwd_state_get_out *out;
+
+ if (!msg->in_msg || msg->in_msg_sz < sizeof(domain_id) ||
+ !msg->out_msg || msg->out_msg_sz < sizeof(*out))
+ return -EINVAL;
+
+ domain_id = *(u32 *)msg->in_msg;
+ out = (struct scmi_pwd_state_get_out *)msg->out_msg;
+
+ if (domain_id >= ARRAY_SIZE(scmi_pwdom)) {
+ out->status = SCMI_NOT_FOUND;
+
+ return 0;
+ }
+
+ out->pstate = scmi_pwdom[domain_id].pstate;
+ out->status = SCMI_SUCCESS;
+
+ return 0;
+}
+
+/**
+ * sandbox_scmi_pwd_name_get - implement SCMI_PWD_NAME_GET
+ * @dev: SCMI device
+ * @msg: SCMI message
+ *
+ * Implement SCMI_PWD_NAME_GET command.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int sandbox_scmi_pwd_name_get(struct udevice *dev, struct scmi_msg *msg)
+{
+ u32 domain_id;
+ struct scmi_pwd_name_get_out *out;
+
+ if (!msg->in_msg || msg->in_msg_sz < sizeof(domain_id) ||
+ !msg->out_msg || msg->out_msg_sz < sizeof(*out))
+ return -EINVAL;
+
+ domain_id = *(u32 *)msg->in_msg;
+ out = (struct scmi_pwd_name_get_out *)msg->out_msg;
+
+ if (domain_id >= ARRAY_SIZE(scmi_pwdom)) {
+ out->status = SCMI_NOT_FOUND;
+
+ return 0;
+ }
+
+ snprintf(out->extended_name, SCMI_PWD_EXTENDED_NAME_MAX,
+ "power-domain--%d-extended", domain_id);
+ out->status = SCMI_SUCCESS;
+
+ return 0;
+}
+
+/* Clock Protocol */
+
static int sandbox_scmi_clock_protocol_attribs(struct udevice *dev,
struct scmi_msg *msg)
{
@@ -470,11 +1057,128 @@
return 0;
}
+/**
+ * sandbox_scmi_of_get_channel - assigne a channel
+ * @dev: SCMI agent device
+ * @protocol: SCMI protocol device
+ * @channel: Pointer to channel info
+ *
+ * Assign a channel for the protocol, @protocol, in @channel,
+ * based on a device tree's property.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int sandbox_scmi_of_get_channel(struct udevice *dev,
+ struct udevice *protocol,
+ struct scmi_channel **channel)
+{
+ struct sandbox_channel *agent_chan = dev_get_plat(dev);
+ struct sandbox_channel *chan;
+ u32 channel_id;
+
+ if (dev_read_u32(protocol, "linaro,sandbox-channel-id", &channel_id)) {
+ /* Uses agent channel */
+ *channel = container_of(agent_chan, struct scmi_channel, ref);
+
+ return 0;
+ }
+
+ /* Setup a dedicated channel */
+ chan = calloc(1, sizeof(*chan));
+ if (!chan)
+ return -ENOMEM;
+
+ chan->channel_id = channel_id;
+
+ *channel = container_of(chan, struct scmi_channel, ref);
+
+ return 0;
+}
+
+/**
+ * sandbox_scmi_of_to_plat - assigne a channel to agent
+ * @dev: SCMI agent device
+ *
+ * Assign a channel for the agent, @protocol.
+ *
+ * Return: always 0
+ */
+static int sandbox_scmi_of_to_plat(struct udevice *dev)
+{
+ struct sandbox_channel *chan = dev_get_plat(dev);
+
+ /* The channel for agent is always 0 */
+ chan->channel_id = 0;
+
+ return 0;
+}
+
+unsigned int sandbox_scmi_channel_id(struct udevice *dev)
+{
+ struct scmi_agent_proto_priv *priv;
+ struct sandbox_channel *chan;
+
+ priv = dev_get_parent_priv(dev);
+ chan = (struct sandbox_channel *)&priv->channel->ref;
+
+ return chan->channel_id;
+}
+
static int sandbox_scmi_test_process_msg(struct udevice *dev,
struct scmi_channel *channel,
struct scmi_msg *msg)
{
switch (msg->protocol_id) {
+ case SCMI_PROTOCOL_ID_BASE:
+ switch (msg->message_id) {
+ case SCMI_PROTOCOL_VERSION:
+ return sandbox_scmi_base_protocol_version(dev, msg);
+ case SCMI_PROTOCOL_ATTRIBUTES:
+ return sandbox_scmi_base_protocol_attrs(dev, msg);
+ case SCMI_PROTOCOL_MESSAGE_ATTRIBUTES:
+ return sandbox_scmi_base_message_attrs(dev, msg);
+ case SCMI_BASE_DISCOVER_VENDOR:
+ return sandbox_scmi_base_discover_vendor(dev, msg);
+ case SCMI_BASE_DISCOVER_SUB_VENDOR:
+ return sandbox_scmi_base_discover_sub_vendor(dev, msg);
+ case SCMI_BASE_DISCOVER_IMPL_VERSION:
+ return sandbox_scmi_base_discover_impl_version(dev, msg);
+ case SCMI_BASE_DISCOVER_LIST_PROTOCOLS:
+ return sandbox_scmi_base_discover_list_protocols(dev, msg);
+ case SCMI_BASE_DISCOVER_AGENT:
+ return sandbox_scmi_base_discover_agent(dev, msg);
+ case SCMI_BASE_NOTIFY_ERRORS:
+ break;
+ case SCMI_BASE_SET_DEVICE_PERMISSIONS:
+ return sandbox_scmi_base_set_device_permissions(dev, msg);
+ case SCMI_BASE_SET_PROTOCOL_PERMISSIONS:
+ return sandbox_scmi_base_set_protocol_permissions(dev, msg);
+ case SCMI_BASE_RESET_AGENT_CONFIGURATION:
+ return sandbox_scmi_base_reset_agent_configuration(dev, msg);
+ default:
+ break;
+ }
+ break;
+ case SCMI_PROTOCOL_ID_POWER_DOMAIN:
+ switch (msg->message_id) {
+ case SCMI_PROTOCOL_VERSION:
+ return sandbox_scmi_pwd_protocol_version(dev, msg);
+ case SCMI_PROTOCOL_ATTRIBUTES:
+ return sandbox_scmi_pwd_protocol_attribs(dev, msg);
+ case SCMI_PROTOCOL_MESSAGE_ATTRIBUTES:
+ return sandbox_scmi_pwd_protocol_msg_attribs(dev, msg);
+ case SCMI_PWD_ATTRIBUTES:
+ return sandbox_scmi_pwd_attribs(dev, msg);
+ case SCMI_PWD_STATE_SET:
+ return sandbox_scmi_pwd_state_set(dev, msg);
+ case SCMI_PWD_STATE_GET:
+ return sandbox_scmi_pwd_state_get(dev, msg);
+ case SCMI_PWD_NAME_GET:
+ return sandbox_scmi_pwd_name_get(dev, msg);
+ default:
+ break;
+ }
+ break;
case SCMI_PROTOCOL_ID_CLOCK:
switch (msg->message_id) {
case SCMI_PROTOCOL_ATTRIBUTES:
@@ -517,8 +1221,6 @@
break;
}
break;
- case SCMI_PROTOCOL_ID_BASE:
- case SCMI_PROTOCOL_ID_POWER_DOMAIN:
case SCMI_PROTOCOL_ID_SYSTEM:
case SCMI_PROTOCOL_ID_PERF:
case SCMI_PROTOCOL_ID_SENSOR:
@@ -541,16 +1243,8 @@
static int sandbox_scmi_test_remove(struct udevice *dev)
{
- struct sandbox_scmi_agent *agent = dev_get_priv(dev);
-
- if (agent != sandbox_scmi_service_ctx()->agent)
- return -EINVAL;
-
debug_print_agent_state(dev, "removed");
- /* We only need to dereference the agent in the context */
- sandbox_scmi_service_ctx()->agent = NULL;
-
return 0;
}
@@ -558,10 +1252,10 @@
{
struct sandbox_scmi_agent *agent = dev_get_priv(dev);
- if (sandbox_scmi_service_ctx()->agent)
- return -EINVAL;
-
*agent = (struct sandbox_scmi_agent){
+ .pwdom_version = SANDBOX_SCMI_PWD_PROTOCOL_VERSION,
+ .pwdom = scmi_pwdom,
+ .pwdom_count = ARRAY_SIZE(scmi_pwdom),
.clk = scmi_clk,
.clk_count = ARRAY_SIZE(scmi_clk),
.reset = scmi_reset,
@@ -572,9 +1266,6 @@
debug_print_agent_state(dev, "probed");
- /* Save reference for tests purpose */
- sandbox_scmi_service_ctx()->agent = agent;
-
return 0;
};
@@ -584,6 +1275,7 @@
};
struct scmi_agent_ops sandbox_scmi_test_ops = {
+ .of_get_channel = sandbox_scmi_of_get_channel,
.process_msg = sandbox_scmi_test_process_msg,
};
@@ -592,6 +1284,8 @@
.id = UCLASS_SCMI_AGENT,
.of_match = sandbox_scmi_test_ids,
.priv_auto = sizeof(struct sandbox_scmi_agent),
+ .plat_auto = sizeof(struct sandbox_channel),
+ .of_to_plat = sandbox_scmi_of_to_plat,
.probe = sandbox_scmi_test_probe,
.remove = sandbox_scmi_test_remove,
.ops = &sandbox_scmi_test_ops,
diff --git a/drivers/firmware/scmi/sandbox-scmi_devices.c b/drivers/firmware/scmi/sandbox-scmi_devices.c
index 9baeb46..facb5b0 100644
--- a/drivers/firmware/scmi/sandbox-scmi_devices.c
+++ b/drivers/firmware/scmi/sandbox-scmi_devices.c
@@ -29,12 +29,14 @@
/*
* struct sandbox_scmi_device_priv - Storage for device handles used by test
+ * @pwdom: Power domain device
* @clk: Array of clock instances used by tests
* @reset_clt: Array of the reset controller instances used by tests
* @regulators: Array of regulator device references used by the tests
* @devices: Resources exposed by sandbox_scmi_devices_ctx()
*/
struct sandbox_scmi_device_priv {
+ struct power_domain pwdom;
struct clk clk[SCMI_TEST_DEVICES_CLK_COUNT];
struct reset_ctl reset_ctl[SCMI_TEST_DEVICES_RD_COUNT];
struct udevice *regulators[SCMI_TEST_DEVICES_VOLTD_COUNT];
@@ -77,6 +79,8 @@
size_t n;
priv->devices = (struct sandbox_scmi_devices){
+ .pwdom = &priv->pwdom,
+ .pwdom_count = 1,
.clk = priv->clk,
.clk_count = SCMI_TEST_DEVICES_CLK_COUNT,
.reset = priv->reset_ctl,
@@ -85,6 +89,12 @@
.regul_count = SCMI_TEST_DEVICES_VOLTD_COUNT,
};
+ ret = power_domain_get_by_index(dev, priv->devices.pwdom, 0);
+ if (ret) {
+ dev_err(dev, "%s: Failed on power domain\n", __func__);
+ return ret;
+ }
+
for (n = 0; n < SCMI_TEST_DEVICES_CLK_COUNT; n++) {
ret = clk_get_by_index(dev, n, priv->devices.clk + n);
if (ret) {
diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c
index 02de692..0f1003e 100644
--- a/drivers/firmware/scmi/scmi_agent-uclass.c
+++ b/drivers/firmware/scmi/scmi_agent-uclass.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <dm.h>
#include <errno.h>
+#include <scmi_agent.h>
#include <scmi_agent-uclass.h>
#include <scmi_protocols.h>
#include <dm/device_compat.h>
@@ -37,6 +38,124 @@
{ .scmi = SCMI_PROTOCOL_ERROR, .errno = -EPROTO, },
};
+/**
+ * scmi_protocol_is_supported - check availability of protocol
+ * @dev: SCMI agent device
+ * @proto_id: Identifier of protocol
+ *
+ * check if the protocol, @proto_id, is provided by the SCMI agent,
+ * @dev.
+ *
+ * Return: 0 on success, error code otherwise
+ */
+static bool scmi_protocol_is_supported(struct udevice *dev,
+ enum scmi_std_protocol proto_id)
+{
+ struct scmi_agent_priv *priv;
+ int i;
+
+ if (proto_id == SCMI_PROTOCOL_ID_BASE)
+ return true;
+
+ priv = dev_get_uclass_plat(dev);
+ if (!priv) {
+ dev_err(dev, "No priv data found\n");
+ return false;
+ }
+
+ for (i = 0; i < priv->num_protocols; i++)
+ if (priv->protocols[i] == proto_id)
+ return true;
+
+ return false;
+}
+
+struct udevice *scmi_get_protocol(struct udevice *dev,
+ enum scmi_std_protocol id)
+{
+ struct scmi_agent_priv *priv;
+ struct udevice *proto;
+
+ priv = dev_get_uclass_plat(dev);
+ if (!priv) {
+ dev_err(dev, "No priv data found\n");
+ return NULL;
+ }
+
+ switch (id) {
+ case SCMI_PROTOCOL_ID_BASE:
+ proto = priv->base_dev;
+ break;
+ case SCMI_PROTOCOL_ID_POWER_DOMAIN:
+ proto = priv->pwdom_dev;
+ break;
+ case SCMI_PROTOCOL_ID_CLOCK:
+ proto = priv->clock_dev;
+ break;
+ case SCMI_PROTOCOL_ID_RESET_DOMAIN:
+ proto = priv->resetdom_dev;
+ break;
+ case SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN:
+ proto = priv->voltagedom_dev;
+ break;
+ default:
+ dev_err(dev, "Protocol not supported\n");
+ proto = NULL;
+ break;
+ }
+ if (proto && device_probe(proto))
+ dev_err(dev, "Probe failed\n");
+
+ return proto;
+}
+
+/**
+ * scmi_add_protocol - add protocol to agent
+ * @dev: SCMI agent device
+ * @proto_id: SCMI protocol ID
+ * @proto: SCMI protocol device
+ *
+ * Associate the protocol instance, @proto, to the agent, @dev,
+ * for later use.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int scmi_add_protocol(struct udevice *dev,
+ enum scmi_std_protocol proto_id,
+ struct udevice *proto)
+{
+ struct scmi_agent_priv *priv;
+
+ priv = dev_get_uclass_plat(dev);
+ if (!priv) {
+ dev_err(dev, "No priv data found\n");
+ return -ENODEV;
+ }
+
+ switch (proto_id) {
+ case SCMI_PROTOCOL_ID_BASE:
+ priv->base_dev = proto;
+ break;
+ case SCMI_PROTOCOL_ID_POWER_DOMAIN:
+ priv->pwdom_dev = proto;
+ break;
+ case SCMI_PROTOCOL_ID_CLOCK:
+ priv->clock_dev = proto;
+ break;
+ case SCMI_PROTOCOL_ID_RESET_DOMAIN:
+ priv->resetdom_dev = proto;
+ break;
+ case SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN:
+ priv->voltagedom_dev = proto;
+ break;
+ default:
+ dev_err(dev, "Protocol not supported\n");
+ return -EPROTO;
+ }
+
+ return 0;
+}
+
int scmi_to_linux_errno(s32 scmi_code)
{
int n;
@@ -51,8 +170,191 @@
return -EPROTO;
}
+static struct udevice *find_scmi_protocol_device(struct udevice *dev)
+{
+ struct udevice *parent = NULL, *protocol;
+
+ for (protocol = dev; protocol; protocol = parent) {
+ parent = dev_get_parent(protocol);
+ if (!parent ||
+ device_get_uclass_id(parent) == UCLASS_SCMI_AGENT)
+ break;
+ }
+
+ if (!parent) {
+ dev_err(dev, "Invalid SCMI device, agent not found\n");
+ return NULL;
+ }
+
+ return protocol;
+}
+
+static const struct scmi_agent_ops *transport_dev_ops(struct udevice *dev)
+{
+ return (const struct scmi_agent_ops *)dev->driver->ops;
+}
+
+/**
+ * scmi_of_get_channel() - Get SCMI channel handle
+ *
+ * @dev: SCMI agent device
+ * @channel: Output reference to the SCMI channel upon success
+ *
+ * On return, @channel will be set.
+ * Return 0 on success and a negative errno on failure
+ */
+static int scmi_of_get_channel(struct udevice *dev, struct udevice *protocol,
+ struct scmi_channel **channel)
+{
+ const struct scmi_agent_ops *ops;
+
+ ops = transport_dev_ops(dev);
+ if (ops->of_get_channel)
+ return ops->of_get_channel(dev, protocol, channel);
+ else
+ return -EPROTONOSUPPORT;
+}
+
+int devm_scmi_of_get_channel(struct udevice *dev)
+{
+ struct udevice *protocol;
+ struct scmi_agent_proto_priv *priv;
+ int ret;
+
+ protocol = find_scmi_protocol_device(dev);
+ if (!protocol)
+ return -ENODEV;
+
+ priv = dev_get_parent_priv(protocol);
+ ret = scmi_of_get_channel(protocol->parent, protocol, &priv->channel);
+ if (ret == -EPROTONOSUPPORT) {
+ /* Drivers without a get_channel operator don't need a channel ref */
+ priv->channel = NULL;
+
+ return 0;
+ }
+
+ return ret;
+}
+
+/**
+ * scmi_process_msg() - Send and process an SCMI message
+ *
+ * Send a message to an SCMI server.
+ * Caller sets scmi_msg::out_msg_sz to the output message buffer size.
+ *
+ * @dev: SCMI agent device
+ * @channel: Communication channel for the device
+ * @msg: Message structure reference
+ *
+ * On return, scmi_msg::out_msg_sz stores the response payload size.
+ * Return: 0 on success and a negative errno on failure
+ */
+static int scmi_process_msg(struct udevice *dev, struct scmi_channel *channel,
+ struct scmi_msg *msg)
+{
+ const struct scmi_agent_ops *ops;
+
+ ops = transport_dev_ops(dev);
+ if (ops->process_msg)
+ return ops->process_msg(dev, channel, msg);
+ else
+ return -EPROTONOSUPPORT;
+}
+
+int devm_scmi_process_msg(struct udevice *dev, struct scmi_msg *msg)
+{
+ struct udevice *protocol;
+ struct scmi_agent_proto_priv *priv;
+
+ protocol = find_scmi_protocol_device(dev);
+ if (!protocol)
+ return -ENODEV;
+
+ priv = dev_get_parent_priv(protocol);
+
+ return scmi_process_msg(protocol->parent, priv->channel, msg);
+}
+
+/**
+ * scmi_fill_base_info - get base information about SCMI server
+ * @agent: SCMI agent device
+ * @dev: SCMI protocol device
+ *
+ * By using Base protocol commands, collect the base information
+ * about SCMI server.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int scmi_fill_base_info(struct udevice *agent, struct udevice *dev)
+{
+ struct scmi_agent_priv *priv = dev_get_uclass_plat(agent);
+ int ret;
+
+ ret = scmi_base_protocol_version(dev, &priv->version);
+ if (ret) {
+ dev_err(dev, "protocol_version() failed (%d)\n", ret);
+ return ret;
+ }
+ /* check for required version */
+ if (priv->version < SCMI_BASE_PROTOCOL_VERSION) {
+ dev_err(dev, "base protocol version (%d) lower than expected\n",
+ priv->version);
+ return -EPROTO;
+ }
+
+ ret = scmi_base_protocol_attrs(dev, &priv->num_agents,
+ &priv->num_protocols);
+ if (ret) {
+ dev_err(dev, "protocol_attrs() failed (%d)\n", ret);
+ return ret;
+ }
+ ret = scmi_base_discover_vendor(dev, &priv->vendor);
+ if (ret) {
+ dev_err(dev, "base_discover_vendor() failed (%d)\n", ret);
+ return ret;
+ }
+ ret = scmi_base_discover_sub_vendor(dev, &priv->sub_vendor);
+ if (ret) {
+ if (ret != -EOPNOTSUPP) {
+ dev_err(dev, "base_discover_sub_vendor() failed (%d)\n",
+ ret);
+ return ret;
+ }
+ priv->sub_vendor = "NA";
+ }
+ ret = scmi_base_discover_impl_version(dev, &priv->impl_version);
+ if (ret) {
+ dev_err(dev, "base_discover_impl_version() failed (%d)\n",
+ ret);
+ return ret;
+ }
+
+ ret = scmi_base_discover_agent(dev, 0xffffffff,
+ &priv->agent_id, &priv->agent_name);
+ if (ret) {
+ if (ret != -EOPNOTSUPP) {
+ dev_err(dev,
+ "base_discover_agent() failed for myself (%d)\n",
+ ret);
+ return ret;
+ }
+ priv->agent_id = 0xffffffff;
+ priv->agent_name = "NA";
+ }
+
+ ret = scmi_base_discover_list_protocols(dev, &priv->protocols);
+ if (ret != priv->num_protocols) {
+ dev_err(dev, "base_discover_list_protocols() failed (%d)\n",
+ ret);
+ return -EPROTO;
+ }
+
+ return 0;
+}
+
/*
- * SCMI agent devices binds devices of various uclasses depeding on
+ * SCMI agent devices binds devices of various uclasses depending on
* the FDT description. scmi_bind_protocol() is a generic bind sequence
* called by the uclass at bind stage, that is uclass post_bind.
*/
@@ -61,9 +363,43 @@
int ret = 0;
ofnode node;
const char *name;
+ struct driver *drv;
+ struct udevice *agent, *proto;
+
+ if (!uclass_get_device(UCLASS_SCMI_AGENT, 1, &agent)) {
+ /* This is a second SCMI agent */
+ dev_err(dev, "Cannot have more than one SCMI agent\n");
+ return -EEXIST;
+ }
+
+ /* initialize the device from device tree */
+ drv = DM_DRIVER_GET(scmi_base_drv);
+ name = "scmi-base.0";
+ ret = device_bind(dev, drv, name, NULL, ofnode_null(), &proto);
+ if (ret) {
+ dev_err(dev, "failed to bind base protocol\n");
+ return ret;
+ }
+ ret = scmi_add_protocol(dev, SCMI_PROTOCOL_ID_BASE, proto);
+ if (ret) {
+ dev_err(dev, "failed to add protocol: %s, ret: %d\n",
+ proto->name, ret);
+ return ret;
+ }
+
+ ret = device_probe(proto);
+ if (ret) {
+ dev_err(dev, "failed to probe base protocol\n");
+ return ret;
+ }
+
+ ret = scmi_fill_base_info(dev, proto);
+ if (ret) {
+ dev_err(dev, "failed to get base information\n");
+ return ret;
+ }
dev_for_each_subnode(node, dev) {
- struct driver *drv = NULL;
u32 protocol_id;
if (!ofnode_is_enabled(node))
@@ -72,18 +408,27 @@
if (ofnode_read_u32(node, "reg", &protocol_id))
continue;
+ drv = NULL;
name = ofnode_get_name(node);
switch (protocol_id) {
+ case SCMI_PROTOCOL_ID_POWER_DOMAIN:
+ if (CONFIG_IS_ENABLED(SCMI_POWER_DOMAIN) &&
+ scmi_protocol_is_supported(dev, protocol_id))
+ drv = DM_DRIVER_GET(scmi_power_domain);
+ break;
case SCMI_PROTOCOL_ID_CLOCK:
- if (CONFIG_IS_ENABLED(CLK_SCMI))
+ if (CONFIG_IS_ENABLED(CLK_SCMI) &&
+ scmi_protocol_is_supported(dev, protocol_id))
drv = DM_DRIVER_GET(scmi_clock);
break;
case SCMI_PROTOCOL_ID_RESET_DOMAIN:
- if (IS_ENABLED(CONFIG_RESET_SCMI))
+ if (IS_ENABLED(CONFIG_RESET_SCMI) &&
+ scmi_protocol_is_supported(dev, protocol_id))
drv = DM_DRIVER_GET(scmi_reset_domain);
break;
case SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN:
- if (IS_ENABLED(CONFIG_DM_REGULATOR_SCMI)) {
+ if (IS_ENABLED(CONFIG_DM_REGULATOR_SCMI) &&
+ scmi_protocol_is_supported(dev, protocol_id)) {
node = ofnode_find_subnode(node, "regulators");
if (!ofnode_valid(node)) {
dev_err(dev, "no regulators node\n");
@@ -102,70 +447,26 @@
continue;
}
- ret = device_bind(dev, drv, name, NULL, node, NULL);
- if (ret)
+ ret = device_bind(dev, drv, name, NULL, node, &proto);
+ if (ret) {
+ dev_err(dev, "failed to bind %s protocol\n", drv->name);
break;
+ }
+ ret = scmi_add_protocol(dev, protocol_id, proto);
+ if (ret) {
+ dev_err(dev, "failed to add protocol: %s, ret: %d\n",
+ proto->name, ret);
+ break;
+ }
}
return ret;
}
-static struct udevice *find_scmi_transport_device(struct udevice *dev)
-{
- struct udevice *parent = dev;
-
- do {
- parent = dev_get_parent(parent);
- } while (parent && device_get_uclass_id(parent) != UCLASS_SCMI_AGENT);
-
- if (!parent)
- dev_err(dev, "Invalid SCMI device, agent not found\n");
-
- return parent;
-}
-
-static const struct scmi_agent_ops *transport_dev_ops(struct udevice *dev)
-{
- return (const struct scmi_agent_ops *)dev->driver->ops;
-}
-
-int devm_scmi_of_get_channel(struct udevice *dev, struct scmi_channel **channel)
-{
- struct udevice *parent;
-
- parent = find_scmi_transport_device(dev);
- if (!parent)
- return -ENODEV;
-
- if (transport_dev_ops(parent)->of_get_channel)
- return transport_dev_ops(parent)->of_get_channel(parent, channel);
-
- /* Drivers without a get_channel operator don't need a channel ref */
- *channel = NULL;
-
- return 0;
-}
-
-int devm_scmi_process_msg(struct udevice *dev, struct scmi_channel *channel,
- struct scmi_msg *msg)
-{
- const struct scmi_agent_ops *ops;
- struct udevice *parent;
-
- parent = find_scmi_transport_device(dev);
- if (!parent)
- return -ENODEV;
-
- ops = transport_dev_ops(parent);
-
- if (ops->process_msg)
- return ops->process_msg(parent, channel, msg);
-
- return -EPROTONOSUPPORT;
-}
-
UCLASS_DRIVER(scmi_agent) = {
.id = UCLASS_SCMI_AGENT,
.name = "scmi_agent",
.post_bind = scmi_bind_protocols,
+ .per_device_plat_auto = sizeof(struct scmi_agent_priv),
+ .per_child_auto = sizeof(struct scmi_agent_proto_priv),
};
diff --git a/drivers/firmware/scmi/smccc_agent.c b/drivers/firmware/scmi/smccc_agent.c
index 6a52cd7..972c6ad 100644
--- a/drivers/firmware/scmi/smccc_agent.c
+++ b/drivers/firmware/scmi/smccc_agent.c
@@ -81,6 +81,7 @@
}
static int scmi_smccc_get_channel(struct udevice *dev,
+ struct udevice *protocol,
struct scmi_channel **channel)
{
struct scmi_smccc_channel *base_chan = dev_get_plat(dev);
@@ -88,7 +89,7 @@
u32 func_id;
int ret;
- if (dev_read_u32(dev, "arm,smc-id", &func_id)) {
+ if (dev_read_u32(protocol, "arm,smc-id", &func_id)) {
/* Uses agent base channel */
*channel = container_of(base_chan, struct scmi_channel, ref);
@@ -100,7 +101,7 @@
if (!chan)
return -ENOMEM;
- ret = setup_channel(dev, chan);
+ ret = setup_channel(protocol, chan);
if (ret) {
free(chan);
return ret;
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index 72f572d..6e9f93e 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -3,7 +3,7 @@
* Texas Instruments System Control Interface Protocol Driver
* Based on drivers/firmware/ti_sci.c from Linux.
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
@@ -2690,6 +2690,8 @@
const
struct ti_sci_handle *ti_sci_get_handle_from_sysfw(struct udevice *sci_dev)
{
+ int ret;
+
if (!sci_dev)
return ERR_PTR(-EINVAL);
@@ -2703,6 +2705,11 @@
if (!handle)
return ERR_PTR(-EINVAL);
+ ret = ti_sci_cmd_get_revision(handle);
+
+ if (ret)
+ return ERR_PTR(-EINVAL);
+
return handle;
}
@@ -2825,11 +2832,9 @@
list_add_tail(&info->list, &ti_sci_list);
ti_sci_setup_ops(info);
- ret = ti_sci_cmd_get_revision(&info->handle);
-
INIT_LIST_HEAD(&info->dev_list);
- return ret;
+ return 0;
}
/**
diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h
index 101210e..bb8bc7b 100644
--- a/drivers/firmware/ti_sci.h
+++ b/drivers/firmware/ti_sci.h
@@ -6,7 +6,7 @@
* The system works in a message response protocol
* See: http://processors.wiki.ti.com/index.php/TISCI for details
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Based on drivers/firmware/ti_sci.h from Linux.
*
*/
diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h
index 1a461fa..567ce89 100644
--- a/drivers/firmware/ti_sci_static_data.h
+++ b/drivers/firmware/ti_sci_static_data.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/*
- * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*
*/
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index b1f201f..2656f5f 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -2,7 +2,7 @@
/*
* (C) Copyright 2015 - 2016, Xilinx, Inc,
* Michal Simek <michal.simek@amd.com>
- * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
*/
#include <console.h>
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 9bf6e42..ba42b07 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -372,6 +372,13 @@
help
Support the GPIO device in Allwinner SoCs.
+config SUNXI_NEW_PINCTRL
+ bool
+ depends on SUNXI_GPIO
+ ---help---
+ The Allwinner D1 and other new SoCs use a different register map
+ for the GPIO block, which we need to know about in the SPL.
+
config XILINX_GPIO
bool "Xilinx GPIO driver"
depends on DM_GPIO
@@ -659,4 +666,11 @@
help
Support ADP5585 GPIO expander.
+config RZG2L_GPIO
+ bool "Renesas RZ/G2L family GPIO driver"
+ depends on DM_GPIO && PINCTRL_RZG2L
+ help
+ Support the gpio functionality of the pin function controller (PFC)
+ on the Renesas RZ/G2L SoC family.
+
endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 64a36c4..c8b3fd7 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -74,3 +74,4 @@
obj-$(CONFIG_$(SPL_TPL_)TURRIS_OMNIA_MCU) += turris_omnia_mcu.o
obj-$(CONFIG_FTGPIO010) += ftgpio010.o
obj-$(CONFIG_ADP5585_GPIO) += adp5585_gpio.o
+obj-$(CONFIG_RZG2L_GPIO) += rzg2l-gpio.o
diff --git a/drivers/gpio/axp_gpio.c b/drivers/gpio/axp_gpio.c
index 4967219..af66316 100644
--- a/drivers/gpio/axp_gpio.c
+++ b/drivers/gpio/axp_gpio.c
@@ -14,6 +14,7 @@
#include <dm/lists.h>
#include <dm/root.h>
#include <errno.h>
+#include <sunxi_gpio.h>
static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val);
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index 31027f3..7aece85 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -28,6 +28,8 @@
DECLARE_GLOBAL_DATA_PTR;
+#define GPIO_ALLOC_BITS 32
+
/**
* gpio_desc_init() - Initialize the GPIO descriptor
*
@@ -75,6 +77,46 @@
return -ENOENT;
}
+/**
+ * gpio_is_claimed() - Test whether GPIO is claimed by consumer
+ *
+ * Test whether GPIO is claimed by consumer already.
+ *
+ * @uc_priv: gpio_dev_priv pointer.
+ * @offset: gpio offset within the device
+ * @return: true if claimed, false if not claimed
+ */
+static bool gpio_is_claimed(struct gpio_dev_priv *uc_priv, unsigned int offset)
+{
+ return !!(uc_priv->claimed[offset / GPIO_ALLOC_BITS] & BIT(offset % GPIO_ALLOC_BITS));
+}
+
+/**
+ * gpio_set_claim() - Set GPIO claimed by consumer
+ *
+ * Set a bit which indicate the GPIO is claimed by consumer
+ *
+ * @uc_priv: gpio_dev_priv pointer.
+ * @offset: gpio offset within the device
+ */
+static void gpio_set_claim(struct gpio_dev_priv *uc_priv, unsigned int offset)
+{
+ uc_priv->claimed[offset / GPIO_ALLOC_BITS] |= BIT(offset % GPIO_ALLOC_BITS);
+}
+
+/**
+ * gpio_clear_claim() - Clear GPIO claimed by consumer
+ *
+ * Clear a bit which indicate the GPIO is claimed by consumer
+ *
+ * @uc_priv: gpio_dev_priv pointer.
+ * @offset: gpio offset within the device
+ */
+static void gpio_clear_claim(struct gpio_dev_priv *uc_priv, unsigned int offset)
+{
+ uc_priv->claimed[offset / GPIO_ALLOC_BITS] &= ~BIT(offset % GPIO_ALLOC_BITS);
+}
+
#if CONFIG_IS_ENABLED(DM_GPIO_LOOKUP_LABEL)
/**
* dm_gpio_lookup_label() - look for name in gpio device
@@ -94,7 +136,7 @@
*offset = -1;
for (i = 0; i < uc_priv->gpio_count; i++) {
- if (!uc_priv->name[i])
+ if (!gpio_is_claimed(uc_priv, i))
continue;
if (!strcmp(name, uc_priv->name[i])) {
*offset = i;
@@ -350,7 +392,7 @@
int ret;
uc_priv = dev_get_uclass_priv(dev);
- if (uc_priv->name[desc->offset])
+ if (gpio_is_claimed(uc_priv, desc->offset))
return -EBUSY;
str = strdup(label);
if (!str)
@@ -362,6 +404,8 @@
return ret;
}
}
+
+ gpio_set_claim(uc_priv, desc->offset);
uc_priv->name[desc->offset] = str;
return 0;
@@ -438,7 +482,7 @@
int ret;
uc_priv = dev_get_uclass_priv(dev);
- if (!uc_priv->name[offset])
+ if (!gpio_is_claimed(uc_priv, offset))
return -ENXIO;
if (ops->rfree) {
ret = ops->rfree(dev, offset);
@@ -446,6 +490,7 @@
return ret;
}
+ gpio_clear_claim(uc_priv, offset);
free(uc_priv->name[offset]);
uc_priv->name[offset] = NULL;
@@ -480,7 +525,7 @@
return -ENOENT;
uc_priv = dev_get_uclass_priv(desc->dev);
- if (!uc_priv->name[desc->offset]) {
+ if (!gpio_is_claimed(uc_priv, desc->offset)) {
printf("%s: %s: error: gpio %s%d not reserved\n",
desc->dev->name, func,
uc_priv->bank_name ? uc_priv->bank_name : "",
@@ -826,7 +871,7 @@
return -EINVAL;
if (namep)
*namep = uc_priv->name[offset];
- if (skip_unused && !uc_priv->name[offset])
+ if (skip_unused && !gpio_is_claimed(uc_priv, offset))
return GPIOF_UNUSED;
if (ops->get_function) {
int ret;
@@ -1341,6 +1386,14 @@
if (!uc_priv->name)
return -ENOMEM;
+ uc_priv->claimed = calloc(DIV_ROUND_UP(uc_priv->gpio_count,
+ GPIO_ALLOC_BITS),
+ GPIO_ALLOC_BITS / 8);
+ if (!uc_priv->claimed) {
+ free(uc_priv->name);
+ return -ENOMEM;
+ }
+
return gpio_renumber(NULL);
}
@@ -1353,6 +1406,7 @@
if (uc_priv->name[i])
free(uc_priv->name[i]);
}
+ free(uc_priv->claimed);
free(uc_priv->name);
return gpio_renumber(dev);
@@ -1444,36 +1498,6 @@
static int gpio_post_bind(struct udevice *dev)
{
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- struct dm_gpio_ops *ops = (struct dm_gpio_ops *)device_get_ops(dev);
- static int reloc_done;
-
- if (!reloc_done) {
- if (ops->request)
- ops->request += gd->reloc_off;
- if (ops->rfree)
- ops->rfree += gd->reloc_off;
- if (ops->direction_input)
- ops->direction_input += gd->reloc_off;
- if (ops->direction_output)
- ops->direction_output += gd->reloc_off;
- if (ops->get_value)
- ops->get_value += gd->reloc_off;
- if (ops->set_value)
- ops->set_value += gd->reloc_off;
- if (ops->get_function)
- ops->get_function += gd->reloc_off;
- if (ops->xlate)
- ops->xlate += gd->reloc_off;
- if (ops->set_flags)
- ops->set_flags += gd->reloc_off;
- if (ops->get_flags)
- ops->get_flags += gd->reloc_off;
-
- reloc_done++;
- }
-#endif
-
if (CONFIG_IS_ENABLED(GPIO_HOG) && dev_has_ofnode(dev)) {
struct udevice *child;
ofnode node;
diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c
index 4654f9e..b0c66d1 100644
--- a/drivers/gpio/pca953x_gpio.c
+++ b/drivers/gpio/pca953x_gpio.c
@@ -407,6 +407,7 @@
{ .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
{ .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
{ .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), },
+ { .compatible = "ti,tca9554", .data = OF_953X(8, PCA_INT), },
{ .compatible = "onsemi,pca9654", .data = OF_953X(8, PCA_INT), },
diff --git a/drivers/gpio/pcf8575_gpio.c b/drivers/gpio/pcf8575_gpio.c
index d5930d9..f38e215 100644
--- a/drivers/gpio/pcf8575_gpio.c
+++ b/drivers/gpio/pcf8575_gpio.c
@@ -2,7 +2,7 @@
/*
* PCF8575 I2C GPIO EXPANDER DRIVER
*
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
*
* Vignesh R <vigneshr@ti.com>
*
diff --git a/drivers/gpio/rzg2l-gpio.c b/drivers/gpio/rzg2l-gpio.c
new file mode 100644
index 0000000..2477af7
--- /dev/null
+++ b/drivers/gpio/rzg2l-gpio.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/G2L Pin Function Controller
+ *
+ * Copyright (C) 2021-2023 Renesas Electronics Corp.
+ */
+
+#include <asm-generic/gpio.h>
+#include <asm/io.h>
+#include <dm/device.h>
+#include <dm/device_compat.h>
+#include <renesas/rzg2l-pfc.h>
+
+static void rzg2l_gpio_set(const struct rzg2l_pfc_data *data, u32 port, u8 pin,
+ bool value)
+{
+ if (value)
+ setbits_8(data->base + P(port), BIT(pin));
+ else
+ clrbits_8(data->base + P(port), BIT(pin));
+}
+
+static int rzg2l_gpio_get_value(struct udevice *dev, unsigned int offset)
+{
+ const struct rzg2l_pfc_data *data =
+ (const struct rzg2l_pfc_data *)dev_get_driver_data(dev);
+ const u32 port = RZG2L_PINMUX_TO_PORT(offset);
+ const u8 pin = RZG2L_PINMUX_TO_PIN(offset);
+ u16 pm_state;
+
+ pm_state = (readw(data->base + PM(port)) >> (pin * 2)) & PM_MASK;
+ switch (pm_state) {
+ case PM_INPUT:
+ return !!(readb(data->base + PIN(port)) & BIT(pin));
+ case PM_OUTPUT:
+ case PM_OUTPUT_IEN:
+ return !!(readb(data->base + P(port)) & BIT(pin));
+ default: /* PM_HIGH_Z */
+ return 0;
+ }
+}
+
+static int rzg2l_gpio_set_value(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ const struct rzg2l_pfc_data *data =
+ (const struct rzg2l_pfc_data *)dev_get_driver_data(dev);
+ const u32 port = RZG2L_PINMUX_TO_PORT(offset);
+ const u8 pin = RZG2L_PINMUX_TO_PIN(offset);
+
+ rzg2l_gpio_set(data, port, pin, (bool)value);
+ return 0;
+}
+
+static void rzg2l_gpio_set_direction(const struct rzg2l_pfc_data *data,
+ u32 port, u8 pin, bool output)
+{
+ clrsetbits_le16(data->base + PM(port), PM_MASK << (pin * 2),
+ (output ? PM_OUTPUT : PM_INPUT) << (pin * 2));
+}
+
+static int rzg2l_gpio_direction_input(struct udevice *dev, unsigned int offset)
+{
+ const struct rzg2l_pfc_data *data =
+ (const struct rzg2l_pfc_data *)dev_get_driver_data(dev);
+ const u32 port = RZG2L_PINMUX_TO_PORT(offset);
+ const u8 pin = RZG2L_PINMUX_TO_PIN(offset);
+
+ rzg2l_gpio_set_direction(data, port, pin, false);
+ return 0;
+}
+
+static int rzg2l_gpio_direction_output(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ const struct rzg2l_pfc_data *data =
+ (const struct rzg2l_pfc_data *)dev_get_driver_data(dev);
+ const u32 port = RZG2L_PINMUX_TO_PORT(offset);
+ const u8 pin = RZG2L_PINMUX_TO_PIN(offset);
+
+ rzg2l_gpio_set(data, port, pin, (bool)value);
+ rzg2l_gpio_set_direction(data, port, pin, true);
+ return 0;
+}
+
+static int rzg2l_gpio_request(struct udevice *dev, unsigned int offset,
+ const char *label)
+{
+ const struct rzg2l_pfc_data *data =
+ (const struct rzg2l_pfc_data *)dev_get_driver_data(dev);
+ const u32 port = RZG2L_PINMUX_TO_PORT(offset);
+ const u8 pin = RZG2L_PINMUX_TO_PIN(offset);
+
+ if (!rzg2l_port_validate(data, port, pin)) {
+ dev_err(dev, "Invalid GPIO %u:%u\n", port, pin);
+ return -EINVAL;
+ }
+
+ /* Select GPIO mode in PMC Register */
+ clrbits_8(data->base + PMC(port), BIT(pin));
+
+ return 0;
+}
+
+static int rzg2l_gpio_get_function(struct udevice *dev, unsigned int offset)
+{
+ const struct rzg2l_pfc_data *data =
+ (const struct rzg2l_pfc_data *)dev_get_driver_data(dev);
+ const u32 port = RZG2L_PINMUX_TO_PORT(offset);
+ const u8 pin = RZG2L_PINMUX_TO_PIN(offset);
+ u16 pm_state;
+ u8 pmc_state;
+
+ if (!rzg2l_port_validate(data, port, pin)) {
+ /* This offset does not correspond to a valid GPIO pin. */
+ return -ENOENT;
+ }
+
+ /* Check if the pin is in GPIO or function mode. */
+ pmc_state = readb(data->base + PMC(port)) & BIT(pin);
+ if (pmc_state)
+ return GPIOF_FUNC;
+
+ /* Check the pin direction. */
+ pm_state = (readw(data->base + PM(port)) >> (pin * 2)) & PM_MASK;
+ switch (pm_state) {
+ case PM_INPUT:
+ return GPIOF_INPUT;
+ case PM_OUTPUT:
+ case PM_OUTPUT_IEN:
+ return GPIOF_OUTPUT;
+ default: /* PM_HIGH_Z */
+ return GPIOF_UNUSED;
+ }
+}
+
+static const struct dm_gpio_ops rzg2l_gpio_ops = {
+ .direction_input = rzg2l_gpio_direction_input,
+ .direction_output = rzg2l_gpio_direction_output,
+ .get_value = rzg2l_gpio_get_value,
+ .set_value = rzg2l_gpio_set_value,
+ .request = rzg2l_gpio_request,
+ .get_function = rzg2l_gpio_get_function,
+};
+
+static int rzg2l_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct ofnode_phandle_args args;
+ int ret;
+
+ uc_priv->bank_name = "rzg2l-pfc-gpio";
+ ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "gpio-ranges",
+ NULL, 3, 0, &args);
+ if (ret < 0) {
+ dev_err(dev, "Failed to parse gpio-ranges: %d\n", ret);
+ return -EINVAL;
+ }
+
+ uc_priv->gpio_count = args.args[2];
+ return rzg2l_pfc_enable(dev);
+}
+
+U_BOOT_DRIVER(rzg2l_pfc_gpio) = {
+ .name = "rzg2l-pfc-gpio",
+ .id = UCLASS_GPIO,
+ .ops = &rzg2l_gpio_ops,
+ .probe = rzg2l_gpio_probe,
+};
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index f0b42e4..e4463a2 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -17,37 +17,165 @@
#include <asm/io.h>
#include <asm/gpio.h>
#include <dt-bindings/gpio/gpio.h>
+#include <sunxi_gpio.h>
-#if !CONFIG_IS_ENABLED(DM_GPIO)
-static int sunxi_gpio_output(u32 pin, u32 val)
+/*
+ * =======================================================================
+ * Low level GPIO/pin controller access functions, to be shared by non-DM
+ * SPL code and the DM pinctrl/GPIO drivers.
+ * The functions ending in "bank" take a base pointer to a GPIO bank, and
+ * the pin offset is relative to that bank.
+ * The functions without "bank" in their name take a linear GPIO number,
+ * covering all ports, and starting at 0 for PortA.
+ * =======================================================================
+ */
+
+#define GPIO_BANK(pin) ((pin) >> 5)
+#define GPIO_NUM(pin) ((pin) & 0x1f)
+
+#define GPIO_CFG_REG_OFFSET 0x00
+#define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3)
+#define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1f) & 0x7) << 2)
+
+#define GPIO_DAT_REG_OFFSET 0x10
+
+#define GPIO_DRV_REG_OFFSET 0x14
+
+/* Newer SoCs use a slightly different register layout */
+#ifdef CONFIG_SUNXI_NEW_PINCTRL
+/* pin drive strength: 4 bits per pin */
+#define GPIO_DRV_INDEX(pin) ((pin) / 8)
+#define GPIO_DRV_OFFSET(pin) (((pin) % 8) * 4)
+
+#define GPIO_PULL_REG_OFFSET 0x24
+
+#else /* older generation pin controllers */
+/* pin drive strength: 2 bits per pin */
+#define GPIO_DRV_INDEX(pin) ((pin) / 16)
+#define GPIO_DRV_OFFSET(pin) (((pin) % 16) * 2)
+
+#define GPIO_PULL_REG_OFFSET 0x1c
+#endif
+
+#define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4)
+#define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1)
+
+static void* BANK_TO_GPIO(int bank)
{
- u32 dat;
- u32 bank = GPIO_BANK(pin);
- u32 num = GPIO_NUM(pin);
- struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+ void *pio_base;
- dat = readl(&pio->dat);
- if (val)
- dat |= 0x1 << num;
- else
- dat &= ~(0x1 << num);
+ if (bank < SUNXI_GPIO_L) {
+ pio_base = (void *)(uintptr_t)SUNXI_PIO_BASE;
+ } else {
+ pio_base = (void *)(uintptr_t)SUNXI_R_PIO_BASE;
+ bank -= SUNXI_GPIO_L;
+ }
- writel(dat, &pio->dat);
-
- return 0;
+ return pio_base + bank * SUNXI_PINCTRL_BANK_SIZE;
}
-static int sunxi_gpio_input(u32 pin)
+void sunxi_gpio_set_cfgbank(void *bank_base, int pin_offset, u32 val)
{
- u32 dat;
+ u32 index = GPIO_CFG_INDEX(pin_offset);
+ u32 offset = GPIO_CFG_OFFSET(pin_offset);
+
+ clrsetbits_le32(bank_base + GPIO_CFG_REG_OFFSET + index * 4,
+ 0xfU << offset, val << offset);
+}
+
+void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
+{
u32 bank = GPIO_BANK(pin);
- u32 num = GPIO_NUM(pin);
- struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+ void *pio = BANK_TO_GPIO(bank);
- dat = readl(&pio->dat);
- dat >>= num;
+ sunxi_gpio_set_cfgbank(pio, GPIO_NUM(pin), val);
+}
- return dat & 0x1;
+int sunxi_gpio_get_cfgbank(void *bank_base, int pin_offset)
+{
+ u32 index = GPIO_CFG_INDEX(pin_offset);
+ u32 offset = GPIO_CFG_OFFSET(pin_offset);
+ u32 cfg;
+
+ cfg = readl(bank_base + GPIO_CFG_REG_OFFSET + index * 4);
+ cfg >>= offset;
+
+ return cfg & 0xf;
+}
+
+int sunxi_gpio_get_cfgpin(u32 pin)
+{
+ u32 bank = GPIO_BANK(pin);
+ void *bank_base = BANK_TO_GPIO(bank);
+
+ return sunxi_gpio_get_cfgbank(bank_base, GPIO_NUM(pin));
+}
+
+static void sunxi_gpio_set_value_bank(void *bank_base, int pin, bool set)
+{
+ u32 mask = 1U << pin;
+
+ clrsetbits_le32(bank_base + GPIO_DAT_REG_OFFSET,
+ set ? 0 : mask, set ? mask : 0);
+}
+
+static int sunxi_gpio_get_value_bank(void *bank_base, int pin)
+{
+ return !!(readl(bank_base + GPIO_DAT_REG_OFFSET) & (1U << pin));
+}
+
+void sunxi_gpio_set_drv(u32 pin, u32 val)
+{
+ u32 bank = GPIO_BANK(pin);
+ void *bank_base = BANK_TO_GPIO(bank);
+
+ sunxi_gpio_set_drv_bank(bank_base, GPIO_NUM(pin), val);
+}
+
+void sunxi_gpio_set_drv_bank(void *bank_base, u32 pin_offset, u32 val)
+{
+ u32 index = GPIO_DRV_INDEX(pin_offset);
+ u32 offset = GPIO_DRV_OFFSET(pin_offset);
+
+ clrsetbits_le32(bank_base + GPIO_DRV_REG_OFFSET + index * 4,
+ 0x3U << offset, val << offset);
+}
+
+void sunxi_gpio_set_pull(u32 pin, u32 val)
+{
+ u32 bank = GPIO_BANK(pin);
+ void *bank_base = BANK_TO_GPIO(bank);
+
+ sunxi_gpio_set_pull_bank(bank_base, GPIO_NUM(pin), val);
+}
+
+void sunxi_gpio_set_pull_bank(void *bank_base, int pin_offset, u32 val)
+{
+ u32 index = GPIO_PULL_INDEX(pin_offset);
+ u32 offset = GPIO_PULL_OFFSET(pin_offset);
+
+ clrsetbits_le32(bank_base + GPIO_PULL_REG_OFFSET + index * 4,
+ 0x3U << offset, val << offset);
+}
+
+
+/* =========== Non-DM code, used by the SPL. ============ */
+
+#if !CONFIG_IS_ENABLED(DM_GPIO)
+static void sunxi_gpio_set_value(u32 pin, bool set)
+{
+ u32 bank = GPIO_BANK(pin);
+ void *pio = BANK_TO_GPIO(bank);
+
+ sunxi_gpio_set_value_bank(pio, GPIO_NUM(pin), set);
+}
+
+static int sunxi_gpio_get_value(u32 pin)
+{
+ u32 bank = GPIO_BANK(pin);
+ void *pio = BANK_TO_GPIO(bank);
+
+ return sunxi_gpio_get_value_bank(pio, GPIO_NUM(pin));
}
int gpio_request(unsigned gpio, const char *label)
@@ -70,18 +198,21 @@
int gpio_direction_output(unsigned gpio, int value)
{
sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_OUTPUT);
+ sunxi_gpio_set_value(gpio, value);
- return sunxi_gpio_output(gpio, value);
+ return 0;
}
int gpio_get_value(unsigned gpio)
{
- return sunxi_gpio_input(gpio);
+ return sunxi_gpio_get_value(gpio);
}
int gpio_set_value(unsigned gpio, int value)
{
- return sunxi_gpio_output(gpio, value);
+ sunxi_gpio_set_value(gpio, value);
+
+ return 0;
}
int sunxi_name_to_gpio(const char *name)
@@ -106,7 +237,9 @@
return -1;
return group * 32 + pin;
}
-#endif /* DM_GPIO */
+#endif /* !DM_GPIO */
+
+/* =========== DM code, used by U-Boot proper. ============ */
#if CONFIG_IS_ENABLED(DM_GPIO)
/* TODO(sjg@chromium.org): Remove this function and use device tree */
@@ -131,13 +264,8 @@
static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset)
{
struct sunxi_gpio_plat *plat = dev_get_plat(dev);
- u32 num = GPIO_NUM(offset);
- unsigned dat;
- dat = readl(&plat->regs->dat);
- dat >>= num;
-
- return dat & 0x1;
+ return sunxi_gpio_get_value_bank(plat->regs, offset);
}
static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset)
@@ -175,9 +303,8 @@
if (flags & GPIOD_IS_OUT) {
u32 value = !!(flags & GPIOD_IS_OUT_ACTIVE);
- u32 num = GPIO_NUM(offset);
- clrsetbits_le32(&plat->regs->dat, 1 << num, value << num);
+ sunxi_gpio_set_value_bank(plat->regs, offset, value);
sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT);
} else if (flags & GPIOD_IS_IN) {
u32 pull = 0;
diff --git a/drivers/gpio/tegra186_gpio.c b/drivers/gpio/tegra186_gpio.c
index 82dcaf9..94a20d1 100644
--- a/drivers/gpio/tegra186_gpio.c
+++ b/drivers/gpio/tegra186_gpio.c
@@ -176,8 +176,8 @@
if (parent_plat)
return 0;
- regs = (uint32_t *)devfdt_get_addr_name(parent, "gpio");
- if (regs == (uint32_t *)FDT_ADDR_T_NONE)
+ regs = dev_read_addr_name_ptr(parent, "gpio");
+ if (!regs)
return -EINVAL;
for (port = 0; port < ctlr_data->port_count; port++) {
diff --git a/drivers/hwspinlock/hwspinlock-uclass.c b/drivers/hwspinlock/hwspinlock-uclass.c
index e012d5a..e9a4d7f 100644
--- a/drivers/hwspinlock/hwspinlock-uclass.c
+++ b/drivers/hwspinlock/hwspinlock-uclass.c
@@ -123,28 +123,7 @@
return ops->unlock(hws->dev, hws->id);
}
-static int hwspinlock_post_bind(struct udevice *dev)
-{
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- struct hwspinlock_ops *ops = device_get_ops(dev);
- static int reloc_done;
-
- if (!reloc_done) {
- if (ops->lock)
- ops->lock += gd->reloc_off;
- if (ops->unlock)
- ops->unlock += gd->reloc_off;
- if (ops->relax)
- ops->relax += gd->reloc_off;
-
- reloc_done++;
- }
-#endif
- return 0;
-}
-
UCLASS_DRIVER(hwspinlock) = {
.id = UCLASS_HWSPINLOCK,
.name = "hwspinlock",
- .post_bind = hwspinlock_post_bind,
};
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 4c76fd7..4f42200 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -372,7 +372,7 @@
config SYS_MXC_I2C1_SLAVE
hex "I2C1 Slave"
- default 0
+ default 0x0
help
MXC I2C1 Slave
endif
@@ -387,7 +387,7 @@
config SYS_MXC_I2C2_SLAVE
hex "I2C2 Slave"
- default 0
+ default 0x0
help
MXC I2C2 Slave
endif
@@ -401,7 +401,7 @@
config SYS_MXC_I2C3_SLAVE
hex "I2C3 Slave"
- default 0
+ default 0x0
help
MXC I2C3 Slave
endif
@@ -415,7 +415,7 @@
config SYS_MXC_I2C4_SLAVE
hex "I2C4 Slave"
- default 0
+ default 0x0
help
MXC I2C4 Slave
endif
@@ -429,7 +429,7 @@
config SYS_MXC_I2C5_SLAVE
hex "I2C5 Slave"
- default 0
+ default 0x0
help
MXC I2C5 Slave
endif
@@ -443,7 +443,7 @@
config SYS_MXC_I2C6_SLAVE
hex "I2C6 Slave"
- default 0
+ default 0x0
help
MXC I2C6 Slave
endif
@@ -457,7 +457,7 @@
config SYS_MXC_I2C7_SLAVE
hex "I2C7 Slave"
- default 0
+ default 0x0
help
MXC I2C7 Slave
endif
@@ -471,7 +471,7 @@
config SYS_MXC_I2C8_SLAVE
hex "I2C8 Slave"
- default 0
+ default 0x0
help
MXC I2C8 Slave
endif
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index d5b85f3..a96a8c7 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -3,7 +3,7 @@
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-$(CONFIG_$(SPL_)DM_I2C) += i2c-uclass.o
-ifdef CONFIG_ACPIGEN
+ifdef CONFIG_$(SPL_)ACPIGEN
obj-$(CONFIG_$(SPL_)DM_I2C) += acpi_i2c.o
endif
obj-$(CONFIG_$(SPL_)DM_I2C_GPIO) += i2c-gpio.o
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index e54de42..215ce01 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -24,6 +24,17 @@
*/
#define DW_I2C_COMP_TYPE 0x44570140
+/*
+ * This constant is used to calculate when during the clock high phase the data
+ * bit shall be read. The value was copied from the Linux v6.5 function
+ * i2c_dw_scl_hcnt() which provides the following explanation:
+ *
+ * "This is just an experimental rule: the tHD;STA period turned out to be
+ * proportinal to (_HCNT + 3). With this setting, we could meet both tHIGH and
+ * tHD;STA timing specs."
+ */
+#define T_HD_STA_OFFSET 3
+
static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
{
u32 ena = enable ? IC_ENABLE_0B : 0;
@@ -155,10 +166,10 @@
/*
* Back-solve for hcnt and lcnt according to the following equations:
- * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
+ * SCL_High_time = [(HCNT + IC_*_SPKLEN + T_HD_STA_OFFSET) * ic_clk] + SCL_Fall_time
* SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
*/
- hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
+ hcnt = min_thigh_cnt - fall_cnt - T_HD_STA_OFFSET - spk_cnt;
lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
if (hcnt < 0 || lcnt < 0) {
@@ -170,13 +181,13 @@
* Now add things back up to ensure the period is hit. If it is off,
* split the difference and bias to lcnt for remainder
*/
- tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
+ tot = hcnt + lcnt + T_HD_STA_OFFSET + spk_cnt + rise_cnt + 1;
if (tot < period_cnt) {
diff = (period_cnt - tot) / 2;
hcnt += diff;
lcnt += diff;
- tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
+ tot = hcnt + lcnt + T_HD_STA_OFFSET + spk_cnt + rise_cnt + 1;
lcnt += period_cnt - tot;
}
diff --git a/drivers/i2c/i2c-emul-uclass.c b/drivers/i2c/i2c-emul-uclass.c
index 1107cf3..d421ddf 100644
--- a/drivers/i2c/i2c-emul-uclass.c
+++ b/drivers/i2c/i2c-emul-uclass.c
@@ -46,7 +46,7 @@
struct udevice *emul;
int ret;
- if (!CONFIG_IS_ENABLED(OF_PLATDATA)) {
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
ret = uclass_find_device_by_phandle(UCLASS_I2C_EMUL, dev,
"sandbox,emul", &emul);
} else {
diff --git a/drivers/i2c/i2c-gpio.c b/drivers/i2c/i2c-gpio.c
index c1fc290..5fc3cfe 100644
--- a/drivers/i2c/i2c-gpio.c
+++ b/drivers/i2c/i2c-gpio.c
@@ -12,6 +12,7 @@
#include <log.h>
#include <asm/gpio.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#define DEFAULT_UDELAY 5
#define RETRIES 0
diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
index 8867a56..98f9585 100644
--- a/drivers/i2c/i2c-uclass.c
+++ b/drivers/i2c/i2c-uclass.c
@@ -388,6 +388,81 @@
return 0;
}
+/* Find and probe I2C bus based on a chip attached to it */
+static int i2c_get_parent_bus(ofnode chip, struct udevice **devp)
+{
+ ofnode node;
+ struct udevice *dev;
+ int ret;
+
+ node = ofnode_get_parent(chip);
+ if (!ofnode_valid(node))
+ return -ENODEV;
+
+ ret = uclass_get_device_by_ofnode(UCLASS_I2C, node, &dev);
+ if (ret) {
+ *devp = NULL;
+ return ret;
+ }
+
+ *devp = dev;
+ return 0;
+}
+
+int i2c_get_chip_by_phandle(const struct udevice *parent, const char *prop_name,
+ struct udevice **devp)
+{
+ ofnode node;
+ uint phandle;
+ struct udevice *bus, *chip;
+ char *dev_name;
+ int ret;
+
+ debug("%s: Searching I2C chip for phandle \"%s\"\n",
+ __func__, prop_name);
+
+ dev_name = strdup(prop_name);
+ if (!dev_name) {
+ ret = -ENOMEM;
+ goto err_exit;
+ }
+
+ ret = dev_read_u32(parent, prop_name, &phandle);
+ if (ret)
+ goto err_exit;
+
+ node = ofnode_get_by_phandle(phandle);
+ if (!ofnode_valid(node)) {
+ ret = -ENODEV;
+ goto err_exit;
+ }
+
+ ret = i2c_get_parent_bus(node, &bus);
+ if (ret)
+ goto err_exit;
+
+ ret = device_bind_driver_to_node(bus, "i2c_generic_chip_drv",
+ dev_name, node, &chip);
+ if (ret)
+ goto err_exit;
+
+ ret = device_probe(chip);
+ if (ret) {
+ device_unbind(chip);
+ goto err_exit;
+ }
+
+ debug("%s succeeded\n", __func__);
+ *devp = chip;
+ return 0;
+
+err_exit:
+ free(dev_name);
+ debug("%s failed, ret = %d\n", __func__, ret);
+ *devp = NULL;
+ return ret;
+}
+
int dm_i2c_probe(struct udevice *bus, uint chip_addr, uint chip_flags,
struct udevice **devp)
{
diff --git a/drivers/i2c/iproc_i2c.c b/drivers/i2c/iproc_i2c.c
index d975e78..39af49c 100644
--- a/drivers/i2c/iproc_i2c.c
+++ b/drivers/i2c/iproc_i2c.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <config.h>
#include <dm.h>
+#include <linux/printk.h>
#include "errno.h"
#include <i2c.h>
#include "iproc_i2c.h"
diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 14cdb0f..c38330f 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -124,7 +124,8 @@
* on other platforms, it is a normal r/w bit, which is cleared by writing 0.
*/
-#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
+#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || \
+ defined(CONFIG_SUNXI_GEN_NCAT2)
#define MVTWSI_CONTROL_CLEAR_IFLG 0x00000008
#else
#define MVTWSI_CONTROL_CLEAR_IFLG 0x00000000
diff --git a/drivers/i2c/npcm_i2c.c b/drivers/i2c/npcm_i2c.c
index ea4ef53..b867b6c 100644
--- a/drivers/i2c/npcm_i2c.c
+++ b/drivers/i2c/npcm_i2c.c
@@ -517,11 +517,6 @@
u32 sclfrq;
u8 hldt, val;
- if (bus_freq > I2C_FREQ_100K) {
- printf("Support standard mode only\n");
- return -EINVAL;
- }
-
/* SCLFRQ = T(SCL)/4/T(CLK) = FREQ(CLK)/4/FREQ(SCL) */
sclfrq = freq / (bus_freq * 4);
if (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX)
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index c656cf8..6fc9d1e 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -43,6 +43,7 @@
#include <i2c.h>
#include <log.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <asm/io.h>
#include <asm/omap_i2c.h>
diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c
index 836148e..b6c7178 100644
--- a/drivers/i2c/stm32f7_i2c.c
+++ b/drivers/i2c/stm32f7_i2c.c
@@ -19,6 +19,7 @@
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
+#include <linux/printk.h>
/* STM32 I2C registers */
struct stm32_i2c_regs {
diff --git a/drivers/i2c/sun6i_p2wi.c b/drivers/i2c/sun6i_p2wi.c
index d221323..b8e07a5 100644
--- a/drivers/i2c/sun6i_p2wi.c
+++ b/drivers/i2c/sun6i_p2wi.c
@@ -20,10 +20,10 @@
#include <errno.h>
#include <i2c.h>
#include <reset.h>
+#include <sunxi_gpio.h>
#include <time.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/p2wi.h>
#include <asm/arch/prcm.h>
#include <asm/arch/sys_proto.h>
diff --git a/drivers/i2c/sun8i_rsb.c b/drivers/i2c/sun8i_rsb.c
index 47fa05b..f36f2c7 100644
--- a/drivers/i2c/sun8i_rsb.c
+++ b/drivers/i2c/sun8i_rsb.c
@@ -14,10 +14,10 @@
#include <dm.h>
#include <errno.h>
#include <i2c.h>
+#include <sunxi_gpio.h>
#include <reset.h>
#include <time.h>
#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/prcm.h>
#include <asm/arch/rsb.h>
diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c
index 5864a1a..57d77d5 100644
--- a/drivers/i2c/tegra_i2c.c
+++ b/drivers/i2c/tegra_i2c.c
@@ -21,6 +21,7 @@
#include <asm/arch-tegra/tegra_i2c.h>
#include <linux/delay.h>
#include <linux/err.h>
+#include <linux/printk.h>
enum i2c_type {
TYPE_114,
diff --git a/drivers/input/input.c b/drivers/input/input.c
index a4341e8..8a6506e 100644
--- a/drivers/input/input.c
+++ b/drivers/input/input.c
@@ -669,17 +669,22 @@
int error;
error = stdio_register(dev);
-#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(ENV_SUPPORT)
- /* check if this is the standard input device */
- if (!error && strcmp(env_get("stdin"), dev->name) == 0) {
- /* reassign the console */
- if (OVERWRITE_CONSOLE ||
- console_assign(stdin, dev->name))
- return -1;
+
+ if (!CONFIG_IS_ENABLED(ENV_SUPPORT))
+ return 0;
+
+ if (!error) {
+ const char *cstdin;
+
+ /* check if this is the standard input device */
+ cstdin = env_get("stdin");
+ if (cstdin && !strcmp(cstdin, dev->name)) {
+ /* reassign the console */
+ if (OVERWRITE_CONSOLE ||
+ console_assign(stdin, dev->name))
+ return -1;
+ }
}
-#else
- error = error;
-#endif
return 0;
}
diff --git a/drivers/mailbox/k3-sec-proxy.c b/drivers/mailbox/k3-sec-proxy.c
index 8158084..05f6b17 100644
--- a/drivers/mailbox/k3-sec-proxy.c
+++ b/drivers/mailbox/k3-sec-proxy.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments' K3 Secure proxy Driver
*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
@@ -84,9 +84,9 @@
struct mbox_chan chan;
struct k3_sec_proxy_desc *desc;
struct k3_sec_proxy_thread *chans;
- phys_addr_t target_data;
- phys_addr_t scfg;
- phys_addr_t rt;
+ void *target_data;
+ void *scfg;
+ void *rt;
};
static inline u32 sp_readl(void __iomem *addr, unsigned int offset)
@@ -319,20 +319,20 @@
return -ENODEV;
}
- spm->target_data = devfdt_get_addr_name(dev, "target_data");
- if (spm->target_data == FDT_ADDR_T_NONE) {
+ spm->target_data = dev_read_addr_name_ptr(dev, "target_data");
+ if (!spm->target_data) {
dev_err(dev, "No reg property for target data base\n");
return -EINVAL;
}
- spm->scfg = devfdt_get_addr_name(dev, "scfg");
- if (spm->rt == FDT_ADDR_T_NONE) {
+ spm->scfg = dev_read_addr_name_ptr(dev, "scfg");
+ if (!spm->scfg) {
dev_err(dev, "No reg property for Secure Cfg base\n");
return -EINVAL;
}
- spm->rt = devfdt_get_addr_name(dev, "rt");
- if (spm->rt == FDT_ADDR_T_NONE) {
+ spm->rt = dev_read_addr_name_ptr(dev, "rt");
+ if (!spm->rt) {
dev_err(dev, "No reg property for Real Time Cfg base\n");
return -EINVAL;
}
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 22cb9d6..d10edd2 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -61,7 +61,6 @@
if TI_GPMC
config TI_GPMC_DEBUG
bool "Debug Texas Instruments GPMC timings"
- default n
help
Enable this to print GPMC timings before and after the GPMC registers
are programmed. This should not be left enabled on production systems.
diff --git a/drivers/memory/ti-gpmc.c b/drivers/memory/ti-gpmc.c
index f511a52..775e78c 100644
--- a/drivers/memory/ti-gpmc.c
+++ b/drivers/memory/ti-gpmc.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments GPMC Driver
*
- * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <asm/io.h>
diff --git a/drivers/memory/ti-gpmc.h b/drivers/memory/ti-gpmc.h
index 90f8e65..6fe098a 100644
--- a/drivers/memory/ti-gpmc.h
+++ b/drivers/memory/ti-gpmc.h
@@ -2,7 +2,7 @@
/*
* Texas Instruments GPMC Driver
*
- * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/* GPMC register offsets */
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 749d3c4..fdac378 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -101,6 +101,15 @@
addressing and a length or through child-nodes that are generated
based on the e-fuse map retrieved from the DTS.
+config ROCKCHIP_IODOMAIN
+ bool "Rockchip IO-domain driver support"
+ depends on DM_REGULATOR && ARCH_ROCKCHIP
+ default y if ROCKCHIP_RK3568
+ help
+ Enable support for IO-domains in Rockchip SoCs. It is necessary
+ for the IO-domain setting of the SoC to match the voltage supplied
+ by the regulators.
+
config SIFIVE_OTP
bool "SiFive eMemory OTP driver"
depends on MISC
@@ -122,6 +131,14 @@
configuration bus on the Arm Versatile Express boards via
a sysreg driver.
+config CBMEM_CONSOLE
+ bool "Write console output to coreboot cbmem"
+ depends on X86
+ help
+ Enables console output to the cbmem console, which is a memory
+ region set up by coreboot to hold a record of all console output.
+ Enable this only if booting from coreboot.
+
config CMD_CROS_EC
bool "Enable crosec command"
depends on CROS_EC
@@ -358,7 +375,6 @@
config NPCM_OTP
bool "Nnvoton NPCM BMC On-Chip OTP Memory Support"
depends on (ARM && ARCH_NPCM)
- default n
help
Support NPCM BMC OTP memory (fuse).
To compile this driver as a module, choose M here: the module
@@ -555,7 +571,7 @@
config SYS_I2C_EEPROM_ADDR
hex "Chip address of the EEPROM device"
depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
- default 0
+ default 0x0
if I2C_EEPROM
@@ -599,7 +615,7 @@
ie. the FPGA device.
config SPL_FS_LOADER
- bool "Enable loader driver for file system"
+ bool "Enable loader driver for file system in SPL"
depends on SPL
help
This is file system generic loader which can be used to load
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index fd8805f..b67b823 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -69,6 +69,7 @@
endif
obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
obj-$(CONFIG_ROCKCHIP_OTP) += rockchip-otp.o
+obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_IODOMAIN) += rockchip-io-domain.o
obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o
obj-$(CONFIG_SIFIVE_OTP) += sifive-otp.o
obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
diff --git a/drivers/misc/cbmem_console.c b/drivers/misc/cbmem_console.c
index 8bbe33d..ba3a599 100644
--- a/drivers/misc/cbmem_console.c
+++ b/drivers/misc/cbmem_console.c
@@ -5,27 +5,37 @@
#include <common.h>
#include <console.h>
-#ifndef CONFIG_SYS_COREBOOT
-#error This driver requires coreboot
-#endif
-
#include <asm/cb_sysinfo.h>
-struct cbmem_console {
- u32 buffer_size;
- u32 buffer_cursor;
- u8 buffer_body[0];
-} __attribute__ ((__packed__));
-
-static struct cbmem_console *cbmem_console_p;
-
void cbmemc_putc(struct stdio_dev *dev, char data)
{
- int cursor;
+ const struct sysinfo_t *sysinfo = cb_get_sysinfo();
+ struct cbmem_console *cons;
+ uint pos, flags;
- cursor = cbmem_console_p->buffer_cursor++;
- if (cursor < cbmem_console_p->buffer_size)
- cbmem_console_p->buffer_body[cursor] = data;
+ if (!sysinfo)
+ return;
+ cons = sysinfo->cbmem_cons;
+ if (!cons)
+ return;
+
+ pos = cons->cursor & CBMC_CURSOR_MASK;
+
+ /* preserve the overflow flag if present */
+ flags = cons->cursor & ~CBMC_CURSOR_MASK;
+
+ cons->body[pos++] = data;
+
+ /*
+ * Deal with overflow - the flag may be cleared by another program which
+ * reads the buffer out later, e.g. Linux
+ */
+ if (pos >= cons->size) {
+ pos = 0;
+ flags |= CBMC_OVERFLOW;
+ }
+
+ cons->cursor = flags | pos;
}
void cbmemc_puts(struct stdio_dev *dev, const char *str)
@@ -40,7 +50,6 @@
{
int rc;
struct stdio_dev cons_dev;
- cbmem_console_p = lib_sysinfo.cbmem_cons;
memset(&cons_dev, 0, sizeof(cons_dev));
diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index 621d175..9c1e6a5 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -1100,8 +1100,11 @@
ret = ec_command_inptr(dev, EC_CMD_GET_SKU_ID, 0, NULL, 0,
(uint8_t **)&r, sizeof(*r));
- if (ret != sizeof(*r))
- return -ret;
+ if (ret != sizeof(*r)) {
+ if (ret >= 0)
+ ret = -EIO;
+ return ret;
+ }
return r->sku_id;
}
diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c
index 8dbe0b1..1201535 100644
--- a/drivers/misc/cros_ec_sandbox.c
+++ b/drivers/misc/cros_ec_sandbox.c
@@ -81,6 +81,7 @@
/**
* struct ec_state - Information about the EC state
*
+ * @valid: true if this struct contains valid state data
* @vbnv_context: Vboot context data stored by EC
* @ec_config: FDT config information about the EC (e.g. flashmap)
* @flash_data: Contents of flash memory
@@ -95,6 +96,7 @@
* @pwm: Information per PWM channel
*/
struct ec_state {
+ bool valid;
u8 vbnv_context[EC_VBNV_BLOCK_SIZE_V2];
struct fdt_cros_ec ec_config;
uint8_t *flash_data;
@@ -145,6 +147,7 @@
memcpy(ec->flash_data, prop, len);
debug("%s: Loaded EC flash data size %#x\n", __func__, len);
}
+ ec->valid = true;
return 0;
}
@@ -589,6 +592,7 @@
printf(" ** Unknown EC command %#02x\n", req_hdr->command);
return -1;
}
+ debug(" - EC command %#0x, result %d\n", req_hdr->command, len);
return len;
}
@@ -675,7 +679,10 @@
ofnode node;
int err;
- memcpy(ec, &s_state, sizeof(*ec));
+ if (s_state.valid)
+ memcpy(ec, &s_state, sizeof(*ec));
+ else
+ ec->current_image = EC_IMAGE_RO;
err = cros_ec_decode_ec_flash(dev, &ec->ec_config);
if (err) {
debug("%s: Cannot device EC flash\n", __func__);
diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c
index 001f0a8..591ff30 100644
--- a/drivers/misc/cros_ec_spi.c
+++ b/drivers/misc/cros_ec_spi.c
@@ -151,7 +151,7 @@
/* Response code is first byte of message */
if (p[0] != EC_RES_SUCCESS) {
- printf("%s: Returned status %d\n", __func__, p[0]);
+ log_debug("Returned status %d\n", p[0]);
return -(int)(p[0]);
}
diff --git a/drivers/misc/esm_pmic.c b/drivers/misc/esm_pmic.c
index b971f32..a518f75 100644
--- a/drivers/misc/esm_pmic.c
+++ b/drivers/misc/esm_pmic.c
@@ -2,7 +2,7 @@
/*
* PMIC Error Signal Monitor driver
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* Tero Kristo <t-kristo@ti.com>
*
*/
diff --git a/drivers/misc/fs_loader.c b/drivers/misc/fs_loader.c
index ccf5c7a..1ffc199 100644
--- a/drivers/misc/fs_loader.c
+++ b/drivers/misc/fs_loader.c
@@ -316,7 +316,7 @@
return ret;
/* Just create a new device */
- ret = device_bind(dm_root(), DM_DRIVER_GET(fs_loader), "default-loader",
+ ret = device_bind(dm_root(), DM_DRIVER_REF(fs_loader), "default-loader",
&default_plat, ofnode_null(), dev);
if (ret)
return ret;
diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c
index bdd7e01..9111bd7 100644
--- a/drivers/misc/i2c_eeprom.c
+++ b/drivers/misc/i2c_eeprom.c
@@ -60,6 +60,17 @@
return dm_i2c_read(dev, offset, buf, size);
}
+static int i2c_eeprom_len(int offset, int len, int pagesize)
+{
+ int page_offset = offset & (pagesize - 1);
+ int maxlen = pagesize - page_offset;
+
+ if (len > maxlen)
+ len = maxlen;
+
+ return len;
+}
+
static int i2c_eeprom_std_write(struct udevice *dev, int offset,
const uint8_t *buf, int size)
{
@@ -67,7 +78,7 @@
int ret;
while (size > 0) {
- int write_size = min_t(int, size, priv->pagesize);
+ int write_size = i2c_eeprom_len(offset, size, priv->pagesize);
ret = dm_i2c_write(dev, offset, buf, write_size);
if (ret)
@@ -227,6 +238,13 @@
.offset_len = 2,
};
+static const struct i2c_eeprom_drv_data atmel24c32d_wlp_data = {
+ .size = 32,
+ .pagesize = 32,
+ .addr_offset_mask = 0,
+ .offset_len = 2,
+};
+
static const struct i2c_eeprom_drv_data atmel24c64_data = {
.size = 8192,
.pagesize = 32,
@@ -266,6 +284,7 @@
{ .compatible = "atmel,24c16a", (ulong)&atmel24c16a_data },
{ .compatible = "atmel,24mac402", (ulong)&atmel24mac402_data },
{ .compatible = "atmel,24c32", (ulong)&atmel24c32_data },
+ { .compatible = "atmel,24c32d-wl", (ulong)&atmel24c32d_wlp_data },
{ .compatible = "atmel,24c64", (ulong)&atmel24c64_data },
{ .compatible = "atmel,24c128", (ulong)&atmel24c128_data },
{ .compatible = "atmel,24c256", (ulong)&atmel24c256_data },
diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c
index 840148d..0d29eff 100644
--- a/drivers/misc/k3_avs.c
+++ b/drivers/misc/k3_avs.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments' K3 Clas 0 Adaptive Voltage Scaling driver
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* Tero Kristo <t-kristo@ti.com>
*
*/
@@ -15,6 +15,7 @@
#include <k3-avs.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
+#include <linux/delay.h>
#include <power/regulator.h>
#define AM6_VTM_DEVINFO(i) (priv->base + 0x100 + 0x20 * (i))
@@ -25,11 +26,28 @@
#define AM6_VTM_OPP_SHIFT(opp) (8 * (opp))
#define AM6_VTM_OPP_MASK 0xff
+#define K3_VTM_DEVINFO_PWR0_OFFSET 0x4
+#define K3_VTM_DEVINFO_PWR0_TEMPSENS_CT_MASK 0xf0
+#define K3_VTM_TMPSENS0_CTRL_OFFSET 0x300
+#define K3_VTM_TMPSENS_STAT_OFFSET 0x8
+#define K3_VTM_ANYMAXT_OUTRG_ALERT_EN 0x1
+#define K3_VTM_LOW_TEMP_OFFSET 0x10
+#define K3_VTM_MISC_CTRL2_OFFSET 0x10
+#define K3_VTM_MISC_CTRL1_OFFSET 0xc
+#define K3_VTM_TMPSENS_CTRL1_SOC BIT(5)
+#define K3_VTM_TMPSENS_CTRL_CLRZ BIT(6)
+#define K3_VTM_TMPSENS_CTRL_MAXT_OUTRG_EN BIT(11)
+#define K3_VTM_ADC_COUNT_FOR_123C 0x2f8
+#define K3_VTM_ADC_COUNT_FOR_105C 0x288
+#define K3_VTM_ADC_WA_VALUE 0x2c
+#define K3_VTM_FUSE_MASK 0xc0000000
+
#define VD_FLAG_INIT_DONE BIT(0)
struct k3_avs_privdata {
void *base;
struct vd_config *vd_config;
+ struct udevice *dev;
};
struct opp {
@@ -237,6 +255,88 @@
return 0;
}
+/* k3_avs_program_tshut : Program thermal shutdown value for SOC
+ * set the values corresponding to thresholds to ~123C and 105C
+ * This is optional feature, Few times OS driver takes care of
+ * tshut programing.
+ */
+
+static void k3_avs_program_tshut(struct k3_avs_privdata *priv)
+{
+ int cnt, id, val;
+ int workaround_needed = 0;
+ u32 ctrl_offset;
+ void __iomem *cfg2_base;
+ void __iomem *fuse_base;
+
+ cfg2_base = (void __iomem *)devfdt_get_addr_index(priv->dev, 1);
+ if (IS_ERR(cfg2_base)) {
+ dev_err(priv->dev, "cfg base is not defined\n");
+ return;
+ }
+
+ /*
+ * Some of TI's J721E SoCs require a software trimming procedure
+ * for the temperature monitors to function properly. To determine
+ * if this particular SoC is NOT affected, both bits in the
+ * WKUP_SPARE_FUSE0[31:30] will be set (0xC0000000) indicating
+ * when software trimming should NOT be applied.
+ *
+ * https://www.ti.com/lit/er/sprz455c/sprz455c.pdf
+ * This routine checks if workaround_needed to be applied or not
+ * based upon workaround_needed, adjust fixed value of tshut high and low
+ */
+
+ if (device_is_compatible(priv->dev, "ti,j721e-vtm")) {
+ fuse_base = (void __iomem *)devfdt_get_addr_index(priv->dev, 2);
+ if (IS_ERR(fuse_base)) {
+ dev_err(priv->dev, "fuse-base is not defined for J721E Soc\n");
+ return;
+ }
+
+ if (!((readl(fuse_base) & K3_VTM_FUSE_MASK) == K3_VTM_FUSE_MASK))
+ workaround_needed = 1;
+ }
+
+ dev_dbg(priv->dev, "Work around %sneeded\n", workaround_needed ? "" : "not ");
+
+ /* Get the sensor count in the VTM */
+ val = readl(priv->base + K3_VTM_DEVINFO_PWR0_OFFSET);
+ cnt = val & K3_VTM_DEVINFO_PWR0_TEMPSENS_CT_MASK;
+ cnt >>= __ffs(K3_VTM_DEVINFO_PWR0_TEMPSENS_CT_MASK);
+
+ /* Program the thermal sensors */
+ for (id = 0; id < cnt; id++) {
+ ctrl_offset = K3_VTM_TMPSENS0_CTRL_OFFSET + id * 0x20;
+
+ val = readl(cfg2_base + ctrl_offset);
+ val |= (K3_VTM_TMPSENS_CTRL_MAXT_OUTRG_EN |
+ K3_VTM_TMPSENS_CTRL1_SOC |
+ K3_VTM_TMPSENS_CTRL_CLRZ | BIT(4));
+ writel(val, cfg2_base + ctrl_offset);
+ }
+
+ /*
+ * Program TSHUT thresholds
+ * Step 1: set the thresholds to ~123C and 105C WKUP_VTM_MISC_CTRL2
+ * Step 2: WKUP_VTM_TMPSENS_CTRL_j set the MAXT_OUTRG_EN bit
+ * This is already taken care as per of init
+ * Step 3: WKUP_VTM_MISC_CTRL set the ANYMAXT_OUTRG_ALERT_EN bit
+ */
+
+ /* Low thresholds for tshut*/
+ val = (K3_VTM_ADC_COUNT_FOR_105C - workaround_needed * K3_VTM_ADC_WA_VALUE)
+ << K3_VTM_LOW_TEMP_OFFSET;
+ /* high thresholds */
+ val |= K3_VTM_ADC_COUNT_FOR_123C - workaround_needed * K3_VTM_ADC_WA_VALUE;
+
+ writel(val, cfg2_base + K3_VTM_MISC_CTRL2_OFFSET);
+ /* ramp-up delay from Linux code */
+ mdelay(100);
+ val = readl(cfg2_base + K3_VTM_MISC_CTRL1_OFFSET) | K3_VTM_ANYMAXT_OUTRG_ALERT_EN;
+ writel(val, cfg2_base + K3_VTM_MISC_CTRL1_OFFSET);
+}
+
/**
* k3_avs_probe: parses VD info from VTM, and re-configures the OPP data
*
@@ -255,6 +355,7 @@
int ret;
priv = dev_get_priv(dev);
+ priv->dev = dev;
k3_avs_priv = priv;
@@ -294,6 +395,9 @@
k3_avs_program_voltage(priv, vd, vd->opp);
}
+ if (!device_is_compatible(priv->dev, "ti,am654-avs"))
+ k3_avs_program_tshut(priv);
+
return 0;
}
@@ -382,6 +486,8 @@
static const struct udevice_id k3_avs_ids[] = {
{ .compatible = "ti,am654-avs", .data = (ulong)&am654_vd_config },
{ .compatible = "ti,j721e-avs", .data = (ulong)&j721e_vd_config },
+ { .compatible = "ti,j721e-vtm", .data = (ulong)&j721e_vd_config },
+ { .compatible = "ti,j7200-vtm", .data = (ulong)&j721e_vd_config },
{}
};
diff --git a/drivers/misc/k3_esm.c b/drivers/misc/k3_esm.c
index 41faeb3..f6ac18b 100644
--- a/drivers/misc/k3_esm.c
+++ b/drivers/misc/k3_esm.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments' K3 Error Signalling Module driver
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* Tero Kristo <t-kristo@ti.com>
*
*/
diff --git a/drivers/misc/rockchip-io-domain.c b/drivers/misc/rockchip-io-domain.c
new file mode 100644
index 0000000..3f6227f
--- /dev/null
+++ b/drivers/misc/rockchip-io-domain.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Rockchip IO Voltage Domain driver
+ *
+ * Ported from linux drivers/soc/rockchip/io-domain.c
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <power/regulator.h>
+
+#define MAX_SUPPLIES 16
+
+/*
+ * The max voltage for 1.8V and 3.3V come from the Rockchip datasheet under
+ * "Recommended Operating Conditions" for "Digital GPIO". When the typical
+ * is 3.3V the max is 3.6V. When the typical is 1.8V the max is 1.98V.
+ *
+ * They are used like this:
+ * - If the voltage on a rail is above the "1.8" voltage (1.98V) we'll tell the
+ * SoC we're at 3.3.
+ * - If the voltage on a rail is above the "3.3" voltage (3.6V) we'll consider
+ * that to be an error.
+ */
+#define MAX_VOLTAGE_1_8 1980000
+#define MAX_VOLTAGE_3_3 3600000
+
+#define RK3568_PMU_GRF_IO_VSEL0 0x0140
+#define RK3568_PMU_GRF_IO_VSEL1 0x0144
+#define RK3568_PMU_GRF_IO_VSEL2 0x0148
+
+struct rockchip_iodomain_soc_data {
+ int grf_offset;
+ const char *supply_names[MAX_SUPPLIES];
+ int (*write)(struct regmap *grf, int idx, int uV);
+};
+
+static int rk3568_iodomain_write(struct regmap *grf, int idx, int uV)
+{
+ u32 is_3v3 = uV > MAX_VOLTAGE_1_8;
+ u32 val0, val1;
+ int b;
+
+ switch (idx) {
+ case 0: /* pmuio1 */
+ break;
+ case 1: /* pmuio2 */
+ b = idx;
+ val0 = BIT(16 + b) | (is_3v3 ? 0 : BIT(b));
+ b = idx + 4;
+ val1 = BIT(16 + b) | (is_3v3 ? BIT(b) : 0);
+
+ regmap_write(grf, RK3568_PMU_GRF_IO_VSEL2, val0);
+ regmap_write(grf, RK3568_PMU_GRF_IO_VSEL2, val1);
+ break;
+ case 3: /* vccio2 */
+ break;
+ case 2: /* vccio1 */
+ case 4: /* vccio3 */
+ case 5: /* vccio4 */
+ case 6: /* vccio5 */
+ case 7: /* vccio6 */
+ case 8: /* vccio7 */
+ b = idx - 1;
+ val0 = BIT(16 + b) | (is_3v3 ? 0 : BIT(b));
+ val1 = BIT(16 + b) | (is_3v3 ? BIT(b) : 0);
+
+ regmap_write(grf, RK3568_PMU_GRF_IO_VSEL0, val0);
+ regmap_write(grf, RK3568_PMU_GRF_IO_VSEL1, val1);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct rockchip_iodomain_soc_data soc_data_rk3568_pmu = {
+ .grf_offset = 0x140,
+ .supply_names = {
+ NULL,
+ "pmuio2-supply",
+ "vccio1-supply",
+ NULL,
+ "vccio3-supply",
+ "vccio4-supply",
+ "vccio5-supply",
+ "vccio6-supply",
+ "vccio7-supply",
+ },
+ .write = rk3568_iodomain_write,
+};
+
+static const struct udevice_id rockchip_iodomain_ids[] = {
+ {
+ .compatible = "rockchip,rk3568-pmu-io-voltage-domain",
+ .data = (ulong)&soc_data_rk3568_pmu,
+ },
+ { }
+};
+
+static int rockchip_iodomain_bind(struct udevice *dev)
+{
+ /*
+ * According to the Hardware Design Guide, IO-domain configuration must
+ * be consistent with the power supply voltage (1.8V or 3.3V).
+ * Probe after bind to configure IO-domain voltage early during boot.
+ */
+ dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+
+ return 0;
+}
+
+static int rockchip_iodomain_probe(struct udevice *dev)
+{
+ struct rockchip_iodomain_soc_data *soc_data =
+ (struct rockchip_iodomain_soc_data *)dev_get_driver_data(dev);
+ struct regmap *grf;
+ int ret;
+
+ grf = syscon_get_regmap(dev_get_parent(dev));
+ if (IS_ERR(grf))
+ return PTR_ERR(grf);
+
+ for (int i = 0; i < MAX_SUPPLIES; i++) {
+ const char *supply_name = soc_data->supply_names[i];
+ struct udevice *reg;
+ int uV;
+
+ if (!supply_name)
+ continue;
+
+ ret = device_get_supply_regulator(dev, supply_name, ®);
+ if (ret)
+ continue;
+
+ ret = regulator_autoset(reg);
+ if (ret && ret != -EALREADY && ret != -EMEDIUMTYPE &&
+ ret != -ENOSYS)
+ continue;
+
+ uV = regulator_get_value(reg);
+ if (uV <= 0)
+ continue;
+
+ if (uV > MAX_VOLTAGE_3_3) {
+ dev_crit(dev, "%s: %d uV is too high. May damage SoC!\n",
+ supply_name, uV);
+ continue;
+ }
+
+ soc_data->write(grf, i, uV);
+ }
+
+ return 0;
+}
+
+U_BOOT_DRIVER(rockchip_iodomain) = {
+ .name = "rockchip_iodomain",
+ .id = UCLASS_NOP,
+ .of_match = rockchip_iodomain_ids,
+ .bind = rockchip_iodomain_bind,
+ .probe = rockchip_iodomain_probe,
+};
diff --git a/drivers/misc/rockchip-otp.c b/drivers/misc/rockchip-otp.c
index 4814e0e..4f75708 100644
--- a/drivers/misc/rockchip-otp.c
+++ b/drivers/misc/rockchip-otp.c
@@ -61,11 +61,20 @@
#define RK3588_OTPC_INT_ST 0x0084
#define RK3588_RD_DONE BIT(1)
+#define RV1126_OTP_NVM_CEB 0x00
+#define RV1126_OTP_NVM_RSTB 0x04
+#define RV1126_OTP_NVM_ST 0x18
+#define RV1126_OTP_NVM_RADDR 0x1C
+#define RV1126_OTP_NVM_RSTART 0x20
+#define RV1126_OTP_NVM_RDATA 0x24
+#define RV1126_OTP_READ_ST 0x30
+
struct rockchip_otp_plat {
void __iomem *base;
};
struct rockchip_otp_data {
+ int (*init)(struct udevice *dev);
int (*read)(struct udevice *dev, int offset, void *buf, int size);
int offset;
int size;
@@ -232,6 +241,48 @@
return 0;
}
+static int rockchip_rv1126_otp_init(struct udevice *dev)
+{
+ struct rockchip_otp_plat *otp = dev_get_plat(dev);
+ int ret;
+
+ writel(0x0, otp->base + RV1126_OTP_NVM_CEB);
+ ret = rockchip_otp_poll_timeout(otp, 0x1, RV1126_OTP_NVM_ST);
+
+ if (ret)
+ return ret;
+
+ writel(0x1, otp->base + RV1126_OTP_NVM_RSTB);
+ ret = rockchip_otp_poll_timeout(otp, 0x4, RV1126_OTP_NVM_ST);
+
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int rockchip_rv1126_otp_read(struct udevice *dev, int offset, void *buf,
+ int size)
+{
+ struct rockchip_otp_plat *otp = dev_get_plat(dev);
+ u32 status = 0;
+ u8 *buffer = buf;
+ int ret = 0;
+
+ while (size--) {
+ writel(offset++, otp->base + RV1126_OTP_NVM_RADDR);
+ writel(0x1, otp->base + RV1126_OTP_NVM_RSTART);
+ ret = readl_poll_timeout(otp->base + RV1126_OTP_READ_ST,
+ status, !status, OTPC_TIMEOUT);
+ if (ret)
+ return ret;
+
+ *buffer++ = (u8)(readl(otp->base + RV1126_OTP_NVM_RDATA) & 0xFF);
+ }
+
+ return 0;
+}
+
static int rockchip_otp_read(struct udevice *dev, int offset,
void *buf, int size)
{
@@ -286,6 +337,20 @@
return 0;
}
+static int rockchip_otp_probe(struct udevice *dev)
+{
+ struct rockchip_otp_data *data;
+
+ data = (struct rockchip_otp_data *)dev_get_driver_data(dev);
+ if (!data)
+ return -EINVAL;
+
+ if (data->init)
+ return data->init(dev);
+
+ return 0;
+}
+
static const struct rockchip_otp_data px30_data = {
.read = rockchip_px30_otp_read,
.size = 0x40,
@@ -304,6 +369,12 @@
.block_size = 4,
};
+static const struct rockchip_otp_data rv1126_data = {
+ .init = rockchip_rv1126_otp_init,
+ .read = rockchip_rv1126_otp_read,
+ .size = 0x40,
+};
+
static const struct udevice_id rockchip_otp_ids[] = {
{
.compatible = "rockchip,px30-otp",
@@ -321,6 +392,10 @@
.compatible = "rockchip,rk3588-otp",
.data = (ulong)&rk3588_data,
},
+ {
+ .compatible = "rockchip,rv1126-otp",
+ .data = (ulong)&rv1126_data,
+ },
{}
};
@@ -331,4 +406,5 @@
.of_to_plat = rockchip_otp_of_to_plat,
.plat_auto = sizeof(struct rockchip_otp_plat),
.ops = &rockchip_otp_ops,
+ .probe = rockchip_otp_probe,
};
diff --git a/drivers/misc/sifive-otp.c b/drivers/misc/sifive-otp.c
index 3e658b3..a624a35 100644
--- a/drivers/misc/sifive-otp.c
+++ b/drivers/misc/sifive-otp.c
@@ -24,6 +24,7 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <misc.h>
+#include <linux/printk.h>
#define BYTES_PER_FUSE 4
diff --git a/drivers/misc/tegra186_bpmp.c b/drivers/misc/tegra186_bpmp.c
index dbee7f7..fecac9c 100644
--- a/drivers/misc/tegra186_bpmp.c
+++ b/drivers/misc/tegra186_bpmp.c
@@ -17,6 +17,7 @@
#include <asm/arch-tegra/ivc.h>
#include <linux/bitops.h>
#include <linux/err.h>
+#include <linux/printk.h>
#define BPMP_IVC_FRAME_COUNT 1
#define BPMP_IVC_FRAME_SIZE 128
diff --git a/drivers/misc/vexpress_config.c b/drivers/misc/vexpress_config.c
index 2baca48..99aad14 100644
--- a/drivers/misc/vexpress_config.c
+++ b/drivers/misc/vexpress_config.c
@@ -92,7 +92,7 @@
static int vexpress_config_probe(struct udevice *dev)
{
struct ofnode_phandle_args args;
- struct vexpress_config_sysreg *priv;
+ struct vexpress_config_sysreg *priv = dev_get_priv(dev);
const char *prop;
int err, prop_size;
@@ -105,11 +105,9 @@
if (!prop || (strncmp(prop, "arm,vexpress-sysreg", 19) != 0))
return -ENOENT;
- priv = calloc(1, sizeof(*priv));
if (!priv)
return -ENOMEM;
- dev_get_uclass_priv(dev) = priv;
priv->addr = ofnode_get_addr(args.node);
return dev_read_u32(dev, "arm,vexpress,site", &priv->site);
@@ -127,4 +125,5 @@
.bind = dm_scan_fdt_dev,
.probe = vexpress_config_probe,
.ops = &vexpress_config_ops,
+ .priv_auto = sizeof(struct vexpress_config_sysreg),
};
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index de01b96..17618c3 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -46,6 +46,7 @@
depends on SPL_DM && DM_MMC
default n if ARCH_MVEBU && !MVEBU_SPL_BOOT_DEVICE_MMC
default y
+ select SPL_BLK
help
This enables the MultiMediaCard (MMC) uclass which supports MMC and
Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
@@ -390,12 +391,6 @@
depends on MMC_OMAP_HS && (OMAP44XX || OMAP54XX || DRA7XX || AM33XX || \
AM43XX || ARCH_KEYSTONE)
-config SH_SDHI
- bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support"
- depends on ARCH_RMOBILE
- help
- Support for the on-chip SDHI host controller on SuperH/Renesas ARM SoCs platform
-
config SH_MMCIF
bool "SuperH/Renesas ARM SoCs on-chip MMCIF host controller support"
depends on ARCH_RMOBILE || SH
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 2c65c47..e9cf1fc 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -49,7 +49,6 @@
obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
obj-$(CONFIG_MMC_SANDBOX) += sandbox_mmc.o
obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
-obj-$(CONFIG_SH_SDHI) += sh_sdhi.o
obj-$(CONFIG_STM32_SDMMC2) += stm32_sdmmc2.o
obj-$(CONFIG_JZ47XX_MMC) += jz_mmc.o
obj-$(CONFIG_NEXELL_DWMMC) += nexell_dw_mmc.o
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index fd667ae..05595bd 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*
* Texas Instruments' K3 SD Host Controller Interface
*/
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 5085a3b..400066f 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -509,6 +509,10 @@
if (mmc->vqmmc_supply) {
int ret;
+ ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
+ if (ret)
+ return ret;
+
if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
regulator_set_value(mmc->vqmmc_supply, 1800000);
else
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 544798b..2f849c4 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -16,6 +16,7 @@
#include <asm/arch/pinmux.h>
#include <asm/arch/power.h>
#include <asm/gpio.h>
+#include <linux/printk.h>
#define DWMMC_MAX_CH_NUM 4
#define DWMMC_MAX_FREQ 52000000
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 66caf68..7c39c86 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -26,6 +26,7 @@
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
+#include <linux/printk.h>
#include <power/regulator.h>
#include <malloc.h>
#include <fsl_esdhc_imx.h>
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index 0e15767..3284568 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -412,7 +412,7 @@
debug("%s: alias devnum=%d\n", __func__, dev_seq(dev));
ret = blk_create_devicef(dev, "mmc_blk", "blk", UCLASS_MMC,
- dev_seq(dev), 512, 0, &bdev);
+ dev_seq(dev), DEFAULT_BLKSZ, 0, &bdev);
if (ret) {
debug("Cannot create block device\n");
return ret;
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 31cfda2..d96db7a 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -19,6 +19,7 @@
#include <part.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <power/regulator.h>
#include <malloc.h>
#include <memalign.h>
@@ -2775,9 +2776,10 @@
{
#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
if (mmc->vmmc_supply) {
- int ret = regulator_set_enable(mmc->vmmc_supply, true);
+ int ret = regulator_set_enable_if_allowed(mmc->vmmc_supply,
+ true);
- if (ret && ret != -EACCES) {
+ if (ret && ret != -ENOSYS) {
printf("Error enabling VMMC supply : %d\n", ret);
return ret;
}
@@ -2791,9 +2793,10 @@
mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
if (mmc->vmmc_supply) {
- int ret = regulator_set_enable(mmc->vmmc_supply, false);
+ int ret = regulator_set_enable_if_allowed(mmc->vmmc_supply,
+ false);
- if (ret && ret != -EACCES) {
+ if (ret && ret != -ENOSYS) {
pr_debug("Error disabling VMMC supply : %d\n", ret);
return ret;
}
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index b206b0a..d21a30c 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -20,6 +20,7 @@
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/iopoll.h>
+#include <linux/printk.h>
/* MSDC_CFG */
#define MSDC_CFG_HS400_CK_MODE_EXT BIT(22)
diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c
index 9fb7044..4d163cc 100644
--- a/drivers/mmc/pci_mmc.c
+++ b/drivers/mmc/pci_mmc.c
@@ -50,8 +50,8 @@
desc = mmc_get_blk_desc(&plat->mmc);
desc->removable = !(plat->cfg.host_caps & MMC_CAP_NONREMOVABLE);
- host->ioaddr = (void *)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE,
- PCI_REGION_MEM);
+ host->ioaddr = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
+ PCI_REGION_TYPE, PCI_REGION_MEM);
host->name = dev->name;
host->cd_gpio = priv->cd_gpio;
host->mmc = &plat->mmc;
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 8e716f7..97aaf1e 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -3,7 +3,6 @@
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/
-#include <common.h>
#include <bouncebuf.h>
#include <clk.h>
#include <fdtdec.h>
@@ -20,6 +19,7 @@
#include <linux/io.h>
#include <linux/sizes.h>
#include <power/regulator.h>
+#include <reset.h>
#include <asm/unaligned.h>
#include "tmio-common.h"
@@ -318,7 +318,7 @@
RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
}
-static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
+static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv, bool clk_disable)
{
u32 reg;
@@ -350,6 +350,12 @@
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
+
+ if (clk_disable) {
+ reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
+ reg &= ~TMIO_SD_CLKCTL_SCLKEN;
+ tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
+ }
}
static int renesas_sdhi_hs400(struct udevice *dev)
@@ -629,7 +635,7 @@
out:
if (ret < 0) {
dev_warn(dev, "Tuning procedure failed\n");
- renesas_sdhi_reset_tuning(priv);
+ renesas_sdhi_reset_tuning(priv, true);
}
return ret;
@@ -668,7 +674,7 @@
(mmc->selected_mode != UHS_SDR104) &&
(mmc->selected_mode != MMC_HS_200) &&
(mmc->selected_mode != MMC_HS_400)) {
- renesas_sdhi_reset_tuning(priv);
+ renesas_sdhi_reset_tuning(priv, mmc->clk_disable);
}
#endif
@@ -958,17 +964,87 @@
priv->needs_clkh_fallback = false;
}
+static int rzg2l_sdhi_setup(struct udevice *dev)
+{
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
+ struct clk imclk2, aclk;
+ struct reset_ctl rst;
+ int ret;
+
+ /*
+ * On members of the RZ/G2L SoC family, we need to enable
+ * additional chip detect and bus clocks, then release the SDHI
+ * module from reset.
+ */
+ ret = clk_get_by_name(dev, "cd", &imclk2);
+ if (ret < 0) {
+ dev_err(dev, "failed to get imclk2 (chip detect clk)\n");
+ goto err_get_imclk2;
+ }
+
+ ret = clk_get_by_name(dev, "aclk", &aclk);
+ if (ret < 0) {
+ dev_err(dev, "failed to get aclk\n");
+ goto err_get_aclk;
+ }
+
+ ret = clk_enable(&imclk2);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable imclk2 (chip detect clk)\n");
+ goto err_imclk2;
+ }
+
+ ret = clk_enable(&aclk);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable aclk\n");
+ goto err_aclk;
+ }
+
+ ret = reset_get_by_index(dev, 0, &rst);
+ if (ret < 0) {
+ dev_err(dev, "failed to get reset line\n");
+ goto err_get_reset;
+ }
+
+ ret = reset_deassert(&rst);
+ if (ret < 0) {
+ dev_err(dev, "failed to de-assert reset line\n");
+ goto err_reset;
+ }
+
+ ret = tmio_sd_probe(dev, priv->quirks);
+ if (ret)
+ goto err_tmio_probe;
+
+ return 0;
+
+err_tmio_probe:
+ reset_assert(&rst);
+err_reset:
+ reset_free(&rst);
+err_get_reset:
+ clk_disable(&aclk);
+err_aclk:
+ clk_disable(&imclk2);
+err_imclk2:
+ clk_free(&aclk);
+err_get_aclk:
+ clk_free(&imclk2);
+err_get_imclk2:
+ return ret;
+}
+
static int renesas_sdhi_probe(struct udevice *dev)
{
struct tmio_sd_priv *priv = dev_get_priv(dev);
- u32 quirks = dev_get_driver_data(dev);
struct fdt_resource reg_res;
DECLARE_GLOBAL_DATA_PTR;
int ret;
priv->clk_get_rate = renesas_sdhi_clk_get_rate;
- if (quirks == RENESAS_GEN2_QUIRKS) {
+ priv->quirks = dev_get_driver_data(dev);
+ if (priv->quirks == RENESAS_GEN2_QUIRKS) {
ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
"reg", 0, ®_res);
if (ret < 0) {
@@ -978,7 +1054,7 @@
}
if (fdt_resource_size(®_res) == 0x100)
- quirks |= TMIO_SD_CAP_16BIT;
+ priv->quirks |= TMIO_SD_CAP_16BIT;
}
ret = clk_get_by_index(dev, 0, &priv->clk);
@@ -1012,8 +1088,10 @@
goto err_clkh;
}
- priv->quirks = quirks;
- ret = tmio_sd_probe(dev, quirks);
+ if (device_is_compatible(dev, "renesas,sdhi-r9a07g044"))
+ ret = rzg2l_sdhi_setup(dev);
+ else
+ ret = tmio_sd_probe(dev, priv->quirks);
if (ret)
goto err_tmio_probe;
@@ -1023,7 +1101,7 @@
CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
if (priv->caps & TMIO_SD_CAP_RCAR_UHS)
- renesas_sdhi_reset_tuning(priv);
+ renesas_sdhi_reset_tuning(priv, true);
#endif
return 0;
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 9cbe126..0178ed8 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -19,6 +19,7 @@
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
+#include <linux/printk.h>
#include <phys2bus.h>
#include <power/regulator.h>
@@ -305,14 +306,19 @@
if (stat & SDHCI_INT_ERROR)
break;
- if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
- if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
+ if (host->quirks & SDHCI_QUIRK_BROKEN_R1B &&
+ cmd->resp_type & MMC_RSP_BUSY && !data) {
+ unsigned int state =
+ sdhci_readl(host, SDHCI_PRESENT_STATE);
+
+ if (!(state & SDHCI_DAT_ACTIVE))
return 0;
- } else {
- printf("%s: Timeout for status update!\n",
- __func__);
- return -ETIMEDOUT;
- }
+ }
+
+ if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
+ printf("%s: Timeout for status update: %08x %08x\n",
+ __func__, stat, mask);
+ return -ETIMEDOUT;
}
} while ((stat & mask) != mask);
diff --git a/drivers/mmc/sh_sdhi.c b/drivers/mmc/sh_sdhi.c
deleted file mode 100644
index 3ce7cbf..0000000
--- a/drivers/mmc/sh_sdhi.c
+++ /dev/null
@@ -1,910 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * drivers/mmc/sh_sdhi.c
- *
- * SD/MMC driver for Renesas rmobile ARM SoCs.
- *
- * Copyright (C) 2011,2013-2017 Renesas Electronics Corporation
- * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- * Copyright (C) 2008-2009 Renesas Solutions Corp.
- */
-
-#include <common.h>
-#include <log.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <dm.h>
-#include <part.h>
-#include <dm/device_compat.h>
-#include <linux/bitops.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/compat.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-#include <asm/arch/rmobile.h>
-#include <asm/arch/sh_sdhi.h>
-#include <asm/global_data.h>
-#include <clk.h>
-
-#define DRIVER_NAME "sh-sdhi"
-
-struct sh_sdhi_host {
- void __iomem *addr;
- int ch;
- int bus_shift;
- unsigned long quirks;
- unsigned char wait_int;
- unsigned char sd_error;
- unsigned char detect_waiting;
- unsigned char app_cmd;
-};
-
-static inline void sh_sdhi_writeq(struct sh_sdhi_host *host, int reg, u64 val)
-{
- writeq(val, host->addr + (reg << host->bus_shift));
-}
-
-static inline u64 sh_sdhi_readq(struct sh_sdhi_host *host, int reg)
-{
- return readq(host->addr + (reg << host->bus_shift));
-}
-
-static inline void sh_sdhi_writew(struct sh_sdhi_host *host, int reg, u16 val)
-{
- writew(val, host->addr + (reg << host->bus_shift));
-}
-
-static inline u16 sh_sdhi_readw(struct sh_sdhi_host *host, int reg)
-{
- return readw(host->addr + (reg << host->bus_shift));
-}
-
-static void sh_sdhi_detect(struct sh_sdhi_host *host)
-{
- sh_sdhi_writew(host, SDHI_OPTION,
- OPT_BUS_WIDTH_1 | sh_sdhi_readw(host, SDHI_OPTION));
-
- host->detect_waiting = 0;
-}
-
-static int sh_sdhi_intr(void *dev_id)
-{
- struct sh_sdhi_host *host = dev_id;
- int state1 = 0, state2 = 0;
-
- state1 = sh_sdhi_readw(host, SDHI_INFO1);
- state2 = sh_sdhi_readw(host, SDHI_INFO2);
-
- debug("%s: state1 = %x, state2 = %x\n", __func__, state1, state2);
-
- /* CARD Insert */
- if (state1 & INFO1_CARD_IN) {
- sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_CARD_IN);
- if (!host->detect_waiting) {
- host->detect_waiting = 1;
- sh_sdhi_detect(host);
- }
- sh_sdhi_writew(host, SDHI_INFO1_MASK, INFO1M_RESP_END |
- INFO1M_ACCESS_END | INFO1M_CARD_IN |
- INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN);
- return -EAGAIN;
- }
- /* CARD Removal */
- if (state1 & INFO1_CARD_RE) {
- sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_CARD_RE);
- if (!host->detect_waiting) {
- host->detect_waiting = 1;
- sh_sdhi_detect(host);
- }
- sh_sdhi_writew(host, SDHI_INFO1_MASK, INFO1M_RESP_END |
- INFO1M_ACCESS_END | INFO1M_CARD_RE |
- INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN);
- sh_sdhi_writew(host, SDHI_SDIO_INFO1_MASK, SDIO_INFO1M_ON);
- sh_sdhi_writew(host, SDHI_SDIO_MODE, SDIO_MODE_OFF);
- return -EAGAIN;
- }
-
- if (state2 & INFO2_ALL_ERR) {
- sh_sdhi_writew(host, SDHI_INFO2,
- (unsigned short)~(INFO2_ALL_ERR));
- sh_sdhi_writew(host, SDHI_INFO2_MASK,
- INFO2M_ALL_ERR |
- sh_sdhi_readw(host, SDHI_INFO2_MASK));
- host->sd_error = 1;
- host->wait_int = 1;
- return 0;
- }
- /* Respons End */
- if (state1 & INFO1_RESP_END) {
- sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_RESP_END);
- sh_sdhi_writew(host, SDHI_INFO1_MASK,
- INFO1M_RESP_END |
- sh_sdhi_readw(host, SDHI_INFO1_MASK));
- host->wait_int = 1;
- return 0;
- }
- /* SD_BUF Read Enable */
- if (state2 & INFO2_BRE_ENABLE) {
- sh_sdhi_writew(host, SDHI_INFO2, ~INFO2_BRE_ENABLE);
- sh_sdhi_writew(host, SDHI_INFO2_MASK,
- INFO2M_BRE_ENABLE | INFO2M_BUF_ILL_READ |
- sh_sdhi_readw(host, SDHI_INFO2_MASK));
- host->wait_int = 1;
- return 0;
- }
- /* SD_BUF Write Enable */
- if (state2 & INFO2_BWE_ENABLE) {
- sh_sdhi_writew(host, SDHI_INFO2, ~INFO2_BWE_ENABLE);
- sh_sdhi_writew(host, SDHI_INFO2_MASK,
- INFO2_BWE_ENABLE | INFO2M_BUF_ILL_WRITE |
- sh_sdhi_readw(host, SDHI_INFO2_MASK));
- host->wait_int = 1;
- return 0;
- }
- /* Access End */
- if (state1 & INFO1_ACCESS_END) {
- sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_ACCESS_END);
- sh_sdhi_writew(host, SDHI_INFO1_MASK,
- INFO1_ACCESS_END |
- sh_sdhi_readw(host, SDHI_INFO1_MASK));
- host->wait_int = 1;
- return 0;
- }
- return -EAGAIN;
-}
-
-static int sh_sdhi_wait_interrupt_flag(struct sh_sdhi_host *host)
-{
- int timeout = 10000000;
-
- while (1) {
- timeout--;
- if (timeout < 0) {
- debug(DRIVER_NAME": %s timeout\n", __func__);
- return 0;
- }
-
- if (!sh_sdhi_intr(host))
- break;
-
- udelay(1); /* 1 usec */
- }
-
- return 1; /* Return value: NOT 0 = complete waiting */
-}
-
-static int sh_sdhi_clock_control(struct sh_sdhi_host *host, unsigned long clk)
-{
- u32 clkdiv, i, timeout;
-
- if (sh_sdhi_readw(host, SDHI_INFO2) & (1 << 14)) {
- printf(DRIVER_NAME": Busy state ! Cannot change the clock\n");
- return -EBUSY;
- }
-
- sh_sdhi_writew(host, SDHI_CLK_CTRL,
- ~CLK_ENABLE & sh_sdhi_readw(host, SDHI_CLK_CTRL));
-
- if (clk == 0)
- return -EIO;
-
- clkdiv = 0x80;
- i = CONFIG_SH_SDHI_FREQ >> (0x8 + 1);
- for (; clkdiv && clk >= (i << 1); (clkdiv >>= 1))
- i <<= 1;
-
- sh_sdhi_writew(host, SDHI_CLK_CTRL, clkdiv);
-
- timeout = 100000;
- /* Waiting for SD Bus busy to be cleared */
- while (timeout--) {
- if ((sh_sdhi_readw(host, SDHI_INFO2) & 0x2000))
- break;
- }
-
- if (timeout)
- sh_sdhi_writew(host, SDHI_CLK_CTRL,
- CLK_ENABLE | sh_sdhi_readw(host, SDHI_CLK_CTRL));
- else
- return -EBUSY;
-
- return 0;
-}
-
-static int sh_sdhi_sync_reset(struct sh_sdhi_host *host)
-{
- u32 timeout;
- sh_sdhi_writew(host, SDHI_SOFT_RST, SOFT_RST_ON);
- sh_sdhi_writew(host, SDHI_SOFT_RST, SOFT_RST_OFF);
- sh_sdhi_writew(host, SDHI_CLK_CTRL,
- CLK_ENABLE | sh_sdhi_readw(host, SDHI_CLK_CTRL));
-
- timeout = 100000;
- while (timeout--) {
- if (!(sh_sdhi_readw(host, SDHI_INFO2) & INFO2_CBUSY))
- break;
- udelay(100);
- }
-
- if (!timeout)
- return -EBUSY;
-
- if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF)
- sh_sdhi_writew(host, SDHI_HOST_MODE, 1);
-
- return 0;
-}
-
-static int sh_sdhi_error_manage(struct sh_sdhi_host *host)
-{
- unsigned short e_state1, e_state2;
- int ret;
-
- host->sd_error = 0;
- host->wait_int = 0;
-
- e_state1 = sh_sdhi_readw(host, SDHI_ERR_STS1);
- e_state2 = sh_sdhi_readw(host, SDHI_ERR_STS2);
- if (e_state2 & ERR_STS2_SYS_ERROR) {
- if (e_state2 & ERR_STS2_RES_STOP_TIMEOUT)
- ret = -ETIMEDOUT;
- else
- ret = -EILSEQ;
- debug("%s: ERR_STS2 = %04x\n",
- DRIVER_NAME, sh_sdhi_readw(host, SDHI_ERR_STS2));
- sh_sdhi_sync_reset(host);
-
- sh_sdhi_writew(host, SDHI_INFO1_MASK,
- INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN);
- return ret;
- }
- if (e_state1 & ERR_STS1_CRC_ERROR || e_state1 & ERR_STS1_CMD_ERROR)
- ret = -EILSEQ;
- else
- ret = -ETIMEDOUT;
-
- debug("%s: ERR_STS1 = %04x\n",
- DRIVER_NAME, sh_sdhi_readw(host, SDHI_ERR_STS1));
- sh_sdhi_sync_reset(host);
- sh_sdhi_writew(host, SDHI_INFO1_MASK,
- INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN);
- return ret;
-}
-
-static int sh_sdhi_single_read(struct sh_sdhi_host *host, struct mmc_data *data)
-{
- long time;
- unsigned short blocksize, i;
- unsigned short *p = (unsigned short *)data->dest;
- u64 *q = (u64 *)data->dest;
-
- if ((unsigned long)p & 0x00000001) {
- debug(DRIVER_NAME": %s: The data pointer is unaligned.",
- __func__);
- return -EIO;
- }
-
- host->wait_int = 0;
- sh_sdhi_writew(host, SDHI_INFO2_MASK,
- ~(INFO2M_BRE_ENABLE | INFO2M_BUF_ILL_READ) &
- sh_sdhi_readw(host, SDHI_INFO2_MASK));
- sh_sdhi_writew(host, SDHI_INFO1_MASK,
- ~INFO1M_ACCESS_END &
- sh_sdhi_readw(host, SDHI_INFO1_MASK));
- time = sh_sdhi_wait_interrupt_flag(host);
- if (time == 0 || host->sd_error != 0)
- return sh_sdhi_error_manage(host);
-
- host->wait_int = 0;
- blocksize = sh_sdhi_readw(host, SDHI_SIZE);
- if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
- for (i = 0; i < blocksize / 8; i++)
- *q++ = sh_sdhi_readq(host, SDHI_BUF0);
- else
- for (i = 0; i < blocksize / 2; i++)
- *p++ = sh_sdhi_readw(host, SDHI_BUF0);
-
- time = sh_sdhi_wait_interrupt_flag(host);
- if (time == 0 || host->sd_error != 0)
- return sh_sdhi_error_manage(host);
-
- host->wait_int = 0;
- return 0;
-}
-
-static int sh_sdhi_multi_read(struct sh_sdhi_host *host, struct mmc_data *data)
-{
- long time;
- unsigned short blocksize, i, sec;
- unsigned short *p = (unsigned short *)data->dest;
- u64 *q = (u64 *)data->dest;
-
- if ((unsigned long)p & 0x00000001) {
- debug(DRIVER_NAME": %s: The data pointer is unaligned.",
- __func__);
- return -EIO;
- }
-
- debug("%s: blocks = %d, blocksize = %d\n",
- __func__, data->blocks, data->blocksize);
-
- host->wait_int = 0;
- for (sec = 0; sec < data->blocks; sec++) {
- sh_sdhi_writew(host, SDHI_INFO2_MASK,
- ~(INFO2M_BRE_ENABLE | INFO2M_BUF_ILL_READ) &
- sh_sdhi_readw(host, SDHI_INFO2_MASK));
-
- time = sh_sdhi_wait_interrupt_flag(host);
- if (time == 0 || host->sd_error != 0)
- return sh_sdhi_error_manage(host);
-
- host->wait_int = 0;
- blocksize = sh_sdhi_readw(host, SDHI_SIZE);
- if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
- for (i = 0; i < blocksize / 8; i++)
- *q++ = sh_sdhi_readq(host, SDHI_BUF0);
- else
- for (i = 0; i < blocksize / 2; i++)
- *p++ = sh_sdhi_readw(host, SDHI_BUF0);
- }
-
- return 0;
-}
-
-static int sh_sdhi_single_write(struct sh_sdhi_host *host,
- struct mmc_data *data)
-{
- long time;
- unsigned short blocksize, i;
- const unsigned short *p = (const unsigned short *)data->src;
- const u64 *q = (const u64 *)data->src;
-
- if ((unsigned long)p & 0x00000001) {
- debug(DRIVER_NAME": %s: The data pointer is unaligned.",
- __func__);
- return -EIO;
- }
-
- debug("%s: blocks = %d, blocksize = %d\n",
- __func__, data->blocks, data->blocksize);
-
- host->wait_int = 0;
- sh_sdhi_writew(host, SDHI_INFO2_MASK,
- ~(INFO2M_BWE_ENABLE | INFO2M_BUF_ILL_WRITE) &
- sh_sdhi_readw(host, SDHI_INFO2_MASK));
- sh_sdhi_writew(host, SDHI_INFO1_MASK,
- ~INFO1M_ACCESS_END &
- sh_sdhi_readw(host, SDHI_INFO1_MASK));
-
- time = sh_sdhi_wait_interrupt_flag(host);
- if (time == 0 || host->sd_error != 0)
- return sh_sdhi_error_manage(host);
-
- host->wait_int = 0;
- blocksize = sh_sdhi_readw(host, SDHI_SIZE);
- if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
- for (i = 0; i < blocksize / 8; i++)
- sh_sdhi_writeq(host, SDHI_BUF0, *q++);
- else
- for (i = 0; i < blocksize / 2; i++)
- sh_sdhi_writew(host, SDHI_BUF0, *p++);
-
- time = sh_sdhi_wait_interrupt_flag(host);
- if (time == 0 || host->sd_error != 0)
- return sh_sdhi_error_manage(host);
-
- host->wait_int = 0;
- return 0;
-}
-
-static int sh_sdhi_multi_write(struct sh_sdhi_host *host, struct mmc_data *data)
-{
- long time;
- unsigned short i, sec, blocksize;
- const unsigned short *p = (const unsigned short *)data->src;
- const u64 *q = (const u64 *)data->src;
-
- debug("%s: blocks = %d, blocksize = %d\n",
- __func__, data->blocks, data->blocksize);
-
- host->wait_int = 0;
- for (sec = 0; sec < data->blocks; sec++) {
- sh_sdhi_writew(host, SDHI_INFO2_MASK,
- ~(INFO2M_BWE_ENABLE | INFO2M_BUF_ILL_WRITE) &
- sh_sdhi_readw(host, SDHI_INFO2_MASK));
-
- time = sh_sdhi_wait_interrupt_flag(host);
- if (time == 0 || host->sd_error != 0)
- return sh_sdhi_error_manage(host);
-
- host->wait_int = 0;
- blocksize = sh_sdhi_readw(host, SDHI_SIZE);
- if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
- for (i = 0; i < blocksize / 8; i++)
- sh_sdhi_writeq(host, SDHI_BUF0, *q++);
- else
- for (i = 0; i < blocksize / 2; i++)
- sh_sdhi_writew(host, SDHI_BUF0, *p++);
- }
-
- return 0;
-}
-
-static void sh_sdhi_get_response(struct sh_sdhi_host *host, struct mmc_cmd *cmd)
-{
- unsigned short i, j, cnt = 1;
- unsigned short resp[8];
-
- if (cmd->resp_type & MMC_RSP_136) {
- cnt = 4;
- resp[0] = sh_sdhi_readw(host, SDHI_RSP00);
- resp[1] = sh_sdhi_readw(host, SDHI_RSP01);
- resp[2] = sh_sdhi_readw(host, SDHI_RSP02);
- resp[3] = sh_sdhi_readw(host, SDHI_RSP03);
- resp[4] = sh_sdhi_readw(host, SDHI_RSP04);
- resp[5] = sh_sdhi_readw(host, SDHI_RSP05);
- resp[6] = sh_sdhi_readw(host, SDHI_RSP06);
- resp[7] = sh_sdhi_readw(host, SDHI_RSP07);
-
- /* SDHI REGISTER SPECIFICATION */
- for (i = 7, j = 6; i > 0; i--) {
- resp[i] = (resp[i] << 8) & 0xff00;
- resp[i] |= (resp[j--] >> 8) & 0x00ff;
- }
- resp[0] = (resp[0] << 8) & 0xff00;
- } else {
- resp[0] = sh_sdhi_readw(host, SDHI_RSP00);
- resp[1] = sh_sdhi_readw(host, SDHI_RSP01);
- }
-
-#if defined(__BIG_ENDIAN_BITFIELD)
- if (cnt == 4) {
- cmd->response[0] = (resp[6] << 16) | resp[7];
- cmd->response[1] = (resp[4] << 16) | resp[5];
- cmd->response[2] = (resp[2] << 16) | resp[3];
- cmd->response[3] = (resp[0] << 16) | resp[1];
- } else {
- cmd->response[0] = (resp[0] << 16) | resp[1];
- }
-#else
- if (cnt == 4) {
- cmd->response[0] = (resp[7] << 16) | resp[6];
- cmd->response[1] = (resp[5] << 16) | resp[4];
- cmd->response[2] = (resp[3] << 16) | resp[2];
- cmd->response[3] = (resp[1] << 16) | resp[0];
- } else {
- cmd->response[0] = (resp[1] << 16) | resp[0];
- }
-#endif /* __BIG_ENDIAN_BITFIELD */
-}
-
-static unsigned short sh_sdhi_set_cmd(struct sh_sdhi_host *host,
- struct mmc_data *data, unsigned short opc)
-{
- if (host->app_cmd) {
- if (!data)
- host->app_cmd = 0;
- return opc | BIT(6);
- }
-
- switch (opc) {
- case MMC_CMD_SWITCH:
- return opc | (data ? 0x1c00 : 0x40);
- case MMC_CMD_SEND_EXT_CSD:
- return opc | (data ? 0x1c00 : 0);
- case MMC_CMD_SEND_OP_COND:
- return opc | 0x0700;
- case MMC_CMD_APP_CMD:
- host->app_cmd = 1;
- default:
- return opc;
- }
-}
-
-static unsigned short sh_sdhi_data_trans(struct sh_sdhi_host *host,
- struct mmc_data *data, unsigned short opc)
-{
- if (host->app_cmd) {
- host->app_cmd = 0;
- switch (opc) {
- case SD_CMD_APP_SEND_SCR:
- case SD_CMD_APP_SD_STATUS:
- return sh_sdhi_single_read(host, data);
- default:
- printf(DRIVER_NAME": SD: NOT SUPPORT APP CMD = d'%04d\n",
- opc);
- return -EINVAL;
- }
- } else {
- switch (opc) {
- case MMC_CMD_WRITE_MULTIPLE_BLOCK:
- return sh_sdhi_multi_write(host, data);
- case MMC_CMD_READ_MULTIPLE_BLOCK:
- return sh_sdhi_multi_read(host, data);
- case MMC_CMD_WRITE_SINGLE_BLOCK:
- return sh_sdhi_single_write(host, data);
- case MMC_CMD_READ_SINGLE_BLOCK:
- case MMC_CMD_SWITCH:
- case MMC_CMD_SEND_EXT_CSD:;
- return sh_sdhi_single_read(host, data);
- default:
- printf(DRIVER_NAME": SD: NOT SUPPORT CMD = d'%04d\n", opc);
- return -EINVAL;
- }
- }
-}
-
-static int sh_sdhi_start_cmd(struct sh_sdhi_host *host,
- struct mmc_data *data, struct mmc_cmd *cmd)
-{
- long time;
- unsigned short shcmd, opc = cmd->cmdidx;
- int ret = 0;
- unsigned long timeout;
-
- debug("opc = %d, arg = %x, resp_type = %x\n",
- opc, cmd->cmdarg, cmd->resp_type);
-
- if (opc == MMC_CMD_STOP_TRANSMISSION) {
- /* SDHI sends the STOP command automatically by STOP reg */
- sh_sdhi_writew(host, SDHI_INFO1_MASK, ~INFO1M_ACCESS_END &
- sh_sdhi_readw(host, SDHI_INFO1_MASK));
-
- time = sh_sdhi_wait_interrupt_flag(host);
- if (time == 0 || host->sd_error != 0)
- return sh_sdhi_error_manage(host);
-
- sh_sdhi_get_response(host, cmd);
- return 0;
- }
-
- if (data) {
- if ((opc == MMC_CMD_READ_MULTIPLE_BLOCK) ||
- opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
- sh_sdhi_writew(host, SDHI_STOP, STOP_SEC_ENABLE);
- sh_sdhi_writew(host, SDHI_SECCNT, data->blocks);
- }
- sh_sdhi_writew(host, SDHI_SIZE, data->blocksize);
- }
-
- shcmd = sh_sdhi_set_cmd(host, data, opc);
-
- /*
- * U-Boot cannot use interrupt.
- * So this flag may not be clear by timing
- */
- sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_RESP_END);
-
- sh_sdhi_writew(host, SDHI_INFO1_MASK,
- INFO1M_RESP_END | sh_sdhi_readw(host, SDHI_INFO1_MASK));
- sh_sdhi_writew(host, SDHI_ARG0,
- (unsigned short)(cmd->cmdarg & ARG0_MASK));
- sh_sdhi_writew(host, SDHI_ARG1,
- (unsigned short)((cmd->cmdarg >> 16) & ARG1_MASK));
-
- timeout = 100000;
- /* Waiting for SD Bus busy to be cleared */
- while (timeout--) {
- if ((sh_sdhi_readw(host, SDHI_INFO2) & 0x2000))
- break;
- }
-
- host->wait_int = 0;
- sh_sdhi_writew(host, SDHI_INFO1_MASK,
- ~INFO1M_RESP_END & sh_sdhi_readw(host, SDHI_INFO1_MASK));
- sh_sdhi_writew(host, SDHI_INFO2_MASK,
- ~(INFO2M_CMD_ERROR | INFO2M_CRC_ERROR |
- INFO2M_END_ERROR | INFO2M_TIMEOUT |
- INFO2M_RESP_TIMEOUT | INFO2M_ILA) &
- sh_sdhi_readw(host, SDHI_INFO2_MASK));
-
- sh_sdhi_writew(host, SDHI_CMD, (unsigned short)(shcmd & CMD_MASK));
- time = sh_sdhi_wait_interrupt_flag(host);
- if (!time) {
- host->app_cmd = 0;
- return sh_sdhi_error_manage(host);
- }
-
- if (host->sd_error) {
- switch (cmd->cmdidx) {
- case MMC_CMD_ALL_SEND_CID:
- case MMC_CMD_SELECT_CARD:
- case SD_CMD_SEND_IF_COND:
- case MMC_CMD_APP_CMD:
- ret = -ETIMEDOUT;
- break;
- default:
- debug(DRIVER_NAME": Cmd(d'%d) err\n", opc);
- debug(DRIVER_NAME": cmdidx = %d\n", cmd->cmdidx);
- ret = sh_sdhi_error_manage(host);
- break;
- }
- host->sd_error = 0;
- host->wait_int = 0;
- host->app_cmd = 0;
- return ret;
- }
-
- if (sh_sdhi_readw(host, SDHI_INFO1) & INFO1_RESP_END) {
- host->app_cmd = 0;
- return -EINVAL;
- }
-
- if (host->wait_int) {
- sh_sdhi_get_response(host, cmd);
- host->wait_int = 0;
- }
-
- if (data)
- ret = sh_sdhi_data_trans(host, data, opc);
-
- debug("ret = %d, resp = %08x, %08x, %08x, %08x\n",
- ret, cmd->response[0], cmd->response[1],
- cmd->response[2], cmd->response[3]);
- return ret;
-}
-
-static int sh_sdhi_send_cmd_common(struct sh_sdhi_host *host,
- struct mmc_cmd *cmd, struct mmc_data *data)
-{
- host->sd_error = 0;
-
- return sh_sdhi_start_cmd(host, data, cmd);
-}
-
-static int sh_sdhi_set_ios_common(struct sh_sdhi_host *host, struct mmc *mmc)
-{
- int ret;
-
- ret = sh_sdhi_clock_control(host, mmc->clock);
- if (ret)
- return -EINVAL;
-
- if (mmc->bus_width == 8)
- sh_sdhi_writew(host, SDHI_OPTION,
- OPT_BUS_WIDTH_8 | (~OPT_BUS_WIDTH_M &
- sh_sdhi_readw(host, SDHI_OPTION)));
- else if (mmc->bus_width == 4)
- sh_sdhi_writew(host, SDHI_OPTION,
- OPT_BUS_WIDTH_4 | (~OPT_BUS_WIDTH_M &
- sh_sdhi_readw(host, SDHI_OPTION)));
- else
- sh_sdhi_writew(host, SDHI_OPTION,
- OPT_BUS_WIDTH_1 | (~OPT_BUS_WIDTH_M &
- sh_sdhi_readw(host, SDHI_OPTION)));
-
- debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);
-
- return 0;
-}
-
-static int sh_sdhi_initialize_common(struct sh_sdhi_host *host)
-{
- int ret = sh_sdhi_sync_reset(host);
-
- sh_sdhi_writew(host, SDHI_PORTSEL, USE_1PORT);
-
-#if defined(__BIG_ENDIAN_BITFIELD)
- sh_sdhi_writew(host, SDHI_EXT_SWAP, SET_SWAP);
-#endif
-
- sh_sdhi_writew(host, SDHI_INFO1_MASK, INFO1M_RESP_END |
- INFO1M_ACCESS_END | INFO1M_CARD_RE |
- INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN);
-
- return ret;
-}
-
-#ifndef CONFIG_DM_MMC
-static void *mmc_priv(struct mmc *mmc)
-{
- return (void *)mmc->priv;
-}
-
-static int sh_sdhi_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
- struct mmc_data *data)
-{
- struct sh_sdhi_host *host = mmc_priv(mmc);
-
- return sh_sdhi_send_cmd_common(host, cmd, data);
-}
-
-static int sh_sdhi_set_ios(struct mmc *mmc)
-{
- struct sh_sdhi_host *host = mmc_priv(mmc);
-
- return sh_sdhi_set_ios_common(host, mmc);
-}
-
-static int sh_sdhi_initialize(struct mmc *mmc)
-{
- struct sh_sdhi_host *host = mmc_priv(mmc);
-
- return sh_sdhi_initialize_common(host);
-}
-
-static const struct mmc_ops sh_sdhi_ops = {
- .send_cmd = sh_sdhi_send_cmd,
- .set_ios = sh_sdhi_set_ios,
- .init = sh_sdhi_initialize,
-};
-
-#ifdef CONFIG_RCAR_GEN3
-static struct mmc_config sh_sdhi_cfg = {
- .name = DRIVER_NAME,
- .ops = &sh_sdhi_ops,
- .f_min = CLKDEV_INIT,
- .f_max = CLKDEV_HS_DATA,
- .voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
- .host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HS |
- MMC_MODE_HS_52MHz,
- .part_type = PART_TYPE_DOS,
- .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
-};
-#else
-static struct mmc_config sh_sdhi_cfg = {
- .name = DRIVER_NAME,
- .ops = &sh_sdhi_ops,
- .f_min = CLKDEV_INIT,
- .f_max = CLKDEV_HS_DATA,
- .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- .host_caps = MMC_MODE_4BIT | MMC_MODE_HS,
- .part_type = PART_TYPE_DOS,
- .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
-};
-#endif
-
-int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks)
-{
- int ret = 0;
- struct mmc *mmc;
- struct sh_sdhi_host *host = NULL;
-
- if (ch >= CFG_SYS_SH_SDHI_NR_CHANNEL)
- return -ENODEV;
-
- host = malloc(sizeof(struct sh_sdhi_host));
- if (!host)
- return -ENOMEM;
-
- mmc = mmc_create(&sh_sdhi_cfg, host);
- if (!mmc) {
- ret = -1;
- goto error;
- }
-
- host->ch = ch;
- host->addr = (void __iomem *)addr;
- host->quirks = quirks;
-
- if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
- host->bus_shift = 2;
- else if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF)
- host->bus_shift = 1;
-
- return ret;
-error:
- free(host);
- return ret;
-}
-
-#else
-
-struct sh_sdhi_plat {
- struct mmc_config cfg;
- struct mmc mmc;
-};
-
-int sh_sdhi_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
- struct mmc_data *data)
-{
- struct sh_sdhi_host *host = dev_get_priv(dev);
-
- return sh_sdhi_send_cmd_common(host, cmd, data);
-}
-
-int sh_sdhi_dm_set_ios(struct udevice *dev)
-{
- struct sh_sdhi_host *host = dev_get_priv(dev);
- struct mmc *mmc = mmc_get_mmc_dev(dev);
-
- return sh_sdhi_set_ios_common(host, mmc);
-}
-
-static const struct dm_mmc_ops sh_sdhi_dm_ops = {
- .send_cmd = sh_sdhi_dm_send_cmd,
- .set_ios = sh_sdhi_dm_set_ios,
-};
-
-static int sh_sdhi_dm_bind(struct udevice *dev)
-{
- struct sh_sdhi_plat *plat = dev_get_plat(dev);
-
- return mmc_bind(dev, &plat->mmc, &plat->cfg);
-}
-
-static int sh_sdhi_dm_probe(struct udevice *dev)
-{
- struct sh_sdhi_plat *plat = dev_get_plat(dev);
- struct sh_sdhi_host *host = dev_get_priv(dev);
- struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct clk sh_sdhi_clk;
- const u32 quirks = dev_get_driver_data(dev);
- fdt_addr_t base;
- int ret;
-
- base = dev_read_addr(dev);
- if (base == FDT_ADDR_T_NONE)
- return -EINVAL;
-
- host->addr = devm_ioremap(dev, base, SZ_2K);
- if (!host->addr)
- return -ENOMEM;
-
- ret = clk_get_by_index(dev, 0, &sh_sdhi_clk);
- if (ret) {
- debug("failed to get clock, ret=%d\n", ret);
- return ret;
- }
-
- ret = clk_enable(&sh_sdhi_clk);
- if (ret) {
- debug("failed to enable clock, ret=%d\n", ret);
- return ret;
- }
-
- host->quirks = quirks;
-
- if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
- host->bus_shift = 2;
- else if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF)
- host->bus_shift = 1;
-
- plat->cfg.name = dev->name;
- plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
-
- switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
- 1)) {
- case 8:
- plat->cfg.host_caps |= MMC_MODE_8BIT;
- break;
- case 4:
- plat->cfg.host_caps |= MMC_MODE_4BIT;
- break;
- case 1:
- break;
- default:
- dev_err(dev, "Invalid \"bus-width\" value\n");
- return -EINVAL;
- }
-
- sh_sdhi_initialize_common(host);
-
- plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
- plat->cfg.f_min = CLKDEV_INIT;
- plat->cfg.f_max = CLKDEV_HS_DATA;
- plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
-
- upriv->mmc = &plat->mmc;
-
- return 0;
-}
-
-static const struct udevice_id sh_sdhi_sd_match[] = {
- { .compatible = "renesas,sdhi-r8a7795", .data = SH_SDHI_QUIRK_64BIT_BUF },
- { .compatible = "renesas,sdhi-r8a7796", .data = SH_SDHI_QUIRK_64BIT_BUF },
- { /* sentinel */ }
-};
-
-U_BOOT_DRIVER(sh_sdhi_mmc) = {
- .name = "sh-sdhi-mmc",
- .id = UCLASS_MMC,
- .of_match = sh_sdhi_sd_match,
- .bind = sh_sdhi_dm_bind,
- .probe = sh_sdhi_dm_probe,
- .priv_auto = sizeof(struct sh_sdhi_host),
- .plat_auto = sizeof(struct sh_sdhi_plat),
- .ops = &sh_sdhi_dm_ops,
-};
-#endif
diff --git a/drivers/mmc/sti_sdhci.c b/drivers/mmc/sti_sdhci.c
index 6194768..23a1dd4 100644
--- a/drivers/mmc/sti_sdhci.c
+++ b/drivers/mmc/sti_sdhci.c
@@ -12,6 +12,7 @@
#include <sdhci.h>
#include <asm/arch/sdhci.h>
#include <asm/global_data.h>
+#include <linux/printk.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c
index b68594d..5ff5e1a 100644
--- a/drivers/mmc/stm32_sdmmc2.c
+++ b/drivers/mmc/stm32_sdmmc2.c
@@ -27,6 +27,7 @@
#include <linux/iopoll.h>
#include <power/regulator.h>
#include <watchdog.h>
+#include <linux/printk.h>
struct stm32_sdmmc2_plat {
struct mmc_config cfg;
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 23bc7da..714706d 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -25,8 +25,13 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
+#if !CONFIG_IS_ENABLED(DM_MMC)
#include <asm/arch/mmc.h>
+#endif
#include <linux/delay.h>
+#include <sunxi_gpio.h>
+
+#include "sunxi_mmc.h"
#ifndef CCM_MMC_CTRL_MODE_SEL_NEW
#define CCM_MMC_CTRL_MODE_SEL_NEW 0
@@ -56,6 +61,7 @@
return IS_ENABLED(CONFIG_MACH_SUN50I) ||
IS_ENABLED(CONFIG_MACH_SUN50I_H5) ||
IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
+ IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) ||
IS_ENABLED(CONFIG_MACH_SUN8I_R40);
}
@@ -190,7 +196,7 @@
rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
writel(rval, &priv->reg->clkcr);
-#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
+#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
/* A64 supports calibration of delays on MMC controller and we
* have to set delay of zero before starting calibration.
* Allwinner BSP driver sets a delay only in the case of
@@ -543,7 +549,7 @@
/* config ahb clock */
debug("init mmc %d clock and io\n", sdc_no);
-#if !defined(CONFIG_SUN50I_GEN_H6)
+#if !defined(CONFIG_SUN50I_GEN_H6) && !defined(CONFIG_SUNXI_GEN_NCAT2)
setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
#ifdef CONFIG_SUNXI_GEN_SUN6I
@@ -618,7 +624,7 @@
if (IS_ENABLED(CONFIG_MACH_SUN9I_A80))
return 0x410;
- if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
+ if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
return 0x830;
return 0x88;
@@ -699,6 +705,7 @@
{ .compatible = "allwinner,sun7i-a20-mmc" },
{ .compatible = "allwinner,sun8i-a83t-emmc" },
{ .compatible = "allwinner,sun9i-a80-mmc" },
+ { .compatible = "allwinner,sun20i-d1-mmc" },
{ .compatible = "allwinner,sun50i-a64-mmc" },
{ .compatible = "allwinner,sun50i-a64-emmc" },
{ .compatible = "allwinner,sun50i-h6-mmc" },
diff --git a/drivers/mmc/sunxi_mmc.h b/drivers/mmc/sunxi_mmc.h
new file mode 100644
index 0000000..f4ae5a7
--- /dev/null
+++ b/drivers/mmc/sunxi_mmc.h
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Aaron <leafy.myeh@allwinnertech.com>
+ *
+ * MMC register definition for allwinner sunxi platform.
+ */
+
+#ifndef _SUNXI_MMC_H
+#define _SUNXI_MMC_H
+
+#include <linux/types.h>
+
+struct sunxi_mmc {
+ u32 gctrl; /* 0x00 global control */
+ u32 clkcr; /* 0x04 clock control */
+ u32 timeout; /* 0x08 time out */
+ u32 width; /* 0x0c bus width */
+ u32 blksz; /* 0x10 block size */
+ u32 bytecnt; /* 0x14 byte count */
+ u32 cmd; /* 0x18 command */
+ u32 arg; /* 0x1c argument */
+ u32 resp0; /* 0x20 response 0 */
+ u32 resp1; /* 0x24 response 1 */
+ u32 resp2; /* 0x28 response 2 */
+ u32 resp3; /* 0x2c response 3 */
+ u32 imask; /* 0x30 interrupt mask */
+ u32 mint; /* 0x34 masked interrupt status */
+ u32 rint; /* 0x38 raw interrupt status */
+ u32 status; /* 0x3c status */
+ u32 ftrglevel; /* 0x40 FIFO threshold watermark*/
+ u32 funcsel; /* 0x44 function select */
+ u32 cbcr; /* 0x48 CIU byte count */
+ u32 bbcr; /* 0x4c BIU byte count */
+ u32 dbgc; /* 0x50 debug enable */
+ u32 res0; /* 0x54 reserved */
+ u32 a12a; /* 0x58 Auto command 12 argument */
+ u32 ntsr; /* 0x5c New timing set register */
+ u32 res1[8];
+ u32 dmac; /* 0x80 internal DMA control */
+ u32 dlba; /* 0x84 internal DMA descr list base address */
+ u32 idst; /* 0x88 internal DMA status */
+ u32 idie; /* 0x8c internal DMA interrupt enable */
+ u32 chda; /* 0x90 */
+ u32 cbda; /* 0x94 */
+ u32 res2[26];
+#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
+ u32 res3[17];
+ u32 samp_dl;
+ u32 res4[46];
+#endif
+ u32 fifo; /* 0x100 / 0x200 FIFO access address */
+};
+
+#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17)
+#define SUNXI_MMC_CLK_ENABLE (0x1 << 16)
+#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff)
+
+#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0)
+#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1)
+#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2)
+#define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\
+ SUNXI_MMC_GCTRL_FIFO_RESET|\
+ SUNXI_MMC_GCTRL_DMA_RESET)
+#define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5)
+#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31)
+
+#define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6)
+#define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7)
+#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8)
+#define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9)
+#define SUNXI_MMC_CMD_WRITE (0x1 << 10)
+#define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12)
+#define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13)
+#define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15)
+#define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21)
+#define SUNXI_MMC_CMD_START (0x1 << 31)
+
+#define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1)
+#define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2)
+#define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3)
+#define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4)
+#define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5)
+#define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6)
+#define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7)
+#define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8)
+#define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9)
+#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10)
+#define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11)
+#define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12)
+#define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13)
+#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14)
+#define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15)
+#define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16)
+#define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30)
+#define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31)
+#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \
+ (SUNXI_MMC_RINT_RESP_ERROR | \
+ SUNXI_MMC_RINT_RESP_CRC_ERROR | \
+ SUNXI_MMC_RINT_DATA_CRC_ERROR | \
+ SUNXI_MMC_RINT_RESP_TIMEOUT | \
+ SUNXI_MMC_RINT_DATA_TIMEOUT | \
+ SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \
+ SUNXI_MMC_RINT_FIFO_RUN_ERROR | \
+ SUNXI_MMC_RINT_HARD_WARE_LOCKED | \
+ SUNXI_MMC_RINT_START_BIT_ERROR | \
+ SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */
+#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \
+ (SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \
+ SUNXI_MMC_RINT_DATA_OVER | \
+ SUNXI_MMC_RINT_COMMAND_DONE | \
+ SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE)
+
+#define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0)
+#define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1)
+#define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2)
+#define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3)
+#define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8)
+#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9)
+#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10)
+#define SUNXI_MMC_STATUS_FIFO_LEVEL(reg) (((reg) >> 17) & 0x3fff)
+
+#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31)
+
+#define SUNXI_MMC_IDMAC_RESET (0x1 << 0)
+#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1)
+#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7)
+
+#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0)
+#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1)
+
+#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
+#define SUNXI_MMC_COMMON_RESET (1 << 18)
+
+#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
+
+#endif /* _SUNXI_MMC_H */
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index f76fee3..d507adb 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -37,6 +37,9 @@
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
int mmc_id; /* peripheral id */
+
+ int tap_value;
+ int trim_value;
};
static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
@@ -526,31 +529,6 @@
printf("%s: Warning: Autocal timed out!\n", __func__);
/* TBD: Set CFG2TMC_SDMMC1_PAD_CAL_DRV* regs here */
}
-
-#if defined(CONFIG_TEGRA210)
- u32 tap_value, trim_value;
-
- /* Set tap/trim values for SDMMC1/3 @ <48MHz here */
- val = readl(&priv->reg->venspictl); /* aka VENDOR_SYS_SW_CNTL */
- val &= IO_TRIM_BYPASS_MASK;
- if (id == PERIPH_ID_SDMMC1) {
- tap_value = 4; /* default */
- if (val)
- tap_value = 3;
- trim_value = 2;
- } else { /* SDMMC3 */
- tap_value = 3;
- trim_value = 3;
- }
-
- val = readl(&priv->reg->venclkctl);
- val &= ~TRIM_VAL_MASK;
- val |= (trim_value << TRIM_VAL_SHIFT);
- val &= ~TAP_VAL_MASK;
- val |= (tap_value << TAP_VAL_SHIFT);
- writel(val, &priv->reg->venclkctl);
- debug("%s: VENDOR_CLOCK_CNTRL = 0x%08X\n", __func__, val);
-#endif /* T210 */
#endif /* T30/T210 */
}
@@ -588,6 +566,22 @@
/* Make sure SDIO pads are set up */
tegra_mmc_pad_init(priv);
+
+ if (!IS_ERR_VALUE(priv->tap_value) ||
+ !IS_ERR_VALUE(priv->trim_value)) {
+ u32 val;
+
+ val = readl(&priv->reg->venclkctl);
+
+ val &= ~TRIM_VAL_MASK;
+ val |= (priv->trim_value << TRIM_VAL_SHIFT);
+
+ val &= ~TAP_VAL_MASK;
+ val |= (priv->tap_value << TAP_VAL_SHIFT);
+
+ writel(val, &priv->reg->venclkctl);
+ debug("%s: VENDOR_CLOCK_CNTRL = 0x%08X\n", __func__, val);
+ }
}
static int tegra_mmc_init(struct udevice *dev)
@@ -742,6 +736,14 @@
if (dm_gpio_is_valid(&priv->pwr_gpio))
dm_gpio_set_value(&priv->pwr_gpio, 1);
+ ret = dev_read_u32(dev, "nvidia,default-tap", &priv->tap_value);
+ if (ret)
+ priv->tap_value = ret;
+
+ ret = dev_read_u32(dev, "nvidia,default-trim", &priv->trim_value);
+ if (ret)
+ priv->trim_value = ret;
+
upriv->mmc = &plat->mmc;
return tegra_mmc_init(dev);
diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c
index d1e2681..890c496 100644
--- a/drivers/mmc/tmio-common.c
+++ b/drivers/mmc/tmio-common.c
@@ -122,7 +122,10 @@
long wait = 1000000;
int ret;
- while (!(tmio_sd_readl(priv, reg) & flag)) {
+ while (true) {
+ if (tmio_sd_readl(priv, reg) & flag)
+ return tmio_sd_check_error(dev, cmd);
+
if (wait-- < 0) {
dev_err(dev, "timeout\n");
return -ETIMEDOUT;
@@ -756,7 +759,8 @@
dev_dbg(dev, "version %x\n", priv->version);
if (priv->version >= 0x10) {
priv->caps |= TMIO_SD_CAP_DMA_INTERNAL;
- priv->caps |= TMIO_SD_CAP_DIV1024;
+ if (!(priv->caps & TMIO_SD_CAP_RCAR))
+ priv->caps |= TMIO_SD_CAP_DIV1024;
}
if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c
index 16ac84a..27dbe04 100644
--- a/drivers/mmc/xenon_sdhci.c
+++ b/drivers/mmc/xenon_sdhci.c
@@ -23,6 +23,7 @@
#include <linux/libfdt.h>
#include <malloc.h>
#include <sdhci.h>
+#include <linux/printk.h>
#include <power/regulator.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/mtd/hbmc-am654.c b/drivers/mtd/hbmc-am654.c
index c86e504..8161087 100644
--- a/drivers/mtd/hbmc-am654.c
+++ b/drivers/mtd/hbmc-am654.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
//
-// Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+// Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
// Author: Vignesh Raghavendra <vigneshr@ti.com>
#include <common.h>
diff --git a/drivers/mtd/mtdconcat.c b/drivers/mtd/mtdconcat.c
index af3c476..5123258 100644
--- a/drivers/mtd/mtdconcat.c
+++ b/drivers/mtd/mtdconcat.c
@@ -23,6 +23,7 @@
#include <div64.h>
#include <linux/bug.h>
#include <linux/compat.h>
+#include <linux/printk.h>
#endif
#include <linux/mtd/mtd.h>
diff --git a/drivers/mtd/nand/bbt.c b/drivers/mtd/nand/bbt.c
index 294daee..972aec6 100644
--- a/drivers/mtd/nand/bbt.c
+++ b/drivers/mtd/nand/bbt.c
@@ -16,6 +16,7 @@
#ifndef __UBOOT__
#include <linux/slab.h>
#endif
+#include <linux/printk.h>
/**
* nanddev_bbt_init() - Initialize the BBT (Bad Block Table)
diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c
index 4b9dd6a..f6d9c58 100644
--- a/drivers/mtd/nand/core.c
+++ b/drivers/mtd/nand/core.c
@@ -17,6 +17,7 @@
#endif
#include <linux/bitops.h>
#include <linux/mtd/nand.h>
+#include <linux/printk.h>
/**
* nanddev_isbad() - Check if a block is bad
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index d624589..a13e6f5 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -611,6 +611,14 @@
NFC v800: RK3308, RV1108
NFC v900: PX30, RK3326
+config ROCKCHIP_NAND_SKIP_BBTSCAN
+ bool "Skip the automatic BBT scan with Rockchip NAND controllers"
+ depends on ROCKCHIP_NAND
+ help
+ Skip the automatic BBT scan with the NAND_SKIP_BBTSCAN
+ option when data content is not in MTD format or
+ must remain unchanged.
+
config TEGRA_NAND
bool "Support for NAND controller on Tegra SoCs"
depends on ARCH_TEGRA
diff --git a/drivers/mtd/nand/raw/arasan_nfc.c b/drivers/mtd/nand/raw/arasan_nfc.c
index 5879412..1476640 100644
--- a/drivers/mtd/nand/raw/arasan_nfc.c
+++ b/drivers/mtd/nand/raw/arasan_nfc.c
@@ -18,6 +18,7 @@
#include <asm/arch/sys_proto.h>
#include <dm.h>
#include <nand.h>
+#include <linux/printk.h>
struct nand_config {
u32 page;
diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c
index 950e626..fa962ba 100644
--- a/drivers/mtd/nand/raw/atmel/nand-controller.c
+++ b/drivers/mtd/nand/raw/atmel/nand-controller.c
@@ -1474,7 +1474,6 @@
mtd->dev->parent = nc->dev;
nand->controller = &nc->base;
- nand->controller = &nc->base;
chip->cmd_ctrl = atmel_nand_cmd_ctrl;
chip->read_byte = atmel_nand_read_byte;
diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c
index b7e473c..6b17e74 100644
--- a/drivers/mtd/nand/raw/atmel_nand.c
+++ b/drivers/mtd/nand/raw/atmel_nand.c
@@ -19,6 +19,7 @@
#include <linux/bitops.h>
#include <linux/bug.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <malloc.h>
#include <nand.h>
diff --git a/drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c
index aa095c4..4e6d99f 100644
--- a/drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c
+++ b/drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c
@@ -10,6 +10,7 @@
#include <linux/io.h>
#include <linux/ioport.h>
#include <dm.h>
+#include <linux/printk.h>
#include "brcmnand.h"
diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c
index e4bf193..6164989 100644
--- a/drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c
+++ b/drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c
@@ -9,6 +9,7 @@
#include <linux/io.h>
#include <linux/ioport.h>
#include <dm.h>
+#include <linux/printk.h>
#include "brcmnand.h"
diff --git a/drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c
index 586ea3d..dbd85af 100644
--- a/drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c
+++ b/drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c
@@ -9,6 +9,7 @@
#include <linux/io.h>
#include <linux/ioport.h>
#include <dm.h>
+#include <linux/printk.h>
#include "brcmnand.h"
diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6838_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6838_nand.c
index 85f318b..ef36496 100644
--- a/drivers/mtd/nand/raw/brcmnand/bcm6838_nand.c
+++ b/drivers/mtd/nand/raw/brcmnand/bcm6838_nand.c
@@ -10,6 +10,7 @@
#include <linux/io.h>
#include <linux/ioport.h>
#include <dm.h>
+#include <linux/printk.h>
#include "brcmnand.h"
diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c
index a5e159a..027fdd3 100644
--- a/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c
+++ b/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c
@@ -10,6 +10,7 @@
#include <linux/io.h>
#include <linux/ioport.h>
#include <dm.h>
+#include <linux/printk.h>
#include "brcmnand.h"
diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c
index e4e144b..71bbb82 100644
--- a/drivers/mtd/nand/raw/davinci_nand.c
+++ b/drivers/mtd/nand/raw/davinci_nand.c
@@ -35,6 +35,7 @@
#include <nand.h>
#include <dm/uclass.h>
#include <asm/ti-common/davinci_nand.h>
+#include <linux/printk.h>
/* Definitions for 4-bit hardware ECC */
#define NAND_TIMEOUT 10240
diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
index 2854117..ac2e669 100644
--- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
@@ -28,6 +28,7 @@
#include <nand.h>
#include <asm/arch/clk.h>
#include <asm/arch/sys_proto.h>
+#include <linux/printk.h>
/*
* MLC NAND controller registers.
diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
index 356f8d9..b21a0b9 100644
--- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
@@ -23,6 +23,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/dma.h>
#include <asm/arch/cpu.h>
+#include <linux/printk.h>
struct lpc32xx_nand_slc_regs {
u32 data;
diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c
index 051ded6..dbdc5b0 100644
--- a/drivers/mtd/nand/raw/mxc_nand.c
+++ b/drivers/mtd/nand/raw/mxc_nand.c
@@ -15,6 +15,7 @@
#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/imx-regs.h>
#endif
+#include <linux/printk.h>
#include "mxc_nand.h"
#define DRIVER_NAME "mxc_nand"
diff --git a/drivers/mtd/nand/raw/nand_bch.c b/drivers/mtd/nand/raw/nand_bch.c
index 734d1c6..bb48ebb 100644
--- a/drivers/mtd/nand/raw/nand_bch.c
+++ b/drivers/mtd/nand/raw/nand_bch.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <log.h>
#include <dm/devres.h>
+#include <linux/printk.h>
/*#include <asm/io.h>*/
#include <linux/types.h>
diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c
index d502e96..1d9a6d1 100644
--- a/drivers/mtd/nand/raw/pxa3xx_nand.c
+++ b/drivers/mtd/nand/raw/pxa3xx_nand.c
@@ -22,6 +22,7 @@
#include <asm/arch/cpu.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/rawnand.h>
+#include <linux/printk.h>
#include <linux/types.h>
#include <syscon.h>
#include <regmap.h>
diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c b/drivers/mtd/nand/raw/rockchip_nfc.c
index 274489e..088cc7f 100644
--- a/drivers/mtd/nand/raw/rockchip_nfc.c
+++ b/drivers/mtd/nand/raw/rockchip_nfc.c
@@ -955,6 +955,9 @@
chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;
+ if (IS_ENABLED(CONFIG_ROCKCHIP_NAND_SKIP_BBTSCAN))
+ chip->options |= NAND_SKIP_BBTSCAN;
+
rk_nfc_hw_init(nfc);
ret = nand_scan_ident(mtd, nsels, NULL);
if (ret)
diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
index 69dbb62..64be648 100644
--- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c
+++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
@@ -21,6 +21,7 @@
#include <linux/iopoll.h>
#include <linux/ioport.h>
#include <linux/mtd/rawnand.h>
+#include <linux/printk.h>
/* Bad block marker length */
#define FMC2_BBM_LEN 2
diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c
index c0fa1e3..0b5b74d 100644
--- a/drivers/mtd/nand/raw/sunxi_nand.c
+++ b/drivers/mtd/nand/raw/sunxi_nand.c
@@ -36,6 +36,7 @@
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
+#include <linux/printk.h>
#include <linux/kernel.h>
#include <linux/mtd/mtd.h>
diff --git a/drivers/mtd/nand/raw/tegra_nand.c b/drivers/mtd/nand/raw/tegra_nand.c
index 139d978..6086ecd 100644
--- a/drivers/mtd/nand/raw/tegra_nand.c
+++ b/drivers/mtd/nand/raw/tegra_nand.c
@@ -24,6 +24,7 @@
#include <fdtdec.h>
#include <bouncebuf.h>
#include <dm.h>
+#include <linux/printk.h>
#include "tegra_nand.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/mtd/nand/raw/vf610_nfc.c b/drivers/mtd/nand/raw/vf610_nfc.c
index d4b40e8..d2363a0 100644
--- a/drivers/mtd/nand/raw/vf610_nfc.c
+++ b/drivers/mtd/nand/raw/vf610_nfc.c
@@ -24,6 +24,7 @@
#include <common.h>
#include <malloc.h>
#include <dm/device_compat.h>
+#include <linux/printk.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/rawnand.h>
diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c
index 545fdd7..bacaf13 100644
--- a/drivers/mtd/nand/raw/zynq_nand.c
+++ b/drivers/mtd/nand/raw/zynq_nand.c
@@ -21,6 +21,7 @@
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <dm.h>
+#include <linux/printk.h>
/* The NAND flash driver defines */
#define ZYNQ_NAND_CMD_PHASE 1
diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile
index 6c65b18..3051de4 100644
--- a/drivers/mtd/nand/spi/Makefile
+++ b/drivers/mtd/nand/spi/Makefile
@@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-spinand-objs := core.o gigadevice.o macronix.o micron.o toshiba.o winbond.o
+spinand-objs := core.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index 70d8ae5..597b088 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -17,6 +17,7 @@
#include <linux/mtd/spinand.h>
#include <linux/of.h>
#include <linux/slab.h>
+#include <linux/string.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi-mem.h>
#else
@@ -30,6 +31,7 @@
#include <linux/bitops.h>
#include <linux/bug.h>
#include <linux/mtd/spinand.h>
+#include <linux/printk.h>
#endif
/* SPI NAND index visible in MTD names */
@@ -325,6 +327,13 @@
u16 column = 0;
int ret;
+ /*
+ * Looks like PROGRAM LOAD (AKA write cache) does not necessarily reset
+ * the cache content to 0xFF (depends on vendor implementation), so we
+ * must fill the page cache entirely even if we only want to program
+ * the data portion of the page, otherwise we might corrupt the BBM or
+ * user data previously programmed in OOB area.
+ */
memset(spinand->databuf, 0xff,
nanddev_page_size(nand) +
nanddev_per_page_oobsize(nand));
@@ -451,9 +460,11 @@
return status & STATUS_BUSY ? -ETIMEDOUT : 0;
}
-static int spinand_read_id_op(struct spinand_device *spinand, u8 *buf)
+static int spinand_read_id_op(struct spinand_device *spinand, u8 naddr,
+ u8 ndummy, u8 *buf)
{
- struct spi_mem_op op = SPINAND_READID_OP(0, spinand->scratchbuf,
+ struct spi_mem_op op = SPINAND_READID_OP(naddr, ndummy,
+ spinand->scratchbuf,
SPINAND_MAX_ID_LEN);
int ret;
@@ -595,12 +606,12 @@
if (ret == -EBADMSG) {
ecc_failed = true;
mtd->ecc_stats.failed++;
- ret = 0;
} else {
mtd->ecc_stats.corrected += ret;
max_bitflips = max_t(unsigned int, max_bitflips, ret);
}
+ ret = 0;
ops->retlen += iter.req.datalen;
ops->oobretlen += iter.req.ooblen;
}
@@ -666,16 +677,9 @@
.oobbuf.in = marker,
.mode = MTD_OPS_RAW,
};
- int ret;
- ret = spinand_select_target(spinand, pos->target);
- if (ret)
- return ret;
-
- ret = spinand_read_page(spinand, &req, false);
- if (ret)
- return ret;
-
+ spinand_select_target(spinand, pos->target);
+ spinand_read_page(spinand, &req, false);
if (marker[0] != 0xff || marker[1] != 0xff)
return true;
@@ -719,6 +723,10 @@
if (ret)
return ret;
+ ret = spinand_write_enable_op(spinand);
+ if (ret)
+ return ret;
+
return spinand_write_page(spinand, &req);
}
@@ -807,21 +815,6 @@
return ret;
}
-const struct spi_mem_op *
-spinand_find_supported_op(struct spinand_device *spinand,
- const struct spi_mem_op *ops,
- unsigned int nops)
-{
- unsigned int i;
-
- for (i = 0; i < nops; i++) {
- if (spi_mem_supports_op(spinand->slave, &ops[i]))
- return &ops[i];
- }
-
- return NULL;
-}
-
static const struct nand_ops spinand_ops = {
.erase = spinand_erase,
.markbad = spinand_markbad,
@@ -832,28 +825,67 @@
&gigadevice_spinand_manufacturer,
¯onix_spinand_manufacturer,
µn_spinand_manufacturer,
+ ¶gon_spinand_manufacturer,
&toshiba_spinand_manufacturer,
&winbond_spinand_manufacturer,
};
-static int spinand_manufacturer_detect(struct spinand_device *spinand)
+static int spinand_manufacturer_match(struct spinand_device *spinand,
+ enum spinand_readid_method rdid_method)
{
+ u8 *id = spinand->id.data;
unsigned int i;
int ret;
for (i = 0; i < ARRAY_SIZE(spinand_manufacturers); i++) {
- ret = spinand_manufacturers[i]->ops->detect(spinand);
- if (ret > 0) {
- spinand->manufacturer = spinand_manufacturers[i];
- return 0;
- } else if (ret < 0) {
- return ret;
- }
- }
+ const struct spinand_manufacturer *manufacturer =
+ spinand_manufacturers[i];
+ if (id[0] != manufacturer->id)
+ continue;
+
+ ret = spinand_match_and_init(spinand,
+ manufacturer->chips,
+ manufacturer->nchips,
+ rdid_method);
+ if (ret < 0)
+ continue;
+
+ spinand->manufacturer = manufacturer;
+ return 0;
+ }
return -ENOTSUPP;
}
+static int spinand_id_detect(struct spinand_device *spinand)
+{
+ u8 *id = spinand->id.data;
+ int ret;
+
+ ret = spinand_read_id_op(spinand, 0, 0, id);
+ if (ret)
+ return ret;
+ ret = spinand_manufacturer_match(spinand, SPINAND_READID_METHOD_OPCODE);
+ if (!ret)
+ return 0;
+
+ ret = spinand_read_id_op(spinand, 1, 0, id);
+ if (ret)
+ return ret;
+ ret = spinand_manufacturer_match(spinand,
+ SPINAND_READID_METHOD_OPCODE_ADDR);
+ if (!ret)
+ return 0;
+
+ ret = spinand_read_id_op(spinand, 0, 1, id);
+ if (ret)
+ return ret;
+ ret = spinand_manufacturer_match(spinand,
+ SPINAND_READID_METHOD_OPCODE_DUMMY);
+
+ return ret;
+}
+
static int spinand_manufacturer_init(struct spinand_device *spinand)
{
if (spinand->manufacturer->ops->init)
@@ -909,9 +941,9 @@
* @spinand: SPI NAND object
* @table: SPI NAND device description table
* @table_size: size of the device description table
+ * @rdid_method: read id method to match
*
- * Should be used by SPI NAND manufacturer drivers when they want to find a
- * match between a device ID retrieved through the READ_ID command and an
+ * Match between a device ID retrieved through the READ_ID command and an
* entry in the SPI NAND description table. If a match is found, the spinand
* object will be initialized with information provided by the matching
* spinand_info entry.
@@ -920,8 +952,10 @@
*/
int spinand_match_and_init(struct spinand_device *spinand,
const struct spinand_info *table,
- unsigned int table_size, u8 devid)
+ unsigned int table_size,
+ enum spinand_readid_method rdid_method)
{
+ u8 *id = spinand->id.data;
struct nand_device *nand = spinand_to_nand(spinand);
unsigned int i;
@@ -929,13 +963,17 @@
const struct spinand_info *info = &table[i];
const struct spi_mem_op *op;
- if (devid != info->devid)
+ if (rdid_method != info->devid.method)
+ continue;
+
+ if (memcmp(id + 1, info->devid.id, info->devid.len))
continue;
nand->memorg = table[i].memorg;
nand->eccreq = table[i].eccreq;
spinand->eccinfo = table[i].eccinfo;
spinand->flags = table[i].flags;
+ spinand->id.len = 1 + table[i].devid.len;
spinand->select_target = table[i].select_target;
op = spinand_select_op_variant(spinand,
@@ -971,13 +1009,7 @@
if (ret)
return ret;
- ret = spinand_read_id_op(spinand, spinand->id.data);
- if (ret)
- return ret;
-
- spinand->id.len = SPINAND_MAX_ID_LEN;
-
- ret = spinand_manufacturer_detect(spinand);
+ ret = spinand_id_detect(spinand);
if (ret) {
dev_err(spinand->slave->dev, "unknown raw ID %02x %02x %02x %02x\n",
spinand->id.data[0], spinand->id.data[1],
@@ -1082,11 +1114,11 @@
for (i = 0; i < nand->memorg.ntargets; i++) {
ret = spinand_select_target(spinand, i);
if (ret)
- goto err_free_bufs;
+ goto err_manuf_cleanup;
ret = spinand_lock_block(spinand, BL_ALL_UNLOCKED);
if (ret)
- goto err_free_bufs;
+ goto err_manuf_cleanup;
}
ret = nanddev_init(nand, &spinand_ops, THIS_MODULE);
diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
index a2c9348..f2ecf47 100644
--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -7,13 +7,13 @@
*/
#ifndef __UBOOT__
-#include <malloc.h>
#include <linux/device.h>
#include <linux/kernel.h>
#endif
#include <linux/mtd/spinand.h>
#define SPINAND_MFR_GIGADEVICE 0xC8
+
#define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4)
#define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4)
@@ -22,8 +22,12 @@
#define GD5FXGQXXEXXG_REG_STATUS2 0xf0
-/* Q4 devices, QUADIO: Dummy bytes valid for 1 and 2 GBit variants */
-static SPINAND_OP_VARIANTS(gd5fxgq4_read_cache_variants,
+#define GD5FXGQ4UXFXXG_STATUS_ECC_MASK (7 << 4)
+#define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS (0 << 4)
+#define GD5FXGQ4UXFXXG_STATUS_ECC_1_3_BITFLIPS (1 << 4)
+#define GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR (7 << 4)
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
@@ -31,14 +35,13 @@
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
-/* Q5 devices, QUADIO: Dummy bytes only valid for 1 GBit variants */
-static SPINAND_OP_VARIANTS(gd5f1gq5_read_cache_variants,
- SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
- SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+static SPINAND_OP_VARIANTS(read_cache_variants_f,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
- SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
- SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
- SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
static SPINAND_OP_VARIANTS(write_cache_variants,
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
@@ -48,7 +51,65 @@
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
SPINAND_PROG_LOAD(false, 0, NULL, 0));
-static int gd5fxgqxxexxg_ooblayout_ecc(struct mtd_info *mtd, int section,
+static int gd5fxgq4xa_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (16 * section) + 8;
+ region->length = 8;
+
+ return 0;
+}
+
+static int gd5fxgq4xa_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ if (section) {
+ region->offset = 16 * section;
+ region->length = 8;
+ } else {
+ /* section 0 has one byte reserved for bad block mark */
+ region->offset = 1;
+ region->length = 7;
+ }
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops gd5fxgq4xa_ooblayout = {
+ .ecc = gd5fxgq4xa_ooblayout_ecc,
+ .rfree = gd5fxgq4xa_ooblayout_free,
+};
+
+static int gd5fxgq4xa_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ switch (status & STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS:
+ /* 1-7 bits are flipped. return the maximum. */
+ return 7;
+
+ case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS:
+ return 8;
+
+ case STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static int gd5fxgqx_variant2_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
@@ -60,7 +121,7 @@
return 0;
}
-static int gd5fxgqxxexxg_ooblayout_free(struct mtd_info *mtd, int section,
+static int gd5fxgqx_variant2_ooblayout_free(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
@@ -73,7 +134,42 @@
return 0;
}
-static int gd5fxgq4xexxg_ecc_get_status(struct spinand_device *spinand,
+/* Valid for Q4/Q5 and Q6 (untested) devices */
+static const struct mtd_ooblayout_ops gd5fxgqx_variant2_ooblayout = {
+ .ecc = gd5fxgqx_variant2_ooblayout_ecc,
+ .rfree = gd5fxgqx_variant2_ooblayout_free,
+};
+
+static int gd5fxgq4xc_ooblayout_256_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ if (section)
+ return -ERANGE;
+
+ oobregion->offset = 128;
+ oobregion->length = 128;
+
+ return 0;
+}
+
+static int gd5fxgq4xc_ooblayout_256_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ if (section)
+ return -ERANGE;
+
+ oobregion->offset = 1;
+ oobregion->length = 127;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops gd5fxgq4xc_oob_256_ops = {
+ .ecc = gd5fxgq4xc_ooblayout_256_ecc,
+ .rfree = gd5fxgq4xc_ooblayout_256_free,
+};
+
+static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand,
u8 status)
{
u8 status2;
@@ -152,59 +248,116 @@
return -EINVAL;
}
-static const struct mtd_ooblayout_ops gd5fxgqxxexxg_ooblayout = {
- .ecc = gd5fxgqxxexxg_ooblayout_ecc,
- .rfree = gd5fxgqxxexxg_ooblayout_free,
-};
+static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ switch (status & GD5FXGQ4UXFXXG_STATUS_ECC_MASK) {
+ case GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case GD5FXGQ4UXFXXG_STATUS_ECC_1_3_BITFLIPS:
+ return 3;
+
+ case GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ default: /* (2 << 4) through (6 << 4) are 4-8 corrected errors */
+ return ((status & GD5FXGQ4UXFXXG_STATUS_ECC_MASK) >> 4) + 2;
+ }
+
+ return -EINVAL;
+}
static const struct spinand_info gigadevice_spinand_table[] = {
- SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
- NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+ SPINAND_INFO("GD5F1GQ4xA",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&gd5fxgq4_read_cache_variants,
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
- 0,
- SPINAND_ECCINFO(&gd5fxgqxxexxg_ooblayout,
- gd5fxgq4xexxg_ecc_get_status)),
- SPINAND_INFO("GD5F1GQ5UExxG", 0x51,
- NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
+ gd5fxgq4xa_ecc_get_status)),
+ SPINAND_INFO("GD5F2GQ4xA",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf2),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
+ gd5fxgq4xa_ecc_get_status)),
+ SPINAND_INFO("GD5F4GQ4xA",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf4),
+ NAND_MEMORG(1, 2048, 64, 64, 4096, 80, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
+ gd5fxgq4xa_ecc_get_status)),
+ SPINAND_INFO("GD5F4GQ4RC",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xa4, 0x68),
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops,
+ gd5fxgq4ufxxg_ecc_get_status)),
+ SPINAND_INFO("GD5F4GQ4UC",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb4, 0x68),
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops,
+ gd5fxgq4ufxxg_ecc_get_status)),
+ SPINAND_INFO("GD5F1GQ4UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd1),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F1GQ4UFxxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4ufxxg_ecc_get_status)),
+ SPINAND_INFO("GD5F1GQ5UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(4, 512),
- SPINAND_INFO_OP_VARIANTS(&gd5f1gq5_read_cache_variants,
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
- 0,
- SPINAND_ECCINFO(&gd5fxgqxxexxg_ooblayout,
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
gd5fxgq5xexxg_ecc_get_status)),
};
-static int gigadevice_spinand_detect(struct spinand_device *spinand)
-{
- u8 *id = spinand->id.data;
- int ret;
-
- /*
- * For GD NANDs, There is an address byte needed to shift in before IDs
- * are read out, so the first byte in raw_id is dummy.
- */
- if (id[1] != SPINAND_MFR_GIGADEVICE)
- return 0;
-
- ret = spinand_match_and_init(spinand, gigadevice_spinand_table,
- ARRAY_SIZE(gigadevice_spinand_table),
- id[2]);
- if (ret)
- return ret;
-
- return 1;
-}
-
static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
- .detect = gigadevice_spinand_detect,
};
const struct spinand_manufacturer gigadevice_spinand_manufacturer = {
.id = SPINAND_MFR_GIGADEVICE,
.name = "GigaDevice",
+ .chips = gigadevice_spinand_table,
+ .nchips = ARRAY_SIZE(gigadevice_spinand_table),
.ops = &gigadevice_spinand_manuf_ops,
};
diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c
index 6d643a8..86bffc2 100644
--- a/drivers/mtd/nand/spi/macronix.c
+++ b/drivers/mtd/nand/spi/macronix.c
@@ -6,7 +6,6 @@
*/
#ifndef __UBOOT__
-#include <malloc.h>
#include <linux/device.h>
#include <linux/kernel.h>
#endif
@@ -16,7 +15,6 @@
#define SPINAND_MFR_MACRONIX 0xC2
#define MACRONIX_ECCSR_MASK 0x0F
-
static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
@@ -62,7 +60,6 @@
SPI_MEM_OP_DATA_IN(1, eccsr, 1));
int ret = spi_mem_exec_op(spinand->slave, &op);
-
if (ret)
return ret;
@@ -105,8 +102,9 @@
}
static const struct spinand_info macronix_spinand_table[] = {
- SPINAND_INFO("MX35LF1GE4AB", 0x12,
- NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
+ SPINAND_INFO("MX35LF1GE4AB",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x12),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(4, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
@@ -114,16 +112,18 @@
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
mx35lf1ge4ab_ecc_get_status)),
- SPINAND_INFO("MX35LF2GE4AB", 0x22,
- NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1),
+ SPINAND_INFO("MX35LF2GE4AB",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x22),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
NAND_ECCREQ(4, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
- SPINAND_INFO("MX35UF4GE4AD", 0xb7,
- NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
+ SPINAND_INFO("MX35LF2GE4AD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x26),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
@@ -131,8 +131,9 @@
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
mx35lf1ge4ab_ecc_get_status)),
- SPINAND_INFO("MX35UF2GE4AD", 0xa6,
- NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+ SPINAND_INFO("MX35LF4GE4AD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x37),
+ NAND_MEMORG(1, 4096, 128, 64, 2048, 40, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
@@ -140,8 +141,57 @@
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
mx35lf1ge4ab_ecc_get_status)),
- SPINAND_INFO("MX35UF2GE4AC", 0xa2,
- NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
+ SPINAND_INFO("MX35LF1G24AD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
+ SPINAND_INFO("MX35LF2G24AD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
+ SPINAND_INFO("MX35LF4G24AD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
+ SPINAND_INFO("MX31LF1GE4BC",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x1e),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
+ SPINAND_INFO("MX31UF1GE4BC",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x9e),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
+
+ SPINAND_INFO("MX35LF2G14AC",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x20),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
NAND_ECCREQ(4, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
@@ -149,8 +199,9 @@
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
mx35lf1ge4ab_ecc_get_status)),
- SPINAND_INFO("MX35UF1GE4AD", 0x96,
- NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+ SPINAND_INFO("MX35UF4G24AD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb5),
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
@@ -158,8 +209,89 @@
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
mx35lf1ge4ab_ecc_get_status)),
- SPINAND_INFO("MX35UF1GE4AC", 0x92,
- NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
+ SPINAND_INFO("MX35UF4GE4AD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb7),
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
+ SPINAND_INFO("MX35UF2G14AC",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa0),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
+ SPINAND_INFO("MX35UF2G24AD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa4),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
+ SPINAND_INFO("MX35UF2GE4AD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa6),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
+ SPINAND_INFO("MX35UF2GE4AC",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa2),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
+ SPINAND_INFO("MX35UF1G14AC",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x90),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
+ SPINAND_INFO("MX35UF1G24AD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x94),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
+ SPINAND_INFO("MX35UF1GE4AD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x96),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
+ SPINAND_INFO("MX35UF1GE4AC",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(4, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
@@ -170,33 +302,13 @@
};
-static int macronix_spinand_detect(struct spinand_device *spinand)
-{
- u8 *id = spinand->id.data;
- int ret;
-
- /*
- * Macronix SPI NAND read ID needs a dummy byte, so the first byte in
- * raw_id is garbage.
- */
- if (id[1] != SPINAND_MFR_MACRONIX)
- return 0;
-
- ret = spinand_match_and_init(spinand, macronix_spinand_table,
- ARRAY_SIZE(macronix_spinand_table),
- id[2]);
- if (ret)
- return ret;
-
- return 1;
-}
-
static const struct spinand_manufacturer_ops macronix_spinand_manuf_ops = {
- .detect = macronix_spinand_detect,
};
const struct spinand_manufacturer macronix_spinand_manufacturer = {
.id = SPINAND_MFR_MACRONIX,
.name = "Macronix",
+ .chips = macronix_spinand_table,
+ .nchips = ARRAY_SIZE(macronix_spinand_table),
.ops = ¯onix_spinand_manuf_ops,
};
diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
index 6bacf14..b538213 100644
--- a/drivers/mtd/nand/spi/micron.c
+++ b/drivers/mtd/nand/spi/micron.c
@@ -7,11 +7,9 @@
*/
#ifndef __UBOOT__
-#include <malloc.h>
#include <linux/device.h>
#include <linux/kernel.h>
#endif
-#include <linux/bitops.h>
#include <linux/mtd/spinand.h>
#define SPINAND_MFR_MICRON 0x2c
@@ -32,7 +30,7 @@
#define MICRON_SELECT_DIE(x) ((x) << 6)
-static SPINAND_OP_VARIANTS(read_cache_variants,
+static SPINAND_OP_VARIANTS(quadio_read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
@@ -40,14 +38,27 @@
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
-static SPINAND_OP_VARIANTS(write_cache_variants,
+static SPINAND_OP_VARIANTS(x4_write_cache_variants,
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
SPINAND_PROG_LOAD(true, 0, NULL, 0));
-static SPINAND_OP_VARIANTS(update_cache_variants,
+static SPINAND_OP_VARIANTS(x4_update_cache_variants,
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
SPINAND_PROG_LOAD(false, 0, NULL, 0));
+/* Micron MT29F2G01AAAED Device */
+static SPINAND_OP_VARIANTS(x4_read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(x1_write_cache_variants,
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(x1_update_cache_variants,
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
static int micron_8_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
@@ -78,6 +89,47 @@
.rfree = micron_8_ooblayout_free,
};
+static int micron_4_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ struct spinand_device *spinand = mtd_to_spinand(mtd);
+
+ if (section >= spinand->base.memorg.pagesize /
+ mtd->ecc_step_size)
+ return -ERANGE;
+
+ region->offset = (section * 16) + 8;
+ region->length = 8;
+
+ return 0;
+}
+
+static int micron_4_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ struct spinand_device *spinand = mtd_to_spinand(mtd);
+
+ if (section >= spinand->base.memorg.pagesize /
+ mtd->ecc_step_size)
+ return -ERANGE;
+
+ if (section) {
+ region->offset = 16 * section;
+ region->length = 8;
+ } else {
+ /* section 0 has two bytes reserved for the BBM */
+ region->offset = 2;
+ region->length = 6;
+ }
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops micron_4_ooblayout = {
+ .ecc = micron_4_ooblayout_ecc,
+ .rfree = micron_4_ooblayout_free,
+};
+
static int micron_select_target(struct spinand_device *spinand,
unsigned int target)
{
@@ -120,120 +172,119 @@
static const struct spinand_info micron_spinand_table[] = {
/* M79A 2Gb 3.3V */
- SPINAND_INFO("MT29F2G01ABAGD", 0x24,
- NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
+ SPINAND_INFO("MT29F2G01ABAGD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
+ &x4_write_cache_variants,
+ &x4_update_cache_variants),
0,
SPINAND_ECCINFO(µn_8_ooblayout,
micron_8_ecc_get_status)),
/* M79A 2Gb 1.8V */
- SPINAND_INFO("MT29F2G01ABBGD", 0x25,
- NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
+ SPINAND_INFO("MT29F2G01ABBGD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
+ &x4_write_cache_variants,
+ &x4_update_cache_variants),
0,
SPINAND_ECCINFO(µn_8_ooblayout,
micron_8_ecc_get_status)),
/* M78A 1Gb 3.3V */
- SPINAND_INFO("MT29F1G01ABAFD", 0x14,
- NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+ SPINAND_INFO("MT29F1G01ABAFD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
+ &x4_write_cache_variants,
+ &x4_update_cache_variants),
0,
SPINAND_ECCINFO(µn_8_ooblayout,
micron_8_ecc_get_status)),
/* M78A 1Gb 1.8V */
- SPINAND_INFO("MT29F1G01ABAFD", 0x15,
- NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+ SPINAND_INFO("MT29F1G01ABAFD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
+ &x4_write_cache_variants,
+ &x4_update_cache_variants),
0,
SPINAND_ECCINFO(µn_8_ooblayout,
micron_8_ecc_get_status)),
/* M79A 4Gb 3.3V */
- SPINAND_INFO("MT29F4G01ADAGD", 0x36,
- NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 2),
+ SPINAND_INFO("MT29F4G01ADAGD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x36),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 80, 2, 1, 2),
NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
+ &x4_write_cache_variants,
+ &x4_update_cache_variants),
0,
SPINAND_ECCINFO(µn_8_ooblayout,
micron_8_ecc_get_status),
SPINAND_SELECT_TARGET(micron_select_target)),
/* M70A 4Gb 3.3V */
- SPINAND_INFO("MT29F4G01ABAFD", 0x34,
- NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
+ SPINAND_INFO("MT29F4G01ABAFD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34),
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
+ &x4_write_cache_variants,
+ &x4_update_cache_variants),
SPINAND_HAS_CR_FEAT_BIT,
SPINAND_ECCINFO(µn_8_ooblayout,
micron_8_ecc_get_status)),
/* M70A 4Gb 1.8V */
- SPINAND_INFO("MT29F4G01ABBFD", 0x35,
- NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
+ SPINAND_INFO("MT29F4G01ABBFD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
+ &x4_write_cache_variants,
+ &x4_update_cache_variants),
SPINAND_HAS_CR_FEAT_BIT,
SPINAND_ECCINFO(µn_8_ooblayout,
micron_8_ecc_get_status)),
/* M70A 8Gb 3.3V */
- SPINAND_INFO("MT29F8G01ADAFD", 0x46,
- NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 2),
+ SPINAND_INFO("MT29F8G01ADAFD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x46),
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
+ &x4_write_cache_variants,
+ &x4_update_cache_variants),
SPINAND_HAS_CR_FEAT_BIT,
SPINAND_ECCINFO(µn_8_ooblayout,
micron_8_ecc_get_status),
SPINAND_SELECT_TARGET(micron_select_target)),
/* M70A 8Gb 1.8V */
- SPINAND_INFO("MT29F8G01ADBFD", 0x47,
- NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 2),
+ SPINAND_INFO("MT29F8G01ADBFD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x47),
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
+ &x4_write_cache_variants,
+ &x4_update_cache_variants),
SPINAND_HAS_CR_FEAT_BIT,
SPINAND_ECCINFO(µn_8_ooblayout,
micron_8_ecc_get_status),
SPINAND_SELECT_TARGET(micron_select_target)),
+ /* M69A 2Gb 3.3V */
+ SPINAND_INFO("MT29F2G01AAAED",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x9F),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 80, 2, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&x4_read_cache_variants,
+ &x1_write_cache_variants,
+ &x1_update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(µn_4_ooblayout, NULL)),
};
-static int micron_spinand_detect(struct spinand_device *spinand)
-{
- u8 *id = spinand->id.data;
- int ret;
-
- /*
- * Micron SPI NAND read ID need a dummy byte,
- * so the first byte in raw_id is dummy.
- */
- if (id[1] != SPINAND_MFR_MICRON)
- return 0;
-
- ret = spinand_match_and_init(spinand, micron_spinand_table,
- ARRAY_SIZE(micron_spinand_table), id[2]);
- if (ret)
- return ret;
-
- return 1;
-}
-
static int micron_spinand_init(struct spinand_device *spinand)
{
/*
@@ -248,12 +299,13 @@
}
static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = {
- .detect = micron_spinand_detect,
.init = micron_spinand_init,
};
const struct spinand_manufacturer micron_spinand_manufacturer = {
.id = SPINAND_MFR_MICRON,
.name = "Micron",
+ .chips = micron_spinand_table,
+ .nchips = ARRAY_SIZE(micron_spinand_table),
.ops = µn_spinand_manuf_ops,
};
diff --git a/drivers/mtd/nand/spi/paragon.c b/drivers/mtd/nand/spi/paragon.c
new file mode 100644
index 0000000..0c12393
--- /dev/null
+++ b/drivers/mtd/nand/spi/paragon.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Jeff Kletsky
+ *
+ * Author: Jeff Kletsky <git-commits@allycomm.com>
+ */
+
+#ifndef __UBOOT__
+#include <linux/device.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/mtd/spinand.h>
+
+
+#define SPINAND_MFR_PARAGON 0xa1
+
+
+#define PN26G0XA_STATUS_ECC_BITMASK (3 << 4)
+
+#define PN26G0XA_STATUS_ECC_NONE_DETECTED (0 << 4)
+#define PN26G0XA_STATUS_ECC_1_7_CORRECTED (1 << 4)
+#define PN26G0XA_STATUS_ECC_ERRORED (2 << 4)
+#define PN26G0XA_STATUS_ECC_8_CORRECTED (3 << 4)
+
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+
+static int pn26g0xa_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = 6 + (15 * section); /* 4 BBM + 2 user bytes */
+ region->length = 13;
+
+ return 0;
+}
+
+static int pn26g0xa_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 4)
+ return -ERANGE;
+
+ if (section == 4) {
+ region->offset = 64;
+ region->length = 64;
+ } else {
+ region->offset = 4 + (15 * section);
+ region->length = 2;
+ }
+
+ return 0;
+}
+
+static int pn26g0xa_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ switch (status & PN26G0XA_STATUS_ECC_BITMASK) {
+ case PN26G0XA_STATUS_ECC_NONE_DETECTED:
+ return 0;
+
+ case PN26G0XA_STATUS_ECC_1_7_CORRECTED:
+ return 7; /* Return upper limit by convention */
+
+ case PN26G0XA_STATUS_ECC_8_CORRECTED:
+ return 8;
+
+ case PN26G0XA_STATUS_ECC_ERRORED:
+ return -EBADMSG;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static const struct mtd_ooblayout_ops pn26g0xa_ooblayout = {
+ .ecc = pn26g0xa_ooblayout_ecc,
+ .rfree = pn26g0xa_ooblayout_free,
+};
+
+
+static const struct spinand_info paragon_spinand_table[] = {
+ SPINAND_INFO("PN26G01A",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe1),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 21, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&pn26g0xa_ooblayout,
+ pn26g0xa_ecc_get_status)),
+ SPINAND_INFO("PN26G02A",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe2),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 41, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&pn26g0xa_ooblayout,
+ pn26g0xa_ecc_get_status)),
+};
+
+static const struct spinand_manufacturer_ops paragon_spinand_manuf_ops = {
+};
+
+const struct spinand_manufacturer paragon_spinand_manufacturer = {
+ .id = SPINAND_MFR_PARAGON,
+ .name = "Paragon",
+ .chips = paragon_spinand_table,
+ .nchips = ARRAY_SIZE(paragon_spinand_table),
+ .ops = ¶gon_spinand_manuf_ops,
+};
diff --git a/drivers/mtd/nand/spi/toshiba.c b/drivers/mtd/nand/spi/toshiba.c
index c2cd3b4..b9908e7 100644
--- a/drivers/mtd/nand/spi/toshiba.c
+++ b/drivers/mtd/nand/spi/toshiba.c
@@ -7,13 +7,13 @@
*/
#ifndef __UBOOT__
-#include <malloc.h>
#include <linux/device.h>
#include <linux/kernel.h>
#endif
#include <linux/bug.h>
#include <linux/mtd/spinand.h>
+/* Kioxia is new name of Toshiba memory. */
#define SPINAND_MFR_TOSHIBA 0x98
#define TOSH_STATUS_ECC_HAS_BITFLIPS_T (3 << 4)
@@ -31,7 +31,7 @@
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
SPINAND_PROG_LOAD(false, 0, NULL, 0));
-/**
+/*
* Backward compatibility for 1st generation Serial NAND devices
* which don't support Quad Program Load operation.
*/
@@ -42,7 +42,7 @@
SPINAND_PROG_LOAD(false, 0, NULL, 0));
static int tx58cxgxsxraix_ooblayout_ecc(struct mtd_info *mtd, int section,
- struct mtd_oob_region *region)
+ struct mtd_oob_region *region)
{
if (section > 0)
return -ERANGE;
@@ -54,7 +54,7 @@
}
static int tx58cxgxsxraix_ooblayout_free(struct mtd_info *mtd, int section,
- struct mtd_oob_region *region)
+ struct mtd_oob_region *region)
{
if (section > 0)
return -ERANGE;
@@ -72,7 +72,7 @@
};
static int tx58cxgxsxraix_ecc_get_status(struct spinand_device *spinand,
- u8 status)
+ u8 status)
{
struct nand_device *nand = spinand_to_nand(spinand);
u8 mbf = 0;
@@ -111,8 +111,9 @@
static const struct spinand_info toshiba_spinand_table[] = {
/* 3.3V 1Gb (1st generation) */
- SPINAND_INFO("TC58CVG0S3HRAIG", 0xC2,
- NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+ SPINAND_INFO("TC58CVG0S3HRAIG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xC2),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
@@ -121,8 +122,9 @@
SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
tx58cxgxsxraix_ecc_get_status)),
/* 3.3V 2Gb (1st generation) */
- SPINAND_INFO("TC58CVG1S3HRAIG", 0xCB,
- NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+ SPINAND_INFO("TC58CVG1S3HRAIG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCB),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
@@ -131,8 +133,9 @@
SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
tx58cxgxsxraix_ecc_get_status)),
/* 3.3V 4Gb (1st generation) */
- SPINAND_INFO("TC58CVG2S0HRAIG", 0xCD,
- NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
+ SPINAND_INFO("TC58CVG2S0HRAIG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCD),
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
@@ -141,8 +144,9 @@
SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
tx58cxgxsxraix_ecc_get_status)),
/* 1.8V 1Gb (1st generation) */
- SPINAND_INFO("TC58CYG0S3HRAIG", 0xB2,
- NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+ SPINAND_INFO("TC58CYG0S3HRAIG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
@@ -151,8 +155,9 @@
SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
tx58cxgxsxraix_ecc_get_status)),
/* 1.8V 2Gb (1st generation) */
- SPINAND_INFO("TC58CYG1S3HRAIG", 0xBB,
- NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+ SPINAND_INFO("TC58CYG1S3HRAIG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBB),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
@@ -161,8 +166,9 @@
SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
tx58cxgxsxraix_ecc_get_status)),
/* 1.8V 4Gb (1st generation) */
- SPINAND_INFO("TC58CYG2S0HRAIG", 0xBD,
- NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
+ SPINAND_INFO("TC58CYG2S0HRAIG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBD),
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
@@ -176,8 +182,9 @@
* QE_BIT.
*/
/* 3.3V 1Gb (2nd generation) */
- SPINAND_INFO("TC58CVG0S3HRAIJ", 0xE2,
- NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+ SPINAND_INFO("TC58CVG0S3HRAIJ",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE2),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_x4_variants,
@@ -186,8 +193,9 @@
SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
tx58cxgxsxraix_ecc_get_status)),
/* 3.3V 2Gb (2nd generation) */
- SPINAND_INFO("TC58CVG1S3HRAIJ", 0xEB,
- NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+ SPINAND_INFO("TC58CVG1S3HRAIJ",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xEB),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_x4_variants,
@@ -196,8 +204,9 @@
SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
tx58cxgxsxraix_ecc_get_status)),
/* 3.3V 4Gb (2nd generation) */
- SPINAND_INFO("TC58CVG2S0HRAIJ", 0xED,
- NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
+ SPINAND_INFO("TC58CVG2S0HRAIJ",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xED),
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_x4_variants,
@@ -206,8 +215,9 @@
SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
tx58cxgxsxraix_ecc_get_status)),
/* 3.3V 8Gb (2nd generation) */
- SPINAND_INFO("TH58CVG3S0HRAIJ", 0xE4,
- NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1),
+ SPINAND_INFO("TH58CVG3S0HRAIJ",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4),
+ NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_x4_variants,
@@ -216,8 +226,9 @@
SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
tx58cxgxsxraix_ecc_get_status)),
/* 1.8V 1Gb (2nd generation) */
- SPINAND_INFO("TC58CYG0S3HRAIJ", 0xD2,
- NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+ SPINAND_INFO("TC58CYG0S3HRAIJ",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD2),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_x4_variants,
@@ -226,8 +237,9 @@
SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
tx58cxgxsxraix_ecc_get_status)),
/* 1.8V 2Gb (2nd generation) */
- SPINAND_INFO("TC58CYG1S3HRAIJ", 0xDB,
- NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+ SPINAND_INFO("TC58CYG1S3HRAIJ",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDB),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_x4_variants,
@@ -236,8 +248,9 @@
SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
tx58cxgxsxraix_ecc_get_status)),
/* 1.8V 4Gb (2nd generation) */
- SPINAND_INFO("TC58CYG2S0HRAIJ", 0xDD,
- NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
+ SPINAND_INFO("TC58CYG2S0HRAIJ",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDD),
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_x4_variants,
@@ -246,8 +259,9 @@
SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
tx58cxgxsxraix_ecc_get_status)),
/* 1.8V 8Gb (2nd generation) */
- SPINAND_INFO("TH58CYG3S0HRAIJ", 0xD4,
- NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1),
+ SPINAND_INFO("TH58CYG3S0HRAIJ",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4),
+ NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_x4_variants,
@@ -257,33 +271,13 @@
tx58cxgxsxraix_ecc_get_status)),
};
-static int toshiba_spinand_detect(struct spinand_device *spinand)
-{
- u8 *id = spinand->id.data;
- int ret;
-
- /*
- * Toshiba SPI NAND read ID needs a dummy byte,
- * so the first byte in id is garbage.
- */
- if (id[1] != SPINAND_MFR_TOSHIBA)
- return 0;
-
- ret = spinand_match_and_init(spinand, toshiba_spinand_table,
- ARRAY_SIZE(toshiba_spinand_table),
- id[2]);
- if (ret)
- return ret;
-
- return 1;
-}
-
static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = {
- .detect = toshiba_spinand_detect,
};
const struct spinand_manufacturer toshiba_spinand_manufacturer = {
.id = SPINAND_MFR_TOSHIBA,
.name = "Toshiba",
+ .chips = toshiba_spinand_table,
+ .nchips = ARRAY_SIZE(toshiba_spinand_table),
.ops = &toshiba_spinand_manuf_ops,
};
diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
index c119486..dd4ed25 100644
--- a/drivers/mtd/nand/spi/winbond.c
+++ b/drivers/mtd/nand/spi/winbond.c
@@ -8,11 +8,10 @@
*/
#ifndef __UBOOT__
-#include <malloc.h>
#include <linux/device.h>
#include <linux/kernel.h>
#endif
-#include <linux/bitops.h>
+#include <linux/bug.h>
#include <linux/mtd/spinand.h>
#define SPINAND_MFR_WINBOND 0xEF
@@ -78,9 +77,76 @@
return spi_mem_exec_op(spinand->slave, &op);
}
+static int w25n02kv_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = 64 + (16 * section);
+ region->length = 13;
+
+ return 0;
+}
+
+static int w25n02kv_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (16 * section) + 2;
+ region->length = 14;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops w25n02kv_ooblayout = {
+ .ecc = w25n02kv_ooblayout_ecc,
+ .rfree = w25n02kv_ooblayout_free,
+};
+
+static int w25n02kv_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ struct nand_device *nand = spinand_to_nand(spinand);
+ u8 mbf = 0;
+ struct spi_mem_op op = SPINAND_GET_FEATURE_OP(0x30, &mbf);
+
+ switch (status & STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ case STATUS_ECC_HAS_BITFLIPS:
+ /*
+ * Let's try to retrieve the real maximum number of bitflips
+ * in order to avoid forcing the wear-leveling layer to move
+ * data around if it's not necessary.
+ */
+ if (spi_mem_exec_op(spinand->slave, &op))
+ return nand->eccreq.strength;
+
+ mbf >>= 4;
+
+ if (WARN_ON(mbf > nand->eccreq.strength || !mbf))
+ return nand->eccreq.strength;
+
+ return mbf;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
static const struct spinand_info winbond_spinand_table[] = {
- SPINAND_INFO("W25M02GV", 0xAB,
- NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 2),
+ SPINAND_INFO("W25M02GV",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab, 0x21),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 2),
NAND_ECCREQ(1, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
@@ -88,41 +154,26 @@
0,
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
SPINAND_SELECT_TARGET(w25m02gv_select_target)),
- SPINAND_INFO("W25N01GV", 0xAA,
- NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
+ SPINAND_INFO("W25N01GV",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x21),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(1, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
+ SPINAND_INFO("W25N02KV",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
};
-/**
- * winbond_spinand_detect - initialize device related part in spinand_device
- * struct if it is a Winbond device.
- * @spinand: SPI NAND device structure
- */
-static int winbond_spinand_detect(struct spinand_device *spinand)
-{
- u8 *id = spinand->id.data;
- int ret;
-
- /*
- * Winbond SPI NAND read ID need a dummy byte,
- * so the first byte in raw_id is dummy.
- */
- if (id[1] != SPINAND_MFR_WINBOND)
- return 0;
-
- ret = spinand_match_and_init(spinand, winbond_spinand_table,
- ARRAY_SIZE(winbond_spinand_table), id[2]);
- if (ret)
- return ret;
-
- return 1;
-}
-
static int winbond_spinand_init(struct spinand_device *spinand)
{
struct nand_device *nand = spinand_to_nand(spinand);
@@ -142,12 +193,13 @@
}
static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = {
- .detect = winbond_spinand_detect,
.init = winbond_spinand_init,
};
const struct spinand_manufacturer winbond_spinand_manufacturer = {
.id = SPINAND_MFR_WINBOND,
.name = "Winbond",
+ .chips = winbond_spinand_table,
+ .nchips = ARRAY_SIZE(winbond_spinand_table),
.ops = &winbond_spinand_manuf_ops,
};
diff --git a/drivers/mtd/nvmxip/nvmxip-uclass.c b/drivers/mtd/nvmxip/nvmxip-uclass.c
index 6d8eb17..9a316d1 100644
--- a/drivers/mtd/nvmxip/nvmxip-uclass.c
+++ b/drivers/mtd/nvmxip/nvmxip-uclass.c
@@ -22,27 +22,13 @@
#define DEFAULT_LBA_SZ BIT(DEFAULT_LBA_SHIFT)
-/**
- * nvmxip_post_bind() - post binding treatments
- * @dev: the NVMXIP device
- *
- * Create and probe a child block device.
- *
- * Return:
- *
- * 0 on success. Otherwise, failure
- */
-static int nvmxip_post_bind(struct udevice *udev)
+int nvmxip_probe(struct udevice *udev)
{
int ret;
struct udevice *bdev = NULL;
char bdev_name[NVMXIP_BLKDEV_NAME_SZ + 1];
int devnum;
-#if CONFIG_IS_ENABLED(SANDBOX64)
- sandbox_set_enable_memio(true);
-#endif
-
devnum = uclass_id_count(UCLASS_NVMXIP);
snprintf(bdev_name, NVMXIP_BLKDEV_NAME_SZ, "blk#%d", devnum);
@@ -67,6 +53,12 @@
return 0;
}
+static int nvmxip_post_bind(struct udevice *udev)
+{
+ dev_or_flags(udev, DM_FLAG_PROBE_AFTER_BIND);
+ return 0;
+}
+
UCLASS_DRIVER(nvmxip) = {
.name = "nvmxip",
.id = UCLASS_NVMXIP,
diff --git a/drivers/mtd/nvmxip/nvmxip.c b/drivers/mtd/nvmxip/nvmxip.c
index a359e3b..0bd98d6 100644
--- a/drivers/mtd/nvmxip/nvmxip.c
+++ b/drivers/mtd/nvmxip/nvmxip.c
@@ -16,23 +16,6 @@
#include "nvmxip.h"
/**
- * nvmxip_mmio_rawread() - read from the XIP flash
- * @address: address of the data
- * @value: pointer to where storing the value read
- *
- * Read raw data from the XIP flash.
- *
- * Return:
- *
- * Always return 0.
- */
-static int nvmxip_mmio_rawread(const phys_addr_t address, u64 *value)
-{
- *value = readq(address);
- return 0;
-}
-
-/**
* nvmxip_blk_read() - block device read operation
* @dev: the block device
* @blknr: first block number to read from
@@ -49,15 +32,14 @@
{
struct nvmxip_plat *plat = dev_get_plat(dev->parent);
struct blk_desc *desc = dev_get_uclass_plat(dev);
- /* number of the u64 words to read */
- u32 qwords = (blkcnt * desc->blksz) / sizeof(u64);
+ /* number of bytes to read */
+ u32 size = blkcnt * desc->blksz;
/* physical address of the first block to read */
phys_addr_t blkaddr = plat->phys_base + blknr * desc->blksz;
- u64 *virt_blkaddr;
- u64 *pdst = buffer;
+ void *virt_blkaddr;
uint qdata_idx;
- if (!pdst)
+ if (!buffer)
return -EINVAL;
log_debug("[%s]: reading from blknr: %lu , blkcnt: %lu\n", dev->name, blknr, blkcnt);
@@ -66,12 +48,16 @@
/* assumption: the data is virtually contiguous */
- for (qdata_idx = 0 ; qdata_idx < qwords ; qdata_idx++)
- nvmxip_mmio_rawread((phys_addr_t)(virt_blkaddr + qdata_idx), pdst++);
-
+#if IS_ENABLED(CONFIG_PHYS_64BIT)
+ for (qdata_idx = 0 ; qdata_idx < size; qdata_idx += sizeof(u64))
+ *(u64 *)(buffer + qdata_idx) = readq(virt_blkaddr + qdata_idx);
+#else
+ for (qdata_idx = 0 ; qdata_idx < size; qdata_idx += sizeof(u32))
+ *(u32 *)(buffer + qdata_idx) = readl(virt_blkaddr + qdata_idx);
+#endif
log_debug("[%s]: src[0]: 0x%llx , dst[0]: 0x%llx , src[-1]: 0x%llx , dst[-1]: 0x%llx\n",
dev->name,
- *virt_blkaddr,
+ *(u64 *)virt_blkaddr,
*(u64 *)buffer,
*(u64 *)((u8 *)virt_blkaddr + desc->blksz * blkcnt - sizeof(u64)),
*(u64 *)((u8 *)buffer + desc->blksz * blkcnt - sizeof(u64)));
diff --git a/drivers/mtd/nvmxip/nvmxip_qspi.c b/drivers/mtd/nvmxip/nvmxip_qspi.c
index 7221fd1..4d74711 100644
--- a/drivers/mtd/nvmxip/nvmxip_qspi.c
+++ b/drivers/mtd/nvmxip/nvmxip_qspi.c
@@ -50,8 +50,8 @@
return -EINVAL;
}
- log_debug("[%s]: XIP device base addr: 0x%llx , lba_shift: %d , lbas: %lu\n",
- dev->name, plat->phys_base, plat->lba_shift, plat->lba);
+ log_debug("[%s]: XIP device base addr: 0x%p , lba_shift: %d , lbas: %lu\n",
+ dev->name, (void *)(uintptr_t)plat->phys_base, plat->lba_shift, plat->lba);
return 0;
}
@@ -66,5 +66,6 @@
.id = UCLASS_NVMXIP,
.of_match = nvmxip_qspi_ids,
.of_to_plat = nvmxip_qspi_of_to_plat,
+ .probe = nvmxip_probe,
.plat_auto = sizeof(struct nvmxip_plat),
};
diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c
index 08fe7d4..762b01c 100644
--- a/drivers/mtd/onenand/onenand_base.c
+++ b/drivers/mtd/onenand/onenand_base.c
@@ -26,6 +26,7 @@
#include <linux/bitops.h>
#include <linux/compat.h>
#include <linux/mtd/mtd.h>
+#include <linux/printk.h>
#include "linux/mtd/flashchip.h"
#include <linux/mtd/onenand.h>
diff --git a/drivers/mtd/onenand/onenand_bbt.c b/drivers/mtd/onenand/onenand_bbt.c
index eca9edf..cc1e449 100644
--- a/drivers/mtd/onenand/onenand_bbt.c
+++ b/drivers/mtd/onenand/onenand_bbt.c
@@ -20,6 +20,7 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/onenand.h>
#include <malloc.h>
+#include <linux/printk.h>
#include <linux/errno.h>
diff --git a/drivers/mtd/onenand/samsung.c b/drivers/mtd/onenand/samsung.c
index 657abaa..c415e51 100644
--- a/drivers/mtd/onenand/samsung.c
+++ b/drivers/mtd/onenand/samsung.c
@@ -16,6 +16,7 @@
#include <linux/mtd/onenand.h>
#include <linux/mtd/flashchip.h>
#include <linux/mtd/samsung_onenand.h>
+#include <linux/printk.h>
#include <asm/io.h>
#include <linux/errno.h>
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index a9617c6..abed392 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -82,6 +82,7 @@
config BOOTDEV_SPI_FLASH
bool "SPI Flash bootdev support"
+ depends on BOOTSTD
help
Enable a boot device for SPI flash. This allows reading a script
from SPI flash so that it can be used to boot an Operating System.
@@ -107,7 +108,6 @@
config SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT
bool "Command extension type is INVERT for Software Reset on boot"
- default n
help
Because of SFDP information can not be get before boot.
So define command extension type is INVERT when Software Reset on boot only.
@@ -134,6 +134,13 @@
Bank/Extended address registers are used to access the flash
which has size > 16MiB in 3-byte addressing.
+config SPI_FLASH_LOCK
+ bool "Enable the Locking feature"
+ default y
+ help
+ Enable the SPI flash lock support. By default this is set to y.
+ If you intend not to use the lock support you should say n here.
+
config SPI_FLASH_UNLOCK_ALL
bool "Unlock the entire SPI flash on u-boot startup"
default y
@@ -217,6 +224,11 @@
Add support for various XTX (XTX Technology Limited)
SPI flash chips (XT25xxx).
+config SPI_FLASH_ZBIT
+ bool "ZBIT SPI flash support"
+ help
+ Add support for Zbit Semiconductor Inc. SPI flash chips (ZB25xxx).
+
endif
config SPI_FLASH_USE_4K_SECTORS
diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c
index df1f753..2da0cf0 100644
--- a/drivers/mtd/spi/sf-uclass.c
+++ b/drivers/mtd/spi/sf-uclass.c
@@ -96,22 +96,6 @@
return log_msg_ret("bd", ret);
}
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- struct dm_spi_flash_ops *ops = sf_get_ops(dev);
- static int reloc_done;
-
- if (!reloc_done) {
- if (ops->read)
- ops->read += gd->reloc_off;
- if (ops->write)
- ops->write += gd->reloc_off;
- if (ops->erase)
- ops->erase += gd->reloc_off;
-
- reloc_done++;
- }
-#endif
-
return 0;
}
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 6093277..9a1801b 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -21,6 +21,7 @@
#include <linux/errno.h>
#include <linux/log2.h>
#include <linux/math64.h>
+#include <linux/printk.h>
#include <linux/sizes.h>
#include <linux/bitfield.h>
#include <linux/delay.h>
@@ -1099,6 +1100,7 @@
}
#endif
+#if defined(CONFIG_SPI_FLASH_LOCK)
#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
/* Write status register and ensure bits in mask match written values */
static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
@@ -1386,6 +1388,7 @@
return stm_is_unlocked_sr(nor, ofs, len, status);
}
#endif /* CONFIG_SPI_FLASH_STMICRO */
+#endif
static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
{
@@ -1461,6 +1464,7 @@
return ret;
}
+#if defined(CONFIG_SPI_FLASH_LOCK)
#ifdef CONFIG_SPI_FLASH_SST
/*
* sst26 flash series has its own block protection implementation:
@@ -1729,6 +1733,8 @@
return ret;
}
#endif
+#endif
+
/*
* Write an address range to the nor chip. Data must be written in
* FLASH_PAGESIZE chunks. The address range may be any size provided
@@ -4103,6 +4109,7 @@
mtd->_read = spi_nor_read;
mtd->_write = spi_nor_write;
+#if defined(CONFIG_SPI_FLASH_LOCK)
#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
/* NOR protection support for STmicro/Micron chips and similar */
if (JEDEC_MFR(info) == SNOR_MFR_ST ||
@@ -4126,7 +4133,7 @@
nor->flash_is_unlocked = sst26_is_unlocked;
}
#endif
-
+#endif
if (info->flags & USE_FSR)
nor->flags |= SNOR_F_USE_FSR;
if (info->flags & SPI_NOR_HAS_TB)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 4587215..f86e7ff 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -3,7 +3,7 @@
*
* Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
* Copyright (C) 2016 Jagan Teki <jagan@openedev.com>
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
@@ -249,6 +249,7 @@
{ INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K) },
{ INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K) },
+ { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K) },
{ INFO("mx25u51245g", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
@@ -531,6 +532,7 @@
{ INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("XM25QH64C", 0x204017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("XM25QU128C", 0x204118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
#endif
#ifdef CONFIG_SPI_FLASH_XTX
/* XTX Technology Limited */
@@ -570,5 +572,10 @@
{ INFO("xt25w01g", 0x0b651B, 0, 64 * 1024, 2048,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
#endif
+#ifdef CONFIG_SPI_FLASH_ZBIT
+ /* Zbit Semiconductor Inc. */
+ { INFO("zb25vq128", 0x5e4018, 0, 64 * 1024, 256,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+#endif
{ },
};
diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c
index 7aa24e1..0719fe8 100644
--- a/drivers/mtd/spi/spi-nor-tiny.c
+++ b/drivers/mtd/spi/spi-nor-tiny.c
@@ -16,6 +16,7 @@
#include <linux/errno.h>
#include <linux/log2.h>
#include <linux/math64.h>
+#include <linux/printk.h>
#include <linux/sizes.h>
#include <linux/mtd/mtd.h>
diff --git a/drivers/mtd/ubi/attach.c b/drivers/mtd/ubi/attach.c
index e488caa..2ef8fde 100644
--- a/drivers/mtd/ubi/attach.c
+++ b/drivers/mtd/ubi/attach.c
@@ -81,6 +81,7 @@
#include <div64.h>
#include <linux/bug.h>
#include <linux/err.h>
+#include <linux/printk.h>
#endif
#include <linux/math64.h>
diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index 3ac0b19..a1941b8 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -33,6 +33,7 @@
#else
#include <linux/bug.h>
#include <linux/log2.h>
+#include <linux/printk.h>
#endif
#include <linux/err.h>
#include <ubi_uboot.h>
diff --git a/drivers/mtd/ubi/debug.c b/drivers/mtd/ubi/debug.c
index d2b7ca5..b119cb6 100644
--- a/drivers/mtd/ubi/debug.c
+++ b/drivers/mtd/ubi/debug.c
@@ -8,6 +8,7 @@
#include <hexdump.h>
#include <malloc.h>
#include <ubi_uboot.h>
+#include <linux/printk.h>
#include "ubi.h"
#ifndef __UBOOT__
#include <linux/debugfs.h>
diff --git a/drivers/mtd/ubi/debug.h b/drivers/mtd/ubi/debug.h
index 9c8ce51..2e13ebb 100644
--- a/drivers/mtd/ubi/debug.h
+++ b/drivers/mtd/ubi/debug.h
@@ -17,6 +17,7 @@
#endif
#include <hexdump.h>
+#include <linux/printk.h>
#ifndef __UBOOT__
#define ubi_assert(expr) do { \
diff --git a/drivers/mtd/ubi/ubi.h b/drivers/mtd/ubi/ubi.h
index f449601..1759888 100644
--- a/drivers/mtd/ubi/ubi.h
+++ b/drivers/mtd/ubi/ubi.h
@@ -28,6 +28,7 @@
#include <asm/pgtable.h>
#else
#include <ubi_uboot.h>
+#include <linux/printk.h>
#endif
#include <linux/mtd/mtd.h>
#include <linux/mtd/ubi.h>
diff --git a/drivers/mux/mux-uclass.c b/drivers/mux/mux-uclass.c
index 8870305..c98576c 100644
--- a/drivers/mux/mux-uclass.c
+++ b/drivers/mux/mux-uclass.c
@@ -7,7 +7,7 @@
* Copyright (C) 2017 Axentia Technologies AB
* Author: Peter Rosin <peda@axentia.se>
*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 0ed39a6..ebab4d9 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -225,6 +225,14 @@
The Synopsys Designware Ethernet QOS IP block with the specific
configuration used in IMX soc.
+config DWC_ETH_QOS_ROCKCHIP
+ bool "Synopsys DWC Ethernet QOS device support for Rockchip SoCs"
+ depends on DWC_ETH_QOS
+ select DM_ETH_PHY
+ help
+ The Synopsys Designware Ethernet QOS IP block with specific
+ configuration used in Rockchip SoCs.
+
config DWC_ETH_QOS_STM32
bool "Synopsys DWC Ethernet QOS device support for STM32"
depends on DWC_ETH_QOS
@@ -895,6 +903,23 @@
This Driver support MediaTek Ethernet GMAC
Say Y to enable support for the MediaTek Ethernet GMAC.
+config HIFEMAC_ETH
+ bool "HiSilicon Fast Ethernet Controller"
+ select DM_CLK
+ select DM_RESET
+ select PHYLIB
+ help
+ This driver supports HIFEMAC Ethernet controller found on
+ HiSilicon SoCs.
+
+config HIFEMAC_MDIO
+ bool "HiSilicon Fast Ethernet Controller MDIO interface"
+ depends on DM_MDIO
+ select DM_CLK
+ help
+ This driver supports the internal MDIO interface of HIFEMAC
+ Ethernet controller.
+
config HIGMACV300_ETH
bool "HiSilicon Gigabit Ethernet Controller"
select DM_RESET
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index d4af253..1ce6fea 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -20,6 +20,7 @@
obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
+obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o
obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o
obj-$(CONFIG_E1000) += e1000.o
@@ -46,6 +47,8 @@
obj-$(CONFIG_FTGMAC100) += ftgmac100.o
obj-$(CONFIG_FTMAC100) += ftmac100.o
obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o
+obj-$(CONFIG_HIFEMAC_ETH) += hifemac.o
+obj-$(CONFIG_HIFEMAC_MDIO) += hifemac_mdio.o
obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
obj-$(CONFIG_KSZ9477) += ksz9477.o
diff --git a/drivers/net/bcm-sf2-eth-gmac.c b/drivers/net/bcm-sf2-eth-gmac.c
index 3caf0f3..cbe1e85 100644
--- a/drivers/net/bcm-sf2-eth-gmac.c
+++ b/drivers/net/bcm-sf2-eth-gmac.c
@@ -6,6 +6,7 @@
#ifdef BCM_GMAC_DEBUG
#ifndef DEBUG
#define DEBUG
+#include <linux/printk.h>
#endif
#endif
diff --git a/drivers/net/bcm-sf2-eth.c b/drivers/net/bcm-sf2-eth.c
index 88dc3ab..1524f5c 100644
--- a/drivers/net/bcm-sf2-eth.c
+++ b/drivers/net/bcm-sf2-eth.c
@@ -9,6 +9,7 @@
#include <net.h>
#include <config.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <phy.h>
#include <miiphy.h>
diff --git a/drivers/net/bcm6348-eth.c b/drivers/net/bcm6348-eth.c
index 5317173..72dcd07 100644
--- a/drivers/net/bcm6348-eth.c
+++ b/drivers/net/bcm6348-eth.c
@@ -18,6 +18,7 @@
#include <reset.h>
#include <wait_bit.h>
#include <asm/io.h>
+#include <linux/printk.h>
#define ETH_RX_DESC PKTBUFSRX
#define ETH_MAX_MTU_SIZE 1518
diff --git a/drivers/net/bcm6368-eth.c b/drivers/net/bcm6368-eth.c
index c2a8b9f..fdd938c 100644
--- a/drivers/net/bcm6368-eth.c
+++ b/drivers/net/bcm6368-eth.c
@@ -19,6 +19,7 @@
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#define ETH_PORT_STR "brcm,enetsw-port"
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index e09ca33..a174344 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -19,6 +19,7 @@
#include <net.h>
#include <pci.h>
#include <reset.h>
+#include <phys2bus.h>
#include <asm/cache.h>
#include <dm/device_compat.h>
#include <dm/device-internal.h>
@@ -29,6 +30,7 @@
#include <linux/err.h>
#include <linux/kernel.h>
#include <asm/io.h>
+#include <linux/printk.h>
#include <power/regulator.h>
#include "designware.h"
@@ -231,8 +233,10 @@
for (idx = 0; idx < CFG_TX_DESCR_NUM; idx++) {
desc_p = &desc_table_p[idx];
- desc_p->dmamac_addr = (ulong)&txbuffs[idx * CFG_ETH_BUFSIZE];
- desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
+ desc_p->dmamac_addr = dev_phys_to_bus(priv->dev,
+ (ulong)&txbuffs[idx * CFG_ETH_BUFSIZE]);
+ desc_p->dmamac_next = dev_phys_to_bus(priv->dev,
+ (ulong)&desc_table_p[idx + 1]);
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
@@ -250,14 +254,15 @@
}
/* Correcting the last pointer of the chain */
- desc_p->dmamac_next = (ulong)&desc_table_p[0];
+ desc_p->dmamac_next = dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]);
/* Flush all Tx buffer descriptors at once */
flush_dcache_range((ulong)priv->tx_mac_descrtable,
(ulong)priv->tx_mac_descrtable +
sizeof(priv->tx_mac_descrtable));
- writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
+ writel(dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]),
+ &dma_p->txdesclistaddr);
priv->tx_currdescnum = 0;
}
@@ -279,8 +284,10 @@
for (idx = 0; idx < CFG_RX_DESCR_NUM; idx++) {
desc_p = &desc_table_p[idx];
- desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CFG_ETH_BUFSIZE];
- desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
+ desc_p->dmamac_addr = dev_phys_to_bus(priv->dev,
+ (ulong)&rxbuffs[idx * CFG_ETH_BUFSIZE]);
+ desc_p->dmamac_next = dev_phys_to_bus(priv->dev,
+ (ulong)&desc_table_p[idx + 1]);
desc_p->dmamac_cntl =
(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
@@ -290,14 +297,15 @@
}
/* Correcting the last pointer of the chain */
- desc_p->dmamac_next = (ulong)&desc_table_p[0];
+ desc_p->dmamac_next = dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]);
/* Flush all Rx buffer descriptors at once */
flush_dcache_range((ulong)priv->rx_mac_descrtable,
(ulong)priv->rx_mac_descrtable +
sizeof(priv->rx_mac_descrtable));
- writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
+ writel(dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]),
+ &dma_p->rxdesclistaddr);
priv->rx_currdescnum = 0;
}
@@ -447,7 +455,7 @@
ulong desc_start = (ulong)desc_p;
ulong desc_end = desc_start +
roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
- ulong data_start = desc_p->dmamac_addr;
+ ulong data_start = dev_bus_to_phys(priv->dev, desc_p->dmamac_addr);
ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
/*
* Strictly we only need to invalidate the "txrx_status" field
@@ -514,7 +522,7 @@
ulong desc_start = (ulong)desc_p;
ulong desc_end = desc_start +
roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
- ulong data_start = desc_p->dmamac_addr;
+ ulong data_start = dev_bus_to_phys(priv->dev, desc_p->dmamac_addr);
ulong data_end;
/* Invalidate entire buffer descriptor */
@@ -531,7 +539,8 @@
/* Invalidate received data */
data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
invalidate_dcache_range(data_start, data_end);
- *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
+ *packetp = (uchar *)(ulong)dev_bus_to_phys(priv->dev,
+ desc_p->dmamac_addr);
}
return length;
@@ -756,6 +765,7 @@
goto mdio_err;
}
priv->bus = miiphy_get_dev_by_name(dev->name);
+ priv->dev = dev;
ret = dw_phy_init(priv, dev);
debug("%s, ret=%d\n", __func__, ret);
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index 9da4e90..918a386 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -241,6 +241,7 @@
int clock_count; /* number of clock in clock list */
#endif
+ struct udevice *dev;
struct phy_device *phydev;
struct mii_dev *bus;
};
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 1e92bd9..a4e3698 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -52,6 +52,7 @@
#include <asm/mach-imx/sys_proto.h>
#endif
#include <linux/delay.h>
+#include <linux/printk.h>
#include "dwc_eth_qos.h"
@@ -745,6 +746,7 @@
u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
ulong last_rx_desc;
ulong desc_pad;
+ ulong addr64;
debug("%s(dev=%p):\n", __func__, dev);
@@ -811,6 +813,7 @@
if (!eqos->phy) {
pr_err("phy_connect() failed");
+ ret = -ENODEV;
goto err_stop_resets;
}
@@ -838,6 +841,7 @@
if (!eqos->phy->link) {
pr_err("No link");
+ ret = -EAGAIN;
goto err_shutdown_phy;
}
@@ -1036,25 +1040,25 @@
for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) {
struct eqos_desc *rx_desc = eqos_get_desc(eqos, i, true);
- rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
- (i * EQOS_MAX_PACKET_SIZE));
+
+ addr64 = (ulong)(eqos->rx_dma_buf + (i * EQOS_MAX_PACKET_SIZE));
+ rx_desc->des0 = lower_32_bits(addr64);
+ rx_desc->des1 = upper_32_bits(addr64);
rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
mb();
eqos->config->ops->eqos_flush_desc(rx_desc);
- eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf +
- (i * EQOS_MAX_PACKET_SIZE),
- EQOS_MAX_PACKET_SIZE);
+ eqos->config->ops->eqos_inval_buffer((void *)addr64, EQOS_MAX_PACKET_SIZE);
}
- writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
- writel((ulong)eqos_get_desc(eqos, 0, false),
- &eqos->dma_regs->ch0_txdesc_list_address);
+ addr64 = (ulong)eqos_get_desc(eqos, 0, false);
+ writel(upper_32_bits(addr64), &eqos->dma_regs->ch0_txdesc_list_haddress);
+ writel(lower_32_bits(addr64), &eqos->dma_regs->ch0_txdesc_list_address);
writel(EQOS_DESCRIPTORS_TX - 1,
&eqos->dma_regs->ch0_txdesc_ring_length);
- writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress);
- writel((ulong)eqos_get_desc(eqos, 0, true),
- &eqos->dma_regs->ch0_rxdesc_list_address);
+ addr64 = (ulong)eqos_get_desc(eqos, 0, true);
+ writel(upper_32_bits(addr64), &eqos->dma_regs->ch0_rxdesc_list_haddress);
+ writel(lower_32_bits(addr64), &eqos->dma_regs->ch0_rxdesc_list_address);
writel(EQOS_DESCRIPTORS_RX - 1,
&eqos->dma_regs->ch0_rxdesc_ring_length);
@@ -1159,8 +1163,8 @@
eqos->tx_desc_idx++;
eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX;
- tx_desc->des0 = (ulong)eqos->tx_dma_buf;
- tx_desc->des1 = 0;
+ tx_desc->des0 = lower_32_bits((ulong)eqos->tx_dma_buf);
+ tx_desc->des1 = upper_32_bits((ulong)eqos->tx_dma_buf);
tx_desc->des2 = length;
/*
* Make sure that if HW sees the _OWN write below, it will see all the
@@ -1191,14 +1195,12 @@
struct eqos_desc *rx_desc;
int length;
- debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
-
rx_desc = eqos_get_desc(eqos, eqos->rx_desc_idx, true);
eqos->config->ops->eqos_inval_desc(rx_desc);
- if (rx_desc->des3 & EQOS_DESC3_OWN) {
- debug("%s: RX packet not available\n", __func__);
+ if (rx_desc->des3 & EQOS_DESC3_OWN)
return -EAGAIN;
- }
+
+ debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
*packetp = eqos->rx_dma_buf +
(eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
@@ -1233,14 +1235,17 @@
for (idx = eqos->rx_desc_idx - idx_mask;
idx <= eqos->rx_desc_idx;
idx++) {
+ ulong addr64;
+
rx_desc = eqos_get_desc(eqos, idx, true);
rx_desc->des0 = 0;
+ rx_desc->des1 = 0;
mb();
eqos->config->ops->eqos_flush_desc(rx_desc);
eqos->config->ops->eqos_inval_buffer(packet, length);
- rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
- (idx * EQOS_MAX_PACKET_SIZE));
- rx_desc->des1 = 0;
+ addr64 = (ulong)(eqos->rx_dma_buf + (idx * EQOS_MAX_PACKET_SIZE));
+ rx_desc->des0 = lower_32_bits(addr64);
+ rx_desc->des1 = upper_32_bits(addr64);
rx_desc->des2 = 0;
/*
* Make sure that if HW sees the _OWN write below,
@@ -1314,22 +1319,12 @@
}
debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf);
- eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE);
- if (!eqos->rx_pkt) {
- debug("%s: malloc(rx_pkt) failed\n", __func__);
- ret = -ENOMEM;
- goto err_free_rx_dma_buf;
- }
- debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt);
-
eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf,
EQOS_MAX_PACKET_SIZE * EQOS_DESCRIPTORS_RX);
debug("%s: OK\n", __func__);
return 0;
-err_free_rx_dma_buf:
- free(eqos->rx_dma_buf);
err_free_tx_dma_buf:
free(eqos->tx_dma_buf);
err_free_descs:
@@ -1348,7 +1343,6 @@
debug("%s(dev=%p):\n", __func__, dev);
- free(eqos->rx_pkt);
free(eqos->rx_dma_buf);
free(eqos->tx_dma_buf);
eqos_free_descs(eqos->rx_descs);
@@ -1718,7 +1712,16 @@
.data = (ulong)&eqos_imx_config
},
#endif
-
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_ROCKCHIP)
+ {
+ .compatible = "rockchip,rk3568-gmac",
+ .data = (ulong)&eqos_rockchip_config
+ },
+ {
+ .compatible = "rockchip,rk3588-gmac",
+ .data = (ulong)&eqos_rockchip_config
+ },
+#endif
#if IS_ENABLED(CONFIG_DWC_ETH_QOS_QCOM)
{
.compatible = "qcom,qcs404-ethqos",
@@ -1731,7 +1734,6 @@
.data = (ulong)&eqos_jh7110_config
},
#endif
-
{ }
};
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index a6b719a..e3222e1 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -82,6 +82,7 @@
#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
+#define EQOS_MAC_MDIO_ADDRESS_CR_100_150 1
#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
@@ -273,7 +274,6 @@
unsigned int desc_per_cacheline;
void *tx_dma_buf;
void *rx_dma_buf;
- void *rx_pkt;
bool started;
bool reg_access_ok;
bool clk_ck_enabled;
@@ -288,5 +288,6 @@
int eqos_null_ops(struct udevice *dev);
extern struct eqos_config eqos_imx_config;
+extern struct eqos_config eqos_rockchip_config;
extern struct eqos_config eqos_qcom_config;
extern struct eqos_config eqos_jh7110_config;
diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c
new file mode 100644
index 0000000..834307a
--- /dev/null
+++ b/drivers/net/dwc_eth_qos_rockchip.c
@@ -0,0 +1,531 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright Contributors to the U-Boot project.
+ *
+ * rk_gmac_ops ported from linux drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+ *
+ * Ported code is intentionally left as close as possible with linux counter
+ * part in order to simplify future porting of fixes and support for other SoCs.
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <net.h>
+#include <phy.h>
+#include <regmap.h>
+#include <reset.h>
+#include <syscon.h>
+#include <asm/gpio.h>
+#include <linux/delay.h>
+
+#include "dwc_eth_qos.h"
+
+struct rk_gmac_ops {
+ const char *compatible;
+ int (*set_to_rgmii)(struct udevice *dev,
+ int tx_delay, int rx_delay);
+ int (*set_to_rmii)(struct udevice *dev);
+ int (*set_gmac_speed)(struct udevice *dev);
+ void (*set_clock_selection)(struct udevice *dev, bool enable);
+ u32 regs[3];
+};
+
+struct rockchip_platform_data {
+ struct reset_ctl_bulk resets;
+ const struct rk_gmac_ops *ops;
+ int id;
+ bool clock_input;
+ struct regmap *grf;
+ struct regmap *php_grf;
+};
+
+#define HIWORD_UPDATE(val, mask, shift) \
+ ((val) << (shift) | (mask) << ((shift) + 16))
+
+#define GRF_BIT(nr) (BIT(nr) | BIT((nr) + 16))
+#define GRF_CLR_BIT(nr) (BIT((nr) + 16))
+
+#define RK3568_GRF_GMAC0_CON0 0x0380
+#define RK3568_GRF_GMAC0_CON1 0x0384
+#define RK3568_GRF_GMAC1_CON0 0x0388
+#define RK3568_GRF_GMAC1_CON1 0x038c
+
+/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
+#define RK3568_GMAC_PHY_INTF_SEL_RGMII \
+ (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
+#define RK3568_GMAC_PHY_INTF_SEL_RMII \
+ (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
+#define RK3568_GMAC_FLOW_CTRL GRF_BIT(3)
+#define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
+#define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
+#define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
+#define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
+#define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
+
+/* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
+#define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
+#define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+
+static int rk3568_set_to_rgmii(struct udevice *dev,
+ int tx_delay, int rx_delay)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+ u32 con0, con1;
+
+ con0 = (data->id == 1) ? RK3568_GRF_GMAC1_CON0 :
+ RK3568_GRF_GMAC0_CON0;
+ con1 = (data->id == 1) ? RK3568_GRF_GMAC1_CON1 :
+ RK3568_GRF_GMAC0_CON1;
+
+ regmap_write(data->grf, con0,
+ RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
+
+ regmap_write(data->grf, con1,
+ RK3568_GMAC_PHY_INTF_SEL_RGMII |
+ RK3568_GMAC_RXCLK_DLY_ENABLE |
+ RK3568_GMAC_TXCLK_DLY_ENABLE);
+
+ return 0;
+}
+
+static int rk3568_set_to_rmii(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+ u32 con1;
+
+ con1 = (data->id == 1) ? RK3568_GRF_GMAC1_CON1 :
+ RK3568_GRF_GMAC0_CON1;
+ regmap_write(data->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
+
+ return 0;
+}
+
+static int rk3568_set_gmac_speed(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ ulong rate;
+ int ret;
+
+ switch (eqos->phy->speed) {
+ case SPEED_10:
+ rate = 2500000;
+ break;
+ case SPEED_100:
+ rate = 25000000;
+ break;
+ case SPEED_1000:
+ rate = 125000000;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ ret = clk_set_rate(&eqos->clk_tx, rate);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/* sys_grf */
+#define RK3588_GRF_GMAC_CON7 0x031c
+#define RK3588_GRF_GMAC_CON8 0x0320
+#define RK3588_GRF_GMAC_CON9 0x0324
+
+#define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3)
+#define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3)
+#define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2)
+#define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2)
+
+#define RK3588_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
+#define RK3588_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
+
+/* php_grf */
+#define RK3588_GRF_GMAC_CON0 0x0008
+#define RK3588_GRF_CLK_CON1 0x0070
+
+#define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \
+ (GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6))
+#define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \
+ (GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6))
+
+#define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id))
+#define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id))
+
+#define RK3588_GMAC_CLK_SELET_CRU(id) GRF_BIT(5 * (id) + 4)
+#define RK3588_GMAC_CLK_SELET_IO(id) GRF_CLR_BIT(5 * (id) + 4)
+
+#define RK3588_GMAC_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2)
+#define RK3588_GMAC_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2)
+
+#define RK3588_GMAC_CLK_RGMII_DIV1(id) \
+ (GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3))
+#define RK3588_GMAC_CLK_RGMII_DIV5(id) \
+ (GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
+#define RK3588_GMAC_CLK_RGMII_DIV50(id) \
+ (GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
+
+#define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1)
+#define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1)
+
+static int rk3588_set_to_rgmii(struct udevice *dev,
+ int tx_delay, int rx_delay)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+ u32 offset_con, id = data->id;
+
+ offset_con = data->id == 1 ? RK3588_GRF_GMAC_CON9 :
+ RK3588_GRF_GMAC_CON8;
+
+ regmap_write(data->php_grf, RK3588_GRF_GMAC_CON0,
+ RK3588_GMAC_PHY_INTF_SEL_RGMII(id));
+
+ regmap_write(data->php_grf, RK3588_GRF_CLK_CON1,
+ RK3588_GMAC_CLK_RGMII_MODE(id));
+
+ regmap_write(data->grf, RK3588_GRF_GMAC_CON7,
+ RK3588_GMAC_RXCLK_DLY_ENABLE(id) |
+ RK3588_GMAC_TXCLK_DLY_ENABLE(id));
+
+ regmap_write(data->grf, offset_con,
+ RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3588_GMAC_CLK_TX_DL_CFG(tx_delay));
+
+ return 0;
+}
+
+static int rk3588_set_to_rmii(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+
+ regmap_write(data->php_grf, RK3588_GRF_GMAC_CON0,
+ RK3588_GMAC_PHY_INTF_SEL_RMII(data->id));
+
+ regmap_write(data->php_grf, RK3588_GRF_CLK_CON1,
+ RK3588_GMAC_CLK_RMII_MODE(data->id));
+
+ return 0;
+}
+
+static int rk3588_set_gmac_speed(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+ u32 val = 0, id = data->id;
+
+ switch (eqos->phy->speed) {
+ case SPEED_10:
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
+ val = RK3588_GMAC_CLK_RMII_DIV20(id);
+ else
+ val = RK3588_GMAC_CLK_RGMII_DIV50(id);
+ break;
+ case SPEED_100:
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
+ val = RK3588_GMAC_CLK_RMII_DIV2(id);
+ else
+ val = RK3588_GMAC_CLK_RGMII_DIV5(id);
+ break;
+ case SPEED_1000:
+ if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
+ val = RK3588_GMAC_CLK_RGMII_DIV1(id);
+ else
+ return -EINVAL;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_write(data->php_grf, RK3588_GRF_CLK_CON1, val);
+
+ return 0;
+}
+
+static void rk3588_set_clock_selection(struct udevice *dev, bool enable)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+
+ u32 val = data->clock_input ? RK3588_GMAC_CLK_SELET_IO(data->id) :
+ RK3588_GMAC_CLK_SELET_CRU(data->id);
+
+ val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(data->id) :
+ RK3588_GMAC_CLK_RMII_GATE(data->id);
+
+ regmap_write(data->php_grf, RK3588_GRF_CLK_CON1, val);
+}
+
+static const struct rk_gmac_ops rk_gmac_ops[] = {
+ {
+ .compatible = "rockchip,rk3568-gmac",
+ .set_to_rgmii = rk3568_set_to_rgmii,
+ .set_to_rmii = rk3568_set_to_rmii,
+ .set_gmac_speed = rk3568_set_gmac_speed,
+ .regs = {
+ 0xfe2a0000, /* gmac0 */
+ 0xfe010000, /* gmac1 */
+ 0x0, /* sentinel */
+ },
+ },
+ {
+ .compatible = "rockchip,rk3588-gmac",
+ .set_to_rgmii = rk3588_set_to_rgmii,
+ .set_to_rmii = rk3588_set_to_rmii,
+ .set_gmac_speed = rk3588_set_gmac_speed,
+ .set_clock_selection = rk3588_set_clock_selection,
+ .regs = {
+ 0xfe1b0000, /* gmac0 */
+ 0xfe1c0000, /* gmac1 */
+ 0x0, /* sentinel */
+ },
+ },
+ { }
+};
+
+static const struct rk_gmac_ops *get_rk_gmac_ops(struct udevice *dev)
+{
+ const struct rk_gmac_ops *ops = rk_gmac_ops;
+
+ while (ops->compatible) {
+ if (device_is_compatible(dev, ops->compatible))
+ return ops;
+ ops++;
+ }
+
+ return NULL;
+}
+
+static int eqos_probe_resources_rk(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data;
+ const char *clock_in_out;
+ int reset_flags = GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE;
+ int ret;
+
+ data = calloc(1, sizeof(struct rockchip_platform_data));
+ if (!data)
+ return -ENOMEM;
+
+ data->ops = get_rk_gmac_ops(dev);
+ if (!data->ops) {
+ ret = -EINVAL;
+ goto err_free;
+ }
+
+ for (int i = 0; data->ops->regs[i]; i++) {
+ if (data->ops->regs[i] == (u32)eqos->regs) {
+ data->id = i;
+ break;
+ }
+ }
+
+ pdata->priv_pdata = data;
+ pdata->phy_interface = eqos->config->interface(dev);
+ pdata->max_speed = eqos->max_speed;
+
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) {
+ pr_err("Invalid PHY interface\n");
+ ret = -EINVAL;
+ goto err_free;
+ }
+
+ data->grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,grf");
+ if (IS_ERR(data->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ ret = -EINVAL;
+ goto err_free;
+ }
+
+ if (device_is_compatible(dev, "rockchip,rk3588-gmac")) {
+ data->php_grf =
+ syscon_regmap_lookup_by_phandle(dev, "rockchip,php-grf");
+ if (IS_ERR(data->php_grf)) {
+ dev_err(dev, "Missing rockchip,php-grf property\n");
+ ret = -EINVAL;
+ goto err_free;
+ }
+ }
+
+ ret = reset_get_bulk(dev, &data->resets);
+ if (ret < 0)
+ goto err_free;
+
+ reset_assert_bulk(&data->resets);
+
+ ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
+ if (ret) {
+ dev_dbg(dev, "clk_get_by_name(stmmaceth) failed: %d", ret);
+ goto err_release_resets;
+ }
+
+ if (device_is_compatible(dev, "rockchip,rk3568-gmac")) {
+ ret = clk_get_by_name(dev, "clk_mac_speed", &eqos->clk_tx);
+ if (ret) {
+ dev_dbg(dev, "clk_get_by_name(clk_mac_speed) failed: %d", ret);
+ goto err_free_clk_master_bus;
+ }
+ }
+
+ clock_in_out = dev_read_string(dev, "clock_in_out");
+ if (clock_in_out && !strcmp(clock_in_out, "input"))
+ data->clock_input = true;
+ else
+ data->clock_input = false;
+
+ /* snps,reset props are deprecated, do bare minimum to support them */
+ if (dev_read_bool(dev, "snps,reset-active-low"))
+ reset_flags |= GPIOD_ACTIVE_LOW;
+
+ dev_read_u32_array(dev, "snps,reset-delays-us", eqos->reset_delays, 3);
+
+ gpio_request_by_name(dev, "snps,reset-gpio", 0,
+ &eqos->phy_reset_gpio, reset_flags);
+
+ return 0;
+
+err_free_clk_master_bus:
+ clk_free(&eqos->clk_master_bus);
+err_release_resets:
+ reset_release_bulk(&data->resets);
+err_free:
+ free(data);
+
+ return ret;
+}
+
+static int eqos_remove_resources_rk(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+
+ if (dm_gpio_is_valid(&eqos->phy_reset_gpio))
+ dm_gpio_free(dev, &eqos->phy_reset_gpio);
+
+ clk_free(&eqos->clk_tx);
+ clk_free(&eqos->clk_master_bus);
+ reset_release_bulk(&data->resets);
+ free(data);
+
+ return 0;
+}
+
+static int eqos_stop_resets_rk(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+
+ return reset_assert_bulk(&data->resets);
+}
+
+static int eqos_start_resets_rk(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+
+ return reset_deassert_bulk(&data->resets);
+}
+
+static int eqos_stop_clks_rk(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+
+ if (data->ops->set_clock_selection)
+ data->ops->set_clock_selection(dev, false);
+
+ return 0;
+}
+
+static int eqos_start_clks_rk(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+ int tx_delay, rx_delay, ret;
+
+ if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
+ udelay(eqos->reset_delays[1]);
+
+ ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
+ if (ret < 0)
+ return ret;
+
+ udelay(eqos->reset_delays[2]);
+ }
+
+ if (data->ops->set_clock_selection)
+ data->ops->set_clock_selection(dev, true);
+
+ tx_delay = dev_read_u32_default(dev, "tx_delay", 0x30);
+ rx_delay = dev_read_u32_default(dev, "rx_delay", 0x10);
+
+ switch (pdata->phy_interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ return data->ops->set_to_rgmii(dev, tx_delay, rx_delay);
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ return data->ops->set_to_rgmii(dev, 0, 0);
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ return data->ops->set_to_rgmii(dev, tx_delay, 0);
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ return data->ops->set_to_rgmii(dev, 0, rx_delay);
+ case PHY_INTERFACE_MODE_RMII:
+ return data->ops->set_to_rmii(dev);
+ }
+
+ return -EINVAL;
+}
+
+static int eqos_set_tx_clk_speed_rk(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+
+ return data->ops->set_gmac_speed(dev);
+}
+
+static ulong eqos_get_tick_clk_rate_rk(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+
+ return clk_get_rate(&eqos->clk_master_bus);
+}
+
+static struct eqos_ops eqos_rockchip_ops = {
+ .eqos_inval_desc = eqos_inval_desc_generic,
+ .eqos_flush_desc = eqos_flush_desc_generic,
+ .eqos_inval_buffer = eqos_inval_buffer_generic,
+ .eqos_flush_buffer = eqos_flush_buffer_generic,
+ .eqos_probe_resources = eqos_probe_resources_rk,
+ .eqos_remove_resources = eqos_remove_resources_rk,
+ .eqos_stop_resets = eqos_stop_resets_rk,
+ .eqos_start_resets = eqos_start_resets_rk,
+ .eqos_stop_clks = eqos_stop_clks_rk,
+ .eqos_start_clks = eqos_start_clks_rk,
+ .eqos_calibrate_pads = eqos_null_ops,
+ .eqos_disable_calibration = eqos_null_ops,
+ .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_rk,
+ .eqos_get_enetaddr = eqos_null_ops,
+ .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_rk,
+};
+
+struct eqos_config eqos_rockchip_config = {
+ .reg_access_always_ok = false,
+ .mdio_wait = 10,
+ .swr_wait = 50,
+ .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
+ .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150,
+ .axi_bus_width = EQOS_AXI_WIDTH_64,
+ .interface = dev_read_phy_mode,
+ .ops = &eqos_rockchip_ops,
+};
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 41e6ba7..84a2a7c 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -5718,15 +5718,9 @@
.write_hwaddr = e1000_write_hwaddr,
};
-static const struct udevice_id e1000_eth_ids[] = {
- { .compatible = "intel,e1000" },
- { }
-};
-
U_BOOT_DRIVER(eth_e1000) = {
.name = "eth_e1000",
.id = UCLASS_ETH,
- .of_match = e1000_eth_ids,
.bind = e1000_eth_bind,
.probe = e1000_eth_probe,
.ops = &e1000_eth_ops,
diff --git a/drivers/net/fsl-mc/dpio/qbman_sys.h b/drivers/net/fsl-mc/dpio/qbman_sys.h
index ff998d4..1c6e489 100644
--- a/drivers/net/fsl-mc/dpio/qbman_sys.h
+++ b/drivers/net/fsl-mc/dpio/qbman_sys.h
@@ -21,6 +21,7 @@
/* Trace the 3 different classes of read/write access to QBMan. #undef as
* required. */
#include <linux/bug.h>
+#include <linux/printk.h>
#undef QBMAN_CCSR_TRACE
#undef QBMAN_CINH_TRACE
#undef QBMAN_CENA_TRACE
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 984616f..f5c5057 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -30,6 +30,8 @@
#include <fsl-mc/fsl_qbman_portal.h>
#include <fsl-mc/ldpaa_wriop.h>
#include <net/ldpaa_eth.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
#define MC_RAM_BASE_ADDR_ALIGNMENT (512UL * 1024 * 1024)
#define MC_RAM_BASE_ADDR_ALIGNMENT_MASK (~(MC_RAM_BASE_ADDR_ALIGNMENT - 1))
@@ -929,6 +931,114 @@
return dram_block_size;
}
+/**
+ * Populate the device tree with MC reserved memory ranges.
+ */
+void fdt_reserve_mc_mem(void *blob, u32 mc_icid)
+{
+ u32 phandle, mc_ph;
+ int noff, ret, i;
+ char mem_name[16];
+ struct fdt_memory mc_mem_ranges[] = {
+ {
+ .start = 0,
+ .end = 0
+ },
+ {
+ .start = CFG_SYS_FSL_MC_BASE,
+ .end = CFG_SYS_FSL_MC_BASE + CFG_SYS_FSL_MC_SIZE - 1
+ },
+ {
+ .start = CFG_SYS_FSL_NI_BASE,
+ .end = CFG_SYS_FSL_NI_BASE + CFG_SYS_FSL_NI_SIZE - 1
+ },
+ {
+ .start = CFG_SYS_FSL_QBMAN_BASE,
+ .end = CFG_SYS_FSL_QBMAN_BASE +
+ CFG_SYS_FSL_QBMAN_SIZE - 1
+ },
+ {
+ .start = CFG_SYS_FSL_PEBUF_BASE,
+ .end = CFG_SYS_FSL_PEBUF_BASE +
+ CFG_SYS_FSL_PEBUF_SIZE - 1
+ },
+ {
+ .start = CFG_SYS_FSL_CCSR_BASE,
+ .end = CFG_SYS_FSL_CCSR_BASE + CFG_SYS_FSL_CCSR_SIZE - 1
+ }
+ };
+
+ mc_mem_ranges[0].start = gd->arch.resv_ram;
+ mc_mem_ranges[0].end = mc_mem_ranges[0].start +
+ mc_get_dram_block_size() - 1;
+
+ for (i = 0; i < ARRAY_SIZE(mc_mem_ranges); i++) {
+ noff = fdt_node_offset_by_compatible(blob, -1, "fsl,qoriq-mc");
+ if (noff < 0) {
+ printf("WARN: failed to get MC node: %d\n", noff);
+ return;
+ }
+ mc_ph = fdt_get_phandle(blob, noff);
+ if (!mc_ph) {
+ mc_ph = fdt_create_phandle(blob, noff);
+ if (!mc_ph) {
+ printf("WARN: failed to get MC node phandle\n");
+ return;
+ }
+ }
+
+ sprintf(mem_name, "mc-mem%d", i);
+ ret = fdtdec_add_reserved_memory(blob, mem_name,
+ &mc_mem_ranges[i], NULL, 0,
+ &phandle, 0);
+ if (ret < 0) {
+ printf("ERROR: failed to reserve MC memory: %d\n", ret);
+ return;
+ }
+
+ noff = fdt_node_offset_by_phandle(blob, phandle);
+ if (noff < 0) {
+ printf("ERROR: failed get resvmem node offset: %d\n",
+ noff);
+ return;
+ }
+ ret = fdt_setprop_u32(blob, noff, "iommu-addresses", mc_ph);
+ if (ret < 0) {
+ printf("ERROR: failed to set 'iommu-addresses': %d\n",
+ ret);
+ return;
+ }
+ ret = fdt_appendprop_u64(blob, noff, "iommu-addresses",
+ mc_mem_ranges[i].start);
+ if (ret < 0) {
+ printf("ERROR: failed to set 'iommu-addresses': %d\n",
+ ret);
+ return;
+ }
+ ret = fdt_appendprop_u64(blob, noff, "iommu-addresses",
+ mc_mem_ranges[i].end -
+ mc_mem_ranges[i].start + 1);
+ if (ret < 0) {
+ printf("ERROR: failed to set 'iommu-addresses': %d\n",
+ ret);
+ return;
+ }
+
+ noff = fdt_node_offset_by_phandle(blob, mc_ph);
+ if (noff < 0) {
+ printf("ERROR: failed get MC node offset: %d\n", noff);
+ return;
+ }
+ ret = fdt_appendprop_u32(blob, noff, "memory-region", phandle);
+ if (ret < 0) {
+ printf("ERROR: failed to set 'memory-region': %d\n",
+ ret);
+ }
+ }
+
+ fdt_set_iommu_prop(blob, noff, fdt_get_smmu_phandle(blob), &mc_icid, 1);
+}
+
int fsl_mc_ldpaa_init(struct bd_info *bis)
{
int i;
diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index a50cde3..9b536fd 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -13,6 +13,7 @@
#include <common.h>
#include <clk.h>
+#include <reset.h>
#include <cpu_func.h>
#include <dm.h>
#include <log.h>
@@ -25,6 +26,7 @@
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/iopoll.h>
+#include <linux/printk.h>
#include "ftgmac100.h"
@@ -90,6 +92,7 @@
u32 max_speed;
struct clk_bulk clks;
+ struct reset_ctl *reset_ctl;
/* End of RX/TX ring buffer bits. Depend on model */
u32 rxdes0_edorr_mask;
@@ -568,6 +571,8 @@
priv->txdes0_edotr_mask = BIT(15);
}
+ priv->reset_ctl = devm_reset_control_get_optional(dev, NULL);
+
return clk_get_bulk(dev, &priv->clks);
}
@@ -593,6 +598,12 @@
if (ret)
goto out;
+ if (priv->reset_ctl) {
+ ret = reset_deassert(priv->reset_ctl);
+ if (ret)
+ goto out;
+ }
+
/*
* If DM MDIO is enabled, the MDIO bus will be initialized later in
* dm_eth_phy_connect
@@ -628,6 +639,8 @@
free(priv->phydev);
mdio_unregister(priv->bus);
mdio_free(priv->bus);
+ if (priv->reset_ctl)
+ reset_assert(priv->reset_ctl);
clk_release_bulk(&priv->clks);
return 0;
diff --git a/drivers/net/hifemac.c b/drivers/net/hifemac.c
new file mode 100644
index 0000000..b61a29e
--- /dev/null
+++ b/drivers/net/hifemac.c
@@ -0,0 +1,481 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Hisilicon Fast Ethernet MAC Driver
+ * Adapted from linux
+ *
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ * Copyright (c) 2023 Yang Xiwen <forbidden405@outlook.com>
+ */
+
+#include <dm.h>
+#include <clk.h>
+#include <miiphy.h>
+#include <net.h>
+#include <reset.h>
+#include <wait_bit.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+
+/* MAC control register list */
+#define MAC_PORTSEL 0x0200
+#define MAC_PORTSEL_STAT_CPU BIT(0)
+#define MAC_PORTSEL_RMII BIT(1)
+#define MAC_PORTSET 0x0208
+#define MAC_PORTSET_DUPLEX_FULL BIT(0)
+#define MAC_PORTSET_LINKED BIT(1)
+#define MAC_PORTSET_SPEED_100M BIT(2)
+#define MAC_SET 0x0210
+#define MAX_FRAME_SIZE 1600
+#define MAX_FRAME_SIZE_MASK GENMASK(10, 0)
+#define BIT_PAUSE_EN BIT(18)
+#define RX_COALESCE_SET 0x0340
+#define RX_COALESCED_FRAME_OFFSET 24
+#define RX_COALESCED_FRAMES 8
+#define RX_COALESCED_TIMER 0x74
+#define QLEN_SET 0x0344
+#define RX_DEPTH_OFFSET 8
+#define MAX_HW_FIFO_DEPTH 64
+#define HW_TX_FIFO_DEPTH 1
+#define MAX_HW_RX_FIFO_DEPTH (MAX_HW_FIFO_DEPTH - HW_TX_FIFO_DEPTH)
+#define HW_RX_FIFO_DEPTH min(PKTBUFSRX, MAX_HW_RX_FIFO_DEPTH)
+#define IQFRM_DES 0x0354
+#define RX_FRAME_LEN_MASK GENMASK(11, 0)
+#define RX_FRAME_IN_INDEX_MASK GENMASK(17, 12)
+#define IQ_ADDR 0x0358
+#define EQ_ADDR 0x0360
+#define EQFRM_LEN 0x0364
+#define ADDRQ_STAT 0x036C
+#define TX_CNT_INUSE_MASK GENMASK(5, 0)
+#define BIT_TX_READY BIT(24)
+#define BIT_RX_READY BIT(25)
+/* global control register list */
+#define GLB_HOSTMAC_L32 0x0000
+#define GLB_HOSTMAC_H16 0x0004
+#define GLB_SOFT_RESET 0x0008
+#define SOFT_RESET_ALL BIT(0)
+#define GLB_FWCTRL 0x0010
+#define FWCTRL_VLAN_ENABLE BIT(0)
+#define FWCTRL_FW2CPU_ENA BIT(5)
+#define FWCTRL_FWALL2CPU BIT(7)
+#define GLB_MACTCTRL 0x0014
+#define MACTCTRL_UNI2CPU BIT(1)
+#define MACTCTRL_MULTI2CPU BIT(3)
+#define MACTCTRL_BROAD2CPU BIT(5)
+#define MACTCTRL_MACT_ENA BIT(7)
+#define GLB_IRQ_STAT 0x0030
+#define GLB_IRQ_ENA 0x0034
+#define IRQ_ENA_PORT0_MASK GENMASK(7, 0)
+#define IRQ_ENA_PORT0 BIT(18)
+#define IRQ_ENA_ALL BIT(19)
+#define GLB_IRQ_RAW 0x0038
+#define IRQ_INT_RX_RDY BIT(0)
+#define IRQ_INT_TX_PER_PACKET BIT(1)
+#define IRQ_INT_TX_FIFO_EMPTY BIT(6)
+#define IRQ_INT_MULTI_RXRDY BIT(7)
+#define DEF_INT_MASK (IRQ_INT_MULTI_RXRDY | \
+ IRQ_INT_TX_PER_PACKET | \
+ IRQ_INT_TX_FIFO_EMPTY)
+#define GLB_MAC_L32_BASE 0x0100
+#define GLB_MAC_H16_BASE 0x0104
+#define MACFLT_HI16_MASK GENMASK(15, 0)
+#define BIT_MACFLT_ENA BIT(17)
+#define BIT_MACFLT_FW2CPU BIT(21)
+#define GLB_MAC_H16(reg) (GLB_MAC_H16_BASE + ((reg) * 0x8))
+#define GLB_MAC_L32(reg) (GLB_MAC_L32_BASE + ((reg) * 0x8))
+#define MAX_MAC_FILTER_NUM 8
+#define MAX_UNICAST_ADDRESSES 2
+#define MAX_MULTICAST_ADDRESSES (MAX_MAC_FILTER_NUM - \
+ MAX_UNICAST_ADDRESSES)
+/* software tx and rx queue number, should be power of 2 */
+#define TXQ_NUM 64
+#define RXQ_NUM 128
+
+#define PHY_RESET_DELAYS_PROPERTY "hisilicon,phy-reset-delays-us"
+#define MAC_RESET_DELAY_PROPERTY "hisilicon,mac-reset-delay-us"
+#define MAC_RESET_ASSERT_PERIOD 200000
+
+enum phy_reset_delays {
+ PRE_DELAY,
+ PULSE,
+ POST_DELAY,
+ DELAYS_NUM,
+};
+
+enum clk_type {
+ CLK_MAC,
+ CLK_BUS,
+ CLK_PHY,
+ CLK_NUM,
+};
+
+struct hisi_femac_priv {
+ void __iomem *port_base;
+ void __iomem *glb_base;
+ struct clk *clks[CLK_NUM];
+ struct reset_ctl *mac_rst;
+ struct reset_ctl *phy_rst;
+ u32 phy_reset_delays[DELAYS_NUM];
+ u32 mac_reset_delay;
+
+ struct phy_device *phy;
+
+ u32 link_status;
+};
+
+static void hisi_femac_irq_enable(struct hisi_femac_priv *priv, int irqs)
+{
+ u32 val;
+
+ val = readl(priv->glb_base + GLB_IRQ_ENA);
+ writel(val | irqs, priv->glb_base + GLB_IRQ_ENA);
+}
+
+static void hisi_femac_irq_disable(struct hisi_femac_priv *priv, int irqs)
+{
+ u32 val;
+
+ val = readl(priv->glb_base + GLB_IRQ_ENA);
+ writel(val & (~irqs), priv->glb_base + GLB_IRQ_ENA);
+}
+
+static void hisi_femac_port_init(struct hisi_femac_priv *priv)
+{
+ u32 val;
+
+ /* MAC gets link status info and phy mode by software config */
+ val = MAC_PORTSEL_STAT_CPU;
+ if (priv->phy->interface == PHY_INTERFACE_MODE_RMII)
+ val |= MAC_PORTSEL_RMII;
+ writel(val, priv->port_base + MAC_PORTSEL);
+
+ /*clear all interrupt status */
+ writel(IRQ_ENA_PORT0_MASK, priv->glb_base + GLB_IRQ_RAW);
+ hisi_femac_irq_disable(priv, IRQ_ENA_PORT0_MASK | IRQ_ENA_PORT0);
+
+ val = readl(priv->glb_base + GLB_FWCTRL);
+ val &= ~(FWCTRL_VLAN_ENABLE | FWCTRL_FWALL2CPU);
+ val |= FWCTRL_FW2CPU_ENA;
+ writel(val, priv->glb_base + GLB_FWCTRL);
+
+ val = readl(priv->glb_base + GLB_MACTCTRL);
+ val |= (MACTCTRL_BROAD2CPU | MACTCTRL_MACT_ENA);
+ writel(val, priv->glb_base + GLB_MACTCTRL);
+
+ val = readl(priv->port_base + MAC_SET);
+ val &= ~MAX_FRAME_SIZE_MASK;
+ val |= MAX_FRAME_SIZE;
+ writel(val, priv->port_base + MAC_SET);
+
+ val = RX_COALESCED_TIMER |
+ (RX_COALESCED_FRAMES << RX_COALESCED_FRAME_OFFSET);
+ writel(val, priv->port_base + RX_COALESCE_SET);
+
+ val = (HW_RX_FIFO_DEPTH << RX_DEPTH_OFFSET) | HW_TX_FIFO_DEPTH;
+ writel(val, priv->port_base + QLEN_SET);
+}
+
+static void hisi_femac_rx_refill(struct hisi_femac_priv *priv)
+{
+ int i;
+ ulong addr;
+
+ for (i = 0; i < HW_RX_FIFO_DEPTH; i++) {
+ addr = (ulong)net_rx_packets[i];
+ writel(addr, priv->port_base + IQ_ADDR);
+ }
+}
+
+static void hisi_femac_adjust_link(struct udevice *dev)
+{
+ struct hisi_femac_priv *priv = dev_get_priv(dev);
+ struct phy_device *phy = priv->phy;
+ u32 status = 0;
+
+ if (phy->link)
+ status |= MAC_PORTSET_LINKED;
+ if (phy->duplex == DUPLEX_FULL)
+ status |= MAC_PORTSET_DUPLEX_FULL;
+ if (phy->speed == SPEED_100)
+ status |= MAC_PORTSET_SPEED_100M;
+
+ writel(status, priv->port_base + MAC_PORTSET);
+}
+
+static int hisi_femac_port_reset(struct hisi_femac_priv *priv)
+{
+ u32 val;
+
+ val = readl(priv->glb_base + GLB_SOFT_RESET);
+ val |= SOFT_RESET_ALL;
+ writel(val, priv->glb_base + GLB_SOFT_RESET);
+
+ udelay(800);
+
+ val &= ~SOFT_RESET_ALL;
+ writel(val, priv->glb_base + GLB_SOFT_RESET);
+
+ return 0;
+}
+
+static int hisi_femac_set_hw_mac_addr(struct udevice *dev)
+{
+ struct hisi_femac_priv *priv = dev_get_priv(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
+ unsigned char *mac = plat->enetaddr;
+ u32 reg;
+
+ reg = mac[1] | (mac[0] << 8);
+ writel(reg, priv->glb_base + GLB_HOSTMAC_H16);
+
+ reg = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24);
+ writel(reg, priv->glb_base + GLB_HOSTMAC_L32);
+
+ return 0;
+}
+
+static int hisi_femac_start(struct udevice *dev)
+{
+ int ret;
+ struct hisi_femac_priv *priv = dev_get_priv(dev);
+
+ hisi_femac_port_reset(priv);
+ hisi_femac_set_hw_mac_addr(dev);
+ hisi_femac_rx_refill(priv);
+
+ ret = phy_startup(priv->phy);
+ if (ret)
+ return log_msg_ret("Failed to startup phy", ret);
+
+ if (!priv->phy->link) {
+ debug("%s: link down\n", __func__);
+ return -ENODEV;
+ }
+
+ hisi_femac_adjust_link(dev);
+
+ writel(IRQ_ENA_PORT0_MASK, priv->glb_base + GLB_IRQ_RAW);
+ hisi_femac_irq_enable(priv, IRQ_ENA_ALL | IRQ_ENA_PORT0 | DEF_INT_MASK);
+
+ return 0;
+}
+
+static int hisi_femac_send(struct udevice *dev, void *packet, int length)
+{
+ struct hisi_femac_priv *priv = dev_get_priv(dev);
+ ulong addr = (ulong)packet;
+ int ret;
+
+ // clear previous irq
+ writel(IRQ_INT_TX_PER_PACKET, priv->glb_base + GLB_IRQ_RAW);
+
+ // flush cache
+ flush_cache(addr, length + ETH_FCS_LEN);
+
+ // write packet address
+ writel(addr, priv->port_base + EQ_ADDR);
+
+ // write packet length (and send it)
+ writel(length + ETH_FCS_LEN, priv->port_base + EQFRM_LEN);
+
+ // wait until FIFO is empty
+ ret = wait_for_bit_le32(priv->glb_base + GLB_IRQ_RAW, IRQ_INT_TX_PER_PACKET, true, 50, false);
+ if (ret == -ETIMEDOUT)
+ return log_msg_ret("FIFO timeout", ret);
+
+ return 0;
+}
+
+static int hisi_femac_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct hisi_femac_priv *priv = dev_get_priv(dev);
+ int val, index, length;
+
+ val = readl(priv->glb_base + GLB_IRQ_RAW);
+ if (!(val & IRQ_INT_RX_RDY))
+ return -EAGAIN;
+
+ val = readl(priv->port_base + IQFRM_DES);
+ index = (val & RX_FRAME_IN_INDEX_MASK) >> 12;
+ length = val & RX_FRAME_LEN_MASK;
+
+ // invalidate cache
+ invalidate_dcache_range((ulong)net_rx_packets[index], (ulong)net_rx_packets[index] + length);
+ *packetp = net_rx_packets[index];
+
+ // Tell hardware we will process the packet
+ writel(IRQ_INT_RX_RDY, priv->glb_base + GLB_IRQ_RAW);
+
+ return length;
+}
+
+static int hisi_femac_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct hisi_femac_priv *priv = dev_get_priv(dev);
+ ulong addr = (ulong)packet;
+
+ // Tell hardware the packet can be reused
+ writel(addr, priv->port_base + IQ_ADDR);
+
+ return 0;
+}
+
+static void hisi_femac_stop(struct udevice *dev)
+{
+ struct hisi_femac_priv *priv = dev_get_priv(dev);
+
+ // assert internal reset
+ writel(SOFT_RESET_ALL, priv->glb_base + GLB_SOFT_RESET);
+}
+
+int hisi_femac_of_to_plat(struct udevice *dev)
+{
+ int ret, i;
+ struct hisi_femac_priv *priv = dev_get_priv(dev);
+ static const char * const clk_strs[] = {
+ [CLK_MAC] = "mac",
+ [CLK_BUS] = "bus",
+ [CLK_PHY] = "phy",
+ };
+
+ priv->port_base = dev_remap_addr_name(dev, "port");
+ if (IS_ERR(priv->port_base))
+ return log_msg_ret("Failed to remap port address space", PTR_ERR(priv->port_base));
+
+ priv->glb_base = dev_remap_addr_name(dev, "glb");
+ if (IS_ERR(priv->glb_base))
+ return log_msg_ret("Failed to remap global address space", PTR_ERR(priv->glb_base));
+
+ for (i = 0; i < ARRAY_SIZE(clk_strs); i++) {
+ priv->clks[i] = devm_clk_get(dev, clk_strs[i]);
+ if (IS_ERR(priv->clks[i])) {
+ dev_err(dev, "Error getting clock %s\n", clk_strs[i]);
+ return log_msg_ret("Failed to get clocks", PTR_ERR(priv->clks[i]));
+ }
+ }
+
+ priv->mac_rst = devm_reset_control_get(dev, "mac");
+ if (IS_ERR(priv->mac_rst))
+ return log_msg_ret("Failed to get MAC reset", PTR_ERR(priv->mac_rst));
+
+ priv->phy_rst = devm_reset_control_get(dev, "phy");
+ if (IS_ERR(priv->phy_rst))
+ return log_msg_ret("Failed to get PHY reset", PTR_ERR(priv->phy_rst));
+
+ ret = dev_read_u32_array(dev,
+ PHY_RESET_DELAYS_PROPERTY,
+ priv->phy_reset_delays,
+ DELAYS_NUM);
+ if (ret < 0)
+ return log_msg_ret("Failed to get PHY reset delays", ret);
+
+ priv->mac_reset_delay = dev_read_u32_default(dev,
+ MAC_RESET_DELAY_PROPERTY,
+ MAC_RESET_ASSERT_PERIOD);
+
+ return 0;
+}
+
+static int hisi_femac_phy_reset(struct hisi_femac_priv *priv)
+{
+ struct reset_ctl *rst = priv->phy_rst;
+ u32 *delays = priv->phy_reset_delays;
+ int ret;
+
+ // Disable MAC clk before phy reset
+ ret = clk_disable(priv->clks[CLK_MAC]);
+ if (ret < 0)
+ return log_msg_ret("Failed to disable MAC clock", ret);
+ ret = clk_disable(priv->clks[CLK_BUS]);
+ if (ret < 0)
+ return log_msg_ret("Failed to disable bus clock", ret);
+
+ udelay(delays[PRE_DELAY]);
+
+ ret = reset_assert(rst);
+ if (ret < 0)
+ return log_msg_ret("Failed to assert reset", ret);
+
+ udelay(delays[PULSE]);
+
+ ret = reset_deassert(rst);
+ if (ret < 0)
+ return log_msg_ret("Failed to deassert reset", ret);
+
+ udelay(delays[POST_DELAY]);
+
+ ret = clk_enable(priv->clks[CLK_MAC]);
+ if (ret < 0)
+ return log_msg_ret("Failed to enable MAC clock", ret);
+ ret = clk_enable(priv->clks[CLK_BUS]);
+ if (ret < 0)
+ return log_msg_ret("Failed to enable MAC bus clock", ret);
+
+ return 0;
+}
+
+int hisi_femac_probe(struct udevice *dev)
+{
+ struct hisi_femac_priv *priv = dev_get_priv(dev);
+ int ret, i;
+
+ // Enable clocks
+ for (i = 0; i < CLK_NUM; i++) {
+ ret = clk_prepare_enable(priv->clks[i]);
+ if (ret < 0)
+ return log_msg_ret("Failed to enable clks", ret);
+ }
+
+ // Reset MAC
+ ret = reset_assert(priv->mac_rst);
+ if (ret < 0)
+ return log_msg_ret("Failed to assert MAC reset", ret);
+
+ udelay(priv->mac_reset_delay);
+
+ ret = reset_deassert(priv->mac_rst);
+ if (ret < 0)
+ return log_msg_ret("Failed to deassert MAC reset", ret);
+
+ // Reset PHY
+ ret = hisi_femac_phy_reset(priv);
+ if (ret < 0)
+ return log_msg_ret("Failed to reset phy", ret);
+
+ // Connect to PHY
+ priv->phy = dm_eth_phy_connect(dev);
+ if (!priv->phy)
+ return log_msg_ret("Failed to connect to phy", -EINVAL);
+
+ hisi_femac_port_init(priv);
+ return 0;
+}
+
+static const struct eth_ops hisi_femac_ops = {
+ .start = hisi_femac_start,
+ .send = hisi_femac_send,
+ .recv = hisi_femac_recv,
+ .free_pkt = hisi_femac_free_pkt,
+ .stop = hisi_femac_stop,
+ .write_hwaddr = hisi_femac_set_hw_mac_addr,
+};
+
+static const struct udevice_id hisi_femac_ids[] = {
+ {.compatible = "hisilicon,hisi-femac-v1",},
+ {.compatible = "hisilicon,hisi-femac-v2",},
+ {.compatible = "hisilicon,hi3516cv300-femac",},
+ {.compatible = "hisilicon,hi3798mv200-femac",},
+ {},
+};
+
+U_BOOT_DRIVER(hisi_femac_driver) = {
+ .name = "eth_hisi_femac",
+ .id = UCLASS_ETH,
+ .of_match = of_match_ptr(hisi_femac_ids),
+ .of_to_plat = hisi_femac_of_to_plat,
+ .ops = &hisi_femac_ops,
+ .probe = hisi_femac_probe,
+ .plat_auto = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct hisi_femac_priv),
+};
diff --git a/drivers/net/hifemac_mdio.c b/drivers/net/hifemac_mdio.c
new file mode 100644
index 0000000..343c5f3
--- /dev/null
+++ b/drivers/net/hifemac_mdio.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hisilicon Fast Ethernet MDIO Bus Driver
+ *
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ */
+
+#include <dm.h>
+#include <clk.h>
+#include <miiphy.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+
+#define MDIO_RWCTRL 0x00
+#define MDIO_RO_DATA 0x04
+#define MDIO_WRITE BIT(13)
+#define MDIO_RW_FINISH BIT(15)
+#define BIT_PHY_ADDR_OFFSET 8
+#define BIT_WR_DATA_OFFSET 16
+
+struct hisi_femac_mdio_data {
+ struct clk *clk;
+ void __iomem *membase;
+};
+
+static int hisi_femac_mdio_wait_ready(struct hisi_femac_mdio_data *data)
+{
+ u32 val;
+
+ return readl_poll_timeout(data->membase + MDIO_RWCTRL,
+ val, val & MDIO_RW_FINISH, 10000);
+}
+
+static int hisi_femac_mdio_read(struct udevice *dev, int addr, int devad, int reg)
+{
+ struct hisi_femac_mdio_data *data = dev_get_priv(dev);
+ int ret;
+
+ ret = hisi_femac_mdio_wait_ready(data);
+ if (ret)
+ return ret;
+
+ writel((addr << BIT_PHY_ADDR_OFFSET) | reg,
+ data->membase + MDIO_RWCTRL);
+
+ ret = hisi_femac_mdio_wait_ready(data);
+ if (ret)
+ return ret;
+
+ return readl(data->membase + MDIO_RO_DATA) & 0xFFFF;
+}
+
+static int hisi_femac_mdio_write(struct udevice *dev, int addr, int devad, int reg, u16 val)
+{
+ struct hisi_femac_mdio_data *data = dev_get_priv(dev);
+ int ret;
+
+ ret = hisi_femac_mdio_wait_ready(data);
+ if (ret)
+ return ret;
+
+ writel(MDIO_WRITE | (val << BIT_WR_DATA_OFFSET) |
+ (addr << BIT_PHY_ADDR_OFFSET) | reg,
+ data->membase + MDIO_RWCTRL);
+
+ return hisi_femac_mdio_wait_ready(data);
+}
+
+static int hisi_femac_mdio_of_to_plat(struct udevice *dev)
+{
+ struct hisi_femac_mdio_data *data = dev_get_priv(dev);
+ int ret;
+
+ data->membase = dev_remap_addr(dev);
+ if (IS_ERR(data->membase)) {
+ ret = PTR_ERR(data->membase);
+ return log_msg_ret("Failed to remap base addr", ret);
+ }
+
+ // clk is optional
+ data->clk = devm_clk_get_optional(dev, NULL);
+
+ return 0;
+}
+
+static int hisi_femac_mdio_probe(struct udevice *dev)
+{
+ struct hisi_femac_mdio_data *data = dev_get_priv(dev);
+ int ret;
+
+ ret = clk_prepare_enable(data->clk);
+ if (ret)
+ return log_msg_ret("Failed to enable clk", ret);
+
+ return 0;
+}
+
+static const struct mdio_ops hisi_femac_mdio_ops = {
+ .read = hisi_femac_mdio_read,
+ .write = hisi_femac_mdio_write,
+};
+
+static const struct udevice_id hisi_femac_mdio_dt_ids[] = {
+ { .compatible = "hisilicon,hisi-femac-mdio" },
+ { }
+};
+
+U_BOOT_DRIVER(hisi_femac_mdio_driver) = {
+ .name = "hisi-femac-mdio",
+ .id = UCLASS_MDIO,
+ .of_match = hisi_femac_mdio_dt_ids,
+ .of_to_plat = hisi_femac_mdio_of_to_plat,
+ .probe = hisi_femac_mdio_probe,
+ .ops = &hisi_femac_mdio_ops,
+ .priv_auto = sizeof(struct hisi_femac_mdio_data),
+};
diff --git a/drivers/net/mscc_eswitch/jr2_switch.c b/drivers/net/mscc_eswitch/jr2_switch.c
index 1462b8f..7157428 100644
--- a/drivers/net/mscc_eswitch/jr2_switch.c
+++ b/drivers/net/mscc_eswitch/jr2_switch.c
@@ -17,6 +17,7 @@
#include <miiphy.h>
#include <net.h>
#include <wait_bit.h>
+#include <linux/printk.h>
#include <dt-bindings/mscc/jr2_data.h>
#include "mscc_xfer.h"
diff --git a/drivers/net/mscc_eswitch/ocelot_switch.c b/drivers/net/mscc_eswitch/ocelot_switch.c
index 1bf6c42..7ea1f55 100644
--- a/drivers/net/mscc_eswitch/ocelot_switch.c
+++ b/drivers/net/mscc_eswitch/ocelot_switch.c
@@ -17,6 +17,7 @@
#include <miiphy.h>
#include <net.h>
#include <wait_bit.h>
+#include <linux/printk.h>
#include "mscc_xfer.h"
#include "mscc_mac_table.h"
diff --git a/drivers/net/mscc_eswitch/serval_switch.c b/drivers/net/mscc_eswitch/serval_switch.c
index 38ddba1..be06e48 100644
--- a/drivers/net/mscc_eswitch/serval_switch.c
+++ b/drivers/net/mscc_eswitch/serval_switch.c
@@ -17,6 +17,7 @@
#include <miiphy.h>
#include <net.h>
#include <wait_bit.h>
+#include <linux/printk.h>
#include "mscc_xfer.h"
#include "mscc_mac_table.h"
diff --git a/drivers/net/mscc_eswitch/servalt_switch.c b/drivers/net/mscc_eswitch/servalt_switch.c
index db863c2..2d2329c 100644
--- a/drivers/net/mscc_eswitch/servalt_switch.c
+++ b/drivers/net/mscc_eswitch/servalt_switch.c
@@ -16,6 +16,7 @@
#include <miiphy.h>
#include <net.h>
#include <wait_bit.h>
+#include <linux/printk.h>
#include "mscc_xfer.h"
#include "mscc_miim.h"
diff --git a/drivers/net/mt7628-eth.c b/drivers/net/mt7628-eth.c
index 0a9bdb3..b95de47 100644
--- a/drivers/net/mt7628-eth.c
+++ b/drivers/net/mt7628-eth.c
@@ -28,6 +28,7 @@
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
+#include <linux/printk.h>
/* Ethernet frame engine register */
#define PDMA_RELATED 0x0800
diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c
index d4111e7..3cfce05 100644
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -26,6 +26,7 @@
#include <linux/ioport.h>
#include <linux/mdio.h>
#include <linux/mii.h>
+#include <linux/printk.h>
#include "mtk_eth.h"
diff --git a/drivers/net/mv88e6xxx.c b/drivers/net/mv88e6xxx.c
index 64e860e..c073f81 100644
--- a/drivers/net/mv88e6xxx.c
+++ b/drivers/net/mv88e6xxx.c
@@ -29,6 +29,7 @@
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dm/of_extra.h>
+#include <linux/bitfield.h>
#include <linux/delay.h>
#include <miiphy.h>
#include <net/dsa.h>
@@ -110,20 +111,35 @@
*/
#define SMI_BUSY BIT(15)
#define SMI_CMD_CLAUSE_22 BIT(12)
-#define SMI_CMD_CLAUSE_22_OP_READ (2 << 10)
-#define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10)
-#define SMI_CMD_ADDR_SHIFT 5
-#define SMI_CMD_ADDR_MASK 0x1f
-#define SMI_CMD_REG_SHIFT 0
-#define SMI_CMD_REG_MASK 0x1f
+#define SMI_CMD_OP_MASK GENMASK(11, 10)
+#define SMI_CMD_CLAUSE_22_OP_WRITE 0x1
+#define SMI_CMD_CLAUSE_22_OP_READ 0x2
+#define SMI_CMD_CLAUSE_45_OP_WRITE_ADDR 0x0
+#define SMI_CMD_CLAUSE_45_OP_WRITE 0x1
+#define SMI_CMD_CLAUSE_45_OP_READ 0x3
+
+#define SMI_CMD_ADDR_MASK GENMASK(9, 5)
+#define SMI_CMD_REG_MASK GENMASK(4, 0)
#define SMI_CMD_READ(addr, reg) \
- (SMI_BUSY | SMI_CMD_CLAUSE_22 | SMI_CMD_CLAUSE_22_OP_READ) | \
- (((addr) & SMI_CMD_ADDR_MASK) << SMI_CMD_ADDR_SHIFT) | \
- (((reg) & SMI_CMD_REG_MASK) << SMI_CMD_REG_SHIFT)
+ (SMI_BUSY | SMI_CMD_CLAUSE_22 | FIELD_PREP(SMI_CMD_OP_MASK, SMI_CMD_CLAUSE_22_OP_READ)) | \
+ (FIELD_PREP(SMI_CMD_ADDR_MASK, addr)) | \
+ (FIELD_PREP(SMI_CMD_REG_MASK, reg))
#define SMI_CMD_WRITE(addr, reg) \
- (SMI_BUSY | SMI_CMD_CLAUSE_22 | SMI_CMD_CLAUSE_22_OP_WRITE) | \
- (((addr) & SMI_CMD_ADDR_MASK) << SMI_CMD_ADDR_SHIFT) | \
- (((reg) & SMI_CMD_REG_MASK) << SMI_CMD_REG_SHIFT)
+ (SMI_BUSY | SMI_CMD_CLAUSE_22 | FIELD_PREP(SMI_CMD_OP_MASK, SMI_CMD_CLAUSE_22_OP_WRITE)) | \
+ (FIELD_PREP(SMI_CMD_ADDR_MASK, addr)) | \
+ (FIELD_PREP(SMI_CMD_REG_MASK, reg))
+#define SMI_CMD_SET_C45_ADDR(phyad, devad) \
+ (SMI_BUSY | FIELD_PREP(SMI_CMD_OP_MASK, SMI_CMD_CLAUSE_45_OP_WRITE_ADDR)) | \
+ (FIELD_PREP(SMI_CMD_ADDR_MASK, phyad)) | \
+ (FIELD_PREP(SMI_CMD_REG_MASK, devad))
+#define SMI_CMD_READ_C45(phyad, devad) \
+ (SMI_BUSY | FIELD_PREP(SMI_CMD_OP_MASK, SMI_CMD_CLAUSE_45_OP_READ)) | \
+ (FIELD_PREP(SMI_CMD_ADDR_MASK, phyad)) | \
+ (FIELD_PREP(SMI_CMD_REG_MASK, devad))
+#define SMI_CMD_WRITE_C45(phyad, devad) \
+ (SMI_BUSY | FIELD_PREP(SMI_CMD_OP_MASK, SMI_CMD_CLAUSE_45_OP_WRITE)) | \
+ (FIELD_PREP(SMI_CMD_ADDR_MASK, phyad)) | \
+ (FIELD_PREP(SMI_CMD_REG_MASK, devad))
/* ID register values for different switch models */
#define PORT_SWITCH_ID_6020 0x0200
@@ -272,12 +288,37 @@
static int mv88e6xxx_phy_read_indirect(struct udevice *dev, int phyad, int devad, int reg)
{
struct mv88e6xxx_priv *priv = dev_get_priv(dev);
+ u16 smi_cmd;
int res;
+ if (devad >= 0) {
+ /*
+ * For C45 we need to write the register address into the
+ * PHY Data register first and then call the Write Address
+ * Register OP in the PHY command register.
+ */
+ res = mv88e6xxx_reg_write(dev, priv->global2,
+ GLOBAL2_REG_PHY_DATA,
+ reg);
+
+ res = mv88e6xxx_reg_write(dev, priv->global2,
+ GLOBAL2_REG_PHY_CMD,
+ SMI_CMD_SET_C45_ADDR(phyad, devad));
+
+ /* Wait for busy bit to clear */
+ res = mv88e6xxx_phy_wait(dev);
+ if (res < 0)
+ return res;
+
+ /* Set the actual C45 or C22 OP-s */
+ smi_cmd = SMI_CMD_READ_C45(phyad, devad);
+ } else
+ smi_cmd = SMI_CMD_READ(phyad, reg);
+
/* Issue command to read */
res = mv88e6xxx_reg_write(dev, priv->global2,
GLOBAL2_REG_PHY_CMD,
- SMI_CMD_READ(phyad, reg));
+ smi_cmd);
/* Wait for data to be read */
res = mv88e6xxx_phy_wait(dev);
@@ -293,8 +334,33 @@
int devad, int reg, u16 data)
{
struct mv88e6xxx_priv *priv = dev_get_priv(dev);
+ u16 smi_cmd;
int res;
+ if (devad >= 0) {
+ /*
+ * For C45 we need to write the register address into the
+ * PHY Data register first and then call the Write Address
+ * Register OP in the PHY command register.
+ */
+ res = mv88e6xxx_reg_write(dev, priv->global2,
+ GLOBAL2_REG_PHY_DATA,
+ reg);
+
+ res = mv88e6xxx_reg_write(dev, priv->global2,
+ GLOBAL2_REG_PHY_CMD,
+ SMI_CMD_SET_C45_ADDR(phyad, devad));
+
+ /* Wait for busy bit to clear */
+ res = mv88e6xxx_phy_wait(dev);
+ if (res < 0)
+ return res;
+
+ /* Set the actual C45 or C22 OP-s */
+ smi_cmd = SMI_CMD_WRITE_C45(phyad, devad);
+ } else
+ smi_cmd = SMI_CMD_WRITE(phyad, reg);
+
/* Set the data to write */
res = mv88e6xxx_reg_write(dev, priv->global2,
GLOBAL2_REG_PHY_DATA, data);
@@ -303,7 +369,7 @@
/* Issue the write command */
res = mv88e6xxx_reg_write(dev, priv->global2,
GLOBAL2_REG_PHY_CMD,
- SMI_CMD_WRITE(phyad, reg));
+ smi_cmd);
if (res < 0)
return res;
diff --git a/drivers/net/mvmdio.c b/drivers/net/mvmdio.c
index c0ebcdb..5ebcfe1 100644
--- a/drivers/net/mvmdio.c
+++ b/drivers/net/mvmdio.c
@@ -13,6 +13,7 @@
#include <asm/io.h>
#include <wait_bit.h>
#include <linux/bitops.h>
+#include <linux/printk.h>
#define MVMDIO_SMI_DATA_SHIFT 0
#define MVMDIO_SMI_PHY_ADDR_SHIFT 16
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 0c3c39a..3d96938 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -224,7 +224,7 @@
tristate "Motorcomm PHYs"
help
Enables support for Motorcomm network PHYs.
- Currently supports the YT8531 Gigabit Ethernet PHYs.
+ Currently supports the YT8511 and YT8531 Gigabit Ethernet PHYs.
config PHY_MSCC
bool "Microsemi Corp Ethernet PHYs support"
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 36c70da..82e3bbe 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -30,10 +30,87 @@
#define MIIM_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */
#define MIIM_BCM_AUXCNTL_SHDWSEL_MISC 0x0007
-#define MIIM_BCM_AUXCNTL_ACTL_SMDSP_EN 0x0800
+#define MIIM_BCM_AUXCNTL_SHDWSEL_MISC_WIRESPEED_EN 0x0010
+#define MIIM_BCM_AUXCNTL_SHDWSEL_MISC_RGMII_EN 0x0080
+#define MIIM_BCM_AUXCNTL_SHDWSEL_MISC_RGMII_SKEW_EN 0x0100
+#define MIIM_BCM_AUXCNTL_MISC_FORCE_AMDIX 0x0200
+#define MIIM_BCM_AUXCNTL_ACTL_SMDSP_EN 0x0800
+#define MIIM_BCM_AUXCNTL_MISC_WREN 0x8000
#define MIIM_BCM_CHANNEL_WIDTH 0x2000
+#define BCM54810_SHD_CLK_CTL 0x3
+#define BCM54810_SHD_CLK_CTL_GTXCLK_EN BIT(9)
+
+static int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum)
+{
+ /* The register must be written to both the Shadow Register Select and
+ * the Shadow Read Register Selector
+ */
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL,
+ MIIM_BCM54xx_AUXCNTL_ENCODE(regnum));
+ return phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL);
+}
+
+static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
+{
+ return phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, regnum | val);
+}
+
+static int bcm_phy_read_shadow(struct phy_device *phydev, u16 shadow)
+{
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD,
+ MIIM_BCM54XX_SHD_VAL(shadow));
+ return MIIM_BCM54XX_SHD_DATA(phy_read(phydev, MDIO_DEVAD_NONE,
+ MIIM_BCM54XX_SHD));
+}
+
+static int bcm_phy_write_shadow(struct phy_device *phydev, u16 shadow, u16 val)
+{
+ return phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD,
+ MIIM_BCM54XX_SHD_WR_ENCODE(shadow, val));
+}
+
+static int bcm54xx_config_clock_delay(struct phy_device *phydev)
+{
+ int rc, val;
+
+ /* handling PHY's internal RX clock delay */
+ val = bcm54xx_auxctl_read(phydev, MIIM_BCM_AUXCNTL_SHDWSEL_MISC);
+ val |= MIIM_BCM_AUXCNTL_MISC_WREN;
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
+ /* Disable RGMII RXC-RXD skew */
+ val &= ~MIIM_BCM_AUXCNTL_SHDWSEL_MISC_RGMII_SKEW_EN;
+ }
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
+ /* Enable RGMII RXC-RXD skew */
+ val |= MIIM_BCM_AUXCNTL_SHDWSEL_MISC_RGMII_SKEW_EN;
+ }
+ rc = bcm54xx_auxctl_write(phydev, MIIM_BCM_AUXCNTL_SHDWSEL_MISC, val);
+ if (rc < 0)
+ return rc;
+
+ /* handling PHY's internal TX clock delay */
+ val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
+ /* Disable internal TX clock delay */
+ val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
+ }
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
+ /* Enable internal TX clock delay */
+ val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN;
+ }
+ rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
+ if (rc < 0)
+ return rc;
+
+ return 0;
+}
+
static void bcm_phy_write_misc(struct phy_device *phydev,
u16 reg, u16 chl, u16 value)
{
@@ -62,6 +139,18 @@
return 0;
}
+/* Broadcom BCM54210E */
+static int bcm54210e_config(struct phy_device *phydev)
+{
+ int ret;
+
+ ret = bcm54xx_config_clock_delay(phydev);
+ if (ret < 0)
+ return ret;
+
+ return bcm5461_config(phydev);
+}
+
static int bcm54xx_parse_status(struct phy_device *phydev)
{
unsigned int mii_reg;
@@ -311,6 +400,16 @@
return bcm54xx_parse_status(phydev);
}
+U_BOOT_PHY_DRIVER(bcm54210e) = {
+ .name = "Broadcom BCM54210E",
+ .uid = 0x600d84a0,
+ .mask = 0xfffffff0,
+ .features = PHY_GBIT_FEATURES,
+ .config = &bcm54210e_config,
+ .startup = &bcm54xx_startup,
+ .shutdown = &genphy_shutdown,
+};
+
U_BOOT_PHY_DRIVER(bcm5461s) = {
.name = "Broadcom BCM5461S",
.uid = 0x2060c0,
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 7111e36..b672603 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -10,6 +10,7 @@
#include <linux/bitops.h>
#include <linux/compat.h>
#include <malloc.h>
+#include <linux/printk.h>
#include <dm.h>
#include <dt-bindings/net/ti-dp83867.h>
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 8d32d73..f9d4782 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -81,7 +81,10 @@
/* RGMIIDCTL bits */
#define DP83869_RGMII_TX_CLK_DELAY_SHIFT 4
-#define DP83869_CLK_DELAY_DEF 7
+#define DP83869_CLK_DELAY_STEP 250
+#define DP83869_CLK_DELAY_MIN 250
+#define DP83869_CLK_DELAY_MAX 4000
+#define DP83869_CLK_DELAY_DEFAULT 2000
/* CFG2 bits */
#define MII_DP83869_CFG2_SPEEDOPT_10EN 0x0040
@@ -157,10 +160,6 @@
return 0;
}
-static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500,
- 1750, 2000, 2250, 2500, 2750, 3000,
- 3250, 3500, 3750, 4000};
-
static int dp83869_set_strapped_mode(struct phy_device *phydev)
{
struct dp83869_private *dp83869 = phydev->priv;
@@ -183,7 +182,6 @@
static int dp83869_of_init(struct phy_device *phydev)
{
struct dp83869_private * const dp83869 = phydev->priv;
- const int delay_entries = ARRAY_SIZE(dp83869_internal_delay);
int ret;
ofnode node;
@@ -238,32 +236,45 @@
dp83869->tx_fifo_depth = ofnode_read_s32_default(node, "tx-fifo-depth",
DP83869_PHYCR_FIFO_DEPTH_4_B_NIB);
+ /* Internal clock delay values can be configured in steps of
+ * 250ps (0.25ns). The register field for clock delay is 4-bits wide,
+ * the values range from 0b0000 for 0.25ns to 0b1111 for 4ns.
+ */
+
/* RX delay *must* be specified if internal delay of RX is used. */
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
- dp83869->rx_int_delay = ofnode_read_u32_default(node, "rx-internal-delay-ps",
- DP83869_CLK_DELAY_DEF);
- if (dp83869->rx_int_delay > delay_entries) {
- dp83869->rx_int_delay = DP83869_CLK_DELAY_DEF;
- pr_debug("rx-internal-delay-ps not set/invalid, default to %ups\n",
- dp83869_internal_delay[dp83869->rx_int_delay]);
+ dp83869->rx_int_delay = ofnode_read_u32_default(node,
+ "rx-internal-delay-ps", DP83869_CLK_DELAY_DEFAULT);
+ if (dp83869->rx_int_delay > DP83869_CLK_DELAY_MAX ||
+ dp83869->rx_int_delay < DP83869_CLK_DELAY_MIN ||
+ dp83869->rx_int_delay % DP83869_CLK_DELAY_STEP) {
+ dp83869->rx_int_delay = DP83869_CLK_DELAY_DEFAULT;
+ pr_warn("rx-internal-delay-ps not set/invalid, default"
+ " to %ups\n", DP83869_CLK_DELAY_DEFAULT);
}
- dp83869->rx_int_delay = dp83869_internal_delay[dp83869->rx_int_delay];
+ dp83869->rx_int_delay =
+ (dp83869->rx_int_delay - DP83869_CLK_DELAY_STEP)
+ / DP83869_CLK_DELAY_STEP;
}
- /* TX delay *must* be specified if internal delay of RX is used. */
+ /* TX delay *must* be specified if internal delay of TX is used. */
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
- dp83869->tx_int_delay = ofnode_read_u32_default(node, "tx-internal-delay-ps",
- DP83869_CLK_DELAY_DEF);
- if (dp83869->tx_int_delay > delay_entries) {
- dp83869->tx_int_delay = DP83869_CLK_DELAY_DEF;
- pr_debug("tx-internal-delay-ps not set/invalid, default to %ups\n",
- dp83869_internal_delay[dp83869->tx_int_delay]);
+ dp83869->tx_int_delay = ofnode_read_u32_default(node,
+ "tx-internal-delay-ps", DP83869_CLK_DELAY_DEFAULT);
+ if (dp83869->tx_int_delay > DP83869_CLK_DELAY_MAX ||
+ dp83869->tx_int_delay < DP83869_CLK_DELAY_MIN ||
+ dp83869->tx_int_delay % DP83869_CLK_DELAY_STEP) {
+ dp83869->tx_int_delay = DP83869_CLK_DELAY_DEFAULT;
+ pr_warn("tx-internal-delay-ps not set/invalid, default"
+ " to %ups\n", DP83869_CLK_DELAY_DEFAULT);
}
- dp83869->tx_int_delay = dp83869_internal_delay[dp83869->tx_int_delay];
+ dp83869->tx_int_delay =
+ (dp83869->tx_int_delay - DP83869_CLK_DELAY_STEP)
+ / DP83869_CLK_DELAY_STEP;
}
return 0;
diff --git a/drivers/net/phy/et1011c.c b/drivers/net/phy/et1011c.c
index fa48314..db879bc 100644
--- a/drivers/net/phy/et1011c.c
+++ b/drivers/net/phy/et1011c.c
@@ -3,7 +3,7 @@
* ET1011C PHY driver
*
* Derived from Linux kernel driver by Chaithrika U S
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <config.h>
#include <phy.h>
diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c
index 24d6175..cf71f7d 100644
--- a/drivers/net/phy/miiphybb.c
+++ b/drivers/net/phy/miiphybb.c
@@ -18,10 +18,6 @@
#include <miiphy.h>
#include <asm/global_data.h>
-#define BB_MII_RELOCATE(v,off) (v += (v?off:0))
-
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_BITBANGMII_MULTI
/*
@@ -110,21 +106,9 @@
{
int i;
- for (i = 0; i < bb_miiphy_buses_num; i++) {
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- /* Relocate the hook pointers*/
- BB_MII_RELOCATE(bb_miiphy_buses[i].init, gd->reloc_off);
- BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_active, gd->reloc_off);
- BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_tristate, gd->reloc_off);
- BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdio, gd->reloc_off);
- BB_MII_RELOCATE(bb_miiphy_buses[i].get_mdio, gd->reloc_off);
- BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdc, gd->reloc_off);
- BB_MII_RELOCATE(bb_miiphy_buses[i].delay, gd->reloc_off);
-#endif
- if (bb_miiphy_buses[i].init != NULL) {
+ for (i = 0; i < bb_miiphy_buses_num; i++)
+ if (bb_miiphy_buses[i].init != NULL)
bb_miiphy_buses[i].init(&bb_miiphy_buses[i]);
- }
- }
return 0;
}
diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
index e822fd7..8635a96 100644
--- a/drivers/net/phy/motorcomm.c
+++ b/drivers/net/phy/motorcomm.c
@@ -11,6 +11,7 @@
#include <phy.h>
#include <linux/bitfield.h>
+#define PHY_ID_YT8511 0x0000010a
#define PHY_ID_YT8531 0x4f51e91b
#define PHY_ID_MASK GENMASK(31, 0)
@@ -26,6 +27,31 @@
#define YTPHY_DTS_OUTPUT_CLK_25M 25000000
#define YTPHY_DTS_OUTPUT_CLK_125M 125000000
+#define YT8511_EXT_CLK_GATE 0x0c
+#define YT8511_EXT_DELAY_DRIVE 0x0d
+#define YT8511_EXT_SLEEP_CTRL 0x27
+
+/* 2b00 25m from pll
+ * 2b01 25m from xtl *default*
+ * 2b10 62.m from pll
+ * 2b11 125m from pll
+ */
+#define YT8511_CLK_125M (BIT(2) | BIT(1))
+#define YT8511_PLLON_SLP BIT(14)
+
+/* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */
+#define YT8511_DELAY_RX BIT(0)
+
+/* TX Gig-E Delay is bits 7:4, default 0x5
+ * TX Fast-E Delay is bits 15:12, default 0xf
+ * Delay = 150ps * N - 250ps
+ * On = 2000ps, off = 50ps
+ */
+#define YT8511_DELAY_GE_TX_EN (0xf << 4)
+#define YT8511_DELAY_GE_TX_DIS (0x2 << 4)
+#define YT8511_DELAY_FE_TX_EN (0xf << 12)
+#define YT8511_DELAY_FE_TX_DIS (0x2 << 12)
+
#define YT8531_SCR_SYNCE_ENABLE BIT(6)
/* 1b0 output 25m clock *default*
* 1b1 output 125m clock
@@ -347,6 +373,58 @@
priv->flag |= TX_CLK_1000_INVERTED;
}
+static int yt8511_config(struct phy_device *phydev)
+{
+ u32 ge, fe;
+ int ret;
+
+ ret = genphy_config_aneg(phydev);
+ if (ret < 0)
+ return ret;
+
+ switch (phydev->interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ ge = YT8511_DELAY_GE_TX_DIS;
+ fe = YT8511_DELAY_FE_TX_DIS;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_DIS;
+ fe = YT8511_DELAY_FE_TX_DIS;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ ge = YT8511_DELAY_GE_TX_EN;
+ fe = YT8511_DELAY_FE_TX_EN;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN;
+ fe = YT8511_DELAY_FE_TX_EN;
+ break;
+ default: /* do not support other modes */
+ return -EOPNOTSUPP;
+ }
+
+ ret = ytphy_modify_ext(phydev, YT8511_EXT_CLK_GATE,
+ (YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN), ge);
+ if (ret < 0)
+ return ret;
+ /* set clock mode to 125m */
+ ret = ytphy_modify_ext(phydev, YT8511_EXT_CLK_GATE,
+ YT8511_CLK_125M, YT8511_CLK_125M);
+ if (ret < 0)
+ return ret;
+ ret = ytphy_modify_ext(phydev, YT8511_EXT_DELAY_DRIVE,
+ YT8511_DELAY_FE_TX_EN, fe);
+ if (ret < 0)
+ return ret;
+ /* sleep control, disable PLL in sleep for now */
+ ret = ytphy_modify_ext(phydev, YT8511_EXT_SLEEP_CTRL, YT8511_PLLON_SLP,
+ 0);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
static int yt8531_config(struct phy_device *phydev)
{
struct ytphy_plat_priv *priv = phydev->priv;
@@ -425,6 +503,16 @@
return 0;
}
+U_BOOT_PHY_DRIVER(motorcomm8511) = {
+ .name = "YT8511 Gigabit Ethernet",
+ .uid = PHY_ID_YT8511,
+ .mask = PHY_ID_MASK,
+ .features = PHY_GBIT_FEATURES,
+ .config = &yt8511_config,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
U_BOOT_PHY_DRIVER(motorcomm8531) = {
.name = "YT8531 Gigabit Ethernet",
.uid = PHY_ID_YT8531,
diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index ef1761a..bd9cd95 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -15,6 +15,7 @@
#include <time.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <linux/printk.h>
/* Microsemi PHY ID's */
#define PHY_ID_VSC8530 0x00070560
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index ae21acb..63b3e46 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -463,37 +463,6 @@
.shutdown = genphy_shutdown,
};
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
-int phy_init(void)
-{
- const int ll_n_ents = ll_entry_count(struct phy_driver, phy_driver);
- struct phy_driver *drv, *ll_entry;
-
- /* Perform manual relocation on linker list based PHY drivers */
- ll_entry = ll_entry_start(struct phy_driver, phy_driver);
- for (drv = ll_entry; drv != ll_entry + ll_n_ents; drv++) {
- if (drv->probe)
- drv->probe += gd->reloc_off;
- if (drv->config)
- drv->config += gd->reloc_off;
- if (drv->startup)
- drv->startup += gd->reloc_off;
- if (drv->shutdown)
- drv->shutdown += gd->reloc_off;
- if (drv->readext)
- drv->readext += gd->reloc_off;
- if (drv->writeext)
- drv->writeext += gd->reloc_off;
- if (drv->read_mmd)
- drv->read_mmd += gd->reloc_off;
- if (drv->write_mmd)
- drv->write_mmd += gd->reloc_off;
- }
-
- return 0;
-}
-#endif
-
int phy_set_supported(struct phy_device *phydev, u32 max_speed)
{
/* The default values for phydev->supported are provided by the PHY
@@ -838,7 +807,10 @@
ofnode_for_each_subnode(node, dev_ofnode(dev)) {
node = ofnode_by_compatible(node, "xlnx,gmii-to-rgmii-1.0");
if (ofnode_valid(node)) {
- phydev = phy_device_create(bus, 0,
+ int gmiirgmii_phyaddr;
+
+ gmiirgmii_phyaddr = ofnode_read_u32_default(node, "reg", 0);
+ phydev = phy_device_create(bus, gmiirgmii_phyaddr,
PHY_GMII2RGMII_ID, false);
if (phydev)
phydev->node = node;
diff --git a/drivers/net/phy/xilinx_phy.c b/drivers/net/phy/xilinx_phy.c
index 1df639d..c07c780 100644
--- a/drivers/net/phy/xilinx_phy.c
+++ b/drivers/net/phy/xilinx_phy.c
@@ -99,7 +99,6 @@
static int xilinxphy_of_init(struct phy_device *phydev)
{
- u32 phytype;
ofnode node;
debug("%s\n", __func__);
@@ -107,10 +106,6 @@
if (!ofnode_valid(node))
return -EINVAL;
- phytype = ofnode_read_u32_default(node, "xlnx,phy-type", -1);
- if (phytype == XAE_PHY_TYPE_1000BASE_X)
- phydev->flags |= XAE_PHY_TYPE_1000BASE_X;
-
return 0;
}
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 9637027..93e83661 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -51,6 +51,7 @@
#include <asm/io.h>
#include <pci.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#undef DEBUG_RTL8169
#undef DEBUG_RTL8169_TX
diff --git a/drivers/net/sni_ave.c b/drivers/net/sni_ave.c
index f5a0d80..8eeecbc 100644
--- a/drivers/net/sni_ave.c
+++ b/drivers/net/sni_ave.c
@@ -23,6 +23,7 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/iopoll.h>
+#include <linux/printk.h>
#define AVE_GRST_DELAY_MSEC 40
#define AVE_MIN_XMITSIZE 60
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 04c3274..a12f7e3 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -29,6 +29,7 @@
#include <net.h>
#include <reset.h>
#include <wait_bit.h>
+#include <power/regulator.h>
#define MDIO_CMD_MII_BUSY BIT(0)
#define MDIO_CMD_MII_WRITE BIT(1)
@@ -167,9 +168,8 @@
struct clk ephy_clk;
struct reset_ctl tx_rst;
struct reset_ctl ephy_rst;
-#if CONFIG_IS_ENABLED(DM_GPIO)
struct gpio_desc reset_gpio;
-#endif
+ struct udevice *phy_reg;
};
@@ -615,7 +615,6 @@
return ret;
}
-#if CONFIG_IS_ENABLED(DM_GPIO)
static int sun8i_mdio_reset(struct mii_dev *bus)
{
struct udevice *dev = bus->priv;
@@ -647,7 +646,6 @@
return 0;
}
-#endif
static int sun8i_mdio_init(const char *name, struct udevice *priv)
{
@@ -662,9 +660,7 @@
bus->write = sun8i_mdio_write;
snprintf(bus->name, sizeof(bus->name), name);
bus->priv = (void *)priv;
-#if CONFIG_IS_ENABLED(DM_GPIO)
bus->reset = sun8i_mdio_reset;
-#endif
return mdio_register(bus);
}
@@ -720,6 +716,9 @@
sun8i_emac_set_syscon(sun8i_pdata, priv);
+ if (priv->phy_reg)
+ regulator_set_enable(priv->phy_reg, true);
+
sun8i_mdio_init(dev->name, dev);
priv->bus = miiphy_get_dev_by_name(dev->name);
@@ -778,9 +777,7 @@
const fdt32_t *reg;
int node = dev_of_offset(dev);
int offset = 0;
-#if CONFIG_IS_ENABLED(DM_GPIO)
int reset_flags = GPIOD_IS_OUT;
-#endif
int ret;
pdata->iobase = dev_read_addr(dev);
@@ -829,6 +826,8 @@
priv->sysctl_reg = (void *)syscon_base + priv->variant->syscon_offset;
+ device_get_supply_regulator(dev, "phy-supply", &priv->phy_reg);
+
pdata->phy_interface = -1;
priv->phyaddr = -1;
priv->use_internal_phy = false;
@@ -865,7 +864,6 @@
printf("%s: Invalid RX delay value %d\n", __func__,
sun8i_pdata->rx_delay_ps);
-#if CONFIG_IS_ENABLED(DM_GPIO)
if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
"snps,reset-active-low"))
reset_flags |= GPIOD_ACTIVE_LOW;
@@ -880,7 +878,6 @@
} else if (ret == -ENOENT) {
ret = 0;
}
-#endif
return 0;
}
diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
index 4c90d4b..f546ad1 100644
--- a/drivers/net/sunxi_emac.c
+++ b/drivers/net/sunxi_emac.c
@@ -17,6 +17,7 @@
#include <net.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
+#include <power/regulator.h>
/* EMAC register */
struct emac_regs {
@@ -165,6 +166,7 @@
struct phy_device *phydev;
int link_printed;
uchar rx_buf[EMAC_RX_BUFSIZE];
+ struct udevice *phy_reg;
};
struct emac_rxhdr {
@@ -572,6 +574,9 @@
if (ret)
return ret;
+ if (priv->phy_reg)
+ regulator_set_enable(priv->phy_reg, true);
+
return sunxi_emac_init_phy(priv, dev);
}
@@ -585,9 +590,42 @@
static int sunxi_emac_eth_of_to_plat(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
+ struct emac_eth_dev *priv = dev_get_priv(dev);
+ struct ofnode_phandle_args args;
+ ofnode phy_node, mdio_node;
+ int ret;
pdata->iobase = dev_read_addr(dev);
+ phy_node = dev_get_phy_node(dev);
+ if (!ofnode_valid(phy_node)) {
+ dev_err(dev, "failed to get PHY node\n");
+ return -ENOENT;
+ }
+ /*
+ * The PHY regulator is in the MDIO node, not the EMAC or PHY node.
+ * U-Boot does not have (and does not need) a device driver for the
+ * MDIO device, so just "pass through" that DT node to get to the
+ * regulator phandle.
+ * The PHY regulator is optional, though: ignore if we cannot find
+ * a phy-supply property.
+ */
+ mdio_node = ofnode_get_parent(phy_node);
+ ret= ofnode_parse_phandle_with_args(mdio_node, "phy-supply", NULL, 0, 0,
+ &args);
+ if (ret && ret != -ENOENT) {
+ dev_err(dev, "failed to get PHY supply node\n");
+ return ret;
+ }
+ if (!ret) {
+ ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR, args.node,
+ &priv->phy_reg);
+ if (ret) {
+ dev_err(dev, "failed to get PHY regulator node\n");
+ return ret;
+ }
+ }
+
return 0;
}
diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig
index 02660e4..c75f4186 100644
--- a/drivers/net/ti/Kconfig
+++ b/drivers/net/ti/Kconfig
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
config DRIVER_TI_CPSW
bool "TI Common Platform Ethernet Switch"
diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile
index 8d3808b..0ce0cf2 100644
--- a/drivers/net/ti/Makefile
+++ b/drivers/net/ti/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o cpsw_mdio.o
obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index 51a8167..18a33c4 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <malloc.h>
#include <asm/cache.h>
+#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <clk.h>
@@ -26,6 +27,8 @@
#include <soc.h>
#include <syscon.h>
#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/printk.h>
#include <linux/soc/ti/ti-udma.h>
#include "cpsw_mdio.h"
@@ -57,6 +60,12 @@
#define AM65_CPSW_PN_REG_SA_L 0x308
#define AM65_CPSW_PN_REG_SA_H 0x30c
+#define AM65_CPSW_SGMII_CONTROL_REG 0x010
+#define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG 0x018
+#define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0)
+
+#define ADVERTISE_SGMII 0x1
+
#define AM65_CPSW_ALE_CTL_REG 0x8
#define AM65_CPSW_ALE_CTL_REG_ENABLE BIT(31)
#define AM65_CPSW_ALE_CTL_REG_RESET_TBL BIT(30)
@@ -90,8 +99,11 @@
#define AM65_CPSW_CPPI_PKT_TYPE 0x7
+#define DEFAULT_GPIO_RESET_DELAY 10
+
struct am65_cpsw_port {
fdt_addr_t port_base;
+ fdt_addr_t port_sgmii_base;
fdt_addr_t macsl_base;
bool disabled;
u32 mac_control;
@@ -113,6 +125,10 @@
struct mii_dev *bus;
u32 bus_freq;
+ struct gpio_desc mdio_gpio_reset;
+ u32 reset_delay_us;
+ u32 reset_post_delay_us;
+
struct dma dma_tx;
struct dma dma_rx;
u32 rx_next;
@@ -204,6 +220,8 @@
mac_control |= AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX;
if (phy->speed == 100)
mac_control |= AM65_CPSW_MACSL_CTL_REG_IFCTL_A;
+ if (phy->interface == PHY_INTERFACE_MODE_SGMII)
+ mac_control |= AM65_CPSW_MACSL_CTL_EXT_EN;
}
if (mac_control == port->mac_control)
@@ -229,6 +247,7 @@
#define AM65_GMII_SEL_MODE_MII 0
#define AM65_GMII_SEL_MODE_RMII 1
#define AM65_GMII_SEL_MODE_RGMII 2
+#define AM65_GMII_SEL_MODE_SGMII 3
#define AM65_GMII_SEL_RGMII_IDMODE BIT(4)
@@ -280,6 +299,10 @@
rgmii_id = true;
break;
+ case PHY_INTERFACE_MODE_SGMII:
+ mode = AM65_GMII_SEL_MODE_SGMII;
+ break;
+
default:
dev_warn(dev,
"Unsupported PHY mode: %u. Defaulting to MII.\n",
@@ -420,6 +443,13 @@
goto err_dis_rx;
}
+ if (priv->phydev->interface == PHY_INTERFACE_MODE_SGMII) {
+ writel(ADVERTISE_SGMII,
+ port->port_sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG);
+ writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE,
+ port->port_sgmii_base + AM65_CPSW_SGMII_CONTROL_REG);
+ }
+
ret = phy_startup(priv->phydev);
if (ret) {
dev_err(dev, "phy_startup failed\n");
@@ -658,6 +688,16 @@
if (!priv->has_phy || cpsw_common->bus)
return 0;
+ if (IS_ENABLED(CONFIG_DM_GPIO)) {
+ if (dm_gpio_is_valid(&cpsw_common->mdio_gpio_reset)) {
+ dm_gpio_set_value(&cpsw_common->mdio_gpio_reset, 1);
+ udelay(cpsw_common->reset_delay_us);
+ dm_gpio_set_value(&cpsw_common->mdio_gpio_reset, 0);
+ if (cpsw_common->reset_post_delay_us > 0)
+ udelay(cpsw_common->reset_post_delay_us);
+ }
+ }
+
ret = am65_cpsw_mdio_setup(dev);
if (ret)
return ret;
@@ -797,7 +837,7 @@
static int am65_cpsw_probe_nuss(struct udevice *dev)
{
struct am65_cpsw_common *cpsw_common = dev_get_priv(dev);
- ofnode ports_np, node;
+ ofnode ports_np, node, mdio_np;
int ret, i;
struct udevice *port_dev;
@@ -824,6 +864,24 @@
AM65_CPSW_CPSW_NU_ALE_BASE;
cpsw_common->mdio_base = cpsw_common->ss_base + AM65_CPSW_MDIO_BASE;
+ if (IS_ENABLED(CONFIG_DM_GPIO)) {
+ /* get bus level PHY reset GPIO details */
+ mdio_np = dev_read_subnode(dev, "mdio");
+ if (!ofnode_valid(mdio_np)) {
+ ret = -ENOENT;
+ goto out;
+ }
+
+ cpsw_common->reset_delay_us = ofnode_read_u32_default(mdio_np, "reset-delay-us",
+ DEFAULT_GPIO_RESET_DELAY);
+ cpsw_common->reset_post_delay_us = ofnode_read_u32_default(mdio_np,
+ "reset-post-delay-us",
+ 0);
+ ret = gpio_request_by_name_nodev(mdio_np, "reset-gpios", 0,
+ &cpsw_common->mdio_gpio_reset,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+ }
+
ports_np = dev_read_subnode(dev, "ethernet-ports");
if (!ofnode_valid(ports_np)) {
ret = -ENOENT;
@@ -872,6 +930,8 @@
port->port_base = cpsw_common->cpsw_base +
AM65_CPSW_CPSW_NU_PORTS_OFFSET +
(i * AM65_CPSW_CPSW_NU_PORTS_OFFSET);
+ port->port_sgmii_base = cpsw_common->ss_base +
+ (i * AM65_CPSW_SGMII_BASE);
port->macsl_base = port->port_base +
AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET;
}
diff --git a/drivers/net/ti/cpsw-common.c b/drivers/net/ti/cpsw-common.c
index 3140f25..d542827 100644
--- a/drivers/net/ti/cpsw-common.c
+++ b/drivers/net/ti/cpsw-common.c
@@ -12,6 +12,7 @@
#include <asm/io.h>
#include <cpsw.h>
#include <dm/device_compat.h>
+#include <linux/printk.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index 3a8cc9c..9a5e964 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -2,7 +2,7 @@
/*
* CPSW Ethernet Switch Driver
*
- * Copyright (C) 2010-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010-2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
@@ -24,6 +24,7 @@
#include <phy.h>
#include <asm/arch/cpu.h>
#include <dm.h>
+#include <linux/printk.h>
#include "cpsw_mdio.h"
diff --git a/drivers/net/ti/cpsw_mdio.c b/drivers/net/ti/cpsw_mdio.c
index ac791fa..74cc956 100644
--- a/drivers/net/ti/cpsw_mdio.c
+++ b/drivers/net/ti/cpsw_mdio.c
@@ -2,7 +2,7 @@
/*
* CPSW MDIO generic driver for TI AMxx/K2x/EMAC devices.
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/drivers/net/ti/cpsw_mdio.h b/drivers/net/ti/cpsw_mdio.h
index 9b98763..ddf65a4 100644
--- a/drivers/net/ti/cpsw_mdio.h
+++ b/drivers/net/ti/cpsw_mdio.h
@@ -2,7 +2,7 @@
/*
* CPSW MDIO generic driver API for TI AMxx/K2x/EMAC devices.
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef CPSW_MDIO_H_
diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c
index 89b04b6..43dbf3f 100644
--- a/drivers/net/ti/keystone_net.c
+++ b/drivers/net/ti/keystone_net.c
@@ -10,6 +10,7 @@
#include <console.h>
#include <asm/global_data.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <dm.h>
#include <dm/lists.h>
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 39cb3cc..54f2232 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -112,7 +112,7 @@
int pcsaddr;
int phyaddr;
u8 eth_hasnobuf;
- int phy_of_handle;
+ ofnode phynode;
enum emac_variant mactype;
};
@@ -127,7 +127,7 @@
struct phy_device *phydev;
struct mii_dev *bus;
u8 eth_hasnobuf;
- int phy_of_handle;
+ ofnode phynode;
enum emac_variant mactype;
};
@@ -335,8 +335,8 @@
phydev->supported &= supported;
phydev->advertising = phydev->supported;
priv->phydev = phydev;
- if (priv->phy_of_handle)
- priv->phydev->node = offset_to_ofnode(priv->phy_of_handle);
+ if (ofnode_valid(priv->phynode))
+ priv->phydev->node = priv->phynode;
phy_config(phydev);
return 0;
@@ -839,7 +839,7 @@
priv->eth_hasnobuf = plat->eth_hasnobuf;
priv->pcsaddr = plat->pcsaddr;
priv->phyaddr = plat->phyaddr;
- priv->phy_of_handle = plat->phy_of_handle;
+ priv->phynode = plat->phynode;
priv->interface = pdata->phy_interface;
if (IS_ENABLED(CONFIG_DM_ETH_PHY))
@@ -894,20 +894,21 @@
{
struct axidma_plat *plat = dev_get_plat(dev);
struct eth_pdata *pdata = &plat->eth_pdata;
- int node = dev_of_offset(dev);
- int offset = 0;
+ struct ofnode_phandle_args pcs_node, axistream_node;
+ ofnode phynode;
+ int ret;
pdata->iobase = dev_read_addr(dev);
plat->mactype = dev_get_driver_data(dev);
- offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
- "axistream-connected");
- if (offset <= 0) {
+ ret = dev_read_phandle_with_args(dev, "axistream-connected", NULL, 0, 0,
+ &axistream_node);
+ if (ret) {
printf("%s: axistream is not found\n", __func__);
return -EINVAL;
}
- plat->dmatx = (struct axidma_reg *)fdtdec_get_addr_size_auto_parent
- (gd->fdt_blob, 0, offset, "reg", 0, NULL, false);
+
+ plat->dmatx = (struct axidma_reg *)ofnode_get_addr(axistream_node.node);
if (!plat->dmatx) {
printf("%s: axi_dma register space not found\n", __func__);
return -EINVAL;
@@ -918,30 +919,27 @@
/* PHYAD 0 always redirects to the PCS/PMA PHY */
plat->pcsaddr = 0;
- offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
- "phy-handle");
- if (offset > 0) {
+ phynode = dev_get_phy_node(dev);
+ if (ofnode_valid(phynode)) {
if (!(IS_ENABLED(CONFIG_DM_ETH_PHY)))
- plat->phyaddr = fdtdec_get_int(gd->fdt_blob,
- offset,
- "reg", -1);
- plat->phy_of_handle = offset;
+ plat->phyaddr = ofnode_read_u32_default(phynode,
+ "reg", -1);
+ plat->phynode = phynode;
}
pdata->phy_interface = dev_read_phy_mode(dev);
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
- plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
- "xlnx,eth-hasnobuf");
+ plat->eth_hasnobuf = dev_read_bool(dev, "xlnx,eth-hasnobuf");
if (pdata->phy_interface == PHY_INTERFACE_MODE_SGMII ||
pdata->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
- offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
- "pcs-handle");
- if (offset > 0) {
- plat->pcsaddr = fdtdec_get_int(gd->fdt_blob,
- offset, "reg", -1);
+ ret = dev_read_phandle_with_args(dev, "pcs-handle", NULL, 0, 0,
+ &pcs_node);
+ if (!ret) {
+ plat->pcsaddr = ofnode_read_u32_default(pcs_node.node,
+ "reg", -1);
}
}
}
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index f3cdfb0..7c57d32 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -321,11 +321,38 @@
return 0;
}
+static u32 gem_mdc_clk_div(struct zynq_gem_priv *priv)
+{
+ u32 config;
+ unsigned long pclk_hz;
+
+ pclk_hz = clk_get_rate(&priv->pclk);
+ if (pclk_hz <= 20000000)
+ config = GEM_MDC_SET(GEM_CLK_DIV8);
+ else if (pclk_hz <= 40000000)
+ config = GEM_MDC_SET(GEM_CLK_DIV16);
+ else if (pclk_hz <= 80000000)
+ config = GEM_MDC_SET(GEM_CLK_DIV32);
+ else if (pclk_hz <= 120000000)
+ config = GEM_MDC_SET(GEM_CLK_DIV48);
+ else if (pclk_hz <= 160000000)
+ config = GEM_MDC_SET(GEM_CLK_DIV64);
+ else if (pclk_hz <= 240000000)
+ config = GEM_MDC_SET(GEM_CLK_DIV96);
+ else if (pclk_hz <= 320000000)
+ config = GEM_MDC_SET(GEM_CLK_DIV128);
+ else
+ config = GEM_MDC_SET(GEM_CLK_DIV224);
+
+ return config;
+}
+
static int zynq_phy_init(struct udevice *dev)
{
- int ret;
+ int ret, val;
struct zynq_gem_priv *priv = dev_get_priv(dev);
struct zynq_gem_regs *regs_mdio = priv->mdiobase;
+ struct zynq_gem_regs *regs = priv->iobase;
const u32 supported = SUPPORTED_10baseT_Half |
SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Half |
@@ -333,6 +360,10 @@
SUPPORTED_1000baseT_Half |
SUPPORTED_1000baseT_Full;
+ val = gem_mdc_clk_div(priv);
+ if (val)
+ writel(val, ®s->nwcfg);
+
/* Enable only MDIO bus */
writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s_mdio->nwctrl);
@@ -360,35 +391,10 @@
return phy_config(priv->phydev);
}
-static u32 gem_mdc_clk_div(struct zynq_gem_priv *priv)
-{
- u32 config;
- unsigned long pclk_hz;
-
- pclk_hz = clk_get_rate(&priv->pclk);
- if (pclk_hz <= 20000000)
- config = GEM_MDC_SET(GEM_CLK_DIV8);
- else if (pclk_hz <= 40000000)
- config = GEM_MDC_SET(GEM_CLK_DIV16);
- else if (pclk_hz <= 80000000)
- config = GEM_MDC_SET(GEM_CLK_DIV32);
- else if (pclk_hz <= 120000000)
- config = GEM_MDC_SET(GEM_CLK_DIV48);
- else if (pclk_hz <= 160000000)
- config = GEM_MDC_SET(GEM_CLK_DIV64);
- else if (pclk_hz <= 240000000)
- config = GEM_MDC_SET(GEM_CLK_DIV96);
- else if (pclk_hz <= 320000000)
- config = GEM_MDC_SET(GEM_CLK_DIV128);
- else
- config = GEM_MDC_SET(GEM_CLK_DIV224);
-
- return config;
-}
static int zynq_gem_init(struct udevice *dev)
{
- u32 i, nwconfig;
+ u32 i, nwconfig, nwcfg;
int ret;
unsigned long clk_rate = 0;
struct zynq_gem_priv *priv = dev_get_priv(dev);
@@ -494,8 +500,7 @@
return -1;
}
- nwconfig = gem_mdc_clk_div(priv);
- nwconfig |= ZYNQ_GEM_NWCFG_INIT;
+ nwconfig = ZYNQ_GEM_NWCFG_INIT;
/*
* Set SGMII enable PCS selection only if internal PCS/PMA
@@ -509,19 +514,21 @@
switch (priv->phydev->speed) {
case SPEED_1000:
- writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000,
- ®s->nwcfg);
+ nwconfig |= ZYNQ_GEM_NWCFG_SPEED1000;
clk_rate = ZYNQ_GEM_FREQUENCY_1000;
break;
case SPEED_100:
- writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100,
- ®s->nwcfg);
+ nwconfig |= ZYNQ_GEM_NWCFG_SPEED100;
clk_rate = ZYNQ_GEM_FREQUENCY_100;
break;
case SPEED_10:
clk_rate = ZYNQ_GEM_FREQUENCY_10;
break;
}
+ nwcfg = readl(®s->nwcfg);
+ nwcfg |= nwconfig;
+ if (nwcfg)
+ writel(nwcfg, ®s->nwcfg);
#ifdef CONFIG_ARM64
if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
@@ -890,7 +897,8 @@
if (ret)
goto err3;
- if (priv->interface == PHY_INTERFACE_MODE_SGMII && phy.dev) {
+ if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
+ generic_phy_valid(&phy)) {
if (IS_ENABLED(CONFIG_DM_ETH_PHY)) {
if (device_is_compatible(dev, "cdns,zynqmp-gem") ||
device_is_compatible(dev, "xlnx,zynqmp-gem")) {
diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index 20dc910..c39cd41 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -906,7 +906,7 @@
/* The real blksz and size will be set by nvme_blk_probe() */
ret = blk_create_devicef(udev, "nvme-blk", name, UCLASS_NVME,
- -1, 512, 0, &ns_udev);
+ -1, DEFAULT_BLKSZ, 0, &ns_udev);
if (ret)
goto free_id;
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 3abfdd7..4d0d649 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -131,11 +131,18 @@
bool "Enable Apple PCIe driver"
depends on ARCH_APPLE
imply PCI_INIT_R
+ select SYS_PCI_64BIT
default y
help
Say Y here if you want to enable PCIe controller support on
Apple SoCs.
+config PCI_FTPCI100
+ bool "Enable Faraday FTPCI100 PCI Bridge Controller driver"
+ help
+ Say Y here if you want to enable Faraday FTPCI100 PCI.
+ FTPCI100 IP is used in SoC chip designs.
+
config PCI_GT64120
bool "GT64120 PCI support"
depends on MIPS
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index a712a31..72ef8b4 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -14,6 +14,7 @@
obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o
obj-$(CONFIG_PCIE_ECAM_SYNQUACER) += pcie_ecam_synquacer.o
obj-$(CONFIG_PCIE_APPLE) += pcie_apple.o
+obj-$(CONFIG_PCI_FTPCI100) += pci_ftpci100.o
obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
obj-$(CONFIG_PCI_MPC85XX) += pci_mpc85xx.o
obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 632c1a6..e0d01f6 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -24,6 +24,7 @@
#endif
#include <dt-bindings/pci/pci.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include "pci_internal.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -122,7 +123,7 @@
dev_for_each_subnode(node, bus) {
ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
- &addr);
+ &addr, NULL);
if (ret)
continue;
@@ -541,14 +542,13 @@
struct pci_child_plat *pplat;
unsigned int sub_bus;
struct udevice *dev;
- int ret;
sub_bus = dev_seq(bus);
debug("%s: start\n", __func__);
pciauto_config_init(hose);
- for (ret = device_find_first_child(bus, &dev);
- !ret && dev;
- ret = device_find_next_child(&dev)) {
+ for (device_find_first_child(bus, &dev);
+ dev;
+ device_find_next_child(&dev)) {
unsigned int max_bus;
int ret;
@@ -1446,7 +1446,7 @@
return res->phys_start + offset;
}
- puts("pci_hose_bus_to_phys: invalid physical address\n");
+ puts("dm_pci_bus_to_phys: invalid physical address\n");
return 0;
}
@@ -1486,7 +1486,7 @@
return res->bus_start + offset;
}
- puts("pci_hose_phys_to_bus: invalid physical address\n");
+ puts("dm_pci_phys_to_bus: invalid physical address\n");
return 0;
}
diff --git a/drivers/pci/pci_ftpci100.c b/drivers/pci/pci_ftpci100.c
new file mode 100644
index 0000000..a177544
--- /dev/null
+++ b/drivers/pci/pci_ftpci100.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <common.h>
+#include <pci.h>
+#include <dm.h>
+#include <asm/io.h>
+
+struct ftpci100_data {
+ void *reg_base;
+};
+
+/* AHB Control Registers */
+struct ftpci100_ahbc {
+ u32 iosize; /* 0x00 - I/O Space Size Signal */
+ u32 prot; /* 0x04 - AHB Protection */
+ u32 rsved[8]; /* 0x08-0x24 - Reserved */
+ u32 conf; /* 0x28 - PCI Configuration */
+ u32 data; /* 0x2c - PCI Configuration DATA */
+};
+
+static int ftpci100_read_config(const struct udevice *dev, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ struct ftpci100_data *priv = dev_get_priv(dev);
+ struct ftpci100_ahbc *regs = priv->reg_base;
+ u32 data;
+
+ out_le32(®s->conf, PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset));
+ data = in_le32(®s->data);
+ *valuep = pci_conv_32_to_size(data, offset, size);
+
+ return 0;
+}
+
+static int ftpci100_write_config(struct udevice *dev, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ struct ftpci100_data *priv = dev_get_priv(dev);
+ struct ftpci100_ahbc *regs = priv->reg_base;
+ u32 data;
+
+ out_le32(®s->conf, PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset));
+
+ if (size == PCI_SIZE_32) {
+ data = value;
+ } else {
+ u32 old = in_le32(®s->data);
+
+ data = pci_conv_size_to_32(old, value, offset, size);
+ }
+
+ out_le32(®s->data, data);
+
+ return 0;
+}
+
+static int ftpci100_probe(struct udevice *dev)
+{
+ struct ftpci100_data *priv = dev_get_priv(dev);
+ struct pci_region *io, *mem;
+ int count;
+
+ count = pci_get_regions(dev, &io, &mem, NULL);
+ if (count != 2) {
+ printf("%s: wrong count of regions: %d != 2\n", dev->name, count);
+ return -EINVAL;
+ }
+
+ priv->reg_base = phys_to_virt(io->phys_start);
+ if (!priv->reg_base)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct dm_pci_ops ftpci100_ops = {
+ .read_config = ftpci100_read_config,
+ .write_config = ftpci100_write_config,
+};
+
+static const struct udevice_id ftpci100_ids[] = {
+ { .compatible = "faraday,ftpci100" },
+ { }
+};
+
+U_BOOT_DRIVER(ftpci100_pci) = {
+ .name = "ftpci100_pci",
+ .id = UCLASS_PCI,
+ .of_match = ftpci100_ids,
+ .ops = &ftpci100_ops,
+ .probe = ftpci100_probe,
+ .priv_auto = sizeof(struct ftpci100_data),
+};
diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index 93a7508..8355955 100644
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -28,6 +28,7 @@
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/mbus.h>
+#include <linux/printk.h>
#include <linux/sizes.h>
/* PCIe unit register offsets */
@@ -640,7 +641,8 @@
pcie->is_x4 = true;
/* devfn is in bits [15:8], see PCI_DEV usage */
- ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg", &pci_addr);
+ ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg", &pci_addr,
+ NULL);
if (ret < 0) {
printf("%s: property \"reg\" is invalid\n", pcie->name);
goto err;
diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c
index 29d5411..d6374a5 100644
--- a/drivers/pci/pci_tegra.c
+++ b/drivers/pci/pci_tegra.c
@@ -22,6 +22,7 @@
#include <power-domain.h>
#include <reset.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <asm/io.h>
#include <asm/gpio.h>
@@ -461,7 +462,7 @@
*lanes = err;
- err = ofnode_read_pci_addr(node, 0, "reg", &addr);
+ err = ofnode_read_pci_addr(node, 0, "reg", &addr, NULL);
if (err < 0) {
pr_err("failed to parse \"reg\" property\n");
return err;
diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c
index 1de2802..cd45f0b 100644
--- a/drivers/pci/pcie_brcmstb.c
+++ b/drivers/pci/pcie_brcmstb.c
@@ -33,6 +33,9 @@
#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
#define CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
+#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
+#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
+
#define PCIE_RC_DL_MDIO_ADDR 0x1100
#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
@@ -88,7 +91,6 @@
PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
-#define PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
#define PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
#define PCIE_MSI_INTR2_CLR 0x4508
@@ -223,6 +225,10 @@
return 0;
}
+ /* An access to our HW w/o link-up will cause a CPU Abort */
+ if (!brcm_pcie_link_up(pcie))
+ return -EINVAL;
+
/* For devices, write to the config space index register */
idx = PCIE_ECAM_OFFSET(pci_bus, pci_dev, pci_func, 0);
@@ -505,6 +511,12 @@
clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1,
RGR1_SW_INIT_1_PERST_MASK);
+ /*
+ * Wait for 100ms after PERST# deassertion; see PCIe CEM specification
+ * sections 2.2, PCIe r5.0, 6.6.1.
+ */
+ mdelay(100);
+
/* Give the RC/EP time to wake up, before trying to configure RC.
* Intermittently check status for link-up, up to a total of 100ms.
*/
@@ -562,12 +574,18 @@
clrsetbits_le32(base + PCIE_RC_CFG_VENDOR_SPECIFIC_REG1,
VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK,
VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN);
+
/*
- * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
- * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
+ * We used to enable the CLKREQ# input here, but a few PCIe cards don't
+ * attach anything to the CLKREQ# line, so we shouldn't assume that
+ * it's connected and working. The controller does allow detecting
+ * whether the port on the other side of our link is/was driving this
+ * signal, so we could check before we assume. But because this signal
+ * is for power management, which doesn't make sense in a bootloader,
+ * let's instead just unadvertise ASPM support.
*/
- setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
- PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK);
+ clrbits_le32(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY,
+ PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
return 0;
}
diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 1a35fae..bc4635f 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -18,6 +18,7 @@
#include <asm/io.h>
#include <asm-generic/gpio.h>
#include <dm/device_compat.h>
+#include <linux/bitfield.h>
#include <linux/iopoll.h>
#include <linux/delay.h>
#include <power/regulator.h>
@@ -43,6 +44,7 @@
struct reset_ctl_bulk rsts;
struct gpio_desc rst_gpio;
u32 gen;
+ u32 num_lanes;
};
/* Parameters for the waiting for iATU enabled routine */
@@ -152,12 +154,13 @@
* rk_pcie_configure() - Configure link capabilities and speed
*
* @rk_pcie: Pointer to the PCI controller state
- * @cap_speed: The capabilities and speed to configure
*
* Configure the link capabilities and speed in the PCIe root complex.
*/
-static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed)
+static void rk_pcie_configure(struct rk_pcie *pci)
{
+ u32 val;
+
dw_pcie_dbi_write_enable(&pci->dw, true);
/* Disable BAR 0 and BAR 1 */
@@ -167,11 +170,49 @@
PCI_BASE_ADDRESS_1);
clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY,
- TARGET_LINK_SPEED_MASK, cap_speed);
+ TARGET_LINK_SPEED_MASK, pci->gen);
clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CTL_2,
- TARGET_LINK_SPEED_MASK, cap_speed);
+ TARGET_LINK_SPEED_MASK, pci->gen);
+ /* Set the number of lanes */
+ val = readl(pci->dw.dbi_base + PCIE_PORT_LINK_CONTROL);
+ val &= ~PORT_LINK_FAST_LINK_MODE;
+ val |= PORT_LINK_DLL_LINK_EN;
+ val &= ~PORT_LINK_MODE_MASK;
+ switch (pci->num_lanes) {
+ case 1:
+ val |= PORT_LINK_MODE_1_LANES;
+ break;
+ case 2:
+ val |= PORT_LINK_MODE_2_LANES;
+ break;
+ case 4:
+ val |= PORT_LINK_MODE_4_LANES;
+ break;
+ default:
+ dev_err(pci->dw.dev, "num-lanes %u: invalid value\n", pci->num_lanes);
+ goto out;
+ }
+ writel(val, pci->dw.dbi_base + PCIE_PORT_LINK_CONTROL);
+
+ /* Set link width speed control register */
+ val = readl(pci->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
+ val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
+ switch (pci->num_lanes) {
+ case 1:
+ val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
+ break;
+ case 2:
+ val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
+ break;
+ case 4:
+ val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
+ break;
+ }
+ writel(val, pci->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
+
+out:
dw_pcie_dbi_write_enable(&pci->dw, false);
}
@@ -231,11 +272,10 @@
* rk_pcie_link_up() - Wait for the link to come up
*
* @rk_pcie: Pointer to the PCI controller state
- * @cap_speed: Desired link speed
*
* Return: 1 (true) for active line and negetive (false) for no link (timeout)
*/
-static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed)
+static int rk_pcie_link_up(struct rk_pcie *priv)
{
int retries;
@@ -245,7 +285,7 @@
}
/* DW pre link configurations */
- rk_pcie_configure(priv, cap_speed);
+ rk_pcie_configure(priv);
rk_pcie_disable_ltssm(priv);
rk_pcie_link_status_clear(priv);
@@ -341,7 +381,7 @@
rk_pcie_writel_apb(priv, 0x0, 0xf00040);
pcie_dw_setup_host(&priv->dw);
- ret = rk_pcie_link_up(priv, priv->gen);
+ ret = rk_pcie_link_up(priv);
if (ret < 0)
goto err_link_up;
@@ -419,6 +459,8 @@
priv->gen = dev_read_u32_default(dev, "max-link-speed",
LINK_SPEED_GEN_3);
+ priv->num_lanes = dev_read_u32_default(dev, "num-lanes", 1);
+
return 0;
rockchip_pcie_parse_dt_err_phy_get_by_index:
diff --git a/drivers/pci/pcie_ecam_generic.c b/drivers/pci/pcie_ecam_generic.c
index ea316e8..09d8b82 100644
--- a/drivers/pci/pcie_ecam_generic.c
+++ b/drivers/pci/pcie_ecam_generic.c
@@ -11,6 +11,7 @@
#include <dm.h>
#include <pci.h>
#include <asm/global_data.h>
+#include <linux/printk.h>
#include <asm/io.h>
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 8d89a1e..ec917ee 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -16,6 +16,7 @@
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include "pcie_fsl.h"
#include <dm/device_compat.h>
diff --git a/drivers/pci/pcie_mediatek.c b/drivers/pci/pcie_mediatek.c
index c6e30e2..f0f34b5 100644
--- a/drivers/pci/pcie_mediatek.c
+++ b/drivers/pci/pcie_mediatek.c
@@ -20,6 +20,7 @@
#include <linux/bitops.h>
#include <linux/iopoll.h>
#include <linux/list.h>
+#include <linux/printk.h>
#include "pci_internal.h"
/* PCIe shared registers */
@@ -660,7 +661,7 @@
if (!ofnode_is_enabled(subnode))
continue;
- err = ofnode_read_pci_addr(subnode, 0, "reg", &addr);
+ err = ofnode_read_pci_addr(subnode, 0, "reg", &addr, NULL);
if (err)
return err;
@@ -699,7 +700,7 @@
if (!ofnode_is_enabled(subnode))
continue;
- err = ofnode_read_pci_addr(subnode, 0, "reg", &addr);
+ err = ofnode_read_pci_addr(subnode, 0, "reg", &addr, NULL);
if (err)
return err;
diff --git a/drivers/pci/pcie_phytium.c b/drivers/pci/pcie_phytium.c
index a807276..3bd1f5c 100644
--- a/drivers/pci/pcie_phytium.c
+++ b/drivers/pci/pcie_phytium.c
@@ -12,6 +12,7 @@
#include <pci.h>
#include <asm/global_data.h>
#include <asm/io.h>
+#include <linux/printk.h>
/**
* struct phytium_pcie - phytium PCIe controller state
diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c
index eb9ec97..53fd121 100644
--- a/drivers/pci/pcie_xilinx.c
+++ b/drivers/pci/pcie_xilinx.c
@@ -10,6 +10,7 @@
#include <pci.h>
#include <asm/global_data.h>
#include <linux/bitops.h>
+#include <linux/printk.h>
#include <asm/io.h>
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 7a2d54f..60138be 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -70,6 +70,16 @@
help
Support for the USB OTG PHY in ST-Ericsson AB8500.
+config APPLE_ATCPHY
+ bool "Apple Type-C PHY Driver"
+ depends on PHY && ARCH_APPLE
+ default y
+ help
+ Support for the Apple Type-C PHY.
+
+ This is a dummy driver since the PHY is initialized
+ sufficiently by previous stage firmware.
+
config BCM6318_USBH_PHY
bool "BCM6318 USBH PHY support"
depends on PHY && ARCH_BMIPS
@@ -190,7 +200,7 @@
config MESON_G12A_USB_PHY
bool "Amlogic Meson G12A USB PHYs"
- depends on PHY && ARCH_MESON && MESON_G12A
+ depends on PHY && ARCH_MESON && (MESON_G12A || MESON_A1)
imply REGMAP
help
This is the generic phy driver for the Amlogic Meson G12A
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index aca365d..2e87231 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
# Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
obj-y += allwinner/
@@ -12,6 +12,7 @@
obj-$(CONFIG_$(SPL_)NOP_PHY) += nop-phy.o
obj-$(CONFIG_MIPI_DPHY_HELPERS) += phy-core-mipi-dphy.o
obj-$(CONFIG_AB8500_USB_PHY) += phy-ab8500-usb.o
+obj-$(CONFIG_APPLE_ATCPHY) += phy-apple-atc.o
obj-$(CONFIG_BCM6318_USBH_PHY) += bcm6318-usbh-phy.o
obj-$(CONFIG_BCM6348_USBH_PHY) += bcm6348-usbh-phy.o
obj-$(CONFIG_BCM6358_USBH_PHY) += bcm6358-usbh-phy.o
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index 77dffca..6624e91 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -472,9 +472,9 @@
if (!data->cfg)
return -EINVAL;
- data->base = (void __iomem *)devfdt_get_addr_name(dev, "phy_ctrl");
- if (IS_ERR(data->base))
- return PTR_ERR(data->base);
+ data->base = (void __iomem *)dev_read_addr_name_ptr(dev, "phy_ctrl");
+ if (!data->base)
+ return -EINVAL;
device_get_supply_regulator(dev, "usb0_vbus_power-supply",
&data->vbus_power_supply);
@@ -555,9 +555,9 @@
if (i || data->cfg->phy0_dual_route) {
snprintf(name, sizeof(name), "pmu%d", i);
- phy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name);
- if (IS_ERR(phy->pmu))
- return PTR_ERR(phy->pmu);
+ phy->pmu = (void __iomem *)dev_read_addr_name_ptr(dev, name);
+ if (!phy->pmu)
+ return -EINVAL;
}
phy->id = i;
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index fc5044f..4bb8a0c 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -7,7 +7,7 @@
* Copyright (c) 2018 Cadence Design Systems
* Author: Alan Douglas <adouglas@cadence.com>
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* Jean-Jacques Hiblot <jjhiblot@ti.com>
*
*/
diff --git a/drivers/phy/keystone-usb-phy.c b/drivers/phy/keystone-usb-phy.c
index 12f8a26..3bb9c08 100644
--- a/drivers/phy/keystone-usb-phy.c
+++ b/drivers/phy/keystone-usb-phy.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
* Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
@@ -13,6 +13,7 @@
#include <asm/arch/psc_defs.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <linux/printk.h>
/* USB PHY control register offsets */
#define USB_PHY_CTL_UTMI 0x0000
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index a7e0099..bb15fba 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -12,6 +12,7 @@
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include "comphy_core.h"
#include "sata.h"
diff --git a/drivers/phy/meson-g12a-usb2.c b/drivers/phy/meson-g12a-usb2.c
index 650b88b..3958d24 100644
--- a/drivers/phy/meson-g12a-usb2.c
+++ b/drivers/phy/meson-g12a-usb2.c
@@ -17,18 +17,36 @@
#include <generic-phy.h>
#include <regmap.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <power/regulator.h>
+#include <power-domain.h>
#include <reset.h>
#include <clk.h>
#include <linux/bitops.h>
#include <linux/compat.h>
+#include <linux/bitfield.h>
#define PHY_CTRL_R0 0x0
#define PHY_CTRL_R1 0x4
#define PHY_CTRL_R2 0x8
+
#define PHY_CTRL_R3 0xc
+ #define PHY_CTRL_R3_SQUELCH_REF GENMASK(1, 0)
+ #define PHY_CTRL_R3_HSDIC_REF GENMASK(3, 2)
+ #define PHY_CTRL_R3_DISC_THRESH GENMASK(7, 4)
+
#define PHY_CTRL_R4 0x10
+ #define PHY_CTRL_R4_CALIB_CODE_7_0 GENMASK(7, 0)
+ #define PHY_CTRL_R4_CALIB_CODE_15_8 GENMASK(15, 8)
+ #define PHY_CTRL_R4_CALIB_CODE_23_16 GENMASK(23, 16)
+ #define PHY_CTRL_R4_I_C2L_CAL_EN BIT(24)
+ #define PHY_CTRL_R4_I_C2L_CAL_RESET_N BIT(25)
+ #define PHY_CTRL_R4_I_C2L_CAL_DONE BIT(26)
+ #define PHY_CTRL_R4_TEST_BYPASS_MODE_EN BIT(27)
+ #define PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0 GENMASK(29, 28)
+ #define PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2 GENMASK(31, 30)
+
#define PHY_CTRL_R5 0x14
#define PHY_CTRL_R6 0x18
#define PHY_CTRL_R7 0x1c
@@ -37,35 +55,131 @@
#define PHY_CTRL_R10 0x28
#define PHY_CTRL_R11 0x2c
#define PHY_CTRL_R12 0x30
+
#define PHY_CTRL_R13 0x34
+ #define PHY_CTRL_R13_CUSTOM_PATTERN_19 GENMASK(7, 0)
+ #define PHY_CTRL_R13_LOAD_STAT BIT(14)
+ #define PHY_CTRL_R13_UPDATE_PMA_SIGNALS BIT(15)
+ #define PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET GENMASK(20, 16)
+ #define PHY_CTRL_R13_CLEAR_HOLD_HS_DISCONNECT BIT(21)
+ #define PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_VAL BIT(22)
+ #define PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_EN BIT(23)
+ #define PHY_CTRL_R13_I_C2L_HS_EN BIT(24)
+ #define PHY_CTRL_R13_I_C2L_FS_EN BIT(25)
+ #define PHY_CTRL_R13_I_C2L_LS_EN BIT(26)
+ #define PHY_CTRL_R13_I_C2L_HS_OE BIT(27)
+ #define PHY_CTRL_R13_I_C2L_FS_OE BIT(28)
+ #define PHY_CTRL_R13_I_C2L_HS_RX_EN BIT(29)
+ #define PHY_CTRL_R13_I_C2L_FSLS_RX_EN BIT(30)
+
#define PHY_CTRL_R14 0x38
#define PHY_CTRL_R15 0x3c
+
#define PHY_CTRL_R16 0x40
+ #define PHY_CTRL_R16_MPLL_M GENMASK(8, 0)
+ #define PHY_CTRL_R16_MPLL_N GENMASK(14, 10)
+ #define PHY_CTRL_R16_MPLL_TDC_MODE BIT(20)
+ #define PHY_CTRL_R16_MPLL_SDM_EN BIT(21)
+ #define PHY_CTRL_R16_MPLL_LOAD BIT(22)
+ #define PHY_CTRL_R16_MPLL_DCO_SDM_EN BIT(23)
+ #define PHY_CTRL_R16_MPLL_LOCK_LONG GENMASK(25, 24)
+ #define PHY_CTRL_R16_MPLL_LOCK_F BIT(26)
+ #define PHY_CTRL_R16_MPLL_FAST_LOCK BIT(27)
+ #define PHY_CTRL_R16_MPLL_EN BIT(28)
+ #define PHY_CTRL_R16_MPLL_RESET BIT(29)
+ #define PHY_CTRL_R16_MPLL_LOCK BIT(30)
+ #define PHY_CTRL_R16_MPLL_LOCK_DIG BIT(31)
+
#define PHY_CTRL_R17 0x44
+ #define PHY_CTRL_R17_MPLL_FRAC_IN GENMASK(13, 0)
+ #define PHY_CTRL_R17_MPLL_FIX_EN BIT(16)
+ #define PHY_CTRL_R17_MPLL_LAMBDA1 GENMASK(19, 17)
+ #define PHY_CTRL_R17_MPLL_LAMBDA0 GENMASK(22, 20)
+ #define PHY_CTRL_R17_MPLL_FILTER_MODE BIT(23)
+ #define PHY_CTRL_R17_MPLL_FILTER_PVT2 GENMASK(27, 24)
+ #define PHY_CTRL_R17_MPLL_FILTER_PVT1 GENMASK(31, 28)
+
#define PHY_CTRL_R18 0x48
+ #define PHY_CTRL_R18_MPLL_LKW_SEL GENMASK(1, 0)
+ #define PHY_CTRL_R18_MPLL_LK_W GENMASK(5, 2)
+ #define PHY_CTRL_R18_MPLL_LK_S GENMASK(11, 6)
+ #define PHY_CTRL_R18_MPLL_DCO_M_EN BIT(12)
+ #define PHY_CTRL_R18_MPLL_DCO_CLK_SEL BIT(13)
+ #define PHY_CTRL_R18_MPLL_PFD_GAIN GENMASK(15, 14)
+ #define PHY_CTRL_R18_MPLL_ROU GENMASK(18, 16)
+ #define PHY_CTRL_R18_MPLL_DATA_SEL GENMASK(21, 19)
+ #define PHY_CTRL_R18_MPLL_BIAS_ADJ GENMASK(23, 22)
+ #define PHY_CTRL_R18_MPLL_BB_MODE GENMASK(25, 24)
+ #define PHY_CTRL_R18_MPLL_ALPHA GENMASK(28, 26)
+ #define PHY_CTRL_R18_MPLL_ADJ_LDO GENMASK(30, 29)
+ #define PHY_CTRL_R18_MPLL_ACG_RANGE BIT(31)
+
#define PHY_CTRL_R19 0x4c
+
#define PHY_CTRL_R20 0x50
+ #define PHY_CTRL_R20_USB2_IDDET_EN BIT(0)
+ #define PHY_CTRL_R20_USB2_OTG_VBUS_TRIM_2_0 GENMASK(3, 1)
+ #define PHY_CTRL_R20_USB2_OTG_VBUSDET_EN BIT(4)
+ #define PHY_CTRL_R20_USB2_AMON_EN BIT(5)
+ #define PHY_CTRL_R20_USB2_CAL_CODE_R5 BIT(6)
+ #define PHY_CTRL_R20_BYPASS_OTG_DET BIT(7)
+ #define PHY_CTRL_R20_USB2_DMON_EN BIT(8)
+ #define PHY_CTRL_R20_USB2_DMON_SEL_3_0 GENMASK(12, 9)
+ #define PHY_CTRL_R20_USB2_EDGE_DRV_EN BIT(13)
+ #define PHY_CTRL_R20_USB2_EDGE_DRV_TRIM_1_0 GENMASK(15, 14)
+ #define PHY_CTRL_R20_USB2_BGR_ADJ_4_0 GENMASK(20, 16)
+ #define PHY_CTRL_R20_USB2_BGR_START BIT(21)
+ #define PHY_CTRL_R20_USB2_BGR_VREF_4_0 GENMASK(28, 24)
+ #define PHY_CTRL_R20_USB2_BGR_DBG_1_0 GENMASK(30, 29)
+ #define PHY_CTRL_R20_BYPASS_CAL_DONE_R5 BIT(31)
+
#define PHY_CTRL_R21 0x54
+ #define PHY_CTRL_R21_USB2_BGR_FORCE BIT(0)
+ #define PHY_CTRL_R21_USB2_CAL_ACK_EN BIT(1)
+ #define PHY_CTRL_R21_USB2_OTG_ACA_EN BIT(2)
+ #define PHY_CTRL_R21_USB2_TX_STRG_PD BIT(3)
+ #define PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0 GENMASK(5, 4)
+ #define PHY_CTRL_R21_BYPASS_UTMI_CNTR GENMASK(15, 6)
+ #define PHY_CTRL_R21_BYPASS_UTMI_REG GENMASK(25, 20)
+
#define PHY_CTRL_R22 0x58
#define PHY_CTRL_R23 0x5c
#define RESET_COMPLETE_TIME 1000
#define PLL_RESET_COMPLETE_TIME 100
+enum meson_soc_id {
+ MESON_SOC_A1,
+ MESON_SOC_G12A,
+};
+
struct phy_meson_g12a_usb2_priv {
struct regmap *regmap;
#if CONFIG_IS_ENABLED(CLK)
struct clk clk;
#endif
struct reset_ctl reset;
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+ struct power_domain pwrdm;
+#endif
+ int soc_id;
};
static int phy_meson_g12a_usb2_init(struct phy *phy)
{
struct udevice *dev = phy->dev;
struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
+ u32 value;
int ret;
+#if CONFIG_IS_ENABLED(CLK)
+ ret = clk_enable(&priv->clk);
+ if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
+ pr_err("failed to enable PHY clock\n");
+ return ret;
+ }
+#endif
+
ret = reset_assert(&priv->reset);
udelay(1);
ret |= reset_deassert(&priv->reset);
@@ -78,25 +192,91 @@
regmap_update_bits(priv->regmap, PHY_CTRL_R21, BIT(2), 0);
/* PLL Setup : 24MHz * 20 / 1 = 480MHz */
- regmap_write(priv->regmap, PHY_CTRL_R16, 0x39400414);
- regmap_write(priv->regmap, PHY_CTRL_R17, 0x927e0000);
- regmap_write(priv->regmap, PHY_CTRL_R18, 0xac5f49e5);
+ regmap_write(priv->regmap, PHY_CTRL_R16,
+ FIELD_PREP(PHY_CTRL_R16_MPLL_M, 20) |
+ FIELD_PREP(PHY_CTRL_R16_MPLL_N, 1) |
+ PHY_CTRL_R16_MPLL_LOAD |
+ FIELD_PREP(PHY_CTRL_R16_MPLL_LOCK_LONG, 1) |
+ PHY_CTRL_R16_MPLL_FAST_LOCK |
+ PHY_CTRL_R16_MPLL_EN |
+ PHY_CTRL_R16_MPLL_RESET);
+
+ regmap_write(priv->regmap, PHY_CTRL_R17,
+ FIELD_PREP(PHY_CTRL_R17_MPLL_FRAC_IN, 0) |
+ FIELD_PREP(PHY_CTRL_R17_MPLL_LAMBDA1, 7) |
+ FIELD_PREP(PHY_CTRL_R17_MPLL_LAMBDA0, 7) |
+ FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT2, 2) |
+ FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT1, 9));
+
+ value = FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_DATA_SEL, 3) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_BIAS_ADJ, 1) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) |
+ PHY_CTRL_R18_MPLL_ACG_RANGE;
+
+ if (priv->soc_id == MESON_SOC_A1)
+ value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL;
+
+ regmap_write(priv->regmap, PHY_CTRL_R18, value);
udelay(PLL_RESET_COMPLETE_TIME);
/* UnReset PLL */
- regmap_write(priv->regmap, PHY_CTRL_R16, 0x19400414);
+ regmap_write(priv->regmap, PHY_CTRL_R16,
+ FIELD_PREP(PHY_CTRL_R16_MPLL_M, 20) |
+ FIELD_PREP(PHY_CTRL_R16_MPLL_N, 1) |
+ PHY_CTRL_R16_MPLL_LOAD |
+ FIELD_PREP(PHY_CTRL_R16_MPLL_LOCK_LONG, 1) |
+ PHY_CTRL_R16_MPLL_FAST_LOCK |
+ PHY_CTRL_R16_MPLL_EN);
/* PHY Tuning */
- regmap_write(priv->regmap, PHY_CTRL_R20, 0xfe18);
- regmap_write(priv->regmap, PHY_CTRL_R4, 0x8000fff);
+ regmap_write(priv->regmap, PHY_CTRL_R20,
+ FIELD_PREP(PHY_CTRL_R20_USB2_OTG_VBUS_TRIM_2_0, 4) |
+ PHY_CTRL_R20_USB2_OTG_VBUSDET_EN |
+ FIELD_PREP(PHY_CTRL_R20_USB2_DMON_SEL_3_0, 15) |
+ PHY_CTRL_R20_USB2_EDGE_DRV_EN |
+ FIELD_PREP(PHY_CTRL_R20_USB2_EDGE_DRV_TRIM_1_0, 3) |
+ FIELD_PREP(PHY_CTRL_R20_USB2_BGR_ADJ_4_0, 0) |
+ FIELD_PREP(PHY_CTRL_R20_USB2_BGR_VREF_4_0, 0) |
+ FIELD_PREP(PHY_CTRL_R20_USB2_BGR_DBG_1_0, 0));
+
+ if (priv->soc_id == MESON_SOC_G12A)
+ regmap_write(priv->regmap, PHY_CTRL_R4,
+ FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) |
+ FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) |
+ FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) |
+ PHY_CTRL_R4_TEST_BYPASS_MODE_EN |
+ FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) |
+ FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0));
+ else if (priv->soc_id == MESON_SOC_A1)
+ regmap_write(priv->regmap, PHY_CTRL_R21,
+ PHY_CTRL_R21_USB2_CAL_ACK_EN |
+ PHY_CTRL_R21_USB2_TX_STRG_PD |
+ FIELD_PREP(PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0, 2));
/* Tuning Disconnect Threshold */
- regmap_write(priv->regmap, PHY_CTRL_R3, 0x34);
+ regmap_write(priv->regmap, PHY_CTRL_R3,
+ FIELD_PREP(PHY_CTRL_R3_SQUELCH_REF, 0) |
+ FIELD_PREP(PHY_CTRL_R3_HSDIC_REF, 1) |
+ FIELD_PREP(PHY_CTRL_R3_DISC_THRESH, 3));
/* Analog Settings */
- regmap_write(priv->regmap, PHY_CTRL_R14, 0);
- regmap_write(priv->regmap, PHY_CTRL_R13, 0x78000);
+ if (priv->soc_id == MESON_SOC_G12A) {
+ regmap_write(priv->regmap, PHY_CTRL_R14, 0);
+ regmap_write(priv->regmap, PHY_CTRL_R13,
+ PHY_CTRL_R13_UPDATE_PMA_SIGNALS |
+ FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
+ } else if (priv->soc_id == MESON_SOC_A1) {
+ regmap_write(priv->regmap, PHY_CTRL_R13,
+ FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
+ }
return 0;
}
@@ -107,6 +287,10 @@
struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
int ret;
+#if CONFIG_IS_ENABLED(CLK)
+ clk_disable(&priv->clk);
+#endif
+
ret = reset_assert(&priv->reset);
if (ret)
return ret;
@@ -124,6 +308,8 @@
struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
int ret;
+ priv->soc_id = (enum meson_soc_id)dev_get_driver_data(dev);
+
ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
if (ret)
return ret;
@@ -140,24 +326,40 @@
return ret;
}
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+ ret = power_domain_get(dev, &priv->pwrdm);
+ if (ret < 0 && ret != -ENODEV && ret != -ENOENT) {
+ pr_err("failed to get power domain : %d\n", ret);
+ return ret;
+ }
+
+ if (ret != -ENODEV && ret != -ENOENT) {
+ ret = power_domain_on(&priv->pwrdm);
+ if (ret < 0) {
+ pr_err("failed to enable power domain\n");
+ return ret;
+ }
+ }
+#endif
+
#if CONFIG_IS_ENABLED(CLK)
ret = clk_get_by_index(dev, 0, &priv->clk);
if (ret < 0)
return ret;
-
- ret = clk_enable(&priv->clk);
- if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
- pr_err("failed to enable PHY clock\n");
- clk_free(&priv->clk);
- return ret;
- }
#endif
return 0;
}
static const struct udevice_id meson_g12a_usb2_phy_ids[] = {
- { .compatible = "amlogic,g12a-usb2-phy" },
+ {
+ .compatible = "amlogic,g12a-usb2-phy",
+ .data = (ulong)MESON_SOC_G12A,
+ },
+ {
+ .compatible = "amlogic,a1-usb2-phy",
+ .data = (ulong)MESON_SOC_A1,
+ },
{ }
};
diff --git a/drivers/phy/meson-g12a-usb3-pcie.c b/drivers/phy/meson-g12a-usb3-pcie.c
index 8f72b5a..40a5da9 100644
--- a/drivers/phy/meson-g12a-usb3-pcie.c
+++ b/drivers/phy/meson-g12a-usb3-pcie.c
@@ -18,6 +18,7 @@
#include <bitfield.h>
#include <generic-phy.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <linux/bitops.h>
#include <linux/compat.h>
diff --git a/drivers/phy/meson-gxbb-usb2.c b/drivers/phy/meson-gxbb-usb2.c
index 70a80b8..725b056 100644
--- a/drivers/phy/meson-gxbb-usb2.c
+++ b/drivers/phy/meson-gxbb-usb2.c
@@ -15,6 +15,7 @@
#include <regmap.h>
#include <reset.h>
#include <linux/bitops.h>
+#include <linux/printk.h>
#define REG_CONFIG 0x00
#define REG_CONFIG_CLK_EN BIT(0)
diff --git a/drivers/phy/meson-gxl-usb2.c b/drivers/phy/meson-gxl-usb2.c
index 4c63131..8f5e4a4 100644
--- a/drivers/phy/meson-gxl-usb2.c
+++ b/drivers/phy/meson-gxl-usb2.c
@@ -11,12 +11,13 @@
#include <malloc.h>
#include <asm/io.h>
#include <bitfield.h>
+#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <generic-phy.h>
#include <regmap.h>
#include <linux/delay.h>
-#include <clk.h>
+#include <linux/printk.h>
#include <linux/usb/otg.h>
#include <asm/arch/usb-gx.h>
diff --git a/drivers/phy/nop-phy.c b/drivers/phy/nop-phy.c
index d0904f4..c53e321 100644
--- a/drivers/phy/nop-phy.c
+++ b/drivers/phy/nop-phy.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
* Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/drivers/phy/omap-usb2-phy.c b/drivers/phy/omap-usb2-phy.c
index 2a9604c..d3d3806 100644
--- a/drivers/phy/omap-usb2-phy.c
+++ b/drivers/phy/omap-usb2-phy.c
@@ -2,7 +2,7 @@
/*
* OMAP USB2 PHY LAYER
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
* Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/drivers/phy/phy-apple-atc.c b/drivers/phy/phy-apple-atc.c
new file mode 100644
index 0000000..15c5b8a
--- /dev/null
+++ b/drivers/phy/phy-apple-atc.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Mark Kettenis <kettenis@openbsd.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <generic-phy.h>
+#include <reset-uclass.h>
+
+static const struct phy_ops apple_atcphy_ops = {
+};
+
+static struct driver apple_atcphy_driver = {
+ .name = "apple-atcphy",
+ .id = UCLASS_PHY,
+ .ops = &apple_atcphy_ops,
+};
+
+static int apple_atcphy_reset_of_xlate(struct reset_ctl *reset_ctl,
+ struct ofnode_phandle_args *args)
+{
+ if (args->args_count != 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct reset_ops apple_atcphy_reset_ops = {
+ .of_xlate = apple_atcphy_reset_of_xlate,
+};
+
+static int apple_atcphy_reset_probe(struct udevice *dev)
+{
+ struct udevice *child;
+
+ device_bind(dev, &apple_atcphy_driver, "apple-atcphy", NULL,
+ dev_ofnode(dev), &child);
+
+ return 0;
+}
+
+static const struct udevice_id apple_atcphy_ids[] = {
+ { .compatible = "apple,t6000-atcphy" },
+ { .compatible = "apple,t8103-atcphy" },
+ { }
+};
+
+U_BOOT_DRIVER(apple_atcphy_reset) = {
+ .name = "apple-atcphy-reset",
+ .id = UCLASS_RESET,
+ .of_match = apple_atcphy_ids,
+ .ops = &apple_atcphy_reset_ops,
+ .probe = apple_atcphy_reset_probe,
+};
diff --git a/drivers/phy/phy-bcm-sr-pcie.c b/drivers/phy/phy-bcm-sr-pcie.c
index f0e7953..cf33bab 100644
--- a/drivers/phy/phy-bcm-sr-pcie.c
+++ b/drivers/phy/phy-bcm-sr-pcie.c
@@ -143,8 +143,8 @@
core->dev = dev;
- core->base = (void __iomem *)devfdt_get_addr_name(dev, "reg_base");
- core->cdru = (void __iomem *)devfdt_get_addr_name(dev, "cdru_base");
+ core->base = (void __iomem *)dev_read_addr_name_ptr(dev, "reg_base");
+ core->cdru = (void __iomem *)dev_read_addr_name_ptr(dev, "cdru_base");
debug("ip base %p\n", core->base);
debug("cdru base %p\n", core->cdru);
diff --git a/drivers/phy/phy-rcar-gen3.c b/drivers/phy/phy-rcar-gen3.c
index 8c59631..7159e7e 100644
--- a/drivers/phy/phy-rcar-gen3.c
+++ b/drivers/phy/phy-rcar-gen3.c
@@ -17,6 +17,7 @@
#include <usb.h>
#include <asm/io.h>
#include <linux/bitops.h>
+#include <linux/printk.h>
#include <power/regulator.h>
/* USB2.0 Host registers (original offset is +0x200) */
diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c
index 15bd60c..000e495 100644
--- a/drivers/phy/phy-stm32-usbphyc.c
+++ b/drivers/phy/phy-stm32-usbphyc.c
@@ -23,6 +23,7 @@
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <power/regulator.h>
/* USBPHYC registers */
diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c
index 629ef3a..0dcfe25 100644
--- a/drivers/phy/phy-uclass.c
+++ b/drivers/phy/phy-uclass.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
* Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
@@ -12,6 +12,7 @@
#include <dm/devres.h>
#include <generic-phy.h>
#include <linux/list.h>
+#include <linux/printk.h>
#include <power/regulator.h>
/**
@@ -195,6 +196,7 @@
return 0;
err:
+ phy->dev = NULL;
return ret;
}
@@ -211,6 +213,9 @@
debug("%s(dev=%p, name=%s, phy=%p)\n", __func__, dev, phy_name, phy);
+ assert(phy);
+ phy->dev = NULL;
+
index = dev_read_stringlist_search(dev, "phy-names", phy_name);
if (index < 0) {
debug("dev_read_stringlist_search() failed: %d\n", index);
@@ -506,44 +511,35 @@
int generic_setup_phy(struct udevice *dev, struct phy *phy, int index)
{
- int ret = 0;
-
- if (!phy)
- return 0;
+ int ret;
ret = generic_phy_get_by_index(dev, index, phy);
- if (ret) {
- if (ret != -ENOENT)
- return ret;
- } else {
- ret = generic_phy_init(phy);
- if (ret)
- return ret;
+ if (ret)
+ return ret == -ENOENT ? 0 : ret;
- ret = generic_phy_power_on(phy);
- if (ret)
- ret = generic_phy_exit(phy);
- }
+ ret = generic_phy_init(phy);
+ if (ret)
+ return ret;
+
+ ret = generic_phy_power_on(phy);
+ if (ret)
+ generic_phy_exit(phy);
return ret;
}
int generic_shutdown_phy(struct phy *phy)
{
- int ret = 0;
+ int ret;
- if (!phy)
+ if (!generic_phy_valid(phy))
return 0;
- if (generic_phy_valid(phy)) {
- ret = generic_phy_power_off(phy);
- if (ret)
- return ret;
+ ret = generic_phy_power_off(phy);
+ if (ret)
+ return ret;
- ret = generic_phy_exit(phy);
- }
-
- return ret;
+ return generic_phy_exit(phy);
}
UCLASS_DRIVER(phy) = {
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index d5408cc..9ca66bf 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -61,6 +61,8 @@
struct combphy_reg pipe_con1_for_sata;
struct combphy_reg pipe_sgmii_mac_sel;
struct combphy_reg pipe_xpcs_phy_ready;
+ struct combphy_reg pipe_pcie1l0_sel;
+ struct combphy_reg pipe_pcie1l1_sel;
struct combphy_reg u3otg0_port_en;
struct combphy_reg u3otg1_port_en;
};
@@ -435,6 +437,8 @@
param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
+ param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true);
+ param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true);
break;
case PHY_TYPE_USB3:
param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
@@ -507,6 +511,8 @@
/* pipe-grf */
.pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 },
.pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 },
+ .pipe_pcie1l0_sel = { 0x0100, 0, 0, 0x01, 0x0 },
+ .pipe_pcie1l1_sel = { 0x0100, 1, 1, 0x01, 0x0 },
};
static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
index 66c75f9..a4392da 100644
--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
@@ -16,9 +16,27 @@
#include <dm/device_compat.h>
#include <dm/lists.h>
-#define GRF_PCIE30PHY_CON1 0x4
-#define GRF_PCIE30PHY_CON6 0x18
-#define GRF_PCIE30PHY_CON9 0x24
+/* Register for RK3568 */
+#define GRF_PCIE30PHY_CON1 0x4
+#define GRF_PCIE30PHY_CON6 0x18
+#define GRF_PCIE30PHY_CON9 0x24
+#define GRF_PCIE30PHY_DA_OCM (BIT(15) | BIT(31))
+#define GRF_PCIE30PHY_STATUS0 0x80
+#define GRF_PCIE30PHY_WR_EN (0xf << 16)
+#define SRAM_INIT_DONE(reg) (reg & BIT(14))
+
+#define RK3568_BIFURCATION_LANE_0_1 BIT(0)
+
+/* Register for RK3588 */
+#define PHP_GRF_PCIESEL_CON 0x100
+#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
+#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
+#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
+#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0))
+
+#define RK3588_BIFURCATION_LANE_0_1 BIT(0)
+#define RK3588_BIFURCATION_LANE_2_3 BIT(1)
+#define RK3588_LANE_AGGREGATION BIT(2)
/**
* struct rockchip_p3phy_priv - RK DW PCIe PHY state
@@ -26,51 +44,144 @@
* @mmio: The base address of PHY internal registers
* @phy_grf: The regmap for controlling pipe signal
* @p30phy: The reset signal for PHY
- * @ref_clk_m: The reference clock of M for PHY
- * @ref_clk_n: The reference clock of N for PHY
- * @pclk: The clock for accessing PHY blocks
+ * @clks: The clocks for PHY
+ * @num_lanes: The number of lane to controller mappings
+ * @lanes: The lane to controller mapping
*/
struct rockchip_p3phy_priv {
void __iomem *mmio;
struct regmap *phy_grf;
+ struct regmap *pipe_grf;
struct reset_ctl p30phy;
- struct clk ref_clk_m;
- struct clk ref_clk_n;
- struct clk pclk;
+ struct clk_bulk clks;
+ int num_lanes;
+ u32 lanes[4];
};
-static int rochchip_p3phy_init(struct phy *phy)
+struct rockchip_p3phy_ops {
+ int (*phy_init)(struct phy *phy);
+};
+
+static int rockchip_p3phy_rk3568_init(struct phy *phy)
{
struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
+ bool bifurcation = false;
int ret;
-
- ret = clk_enable(&priv->ref_clk_m);
- if (ret < 0 && ret != -ENOSYS)
- return ret;
-
- ret = clk_enable(&priv->ref_clk_n);
- if (ret < 0 && ret != -ENOSYS)
- goto err_ref;
-
- ret = clk_enable(&priv->pclk);
- if (ret < 0 && ret != -ENOSYS)
- goto err_pclk;
-
- reset_assert(&priv->p30phy);
- udelay(1);
+ u32 reg;
/* Deassert PCIe PMA output clamp mode */
- regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
- (0x1 << 15) | (0x1 << 31));
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM);
+
+ for (int i = 0; i < priv->num_lanes; i++) {
+ if (priv->lanes[i] > 1)
+ bifurcation = true;
+ }
+
+ /* Set bifurcation if needed, and it doesn't care RC/EP */
+ if (bifurcation) {
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
+ GRF_PCIE30PHY_WR_EN | RK3568_BIFURCATION_LANE_0_1);
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1,
+ GRF_PCIE30PHY_DA_OCM);
+ } else {
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
+ GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1);
+ }
reset_deassert(&priv->p30phy);
udelay(1);
- return 0;
-err_pclk:
- clk_disable(&priv->ref_clk_n);
-err_ref:
- clk_disable(&priv->ref_clk_m);
+ ret = regmap_read_poll_timeout(priv->phy_grf,
+ GRF_PCIE30PHY_STATUS0,
+ reg, SRAM_INIT_DONE(reg),
+ 0, 500);
+ if (ret)
+ dev_err(phy->dev, "lock failed 0x%x\n", reg);
+
+ return ret;
+}
+
+static const struct rockchip_p3phy_ops rk3568_ops = {
+ .phy_init = rockchip_p3phy_rk3568_init,
+};
+
+static int rockchip_p3phy_rk3588_init(struct phy *phy)
+{
+ struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
+ u32 reg = 0;
+ u8 mode = 0;
+ int ret;
+
+ /* Deassert PCIe PMA output clamp mode */
+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
+ BIT(8) | BIT(24));
+
+ /* Set bifurcation if needed */
+ for (int i = 0; i < priv->num_lanes; i++) {
+ if (!priv->lanes[i])
+ mode |= (BIT(i) << 3);
+
+ if (priv->lanes[i] > 1)
+ mode |= (BIT(i) >> 1);
+ }
+
+ if (!mode) {
+ reg = RK3588_LANE_AGGREGATION;
+ } else {
+ if (mode & (BIT(0) | BIT(1)))
+ reg |= RK3588_BIFURCATION_LANE_0_1;
+
+ if (mode & (BIT(2) | BIT(3)))
+ reg |= RK3588_BIFURCATION_LANE_2_3;
+ }
+
+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
+ (0x7 << 16) | reg);
+
+ /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
+ reg = (mode & (BIT(6) | BIT(7))) >> 6;
+ if (reg)
+ regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
+ (reg << 16) | reg);
+
+ reset_deassert(&priv->p30phy);
+ udelay(1);
+
+ ret = regmap_read_poll_timeout(priv->phy_grf,
+ RK3588_PCIE3PHY_GRF_PHY0_STATUS1,
+ reg, RK3588_SRAM_INIT_DONE(reg),
+ 0, 500);
+ ret |= regmap_read_poll_timeout(priv->phy_grf,
+ RK3588_PCIE3PHY_GRF_PHY1_STATUS1,
+ reg, RK3588_SRAM_INIT_DONE(reg),
+ 0, 500);
+ if (ret)
+ dev_err(phy->dev, "lock failed 0x%x\n", reg);
+
+ return ret;
+}
+
+static const struct rockchip_p3phy_ops rk3588_ops = {
+ .phy_init = rockchip_p3phy_rk3588_init,
+};
+
+static int rochchip_p3phy_init(struct phy *phy)
+{
+ struct rockchip_p3phy_ops *ops =
+ (struct rockchip_p3phy_ops *)dev_get_driver_data(phy->dev);
+ struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
+ int ret;
+
+ ret = clk_enable_bulk(&priv->clks);
+ if (ret)
+ return ret;
+
+ reset_assert(&priv->p30phy);
+ udelay(1);
+
+ ret = ops->phy_init(phy);
+ if (ret)
+ clk_disable_bulk(&priv->clks);
return ret;
}
@@ -79,9 +190,7 @@
{
struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
- clk_disable(&priv->ref_clk_m);
- clk_disable(&priv->ref_clk_n);
- clk_disable(&priv->pclk);
+ clk_disable_bulk(&priv->clks);
reset_assert(&priv->p30phy);
return 0;
@@ -90,48 +199,54 @@
static int rockchip_p3phy_probe(struct udevice *dev)
{
struct rockchip_p3phy_priv *priv = dev_get_priv(dev);
- struct udevice *syscon;
int ret;
priv->mmio = dev_read_addr_ptr(dev);
if (!priv->mmio)
return -EINVAL;
- ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
- "rockchip,phy-grf", &syscon);
- if (ret) {
- pr_err("unable to find syscon device for rockchip,phy-grf\n");
- return ret;
- }
-
- priv->phy_grf = syscon_get_regmap(syscon);
+ priv->phy_grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,phy-grf");
if (IS_ERR(priv->phy_grf)) {
dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
return PTR_ERR(priv->phy_grf);
}
+ if (device_is_compatible(dev, "rockchip,rk3588-pcie3-phy")) {
+ priv->pipe_grf =
+ syscon_regmap_lookup_by_phandle(dev, "rockchip,pipe-grf");
+ if (IS_ERR(priv->pipe_grf)) {
+ dev_err(dev, "failed to find rockchip,pipe_grf regmap\n");
+ return PTR_ERR(priv->pipe_grf);
+ }
+ }
+
+ ret = dev_read_size(dev, "data-lanes");
+ if (ret > 0) {
+ priv->num_lanes = ret / sizeof(u32);
+ if (priv->num_lanes < 2 ||
+ priv->num_lanes > ARRAY_SIZE(priv->lanes)) {
+ dev_err(dev, "unsupported data-lanes property size\n");
+ return -EINVAL;
+ }
+
+ ret = dev_read_u32_array(dev, "data-lanes", priv->lanes,
+ priv->num_lanes);
+ if (ret) {
+ dev_err(dev, "failed to read data-lanes property\n");
+ return ret;
+ }
+ }
+
ret = reset_get_by_name(dev, "phy", &priv->p30phy);
if (ret) {
dev_err(dev, "no phy reset control specified\n");
return ret;
}
- ret = clk_get_by_name(dev, "refclk_m", &priv->ref_clk_m);
+ ret = clk_get_bulk(dev, &priv->clks);
if (ret) {
- dev_err(dev, "failed to find ref clock M\n");
- return PTR_ERR(&priv->ref_clk_m);
- }
-
- ret = clk_get_by_name(dev, "refclk_n", &priv->ref_clk_n);
- if (ret) {
- dev_err(dev, "failed to find ref clock N\n");
- return PTR_ERR(&priv->ref_clk_n);
- }
-
- ret = clk_get_by_name(dev, "pclk", &priv->pclk);
- if (ret) {
- dev_err(dev, "failed to find pclk\n");
- return PTR_ERR(&priv->pclk);
+ dev_err(dev, "failed to get clocks\n");
+ return ret;
}
return 0;
@@ -143,7 +258,14 @@
};
static const struct udevice_id rockchip_p3phy_of_match[] = {
- { .compatible = "rockchip,rk3568-pcie3-phy" },
+ {
+ .compatible = "rockchip,rk3568-pcie3-phy",
+ .data = (ulong)&rk3568_ops,
+ },
+ {
+ .compatible = "rockchip,rk3588-pcie3-phy",
+ .data = (ulong)&rk3588_ops,
+ },
{ },
};
diff --git a/drivers/phy/sandbox-phy.c b/drivers/phy/sandbox-phy.c
index 7b3d988..7e123da 100644
--- a/drivers/phy/sandbox-phy.c
+++ b/drivers/phy/sandbox-phy.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
* Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/drivers/phy/sti_usb_phy.c b/drivers/phy/sti_usb_phy.c
index ce4caaf..9e5ac9b 100644
--- a/drivers/phy/sti_usb_phy.c
+++ b/drivers/phy/sti_usb_phy.c
@@ -18,6 +18,7 @@
#include <reset-uclass.h>
#include <syscon.h>
#include <wait_bit.h>
+#include <linux/printk.h>
#include <linux/bitops.h>
#include <linux/compat.h>
diff --git a/drivers/phy/ti-pipe3-phy.c b/drivers/phy/ti-pipe3-phy.c
index b5b3c3f..29a35ae 100644
--- a/drivers/phy/ti-pipe3-phy.c
+++ b/drivers/phy/ti-pipe3-phy.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
* Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
@@ -16,6 +16,7 @@
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
+#include <linux/printk.h>
/* PLLCTRL Registers */
#define PLL_STATUS 0x00000004
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 34314d0..daf62f5 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
@@ -585,12 +585,20 @@
static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
{
- if (wiz->type != AM64_WIZ_10G)
+ switch (wiz->type) {
+ case AM64_WIZ_10G:
+ if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
+ return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
+ break;
+
+ case J721E_WIZ_16G:
+ case J721E_WIZ_10G:
+ if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII)
+ return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2);
+ break;
+ default:
return 0;
-
- if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
- return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
-
+ }
return 0;
}
@@ -706,7 +714,8 @@
int i;
for (i = 0; i < num_lanes; i++) {
- if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
+ if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII ||
+ wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1);
if (ret)
return ret;
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 1be6252..e834ddd 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -35,6 +35,7 @@
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/libfdt.h>
+#include <linux/printk.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
index 7976e3b..ff49819 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
@@ -329,6 +329,7 @@
static const struct group_info npcm8xx_groups[] = {
FUNC_LIST
+ {FN_gpio, "GPIO", NULL, 0, 0, 0}
};
/* Pin flags */
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index d80281f..d1db377 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <mapmem.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <dm/devres.h>
@@ -24,7 +25,7 @@
* @bits_per_mux: true if one register controls more than one pin
*/
struct single_pdata {
- fdt_addr_t base;
+ void *base;
int offset;
u32 mask;
u32 width;
@@ -97,7 +98,7 @@
#if (!IS_ENABLED(CONFIG_SANDBOX))
-static unsigned int single_read(struct udevice *dev, fdt_addr_t reg)
+static unsigned int single_read(struct udevice *dev, void *reg)
{
struct single_pdata *pdata = dev_get_plat(dev);
@@ -113,7 +114,7 @@
return readb(reg);
}
-static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg)
+static void single_write(struct udevice *dev, unsigned int val, void *reg)
{
struct single_pdata *pdata = dev_get_plat(dev);
@@ -131,18 +132,18 @@
#else /* CONFIG_SANDBOX */
-static unsigned int single_read(struct udevice *dev, fdt_addr_t reg)
+static unsigned int single_read(struct udevice *dev, void *reg)
{
struct single_priv *priv = dev_get_priv(dev);
- return priv->sandbox_regs[reg];
+ return priv->sandbox_regs[map_to_sysmem(reg)];
}
-static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg)
+static void single_write(struct udevice *dev, unsigned int val, void *reg)
{
struct single_priv *priv = dev_get_priv(dev);
- priv->sandbox_regs[reg] = val;
+ priv->sandbox_regs[map_to_sysmem(reg)] = val;
}
#endif /* CONFIG_SANDBOX */
@@ -214,7 +215,8 @@
{
struct single_pdata *pdata = dev_get_plat(dev);
struct single_priv *priv = dev_get_priv(dev);
- fdt_addr_t reg;
+ phys_addr_t phys_reg;
+ void *reg;
const char *fname;
unsigned int val;
int offset, pin_shift = 0;
@@ -226,13 +228,15 @@
reg = pdata->base + offset;
val = single_read(dev, reg);
+ phys_reg = map_to_sysmem(reg);
+
if (pdata->bits_per_mux)
pin_shift = pin % (pdata->width / priv->bits_per_pin) *
priv->bits_per_pin;
val &= (pdata->mask << pin_shift);
fname = single_get_pin_function(dev, pin);
- snprintf(buf, size, "%pa 0x%08x %s", ®, val,
+ snprintf(buf, size, "%pa 0x%08x %s", &phys_reg, val,
fname ? fname : "UNCLAIMED");
return 0;
}
@@ -243,7 +247,7 @@
struct single_pdata *pdata = dev_get_plat(dev);
struct single_gpiofunc_range *frange = NULL;
struct list_head *pos, *tmp;
- phys_addr_t reg;
+ void *reg;
int mux_bytes = 0;
u32 data;
@@ -321,7 +325,7 @@
int stride = pdata->args_count + 1;
int n, pin, count = size / sizeof(u32);
struct single_func *func;
- phys_addr_t reg;
+ void *reg;
u32 offset, val, mux;
/* If function mask is null, needn't enable it. */
@@ -379,7 +383,7 @@
int n, pin, count = size / sizeof(struct single_fdt_bits_cfg);
int npins_in_reg, pin_num_from_lsb;
struct single_func *func;
- phys_addr_t reg;
+ void *reg;
u32 offset, val, mask, bit_pos, val_pos, mask_pos, submask;
/* If function mask is null, needn't enable it. */
@@ -570,7 +574,7 @@
static int single_of_to_plat(struct udevice *dev)
{
- fdt_addr_t addr;
+ void *addr;
fdt_size_t size;
struct single_pdata *pdata = dev_get_plat(dev);
int ret;
@@ -591,8 +595,8 @@
return -EINVAL;
}
- addr = dev_read_addr_size_index(dev, 0, &size);
- if (addr == FDT_ADDR_T_NONE) {
+ addr = dev_read_addr_size_index_ptr(dev, 0, &size);
+ if (!addr) {
dev_err(dev, "failed to get base register address\n");
return -EINVAL;
}
diff --git a/drivers/pinctrl/pinctrl-sti.c b/drivers/pinctrl/pinctrl-sti.c
index 20cdbb0..1ff7ea0 100644
--- a/drivers/pinctrl/pinctrl-sti.c
+++ b/drivers/pinctrl/pinctrl-sti.c
@@ -17,6 +17,7 @@
#include <dm/pinctrl.h>
#include <linux/bug.h>
#include <linux/libfdt.h>
+#include <linux/printk.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c
index 02626a7..eb17a42 100644
--- a/drivers/pinctrl/pinctrl-zynqmp.c
+++ b/drivers/pinctrl/pinctrl-zynqmp.c
@@ -158,6 +158,12 @@
{
int ret;
+ if (param == PM_PINCTRL_CONFIG_TRI_STATE) {
+ ret = zynqmp_pm_feature(PM_PINCTRL_CONFIG_PARAM_SET);
+ if (ret < PM_PINCTRL_PARAM_SET_VERSION)
+ return -EOPNOTSUPP;
+ }
+
/* Request the pin first */
ret = xilinx_pm_request(PM_PINCTRL_REQUEST, pin, 0, 0, 0, NULL);
if (ret) {
@@ -467,6 +473,10 @@
pin);
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
+ param = PM_PINCTRL_CONFIG_TRI_STATE;
+ arg = PM_PINCTRL_TRI_STATE_ENABLE;
+ ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
+ break;
case PIN_CONFIG_LOW_POWER_MODE:
/*
* This cases are mentioned in dts but configurable
@@ -475,6 +485,11 @@
*/
ret = 0;
break;
+ case PIN_CONFIG_OUTPUT_ENABLE:
+ param = PM_PINCTRL_CONFIG_TRI_STATE;
+ arg = PM_PINCTRL_TRI_STATE_DISABLE;
+ ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
+ break;
default:
dev_warn(dev, "unsupported configuration parameter '%u'\n",
param);
@@ -533,6 +548,8 @@
&pinmux.drive_strength);
zynqmp_pm_pinctrl_get_config(selector, PM_PINCTRL_CONFIG_VOLTAGE_STATUS,
&pinmux.volt_sts);
+ zynqmp_pm_pinctrl_get_config(selector, PM_PINCTRL_CONFIG_TRI_STATE,
+ &pinmux.tri_state);
switch (pinmux.drive_strength) {
case PM_PINCTRL_DRIVE_STRENGTH_2MA:
@@ -553,13 +570,15 @@
return -EINVAL;
}
- snprintf(buf, size, "slew:%s\tbias:%s\tpull:%s\tinput:%s\tdrive:%dmA\tvolt:%s",
+ snprintf(buf, size,
+ "slew:%s\tbias:%s\tpull:%s\tinput:%s\tdrive:%dmA\tvolt:%s\ttri_state:%s",
pinmux.slew ? "slow" : "fast",
pinmux.bias ? "enabled" : "disabled",
pinmux.pull_ctrl ? "up" : "down",
pinmux.input_type ? "schmitt" : "cmos",
pinmux.drive_strength,
- pinmux.volt_sts ? "1.8" : "3.3");
+ pinmux.volt_sts ? "1.8" : "3.3",
+ pinmux.tri_state ? "enabled" : "disabled");
return 0;
}
diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index b06da50..8bb7588 100644
--- a/drivers/pinctrl/pinctrl_stm32.c
+++ b/drivers/pinctrl/pinctrl_stm32.c
@@ -18,6 +18,7 @@
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/libfdt.h>
+#include <linux/printk.h>
#include "../gpio/stm32_gpio_priv.h"
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 0ea39b4..4c8ec9f 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -131,13 +131,22 @@
help
Support pin multiplexing control on Renesas RCar Gen4 R8A779G0 SoCs.
-config PINCTRL_PFC_R7S72100
+config PINCTRL_RZA1
bool "Renesas RZ/A1 R7S72100 pin control driver"
depends on CPU_RZA1
default y if CPU_RZA1
help
Support pin multiplexing control on Renesas RZ/A1 R7S72100 SoCs.
+config PINCTRL_RZG2L
+ bool "Renesas RZ/G2L family pin control driver"
+ depends on PINCTRL
+ depends on PINCTRL_GENERIC
+ depends on PINCONF
+ help
+ Support the pinctrl functionality of the pin function controller (PFC)
+ on the Renesas RZ/G2L SoC family.
+
endif
config PINCTRL_RZN1
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index 1a61c39..cf7ec10 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -2,13 +2,13 @@
obj-$(CONFIG_PINCTRL_PFC_R8A774A1) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A774B1) += pfc-r8a77965.o
obj-$(CONFIG_PINCTRL_PFC_R8A774C0) += pfc-r8a77990.o
-obj-$(CONFIG_PINCTRL_PFC_R8A774E1) += pfc-r8a7795.o
+obj-$(CONFIG_PINCTRL_PFC_R8A774E1) += pfc-r8a77951.o
obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o
obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o
obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
-obj-$(CONFIG_PINCTRL_PFC_R8A77951) += pfc-r8a7795.o
+obj-$(CONFIG_PINCTRL_PFC_R8A77951) += pfc-r8a77951.o
obj-$(CONFIG_PINCTRL_PFC_R8A77960) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A77961) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
@@ -19,5 +19,6 @@
obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o
obj-$(CONFIG_PINCTRL_PFC_R8A779G0) += pfc-r8a779g0.o
-obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o
+obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
+obj-$(CONFIG_PINCTRL_RZG2L) += rzg2l-pfc.o
diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c
index 432895a..7203648 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7790.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7790.c
@@ -24,7 +24,7 @@
PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_30(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
@@ -5824,7 +5824,7 @@
/* SEL_I2C1 [2] */
FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, ))
},
- { },
+ { /* sentinel */ }
};
static int r8a7790_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c
index 2193331..b25453e 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7791.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7791.c
@@ -25,7 +25,7 @@
PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 26, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
@@ -6555,7 +6555,7 @@
FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
/* RESERVED [6] */ ))
},
- { },
+ { /* sentinel */ }
};
static int r8a7791_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
@@ -6877,7 +6877,7 @@
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a7791_pfc_ops = {
diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c b/drivers/pinctrl/renesas/pfc-r8a7792.c
index 81cfe81..08f1f97 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7792.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7792.c
@@ -2629,7 +2629,7 @@
/* IP7_1_0 [2] */
FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 ))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c
index 7ed54f0..e5d125c 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7794.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7794.c
@@ -43,30 +43,30 @@
PORT_GP_1(5, 25, fn, sfx), \
PORT_GP_1(5, 26, fn, sfx), \
PORT_GP_1(5, 27, fn, sfx), \
- PORT_GP_CFG_1(6, 0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
- PORT_GP_CFG_1(6, 1, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
- PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 11, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 12, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
- PORT_GP_CFG_1(6, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 23, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(6, 1, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 11, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 12, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(6, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 23, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
@@ -5513,7 +5513,7 @@
FN_SEL_SSI9_0, FN_SEL_SSI9_1,
/* RESERVED [12] */ ))
},
- { },
+ { /* sentinel */ }
};
static int r8a7794_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7795.c b/drivers/pinctrl/renesas/pfc-r8a77951.c
similarity index 99%
rename from drivers/pinctrl/renesas/pfc-r8a7795.c
rename to drivers/pinctrl/renesas/pfc-r8a77951.c
index d094bd7..5d1c81c 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7795.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77951.c
@@ -19,12 +19,12 @@
PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
@@ -5612,7 +5612,7 @@
/* RESERVED 16-1 */
MOD_SEL2_0 ))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
@@ -5863,7 +5863,7 @@
{ RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */
{ RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */
} },
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
@@ -5874,7 +5874,7 @@
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
[TDSELCTRL] = { 0xe60603c0, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a77951_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
@@ -6131,7 +6131,7 @@
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a77951_pfc_ops = {
diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c
index 3cc4a3b..163d180 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7796.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7796.c
@@ -25,12 +25,12 @@
PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
@@ -5568,7 +5568,7 @@
/* RESERVED 16-1 */
MOD_SEL2_0 ))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
@@ -5816,7 +5816,7 @@
{ RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
{ RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
} },
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
@@ -5827,7 +5827,7 @@
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
[TDSELCTRL] = { 0xe60603c0, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a7796_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
@@ -6084,7 +6084,7 @@
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a7796_pfc_ops = {
diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c
index 04e8371..377143d 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77965.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77965.c
@@ -26,12 +26,12 @@
PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
@@ -5809,7 +5809,7 @@
/* RESERVED 16-1 */
MOD_SEL2_0 ))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
@@ -6057,7 +6057,7 @@
{ RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
{ RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
} },
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
@@ -6068,7 +6068,7 @@
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
[TDSELCTRL] = { 0xe60603c0, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a77965_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
@@ -6325,7 +6325,7 @@
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a77965_pfc_ops = {
diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c
index 04f0345..1cc6fa4 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77970.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77970.c
@@ -21,10 +21,10 @@
#include "sh_pfc.h"
#define CPU_ALL_GP(fn, sfx) \
- PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
- PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
- PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
@@ -36,7 +36,8 @@
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
- PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
+ PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
/*
* F_() : just information
@@ -172,7 +173,7 @@
#define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -2344,7 +2345,7 @@
MOD_SEL0_1
MOD_SEL0_0 ))
},
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
@@ -2359,26 +2360,37 @@
[POCCTRL1] = { 0xe6060384 },
[POCCTRL2] = { 0xe6060388 },
[TDSELCTRL] = { 0xe60603c0, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a77970_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = pin & 0x1f;
- *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
- if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
+ switch (pin) {
+ case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
return bit;
- if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
+
+ case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
return bit + 22;
- *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
- if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
+ case RCAR_GP_PIN(2, 10) ... RCAR_GP_PIN(2, 16):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
return bit - 10;
- if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
+
+ case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 16):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
return bit + 7;
- return -EINVAL;
+ case PIN_VDDQ_AVB0:
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
+ return 0;
+
+ default:
+ return -EINVAL;
+ }
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c
index 19bd46c..523faa0 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77980.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77980.c
@@ -21,10 +21,10 @@
#include "sh_pfc.h"
#define CPU_ALL_GP(fn, sfx) \
- PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
- PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
- PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
@@ -37,7 +37,9 @@
PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
- PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
+ PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PIN_NOGP_CFG(VDDQ_AVB, "VDDQ_AVB", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33), \
+ PIN_NOGP_CFG(VDDQ_GE, "VDDQ_GE", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
/*
* F_() : just information
@@ -99,7 +101,7 @@
#define GPSR1_0 F_(IRQ0, IP2_27_24)
/* GPSR2 */
-#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
+#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
#define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12)
#define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8)
#define GPSR2_26 F_(SDA3, IP10_7_4)
@@ -264,11 +266,11 @@
#define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -2815,7 +2817,7 @@
MOD_SEL0_1
MOD_SEL0_0 ))
},
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
@@ -2832,31 +2834,46 @@
[POCCTRL2] = { 0xe6060388, },
[POCCTRL3] = { 0xe606038c, },
[TDSELCTRL] = { 0xe60603c0, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a77980_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = pin & 0x1f;
- *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
- if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
+ switch (pin) {
+ case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
return bit;
- else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
+
+ case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
return bit + 22;
- *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
- if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
+ case RCAR_GP_PIN(2, 10) ... RCAR_GP_PIN(2, 16):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
return bit - 10;
- if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) ||
- (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16)))
+
+ case RCAR_GP_PIN(2, 17) ... RCAR_GP_PIN(2, 24):
+ case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 16):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
return bit + 7;
- *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
- if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29))
+ case RCAR_GP_PIN(2, 25) ... RCAR_GP_PIN(2, 29):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
return pin - 25;
- return -EINVAL;
+ case PIN_VDDQ_AVB:
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg;
+ return 0;
+
+ case PIN_VDDQ_GE:
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg;
+ return 1;
+
+ default:
+ return -EINVAL;
+ }
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c
index c6c3d09..215a19e 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77990.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
@@ -26,12 +26,12 @@
PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+ PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+ PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
@@ -60,7 +60,8 @@
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
- PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP)
+ PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
/*
* F_() : just information
@@ -511,7 +512,8 @@
FM(AVB_TD3) \
FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \
FM(ASEBRK) \
- FM(MLB_REF)
+ FM(MLB_REF) \
+ FM(VDDQ_AVB0)
enum {
PINMUX_RESERVED = 0,
@@ -5006,7 +5008,7 @@
MOD_SEL1_4
/* RESERVED 3, 2, 1, 0 */ ))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
@@ -5039,33 +5041,40 @@
{ RCAR_GP_PIN(4, 9), 17, 2 }, /* SD3_DAT7 */
{ RCAR_GP_PIN(4, 10), 14, 2 }, /* SD3_DS */
} },
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
POCCTRL0,
+ POCCTRL2,
TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL0] = { 0xe6060380, },
+ [POCCTRL2] = { 0xe6060388, },
[TDSELCTRL] = { 0xe60603c0, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a77990_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
- int bit = -EINVAL;
+ switch (pin) {
+ case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 11):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
+ return pin & 0x1f;
- *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
+ case RCAR_GP_PIN(4, 0) ... RCAR_GP_PIN(4, 10):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
+ return (pin & 0x1f) + 19;
- if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
- bit = pin & 0x1f;
+ case PIN_VDDQ_AVB0:
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
+ return 0;
- if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10))
- bit = (pin & 0x1f) + 19;
-
- return bit;
+ default:
+ return -EINVAL;
+ }
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
@@ -5273,7 +5282,7 @@
[30] = RCAR_GP_PIN(6, 9), /* USB30_OVC */
[31] = RCAR_GP_PIN(6, 17), /* USB30_PWEN */
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a77990_pfc_ops = {
diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c
index 06caf16..c0d6993 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77995.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77995.c
@@ -23,7 +23,7 @@
PORT_GP_CFG_9(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
- PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_21(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_14(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
@@ -36,7 +36,8 @@
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
- PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
+ PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
/*
* F_() : just information
@@ -2854,19 +2855,37 @@
MOD_SEL1_26
/* RESERVED 25-0 */ ))
},
- { },
+ { /* sentinel */ }
};
+enum ioctrl_regs {
+ POCCTRL0,
+ POCCTRL2,
+ TDSELCTRL,
+};
+
+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
+ [POCCTRL0] = { 0xe6060380, },
+ [POCCTRL2] = { 0xe6060388, },
+ [TDSELCTRL] = { 0xe60603c0, },
+ { /* sentinel */ }
+};
+
+
static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
- int bit = -EINVAL;
+ switch (pin) {
+ case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 9):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
+ return 29 - (pin - RCAR_GP_PIN(3, 0));
- *pocctrl = 0xe6060380;
+ case PIN_VDDQ_AVB0:
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
+ return 0;
- if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9))
- bit = 29 - (pin - RCAR_GP_PIN(3, 0));
-
- return bit;
+ default:
+ return -EINVAL;
+ }
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
@@ -3077,15 +3096,6 @@
{ /* sentinel */ }
};
-enum ioctrl_regs {
- TDSELCTRL,
-};
-
-static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
- [TDSELCTRL] = { 0xe60603c0, },
- { /* sentinel */ },
-};
-
static const struct pinmux_bias_reg *
r8a77995_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
unsigned int *puen_bit, unsigned int *pud_bit)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index 0f570e4..3c4b03b 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -3633,7 +3633,7 @@
MOD_SEL2_3_2
/* RESERVED 1-0 */ ))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
@@ -3938,7 +3938,7 @@
{ RCAR_GP_PIN(9, 17), 4, 3 }, /* AVB5_LINK */
{ RCAR_GP_PIN(9, 16), 0, 3 }, /* AVB5_PHY_INT */
} },
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
@@ -3965,7 +3965,7 @@
[POC8] = { 0xe60690a0, },
[POC9] = { 0xe60698a0, },
[TD1SEL0] = { 0xe6058124, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a779a0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
@@ -4352,7 +4352,7 @@
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a779a0_pfc_ops = {
diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c
index e2ac9d1..5123e26 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779f0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c
@@ -1216,7 +1216,7 @@
RCAR_GP_PIN(3, 13),
};
static const unsigned int tsn1_avtp_pps_mux[] = {
- TSN0_AVTP_PPS_MARK,
+ TSN1_AVTP_PPS_MARK,
};
static const unsigned int tsn1_avtp_capture_a_pins[] = {
/* TSN1_AVTP_CAPTURE_A */
@@ -1787,7 +1787,7 @@
MOD_SEL1_3_2
MOD_SEL1_1_0))
},
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
@@ -1899,7 +1899,7 @@
{ RCAR_GP_PIN(3, 17), 4, 3 }, /* TSN0_AVTP_MATCH_B */
{ RCAR_GP_PIN(3, 16), 0, 3 }, /* TSN0_AVTP_PPS */
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
enum ioctrl_regs {
@@ -1914,7 +1914,7 @@
[POC1] = { 0xe60508a0, },
[POC3] = { 0xe60518a0, },
[TD0SEL1] = { 0xe6050920, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a779f0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
@@ -2073,7 +2073,7 @@
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a779f0_pfc_ops = {
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index 78a91f4..20498a1 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -52,6 +52,12 @@
PORT_GP_CFG_21(7, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_14(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
+#define CPU_ALL_NOGP(fn) \
+ PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
+ PIN_NOGP_CFG(VDDQ_AVB1, "VDDQ_AVB1", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
+ PIN_NOGP_CFG(VDDQ_AVB2, "VDDQ_AVB2", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
+ PIN_NOGP_CFG(VDDQ_TSN0, "VDDQ_TSN0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25)
+
/* GPSR0 */
#define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8)
#define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4)
@@ -159,54 +165,54 @@
#define GPSR3_0 F_(MMC_SD_D1, IP0SR3_3_0)
/* GPSR4 */
-#define GPSR4_24 FM(AVS1)
-#define GPSR4_23 FM(AVS0)
-#define GPSR4_22 FM(PCIE1_CLKREQ_N)
-#define GPSR4_21 FM(PCIE0_CLKREQ_N)
-#define GPSR4_20 FM(TSN0_TXCREFCLK)
-#define GPSR4_19 FM(TSN0_TD2)
-#define GPSR4_18 FM(TSN0_TD3)
-#define GPSR4_17 FM(TSN0_RD2)
-#define GPSR4_16 FM(TSN0_RD3)
-#define GPSR4_15 FM(TSN0_TD0)
-#define GPSR4_14 FM(TSN0_TD1)
-#define GPSR4_13 FM(TSN0_RD1)
-#define GPSR4_12 FM(TSN0_TXC)
-#define GPSR4_11 FM(TSN0_RXC)
-#define GPSR4_10 FM(TSN0_RD0)
-#define GPSR4_9 FM(TSN0_TX_CTL)
-#define GPSR4_8 FM(TSN0_AVTP_PPS0)
-#define GPSR4_7 FM(TSN0_RX_CTL)
-#define GPSR4_6 FM(TSN0_AVTP_CAPTURE)
-#define GPSR4_5 FM(TSN0_AVTP_MATCH)
-#define GPSR4_4 FM(TSN0_LINK)
-#define GPSR4_3 FM(TSN0_PHY_INT)
-#define GPSR4_2 FM(TSN0_AVTP_PPS1)
-#define GPSR4_1 FM(TSN0_MDC)
-#define GPSR4_0 FM(TSN0_MDIO)
+#define GPSR4_24 F_(AVS1, IP3SR4_3_0)
+#define GPSR4_23 F_(AVS0, IP2SR4_31_28)
+#define GPSR4_22 F_(PCIE1_CLKREQ_N, IP2SR4_27_24)
+#define GPSR4_21 F_(PCIE0_CLKREQ_N, IP2SR4_23_20)
+#define GPSR4_20 F_(TSN0_TXCREFCLK, IP2SR4_19_16)
+#define GPSR4_19 F_(TSN0_TD2, IP2SR4_15_12)
+#define GPSR4_18 F_(TSN0_TD3, IP2SR4_11_8)
+#define GPSR4_17 F_(TSN0_RD2, IP2SR4_7_4)
+#define GPSR4_16 F_(TSN0_RD3, IP2SR4_3_0)
+#define GPSR4_15 F_(TSN0_TD0, IP1SR4_31_28)
+#define GPSR4_14 F_(TSN0_TD1, IP1SR4_27_24)
+#define GPSR4_13 F_(TSN0_RD1, IP1SR4_23_20)
+#define GPSR4_12 F_(TSN0_TXC, IP1SR4_19_16)
+#define GPSR4_11 F_(TSN0_RXC, IP1SR4_15_12)
+#define GPSR4_10 F_(TSN0_RD0, IP1SR4_11_8)
+#define GPSR4_9 F_(TSN0_TX_CTL, IP1SR4_7_4)
+#define GPSR4_8 F_(TSN0_AVTP_PPS0, IP1SR4_3_0)
+#define GPSR4_7 F_(TSN0_RX_CTL, IP0SR4_31_28)
+#define GPSR4_6 F_(TSN0_AVTP_CAPTURE, IP0SR4_27_24)
+#define GPSR4_5 F_(TSN0_AVTP_MATCH, IP0SR4_23_20)
+#define GPSR4_4 F_(TSN0_LINK, IP0SR4_19_16)
+#define GPSR4_3 F_(TSN0_PHY_INT, IP0SR4_15_12)
+#define GPSR4_2 F_(TSN0_AVTP_PPS1, IP0SR4_11_8)
+#define GPSR4_1 F_(TSN0_MDC, IP0SR4_7_4)
+#define GPSR4_0 F_(TSN0_MDIO, IP0SR4_3_0)
/* GPSR 5 */
-#define GPSR5_20 FM(AVB2_RX_CTL)
-#define GPSR5_19 FM(AVB2_TX_CTL)
-#define GPSR5_18 FM(AVB2_RXC)
-#define GPSR5_17 FM(AVB2_RD0)
-#define GPSR5_16 FM(AVB2_TXC)
-#define GPSR5_15 FM(AVB2_TD0)
-#define GPSR5_14 FM(AVB2_RD1)
-#define GPSR5_13 FM(AVB2_RD2)
-#define GPSR5_12 FM(AVB2_TD1)
-#define GPSR5_11 FM(AVB2_TD2)
-#define GPSR5_10 FM(AVB2_MDIO)
-#define GPSR5_9 FM(AVB2_RD3)
-#define GPSR5_8 FM(AVB2_TD3)
-#define GPSR5_7 FM(AVB2_TXCREFCLK)
-#define GPSR5_6 FM(AVB2_MDC)
-#define GPSR5_5 FM(AVB2_MAGIC)
-#define GPSR5_4 FM(AVB2_PHY_INT)
-#define GPSR5_3 FM(AVB2_LINK)
-#define GPSR5_2 FM(AVB2_AVTP_MATCH)
-#define GPSR5_1 FM(AVB2_AVTP_CAPTURE)
-#define GPSR5_0 FM(AVB2_AVTP_PPS)
+#define GPSR5_20 F_(AVB2_RX_CTL, IP2SR5_19_16)
+#define GPSR5_19 F_(AVB2_TX_CTL, IP2SR5_15_12)
+#define GPSR5_18 F_(AVB2_RXC, IP2SR5_11_8)
+#define GPSR5_17 F_(AVB2_RD0, IP2SR5_7_4)
+#define GPSR5_16 F_(AVB2_TXC, IP2SR5_3_0)
+#define GPSR5_15 F_(AVB2_TD0, IP1SR5_31_28)
+#define GPSR5_14 F_(AVB2_RD1, IP1SR5_27_24)
+#define GPSR5_13 F_(AVB2_RD2, IP1SR5_23_20)
+#define GPSR5_12 F_(AVB2_TD1, IP1SR5_19_16)
+#define GPSR5_11 F_(AVB2_TD2, IP1SR5_15_12)
+#define GPSR5_10 F_(AVB2_MDIO, IP1SR5_11_8)
+#define GPSR5_9 F_(AVB2_RD3, IP1SR5_7_4)
+#define GPSR5_8 F_(AVB2_TD3, IP1SR5_3_0)
+#define GPSR5_7 F_(AVB2_TXCREFCLK, IP0SR5_31_28)
+#define GPSR5_6 F_(AVB2_MDC, IP0SR5_27_24)
+#define GPSR5_5 F_(AVB2_MAGIC, IP0SR5_23_20)
+#define GPSR5_4 F_(AVB2_PHY_INT, IP0SR5_19_16)
+#define GPSR5_3 F_(AVB2_LINK, IP0SR5_15_12)
+#define GPSR5_2 F_(AVB2_AVTP_MATCH, IP0SR5_11_8)
+#define GPSR5_1 F_(AVB2_AVTP_CAPTURE, IP0SR5_7_4)
+#define GPSR5_0 F_(AVB2_AVTP_PPS, IP0SR5_3_0)
/* GPSR 6 */
#define GPSR6_20 F_(AVB1_TXCREFCLK, IP2SR6_19_16)
@@ -271,209 +277,271 @@
#define GPSR8_0 F_(SCL0, IP0SR8_3_0)
/* SR0 */
-/* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_B) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_15_12 FM(IRQ3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_19_16 FM(IRQ2) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_23_20 FM(IRQ1) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_27_24 FM(IRQ0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_15_12 FM(IRQ3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_19_16 FM(IRQ2) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_23_20 FM(IRQ1) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_27_24 FM(IRQ0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-/* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP1SR0_3_0 FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR0_7_4 FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR0_11_8 FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP1SR0_3_0 FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_7_4 FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_11_8 FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-/* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR1 */
-/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_A) FM(TX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_A) FM(RX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_A) FM(RTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) FM(CTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) FM(SCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_X) FM(TX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_X) FM(RX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_A) FM(TX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_A) FM(RX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_A) FM(RTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) FM(CTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) FM(SCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_X) FM(TX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_X) FM(RX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-/* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_X) FM(CTS1_N_X) FM(CANFD5_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_X) FM(RTS1_N_X) FM(CANFD5_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_X) FM(SCK1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_X) FM(CTS1_N_X) FM(CANFD5_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_X) FM(RTS1_N_X) FM(CANFD5_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_X) FM(SCK1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-/* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_7_4 FM(SCIF_CLK) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_31_28 F_(0, 0) FM(TCLK2) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_7_4 FM(SCIF_CLK) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_31_28 F_(0, 0) FM(TCLK2) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP3SR1_3_0 FM(HRX3) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_7_4 FM(HSCK3) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_15_12 FM(HCTS3_N) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_19_16 FM(HTX3) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP3SR1_3_0 FM(HRX3) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_7_4 FM(HSCK3) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_15_12 FM(HCTS3_N) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_19_16 FM(HTX3) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR2 */
-/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_7_4 FM(FXR_TXENA_N) FM(CANFD1_RX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_23_20 FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_31_28 FM(TPU0TO1) FM(CANFD6_TX) F_(0, 0) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_7_4 FM(FXR_TXENA_N) FM(CANFD1_RX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_23_20 FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_31_28 FM(TPU0TO1) FM(CANFD6_TX) F_(0, 0) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-/* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP1SR2_3_0 FM(TPU0TO0) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2) F_(0, 0) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1_B) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP1SR2_3_0 FM(TPU0TO0) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2) F_(0, 0) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1_B) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-/* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP2SR2_3_0 FM(CANFD4_TX) F_(0, 0) FM(PWM4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR2_7_4 FM(CANFD4_RX) F_(0, 0) FM(PWM5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR2_11_8 FM(CANFD7_TX) F_(0, 0) FM(PWM6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR2_15_12 FM(CANFD7_RX) F_(0, 0) FM(PWM7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP2SR2_3_0 FM(CANFD4_TX) F_(0, 0) FM(PWM4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR2_7_4 FM(CANFD4_RX) F_(0, 0) FM(PWM5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR2_11_8 FM(CANFD7_TX) F_(0, 0) FM(PWM6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR2_15_12 FM(CANFD7_RX) F_(0, 0) FM(PWM7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR3 */
-/* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP0SR3_3_0 FM(MMC_SD_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR3_7_4 FM(MMC_SD_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR3_11_8 FM(MMC_SD_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR3_15_12 FM(MMC_SD_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR3_19_16 FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR3_23_20 FM(MMC_SD_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR3_27_24 FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR3_31_28 FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP0SR3_3_0 FM(MMC_SD_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_7_4 FM(MMC_SD_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_11_8 FM(MMC_SD_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_15_12 FM(MMC_SD_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_19_16 FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_23_20 FM(MMC_SD_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_27_24 FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_31_28 FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-/* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP1SR3_3_0 FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR3_7_4 FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) FM(PWM1_A) FM(TCLK3_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) FM(ERROROUTC_A) FM(TCLK4_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP1SR3_3_0 FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_7_4 FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) FM(PWM1_A) FM(TCLK3_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) FM(ERROROUTC_N_A) FM(TCLK4_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-/* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP2SR3_3_0 FM(QSPI0_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR3_7_4 FM(QSPI0_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR3_11_8 FM(QSPI0_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR3_15_12 FM(QSPI0_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR3_19_16 FM(QSPI0_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR3_23_20 FM(QSPI1_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR3_27_24 FM(QSPI1_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR3_31_28 FM(QSPI1_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP2SR3_3_0 FM(QSPI0_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR3_7_4 FM(QSPI0_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR3_11_8 FM(QSPI0_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR3_15_12 FM(QSPI0_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR3_19_16 FM(QSPI0_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR3_23_20 FM(QSPI1_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR3_27_24 FM(QSPI1_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR3_31_28 FM(QSPI1_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-/* IP3SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP3SR3_3_0 FM(QSPI1_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR3_7_4 FM(QSPI1_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR3_11_8 FM(QSPI1_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR3_15_12 FM(RPC_RESET_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR3_19_16 FM(RPC_WP_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR3_23_20 FM(RPC_INT_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP3SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP3SR3_3_0 FM(QSPI1_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR3_7_4 FM(QSPI1_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR3_11_8 FM(QSPI1_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR3_15_12 FM(RPC_RESET_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR3_19_16 FM(RPC_WP_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR3_23_20 FM(RPC_INT_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* SR4 */
+/* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP0SR4_3_0 FM(TSN0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR4_7_4 FM(TSN0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR4_11_8 FM(TSN0_AVTP_PPS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR4_15_12 FM(TSN0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR4_19_16 FM(TSN0_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR4_23_20 FM(TSN0_AVTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR4_27_24 FM(TSN0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR4_31_28 FM(TSN0_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP1SR4_3_0 FM(TSN0_AVTP_PPS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR4_7_4 FM(TSN0_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR4_11_8 FM(TSN0_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR4_15_12 FM(TSN0_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR4_19_16 FM(TSN0_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR4_23_20 FM(TSN0_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR4_27_24 FM(TSN0_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR4_31_28 FM(TSN0_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP2SR4_3_0 FM(TSN0_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR4_7_4 FM(TSN0_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR4_11_8 FM(TSN0_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR4_15_12 FM(TSN0_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR4_19_16 FM(TSN0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR4_23_20 FM(PCIE0_CLKREQ_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR4_27_24 FM(PCIE1_CLKREQ_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR4_31_28 FM(AVS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP3SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP3SR4_3_0 FM(AVS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* SR5 */
+/* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP0SR5_3_0 FM(AVB2_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR5_7_4 FM(AVB2_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR5_11_8 FM(AVB2_AVTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR5_15_12 FM(AVB2_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR5_19_16 FM(AVB2_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR5_23_20 FM(AVB2_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR5_27_24 FM(AVB2_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR5_31_28 FM(AVB2_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP1SR5_3_0 FM(AVB2_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR5_7_4 FM(AVB2_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR5_11_8 FM(AVB2_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR5_15_12 FM(AVB2_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR5_19_16 FM(AVB2_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR5_23_20 FM(AVB2_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR5_27_24 FM(AVB2_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR5_31_28 FM(AVB2_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP2SR5_3_0 FM(AVB2_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR5_7_4 FM(AVB2_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR5_11_8 FM(AVB2_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR5_15_12 FM(AVB2_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR5_19_16 FM(AVB2_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR6 */
-/* IP0SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP0SR6_3_0 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR6_7_4 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR6_11_8 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR6_15_12 FM(AVB1_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR6_19_16 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR6_27_24 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR6_31_28 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP0SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP0SR6_3_0 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR6_7_4 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR6_11_8 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR6_15_12 FM(AVB1_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR6_19_16 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR6_27_24 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR6_31_28 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-/* IP1SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP1SR6_3_0 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR6_7_4 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR6_11_8 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR6_19_16 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR6_23_20 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR6_27_24 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR6_31_28 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP1SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP1SR6_3_0 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR6_7_4 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR6_11_8 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR6_19_16 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR6_23_20 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR6_27_24 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR6_31_28 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-/* IP2SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP2SR6_3_0 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR6_7_4 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR6_11_8 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR6_15_12 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR6_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP2SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP2SR6_3_0 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR6_7_4 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR6_11_8 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR6_15_12 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR6_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR7 */
-/* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR7_27_24 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR7_31_28 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR7_27_24 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR7_31_28 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-/* IP1SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP1SR7_3_0 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR7_7_4 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR7_11_8 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR7_15_12 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR7_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR7_23_20 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR7_27_24 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR7_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP1SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP1SR7_3_0 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR7_7_4 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR7_11_8 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR7_15_12 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR7_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR7_23_20 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR7_27_24 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR7_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-/* IP2SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP2SR7_3_0 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR7_7_4 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR7_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR7_15_12 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR7_19_16 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP2SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP2SR7_3_0 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR7_7_4 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR7_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR7_15_12 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR7_19_16 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR8 */
-/* IP0SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP0SR8_3_0 FM(SCL0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR8_7_4 FM(SDA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR8_11_8 FM(SCL1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR8_15_12 FM(SDA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR8_19_16 FM(SCL2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR8_23_20 FM(SDA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR8_27_24 FM(SCL3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR8_31_28 FM(SDA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP0SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP0SR8_3_0 FM(SCL0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR8_7_4 FM(SDA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR8_11_8 FM(SCL1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR8_15_12 FM(SDA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR8_19_16 FM(SCL2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR8_23_20 FM(SDA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR8_27_24 FM(SCL3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR8_31_28 FM(SDA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-/* IP1SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP1SR8_3_0 FM(SCL4) FM(HRX2) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR8_7_4 FM(SDA4) FM(HTX2) FM(CTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR8_11_8 FM(SCL5) FM(HRTS2_N) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR8_15_12 FM(SDA5) FM(SCIF_CLK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR8_19_16 F_(0, 0) FM(HCTS2_N) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR8_23_20 F_(0, 0) FM(HSCK2) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP1SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
+#define IP1SR8_3_0 FM(SCL4) FM(HRX2) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR8_7_4 FM(SDA4) FM(HTX2) FM(CTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR8_11_8 FM(SCL5) FM(HRTS2_N) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR8_15_12 FM(SDA5) FM(SCIF_CLK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR8_19_16 F_(0, 0) FM(HCTS2_N) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR8_23_20 F_(0, 0) FM(HSCK2) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define PINMUX_GPSR \
GPSR3_29 \
@@ -545,6 +613,24 @@
FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 FM(IP2SR3_27_24) IP2SR3_27_24 \
FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 FM(IP2SR3_31_28) IP2SR3_31_28 \
\
+FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP2SR4_3_0) IP2SR4_3_0 FM(IP3SR4_3_0) IP3SR4_3_0 \
+FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 FM(IP2SR4_7_4) IP2SR4_7_4 \
+FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 FM(IP2SR4_11_8) IP2SR4_11_8 \
+FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 FM(IP2SR4_15_12) IP2SR4_15_12 \
+FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 FM(IP2SR4_19_16) IP2SR4_19_16 \
+FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \
+FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 FM(IP2SR4_27_24) IP2SR4_27_24 \
+FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \
+\
+FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \
+FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \
+FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \
+FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \
+FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \
+FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 \
+FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 \
+FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 \
+\
FM(IP0SR6_3_0) IP0SR6_3_0 FM(IP1SR6_3_0) IP1SR6_3_0 FM(IP2SR6_3_0) IP2SR6_3_0 \
FM(IP0SR6_7_4) IP0SR6_7_4 FM(IP1SR6_7_4) IP1SR6_7_4 FM(IP2SR6_7_4) IP2SR6_7_4 \
FM(IP0SR6_11_8) IP0SR6_11_8 FM(IP1SR6_11_8) IP1SR6_11_8 FM(IP2SR6_11_8) IP2SR6_11_8 \
@@ -572,54 +658,6 @@
FM(IP0SR8_27_24) IP0SR8_27_24 \
FM(IP0SR8_31_28) IP0SR8_31_28
-/* MOD_SEL4 */ /* 0 */ /* 1 */
-#define MOD_SEL4_19 FM(SEL_TSN0_TD2_0) FM(SEL_TSN0_TD2_1)
-#define MOD_SEL4_18 FM(SEL_TSN0_TD3_0) FM(SEL_TSN0_TD3_1)
-#define MOD_SEL4_15 FM(SEL_TSN0_TD0_0) FM(SEL_TSN0_TD0_1)
-#define MOD_SEL4_14 FM(SEL_TSN0_TD1_0) FM(SEL_TSN0_TD1_1)
-#define MOD_SEL4_12 FM(SEL_TSN0_TXC_0) FM(SEL_TSN0_TXC_1)
-#define MOD_SEL4_9 FM(SEL_TSN0_TX_CTL_0) FM(SEL_TSN0_TX_CTL_1)
-#define MOD_SEL4_8 FM(SEL_TSN0_AVTP_PPS0_0) FM(SEL_TSN0_AVTP_PPS0_1)
-#define MOD_SEL4_5 FM(SEL_TSN0_AVTP_MATCH_0) FM(SEL_TSN0_AVTP_MATCH_1)
-#define MOD_SEL4_2 FM(SEL_TSN0_AVTP_PPS1_0) FM(SEL_TSN0_AVTP_PPS1_1)
-#define MOD_SEL4_1 FM(SEL_TSN0_MDC_0) FM(SEL_TSN0_MDC_1)
-
-/* MOD_SEL5 */ /* 0 */ /* 1 */
-#define MOD_SEL5_19 FM(SEL_AVB2_TX_CTL_0) FM(SEL_AVB2_TX_CTL_1)
-#define MOD_SEL5_16 FM(SEL_AVB2_TXC_0) FM(SEL_AVB2_TXC_1)
-#define MOD_SEL5_15 FM(SEL_AVB2_TD0_0) FM(SEL_AVB2_TD0_1)
-#define MOD_SEL5_12 FM(SEL_AVB2_TD1_0) FM(SEL_AVB2_TD1_1)
-#define MOD_SEL5_11 FM(SEL_AVB2_TD2_0) FM(SEL_AVB2_TD2_1)
-#define MOD_SEL5_8 FM(SEL_AVB2_TD3_0) FM(SEL_AVB2_TD3_1)
-#define MOD_SEL5_6 FM(SEL_AVB2_MDC_0) FM(SEL_AVB2_MDC_1)
-#define MOD_SEL5_5 FM(SEL_AVB2_MAGIC_0) FM(SEL_AVB2_MAGIC_1)
-#define MOD_SEL5_2 FM(SEL_AVB2_AVTP_MATCH_0) FM(SEL_AVB2_AVTP_MATCH_1)
-#define MOD_SEL5_0 FM(SEL_AVB2_AVTP_PPS_0) FM(SEL_AVB2_AVTP_PPS_1)
-
-/* MOD_SEL6 */ /* 0 */ /* 1 */
-#define MOD_SEL6_18 FM(SEL_AVB1_TD3_0) FM(SEL_AVB1_TD3_1)
-#define MOD_SEL6_16 FM(SEL_AVB1_TD2_0) FM(SEL_AVB1_TD2_1)
-#define MOD_SEL6_13 FM(SEL_AVB1_TD0_0) FM(SEL_AVB1_TD0_1)
-#define MOD_SEL6_12 FM(SEL_AVB1_TD1_0) FM(SEL_AVB1_TD1_1)
-#define MOD_SEL6_10 FM(SEL_AVB1_AVTP_PPS_0) FM(SEL_AVB1_AVTP_PPS_1)
-#define MOD_SEL6_7 FM(SEL_AVB1_TX_CTL_0) FM(SEL_AVB1_TX_CTL_1)
-#define MOD_SEL6_6 FM(SEL_AVB1_TXC_0) FM(SEL_AVB1_TXC_1)
-#define MOD_SEL6_5 FM(SEL_AVB1_AVTP_MATCH_0) FM(SEL_AVB1_AVTP_MATCH_1)
-#define MOD_SEL6_2 FM(SEL_AVB1_MDC_0) FM(SEL_AVB1_MDC_1)
-#define MOD_SEL6_1 FM(SEL_AVB1_MAGIC_0) FM(SEL_AVB1_MAGIC_1)
-
-/* MOD_SEL7 */ /* 0 */ /* 1 */
-#define MOD_SEL7_16 FM(SEL_AVB0_TX_CTL_0) FM(SEL_AVB0_TX_CTL_1)
-#define MOD_SEL7_15 FM(SEL_AVB0_TXC_0) FM(SEL_AVB0_TXC_1)
-#define MOD_SEL7_13 FM(SEL_AVB0_MDC_0) FM(SEL_AVB0_MDC_1)
-#define MOD_SEL7_11 FM(SEL_AVB0_TD0_0) FM(SEL_AVB0_TD0_1)
-#define MOD_SEL7_10 FM(SEL_AVB0_MAGIC_0) FM(SEL_AVB0_MAGIC_1)
-#define MOD_SEL7_7 FM(SEL_AVB0_TD1_0) FM(SEL_AVB0_TD1_1)
-#define MOD_SEL7_6 FM(SEL_AVB0_TD2_0) FM(SEL_AVB0_TD2_1)
-#define MOD_SEL7_3 FM(SEL_AVB0_TD3_0) FM(SEL_AVB0_TD3_1)
-#define MOD_SEL7_2 FM(SEL_AVB0_AVTP_MATCH_0) FM(SEL_AVB0_AVTP_MATCH_1)
-#define MOD_SEL7_0 FM(SEL_AVB0_AVTP_PPS_0) FM(SEL_AVB0_AVTP_PPS_1)
-
/* MOD_SEL8 */ /* 0 */ /* 1 */
#define MOD_SEL8_11 FM(SEL_SDA5_0) FM(SEL_SDA5_1)
#define MOD_SEL8_10 FM(SEL_SCL5_0) FM(SEL_SCL5_1)
@@ -636,26 +674,18 @@
#define PINMUX_MOD_SELS \
\
-MOD_SEL4_19 MOD_SEL5_19 \
-MOD_SEL4_18 MOD_SEL6_18 \
- \
- MOD_SEL5_16 MOD_SEL6_16 MOD_SEL7_16 \
-MOD_SEL4_15 MOD_SEL5_15 MOD_SEL7_15 \
-MOD_SEL4_14 \
- MOD_SEL6_13 MOD_SEL7_13 \
-MOD_SEL4_12 MOD_SEL5_12 MOD_SEL6_12 \
- MOD_SEL5_11 MOD_SEL7_11 MOD_SEL8_11 \
- MOD_SEL6_10 MOD_SEL7_10 MOD_SEL8_10 \
-MOD_SEL4_9 MOD_SEL8_9 \
-MOD_SEL4_8 MOD_SEL5_8 MOD_SEL8_8 \
- MOD_SEL6_7 MOD_SEL7_7 MOD_SEL8_7 \
- MOD_SEL5_6 MOD_SEL6_6 MOD_SEL7_6 MOD_SEL8_6 \
-MOD_SEL4_5 MOD_SEL5_5 MOD_SEL6_5 MOD_SEL8_5 \
- MOD_SEL8_4 \
- MOD_SEL7_3 MOD_SEL8_3 \
-MOD_SEL4_2 MOD_SEL5_2 MOD_SEL6_2 MOD_SEL7_2 MOD_SEL8_2 \
-MOD_SEL4_1 MOD_SEL6_1 MOD_SEL8_1 \
- MOD_SEL5_0 MOD_SEL7_0 MOD_SEL8_0
+MOD_SEL8_11 \
+MOD_SEL8_10 \
+MOD_SEL8_9 \
+MOD_SEL8_8 \
+MOD_SEL8_7 \
+MOD_SEL8_6 \
+MOD_SEL8_5 \
+MOD_SEL8_4 \
+MOD_SEL8_3 \
+MOD_SEL8_2 \
+MOD_SEL8_1 \
+MOD_SEL8_0
enum {
PINMUX_RESERVED = 0,
@@ -689,61 +719,8 @@
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(),
- PINMUX_SINGLE(AVS1),
- PINMUX_SINGLE(AVS0),
- PINMUX_SINGLE(PCIE1_CLKREQ_N),
- PINMUX_SINGLE(PCIE0_CLKREQ_N),
-
- /* TSN0 without MODSEL4 */
- PINMUX_SINGLE(TSN0_TXCREFCLK),
- PINMUX_SINGLE(TSN0_RD2),
- PINMUX_SINGLE(TSN0_RD3),
- PINMUX_SINGLE(TSN0_RD1),
- PINMUX_SINGLE(TSN0_RXC),
- PINMUX_SINGLE(TSN0_RD0),
- PINMUX_SINGLE(TSN0_RX_CTL),
- PINMUX_SINGLE(TSN0_AVTP_CAPTURE),
- PINMUX_SINGLE(TSN0_LINK),
- PINMUX_SINGLE(TSN0_PHY_INT),
- PINMUX_SINGLE(TSN0_MDIO),
- /* TSN0 with MODSEL4 */
- PINMUX_IPSR_NOGM(0, TSN0_TD2, SEL_TSN0_TD2_1),
- PINMUX_IPSR_NOGM(0, TSN0_TD3, SEL_TSN0_TD3_1),
- PINMUX_IPSR_NOGM(0, TSN0_TD0, SEL_TSN0_TD0_1),
- PINMUX_IPSR_NOGM(0, TSN0_TD1, SEL_TSN0_TD1_1),
- PINMUX_IPSR_NOGM(0, TSN0_TXC, SEL_TSN0_TXC_1),
- PINMUX_IPSR_NOGM(0, TSN0_TX_CTL, SEL_TSN0_TX_CTL_1),
- PINMUX_IPSR_NOGM(0, TSN0_AVTP_PPS0, SEL_TSN0_AVTP_PPS0_1),
- PINMUX_IPSR_NOGM(0, TSN0_AVTP_MATCH, SEL_TSN0_AVTP_MATCH_1),
- PINMUX_IPSR_NOGM(0, TSN0_AVTP_PPS1, SEL_TSN0_AVTP_PPS1_1),
- PINMUX_IPSR_NOGM(0, TSN0_MDC, SEL_TSN0_MDC_1),
-
- /* TSN0 without MODSEL5 */
- PINMUX_SINGLE(AVB2_RX_CTL),
- PINMUX_SINGLE(AVB2_RXC),
- PINMUX_SINGLE(AVB2_RD0),
- PINMUX_SINGLE(AVB2_RD1),
- PINMUX_SINGLE(AVB2_RD2),
- PINMUX_SINGLE(AVB2_MDIO),
- PINMUX_SINGLE(AVB2_RD3),
- PINMUX_SINGLE(AVB2_TXCREFCLK),
- PINMUX_SINGLE(AVB2_PHY_INT),
- PINMUX_SINGLE(AVB2_LINK),
- PINMUX_SINGLE(AVB2_AVTP_CAPTURE),
- /* TSN0 with MODSEL5 */
- PINMUX_IPSR_NOGM(0, AVB2_TX_CTL, SEL_AVB2_TX_CTL_1),
- PINMUX_IPSR_NOGM(0, AVB2_TXC, SEL_AVB2_TXC_1),
- PINMUX_IPSR_NOGM(0, AVB2_TD0, SEL_AVB2_TD0_1),
- PINMUX_IPSR_NOGM(0, AVB2_TD1, SEL_AVB2_TD1_1),
- PINMUX_IPSR_NOGM(0, AVB2_TD2, SEL_AVB2_TD2_1),
- PINMUX_IPSR_NOGM(0, AVB2_TD3, SEL_AVB2_TD3_1),
- PINMUX_IPSR_NOGM(0, AVB2_MDC, SEL_AVB2_MDC_1),
- PINMUX_IPSR_NOGM(0, AVB2_MAGIC, SEL_AVB2_MAGIC_1),
- PINMUX_IPSR_NOGM(0, AVB2_AVTP_MATCH, SEL_AVB2_AVTP_MATCH_1),
- PINMUX_IPSR_NOGM(0, AVB2_AVTP_PPS, SEL_AVB2_AVTP_PPS_1),
-
/* IP0SR0 */
- PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC_B),
+ PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC_N_B),
PINMUX_IPSR_GPSR(IP0SR0_3_0, TCLK2_A),
PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SS1),
@@ -1009,7 +986,7 @@
PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKOUT),
PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKEN_OUT),
- PINMUX_IPSR_GPSR(IP1SR3_27_24, ERROROUTC_A),
+ PINMUX_IPSR_GPSR(IP1SR3_27_24, ERROROUTC_N_A),
PINMUX_IPSR_GPSR(IP1SR3_27_24, TCLK4_X),
PINMUX_IPSR_GPSR(IP1SR3_31_28, QSPI0_SSL),
@@ -1032,26 +1009,86 @@
PINMUX_IPSR_GPSR(IP3SR3_19_16, RPC_WP_N),
PINMUX_IPSR_GPSR(IP3SR3_23_20, RPC_INT_N),
+ /* IP0SR4 */
+ PINMUX_IPSR_GPSR(IP0SR4_3_0, TSN0_MDIO),
+ PINMUX_IPSR_GPSR(IP0SR4_7_4, TSN0_MDC),
+ PINMUX_IPSR_GPSR(IP0SR4_11_8, TSN0_AVTP_PPS1),
+ PINMUX_IPSR_GPSR(IP0SR4_15_12, TSN0_PHY_INT),
+ PINMUX_IPSR_GPSR(IP0SR4_19_16, TSN0_LINK),
+ PINMUX_IPSR_GPSR(IP0SR4_23_20, TSN0_AVTP_MATCH),
+ PINMUX_IPSR_GPSR(IP0SR4_27_24, TSN0_AVTP_CAPTURE),
+ PINMUX_IPSR_GPSR(IP0SR4_31_28, TSN0_RX_CTL),
+
+ /* IP1SR4 */
+ PINMUX_IPSR_GPSR(IP1SR4_3_0, TSN0_AVTP_PPS0),
+ PINMUX_IPSR_GPSR(IP1SR4_7_4, TSN0_TX_CTL),
+ PINMUX_IPSR_GPSR(IP1SR4_11_8, TSN0_RD0),
+ PINMUX_IPSR_GPSR(IP1SR4_15_12, TSN0_RXC),
+ PINMUX_IPSR_GPSR(IP1SR4_19_16, TSN0_TXC),
+ PINMUX_IPSR_GPSR(IP1SR4_23_20, TSN0_RD1),
+ PINMUX_IPSR_GPSR(IP1SR4_27_24, TSN0_TD1),
+ PINMUX_IPSR_GPSR(IP1SR4_31_28, TSN0_TD0),
+
+ /* IP2SR4 */
+ PINMUX_IPSR_GPSR(IP2SR4_3_0, TSN0_RD3),
+ PINMUX_IPSR_GPSR(IP2SR4_7_4, TSN0_RD2),
+ PINMUX_IPSR_GPSR(IP2SR4_11_8, TSN0_TD3),
+ PINMUX_IPSR_GPSR(IP2SR4_15_12, TSN0_TD2),
+ PINMUX_IPSR_GPSR(IP2SR4_19_16, TSN0_TXCREFCLK),
+ PINMUX_IPSR_GPSR(IP2SR4_23_20, PCIE0_CLKREQ_N),
+ PINMUX_IPSR_GPSR(IP2SR4_27_24, PCIE1_CLKREQ_N),
+ PINMUX_IPSR_GPSR(IP2SR4_31_28, AVS0),
+
+ /* IP3SR4 */
+ PINMUX_IPSR_GPSR(IP3SR4_3_0, AVS1),
+
+ /* IP0SR5 */
+ PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB2_AVTP_PPS),
+ PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB2_AVTP_CAPTURE),
+ PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB2_AVTP_MATCH),
+ PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB2_LINK),
+ PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB2_PHY_INT),
+ PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB2_MAGIC),
+ PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB2_MDC),
+ PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB2_TXCREFCLK),
+
+ /* IP1SR5 */
+ PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB2_TD3),
+ PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB2_RD3),
+ PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB2_MDIO),
+ PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB2_TD2),
+ PINMUX_IPSR_GPSR(IP1SR5_19_16, AVB2_TD1),
+ PINMUX_IPSR_GPSR(IP1SR5_23_20, AVB2_RD2),
+ PINMUX_IPSR_GPSR(IP1SR5_27_24, AVB2_RD1),
+ PINMUX_IPSR_GPSR(IP1SR5_31_28, AVB2_TD0),
+
+ /* IP2SR5 */
+ PINMUX_IPSR_GPSR(IP2SR5_3_0, AVB2_TXC),
+ PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB2_RD0),
+ PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB2_RXC),
+ PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB2_TX_CTL),
+ PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB2_RX_CTL),
+
/* IP0SR6 */
PINMUX_IPSR_GPSR(IP0SR6_3_0, AVB1_MDIO),
- PINMUX_IPSR_MSEL(IP0SR6_7_4, AVB1_MAGIC, SEL_AVB1_MAGIC_1),
+ PINMUX_IPSR_GPSR(IP0SR6_7_4, AVB1_MAGIC),
- PINMUX_IPSR_MSEL(IP0SR6_11_8, AVB1_MDC, SEL_AVB1_MDC_1),
+ PINMUX_IPSR_GPSR(IP0SR6_11_8, AVB1_MDC),
PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT),
PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK),
PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER),
- PINMUX_IPSR_MSEL(IP0SR6_23_20, AVB1_AVTP_MATCH, SEL_AVB1_AVTP_MATCH_1),
- PINMUX_IPSR_MSEL(IP0SR6_23_20, AVB1_MII_RX_ER, SEL_AVB1_AVTP_MATCH_0),
+ PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH),
+ PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER),
- PINMUX_IPSR_MSEL(IP0SR6_27_24, AVB1_TXC, SEL_AVB1_TXC_1),
- PINMUX_IPSR_MSEL(IP0SR6_27_24, AVB1_MII_TXC, SEL_AVB1_TXC_0),
+ PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC),
+ PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC),
- PINMUX_IPSR_MSEL(IP0SR6_31_28, AVB1_TX_CTL, SEL_AVB1_TX_CTL_1),
- PINMUX_IPSR_MSEL(IP0SR6_31_28, AVB1_MII_TX_EN, SEL_AVB1_TX_CTL_0),
+ PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL),
+ PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN),
/* IP1SR6 */
PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC),
@@ -1060,17 +1097,17 @@
PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL),
PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV),
- PINMUX_IPSR_MSEL(IP1SR6_11_8, AVB1_AVTP_PPS, SEL_AVB1_AVTP_PPS_1),
- PINMUX_IPSR_MSEL(IP1SR6_11_8, AVB1_MII_COL, SEL_AVB1_AVTP_PPS_0),
+ PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS),
+ PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL),
PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE),
PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS),
- PINMUX_IPSR_MSEL(IP1SR6_19_16, AVB1_TD1, SEL_AVB1_TD1_1),
- PINMUX_IPSR_MSEL(IP1SR6_19_16, AVB1_MII_TD1, SEL_AVB1_TD1_0),
+ PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1),
+ PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1),
- PINMUX_IPSR_MSEL(IP1SR6_23_20, AVB1_TD0, SEL_AVB1_TD0_1),
- PINMUX_IPSR_MSEL(IP1SR6_23_20, AVB1_MII_TD0, SEL_AVB1_TD0_0),
+ PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0),
+ PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0),
PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1),
PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1),
@@ -1079,14 +1116,14 @@
PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0),
/* IP2SR6 */
- PINMUX_IPSR_MSEL(IP2SR6_3_0, AVB1_TD2, SEL_AVB1_TD2_1),
- PINMUX_IPSR_MSEL(IP2SR6_3_0, AVB1_MII_TD2, SEL_AVB1_TD2_0),
+ PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2),
+ PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2),
PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2),
PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2),
- PINMUX_IPSR_MSEL(IP2SR6_11_8, AVB1_TD3, SEL_AVB1_TD3_1),
- PINMUX_IPSR_MSEL(IP2SR6_11_8, AVB1_MII_TD3, SEL_AVB1_TD3_0),
+ PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3),
+ PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3),
PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3),
PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3),
@@ -1094,29 +1131,29 @@
PINMUX_IPSR_GPSR(IP2SR6_19_16, AVB1_TXCREFCLK),
/* IP0SR7 */
- PINMUX_IPSR_MSEL(IP0SR7_3_0, AVB0_AVTP_PPS, SEL_AVB0_AVTP_PPS_1),
- PINMUX_IPSR_MSEL(IP0SR7_3_0, AVB0_MII_COL, SEL_AVB0_AVTP_PPS_0),
+ PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_AVTP_PPS),
+ PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_MII_COL),
PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_AVTP_CAPTURE),
PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_MII_CRS),
- PINMUX_IPSR_MSEL(IP0SR7_11_8, AVB0_AVTP_MATCH, SEL_AVB0_AVTP_MATCH_1),
- PINMUX_IPSR_MSEL(IP0SR7_11_8, AVB0_MII_RX_ER, SEL_AVB0_AVTP_MATCH_0),
- PINMUX_IPSR_MSEL(IP0SR7_11_8, CC5_OSCOUT, SEL_AVB0_AVTP_MATCH_0),
+ PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_AVTP_MATCH),
+ PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_MII_RX_ER),
+ PINMUX_IPSR_GPSR(IP0SR7_11_8, CC5_OSCOUT),
- PINMUX_IPSR_MSEL(IP0SR7_15_12, AVB0_TD3, SEL_AVB0_TD3_1),
- PINMUX_IPSR_MSEL(IP0SR7_15_12, AVB0_MII_TD3, SEL_AVB0_TD3_0),
+ PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_TD3),
+ PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_MII_TD3),
PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_LINK),
PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_MII_TX_ER),
PINMUX_IPSR_GPSR(IP0SR7_23_20, AVB0_PHY_INT),
- PINMUX_IPSR_MSEL(IP0SR7_27_24, AVB0_TD2, SEL_AVB0_TD2_1),
- PINMUX_IPSR_MSEL(IP0SR7_27_24, AVB0_MII_TD2, SEL_AVB0_TD2_0),
+ PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_TD2),
+ PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_MII_TD2),
- PINMUX_IPSR_MSEL(IP0SR7_31_28, AVB0_TD1, SEL_AVB0_TD1_1),
- PINMUX_IPSR_MSEL(IP0SR7_31_28, AVB0_MII_TD1, SEL_AVB0_TD1_0),
+ PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_TD1),
+ PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_MII_TD1),
/* IP1SR7 */
PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_RD3),
@@ -1124,24 +1161,24 @@
PINMUX_IPSR_GPSR(IP1SR7_7_4, AVB0_TXCREFCLK),
- PINMUX_IPSR_MSEL(IP1SR7_11_8, AVB0_MAGIC, SEL_AVB0_MAGIC_1),
+ PINMUX_IPSR_GPSR(IP1SR7_11_8, AVB0_MAGIC),
- PINMUX_IPSR_MSEL(IP1SR7_15_12, AVB0_TD0, SEL_AVB0_TD0_1),
- PINMUX_IPSR_MSEL(IP1SR7_15_12, AVB0_MII_TD0, SEL_AVB0_TD0_0),
+ PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_TD0),
+ PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_MII_TD0),
PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_RD2),
PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_MII_RD2),
- PINMUX_IPSR_MSEL(IP1SR7_23_20, AVB0_MDC, SEL_AVB0_MDC_1),
+ PINMUX_IPSR_GPSR(IP1SR7_23_20, AVB0_MDC),
PINMUX_IPSR_GPSR(IP1SR7_27_24, AVB0_MDIO),
- PINMUX_IPSR_MSEL(IP1SR7_31_28, AVB0_TXC, SEL_AVB0_TXC_1),
- PINMUX_IPSR_MSEL(IP1SR7_31_28, AVB0_MII_TXC, SEL_AVB0_TXC_0),
+ PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_TXC),
+ PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_MII_TXC),
/* IP2SR7 */
- PINMUX_IPSR_MSEL(IP2SR7_3_0, AVB0_TX_CTL, SEL_AVB0_TX_CTL_1),
- PINMUX_IPSR_MSEL(IP2SR7_3_0, AVB0_MII_TX_EN, SEL_AVB0_TX_CTL_0),
+ PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_TX_CTL),
+ PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_MII_TX_EN),
PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_RD1),
PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_MII_RD1),
@@ -1193,10 +1230,28 @@
*/
enum {
GP_ASSIGN_LAST(),
+ NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
+ PINMUX_NOGP_ALL(),
+};
+
+/* - AUDIO CLOCK ----------------------------------------- */
+static const unsigned int audio_clkin_pins[] = {
+ /* CLK IN */
+ RCAR_GP_PIN(1, 22),
+};
+static const unsigned int audio_clkin_mux[] = {
+ AUDIO_CLKIN_MARK,
+};
+static const unsigned int audio_clkout_pins[] = {
+ /* CLK OUT */
+ RCAR_GP_PIN(1, 21),
+};
+static const unsigned int audio_clkout_mux[] = {
+ AUDIO_CLKOUT_MARK,
};
/* - AVB0 ------------------------------------------------ */
@@ -2332,6 +2387,22 @@
SCIF_CLK_MARK,
};
+/* - SSI ------------------------------------------------- */
+static const unsigned int ssi_data_pins[] = {
+ /* SSI_SD */
+ RCAR_GP_PIN(1, 20),
+};
+static const unsigned int ssi_data_mux[] = {
+ SSI_SD_MARK,
+};
+static const unsigned int ssi_ctrl_pins[] = {
+ /* SSI_SCK, SSI_WS */
+ RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
+};
+static const unsigned int ssi_ctrl_mux[] = {
+ SSI_SCK_MARK, SSI_WS_MARK,
+};
+
/* - TPU ------------------------------------------------------------------- */
static const unsigned int tpu_to0_pins[] = {
/* TPU0TO0 */
@@ -2464,6 +2535,9 @@
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(audio_clkin),
+ SH_PFC_PIN_GROUP(audio_clkout),
+
SH_PFC_PIN_GROUP(avb0_link),
SH_PFC_PIN_GROUP(avb0_magic),
SH_PFC_PIN_GROUP(avb0_phy_int),
@@ -2624,6 +2698,9 @@
SH_PFC_PIN_GROUP(scif4_ctrl),
SH_PFC_PIN_GROUP(scif_clk),
+ SH_PFC_PIN_GROUP(ssi_data),
+ SH_PFC_PIN_GROUP(ssi_ctrl),
+
SH_PFC_PIN_GROUP(tpu_to0), /* suffix might be updated */
SH_PFC_PIN_GROUP(tpu_to0_a), /* suffix might be updated */
SH_PFC_PIN_GROUP(tpu_to1), /* suffix might be updated */
@@ -2643,6 +2720,11 @@
SH_PFC_PIN_GROUP(tsn0_avtp_match),
};
+static const char * const audio_clk_groups[] = {
+ "audio_clkin",
+ "audio_clkout",
+};
+
static const char * const avb0_groups[] = {
"avb0_link",
"avb0_magic",
@@ -2936,6 +3018,11 @@
"scif_clk",
};
+static const char * const ssi_groups[] = {
+ "ssi_data",
+ "ssi_ctrl",
+};
+
static const char * const tpu_groups[] = {
/* suffix might be updated */
"tpu_to0",
@@ -2960,6 +3047,8 @@
};
static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(audio_clk),
+
SH_PFC_FUNCTION(avb0),
SH_PFC_FUNCTION(avb1),
SH_PFC_FUNCTION(avb2),
@@ -3017,6 +3106,8 @@
SH_PFC_FUNCTION(scif4),
SH_PFC_FUNCTION(scif_clk),
+ SH_PFC_FUNCTION(ssi),
+
SH_PFC_FUNCTION(tpu),
SH_PFC_FUNCTION(tsn0),
@@ -3422,6 +3513,82 @@
IP3SR3_7_4
IP3SR3_3_0))
},
+ { PINMUX_CFG_REG_VAR("IP0SR4", 0xE6060060, 32,
+ GROUP(4, 4, 4, 4, 4, 4, 4, 4),
+ GROUP(
+ IP0SR4_31_28
+ IP0SR4_27_24
+ IP0SR4_23_20
+ IP0SR4_19_16
+ IP0SR4_15_12
+ IP0SR4_11_8
+ IP0SR4_7_4
+ IP0SR4_3_0))
+ },
+ { PINMUX_CFG_REG_VAR("IP1SR4", 0xE6060064, 32,
+ GROUP(4, 4, 4, 4, 4, 4, 4, 4),
+ GROUP(
+ IP1SR4_31_28
+ IP1SR4_27_24
+ IP1SR4_23_20
+ IP1SR4_19_16
+ IP1SR4_15_12
+ IP1SR4_11_8
+ IP1SR4_7_4
+ IP1SR4_3_0))
+ },
+ { PINMUX_CFG_REG_VAR("IP2SR4", 0xE6060068, 32,
+ GROUP(4, 4, 4, 4, 4, 4, 4, 4),
+ GROUP(
+ IP2SR4_31_28
+ IP2SR4_27_24
+ IP2SR4_23_20
+ IP2SR4_19_16
+ IP2SR4_15_12
+ IP2SR4_11_8
+ IP2SR4_7_4
+ IP2SR4_3_0))
+ },
+ { PINMUX_CFG_REG_VAR("IP3SR4", 0xE606006C, 32,
+ GROUP(-28, 4),
+ GROUP(
+ /* IP3SR4_31_4 RESERVED */
+ IP3SR4_3_0))
+ },
+ { PINMUX_CFG_REG_VAR("IP0SR5", 0xE6060860, 32,
+ GROUP(4, 4, 4, 4, 4, 4, 4, 4),
+ GROUP(
+ IP0SR5_31_28
+ IP0SR5_27_24
+ IP0SR5_23_20
+ IP0SR5_19_16
+ IP0SR5_15_12
+ IP0SR5_11_8
+ IP0SR5_7_4
+ IP0SR5_3_0))
+ },
+ { PINMUX_CFG_REG_VAR("IP1SR5", 0xE6060864, 32,
+ GROUP(4, 4, 4, 4, 4, 4, 4, 4),
+ GROUP(
+ IP1SR5_31_28
+ IP1SR5_27_24
+ IP1SR5_23_20
+ IP1SR5_19_16
+ IP1SR5_15_12
+ IP1SR5_11_8
+ IP1SR5_7_4
+ IP1SR5_3_0))
+ },
+ { PINMUX_CFG_REG_VAR("IP2SR5", 0xE6060868, 32,
+ GROUP(-12, 4, 4, 4, 4, 4),
+ GROUP(
+ /* IP2SR5_31_20 RESERVED */
+ IP2SR5_19_16
+ IP2SR5_15_12
+ IP2SR5_11_8
+ IP2SR5_7_4
+ IP2SR5_3_0))
+ },
{ PINMUX_CFG_REG("IP0SR6", 0xE6061060, 32, 4, GROUP(
IP0SR6_31_28
IP0SR6_27_24
@@ -3508,95 +3675,6 @@
#define F_(x, y) x,
#define FM(x) FN_##x,
- { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE6060100, 32,
- GROUP(-12, 1, 1, -2, 1, 1, -1, 1, -2, 1, 1, -2, 1,
- -2, 1, 1, -1),
- GROUP(
- /* RESERVED 31-20 */
- MOD_SEL4_19
- MOD_SEL4_18
- /* RESERVED 17-16 */
- MOD_SEL4_15
- MOD_SEL4_14
- /* RESERVED 13 */
- MOD_SEL4_12
- /* RESERVED 11-10 */
- MOD_SEL4_9
- MOD_SEL4_8
- /* RESERVED 7-6 */
- MOD_SEL4_5
- /* RESERVED 4-3 */
- MOD_SEL4_2
- MOD_SEL4_1
- /* RESERVED 0 */
- ))
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL5", 0xE6060900, 32,
- GROUP(-12, 1, -2, 1, 1, -2, 1, 1, -2, 1, -1,
- 1, 1, -2, 1, -1, 1),
- GROUP(
- /* RESERVED 31-20 */
- MOD_SEL5_19
- /* RESERVED 18-17 */
- MOD_SEL5_16
- MOD_SEL5_15
- /* RESERVED 14-13 */
- MOD_SEL5_12
- MOD_SEL5_11
- /* RESERVED 10-9 */
- MOD_SEL5_8
- /* RESERVED 7 */
- MOD_SEL5_6
- MOD_SEL5_5
- /* RESERVED 4-3 */
- MOD_SEL5_2
- /* RESERVED 1 */
- MOD_SEL5_0))
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL6", 0xE6061100, 32,
- GROUP(-13, 1, -1, 1, -2, 1, 1,
- -1, 1, -2, 1, 1, 1, -2, 1, 1, -1),
- GROUP(
- /* RESERVED 31-19 */
- MOD_SEL6_18
- /* RESERVED 17 */
- MOD_SEL6_16
- /* RESERVED 15-14 */
- MOD_SEL6_13
- MOD_SEL6_12
- /* RESERVED 11 */
- MOD_SEL6_10
- /* RESERVED 9-8 */
- MOD_SEL6_7
- MOD_SEL6_6
- MOD_SEL6_5
- /* RESERVED 4-3 */
- MOD_SEL6_2
- MOD_SEL6_1
- /* RESERVED 0 */
- ))
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL7", 0xE6061900, 32,
- GROUP(-15, 1, 1, -1, 1, -1, 1, 1, -2, 1, 1,
- -2, 1, 1, -1, 1),
- GROUP(
- /* RESERVED 31-17 */
- MOD_SEL7_16
- MOD_SEL7_15
- /* RESERVED 14 */
- MOD_SEL7_13
- /* RESERVED 12 */
- MOD_SEL7_11
- MOD_SEL7_10
- /* RESERVED 9-8 */
- MOD_SEL7_7
- MOD_SEL7_6
- /* RESERVED 5-4 */
- MOD_SEL7_3
- MOD_SEL7_2
- /* RESERVED 1 */
- MOD_SEL7_0))
- },
{ PINMUX_CFG_REG_VAR("MOD_SEL8", 0xE6068100, 32,
GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
@@ -3614,7 +3692,7 @@
MOD_SEL8_1
MOD_SEL8_0))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
@@ -3876,7 +3954,7 @@
{ RCAR_GP_PIN(8, 9), 4, 3 }, /* SDA4 */
{ RCAR_GP_PIN(8, 8), 0, 3 }, /* SCL4 */
} },
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
@@ -3899,30 +3977,49 @@
[POC6] = { 0xE60610A0, },
[POC7] = { 0xE60618A0, },
[POC8] = { 0xE60680A0, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a779g0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = pin & 0x1f;
- *pocctrl = pinmux_ioctrl_regs[POC0].reg;
- if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 18))
+ switch (pin) {
+ case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 18):
+ *pocctrl = pinmux_ioctrl_regs[POC0].reg;
return bit;
- *pocctrl = pinmux_ioctrl_regs[POC1].reg;
- if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 22))
+ case RCAR_GP_PIN(1, 0) ... RCAR_GP_PIN(1, 22):
+ *pocctrl = pinmux_ioctrl_regs[POC1].reg;
return bit;
- *pocctrl = pinmux_ioctrl_regs[POC3].reg;
- if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 12))
+ case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 12):
+ *pocctrl = pinmux_ioctrl_regs[POC3].reg;
return bit;
- *pocctrl = pinmux_ioctrl_regs[POC8].reg;
- if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 13))
+ case PIN_VDDQ_TSN0:
+ *pocctrl = pinmux_ioctrl_regs[POC4].reg;
+ return 0;
+
+ case PIN_VDDQ_AVB2:
+ *pocctrl = pinmux_ioctrl_regs[POC5].reg;
+ return 0;
+
+ case PIN_VDDQ_AVB1:
+ *pocctrl = pinmux_ioctrl_regs[POC6].reg;
+ return 0;
+
+ case PIN_VDDQ_AVB0:
+ *pocctrl = pinmux_ioctrl_regs[POC7].reg;
+ return 0;
+
+ case RCAR_GP_PIN(8, 0) ... RCAR_GP_PIN(8, 13):
+ *pocctrl = pinmux_ioctrl_regs[POC8].reg;
return bit;
- return -EINVAL;
+ default:
+ return -EINVAL;
+ }
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
@@ -4232,7 +4329,7 @@
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a779g0_pin_ops = {
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index f6e8dd9..3ac25cb 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -798,7 +798,7 @@
return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
case PIN_CONFIG_POWER_SOURCE:
- return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
+ return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK;
default:
return false;
@@ -814,6 +814,7 @@
int bit, ret;
int idx = sh_pfc_get_pin_index(pfc, _pin);
const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
+ unsigned int mode, hi, lo;
if (!sh_pfc_pinconf_validate(pfc, _pin, param))
return -ENOTSUPP;
@@ -851,8 +852,12 @@
pocctrl = (void __iomem *)(uintptr_t)addr;
+ mode = pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK;
+ lo = mode <= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 1800 : 2500;
+ hi = mode >= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 3300 : 2500;
+
val = sh_pfc_read_raw_reg(pocctrl, 32);
- if (arg == ((pin->configs & SH_PFC_PIN_VOLTAGE_18_25) ? 2500 : 3300))
+ if (arg == hi)
val |= BIT(bit);
else
val &= ~BIT(bit);
diff --git a/drivers/pinctrl/renesas/pfc-r7s72100.c b/drivers/pinctrl/renesas/pinctrl-rza1.c
similarity index 100%
rename from drivers/pinctrl/renesas/pfc-r7s72100.c
rename to drivers/pinctrl/renesas/pinctrl-rza1.c
diff --git a/drivers/pinctrl/renesas/rzg2l-pfc.c b/drivers/pinctrl/renesas/rzg2l-pfc.c
new file mode 100644
index 0000000..e88ec1c
--- /dev/null
+++ b/drivers/pinctrl/renesas/rzg2l-pfc.c
@@ -0,0 +1,624 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/G2L Pin Function Controller
+ *
+ * Copyright (C) 2021-2023 Renesas Electronics Corp.
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/device.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#include <renesas/rzg2l-pfc.h>
+#include <reset.h>
+
+struct rzg2l_pfc_driver_data {
+ uint num_dedicated_pins;
+ uint num_ports;
+ const u32 *gpio_configs;
+};
+
+struct rzg2l_dedicated_configs {
+ const char *name;
+ u32 config;
+};
+
+/*
+ * We need to ensure that the module clock is enabled and all resets are
+ * de-asserted before using either the gpio or pinctrl functionality. Error
+ * handling can be quite simple here as if the PFC cannot be enabled then we
+ * will not be able to progress with the boot anyway.
+ */
+int rzg2l_pfc_enable(struct udevice *dev)
+{
+ struct reset_ctl_bulk rsts;
+ struct clk clk;
+ int ret;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0) {
+ dev_err(dev, "failed to get gpio module clock\n");
+ return ret;
+ }
+
+ ret = clk_enable(&clk);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable gpio module clock\n");
+ return ret;
+ }
+
+ ret = reset_get_bulk(dev, &rsts);
+ if (ret < 0) {
+ dev_err(dev, "failed to get reset lines\n");
+ return ret;
+ }
+
+ ret = reset_deassert_bulk(&rsts);
+ if (ret < 0) {
+ dev_err(dev, "failed to de-assert reset lines\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+bool rzg2l_port_validate(const struct rzg2l_pfc_data *data, u32 port, u8 pin)
+{
+ return (port < data->num_ports) &&
+ (pin < RZG2L_GPIO_PORT_GET_PINCNT(data->gpio_configs[port]));
+}
+
+/* Decode a pin selector, returning the port index and setting *pin to the pin
+ * index. Returns -1 on error, which can be checked directly or by calling
+ * rzg2l_port_validate().
+ */
+static int rzg2l_selector_decode(const struct rzg2l_pfc_data *data,
+ unsigned int selector,
+ u8 *pin)
+{
+ int port;
+
+ selector -= data->num_dedicated_pins;
+ for (port = 0; port < data->num_ports; port++) {
+ u8 num_pins = RZG2L_GPIO_PORT_GET_PINCNT(data->gpio_configs[port]);
+ if (selector < num_pins) {
+ *pin = (u8)selector;
+ return port;
+ }
+ selector -= num_pins;
+ }
+ return -EINVAL;
+}
+
+static unsigned int rzg2l_selector_encode(const struct rzg2l_pfc_data *data,
+ u32 port, u8 pin)
+{
+ unsigned int selector = data->num_dedicated_pins + pin;
+ u32 i;
+
+ for (i = 0; i < port; i++)
+ selector += RZG2L_GPIO_PORT_GET_PINCNT(data->gpio_configs[i]);
+
+ return selector;
+}
+
+static const char * const rzg2l_gpio_names[] = {
+ "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
+ "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
+ "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
+ "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
+ "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
+ "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
+ "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
+ "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
+ "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
+ "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
+ "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7",
+ "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7",
+ "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7",
+ "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7",
+ "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7",
+ "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7",
+ "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7",
+ "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7",
+ "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7",
+ "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7",
+ "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7",
+ "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7",
+ "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7",
+ "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7",
+ "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7",
+ "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7",
+ "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7",
+ "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7",
+ "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7",
+ "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7",
+ "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7",
+ "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7",
+ "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7",
+ "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7",
+ "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7",
+ "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7",
+ "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7",
+ "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7",
+ "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7",
+ "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7",
+ "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7",
+ "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7",
+ "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7",
+ "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7",
+ "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7",
+ "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7",
+ "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7",
+ "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7",
+ "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7",
+};
+
+static const u32 r9a07g044_gpio_configs[] = {
+ RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS),
+};
+
+static const struct {
+ struct rzg2l_dedicated_configs common[35];
+ struct rzg2l_dedicated_configs rzg2l_pins[7];
+} rzg2l_dedicated_pins = {
+ .common = {
+ { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,
+ (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },
+ { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
+ (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
+ { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0,
+ (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
+ { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) },
+ { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) },
+ { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
+ { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) },
+ { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
+ { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
+ { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
+ { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
+ { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
+ { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
+ { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
+ { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
+ { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
+ { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
+ { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
+ { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
+ { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
+ { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) },
+ { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) },
+ { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) },
+ { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) },
+ { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) },
+ },
+ .rzg2l_pins = {
+ { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
+ { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
+ { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
+ { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
+ { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
+ { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
+ { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5,
+ (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
+ }
+};
+
+static void rzg2l_rmw_pin_config(const struct rzg2l_pfc_data *data, u32 offset,
+ u8 pin, u32 mask, u32 val)
+{
+ void __iomem *addr = data->base + offset;
+
+ /* handle _L/_H for 32-bit register read/write */
+ if (pin >= 4) {
+ pin -= 4;
+ addr += 4;
+ }
+
+ clrsetbits_le32(addr, mask << (pin * 8), val << (pin * 8));
+}
+
+static int rzg2l_get_pins_count(struct udevice *dev)
+{
+ const struct rzg2l_pfc_data *data =
+ (const struct rzg2l_pfc_data *)dev_get_driver_data(dev);
+
+ return data->num_dedicated_pins + data->num_pins;
+}
+
+static const char *rzg2l_get_pin_name(struct udevice *dev, unsigned int selector)
+{
+ const struct rzg2l_pfc_data *data =
+ (const struct rzg2l_pfc_data *)dev_get_driver_data(dev);
+ int port;
+ u8 pin;
+
+ if (selector < data->num_dedicated_pins) {
+ if (selector >= ARRAY_SIZE(rzg2l_dedicated_pins.common)) {
+ unsigned int u = selector - ARRAY_SIZE(rzg2l_dedicated_pins.common);
+ return rzg2l_dedicated_pins.rzg2l_pins[u].name;
+ } else {
+ return rzg2l_dedicated_pins.common[selector].name;
+ }
+ }
+
+ port = rzg2l_selector_decode(data, selector, &pin);
+ if (port < 0)
+ return "(invalid pin)";
+ return rzg2l_gpio_names[pin + 8 * port];
+}
+
+static int rzg2l_pinconf_set(struct udevice *dev, unsigned int pin_selector,
+ unsigned int param, unsigned int argument)
+{
+ const struct rzg2l_pfc_data *data =
+ (const struct rzg2l_pfc_data *)dev_get_driver_data(dev);
+ u32 cfg, port_offset;
+ u8 pin;
+
+ if (pin_selector >= data->num_dedicated_pins) {
+ /* The pin selector refers to a multiplexed pin */
+ int port = rzg2l_selector_decode(data, pin_selector, &pin);
+ if (port < 0) {
+ dev_err(dev, "Invalid pin selector %u:%u\n", port, pin);
+ return port;
+ }
+
+ cfg = data->gpio_configs[port];
+ port_offset = P(port);
+ } else {
+ /* The pin selector refers to a dedicated function pin */
+ const struct rzg2l_dedicated_configs *dedicated_config;
+
+ if (pin_selector >= data->num_dedicated_pins) {
+ dev_err(dev, "Invalid dedicated pin %u\n", pin_selector);
+ return -EINVAL;
+ }
+
+ if (pin_selector >= ARRAY_SIZE(rzg2l_dedicated_pins.common)) {
+ pin_selector -= ARRAY_SIZE(rzg2l_dedicated_pins.common);
+ dedicated_config = &rzg2l_dedicated_pins.rzg2l_pins[pin_selector];
+ } else {
+ dedicated_config = &rzg2l_dedicated_pins.common[pin_selector];
+ }
+
+ port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(dedicated_config->config);
+ pin = RZG2L_SINGLE_PIN_GET_BIT(dedicated_config->config);
+ cfg = RZG2L_SINGLE_PIN_GET_CFGS(dedicated_config->config);
+ }
+
+ switch (param) {
+ case PIN_CONFIG_INPUT_ENABLE: {
+ if (!(cfg & PIN_CFG_IEN)) {
+ dev_err(dev, "pin does not support IEN\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "port off %u:%u set IEN=%u\n",
+ port_offset, pin, argument);
+ rzg2l_rmw_pin_config(data, IEN(port_offset), pin, IEN_MASK, !!argument);
+ break;
+ }
+
+ case PIN_CONFIG_POWER_SOURCE: {
+ u32 pwr_reg = 0x0;
+
+ /* argument is in mV */
+ if (argument != 1800 && argument != 3300) {
+ dev_err(dev, "Invalid mV %u\n", argument);
+ return -EINVAL;
+ }
+
+ /*
+ * TODO: PIN_CFG_IO_VMC_ETH0 & PIN_CFG_IO_VMC_ETH1 will be
+ * handled when the RZ/G2L Ethernet driver is added.
+ */
+ if (cfg & PIN_CFG_IO_VMC_SD0) {
+ dev_dbg(dev, "port off %u:%u set SD_CH 0 PVDD=%u\n",
+ port_offset, pin, argument);
+ pwr_reg = SD_CH(0);
+ } else if (cfg & PIN_CFG_IO_VMC_SD1) {
+ dev_dbg(dev, "port off %u:%u set SD_CH 1 PVDD=%u\n",
+ port_offset, pin, argument);
+ pwr_reg = SD_CH(1);
+ } else if (cfg & PIN_CFG_IO_VMC_QSPI) {
+ dev_dbg(dev, "port off %u:%u set QSPI PVDD=%u\n",
+ port_offset, pin, argument);
+ pwr_reg = QSPI;
+ } else {
+ dev_dbg(dev, "pin power source is not selectable\n");
+ return -EINVAL;
+ }
+
+ writel((argument == 1800) ? PVDD_1800 : PVDD_3300,
+ data->base + pwr_reg);
+ break;
+ }
+
+ default:
+ dev_err(dev, "Invalid pinconf parameter\n");
+ return -EOPNOTSUPP;
+ }
+
+ return 0;
+}
+
+static int rzg2l_pinmux_property_set(struct udevice *dev, u32 pinmux_group)
+{
+ const struct rzg2l_pfc_data *data =
+ (const struct rzg2l_pfc_data *)dev_get_driver_data(dev);
+ u32 port, pin, func, pfc_state;
+ u8 pmc_state;
+
+ func = RZG2L_PINMUX_TO_FUNC(pinmux_group);
+ if (func > 5) {
+ dev_err(dev, "Invalid pin function %u\n", func);
+ return -EINVAL;
+ }
+
+ port = RZG2L_PINMUX_TO_PORT(pinmux_group);
+ pin = RZG2L_PINMUX_TO_PIN(pinmux_group);
+ if (!rzg2l_port_validate(data, port, pin)) {
+ dev_err(dev, "Invalid pin selector %u:%u\n", port, pin);
+ return -EINVAL;
+ }
+
+ /* Check current PMC & PFC to decide if we need to change anything. */
+ pmc_state = readb(data->base + PMC(port)) & BIT(pin);
+ pfc_state = (readl(data->base + PFC(port)) >> (pin * 4)) & PFC_MASK;
+ if (pmc_state && pfc_state == func)
+ return 0;
+
+ dev_dbg(dev, "pinmux port %u pin %u func %u\n", port, pin, func);
+
+ /* Set pin to 'Non-use (Hi-Z input protection)' */
+ clrbits_le16(data->base + PM(port), PM_MASK << (pin * 2));
+
+ /* Temporarily switch to GPIO mode with PMC register */
+ clrbits_8(data->base + PMC(port), BIT(pin));
+
+ /* Set the PWPR register to allow PFC register to write */
+ writel(0x0, data->base + PWPR); /* B0WI=0, PFCWE=0 */
+ writel(PWPR_PFCWE, data->base + PWPR); /* B0WI=0, PFCWE=1 */
+
+ /* Select Pin function mode with PFC register */
+ clrsetbits_le32(data->base + PFC(port), PFC_MASK << (pin * 4),
+ func << (pin * 4));
+
+ /* Set the PWPR register to be write-protected */
+ writel(0x0, data->base + PWPR); /* B0WI=0, PFCWE=0 */
+ writel(PWPR_B0WI, data->base + PWPR); /* B0WI=1, PFCWE=0 */
+
+ /* Switch to Peripheral pin function with PMC register */
+ setbits_8(data->base + PMC(port), BIT(pin));
+
+ return rzg2l_selector_encode(data, port, pin);
+}
+
+static int rzg2l_get_pin_muxing(struct udevice *dev, unsigned int selector,
+ char *buf, int size)
+{
+ const struct rzg2l_pfc_data *data =
+ (const struct rzg2l_pfc_data *)dev_get_driver_data(dev);
+ u32 pmc_state;
+ int port;
+ u8 pin;
+
+ if (selector < data->num_dedicated_pins) {
+ snprintf(buf, size, rzg2l_get_pin_name(dev, selector));
+ return 0;
+ }
+
+ port = rzg2l_selector_decode(data, selector, &pin);
+ if (port < 0) {
+ dev_err(dev, "Invalid pin selector %u:%u\n", port, pin);
+ return port;
+ }
+
+ pmc_state = readb(data->base + PMC(port)) & BIT(pin);
+ if (pmc_state) {
+ u32 pfc_state = (readl(data->base + PFC(port)) >> (pin * 4)) & PFC_MASK;
+ snprintf(buf, size, "Function %d", pfc_state);
+ return 0;
+ }
+
+ snprintf(buf, size, "GPIO");
+ return 0;
+}
+
+static const struct pinconf_param rzg2l_pinconf_params[] = {
+ { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
+ { "power-source", PIN_CONFIG_POWER_SOURCE, 3300 /* mV */ },
+};
+
+static const struct pinctrl_ops rzg2l_pinctrl_ops = {
+ .get_pins_count = rzg2l_get_pins_count,
+ .get_pin_name = rzg2l_get_pin_name,
+
+ .pinconf_num_params = ARRAY_SIZE(rzg2l_pinconf_params),
+ .pinconf_params = rzg2l_pinconf_params,
+ .pinconf_set = rzg2l_pinconf_set,
+
+ .pinmux_property_set = rzg2l_pinmux_property_set,
+ .set_state = pinctrl_generic_set_state,
+ .get_pin_muxing = rzg2l_get_pin_muxing,
+};
+
+static int rzg2l_pinctrl_probe(struct udevice *dev)
+{
+ return rzg2l_pfc_enable(dev);
+}
+
+U_BOOT_DRIVER(rzg2l_pfc_pinctrl) = {
+ .name = "rzg2l-pfc-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .ops = &rzg2l_pinctrl_ops,
+ .probe = rzg2l_pinctrl_probe,
+};
+
+static const struct rzg2l_pfc_driver_data r9a07g044_driver_data = {
+ .num_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
+ ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
+ .num_ports = ARRAY_SIZE(r9a07g044_gpio_configs),
+ .gpio_configs = r9a07g044_gpio_configs,
+};
+
+static const struct udevice_id rzg2l_pfc_ids[] = {
+ { .compatible = "renesas,r9a07g044-pinctrl", .data = (ulong)&r9a07g044_driver_data },
+ { /* sentinel */ }
+};
+
+static int rzg2l_pfc_bind(struct udevice *parent)
+{
+ struct rzg2l_pfc_driver_data *driver_data;
+ struct rzg2l_pfc_data *data;
+ struct udevice *pinctrl_dev;
+ struct driver *drv;
+ unsigned int i;
+ int ret;
+
+ driver_data =
+ (struct rzg2l_pfc_driver_data *)dev_get_driver_data(parent);
+ if (!driver_data)
+ return -EINVAL;
+ data = devm_kmalloc(parent, sizeof(*data), 0);
+ if (!data)
+ return -ENOMEM;
+
+ data->base = dev_read_addr_ptr(parent);
+ if (!data->base)
+ return -EINVAL;
+ data->num_dedicated_pins = driver_data->num_dedicated_pins;
+ data->num_ports = driver_data->num_ports;
+ data->gpio_configs = driver_data->gpio_configs;
+
+ data->num_pins = 0;
+ for (i = 0; i < data->num_ports; i++)
+ data->num_pins += RZG2L_GPIO_PORT_GET_PINCNT(data->gpio_configs[i]);
+ dev_dbg(parent, "%u dedicated pins, %u muxed ports, %u muxed pins\n",
+ data->num_dedicated_pins, data->num_ports, data->num_pins);
+
+ drv = lists_driver_lookup_name("rzg2l-pfc-pinctrl");
+ if (!drv)
+ return -ENOENT;
+
+ ret = device_bind_with_driver_data(parent, drv, parent->name,
+ (ulong)data, dev_ofnode(parent),
+ &pinctrl_dev);
+
+ if (!ret && IS_ENABLED(CONFIG_RZG2L_GPIO)) {
+ drv = lists_driver_lookup_name("rzg2l-pfc-gpio");
+ if (!drv) {
+ device_unbind(pinctrl_dev);
+ return -ENOENT;
+ }
+
+ ret = device_bind_with_driver_data(parent, drv, parent->name,
+ (ulong)data,
+ dev_ofnode(parent), NULL);
+ if (ret)
+ device_unbind(pinctrl_dev);
+ }
+
+ return ret;
+}
+
+U_BOOT_DRIVER(rzg2l_pfc) = {
+ .name = "rzg2l-pfc",
+ .id = UCLASS_NOP,
+ .of_match = rzg2l_pfc_ids,
+ .bind = rzg2l_pfc_bind,
+};
diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index f35fd33..e6c2117 100644
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -26,19 +26,13 @@
#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
#define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \
SH_PFC_PIN_CFG_PULL_DOWN)
-#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
-#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
-#define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6)
-#define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6)
-#define SH_PFC_PIN_VOLTAGE_18_25 (2 << 6)
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_MASK GENMASK(5, 4)
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_25 (1 << 4)
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (2 << 4)
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (3 << 4)
-#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
- SH_PFC_PIN_VOLTAGE_18_33)
-#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
- SH_PFC_PIN_VOLTAGE_25_33)
-#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_25 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
- SH_PFC_PIN_VOLTAGE_18_25)
+#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 6)
#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
@@ -302,7 +296,6 @@
extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
-extern const struct sh_pfc_soc_info r8a77950_pinmux_info;
extern const struct sh_pfc_soc_info r8a77951_pinmux_info;
extern const struct sh_pfc_soc_info r8a77960_pinmux_info;
extern const struct sh_pfc_soc_info r8a77961_pinmux_info;
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 77da908..cbd6179 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -124,4 +124,9 @@
default MACH_SUN50I_H616
select PINCTRL_SUNXI
+config PINCTRL_SUN20I_D1
+ bool "Support for the Allwinner D1/R528 PIO"
+ default MACH_SUN8I_R528
+ select PINCTRL_SUNXI
+
endif
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index e510218..37ea937 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -7,6 +7,7 @@
#include <dm/pinctrl.h>
#include <errno.h>
#include <malloc.h>
+#include <sunxi_gpio.h>
#include <asm/gpio.h>
@@ -35,7 +36,7 @@
};
struct sunxi_pinctrl_plat {
- struct sunxi_gpio __iomem *base;
+ void __iomem *base;
};
static int sunxi_pinctrl_get_pins_count(struct udevice *dev)
@@ -49,7 +50,7 @@
uint pin_selector)
{
const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
- static char pin_name[sizeof("PN31")];
+ static char pin_name[sizeof("PN31")] __section(".data");
snprintf(pin_name, sizeof(pin_name), "P%c%d",
pin_selector / SUNXI_GPIOS_PER_BANK + desc->first_bank + 'A',
@@ -86,8 +87,8 @@
sunxi_pinctrl_get_function_name(dev, func_selector),
desc->functions[func_selector].mux);
- sunxi_gpio_set_cfgbank(plat->base + bank, pin,
- desc->functions[func_selector].mux);
+ sunxi_gpio_set_cfgbank(plat->base + bank * SUNXI_PINCTRL_BANK_SIZE,
+ pin, desc->functions[func_selector].mux);
return 0;
}
@@ -102,7 +103,7 @@
static int sunxi_pinctrl_pinconf_set_pull(struct sunxi_pinctrl_plat *plat,
uint bank, uint pin, uint bias)
{
- struct sunxi_gpio *regs = &plat->base[bank];
+ void *regs = plat->base + bank * SUNXI_PINCTRL_BANK_SIZE;
sunxi_gpio_set_pull_bank(regs, pin, bias);
@@ -112,7 +113,7 @@
static int sunxi_pinctrl_pinconf_set_drive(struct sunxi_pinctrl_plat *plat,
uint bank, uint pin, uint drive)
{
- struct sunxi_gpio *regs = &plat->base[bank];
+ void *regs = plat->base + bank * SUNXI_PINCTRL_BANK_SIZE;
if (drive < 10 || drive > 40)
return -EINVAL;
@@ -148,7 +149,7 @@
struct sunxi_pinctrl_plat *plat = dev_get_plat(dev);
int bank = pin_selector / SUNXI_GPIOS_PER_BANK;
int pin = pin_selector % SUNXI_GPIOS_PER_BANK;
- int mux = sunxi_gpio_get_cfgbank(plat->base + bank, pin);
+ int mux = sunxi_gpio_get_cfgbank(plat->base + bank * SUNXI_PINCTRL_BANK_SIZE, pin);
switch (mux) {
case SUNXI_GPIO_INPUT:
@@ -206,7 +207,7 @@
if (!gpio_plat)
return -ENOMEM;
- gpio_plat->regs = plat->base + i;
+ gpio_plat->regs = plat->base + i * SUNXI_PINCTRL_BANK_SIZE;
gpio_plat->bank_name[0] = 'P';
gpio_plat->bank_name[1] = 'A' + desc->first_bank + i;
gpio_plat->bank_name[2] = '\0';
@@ -597,6 +598,32 @@
.num_banks = 3,
};
+static const struct sunxi_pinctrl_function sun20i_d1_pinctrl_functions[] = {
+ { "emac", 8 }, /* PE0-PE15 */
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c0", 4 }, /* PB10-PB11 */
+ { "mmc0", 2 }, /* PF0-PF5 */
+ { "mmc1", 2 }, /* PG0-PG5 */
+ { "mmc2", 3 }, /* PC2-PC7 */
+ { "spi0", 2 }, /* PC2-PC7 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+ { "uart0", 3 }, /* PF2,PF4 */
+#else
+ { "uart0", 6 }, /* PB0-PB1, PB8-PB9, PE2-PE3 */
+#endif
+ { "uart1", 2 }, /* PG6-PG7 */
+ { "uart2", 7 }, /* PB0-PB1 */
+ { "uart3", 7 }, /* PB6-PB7 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun20i_d1_pinctrl_desc = {
+ .functions = sun20i_d1_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun20i_d1_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_A,
+ .num_banks = 7,
+};
+
static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
{ "emac", 4 }, /* PD8-PD23 */
{ "gpio_in", 0 },
@@ -862,6 +889,12 @@
.data = (ulong)&sun9i_a80_r_pinctrl_desc,
},
#endif
+#ifdef CONFIG_PINCTRL_SUN20I_D1
+ {
+ .compatible = "allwinner,sun20i-d1-pinctrl",
+ .data = (ulong)&sun20i_d1_pinctrl_desc,
+ },
+#endif
#ifdef CONFIG_PINCTRL_SUN50I_A64
{
.compatible = "allwinner,sun50i-a64-pinctrl",
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 7f3b990..33b8bc1 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -56,7 +56,6 @@
depends on ARCH_SUNXI
default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40
- default AXP305_POWER if MACH_SUN50I_H616
default AXP818_POWER if MACH_SUN8I_A83T
default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_V3S
@@ -101,6 +100,15 @@
Select this to enable support for the axp305 pmic found on most
H616 boards.
+config AXP313_POWER
+ bool "axp313 pmic support"
+ depends on MACH_SUN50I_H616
+ select AXP_PMIC_BUS
+ select CMD_POWEROFF
+ ---help---
+ Select this to enable support for the AXP313 PMIC found on some
+ H616 boards.
+
config AXP809_POWER
bool "axp809 pmic support"
depends on MACH_SUN9I
@@ -143,9 +151,10 @@
config AXP_DCDC2_VOLT
int "axp pmic dcdc2 voltage"
- depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
+ depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP313_POWER
default 900 if AXP818_POWER
default 1400 if AXP152_POWER || AXP209_POWER
+ default 1000 if AXP313_POWER
default 1200 if MACH_SUN6I
default 1100 if MACH_SUN8I
default 0 if MACH_SUN9I
@@ -158,13 +167,15 @@
On A80 boards dcdc2 powers the GPU and can be left off.
On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V.
On R40 boards dcdc2 is VDD-CPU and should be 1.1V
+ On boards using the AXP313 it's often VDD-CPU.
config AXP_DCDC3_VOLT
int "axp pmic dcdc3 voltage"
- depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
+ depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP313_POWER
default 900 if AXP809_POWER || AXP818_POWER
default 1500 if AXP152_POWER
default 1250 if AXP209_POWER
+ default 1100 if AXP313_POWER
default 1100 if MACH_SUN8I_R40
default 1200 if MACH_SUN6I || MACH_SUN8I
---help---
@@ -177,10 +188,11 @@
On A80 boards dcdc3 is used for VDD-CPUA(cluster 0) and should be 0.9V.
On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V.
On R40 boards dcdc3 is VDD-SYS and VDD-GPU and should be 1.1V.
+ On boards using the AXP313 it's often VDD-DRAM and should be 1.1V for LPDDR4.
config AXP_DCDC4_VOLT
int "axp pmic dcdc4 voltage"
- depends on AXP152_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP305_POWER
+ depends on AXP152_POWER || AXP221_POWER || AXP809_POWER || AXP305_POWER
default 1250 if AXP152_POWER
default 1200 if MACH_SUN6I
default 0 if MACH_SUN8I
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index ba64b2c..c7ee459 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -12,6 +12,7 @@
obj-$(CONFIG_AXP209_POWER) += axp209.o
obj-$(CONFIG_AXP221_POWER) += axp221.o
obj-$(CONFIG_AXP305_POWER) += axp305.o
+obj-$(CONFIG_AXP313_POWER) += axp313.o
obj-$(CONFIG_AXP809_POWER) += axp809.o
obj-$(CONFIG_AXP818_POWER) += axp818.o
obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o
diff --git a/drivers/power/axp313.c b/drivers/power/axp313.c
new file mode 100644
index 0000000..bbc9e91
--- /dev/null
+++ b/drivers/power/axp313.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * AXP313(a) driver
+ *
+ * (C) Copyright 2023 Arm Ltd.
+ *
+ * Based on axp305.c
+ * (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net>
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <asm/arch/pmic_bus.h>
+#include <axp_pmic.h>
+
+enum axp313_reg {
+ AXP313_CHIP_VERSION = 0x03,
+ AXP313_OUTPUT_CTRL = 0x10,
+ AXP313_DCDC1_CTRL = 0x13,
+ AXP313_SHUTDOWN = 0x1a,
+};
+
+#define AXP313_CHIP_VERSION_MASK 0xcf
+#define AXP313_CHIP_VERSION_AXP1530 0x48
+#define AXP313_CHIP_VERSION_AXP313A 0x4b
+#define AXP313_CHIP_VERSION_AXP313B 0x4c
+
+#define AXP313_DCDC_SPLIT_OFFSET 71
+#define AXP313_DCDC_SPLIT_MVOLT 1200
+
+#define AXP313_POWEROFF BIT(7)
+
+static u8 mvolt_to_cfg(int mvolt, int min, int max, int div)
+{
+ if (mvolt < min)
+ mvolt = min;
+ else if (mvolt > max)
+ mvolt = max;
+
+ return (mvolt - min) / div;
+}
+
+static int axp_set_dcdc(int dcdc_num, unsigned int mvolt)
+{
+ int ret;
+ u8 cfg, enable_mask = 1U << (dcdc_num - 1);
+ int volt_reg = AXP313_DCDC1_CTRL + dcdc_num - 1;
+ int max_mV;
+
+ switch (dcdc_num) {
+ case 1:
+ case 2:
+ max_mV = 1540;
+ break;
+ case 3:
+ /*
+ * The manual defines a different split point, but tests
+ * show that it's the same 1200mV as for DCDC1/2.
+ */
+ max_mV = 1840;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (mvolt > AXP313_DCDC_SPLIT_MVOLT)
+ cfg = AXP313_DCDC_SPLIT_OFFSET + mvolt_to_cfg(mvolt,
+ AXP313_DCDC_SPLIT_MVOLT + 20, max_mV, 20);
+ else
+ cfg = mvolt_to_cfg(mvolt, 500, AXP313_DCDC_SPLIT_MVOLT, 10);
+
+ if (mvolt == 0)
+ return pmic_bus_clrbits(AXP313_OUTPUT_CTRL, enable_mask);
+
+ debug("DCDC%d: writing 0x%x to reg 0x%x\n", dcdc_num, cfg, volt_reg);
+ ret = pmic_bus_write(volt_reg, cfg);
+ if (ret)
+ return ret;
+
+ return pmic_bus_setbits(AXP313_OUTPUT_CTRL, enable_mask);
+}
+
+int axp_set_dcdc2(unsigned int mvolt)
+{
+ return axp_set_dcdc(2, mvolt);
+}
+
+int axp_set_dcdc3(unsigned int mvolt)
+{
+ return axp_set_dcdc(3, mvolt);
+}
+
+int axp_init(void)
+{
+ u8 axp_chip_id;
+ int ret;
+
+ ret = pmic_bus_init();
+ if (ret)
+ return ret;
+
+ ret = pmic_bus_read(AXP313_CHIP_VERSION, &axp_chip_id);
+ if (ret)
+ return ret;
+
+ axp_chip_id &= AXP313_CHIP_VERSION_MASK;
+ switch (axp_chip_id) {
+ case AXP313_CHIP_VERSION_AXP1530:
+ case AXP313_CHIP_VERSION_AXP313A:
+ case AXP313_CHIP_VERSION_AXP313B:
+ break;
+ default:
+ debug("unknown PMIC: 0x%x\n", axp_chip_id);
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+#if !CONFIG_IS_ENABLED(ARM_PSCI_FW) && !IS_ENABLED(CONFIG_SYSRESET_CMD_POWEROFF)
+int do_poweroff(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ pmic_bus_write(AXP313_SHUTDOWN, AXP313_POWEROFF);
+
+ /* infinite loop during shutdown */
+ while (1) {}
+
+ /* not reached */
+ return 0;
+}
+#endif
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index 411c210..bd82d2f 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -83,6 +83,13 @@
simply accepts requests to power on/off various HW modules without
actually doing anything beyond a little error checking.
+config SCMI_POWER_DOMAIN
+ bool "Enable SCMI power domain driver"
+ depends on POWER_DOMAIN && SCMI_FIRMWARE
+ help
+ Enable power domain implementation based on SCMI power domain
+ management protocol.
+
config TEGRA186_POWER_DOMAIN
bool "Enable Tegra186 BPMP-based power domain driver"
depends on TEGRA186_BPMP
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index aa5a4ba..2daab73 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -15,6 +15,7 @@
obj-$(CONFIG_MESON_SECURE_POWER_DOMAIN) += meson-secure-pwrc.o
obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
+obj-$(CONFIG_SCMI_POWER_DOMAIN) += scmi-power-domain.o
obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o
obj-$(CONFIG_TI_SCI_POWER_DOMAIN) += ti-sci-power-domain.o
obj-$(CONFIG_TI_POWER_DOMAIN) += ti-power-domain.o
diff --git a/drivers/power/domain/scmi-power-domain.c b/drivers/power/domain/scmi-power-domain.c
new file mode 100644
index 0000000..3cd0f07
--- /dev/null
+++ b/drivers/power/domain/scmi-power-domain.c
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * SCMI Power domain driver
+ *
+ * Copyright (C) 2023 Linaro Limited
+ * author: AKASHI Takahiro <takahiro.akashi@linaro.org>
+ */
+
+#include <dm.h>
+#include <malloc.h>
+#include <power-domain.h>
+#include <power-domain-uclass.h>
+#include <scmi_agent.h>
+#include <scmi_protocols.h>
+#include <dm/device_compat.h>
+
+/**
+ * struct scmi_pwd_properties
+ * @attributes: Power domain attributes
+ * @name: Name of the domain
+ */
+struct scmi_pwd_properties {
+ u32 attributes;
+ u8 *name; /* not used now */
+};
+
+/**
+ * struct scmi_power_domain_priv
+ * @num_pwdoms: Number of power domains
+ * @prop: Pointer to domain's properties
+ * @stats_addr: Address of statistics memory region
+ * @stats_len: Length of statistics memory region
+ */
+struct scmi_power_domain_priv {
+ int num_pwdoms;
+ struct scmi_pwd_properties *prop;
+ u64 stats_addr;
+ size_t stats_len;
+};
+
+/**
+ * async_is_supported - check asynchronous transition
+ * @attributes: Power domain attributes
+ *
+ * Determine if the power transition can be done asynchronously.
+ *
+ * Return: true if supported, false if not
+ */
+static bool async_is_supported(u32 attributes)
+{
+ if (attributes & SCMI_PWD_ATTR_PSTATE_ASYNC)
+ return true;
+
+ /* TODO: check attributes && SCMI_PWD_ATTR_PSTATE_SYNC */
+ return false;
+}
+
+/**
+ * scmi_power_domain_on - Enable the power domain
+ * @power_domain: Power domain
+ *
+ * Turn on the power domain.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int scmi_power_domain_on(struct power_domain *power_domain)
+{
+ struct scmi_power_domain_priv *priv = dev_get_priv(power_domain->dev);
+ u32 flags, pstate;
+ int ret;
+
+ if (power_domain->id > priv->num_pwdoms)
+ return -EINVAL;
+
+ if (async_is_supported(priv->prop[power_domain->id].attributes))
+ flags = SCMI_PWD_SET_FLAGS_ASYNC;
+ else
+ flags = 0;
+
+ /* ON */
+ pstate = 0;
+
+ ret = scmi_pwd_state_set(power_domain->dev, flags, power_domain->id,
+ pstate);
+ if (ret) {
+ dev_err(power_domain->dev, "failed to set the state on (%d)\n",
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * scmi_power_domain_off - Disable the power domain
+ * @power_domain: Power domain
+ *
+ * Turn off the power domain.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int scmi_power_domain_off(struct power_domain *power_domain)
+{
+ struct scmi_power_domain_priv *priv = dev_get_priv(power_domain->dev);
+ u32 flags, pstate;
+ int ret;
+
+ if (power_domain->id > priv->num_pwdoms)
+ return -EINVAL;
+
+ if (async_is_supported(priv->prop[power_domain->id].attributes))
+ flags = SCMI_PWD_SET_FLAGS_ASYNC;
+ else
+ flags = 0;
+
+ /* OFF */
+ pstate = SCMI_PWD_PSTATE_TYPE_LOST;
+
+ ret = scmi_pwd_state_set(power_domain->dev, flags, power_domain->id,
+ pstate);
+ if (ret) {
+ dev_err(power_domain->dev, "failed to set the state off (%d)\n",
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * scmi_power_domain_probe - Probe the power domain
+ * @dev: Power domain device
+ *
+ * Probe the power domain and initialize the properties.
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int scmi_power_domain_probe(struct udevice *dev)
+{
+ struct scmi_power_domain_priv *priv = dev_get_priv(dev);
+ u32 version;
+ int i, ret;
+
+ ret = devm_scmi_of_get_channel(dev);
+ if (ret) {
+ dev_err(dev, "failed to get channel (%d)\n", ret);
+ return ret;
+ }
+
+ ret = scmi_generic_protocol_version(dev, SCMI_PROTOCOL_ID_POWER_DOMAIN,
+ &version);
+
+ ret = scmi_pwd_protocol_attrs(dev, &priv->num_pwdoms, &priv->stats_addr,
+ &priv->stats_len);
+ if (ret) {
+ dev_err(dev, "failed to get protocol attributes (%d)\n", ret);
+ return ret;
+ }
+
+ priv->prop = calloc(sizeof(*priv->prop), priv->num_pwdoms);
+ if (!priv->prop)
+ return -ENOMEM;
+
+ for (i = 0; i < priv->num_pwdoms; i++) {
+ ret = scmi_pwd_attrs(dev, i, &priv->prop[i].attributes,
+ &priv->prop[i].name);
+ if (ret) {
+ dev_err(dev, "failed to get attributes pwd:%d (%d)\n",
+ i, ret);
+ for (i--; i >= 0; i--)
+ free(priv->prop[i].name);
+ free(priv->prop);
+
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+struct power_domain_ops scmi_power_domain_ops = {
+ .on = scmi_power_domain_on,
+ .off = scmi_power_domain_off,
+};
+
+U_BOOT_DRIVER(scmi_power_domain) = {
+ .name = "scmi_power_domain",
+ .id = UCLASS_POWER_DOMAIN,
+ .ops = &scmi_power_domain_ops,
+ .probe = scmi_power_domain_probe,
+ .priv_auto = sizeof(struct scmi_power_domain_priv),
+};
diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c
index 9e71513..b34c982 100644
--- a/drivers/power/domain/ti-power-domain.c
+++ b/drivers/power/domain/ti-power-domain.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments power domain driver
*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
* Tero Kristo <t-kristo@ti.com>
*/
diff --git a/drivers/power/domain/ti-sci-power-domain.c b/drivers/power/domain/ti-sci-power-domain.c
index 0140e5e..8d6abe1 100644
--- a/drivers/power/domain/ti-sci-power-domain.c
+++ b/drivers/power/domain/ti-sci-power-domain.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments System Control Interface (TI SCI) power domain driver
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Andreas Dannenberg <dannenberg@ti.com>
*
* Loosely based on Linux kernel ti_sci_pm_domains.c...
diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c
index 0959445..3ac9712 100644
--- a/drivers/power/palmas.c
+++ b/drivers/power/palmas.c
@@ -5,6 +5,7 @@
*/
#include <config.h>
#include <palmas.h>
+#include <linux/printk.h>
void palmas_init_settings(void)
{
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 176fb07..454a6e0 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -184,6 +184,15 @@
This config enables implementation of driver-model pmic uclass features
for PMIC PFUZE100 in SPL. The driver implements read/write operations.
+config DM_PMIC_MAX77663
+ bool "Enable Driver Model for PMIC MAX77663"
+ ---help---
+ This config enables implementation of driver-model pmic uclass features
+ for PMIC MAX77663. The driver implements read/write operations.
+ This is a Power Management IC with a decent set of peripherals from which
+ 4 DC-to-DC Step-Down (SD) Regulators, 9 Low-Dropout Linear (LDO) Regulators,
+ 8 GPIOs, Real-Time Clock (RTC) and more with I2C Compatible Interface.
+
config DM_PMIC_MAX77686
bool "Enable Driver Model for PMIC MAX77686"
---help---
@@ -233,6 +242,7 @@
config PMIC_RK8XX
bool "Enable support for Rockchip PMIC RK8XX"
+ select SYSRESET_CMD_POWEROFF if SYSRESET && CMD_POWEROFF
---help---
The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs,
an RTC and two low Rds (resistance (drain to source)) switches. It is
@@ -341,6 +351,17 @@
DC-DC converter, 8 LDOs and a RTC. This driver binds the SMPS and LDO
pmic children.
+config DM_PMIC_TPS80031
+ bool "Enable driver for Texas Instruments TPS80031/TPS80032 PMIC"
+ ---help---
+ This config enables implementation of driver-model pmic uclass features
+ for TPS80031/TPS80032 PMICs. The driver implements read/write operations.
+ This is a Power Management IC with a decent set of peripherals from which
+ 5 Buck Converters refered as Switched-mode power supply (SMPS), 11 General-
+ Purpose Low-Dropout Voltage Regulators (LDO), USB OTG Module, Real-Time
+ Clock (RTC) with Timer and Alarm Wake-Up, Two Digital PWM Outputs and more
+ with I2C Compatible Interface. PMIC occupies 4 I2C addresses.
+
config PMIC_STPMIC1
bool "Enable support for STMicroelectronics STPMIC1 PMIC"
depends on DM_I2C
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 0b3b3d6..55ee614 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_$(SPL_TPL_)DM_PMIC) += pmic-uclass.o
obj-$(CONFIG_$(SPL_)DM_PMIC_FAN53555) += fan53555.o
obj-$(CONFIG_$(SPL_)DM_PMIC_DA9063) += da9063.o
+obj-$(CONFIG_$(SPL_)DM_PMIC_MAX77663) += max77663.o
obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
obj-$(CONFIG_DM_PMIC_MC34708) += mc34708.o
@@ -26,6 +27,7 @@
obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
obj-$(CONFIG_DM_PMIC_TPS65910) += pmic_tps65910_dm.o
+obj-$(CONFIG_$(SPL_)DM_PMIC_TPS80031) += tps80031.o
obj-$(CONFIG_$(SPL_)PMIC_PALMAS) += palmas.o
obj-$(CONFIG_$(SPL_)PMIC_LP873X) += lp873x.o
obj-$(CONFIG_$(SPL_)PMIC_LP87565) += lp87565.o
diff --git a/drivers/power/pmic/as3722.c b/drivers/power/pmic/as3722.c
index 3aa3cce..c7dd970 100644
--- a/drivers/power/pmic/as3722.c
+++ b/drivers/power/pmic/as3722.c
@@ -12,6 +12,7 @@
#include <i2c.h>
#include <log.h>
#include <dm/lists.h>
+#include <linux/printk.h>
#include <power/as3722.h>
#include <power/pmic.h>
diff --git a/drivers/power/pmic/as3722_gpio.c b/drivers/power/pmic/as3722_gpio.c
index 96943bc..987fbdf 100644
--- a/drivers/power/pmic/as3722_gpio.c
+++ b/drivers/power/pmic/as3722_gpio.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <dm.h>
#include <asm/gpio.h>
+#include <linux/printk.h>
#include <power/as3722.h>
#include <power/pmic.h>
diff --git a/drivers/power/pmic/axp.c b/drivers/power/pmic/axp.c
index 025dac2..0e1e45f 100644
--- a/drivers/power/pmic/axp.c
+++ b/drivers/power/pmic/axp.c
@@ -87,6 +87,7 @@
{ .compatible = "x-powers,axp209", .data = AXP209_ID },
{ .compatible = "x-powers,axp221", .data = AXP221_ID },
{ .compatible = "x-powers,axp223", .data = AXP223_ID },
+ { .compatible = "x-powers,axp313a", .data = AXP313_ID },
{ .compatible = "x-powers,axp803", .data = AXP803_ID },
{ .compatible = "x-powers,axp806", .data = AXP806_ID },
{ .compatible = "x-powers,axp809", .data = AXP809_ID },
diff --git a/drivers/power/pmic/bd71837.c b/drivers/power/pmic/bd71837.c
index fdbbd6f..ee6ae78 100644
--- a/drivers/power/pmic/bd71837.c
+++ b/drivers/power/pmic/bd71837.c
@@ -9,6 +9,7 @@
#include <i2c.h>
#include <log.h>
#include <asm/global_data.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <power/bd71837.h>
diff --git a/drivers/power/pmic/da9063.c b/drivers/power/pmic/da9063.c
index 25101d1..ca95b82 100644
--- a/drivers/power/pmic/da9063.c
+++ b/drivers/power/pmic/da9063.c
@@ -10,6 +10,7 @@
#include <dm.h>
#include <i2c.h>
#include <log.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <power/da9063_pmic.h>
diff --git a/drivers/power/pmic/fan53555.c b/drivers/power/pmic/fan53555.c
index 0d91628..d556b9a 100644
--- a/drivers/power/pmic/fan53555.c
+++ b/drivers/power/pmic/fan53555.c
@@ -10,6 +10,7 @@
#include <dm/device_compat.h>
#include <dm/lists.h>
#include <i2c.h>
+#include <linux/printk.h>
#include <power/fan53555.h>
#include <power/pmic.h>
#include <power/regulator.h>
diff --git a/drivers/power/pmic/i2c_pmic_emul.c b/drivers/power/pmic/i2c_pmic_emul.c
index abe3a10..f0a0374 100644
--- a/drivers/power/pmic/i2c_pmic_emul.c
+++ b/drivers/power/pmic/i2c_pmic_emul.c
@@ -10,6 +10,7 @@
#include <i2c.h>
#include <log.h>
#include <malloc.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/sandbox_pmic.h>
diff --git a/drivers/power/pmic/lp873x.c b/drivers/power/pmic/lp873x.c
index 2b1260e..fda5bc1 100644
--- a/drivers/power/pmic/lp873x.c
+++ b/drivers/power/pmic/lp873x.c
@@ -10,6 +10,7 @@
#include <dm.h>
#include <i2c.h>
#include <log.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <power/lp873x.h>
diff --git a/drivers/power/pmic/lp87565.c b/drivers/power/pmic/lp87565.c
index f4a4bd0..904e02c 100644
--- a/drivers/power/pmic/lp87565.c
+++ b/drivers/power/pmic/lp87565.c
@@ -10,6 +10,7 @@
#include <dm.h>
#include <i2c.h>
#include <log.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <power/lp87565.h>
diff --git a/drivers/power/pmic/max77663.c b/drivers/power/pmic/max77663.c
new file mode 100644
index 0000000..68c3cbb
--- /dev/null
+++ b/drivers/power/pmic/max77663.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <dm/lists.h>
+#include <power/pmic.h>
+#include <power/max77663.h>
+
+static const struct pmic_child_info pmic_children_info[] = {
+ { .prefix = "ldo", .driver = MAX77663_LDO_DRIVER },
+ { .prefix = "sd", .driver = MAX77663_SD_DRIVER },
+ { },
+};
+
+static int max77663_write(struct udevice *dev, uint reg, const uint8_t *buff,
+ int len)
+{
+ int ret;
+
+ ret = dm_i2c_write(dev, reg, buff, len);
+ if (ret) {
+ log_debug("write error to device: %p register: %#x!\n", dev, reg);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int max77663_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+ int ret;
+
+ ret = dm_i2c_read(dev, reg, buff, len);
+ if (ret) {
+ log_debug("read error from device: %p register: %#x!\n", dev, reg);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int max77663_bind(struct udevice *dev)
+{
+ ofnode regulators_node;
+ int children, ret;
+
+ if (IS_ENABLED(CONFIG_SYSRESET_MAX77663)) {
+ ret = device_bind_driver(dev, MAX77663_RST_DRIVER,
+ "sysreset", NULL);
+ if (ret) {
+ log_err("cannot bind SYSRESET (ret = %d)\n", ret);
+ return ret;
+ }
+ }
+
+ regulators_node = dev_read_subnode(dev, "regulators");
+ if (!ofnode_valid(regulators_node)) {
+ log_err("%s regulators subnode not found!\n", dev->name);
+ return -ENXIO;
+ }
+
+ debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
+
+ children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+ if (!children)
+ log_err("%s - no child found\n", dev->name);
+
+ /* Always return success for this device */
+ return 0;
+}
+
+static struct dm_pmic_ops max77663_ops = {
+ .read = max77663_read,
+ .write = max77663_write,
+};
+
+static const struct udevice_id max77663_ids[] = {
+ { .compatible = "maxim,max77663" },
+ { }
+};
+
+U_BOOT_DRIVER(pmic_max77663) = {
+ .name = "max77663_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = max77663_ids,
+ .bind = max77663_bind,
+ .ops = &max77663_ops,
+};
diff --git a/drivers/power/pmic/max77686.c b/drivers/power/pmic/max77686.c
index 9f02c0b..7e6f7d1 100644
--- a/drivers/power/pmic/max77686.c
+++ b/drivers/power/pmic/max77686.c
@@ -10,6 +10,7 @@
#include <dm.h>
#include <i2c.h>
#include <log.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <power/max77686_pmic.h>
diff --git a/drivers/power/pmic/max8997.c b/drivers/power/pmic/max8997.c
index dbae155..504a63b 100644
--- a/drivers/power/pmic/max8997.c
+++ b/drivers/power/pmic/max8997.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <dm.h>
#include <i2c.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/max8997_pmic.h>
#include <errno.h>
diff --git a/drivers/power/pmic/max8998.c b/drivers/power/pmic/max8998.c
index f58d9f2..d155474 100644
--- a/drivers/power/pmic/max8998.c
+++ b/drivers/power/pmic/max8998.c
@@ -8,6 +8,7 @@
#include <dm.h>
#include <errno.h>
#include <i2c.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/max8998_pmic.h>
diff --git a/drivers/power/pmic/palmas.c b/drivers/power/pmic/palmas.c
index 6080cbf..32f2a93 100644
--- a/drivers/power/pmic/palmas.c
+++ b/drivers/power/pmic/palmas.c
@@ -8,12 +8,13 @@
#include <fdtdec.h>
#include <errno.h>
#include <dm.h>
+#include <dm/lists.h>
#include <i2c.h>
#include <log.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <power/palmas.h>
-#include <dm/device.h>
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = "ldo", .driver = PALMAS_LDO_DRIVER },
@@ -46,7 +47,16 @@
{
ofnode pmic_node = ofnode_null(), regulators_node;
ofnode subnode;
- int children;
+ int children, ret;
+
+ if (IS_ENABLED(CONFIG_SYSRESET_PALMAS)) {
+ ret = device_bind_driver(dev, PALMAS_RST_DRIVER,
+ "sysreset", NULL);
+ if (ret) {
+ log_err("cannot bind SYSRESET (ret = %d)\n", ret);
+ return ret;
+ }
+ }
dev_for_each_subnode(subnode, dev) {
const char *name;
@@ -80,6 +90,24 @@
return 0;
}
+static int palmas_probe(struct udevice *dev)
+{
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
+ struct palmas_priv *priv = dev_get_priv(dev);
+ struct udevice *bus = dev_get_parent(dev);
+ u32 chip2_addr = chip->chip_addr + 1;
+ int ret;
+
+ /* Palmas PMIC is multi chip and chips are located in a row */
+ ret = i2c_get_chip(bus, chip2_addr, 1, &priv->chip2);
+ if (ret) {
+ log_err("cannot get second PMIC I2C chip (err %d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
static struct dm_pmic_ops palmas_ops = {
.read = palmas_read,
.write = palmas_write,
@@ -87,6 +115,7 @@
static const struct udevice_id palmas_ids[] = {
{ .compatible = "ti,tps659038", .data = TPS659038 },
+ { .compatible = "ti,tps65913" , .data = TPS659038 },
{ .compatible = "ti,tps65917" , .data = TPS65917 },
{ }
};
@@ -96,5 +125,7 @@
.id = UCLASS_PMIC,
.of_match = palmas_ids,
.bind = palmas_bind,
+ .probe = palmas_probe,
.ops = &palmas_ops,
+ .priv_auto = sizeof(struct palmas_priv),
};
diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c
index e99ece8..0bbe98c 100644
--- a/drivers/power/pmic/pca9450.c
+++ b/drivers/power/pmic/pca9450.c
@@ -13,6 +13,7 @@
#include <log.h>
#include <asm/global_data.h>
#include <asm-generic/gpio.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <power/pca9450.h>
diff --git a/drivers/power/pmic/pfuze100.c b/drivers/power/pmic/pfuze100.c
index 65c4456..15420ac 100644
--- a/drivers/power/pmic/pfuze100.c
+++ b/drivers/power/pmic/pfuze100.c
@@ -10,6 +10,7 @@
#include <dm.h>
#include <i2c.h>
#include <log.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <power/pfuze100_pmic.h>
diff --git a/drivers/power/pmic/pmic_tps62362.c b/drivers/power/pmic/pmic_tps62362.c
index 59190d6..6426d14 100644
--- a/drivers/power/pmic/pmic_tps62362.c
+++ b/drivers/power/pmic/pmic_tps62362.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2014 Texas Instruments Incorporated - http://www.ti.com
+ * (C) Copyright 2014 Texas Instruments Incorporated - https://www.ti.com
* Author: Felipe Balbi <balbi@ti.com>
*/
diff --git a/drivers/power/pmic/pmic_tps65910_dm.c b/drivers/power/pmic/pmic_tps65910_dm.c
index e03ddc9..ecf836e 100644
--- a/drivers/power/pmic/pmic_tps65910_dm.c
+++ b/drivers/power/pmic/pmic_tps65910_dm.c
@@ -5,19 +5,27 @@
#include <common.h>
#include <dm.h>
+#include <dm/lists.h>
#include <i2c.h>
#include <log.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <power/tps65910_pmic.h>
-static const struct pmic_child_info pmic_children_info[] = {
+static const struct pmic_child_info tps65910_children_info[] = {
{ .prefix = "ldo_", .driver = TPS65910_LDO_DRIVER },
{ .prefix = "buck_", .driver = TPS65910_BUCK_DRIVER },
{ .prefix = "boost_", .driver = TPS65910_BOOST_DRIVER },
{ },
};
+static const struct pmic_child_info tps65911_children_info[] = {
+ { .prefix = "ldo", .driver = TPS65911_LDO_DRIVER },
+ { .prefix = "vdd", .driver = TPS65911_VDD_DRIVER },
+ { },
+};
+
static int pmic_tps65910_reg_count(struct udevice *dev)
{
return TPS65910_NUM_REGS;
@@ -49,8 +57,19 @@
static int pmic_tps65910_bind(struct udevice *dev)
{
+ const struct pmic_child_info *tps6591x_children_info =
+ (struct pmic_child_info *)dev_get_driver_data(dev);
ofnode regulators_node;
- int children;
+ int children, ret;
+
+ if (IS_ENABLED(CONFIG_SYSRESET_TPS65910)) {
+ ret = device_bind_driver(dev, TPS65910_RST_DRIVER,
+ "sysreset", NULL);
+ if (ret) {
+ log_err("cannot bind SYSRESET (ret = %d)\n", ret);
+ return ret;
+ }
+ }
regulators_node = dev_read_subnode(dev, "regulators");
if (!ofnode_valid(regulators_node)) {
@@ -58,7 +77,7 @@
return -EINVAL;
}
- children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+ children = pmic_bind_children(dev, regulators_node, tps6591x_children_info);
if (!children)
debug("%s has no children (regulators)\n", dev->name);
@@ -82,7 +101,8 @@
};
static const struct udevice_id pmic_tps65910_match[] = {
- { .compatible = "ti,tps65910" },
+ { .compatible = "ti,tps65910", .data = (ulong)&tps65910_children_info },
+ { .compatible = "ti,tps65911", .data = (ulong)&tps65911_children_info },
{ /* sentinel */ }
};
diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c
index 25ef621..4e3a173 100644
--- a/drivers/power/pmic/rk8xx.c
+++ b/drivers/power/pmic/rk8xx.c
@@ -156,6 +156,10 @@
if (!children)
debug("%s: %s - no child found\n", __func__, dev->name);
+ if (IS_ENABLED(CONFIG_SPL_BUILD) &&
+ IS_ENABLED(CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON))
+ dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+
/* Always return success for this device */
return 0;
}
@@ -236,14 +240,16 @@
pmic_reg_read(dev, init_data[i].reg));
}
- printf("PMIC: RK%x ", show_variant);
+ if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+ printf("PMIC: RK%x ", show_variant);
+ if (on_source && off_source)
+ printf("(on=0x%02x, off=0x%02x)",
+ pmic_reg_read(dev, on_source),
+ pmic_reg_read(dev, off_source));
+ printf("\n");
+ }
- if (on_source && off_source)
- printf("(on=0x%02x, off=0x%02x)",
- pmic_reg_read(dev, on_source),
- pmic_reg_read(dev, off_source));
- printf("\n");
- if (CONFIG_IS_ENABLED(ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON))
+ if (IS_ENABLED(CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON))
rk8xx_off_for_plugin(dev);
return 0;
diff --git a/drivers/power/pmic/s2mps11.c b/drivers/power/pmic/s2mps11.c
index 1ba1640..5ff4f20 100644
--- a/drivers/power/pmic/s2mps11.c
+++ b/drivers/power/pmic/s2mps11.c
@@ -10,6 +10,7 @@
#include <dm.h>
#include <i2c.h>
#include <log.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/s2mps11.h>
diff --git a/drivers/power/pmic/s5m8767.c b/drivers/power/pmic/s5m8767.c
index db6d035..eea072a 100644
--- a/drivers/power/pmic/s5m8767.c
+++ b/drivers/power/pmic/s5m8767.c
@@ -9,6 +9,7 @@
#include <dm.h>
#include <i2c.h>
#include <log.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <power/s5m8767.h>
diff --git a/drivers/power/pmic/sandbox.c b/drivers/power/pmic/sandbox.c
index acfeae2..14b8245 100644
--- a/drivers/power/pmic/sandbox.c
+++ b/drivers/power/pmic/sandbox.c
@@ -12,6 +12,7 @@
#include <dm.h>
#include <i2c.h>
#include <log.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <power/sandbox_pmic.h>
diff --git a/drivers/power/pmic/tps65090.c b/drivers/power/pmic/tps65090.c
index b81df0d..2a04d59 100644
--- a/drivers/power/pmic/tps65090.c
+++ b/drivers/power/pmic/tps65090.c
@@ -10,6 +10,7 @@
#include <fdtdec.h>
#include <i2c.h>
#include <log.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/tps65090.h>
diff --git a/drivers/power/pmic/tps65941.c b/drivers/power/pmic/tps65941.c
index 83d0f83..727b427 100644
--- a/drivers/power/pmic/tps65941.c
+++ b/drivers/power/pmic/tps65941.c
@@ -10,6 +10,7 @@
#include <dm.h>
#include <i2c.h>
#include <log.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <power/tps65941.h>
diff --git a/drivers/power/pmic/tps80031.c b/drivers/power/pmic/tps80031.c
new file mode 100644
index 0000000..a2f935b
--- /dev/null
+++ b/drivers/power/pmic/tps80031.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <dm/lists.h>
+#include <power/pmic.h>
+#include <power/tps80031.h>
+
+static const struct pmic_child_info pmic_children_info[] = {
+ { .prefix = "ldo", .driver = TPS80031_LDO_DRIVER },
+ { .prefix = "smps", .driver = TPS80031_SMPS_DRIVER },
+ { },
+};
+
+static int tps80031_write(struct udevice *dev, uint reg, const uint8_t *buff,
+ int len)
+{
+ int ret;
+
+ ret = dm_i2c_write(dev, reg, buff, len);
+ if (ret) {
+ log_debug("write error to device: %p register: %#x!\n", dev, reg);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int tps80031_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+ int ret;
+
+ ret = dm_i2c_read(dev, reg, buff, len);
+ if (ret) {
+ log_debug("read error from device: %p register: %#x!\n", dev, reg);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int tps80031_bind(struct udevice *dev)
+{
+ ofnode regulators_node;
+ int children, ret;
+
+ if (IS_ENABLED(CONFIG_SYSRESET_TPS80031)) {
+ ret = device_bind_driver(dev, TPS80031_RST_DRIVER,
+ "sysreset", NULL);
+ if (ret) {
+ log_err("cannot bind SYSRESET (ret = %d)\n", ret);
+ return ret;
+ }
+ }
+
+ regulators_node = dev_read_subnode(dev, "regulators");
+ if (!ofnode_valid(regulators_node)) {
+ log_err("%s regulators subnode not found!\n", dev->name);
+ return -ENXIO;
+ }
+
+ debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
+
+ children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+ if (!children)
+ log_err("%s - no child found\n", dev->name);
+
+ /* Always return success for this device */
+ return 0;
+}
+
+static struct dm_pmic_ops tps80031_ops = {
+ .read = tps80031_read,
+ .write = tps80031_write,
+};
+
+static const struct udevice_id tps80031_ids[] = {
+ { .compatible = "ti,tps80031" },
+ { .compatible = "ti,tps80032" },
+ { }
+};
+
+U_BOOT_DRIVER(pmic_tps80031) = {
+ .name = "tps80031_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = tps80031_ids,
+ .bind = tps80031_bind,
+ .ops = &tps80031_ops,
+};
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index eb5aa38..102ec7b 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -141,6 +141,15 @@
This config enables implementation of driver-model regulator uclass
features for PWM regulators in SPL.
+config DM_REGULATOR_MAX77663
+ bool "Enable Driver Model for REGULATOR MAX77663"
+ depends on DM_REGULATOR && DM_PMIC_MAX77663
+ ---help---
+ This config enables implementation of driver-model regulator uclass
+ features for REGULATOR MAX77663. The driver supports both DC-to-DC
+ Step-Down (SD) Regulators and Low-Dropout Linear (LDO) Regulators
+ found in MAX77663 PMIC and implements get/set api for value and enable.
+
config DM_REGULATOR_MAX77686
bool "Enable Driver Model for REGULATOR MAX77686"
depends on DM_REGULATOR && DM_PMIC_MAX77686
@@ -337,6 +346,17 @@
regulator types of the TPS65910 (BUCK, BOOST and LDO). It implements
the get/set api for value and enable.
+config DM_REGULATOR_TPS65911
+ bool "Enable driver for TPS65911 PMIC regulators"
+ depends on DM_PMIC_TPS65910
+ ---help---
+ This config enables implementation of driver-model regulator
+ uclass features for the TPS65911 PMIC. The driver supports Step-Down
+ DC-DC Converters for Processor Cores (VDD1 and VDD2), Step-Down DC-DC
+ Converter for I/O Power (VIO), Controller for External FETs (VDDCtrl)
+ and LDO Voltage Regulators found in TPS65911 PMIC and implements
+ get/set api for value and enable.
+
config DM_REGULATOR_TPS62360
bool "Enable driver for TPS6236x Power Regulator"
depends on DM_REGULATOR
@@ -347,6 +367,14 @@
implements the get/set api for value only, as the power line is
always on.
+config DM_REGULATOR_TPS80031
+ bool "Enable driver for TPS80031/TPS80032 PMIC regulators"
+ depends on DM_PMIC_TPS80031
+ ---help---
+ This enables implementation of driver-model regulator uclass
+ features for TPS80031/TPS80032 PMICs. The driver implements
+ get/set api for: value and enable.
+
config DM_REGULATOR_STPMIC1
bool "Enable driver for STPMIC1 regulators"
depends on DM_REGULATOR && PMIC_STPMIC1
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index d9e0cd5..f79932d 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -10,6 +10,7 @@
obj-$(CONFIG_$(SPL_)REGULATOR_AXP) += axp_regulator.o
obj-$(CONFIG_$(SPL_)REGULATOR_AXP_USB_POWER) += axp_usb_power.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_DA9063) += da9063.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_MAX77663) += max77663_regulator.o
obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
obj-$(CONFIG_DM_REGULATOR_NPCM8XX) += npcm8xx_regulator.o
obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
@@ -31,7 +32,9 @@
obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP87565) += lp87565_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_STM32_VREFBUF) += stm32-vrefbuf.o
obj-$(CONFIG_DM_REGULATOR_TPS65910) += tps65910_regulator.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS65911) += tps65911_regulator.o
obj-$(CONFIG_DM_REGULATOR_TPS62360) += tps62360_regulator.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS80031) += tps80031_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_STPMIC1) += stpmic1.o
obj-$(CONFIG_DM_REGULATOR_TPS65941) += tps65941_regulator.o
obj-$(CONFIG_DM_REGULATOR_SCMI) += scmi_regulator.o
diff --git a/drivers/power/regulator/axp_regulator.c b/drivers/power/regulator/axp_regulator.c
index 02f320e..d27e095 100644
--- a/drivers/power/regulator/axp_regulator.c
+++ b/drivers/power/regulator/axp_regulator.c
@@ -173,6 +173,22 @@
{ }
};
+/*
+ * The "dcdc1" regulator has another range, beyond 1.54V up to 3.4V, in
+ * steps of 100mV. We cannot model this easily, but also don't need that,
+ * since it's typically only used for ~1.1V anyway, so just ignore it.
+ * Also the DCDC3 regulator is described wrongly in the (available) manual,
+ * experiments show that the split point is at 1200mV, as for DCDC1/2.
+ */
+static const struct axp_regulator_plat axp313_regulators[] = {
+ { "dcdc1", 0x10, BIT(0), 0x13, 0x7f, 500, 1540, 10, 70 },
+ { "dcdc2", 0x10, BIT(1), 0x14, 0x7f, 500, 1540, 10, 70 },
+ { "dcdc3", 0x10, BIT(2), 0x15, 0x7f, 500, 1840, 10, 70 },
+ { "aldo1", 0x10, BIT(3), 0x16, 0x1f, 500, 3500, 100, NA },
+ { "dldo1", 0x10, BIT(4), 0x17, 0x1f, 500, 3500, 100, NA },
+ { }
+};
+
static const struct axp_regulator_plat axp803_regulators[] = {
{ "dcdc1", 0x10, BIT(0), 0x20, 0x1f, 1600, 3400, 100, NA },
{ "dcdc2", 0x10, BIT(1), 0x21, 0x7f, 500, 1300, 10, 70 },
@@ -274,6 +290,7 @@
[AXP209_ID] = axp20x_regulators,
[AXP221_ID] = axp22x_regulators,
[AXP223_ID] = axp22x_regulators,
+ [AXP313_ID] = axp313_regulators,
[AXP803_ID] = axp803_regulators,
[AXP806_ID] = axp806_regulators,
[AXP809_ID] = axp809_regulators,
diff --git a/drivers/power/regulator/bd71837.c b/drivers/power/regulator/bd71837.c
index d4f8da8..913ed88 100644
--- a/drivers/power/regulator/bd71837.c
+++ b/drivers/power/regulator/bd71837.c
@@ -9,6 +9,7 @@
#include <dm.h>
#include <log.h>
#include <linux/bitops.h>
+#include <linux/printk.h>
#include <power/bd71837.h>
#include <power/pmic.h>
#include <power/regulator.h>
diff --git a/drivers/power/regulator/fan53555.c b/drivers/power/regulator/fan53555.c
index 815f96b..fa8d88f 100644
--- a/drivers/power/regulator/fan53555.c
+++ b/drivers/power/regulator/fan53555.c
@@ -11,6 +11,7 @@
#include <log.h>
#include <asm/gpio.h>
#include <linux/bitops.h>
+#include <linux/printk.h>
#include <power/fan53555.h>
#include <power/pmic.h>
#include <power/regulator.h>
diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c
index f7ddba8..590c288 100644
--- a/drivers/power/regulator/fixed.c
+++ b/drivers/power/regulator/fixed.c
@@ -11,8 +11,10 @@
#include <dm.h>
#include <linux/delay.h>
#include <log.h>
+#include <asm/gpio.h>
#include <power/pmic.h>
#include <power/regulator.h>
+#include "regulator_common.h"
#include "regulator_common.h"
diff --git a/drivers/power/regulator/gpio-regulator.c b/drivers/power/regulator/gpio-regulator.c
index ded7be0..74137b7 100644
--- a/drivers/power/regulator/gpio-regulator.c
+++ b/drivers/power/regulator/gpio-regulator.c
@@ -10,8 +10,10 @@
#include <dm.h>
#include <log.h>
#include <asm/gpio.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/regulator.h>
+#include "regulator_common.h"
#include "regulator_common.h"
diff --git a/drivers/power/regulator/max77663_regulator.c b/drivers/power/regulator/max77663_regulator.c
new file mode 100644
index 0000000..ea4b7c6
--- /dev/null
+++ b/drivers/power/regulator/max77663_regulator.c
@@ -0,0 +1,375 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/max77663.h>
+
+/* fist row is control registers, second is voltage registers */
+static const char max77663_sd_reg[][MAX77663_SD_NUM] = {
+ { 0x1d, 0x1e, 0x1f, 0x20, 0x21 },
+ { 0x16, 0x17, 0x18, 0x19, 0x2a },
+};
+
+static const char max77663_ldo_reg[MAX77663_LDO_NUM] = {
+ 0x23, 0x25, 0x27, 0x29, 0x2b, 0x2d, 0x2f, 0x31, 0x33
+};
+
+static int max77663_sd_enable(struct udevice *dev, int op, bool *enable)
+{
+ struct dm_regulator_uclass_plat *uc_pdata =
+ dev_get_uclass_plat(dev);
+ u32 adr = uc_pdata->ctrl_reg;
+ int val, ret;
+
+ val = pmic_reg_read(dev->parent, adr);
+ if (val < 0)
+ return val;
+
+ if (op == PMIC_OP_GET) {
+ if (val & SD_STATUS_MASK)
+ *enable = true;
+ else
+ *enable = false;
+
+ return 0;
+ } else if (op == PMIC_OP_SET) {
+ val &= ~SD_STATUS_MASK;
+
+ if (*enable)
+ val |= SD_STATUS_MASK;
+
+ ret = pmic_reg_write(dev->parent, adr, val);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * max77663_*_volt2hex() - convert voltage in uV into
+ * applicable to register hex value
+ *
+ * @idx: regulator index
+ * @uV: voltage in uV
+ *
+ * Return: voltage in hex on success, -ve on failure
+ */
+static int max77663_sd_volt2hex(int idx, int uV)
+{
+ switch (idx) {
+ case 0:
+ /* SD0 has max voltage 1.4V */
+ if (uV > SD0_VOLT_MAX)
+ return -EINVAL;
+ break;
+ case 1:
+ /* SD1 has max voltage 1.55V */
+ if (uV > SD1_VOLT_MAX)
+ return -EINVAL;
+ break;
+ default:
+ /* SD2 and SD3 have max voltage 3.79V */
+ if (uV > SD_VOLT_MAX)
+ return -EINVAL;
+ break;
+ };
+
+ if (uV < SD_VOLT_MIN)
+ uV = SD_VOLT_MIN;
+
+ return (uV - SD_VOLT_BASE) / 12500;
+}
+
+/**
+ * max77663_*_hex2volt() - convert register hex value into
+ * actual voltage in uV
+ *
+ * @idx: regulator index
+ * @hex: hex value of register
+ *
+ * Return: voltage in uV on success, -ve on failure
+ */
+static int max77663_sd_hex2volt(int idx, int hex)
+{
+ switch (idx) {
+ case 0:
+ /* SD0 has max voltage 1.4V */
+ if (hex > SD0_VOLT_MAX_HEX)
+ return -EINVAL;
+ break;
+ case 1:
+ /* SD1 has max voltage 1.55V */
+ if (hex > SD1_VOLT_MAX_HEX)
+ return -EINVAL;
+ break;
+ default:
+ /* SD2 and SD3 have max voltage 3.79V */
+ if (hex > SD_VOLT_MAX_HEX)
+ return -EINVAL;
+ break;
+ };
+
+ if (hex < SD_VOLT_MIN_HEX)
+ hex = SD_VOLT_MIN_HEX;
+
+ return SD_VOLT_BASE + hex * 12500;
+}
+
+static int max77663_sd_val(struct udevice *dev, int op, int *uV)
+{
+ struct dm_regulator_uclass_plat *uc_pdata =
+ dev_get_uclass_plat(dev);
+ u32 adr = uc_pdata->volt_reg;
+ int idx = dev->driver_data;
+ int hex, ret;
+
+ if (op == PMIC_OP_GET) {
+ hex = pmic_reg_read(dev->parent, adr);
+ if (hex < 0)
+ return hex;
+
+ *uV = 0;
+
+ ret = max77663_sd_hex2volt(idx, hex);
+ if (ret < 0)
+ return ret;
+ *uV = ret;
+
+ return 0;
+ }
+
+ /* SD regulators use entire register for voltage */
+ hex = max77663_sd_volt2hex(idx, *uV);
+ if (hex < 0)
+ return hex;
+
+ return pmic_reg_write(dev->parent, adr, hex);
+}
+
+static int max77663_sd_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_plat *uc_pdata =
+ dev_get_uclass_plat(dev);
+ int idx = dev->driver_data;
+
+ uc_pdata->type = REGULATOR_TYPE_BUCK;
+ uc_pdata->ctrl_reg = max77663_sd_reg[0][idx];
+ uc_pdata->volt_reg = max77663_sd_reg[1][idx];
+
+ return 0;
+}
+
+static int sd_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = max77663_sd_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+
+ return uV;
+}
+
+static int sd_set_value(struct udevice *dev, int uV)
+{
+ return max77663_sd_val(dev, PMIC_OP_SET, &uV);
+}
+
+static int sd_get_enable(struct udevice *dev)
+{
+ bool enable = false;
+ int ret;
+
+ ret = max77663_sd_enable(dev, PMIC_OP_GET, &enable);
+ if (ret)
+ return ret;
+
+ return enable;
+}
+
+static int sd_set_enable(struct udevice *dev, bool enable)
+{
+ return max77663_sd_enable(dev, PMIC_OP_SET, &enable);
+}
+
+static const struct dm_regulator_ops max77663_sd_ops = {
+ .get_value = sd_get_value,
+ .set_value = sd_set_value,
+ .get_enable = sd_get_enable,
+ .set_enable = sd_set_enable,
+};
+
+U_BOOT_DRIVER(max77663_sd) = {
+ .name = MAX77663_SD_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &max77663_sd_ops,
+ .probe = max77663_sd_probe,
+};
+
+static int max77663_ldo_enable(struct udevice *dev, int op, bool *enable)
+{
+ struct dm_regulator_uclass_plat *uc_pdata =
+ dev_get_uclass_plat(dev);
+ u32 adr = uc_pdata->ctrl_reg;
+ int val, ret;
+
+ val = pmic_reg_read(dev->parent, adr);
+ if (val < 0)
+ return val;
+
+ if (op == PMIC_OP_GET) {
+ if (val & LDO_STATUS_MASK)
+ *enable = true;
+ else
+ *enable = false;
+
+ return 0;
+ } else if (op == PMIC_OP_SET) {
+ val &= ~LDO_STATUS_MASK;
+
+ if (*enable)
+ val |= LDO_STATUS_MASK;
+
+ ret = pmic_reg_write(dev->parent, adr, val);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int max77663_ldo_volt2hex(int idx, int uV)
+{
+ switch (idx) {
+ case 0:
+ case 1:
+ if (uV > LDO01_VOLT_MAX)
+ return -EINVAL;
+
+ return (uV - LDO_VOLT_BASE) / 25000;
+ case 4:
+ if (uV > LDO4_VOLT_MAX)
+ return -EINVAL;
+
+ return (uV - LDO_VOLT_BASE) / 12500;
+ default:
+ if (uV > LDO_VOLT_MAX)
+ return -EINVAL;
+
+ return (uV - LDO_VOLT_BASE) / 50000;
+ };
+}
+
+static int max77663_ldo_hex2volt(int idx, int hex)
+{
+ if (hex > LDO_VOLT_MAX_HEX)
+ return -EINVAL;
+
+ switch (idx) {
+ case 0:
+ case 1:
+ return (hex * 25000) + LDO_VOLT_BASE;
+ case 4:
+ return (hex * 12500) + LDO_VOLT_BASE;
+ default:
+ return (hex * 50000) + LDO_VOLT_BASE;
+ };
+}
+
+static int max77663_ldo_val(struct udevice *dev, int op, int *uV)
+{
+ struct dm_regulator_uclass_plat *uc_pdata =
+ dev_get_uclass_plat(dev);
+ u32 adr = uc_pdata->ctrl_reg;
+ int idx = dev->driver_data;
+ int hex, val, ret;
+
+ val = pmic_reg_read(dev->parent, adr);
+ if (val < 0)
+ return val;
+
+ if (op == PMIC_OP_GET) {
+ *uV = 0;
+
+ ret = max77663_ldo_hex2volt(idx, val & LDO_VOLT_MASK);
+ if (ret < 0)
+ return ret;
+
+ *uV = ret;
+ return 0;
+ }
+
+ hex = max77663_ldo_volt2hex(idx, *uV);
+ if (hex < 0)
+ return hex;
+
+ val &= ~LDO_VOLT_MASK;
+
+ return pmic_reg_write(dev->parent, adr, val | hex);
+}
+
+static int max77663_ldo_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_plat *uc_pdata =
+ dev_get_uclass_plat(dev);
+ int idx = dev->driver_data;
+
+ uc_pdata->type = REGULATOR_TYPE_LDO;
+ uc_pdata->ctrl_reg = max77663_ldo_reg[idx];
+
+ return 0;
+}
+
+static int ldo_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = max77663_ldo_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+
+ return uV;
+}
+
+static int ldo_set_value(struct udevice *dev, int uV)
+{
+ return max77663_ldo_val(dev, PMIC_OP_SET, &uV);
+}
+
+static int ldo_get_enable(struct udevice *dev)
+{
+ bool enable = false;
+ int ret;
+
+ ret = max77663_ldo_enable(dev, PMIC_OP_GET, &enable);
+ if (ret)
+ return ret;
+
+ return enable;
+}
+
+static int ldo_set_enable(struct udevice *dev, bool enable)
+{
+ return max77663_ldo_enable(dev, PMIC_OP_SET, &enable);
+}
+
+static const struct dm_regulator_ops max77663_ldo_ops = {
+ .get_value = ldo_get_value,
+ .set_value = ldo_set_value,
+ .get_enable = ldo_get_enable,
+ .set_enable = ldo_set_enable,
+};
+
+U_BOOT_DRIVER(max77663_ldo) = {
+ .name = MAX77663_LDO_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &max77663_ldo_ops,
+ .probe = max77663_ldo_probe,
+};
diff --git a/drivers/power/regulator/max77686.c b/drivers/power/regulator/max77686.c
index cef20e1..3a20803 100644
--- a/drivers/power/regulator/max77686.c
+++ b/drivers/power/regulator/max77686.c
@@ -10,6 +10,7 @@
#include <fdtdec.h>
#include <errno.h>
#include <dm.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <power/max77686_pmic.h>
diff --git a/drivers/power/regulator/palmas_regulator.c b/drivers/power/regulator/palmas_regulator.c
index 3c4eb83..d615e94 100644
--- a/drivers/power/regulator/palmas_regulator.c
+++ b/drivers/power/regulator/palmas_regulator.c
@@ -301,19 +301,23 @@
uc_pdata->type = REGULATOR_TYPE_LDO;
- if (dev->driver_data) {
+ /* check for ldoln and ldousb cases */
+ if (!strcmp("ldoln", dev->name)) {
+ uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][9];
+ uc_pdata->volt_reg = palmas_ldo_volt[type][9];
+ return 0;
+ }
+
+ if (!strcmp("ldousb", dev->name)) {
+ uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][10];
+ uc_pdata->volt_reg = palmas_ldo_volt[type][10];
+ return 0;
+ }
+
+ if (dev->driver_data > 0) {
u8 idx = dev->driver_data - 1;
uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][idx];
uc_pdata->volt_reg = palmas_ldo_volt[type][idx];
- } else {
- /* check for ldoln and ldousb cases */
- if (!strcmp("ldoln", dev->name)) {
- uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][9];
- uc_pdata->volt_reg = palmas_ldo_volt[type][9];
- } else if (!strcmp("ldousb", dev->name)) {
- uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][10];
- uc_pdata->volt_reg = palmas_ldo_volt[type][10];
- }
}
return 0;
diff --git a/drivers/power/regulator/pbias_regulator.c b/drivers/power/regulator/pbias_regulator.c
index 5bf186e..cf4e285 100644
--- a/drivers/power/regulator/pbias_regulator.c
+++ b/drivers/power/regulator/pbias_regulator.c
@@ -10,6 +10,7 @@
#include <log.h>
#include <linux/delay.h>
#include <linux/err.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <regmap.h>
diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c
index 3a6ba69..77d101f 100644
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -293,6 +293,9 @@
uc_pdata = dev_get_uclass_plat(dev);
+ if (uc_pdata->flags & REGULATOR_FLAG_AUTOSET_DONE)
+ return -EALREADY;
+
ret = regulator_set_suspend_enable(dev, uc_pdata->suspend_on);
if (ret == -ENOSYS)
ret = 0;
@@ -306,11 +309,15 @@
return ret;
}
- if (!uc_pdata->always_on && !uc_pdata->boot_on)
- return -EMEDIUMTYPE;
+ if (!uc_pdata->always_on && !uc_pdata->boot_on) {
+ ret = -EMEDIUMTYPE;
+ goto out;
+ }
- if (uc_pdata->type == REGULATOR_TYPE_FIXED)
- return regulator_set_enable(dev, true);
+ if (uc_pdata->type == REGULATOR_TYPE_FIXED) {
+ ret = regulator_set_enable(dev, true);
+ goto out;
+ }
if (uc_pdata->flags & REGULATOR_FLAG_AUTOSET_UV)
ret = regulator_set_value(dev, uc_pdata->min_uV);
@@ -322,6 +329,9 @@
if (!ret)
ret = regulator_set_enable(dev, true);
+out:
+ uc_pdata->flags |= REGULATOR_FLAG_AUTOSET_DONE;
+
return ret;
}
diff --git a/drivers/power/regulator/regulator_common.c b/drivers/power/regulator/regulator_common.c
index e26f5eb..0116fa0 100644
--- a/drivers/power/regulator/regulator_common.c
+++ b/drivers/power/regulator/regulator_common.c
@@ -7,8 +7,10 @@
#include <common.h>
#include <dm.h>
#include <log.h>
+#include <asm/gpio.h>
#include <linux/delay.h>
#include <power/regulator.h>
+#include "regulator_common.h"
#include "regulator_common.h"
diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c
index e95640a..e80bd6c 100644
--- a/drivers/power/regulator/rk8xx.c
+++ b/drivers/power/regulator/rk8xx.c
@@ -88,62 +88,63 @@
u8 config_reg;
u8 vsel_mask;
u8 min_sel;
+ u8 max_sel;
};
static const struct rk8xx_reg_info rk808_buck[] = {
- { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK808_BUCK_VSEL_MASK, },
- { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK808_BUCK_VSEL_MASK, },
- { 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK808_BUCK_VSEL_MASK, },
- { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK808_BUCK4_VSEL_MASK, },
+ { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK808_BUCK_VSEL_MASK, 0x00, 0x3f },
+ { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK808_BUCK_VSEL_MASK, 0x00, 0x3f },
+ { NA, NA, NA, NA, REG_BUCK3_CONFIG, NA, NA, NA },
+ { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK808_BUCK4_VSEL_MASK, 0x00, 0x0f },
};
static const struct rk8xx_reg_info rk816_buck[] = {
/* buck 1 */
- { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, },
- { 1800000, 200000, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, },
- { 2300000, 0, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, },
+ { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3b },
+ { 1800000, 200000, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, 0x3e },
+ { 2300000, 0, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, 0x3f },
/* buck 2 */
- { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, },
- { 1800000, 200000, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, },
- { 2300000, 0, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, },
+ { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3b },
+ { 1800000, 200000, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, 0x3e },
+ { 2300000, 0, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, 0x3f },
/* buck 3 */
- { 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK818_BUCK_VSEL_MASK, },
+ { NA, NA, NA, NA, REG_BUCK3_CONFIG, NA, NA, NA },
/* buck 4 */
- { 800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, },
+ { 800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, 0x00, 0x1f },
};
static const struct rk8xx_reg_info rk809_buck5[] = {
/* buck 5 */
- { 1500000, 0, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x00, },
- { 1800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x01, },
- { 2800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x04, },
- { 3300000, 300000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x06, },
+ { 1500000, 0, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x00, 0x00 },
+ { 1800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x01, 0x03 },
+ { 2800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x04, 0x05 },
+ { 3300000, 300000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x06, 0x07 },
};
static const struct rk8xx_reg_info rk817_buck[] = {
/* buck 1 */
- { 500000, 12500, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x00, },
- { 1500000, 100000, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x50, },
- { 2400000, 0, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x59, },
+ { 500000, 12500, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x00, 0x4f },
+ { 1500000, 100000, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x50, 0x58 },
+ { 2400000, 0, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x59, 0x7f },
/* buck 2 */
- { 500000, 12500, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x00, },
- { 1500000, 100000, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x50, },
- { 2400000, 0, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x59, },
+ { 500000, 12500, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x00, 0x4f },
+ { 1500000, 100000, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x50, 0x58 },
+ { 2400000, 0, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x59, 0x7f },
/* buck 3 */
- { 500000, 12500, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x00, },
- { 1500000, 100000, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x50, },
- { 2400000, 0, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x59, },
+ { 500000, 12500, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x00, 0x4f },
+ { 1500000, 100000, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x50, 0x58 },
+ { 2400000, 0, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x59, 0x7f },
/* buck 4 */
- { 500000, 12500, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x00, },
- { 1500000, 100000, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x50, },
- { 3400000, 0, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x63, },
+ { 500000, 12500, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x00, 0x4f },
+ { 1500000, 100000, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x50, 0x62 },
+ { 3400000, 0, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x63, 0x7f },
};
static const struct rk8xx_reg_info rk818_buck[] = {
- { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, },
- { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, },
- { 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK818_BUCK_VSEL_MASK, },
- { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, },
+ { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3f },
+ { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3f },
+ { NA, NA, NA, NA, REG_BUCK3_CONFIG, NA, NA, NA },
+ { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, 0x00, 0x1f },
};
#ifdef ENABLE_DRIVER
@@ -706,7 +707,6 @@
static int buck_get_value(struct udevice *dev)
{
int buck = dev->driver_data - 1;
- /* We assume level-1 voltage is enough for usage in U-Boot */
const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0);
int mask = info->vsel_mask;
int ret, val;
@@ -717,9 +717,12 @@
ret = pmic_reg_read(dev->parent, info->vsel_reg);
if (ret < 0)
return ret;
- val = ret & mask;
- return info->min_uv + val * info->step_uv;
+ val = ret & mask;
+ while (val > info->max_sel)
+ info++;
+
+ return info->min_uv + (val - info->min_sel) * info->step_uv;
}
static int buck_set_value(struct udevice *dev, int uvolt)
@@ -732,7 +735,6 @@
static int buck_get_suspend_value(struct udevice *dev)
{
int buck = dev->driver_data - 1;
- /* We assume level-1 voltage is enough for usage in U-Boot */
const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0);
int mask = info->vsel_mask;
int ret, val;
@@ -745,8 +747,10 @@
return ret;
val = ret & mask;
+ while (val > info->max_sel)
+ info++;
- return info->min_uv + val * info->step_uv;
+ return info->min_uv + (val - info->min_sel) * info->step_uv;
}
static int buck_set_suspend_value(struct udevice *dev, int uvolt)
@@ -1028,6 +1032,25 @@
*/
static int switch_get_value(struct udevice *dev)
{
+ static const char * const supply_name_rk809[] = {
+ "vcc9-supply",
+ "vcc8-supply",
+ };
+ struct rk8xx_priv *priv = dev_get_priv(dev->parent);
+ struct udevice *supply;
+ int id = dev->driver_data - 1;
+
+ if (!switch_get_enable(dev))
+ return 0;
+
+ if (priv->variant == RK809_ID) {
+ if (!uclass_get_device_by_phandle(UCLASS_REGULATOR,
+ dev->parent,
+ supply_name_rk809[id],
+ &supply))
+ return regulator_get_value(supply);
+ }
+
return 0;
}
diff --git a/drivers/power/regulator/s2mps11_regulator.c b/drivers/power/regulator/s2mps11_regulator.c
index 93fb580..987a1f9 100644
--- a/drivers/power/regulator/s2mps11_regulator.c
+++ b/drivers/power/regulator/s2mps11_regulator.c
@@ -9,6 +9,7 @@
#include <errno.h>
#include <dm.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <power/s2mps11.h>
diff --git a/drivers/power/regulator/sandbox.c b/drivers/power/regulator/sandbox.c
index e8b66bf..71ef0c5 100644
--- a/drivers/power/regulator/sandbox.c
+++ b/drivers/power/regulator/sandbox.c
@@ -8,6 +8,7 @@
#include <fdtdec.h>
#include <errno.h>
#include <dm.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <power/sandbox_pmic.h>
diff --git a/drivers/power/regulator/scmi_regulator.c b/drivers/power/regulator/scmi_regulator.c
index 8011480..9c72c35 100644
--- a/drivers/power/regulator/scmi_regulator.c
+++ b/drivers/power/regulator/scmi_regulator.c
@@ -25,18 +25,9 @@
u32 domain_id;
};
-/**
- * struct scmi_regulator_priv - Private data for SCMI voltage regulator
- * @channel: Reference to the SCMI channel to use
- */
-struct scmi_regulator_priv {
- struct scmi_channel *channel;
-};
-
static int scmi_voltd_set_enable(struct udevice *dev, bool enable)
{
struct scmi_regulator_platdata *pdata = dev_get_plat(dev);
- struct scmi_regulator_priv *priv = dev_get_priv(dev);
struct scmi_voltd_config_set_in in = {
.domain_id = pdata->domain_id,
.config = enable ? SCMI_VOLTD_CONFIG_ON : SCMI_VOLTD_CONFIG_OFF,
@@ -47,7 +38,7 @@
in, out);
int ret;
- ret = devm_scmi_process_msg(dev, priv->channel, &msg);
+ ret = devm_scmi_process_msg(dev, &msg);
if (ret)
return ret;
@@ -57,7 +48,6 @@
static int scmi_voltd_get_enable(struct udevice *dev)
{
struct scmi_regulator_platdata *pdata = dev_get_plat(dev);
- struct scmi_regulator_priv *priv = dev_get_priv(dev);
struct scmi_voltd_config_get_in in = {
.domain_id = pdata->domain_id,
};
@@ -67,7 +57,7 @@
in, out);
int ret;
- ret = devm_scmi_process_msg(dev, priv->channel, &msg);
+ ret = devm_scmi_process_msg(dev, &msg);
if (ret < 0)
return ret;
@@ -80,7 +70,6 @@
static int scmi_voltd_set_voltage_level(struct udevice *dev, int uV)
{
- struct scmi_regulator_priv *priv = dev_get_priv(dev);
struct scmi_regulator_platdata *pdata = dev_get_plat(dev);
struct scmi_voltd_level_set_in in = {
.domain_id = pdata->domain_id,
@@ -92,7 +81,7 @@
in, out);
int ret;
- ret = devm_scmi_process_msg(dev, priv->channel, &msg);
+ ret = devm_scmi_process_msg(dev, &msg);
if (ret < 0)
return ret;
@@ -101,7 +90,6 @@
static int scmi_voltd_get_voltage_level(struct udevice *dev)
{
- struct scmi_regulator_priv *priv = dev_get_priv(dev);
struct scmi_regulator_platdata *pdata = dev_get_plat(dev);
struct scmi_voltd_level_get_in in = {
.domain_id = pdata->domain_id,
@@ -112,7 +100,7 @@
in, out);
int ret;
- ret = devm_scmi_process_msg(dev, priv->channel, &msg);
+ ret = devm_scmi_process_msg(dev, &msg);
if (ret < 0)
return ret;
@@ -140,7 +128,6 @@
static int scmi_regulator_probe(struct udevice *dev)
{
struct scmi_regulator_platdata *pdata = dev_get_plat(dev);
- struct scmi_regulator_priv *priv = dev_get_priv(dev);
struct scmi_voltd_attr_in in = { 0 };
struct scmi_voltd_attr_out out = { 0 };
struct scmi_msg scmi_msg = {
@@ -153,14 +140,14 @@
};
int ret;
- ret = devm_scmi_of_get_channel(dev->parent, &priv->channel);
+ ret = devm_scmi_of_get_channel(dev);
if (ret)
return ret;
/* Check voltage domain is known from SCMI server */
in.domain_id = pdata->domain_id;
- ret = devm_scmi_process_msg(dev, priv->channel, &scmi_msg);
+ ret = devm_scmi_process_msg(dev, &scmi_msg);
if (ret) {
dev_err(dev, "Failed to query voltage domain %u: %d\n",
pdata->domain_id, ret);
@@ -184,7 +171,6 @@
.probe = scmi_regulator_probe,
.of_to_plat = scmi_regulator_of_to_plat,
.plat_auto = sizeof(struct scmi_regulator_platdata),
- .priv_auto = sizeof(struct scmi_regulator_priv *),
};
static int scmi_regulator_bind(struct udevice *dev)
diff --git a/drivers/power/regulator/tps62360_regulator.c b/drivers/power/regulator/tps62360_regulator.c
index b9f4504..7014b19 100644
--- a/drivers/power/regulator/tps62360_regulator.c
+++ b/drivers/power/regulator/tps62360_regulator.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* Tero Kristo <t-kristo@ti.com>
*/
diff --git a/drivers/power/regulator/tps65910_regulator.c b/drivers/power/regulator/tps65910_regulator.c
index 0ed4952..a4b9d44 100644
--- a/drivers/power/regulator/tps65910_regulator.c
+++ b/drivers/power/regulator/tps65910_regulator.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <dm.h>
#include <log.h>
+#include <linux/printk.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <power/tps65910_pmic.h>
diff --git a/drivers/power/regulator/tps65911_regulator.c b/drivers/power/regulator/tps65911_regulator.c
new file mode 100644
index 0000000..2b5acdf
--- /dev/null
+++ b/drivers/power/regulator/tps65911_regulator.c
@@ -0,0 +1,395 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/tps65910_pmic.h>
+
+/* fist row is control registers, second is voltage registers */
+static const char tps65911_vdd_reg[][TPS65911_VDD_NUM] = {
+ { TPS65911_REG_VDD1, TPS65911_REG_VDD2,
+ TPS65911_REG_VDDCTRL, TPS65911_REG_VIO },
+ { TPS65911_REG_VDD1_OP, TPS65911_REG_VDD2_OP,
+ TPS65911_REG_VDDCTRL_OP, 0x00 },
+};
+
+static const char tps65911_ldo_reg[TPS65911_LDO_NUM] = {
+ TPS65911_REG_LDO1, TPS65911_REG_LDO2, TPS65911_REG_LDO3,
+ TPS65911_REG_LDO4, TPS65911_REG_LDO5, TPS65911_REG_LDO6,
+ TPS65911_REG_LDO7, TPS65911_REG_LDO8
+};
+
+static int tps65911_regulator_enable(struct udevice *dev, int op, bool *enable)
+{
+ struct dm_regulator_uclass_plat *uc_pdata =
+ dev_get_uclass_plat(dev);
+ u32 adr = uc_pdata->ctrl_reg;
+ int val, ret;
+
+ val = pmic_reg_read(dev->parent, adr);
+ if (val < 0)
+ return val;
+
+ if (op == PMIC_OP_GET) {
+ if (val & TPS65910_SUPPLY_STATE_ON)
+ *enable = true;
+ else
+ *enable = false;
+
+ return 0;
+ } else if (op == PMIC_OP_SET) {
+ val &= ~TPS65910_SUPPLY_STATE_MASK;
+
+ if (*enable)
+ val |= TPS65910_SUPPLY_STATE_ON;
+
+ ret = pmic_reg_write(dev->parent, adr, val);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int tps65911_get_enable(struct udevice *dev)
+{
+ bool enable = false;
+ int ret;
+
+ ret = tps65911_regulator_enable(dev, PMIC_OP_GET, &enable);
+ if (ret)
+ return ret;
+
+ return enable;
+}
+
+static int tps65911_set_enable(struct udevice *dev, bool enable)
+{
+ return tps65911_regulator_enable(dev, PMIC_OP_SET, &enable);
+}
+
+/**
+ * tps65911_vdd_volt2hex() - convert voltage in uV into
+ * applicable to register hex value
+ *
+ * @uV: voltage in uV
+ *
+ * Return: voltage in hex on success, -ve on failure
+ */
+static int tps65911_vdd_volt2hex(int uV)
+{
+ if (uV > TPS65911_VDD_VOLT_MAX)
+ return -EINVAL;
+
+ if (uV < TPS65911_VDD_VOLT_MIN)
+ uV = TPS65911_VDD_VOLT_MIN;
+
+ return (uV - TPS65911_VDD_VOLT_BASE) / 12500;
+}
+
+/**
+ * tps65911_vdd_hex2volt() - convert register hex value into
+ * actual voltage in uV
+ *
+ * @hex: hex value of register
+ *
+ * Return: voltage in uV on success, -ve on failure
+ */
+static int tps65911_vdd_hex2volt(int hex)
+{
+ if (hex > TPS65910_VDD_SEL_MAX)
+ return -EINVAL;
+
+ if (hex < TPS65910_VDD_SEL_MIN)
+ hex = TPS65910_VDD_SEL_MIN;
+
+ return TPS65911_VDD_VOLT_BASE + hex * 12500;
+}
+
+static int tps65911_vio_range[4] = {
+ 1500000, 1800000, 2500000, 3300000
+};
+
+static int tps65911_vio_val(struct udevice *dev, int op, int *uV)
+{
+ struct dm_regulator_uclass_plat *uc_pdata =
+ dev_get_uclass_plat(dev);
+ u32 adr = uc_pdata->volt_reg;
+ int i, val;
+
+ val = pmic_reg_read(dev->parent, adr);
+ if (val < 0)
+ return val;
+
+ if (op == PMIC_OP_GET) {
+ *uV = 0;
+
+ val &= TPS65910_SEL_MASK;
+
+ *uV = tps65911_vio_range[val >> 2];
+
+ return 0;
+ }
+
+ val &= ~TPS65910_SEL_MASK;
+
+ for (i = 0; i < ARRAY_SIZE(tps65911_vio_range); i++)
+ if (*uV <= tps65911_vio_range[i])
+ break;
+
+ return pmic_reg_write(dev->parent, adr, val | i << 2);
+}
+
+static int tps65911_vdd_val(struct udevice *dev, int op, int *uV)
+{
+ struct dm_regulator_uclass_plat *uc_pdata =
+ dev_get_uclass_plat(dev);
+ u32 adr = uc_pdata->volt_reg;
+ int val, ret;
+
+ /* in case vdd is vio */
+ if (!adr)
+ return tps65911_vio_val(dev, op, uV);
+
+ val = pmic_reg_read(dev->parent, adr);
+ if (val < 0)
+ return val;
+
+ if (op == PMIC_OP_GET) {
+ *uV = 0;
+
+ ret = tps65911_vdd_hex2volt(val);
+ if (ret < 0)
+ return ret;
+
+ *uV = ret;
+ return 0;
+ }
+
+ val = tps65911_vdd_volt2hex(*uV);
+ if (val < 0)
+ return val;
+
+ return pmic_reg_write(dev->parent, adr, val);
+}
+
+static int tps65911_vdd_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_plat *uc_pdata =
+ dev_get_uclass_plat(dev);
+
+ uc_pdata->type = REGULATOR_TYPE_BUCK;
+
+ /* check for vddctrl and vddio cases */
+ if (!strcmp("vddctrl", dev->name)) {
+ uc_pdata->ctrl_reg = tps65911_vdd_reg[0][2];
+ uc_pdata->volt_reg = tps65911_vdd_reg[1][2];
+ return 0;
+ }
+
+ if (!strcmp("vddio", dev->name)) {
+ uc_pdata->ctrl_reg = tps65911_vdd_reg[0][3];
+ uc_pdata->volt_reg = tps65911_vdd_reg[1][3];
+ return 0;
+ }
+
+ if (dev->driver_data > 0) {
+ u8 idx = dev->driver_data - 1;
+
+ uc_pdata->ctrl_reg = tps65911_vdd_reg[0][idx];
+ uc_pdata->volt_reg = tps65911_vdd_reg[1][idx];
+ }
+
+ return 0;
+}
+
+static int vdd_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = tps65911_vdd_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+
+ return uV;
+}
+
+static int vdd_set_value(struct udevice *dev, int uV)
+{
+ return tps65911_vdd_val(dev, PMIC_OP_SET, &uV);
+}
+
+static const struct dm_regulator_ops tps65911_vdd_ops = {
+ .get_value = vdd_get_value,
+ .set_value = vdd_set_value,
+ .get_enable = tps65911_get_enable,
+ .set_enable = tps65911_set_enable,
+};
+
+U_BOOT_DRIVER(tps65911_vdd) = {
+ .name = TPS65911_VDD_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &tps65911_vdd_ops,
+ .probe = tps65911_vdd_probe,
+};
+
+/**
+ * tps65911_ldo_volt2hex() - convert voltage in uV into
+ * applicable to register hex value
+ *
+ * @idx: regulator index
+ * @uV: voltage in uV
+ *
+ * Return: voltage in hex on success, -ve on failure
+ */
+static int tps65911_ldo_volt2hex(int idx, int uV)
+{
+ int step;
+
+ if (uV > TPS65911_LDO_VOLT_MAX)
+ return -EINVAL;
+
+ if (uV < TPS65911_LDO_VOLT_BASE)
+ uV = TPS65911_LDO_VOLT_BASE;
+
+ switch (idx) {
+ case 1:
+ case 2:
+ case 4:
+ step = TPS65911_LDO124_VOLT_STEP;
+ break;
+ case 3:
+ case 5:
+ case 6:
+ case 7:
+ case 8:
+ step = TPS65911_LDO358_VOLT_STEP;
+ break;
+ default:
+ return -EINVAL;
+ };
+
+ return ((uV - TPS65911_LDO_VOLT_BASE) / step) << 2;
+}
+
+/**
+ * tps65911_ldo_hex2volt() - convert register hex value into
+ * actual voltage in uV
+ *
+ * @idx: regulator index
+ * @hex: hex value of register
+ *
+ * Return: voltage in uV on success, -ve on failure
+ */
+static int tps65911_ldo_hex2volt(int idx, int hex)
+{
+ int step;
+
+ switch (idx) {
+ case 1:
+ case 2:
+ case 4:
+ if (hex > TPS65911_LDO124_VOLT_MAX_HEX)
+ return -EINVAL;
+
+ step = TPS65911_LDO124_VOLT_STEP;
+ break;
+ case 3:
+ case 5:
+ case 6:
+ case 7:
+ case 8:
+ if (hex > TPS65911_LDO358_VOLT_MAX_HEX)
+ return -EINVAL;
+
+ if (hex < TPS65911_LDO358_VOLT_MIN_HEX)
+ hex = TPS65911_LDO358_VOLT_MIN_HEX;
+
+ step = TPS65911_LDO358_VOLT_STEP;
+ break;
+ default:
+ return -EINVAL;
+ };
+
+ return TPS65911_LDO_VOLT_BASE + hex * step;
+}
+
+static int tps65911_ldo_val(struct udevice *dev, int op, int *uV)
+{
+ struct dm_regulator_uclass_plat *uc_pdata =
+ dev_get_uclass_plat(dev);
+ u32 adr = uc_pdata->ctrl_reg;
+ int idx = dev->driver_data;
+ int val, hex, ret;
+
+ val = pmic_reg_read(dev->parent, adr);
+ if (val < 0)
+ return val;
+
+ if (op == PMIC_OP_GET) {
+ *uV = 0;
+ val &= TPS65911_LDO_SEL_MASK;
+
+ ret = tps65911_ldo_hex2volt(idx, val >> 2);
+ if (ret < 0)
+ return ret;
+
+ *uV = ret;
+ return 0;
+ }
+
+ hex = tps65911_ldo_volt2hex(idx, *uV);
+ if (hex < 0)
+ return hex;
+
+ val &= ~TPS65911_LDO_SEL_MASK;
+
+ return pmic_reg_write(dev->parent, adr, val | hex);
+}
+
+static int tps65911_ldo_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_plat *uc_pdata =
+ dev_get_uclass_plat(dev);
+ u8 idx = dev->driver_data - 1;
+
+ uc_pdata->type = REGULATOR_TYPE_LDO;
+ uc_pdata->ctrl_reg = tps65911_ldo_reg[idx];
+
+ return 0;
+}
+
+static int ldo_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = tps65911_ldo_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+
+ return uV;
+}
+
+static int ldo_set_value(struct udevice *dev, int uV)
+{
+ return tps65911_ldo_val(dev, PMIC_OP_SET, &uV);
+}
+
+static const struct dm_regulator_ops tps65911_ldo_ops = {
+ .get_value = ldo_get_value,
+ .set_value = ldo_set_value,
+ .get_enable = tps65911_get_enable,
+ .set_enable = tps65911_set_enable,
+};
+
+U_BOOT_DRIVER(tps65911_ldo) = {
+ .name = TPS65911_LDO_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &tps65911_ldo_ops,
+ .probe = tps65911_ldo_probe,
+};
diff --git a/drivers/power/regulator/tps80031_regulator.c b/drivers/power/regulator/tps80031_regulator.c
new file mode 100644
index 0000000..8769666
--- /dev/null
+++ b/drivers/power/regulator/tps80031_regulator.c
@@ -0,0 +1,347 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/tps80031.h>
+
+static const char tps80031_smps_reg[][TPS80031_SMPS_NUM] = {
+ { 0x54, 0x5a, 0x66, 0x42, 0x48 },
+ { 0x56, 0x5c, 0x68, 0x44, 0x4a },
+ { BIT(3), BIT(4), BIT(6), BIT(0), BIT(1) },
+};
+
+static const char tps80031_ldo_reg[][TPS80031_LDO_NUM] = {
+ { 0x9e, 0x86, 0x8e, 0x8a, 0x9a, 0x92, 0xa6, 0x96, 0xa2 },
+ { 0x9f, 0x87, 0x8f, 0x8b, 0x9b, 0x93, 0xa7, 0x97, 0xa3 },
+};
+
+static int tps80031_regulator_enable(struct udevice *dev, int op, bool *enable)
+{
+ struct dm_regulator_uclass_plat *uc_pdata =
+ dev_get_uclass_plat(dev);
+ u32 adr = uc_pdata->ctrl_reg;
+ int val, ret;
+
+ val = pmic_reg_read(dev->parent, adr);
+ if (val < 0)
+ return val;
+
+ if (op == PMIC_OP_GET) {
+ if (val & REGULATOR_MODE_ON)
+ *enable = true;
+ else
+ *enable = false;
+
+ return 0;
+ } else if (op == PMIC_OP_SET) {
+ val &= ~REGULATOR_STATUS_MASK;
+
+ if (*enable)
+ val |= REGULATOR_MODE_ON;
+
+ ret = pmic_reg_write(dev->parent, adr, val);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int tps80031_get_enable(struct udevice *dev)
+{
+ bool enable = false;
+ int ret;
+
+ ret = tps80031_regulator_enable(dev, PMIC_OP_GET, &enable);
+ if (ret)
+ return ret;
+
+ return enable;
+}
+
+static int tps80031_set_enable(struct udevice *dev, bool enable)
+{
+ return tps80031_regulator_enable(dev, PMIC_OP_SET, &enable);
+}
+
+/**
+ * tps80031_ldo_volt2hex() - convert voltage in uV into
+ * applicable to register hex value
+ *
+ * @uV: voltage in uV
+ *
+ * Return: voltage in hex on success, -ve on failure
+ */
+static int tps80031_ldo_volt2hex(int uV)
+{
+ if (uV > LDO_VOLT_MAX)
+ return -EINVAL;
+
+ if (uV < LDO_VOLT_MIN)
+ uV = LDO_VOLT_MIN;
+
+ return DIV_ROUND_UP(uV - LDO_VOLT_BASE, 102000);
+}
+
+/**
+ * tps80031_ldo_hex2volt() - convert register hex value into
+ * actual voltage in uV
+ *
+ * @hex: hex value of register
+ *
+ * Return: voltage in uV on success, -ve on failure
+ */
+static int tps80031_ldo_hex2volt(int hex)
+{
+ if (hex > LDO_VOLT_MAX_HEX)
+ return -EINVAL;
+
+ if (hex < LDO_VOLT_MIN_HEX)
+ hex = LDO_VOLT_MIN_HEX;
+
+ return LDO_VOLT_BASE + hex * 102000;
+}
+
+static int tps80031_ldo_val(struct udevice *dev, int op, int *uV)
+{
+ struct dm_regulator_uclass_plat *uc_pdata =
+ dev_get_uclass_plat(dev);
+ u32 adr = uc_pdata->volt_reg;
+ int val, hex, ret;
+
+ val = pmic_reg_read(dev->parent, adr);
+ if (val < 0)
+ return val;
+
+ if (op == PMIC_OP_GET) {
+ *uV = 0;
+
+ ret = tps80031_ldo_hex2volt(val & LDO_VOLT_MASK);
+ if (ret < 0)
+ return ret;
+
+ *uV = ret;
+ return 0;
+ }
+
+ hex = tps80031_ldo_volt2hex(*uV);
+ if (hex < 0)
+ return hex;
+
+ val &= ~LDO_VOLT_MASK;
+
+ return pmic_reg_write(dev->parent, adr, val | hex);
+}
+
+static int tps80031_ldo_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_plat *uc_pdata =
+ dev_get_uclass_plat(dev);
+
+ uc_pdata->type = REGULATOR_TYPE_LDO;
+
+ /* check for ldoln and ldousb cases */
+ if (!strcmp("ldoln", dev->name)) {
+ uc_pdata->ctrl_reg = tps80031_ldo_reg[CTRL][7];
+ uc_pdata->volt_reg = tps80031_ldo_reg[VOLT][7];
+ return 0;
+ }
+
+ if (!strcmp("ldousb", dev->name)) {
+ uc_pdata->ctrl_reg = tps80031_ldo_reg[CTRL][8];
+ uc_pdata->volt_reg = tps80031_ldo_reg[VOLT][8];
+ return 0;
+ }
+
+ if (dev->driver_data > 0) {
+ u8 idx = dev->driver_data - 1;
+
+ uc_pdata->ctrl_reg = tps80031_ldo_reg[CTRL][idx];
+ uc_pdata->volt_reg = tps80031_ldo_reg[VOLT][idx];
+ }
+
+ return 0;
+}
+
+static int ldo_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = tps80031_ldo_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+
+ return uV;
+}
+
+static int ldo_set_value(struct udevice *dev, int uV)
+{
+ return tps80031_ldo_val(dev, PMIC_OP_SET, &uV);
+}
+
+static const struct dm_regulator_ops tps80031_ldo_ops = {
+ .get_value = ldo_get_value,
+ .set_value = ldo_set_value,
+ .get_enable = tps80031_get_enable,
+ .set_enable = tps80031_set_enable,
+};
+
+U_BOOT_DRIVER(tps80031_ldo) = {
+ .name = TPS80031_LDO_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &tps80031_ldo_ops,
+ .probe = tps80031_ldo_probe,
+};
+
+struct tps80031_smps_priv {
+ int flags;
+};
+
+/* DCDC voltages for the selector of 0x39 to 0x3F */
+static int tps80031_dcdc_voltages[5] = {
+ 1350000, 1500000, 1800000, 1900000, 2100000
+};
+
+/**
+ * tps80031_smps_volt2hex() - convert voltage in uV into
+ * applicable to register hex value
+ *
+ * @base: base voltage in uV
+ * @uV: voltage in uV
+ *
+ * Return: voltage in hex on success, -ve on failure
+ */
+static int tps80031_smps_volt2hex(u32 base, int uV)
+{
+ int i;
+
+ if (uV < base)
+ return 1;
+
+ if (uV > SMPS_VOLT_LINEAR) {
+ for (i = 0; i < ARRAY_SIZE(tps80031_dcdc_voltages); i++)
+ if (uV <= tps80031_dcdc_voltages[i])
+ break;
+
+ return SMPS_VOLT_NLINEAR_HEX + i;
+ }
+
+ return DIV_ROUND_UP(uV - base, 12500);
+}
+
+/**
+ * tps80031_smps_hex2volt() - convert register hex value into
+ * actual voltage in uV
+ *
+ * @base: base voltage in uV
+ * @hex: hex value of register
+ *
+ * Return: voltage in uV on success, -ve on failure
+ */
+static int tps80031_smps_hex2volt(u32 base, int hex)
+{
+ if (!hex)
+ return 0;
+
+ /* if reg value exceeds linear scale use table */
+ if (hex > SMPS_VOLT_LINEAR_HEX)
+ return tps80031_dcdc_voltages[hex - SMPS_VOLT_LINEAR_HEX];
+ else
+ return base + hex * 12500;
+}
+
+static int tps80031_smps_val(struct udevice *dev, int op, int *uV)
+{
+ struct dm_regulator_uclass_plat *uc_pdata =
+ dev_get_uclass_plat(dev);
+ struct tps80031_smps_priv *priv = dev_get_priv(dev);
+ u32 adr = uc_pdata->volt_reg;
+ int base, val, hex, ret;
+
+ /* If offset flag was set then base voltage is higher */
+ if (priv->flags & TPS80031_OFFSET_FLAG)
+ base = SMPS_VOLT_BASE_OFFSET;
+ else
+ base = SMPS_VOLT_BASE;
+
+ val = pmic_reg_read(dev->parent, adr);
+ if (val < 0)
+ return val;
+
+ if (op == PMIC_OP_GET) {
+ *uV = 0;
+
+ ret = tps80031_smps_hex2volt(base, val & SMPS_VOLT_MASK);
+ if (ret < 0)
+ return ret;
+
+ *uV = ret;
+ return 0;
+ }
+
+ hex = tps80031_smps_volt2hex(base, *uV);
+ if (hex < 0)
+ return hex;
+
+ val &= ~SMPS_VOLT_MASK;
+
+ return pmic_reg_write(dev->parent, adr, val | hex);
+}
+
+static int tps80031_smps_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_plat *uc_pdata =
+ dev_get_uclass_plat(dev);
+ struct tps80031_smps_priv *priv = dev_get_priv(dev);
+ int idx = dev->driver_data - 1;
+ int val;
+
+ uc_pdata->type = REGULATOR_TYPE_BUCK;
+
+ uc_pdata->ctrl_reg = tps80031_smps_reg[CTRL][idx];
+ uc_pdata->volt_reg = tps80031_smps_reg[VOLT][idx];
+
+ /* Determine if smps regulator uses higher voltage */
+ val = pmic_reg_read(dev->parent, TPS80031_SMPS_OFFSET);
+ if (val & tps80031_smps_reg[OFFSET][idx])
+ priv->flags |= TPS80031_OFFSET_FLAG;
+
+ return 0;
+}
+
+static int smps_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = tps80031_smps_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+
+ return uV;
+}
+
+static int smps_set_value(struct udevice *dev, int uV)
+{
+ return tps80031_smps_val(dev, PMIC_OP_SET, &uV);
+}
+
+static const struct dm_regulator_ops tps80031_smps_ops = {
+ .get_value = smps_get_value,
+ .set_value = smps_set_value,
+ .get_enable = tps80031_get_enable,
+ .set_enable = tps80031_set_enable,
+};
+
+U_BOOT_DRIVER(tps80031_smps) = {
+ .name = TPS80031_SMPS_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &tps80031_smps_ops,
+ .probe = tps80031_smps_probe,
+ .priv_auto = sizeof(struct tps80031_smps_priv),
+};
diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c
index d3e8949..0c7c396 100644
--- a/drivers/power/twl4030.c
+++ b/drivers/power/twl4030.c
@@ -25,6 +25,7 @@
#include <command.h>
#include <twl4030.h>
#include <linux/delay.h>
+#include <linux/printk.h>
/*
* Power Reset
diff --git a/drivers/power/twl6030.c b/drivers/power/twl6030.c
index 2b50a56..39c05f9 100644
--- a/drivers/power/twl6030.c
+++ b/drivers/power/twl6030.c
@@ -5,6 +5,7 @@
*/
#include <config.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <twl6030.h>
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index bf99964..5b07e92 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -109,8 +109,9 @@
source "drivers/ram/aspeed/Kconfig"
source "drivers/ram/cadence/Kconfig"
+source "drivers/ram/octeon/Kconfig"
source "drivers/ram/rockchip/Kconfig"
source "drivers/ram/sifive/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
-source "drivers/ram/octeon/Kconfig"
source "drivers/ram/starfive/Kconfig"
+source "drivers/ram/sunxi/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 6eb1a24..985990a 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -23,6 +23,9 @@
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive/
endif
+
+obj-$(CONFIG_DRAM_SUN20I_D1) += sunxi/
+
obj-$(CONFIG_ARCH_OCTEON) += octeon/
obj-$(CONFIG_ARCH_RMOBILE) += renesas/
diff --git a/drivers/ram/imxrt_sdram.c b/drivers/ram/imxrt_sdram.c
index d0a8884..6a15242 100644
--- a/drivers/ram/imxrt_sdram.c
+++ b/drivers/ram/imxrt_sdram.c
@@ -15,6 +15,7 @@
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
+#include <linux/printk.h>
/* SDRAM Command Code */
#define SD_CC_ARD 0x0 /* Master Bus (AXI) command - Read */
diff --git a/drivers/ram/k3-am654-ddrss.c b/drivers/ram/k3-am654-ddrss.c
index b8338f8..cff8ffc 100644
--- a/drivers/ram/k3-am654-ddrss.c
+++ b/drivers/ram/k3-am654-ddrss.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments' AM654 DDRSS driver
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
@@ -903,7 +903,7 @@
static int am654_ddrss_ofdata_to_priv(struct udevice *dev)
{
struct am654_ddrss_desc *ddrss = dev_get_priv(dev);
- phys_addr_t reg;
+ void *reg;
int ret;
debug("%s(dev=%p)\n", __func__, dev);
@@ -926,26 +926,26 @@
return ret;
}
- reg = devfdt_get_addr_name(dev, "ss");
- if (reg == FDT_ADDR_T_NONE) {
+ reg = dev_read_addr_name_ptr(dev, "ss");
+ if (!reg) {
dev_err(dev, "No reg property for DDRSS wrapper logic\n");
return -EINVAL;
}
- ddrss->ddrss_ss_cfg = (void *)reg;
+ ddrss->ddrss_ss_cfg = reg;
- reg = devfdt_get_addr_name(dev, "ctl");
- if (reg == FDT_ADDR_T_NONE) {
+ reg = dev_read_addr_name_ptr(dev, "ctl");
+ if (!reg) {
dev_err(dev, "No reg property for Controller region\n");
return -EINVAL;
}
- ddrss->ddrss_ctl_cfg = (void *)reg;
+ ddrss->ddrss_ctl_cfg = reg;
- reg = devfdt_get_addr_name(dev, "phy");
- if (reg == FDT_ADDR_T_NONE) {
+ reg = dev_read_addr_name_ptr(dev, "phy");
+ if (!reg) {
dev_err(dev, "No reg property for PHY region\n");
return -EINVAL;
}
- ddrss->ddrss_phy_cfg = (void *)reg;
+ ddrss->ddrss_phy_cfg = reg;
ret = dev_read_u32_array(dev, "ti,ss-reg",
(u32 *)&ddrss->params.ss_reg,
diff --git a/drivers/ram/k3-am654-ddrss.h b/drivers/ram/k3-am654-ddrss.h
index c87f186..9d03ae1 100644
--- a/drivers/ram/k3-am654-ddrss.h
+++ b/drivers/ram/k3-am654-ddrss.h
@@ -2,7 +2,7 @@
/*
* AM654: DDRSS Register definitions and structures.
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*
*/
diff --git a/drivers/ram/k3-ddrss/Makefile b/drivers/ram/k3-ddrss/Makefile
index ba5d9a2..823d188 100644
--- a/drivers/ram/k3-ddrss/Makefile
+++ b/drivers/ram/k3-ddrss/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2019-2022 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/
#
obj-$(CONFIG_K3_DDRSS) += k3-ddrss.o
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index b54557f..a5c9b82 100644
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments' K3 DDRSS driver
*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
@@ -331,32 +331,29 @@
{
struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
struct k3_ddrss_data *ddrss_data = (struct k3_ddrss_data *)dev_get_driver_data(dev);
- phys_addr_t reg;
+ void *reg;
int ret;
debug("%s(dev=%p)\n", __func__, dev);
- reg = dev_read_addr_name(dev, "cfg");
- if (reg == FDT_ADDR_T_NONE) {
+ reg = dev_read_addr_name_ptr(dev, "cfg");
+ if (!reg) {
dev_err(dev, "No reg property for DDRSS wrapper logic\n");
return -EINVAL;
}
- ddrss->ddrss_ctl_cfg = (void *)reg;
+ ddrss->ddrss_ctl_cfg = reg;
- reg = dev_read_addr_name(dev, "ctrl_mmr_lp4");
- if (reg == FDT_ADDR_T_NONE) {
+ reg = dev_read_addr_name_ptr(dev, "ctrl_mmr_lp4");
+ if (!reg) {
dev_err(dev, "No reg property for CTRL MMR\n");
return -EINVAL;
}
- ddrss->ddrss_ctrl_mmr = (void *)reg;
+ ddrss->ddrss_ctrl_mmr = reg;
- reg = dev_read_addr_name(dev, "ss_cfg");
- if (reg == FDT_ADDR_T_NONE) {
+ reg = dev_read_addr_name_ptr(dev, "ss_cfg");
+ if (!reg)
dev_dbg(dev, "No reg property for SS Config region, but this is optional so continuing.\n");
- ddrss->ddrss_ss_cfg = NULL;
- } else {
- ddrss->ddrss_ss_cfg = (void *)reg;
- }
+ ddrss->ddrss_ss_cfg = reg;
ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
if (ret) {
diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c
index dd5b191..f36be94 100644
--- a/drivers/ram/rockchip/dmc-rk3368.c
+++ b/drivers/ram/rockchip/dmc-rk3368.c
@@ -23,6 +23,7 @@
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
+#include <linux/printk.h>
struct dram_info {
struct ram_info info;
diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c
index 47a930e..891f413 100644
--- a/drivers/ram/stm32_sdram.c
+++ b/drivers/ram/stm32_sdram.c
@@ -16,6 +16,7 @@
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#define MEM_MODE_MASK GENMASK(2, 0)
#define SWP_FMC_OFFSET 10
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c
index ab913a6..8ee4e24 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ddr.c
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c
@@ -16,6 +16,7 @@
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
+#include <linux/printk.h>
#include "stm32mp1_ddr.h"
#include "stm32mp1_ddr_regs.h"
diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c
index a6c19af..a82b1db 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ram.c
+++ b/drivers/ram/stm32mp1/stm32mp1_ram.c
@@ -15,6 +15,7 @@
#include <syscon.h>
#include <asm/io.h>
#include <dm/device_compat.h>
+#include <linux/printk.h>
#include "stm32mp1_ddr.h"
#include "stm32mp1_ddr_regs.h"
@@ -126,7 +127,8 @@
dev_dbg(dev, "no st,mem-name\n");
return -EINVAL;
}
- printf("RAM: %s\n", config.info.name);
+ if (CONFIG_IS_ENABLED(DISPLAY_PRINT))
+ printf("RAM: %s\n", config.info.name);
for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
ret = ofnode_read_u32_array(node, param[idx].name,
diff --git a/drivers/ram/sunxi/Kconfig b/drivers/ram/sunxi/Kconfig
new file mode 100644
index 0000000..1775cb0
--- /dev/null
+++ b/drivers/ram/sunxi/Kconfig
@@ -0,0 +1,60 @@
+config DRAM_SUN20I_D1
+ bool
+ depends on ARCH_SUNXI
+ help
+ This enables support for the DRAM controller driver covering
+ the Allwinner D1/R528/T113s SoCs.
+
+if DRAM_SUN20I_D1
+
+config DRAM_SUNXI_ODT_EN
+ hex "DRAM ODT EN parameter"
+ help
+ ODT EN value from vendor DRAM settings.
+
+config DRAM_SUNXI_TPR0
+ hex "DRAM TPR0 parameter"
+ help
+ TPR0 value from vendor DRAM settings.
+
+config DRAM_SUNXI_TPR11
+ hex "DRAM TPR11 parameter"
+ help
+ TPR11 value from vendor DRAM settings.
+
+config DRAM_SUNXI_TPR12
+ hex "DRAM TPR12 parameter"
+ help
+ TPR12 value from vendor DRAM settings.
+
+config DRAM_SUNXI_TPR13
+ hex "DRAM TPR13 parameter"
+ help
+ TPR13 value from vendor DRAM settings. It tells which features
+ should be configured.
+
+choice
+ prompt "DRAM chip type"
+ default SUNXI_DRAM_TYPE_DDR3 if DRAM_SUN20I_D1
+
+config SUNXI_DRAM_TYPE_DDR2
+ bool "DDR2 chips"
+
+config SUNXI_DRAM_TYPE_DDR3
+ bool "DDR3 chips"
+
+config SUNXI_DRAM_TYPE_LPDDR2
+ bool "LPDDR2 chips"
+
+config SUNXI_DRAM_TYPE_LPDDR3
+ bool "LPDDR3 chips"
+endchoice
+
+config SUNXI_DRAM_TYPE
+ int
+ default 2 if SUNXI_DRAM_TYPE_DDR2
+ default 3 if SUNXI_DRAM_TYPE_DDR3
+ default 6 if SUNXI_DRAM_TYPE_LPDDR2
+ default 7 if SUNXI_DRAM_TYPE_LPDDR3
+
+endif
diff --git a/drivers/ram/sunxi/Makefile b/drivers/ram/sunxi/Makefile
new file mode 100644
index 0000000..86ea0b9
--- /dev/null
+++ b/drivers/ram/sunxi/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_DRAM_SUN20I_D1) += dram_sun20i_d1.o
diff --git a/drivers/ram/sunxi/dram_sun20i_d1.c b/drivers/ram/sunxi/dram_sun20i_d1.c
new file mode 100644
index 0000000..3837928
--- /dev/null
+++ b/drivers/ram/sunxi/dram_sun20i_d1.c
@@ -0,0 +1,1441 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Allwinner D1/D1s/R528/T113-sx DRAM initialisation
+ *
+ * As usual there is no documentation for the memory controller or PHY IP
+ * used here. The baseline of this code was lifted from awboot[1], which
+ * seems to be based on some form of de-compilation of some original Allwinner
+ * code bits (with a GPL2 license tag from the very beginning).
+ * This version here is a reworked version, to match the U-Boot coding style
+ * and style of the other Allwinner DRAM drivers.
+ *
+ * [1] https://github.com/szemzoa/awboot.git
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#ifdef CONFIG_RAM
+ #include <dm.h>
+ #include <ram.h>
+#endif
+#include <linux/delay.h>
+
+#include "dram_sun20i_d1.h"
+
+#ifndef SUNXI_SID_BASE
+#define SUNXI_SID_BASE 0x3006200
+#endif
+
+#ifndef SUNXI_CCM_BASE
+#define SUNXI_CCM_BASE 0x2001000
+#endif
+
+static void sid_read_ldoB_cal(const dram_para_t *para)
+{
+ uint32_t reg;
+
+ reg = (readl(SUNXI_SID_BASE + 0x1c) & 0xff00) >> 8;
+
+ if (reg == 0)
+ return;
+
+ switch (para->dram_type) {
+ case SUNXI_DRAM_TYPE_DDR2:
+ break;
+ case SUNXI_DRAM_TYPE_DDR3:
+ if (reg > 0x20)
+ reg -= 0x16;
+ break;
+ default:
+ reg = 0;
+ break;
+ }
+
+ clrsetbits_le32(0x3000150, 0xff00, reg << 8);
+}
+
+static void dram_voltage_set(const dram_para_t *para)
+{
+ int vol;
+
+ switch (para->dram_type) {
+ case SUNXI_DRAM_TYPE_DDR2:
+ vol = 47;
+ break;
+ case SUNXI_DRAM_TYPE_DDR3:
+ vol = 25;
+ break;
+ default:
+ vol = 0;
+ break;
+ }
+
+ clrsetbits_le32(0x3000150, 0x20ff00, vol << 8);
+
+ udelay(1);
+
+ sid_read_ldoB_cal(para);
+}
+
+static void dram_enable_all_master(void)
+{
+ writel(~0, 0x3102020);
+ writel(0xff, 0x3102024);
+ writel(0xffff, 0x3102028);
+ udelay(10);
+}
+
+static void dram_disable_all_master(void)
+{
+ writel(1, 0x3102020);
+ writel(0, 0x3102024);
+ writel(0, 0x3102028);
+ udelay(10);
+}
+
+static void eye_delay_compensation(const dram_para_t *para)
+{
+ uint32_t delay;
+ unsigned long ptr;
+
+ // DATn0IOCR, n = 0...7
+ delay = (para->dram_tpr11 & 0xf) << 9;
+ delay |= (para->dram_tpr12 & 0xf) << 1;
+ for (ptr = 0x3103310; ptr < 0x3103334; ptr += 4)
+ setbits_le32(ptr, delay);
+
+ // DATn1IOCR, n = 0...7
+ delay = (para->dram_tpr11 & 0xf0) << 5;
+ delay |= (para->dram_tpr12 & 0xf0) >> 3;
+ for (ptr = 0x3103390; ptr != 0x31033b4; ptr += 4)
+ setbits_le32(ptr, delay);
+
+ // PGCR0: assert AC loopback FIFO reset
+ clrbits_le32(0x3103100, 0x04000000);
+
+ // ??
+
+ delay = (para->dram_tpr11 & 0xf0000) >> 7;
+ delay |= (para->dram_tpr12 & 0xf0000) >> 15;
+ setbits_le32(0x3103334, delay);
+ setbits_le32(0x3103338, delay);
+
+ delay = (para->dram_tpr11 & 0xf00000) >> 11;
+ delay |= (para->dram_tpr12 & 0xf00000) >> 19;
+ setbits_le32(0x31033b4, delay);
+ setbits_le32(0x31033b8, delay);
+
+ setbits_le32(0x310333c, (para->dram_tpr11 & 0xf0000) << 9);
+ setbits_le32(0x31033bc, (para->dram_tpr11 & 0xf00000) << 5);
+
+ // PGCR0: release AC loopback FIFO reset
+ setbits_le32(0x3103100, BIT(26));
+
+ udelay(1);
+
+ delay = (para->dram_tpr10 & 0xf0) << 4;
+ for (ptr = 0x3103240; ptr != 0x310327c; ptr += 4)
+ setbits_le32(ptr, delay);
+ for (ptr = 0x3103228; ptr != 0x3103240; ptr += 4)
+ setbits_le32(ptr, delay);
+
+ setbits_le32(0x3103218, (para->dram_tpr10 & 0x0f) << 8);
+ setbits_le32(0x310321c, (para->dram_tpr10 & 0x0f) << 8);
+
+ setbits_le32(0x3103280, (para->dram_tpr10 & 0xf00) >> 4);
+}
+
+/*
+ * Main purpose of the auto_set_timing routine seems to be to calculate all
+ * timing settings for the specific type of sdram used. Read together with
+ * an sdram datasheet for context on the various variables.
+ */
+static void mctl_set_timing_params(const dram_para_t *para,
+ const dram_config_t *config)
+{
+ /* DRAM_TPR0 */
+ u8 tccd = 2;
+ u8 tfaw;
+ u8 trrd;
+ u8 trcd;
+ u8 trc;
+
+ /* DRAM_TPR1 */
+ u8 txp;
+ u8 twtr;
+ u8 trtp = 4;
+ u8 twr;
+ u8 trp;
+ u8 tras;
+
+ /* DRAM_TPR2 */
+ u16 trefi;
+ u16 trfc;
+
+ u8 tcksrx;
+ u8 tckesr;
+ u8 trd2wr;
+ u8 twr2rd;
+ u8 trasmax;
+ u8 twtp;
+ u8 tcke;
+ u8 tmod;
+ u8 tmrd;
+ u8 tmrw;
+
+ u8 tcl;
+ u8 tcwl;
+ u8 t_rdata_en;
+ u8 wr_latency;
+
+ u32 mr0;
+ u32 mr1;
+ u32 mr2;
+ u32 mr3;
+
+ u32 tdinit0;
+ u32 tdinit1;
+ u32 tdinit2;
+ u32 tdinit3;
+
+ switch (para->dram_type) {
+ case SUNXI_DRAM_TYPE_DDR2:
+ /* DRAM_TPR0 */
+ tfaw = ns_to_t(50);
+ trrd = ns_to_t(10);
+ trcd = ns_to_t(20);
+ trc = ns_to_t(65);
+
+ /* DRAM_TPR1 */
+ txp = 2;
+ twtr = ns_to_t(8);
+ twr = ns_to_t(15);
+ trp = ns_to_t(15);
+ tras = ns_to_t(45);
+
+ /* DRAM_TRP2 */
+ trfc = ns_to_t(328);
+ trefi = ns_to_t(7800) / 32;
+
+ trasmax = CONFIG_DRAM_CLK / 30;
+ if (CONFIG_DRAM_CLK < 409) {
+ t_rdata_en = 1;
+ tcl = 3;
+ mr0 = 0x06a3;
+ } else {
+ t_rdata_en = 2;
+ tcl = 4;
+ mr0 = 0x0e73;
+ }
+ tmrd = 2;
+ twtp = twr + 5;
+ tcksrx = 5;
+ tckesr = 4;
+ trd2wr = 4;
+ tcke = 3;
+ tmod = 12;
+ wr_latency = 1;
+ tmrw = 0;
+ twr2rd = twtr + 5;
+ tcwl = 0;
+
+ mr1 = para->dram_mr1;
+ mr2 = 0;
+ mr3 = 0;
+
+ tdinit0 = 200 * CONFIG_DRAM_CLK + 1;
+ tdinit1 = 100 * CONFIG_DRAM_CLK / 1000 + 1;
+ tdinit2 = 200 * CONFIG_DRAM_CLK + 1;
+ tdinit3 = 1 * CONFIG_DRAM_CLK + 1;
+
+ break;
+ case SUNXI_DRAM_TYPE_DDR3:
+ trfc = ns_to_t(350);
+ trefi = ns_to_t(7800) / 32 + 1; // XXX
+
+ twtr = ns_to_t(8) + 2; // + 2 ? XXX
+ /* Only used by trd2wr calculation, which gets discard below */
+// twr = max(ns_to_t(15), 2);
+ trrd = max(ns_to_t(10), 2);
+ txp = max(ns_to_t(10), 2);
+
+ if (CONFIG_DRAM_CLK <= 800) {
+ tfaw = ns_to_t(50);
+ trcd = ns_to_t(15);
+ trp = ns_to_t(15);
+ trc = ns_to_t(53);
+ tras = ns_to_t(38);
+
+ mr0 = 0x1c70;
+ mr2 = 0x18;
+ tcl = 6;
+ wr_latency = 2;
+ tcwl = 4;
+ t_rdata_en = 4;
+ } else {
+ tfaw = ns_to_t(35);
+ trcd = ns_to_t(14);
+ trp = ns_to_t(14);
+ trc = ns_to_t(48);
+ tras = ns_to_t(34);
+
+ mr0 = 0x1e14;
+ mr2 = 0x20;
+ tcl = 7;
+ wr_latency = 3;
+ tcwl = 5;
+ t_rdata_en = 5;
+ }
+
+ trasmax = CONFIG_DRAM_CLK / 30;
+ twtp = tcwl + 2 + twtr; // WL+BL/2+tWTR
+ /* Gets overwritten below */
+// trd2wr = tcwl + 2 + twr; // WL+BL/2+tWR
+ twr2rd = tcwl + twtr; // WL+tWTR
+
+ tdinit0 = 500 * CONFIG_DRAM_CLK + 1; // 500 us
+ tdinit1 = 360 * CONFIG_DRAM_CLK / 1000 + 1; // 360 ns
+ tdinit2 = 200 * CONFIG_DRAM_CLK + 1; // 200 us
+ tdinit3 = 1 * CONFIG_DRAM_CLK + 1; // 1 us
+
+ mr1 = para->dram_mr1;
+ mr3 = 0;
+ tcke = 3;
+ tcksrx = 5;
+ tckesr = 4;
+ if (((config->dram_tpr13 & 0xc) == 0x04) || CONFIG_DRAM_CLK < 912)
+ trd2wr = 5;
+ else
+ trd2wr = 6;
+
+ tmod = 12;
+ tmrd = 4;
+ tmrw = 0;
+
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR2:
+ tfaw = max(ns_to_t(50), 4);
+ trrd = max(ns_to_t(10), 1);
+ trcd = max(ns_to_t(24), 2);
+ trc = ns_to_t(70);
+ txp = ns_to_t(8);
+ if (txp < 2) {
+ txp++;
+ twtr = 2;
+ } else {
+ twtr = txp;
+ }
+ twr = max(ns_to_t(15), 2);
+ trp = ns_to_t(17);
+ tras = ns_to_t(42);
+ trefi = ns_to_t(3900) / 32;
+ trfc = ns_to_t(210);
+
+ trasmax = CONFIG_DRAM_CLK / 60;
+ mr3 = para->dram_mr3;
+ twtp = twr + 5;
+ mr2 = 6;
+ mr1 = 5;
+ tcksrx = 5;
+ tckesr = 5;
+ trd2wr = 10;
+ tcke = 2;
+ tmod = 5;
+ tmrd = 5;
+ tmrw = 3;
+ tcl = 4;
+ wr_latency = 1;
+ t_rdata_en = 1;
+
+ tdinit0 = 200 * CONFIG_DRAM_CLK + 1;
+ tdinit1 = 100 * CONFIG_DRAM_CLK / 1000 + 1;
+ tdinit2 = 11 * CONFIG_DRAM_CLK + 1;
+ tdinit3 = 1 * CONFIG_DRAM_CLK + 1;
+ twr2rd = twtr + 5;
+ tcwl = 2;
+ mr1 = 195;
+ mr0 = 0;
+
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR3:
+ tfaw = max(ns_to_t(50), 4);
+ trrd = max(ns_to_t(10), 1);
+ trcd = max(ns_to_t(24), 2);
+ trc = ns_to_t(70);
+ twtr = max(ns_to_t(8), 2);
+ twr = max(ns_to_t(15), 2);
+ trp = ns_to_t(17);
+ tras = ns_to_t(42);
+ trefi = ns_to_t(3900) / 32;
+ trfc = ns_to_t(210);
+ txp = twtr;
+
+ trasmax = CONFIG_DRAM_CLK / 60;
+ if (CONFIG_DRAM_CLK < 800) {
+ tcwl = 4;
+ wr_latency = 3;
+ t_rdata_en = 6;
+ mr2 = 12;
+ } else {
+ tcwl = 3;
+ tcke = 6;
+ wr_latency = 2;
+ t_rdata_en = 5;
+ mr2 = 10;
+ }
+ twtp = tcwl + 5;
+ tcl = 7;
+ mr3 = para->dram_mr3;
+ tcksrx = 5;
+ tckesr = 5;
+ trd2wr = 13;
+ tcke = 3;
+ tmod = 12;
+ tdinit0 = 400 * CONFIG_DRAM_CLK + 1;
+ tdinit1 = 500 * CONFIG_DRAM_CLK / 1000 + 1;
+ tdinit2 = 11 * CONFIG_DRAM_CLK + 1;
+ tdinit3 = 1 * CONFIG_DRAM_CLK + 1;
+ tmrd = 5;
+ tmrw = 5;
+ twr2rd = tcwl + twtr + 5;
+ mr1 = 195;
+ mr0 = 0;
+
+ break;
+ default:
+ trfc = 128;
+ trp = 6;
+ trefi = 98;
+ txp = 10;
+ twr = 8;
+ twtr = 3;
+ tras = 14;
+ tfaw = 16;
+ trc = 20;
+ trcd = 6;
+ trrd = 3;
+
+ twr2rd = 8;
+ tcksrx = 4;
+ tckesr = 3;
+ trd2wr = 4;
+ trasmax = 27;
+ twtp = 12;
+ tcke = 2;
+ tmod = 6;
+ tmrd = 2;
+ tmrw = 0;
+ tcwl = 3;
+ tcl = 3;
+ wr_latency = 1;
+ t_rdata_en = 1;
+ mr3 = 0;
+ mr2 = 0;
+ mr1 = 0;
+ mr0 = 0;
+ tdinit3 = 0;
+ tdinit2 = 0;
+ tdinit1 = 0;
+ tdinit0 = 0;
+
+ break;
+ }
+
+ /* Set mode registers */
+ writel(mr0, 0x3103030);
+ writel(mr1, 0x3103034);
+ writel(mr2, 0x3103038);
+ writel(mr3, 0x310303c);
+ /* TODO: dram_odt_en is either 0x0 or 0x1, so right shift looks weird */
+ writel((para->dram_odt_en >> 4) & 0x3, 0x310302c);
+
+ /* Set dram timing DRAMTMG0 - DRAMTMG5 */
+ writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0),
+ 0x3103058);
+ writel((txp << 16) | (trtp << 8) | (trc << 0),
+ 0x310305c);
+ writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0),
+ 0x3103060);
+ writel((tmrw << 16) | (tmrd << 12) | (tmod << 0),
+ 0x3103064);
+ writel((trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0),
+ 0x3103068);
+ writel((tcksrx << 24) | (tcksrx << 16) | (tckesr << 8) | (tcke << 0),
+ 0x310306c);
+
+ /* Set dual rank timing */
+ clrsetbits_le32(0x3103078, 0xf000ffff,
+ (CONFIG_DRAM_CLK < 800) ? 0xf0006610 : 0xf0007610);
+
+ /* Set phy interface time PITMG0, PTR3, PTR4 */
+ writel((0x2 << 24) | (t_rdata_en << 16) | BIT(8) | (wr_latency << 0),
+ 0x3103080);
+ writel(((tdinit0 << 0) | (tdinit1 << 20)), 0x3103050);
+ writel(((tdinit2 << 0) | (tdinit3 << 20)), 0x3103054);
+
+ /* Set refresh timing and mode */
+ writel((trefi << 16) | (trfc << 0), 0x3103090);
+ writel((trefi << 15) & 0x0fff0000, 0x3103094);
+}
+
+// Purpose of this routine seems to be to initialize the PLL driving
+// the MBUS and sdram.
+//
+static int ccu_set_pll_ddr_clk(int index, const dram_para_t *para,
+ const dram_config_t *config)
+{
+ unsigned int val, clk, n;
+
+ if (config->dram_tpr13 & BIT(6))
+ clk = para->dram_tpr9;
+ else
+ clk = para->dram_clk;
+
+ // set VCO clock divider
+ n = (clk * 2) / 24;
+
+ val = readl(SUNXI_CCM_BASE + 0x10);
+ val &= ~0x0007ff03; // clear dividers
+ val |= (n - 1) << 8; // set PLL division
+ val |= BIT(31) | BIT(30); // enable PLL and LDO
+ writel(val | BIT(29), SUNXI_CCM_BASE + 0x10);
+
+ // wait for PLL to lock
+ while ((readl(SUNXI_CCM_BASE + 0x10) & BIT(28)) == 0)
+ ;
+
+ udelay(20);
+
+ // enable PLL output
+ setbits_le32(SUNXI_CCM_BASE + 0x0, BIT(27));
+
+ // turn clock gate on
+ val = readl(SUNXI_CCM_BASE + 0x800);
+ val &= ~0x03000303; // select DDR clk source, n=1, m=1
+ val |= BIT(31); // turn clock on
+ writel(val, SUNXI_CCM_BASE + 0x800);
+
+ return n * 24;
+}
+
+/* Set up the PLL and clock gates for the DRAM controller and MBUS clocks. */
+static void mctl_sys_init(const dram_para_t *para, const dram_config_t *config)
+{
+ // assert MBUS reset
+ clrbits_le32(SUNXI_CCM_BASE + 0x540, BIT(30));
+
+ // turn off sdram clock gate, assert sdram reset
+ clrbits_le32(SUNXI_CCM_BASE + 0x80c, 0x10001);
+ clrsetbits_le32(SUNXI_CCM_BASE + 0x800, BIT(31) | BIT(30), BIT(27));
+ udelay(10);
+
+ // set ddr pll clock
+ ccu_set_pll_ddr_clk(0, para, config);
+ udelay(100);
+ dram_disable_all_master();
+
+ // release sdram reset
+ setbits_le32(SUNXI_CCM_BASE + 0x80c, BIT(16));
+
+ // release MBUS reset
+ setbits_le32(SUNXI_CCM_BASE + 0x540, BIT(30));
+ setbits_le32(SUNXI_CCM_BASE + 0x800, BIT(30));
+
+ udelay(5);
+
+ // turn on sdram clock gate
+ setbits_le32(SUNXI_CCM_BASE + 0x80c, BIT(0));
+
+ // turn dram clock gate on, trigger sdr clock update
+ setbits_le32(SUNXI_CCM_BASE + 0x800, BIT(31) | BIT(27));
+ udelay(5);
+
+ // mCTL clock enable
+ writel(0x8000, 0x310300c);
+ udelay(10);
+}
+
+// The main purpose of this routine seems to be to copy an address configuration
+// from the dram_para1 and dram_para2 fields to the PHY configuration registers
+// (0x3102000, 0x3102004).
+//
+static void mctl_com_init(const dram_para_t *para, const dram_config_t *config)
+{
+ uint32_t val, width;
+ unsigned long ptr;
+ int i;
+
+ // purpose ??
+ clrsetbits_le32(0x3102008, 0x3f00, 0x2000);
+
+ // set SDRAM type and word width
+ val = readl(0x3102000) & ~0x00fff000;
+ val |= (para->dram_type & 0x7) << 16; // DRAM type
+ val |= (~config->dram_para2 & 0x1) << 12; // DQ width
+ val |= BIT(22); // ??
+ if (para->dram_type == SUNXI_DRAM_TYPE_LPDDR2 ||
+ para->dram_type == SUNXI_DRAM_TYPE_LPDDR3) {
+ val |= BIT(19); // type 6 and 7 must use 1T
+ } else {
+ if (config->dram_tpr13 & BIT(5))
+ val |= BIT(19);
+ }
+ writel(val, 0x3102000);
+
+ // init rank / bank / row for single/dual or two different ranks
+ if ((config->dram_para2 & BIT(8)) &&
+ ((config->dram_para2 & 0xf000) != 0x1000))
+ width = 32;
+ else
+ width = 16;
+
+ ptr = 0x3102000;
+ for (i = 0; i < width; i += 16) {
+ val = readl(ptr) & 0xfffff000;
+
+ val |= (config->dram_para2 >> 12) & 0x3; // rank
+ val |= ((config->dram_para1 >> (i + 12)) << 2) & 0x4; // bank - 2
+ val |= (((config->dram_para1 >> (i + 4)) - 1) << 4) & 0xff; // row - 1
+
+ // convert from page size to column addr width - 3
+ switch ((config->dram_para1 >> i) & 0xf) {
+ case 8: val |= 0xa00; break;
+ case 4: val |= 0x900; break;
+ case 2: val |= 0x800; break;
+ case 1: val |= 0x700; break;
+ default: val |= 0x600; break;
+ }
+ writel(val, ptr);
+ ptr += 4;
+ }
+
+ // set ODTMAP based on number of ranks in use
+ val = (readl(0x3102000) & 0x1) ? 0x303 : 0x201;
+ writel(val, 0x3103120);
+
+ // set mctl reg 3c4 to zero when using half DQ
+ if (config->dram_para2 & BIT(0))
+ writel(0, 0x31033c4);
+
+ // purpose ??
+ if (para->dram_tpr4) {
+ setbits_le32(0x3102000, (para->dram_tpr4 & 0x3) << 25);
+ setbits_le32(0x3102004, (para->dram_tpr4 & 0x7fc) << 10);
+ }
+}
+
+static const uint8_t ac_remapping_tables[][22] = {
+ [0] = { 0 },
+ [1] = { 1, 9, 3, 7, 8, 18, 4, 13, 5, 6, 10,
+ 2, 14, 12, 0, 0, 21, 17, 20, 19, 11, 22 },
+ [2] = { 4, 9, 3, 7, 8, 18, 1, 13, 2, 6, 10,
+ 5, 14, 12, 0, 0, 21, 17, 20, 19, 11, 22 },
+ [3] = { 1, 7, 8, 12, 10, 18, 4, 13, 5, 6, 3,
+ 2, 9, 0, 0, 0, 21, 17, 20, 19, 11, 22 },
+ [4] = { 4, 12, 10, 7, 8, 18, 1, 13, 2, 6, 3,
+ 5, 9, 0, 0, 0, 21, 17, 20, 19, 11, 22 },
+ [5] = { 13, 2, 7, 9, 12, 19, 5, 1, 6, 3, 4,
+ 8, 10, 0, 0, 0, 21, 22, 18, 17, 11, 20 },
+ [6] = { 3, 10, 7, 13, 9, 11, 1, 2, 4, 6, 8,
+ 5, 12, 0, 0, 0, 20, 1, 0, 21, 22, 17 },
+ [7] = { 3, 2, 4, 7, 9, 1, 17, 12, 18, 14, 13,
+ 8, 15, 6, 10, 5, 19, 22, 16, 21, 20, 11 },
+};
+
+/*
+ * This routine chooses one of several remapping tables for 22 lines.
+ * It is unclear which lines are being remapped. It seems to pick
+ * table cfg7 for the Nezha board.
+ */
+static void mctl_phy_ac_remapping(const dram_para_t *para,
+ const dram_config_t *config)
+{
+ const uint8_t *cfg;
+ uint32_t fuse, val;
+
+ /*
+ * It is unclear whether the LPDDRx types don't need any remapping,
+ * or whether the original code just didn't provide tables.
+ */
+ if (para->dram_type != SUNXI_DRAM_TYPE_DDR2 &&
+ para->dram_type != SUNXI_DRAM_TYPE_DDR3)
+ return;
+
+ fuse = (readl(SUNXI_SID_BASE + 0x28) & 0xf00) >> 8;
+ debug("DDR efuse: 0x%x\n", fuse);
+
+ if (para->dram_type == SUNXI_DRAM_TYPE_DDR2) {
+ if (fuse == 15)
+ return;
+ cfg = ac_remapping_tables[6];
+ } else {
+ if (config->dram_tpr13 & 0xc0000) {
+ cfg = ac_remapping_tables[7];
+ } else {
+ switch (fuse) {
+ case 8: cfg = ac_remapping_tables[2]; break;
+ case 9: cfg = ac_remapping_tables[3]; break;
+ case 10: cfg = ac_remapping_tables[5]; break;
+ case 11: cfg = ac_remapping_tables[4]; break;
+ default:
+ case 12: cfg = ac_remapping_tables[1]; break;
+ case 13:
+ case 14: cfg = ac_remapping_tables[0]; break;
+ }
+ }
+ }
+
+ val = (cfg[4] << 25) | (cfg[3] << 20) | (cfg[2] << 15) |
+ (cfg[1] << 10) | (cfg[0] << 5);
+ writel(val, 0x3102500);
+
+ val = (cfg[10] << 25) | (cfg[9] << 20) | (cfg[8] << 15) |
+ (cfg[ 7] << 10) | (cfg[6] << 5) | cfg[5];
+ writel(val, 0x3102504);
+
+ val = (cfg[15] << 20) | (cfg[14] << 15) | (cfg[13] << 10) |
+ (cfg[12] << 5) | cfg[11];
+ writel(val, 0x3102508);
+
+ val = (cfg[21] << 25) | (cfg[20] << 20) | (cfg[19] << 15) |
+ (cfg[18] << 10) | (cfg[17] << 5) | cfg[16];
+ writel(val, 0x310250c);
+
+ val = (cfg[4] << 25) | (cfg[3] << 20) | (cfg[2] << 15) |
+ (cfg[1] << 10) | (cfg[0] << 5) | 1;
+ writel(val, 0x3102500);
+}
+
+// Init the controller channel. The key part is placing commands in the main
+// command register (PIR, 0x3103000) and checking command status (PGSR0, 0x3103010).
+//
+static unsigned int mctl_channel_init(unsigned int ch_index,
+ const dram_para_t *para,
+ const dram_config_t *config)
+{
+ unsigned int val, dqs_gating_mode;
+
+ dqs_gating_mode = (config->dram_tpr13 & 0xc) >> 2;
+
+ // set DDR clock to half of CPU clock
+ clrsetbits_le32(0x310200c, 0xfff, (para->dram_clk / 2) - 1);
+
+ // MRCTRL0 nibble 3 undocumented
+ clrsetbits_le32(0x3103108, 0xf00, 0x300);
+
+ if (para->dram_odt_en)
+ val = 0;
+ else
+ val = BIT(5);
+
+ // DX0GCR0
+ if (para->dram_clk > 672)
+ clrsetbits_le32(0x3103344, 0xf63e, val);
+ else
+ clrsetbits_le32(0x3103344, 0xf03e, val);
+
+ // DX1GCR0
+ if (para->dram_clk > 672) {
+ setbits_le32(0x3103344, 0x400);
+ clrsetbits_le32(0x31033c4, 0xf63e, val);
+ } else {
+ clrsetbits_le32(0x31033c4, 0xf03e, val);
+ }
+
+ // 0x3103208 undocumented
+ setbits_le32(0x3103208, BIT(1));
+
+ eye_delay_compensation(para);
+
+ // set PLL SSCG ?
+ val = readl(0x3103108);
+ if (dqs_gating_mode == 1) {
+ clrsetbits_le32(0x3103108, 0xc0, 0);
+ clrbits_le32(0x31030bc, 0x107);
+ } else if (dqs_gating_mode == 2) {
+ clrsetbits_le32(0x3103108, 0xc0, 0x80);
+
+ clrsetbits_le32(0x31030bc, 0x107,
+ (((config->dram_tpr13 >> 16) & 0x1f) - 2) | 0x100);
+ clrsetbits_le32(0x310311c, BIT(31), BIT(27));
+ } else {
+ clrbits_le32(0x3103108, 0x40);
+ udelay(10);
+ setbits_le32(0x3103108, 0xc0);
+ }
+
+ if (para->dram_type == SUNXI_DRAM_TYPE_LPDDR2 ||
+ para->dram_type == SUNXI_DRAM_TYPE_LPDDR3) {
+ if (dqs_gating_mode == 1)
+ clrsetbits_le32(0x310311c, 0x080000c0, 0x80000000);
+ else
+ clrsetbits_le32(0x310311c, 0x77000000, 0x22000000);
+ }
+
+ clrsetbits_le32(0x31030c0, 0x0fffffff,
+ (config->dram_para2 & BIT(12)) ? 0x03000001 : 0x01000007);
+
+ if (readl(0x70005d4) & BIT(16)) {
+ clrbits_le32(0x7010250, 0x2);
+ udelay(10);
+ }
+
+ // Set ZQ config
+ clrsetbits_le32(0x3103140, 0x3ffffff,
+ (para->dram_zq & 0x00ffffff) | BIT(25));
+
+ // Initialise DRAM controller
+ if (dqs_gating_mode == 1) {
+ //writel(0x52, 0x3103000); // prep PHY reset + PLL init + z-cal
+ writel(0x53, 0x3103000); // Go
+
+ while ((readl(0x3103010) & 0x1) == 0) {
+ } // wait for IDONE
+ udelay(10);
+
+ // 0x520 = prep DQS gating + DRAM init + d-cal
+ if (para->dram_type == SUNXI_DRAM_TYPE_DDR3)
+ writel(0x5a0, 0x3103000); // + DRAM reset
+ else
+ writel(0x520, 0x3103000);
+ } else {
+ if ((readl(0x70005d4) & (1 << 16)) == 0) {
+ // prep DRAM init + PHY reset + d-cal + PLL init + z-cal
+ if (para->dram_type == SUNXI_DRAM_TYPE_DDR3)
+ writel(0x1f2, 0x3103000); // + DRAM reset
+ else
+ writel(0x172, 0x3103000);
+ } else {
+ // prep PHY reset + d-cal + z-cal
+ writel(0x62, 0x3103000);
+ }
+ }
+
+ setbits_le32(0x3103000, 0x1); // GO
+
+ udelay(10);
+ while ((readl(0x3103010) & 0x1) == 0) {
+ } // wait for IDONE
+
+ if (readl(0x70005d4) & BIT(16)) {
+ clrsetbits_le32(0x310310c, 0x06000000, 0x04000000);
+ udelay(10);
+
+ setbits_le32(0x3103004, 0x1);
+
+ while ((readl(0x3103018) & 0x7) != 0x3) {
+ }
+
+ clrbits_le32(0x7010250, 0x1);
+ udelay(10);
+
+ clrbits_le32(0x3103004, 0x1);
+
+ while ((readl(0x3103018) & 0x7) != 0x1) {
+ }
+
+ udelay(15);
+
+ if (dqs_gating_mode == 1) {
+ clrbits_le32(0x3103108, 0xc0);
+ clrsetbits_le32(0x310310c, 0x06000000, 0x02000000);
+ udelay(1);
+ writel(0x401, 0x3103000);
+
+ while ((readl(0x3103010) & 0x1) == 0) {
+ }
+ }
+ }
+
+ // Check for training error
+ if (readl(0x3103010) & BIT(20)) {
+ printf("ZQ calibration error, check external 240 ohm resistor\n");
+ return 0;
+ }
+
+ // STATR = Zynq STAT? Wait for status 'normal'?
+ while ((readl(0x3103018) & 0x1) == 0) {
+ }
+
+ setbits_le32(0x310308c, BIT(31));
+ udelay(10);
+ clrbits_le32(0x310308c, BIT(31));
+ udelay(10);
+ setbits_le32(0x3102014, BIT(31));
+ udelay(10);
+
+ clrbits_le32(0x310310c, 0x06000000);
+
+ if (dqs_gating_mode == 1)
+ clrsetbits_le32(0x310311c, 0xc0, 0x40);
+
+ return 1;
+}
+
+static unsigned int calculate_rank_size(uint32_t regval)
+{
+ unsigned int bits;
+
+ bits = (regval >> 8) & 0xf; /* page size - 3 */
+ bits += (regval >> 4) & 0xf; /* row width - 1 */
+ bits += (regval >> 2) & 0x3; /* bank count - 2 */
+ bits -= 14; /* 1MB = 20 bits, minus above 6 = 14 */
+
+ return 1U << bits;
+}
+
+/*
+ * The below routine reads the dram config registers and extracts
+ * the number of address bits in each rank available. It then calculates
+ * total memory size in MB.
+ */
+static unsigned int DRAMC_get_dram_size(void)
+{
+ uint32_t val;
+ unsigned int size;
+
+ val = readl(0x3102000); /* MC_WORK_MODE0 */
+ size = calculate_rank_size(val);
+ if ((val & 0x3) == 0) /* single rank? */
+ return size;
+
+ val = readl(0x3102004); /* MC_WORK_MODE1 */
+ if ((val & 0x3) == 0) /* two identical ranks? */
+ return size * 2;
+
+ /* add sizes of both ranks */
+ return size + calculate_rank_size(val);
+}
+
+/*
+ * The below routine reads the command status register to extract
+ * DQ width and rank count. This follows the DQS training command in
+ * channel_init. If error bit 22 is reset, we have two ranks and full DQ.
+ * If there was an error, figure out whether it was half DQ, single rank,
+ * or both. Set bit 12 and 0 in dram_para2 with the results.
+ */
+static int dqs_gate_detect(dram_config_t *config)
+{
+ uint32_t dx0, dx1;
+
+ if ((readl(0x3103010) & BIT(22)) == 0) {
+ config->dram_para2 = (config->dram_para2 & ~0xf) | BIT(12);
+ debug("dual rank and full DQ\n");
+
+ return 1;
+ }
+
+ dx0 = (readl(0x3103348) & 0x3000000) >> 24;
+ if (dx0 == 0) {
+ config->dram_para2 = (config->dram_para2 & ~0xf) | 0x1001;
+ debug("dual rank and half DQ\n");
+
+ return 1;
+ }
+
+ if (dx0 == 2) {
+ dx1 = (readl(0x31033c8) & 0x3000000) >> 24;
+ if (dx1 == 2) {
+ config->dram_para2 = config->dram_para2 & ~0xf00f;
+ debug("single rank and full DQ\n");
+ } else {
+ config->dram_para2 = (config->dram_para2 & ~0xf00f) | BIT(0);
+ debug("single rank and half DQ\n");
+ }
+
+ return 1;
+ }
+
+ if ((config->dram_tpr13 & BIT(29)) == 0)
+ return 0;
+
+ debug("DX0 state: %d\n", dx0);
+ debug("DX1 state: %d\n", dx1);
+
+ return 0;
+}
+
+static int dramc_simple_wr_test(unsigned int mem_mb, int len)
+{
+ unsigned int offs = (mem_mb / 2) << 18; // half of memory size
+ unsigned int patt1 = 0x01234567;
+ unsigned int patt2 = 0xfedcba98;
+ unsigned int *addr, v1, v2, i;
+
+ addr = (unsigned int *)CFG_SYS_SDRAM_BASE;
+ for (i = 0; i != len; i++, addr++) {
+ writel(patt1 + i, (unsigned long)addr);
+ writel(patt2 + i, (unsigned long)(addr + offs));
+ }
+
+ addr = (unsigned int *)CFG_SYS_SDRAM_BASE;
+ for (i = 0; i != len; i++) {
+ v1 = readl((unsigned long)(addr + i));
+ v2 = patt1 + i;
+ if (v1 != v2) {
+ printf("DRAM: simple test FAIL\n");
+ printf("%x != %x at address %p\n", v1, v2, addr + i);
+ return 1;
+ }
+ v1 = readl((unsigned long)(addr + offs + i));
+ v2 = patt2 + i;
+ if (v1 != v2) {
+ printf("DRAM: simple test FAIL\n");
+ printf("%x != %x at address %p\n", v1, v2, addr + offs + i);
+ return 1;
+ }
+ }
+
+ debug("DRAM: simple test OK\n");
+ return 0;
+}
+
+// Set the Vref mode for the controller
+//
+static void mctl_vrefzq_init(const dram_para_t *para, const dram_config_t *config)
+{
+ if (config->dram_tpr13 & BIT(17))
+ return;
+
+ clrsetbits_le32(0x3103110, 0x7f7f7f7f, para->dram_tpr5);
+
+ // IOCVR1
+ if ((config->dram_tpr13 & BIT(16)) == 0)
+ clrsetbits_le32(0x3103114, 0x7f, para->dram_tpr6 & 0x7f);
+}
+
+// Perform an init of the controller. This is actually done 3 times. The first
+// time to establish the number of ranks and DQ width. The second time to
+// establish the actual ram size. The third time is final one, with the final
+// settings.
+//
+static int mctl_core_init(const dram_para_t *para, const dram_config_t *config)
+{
+ mctl_sys_init(para, config);
+
+ mctl_vrefzq_init(para, config);
+
+ mctl_com_init(para, config);
+
+ mctl_phy_ac_remapping(para, config);
+
+ mctl_set_timing_params(para, config);
+
+ return mctl_channel_init(0, para, config);
+}
+
+/*
+ * This routine sizes a DRAM device by cycling through address lines and
+ * figuring out if they are connected to a real address line, or if the
+ * address is a mirror.
+ * First the column and bank bit allocations are set to low values (2 and 9
+ * address lines). Then a maximum allocation (16 lines) is set for rows and
+ * this is tested.
+ * Next the BA2 line is checked. This seems to be placed above the column,
+ * BA0-1 and row addresses. Finally, the column address is allocated 13 lines
+ * and these are tested. The results are placed in dram_para1 and dram_para2.
+ */
+
+static uint32_t get_payload(bool odd, unsigned long int ptr)
+{
+ if (odd)
+ return (uint32_t)ptr;
+ else
+ return ~((uint32_t)ptr);
+}
+
+static int auto_scan_dram_size(const dram_para_t *para, dram_config_t *config)
+{
+ unsigned int rval, i, j, rank, maxrank, offs;
+ unsigned int shft;
+ unsigned long ptr, mc_work_mode, chk;
+
+ if (mctl_core_init(para, config) == 0) {
+ printf("DRAM initialisation error : 0\n");
+ return 0;
+ }
+
+ maxrank = (config->dram_para2 & 0xf000) ? 2 : 1;
+ mc_work_mode = 0x3102000;
+ offs = 0;
+
+ /* write test pattern */
+ for (i = 0, ptr = CFG_SYS_SDRAM_BASE; i < 64; i++, ptr += 4)
+ writel(get_payload(i & 0x1, ptr), ptr);
+
+ for (rank = 0; rank < maxrank;) {
+ /* set row mode */
+ clrsetbits_le32(mc_work_mode, 0xf0c, 0x6f0);
+ udelay(1);
+
+ // Scan per address line, until address wraps (i.e. see shadow)
+ for (i = 11; i < 17; i++) {
+ chk = CFG_SYS_SDRAM_BASE + (1U << (i + 11));
+ ptr = CFG_SYS_SDRAM_BASE;
+ for (j = 0; j < 64; j++) {
+ if (readl(chk) != get_payload(j & 0x1, ptr))
+ break;
+ ptr += 4;
+ chk += 4;
+ }
+ if (j == 64)
+ break;
+ }
+ if (i > 16)
+ i = 16;
+ debug("rank %d row = %d\n", rank, i);
+
+ /* Store rows in para 1 */
+ shft = offs + 4;
+ rval = config->dram_para1;
+ rval &= ~(0xff << shft);
+ rval |= i << shft;
+ config->dram_para1 = rval;
+
+ if (rank == 1) /* Set bank mode for rank0 */
+ clrsetbits_le32(0x3102000, 0xffc, 0x6a4);
+
+ /* Set bank mode for current rank */
+ clrsetbits_le32(mc_work_mode, 0xffc, 0x6a4);
+ udelay(1);
+
+ // Test if bit A23 is BA2 or mirror XXX A22?
+ chk = CFG_SYS_SDRAM_BASE + (1U << 22);
+ ptr = CFG_SYS_SDRAM_BASE;
+ for (i = 0, j = 0; i < 64; i++) {
+ if (readl(chk) != get_payload(i & 1, ptr)) {
+ j = 1;
+ break;
+ }
+ ptr += 4;
+ chk += 4;
+ }
+
+ debug("rank %d bank = %d\n", rank, (j + 1) << 2); /* 4 or 8 */
+
+ /* Store banks in para 1 */
+ shft = 12 + offs;
+ rval = config->dram_para1;
+ rval &= ~(0xf << shft);
+ rval |= j << shft;
+ config->dram_para1 = rval;
+
+ if (rank == 1) /* Set page mode for rank0 */
+ clrsetbits_le32(0x3102000, 0xffc, 0xaa0);
+
+ /* Set page mode for current rank */
+ clrsetbits_le32(mc_work_mode, 0xffc, 0xaa0);
+ udelay(1);
+
+ // Scan per address line, until address wraps (i.e. see shadow)
+ for (i = 9; i < 14; i++) {
+ chk = CFG_SYS_SDRAM_BASE + (1U << i);
+ ptr = CFG_SYS_SDRAM_BASE;
+ for (j = 0; j < 64; j++) {
+ if (readl(chk) != get_payload(j & 1, ptr))
+ break;
+ ptr += 4;
+ chk += 4;
+ }
+ if (j == 64)
+ break;
+ }
+ if (i > 13)
+ i = 13;
+
+ unsigned int pgsize = (i == 9) ? 0 : (1 << (i - 10));
+ debug("rank %d page size = %d KB\n", rank, pgsize);
+
+ /* Store page size */
+ shft = offs;
+ rval = config->dram_para1;
+ rval &= ~(0xf << shft);
+ rval |= pgsize << shft;
+ config->dram_para1 = rval;
+
+ // Move to next rank
+ rank++;
+ if (rank != maxrank) {
+ if (rank == 1) {
+ /* MC_WORK_MODE */
+ clrsetbits_le32(0x3202000, 0xffc, 0x6f0);
+
+ /* MC_WORK_MODE2 */
+ clrsetbits_le32(0x3202004, 0xffc, 0x6f0);
+ }
+ /* store rank1 config in upper half of para1 */
+ offs += 16;
+ mc_work_mode += 4; /* move to MC_WORK_MODE2 */
+ }
+ }
+ if (maxrank == 2) {
+ config->dram_para2 &= 0xfffff0ff;
+ /* note: rval is equal to para->dram_para1 here */
+ if ((rval & 0xffff) == (rval >> 16)) {
+ debug("rank1 config same as rank0\n");
+ } else {
+ config->dram_para2 |= BIT(8);
+ debug("rank1 config different from rank0\n");
+ }
+ }
+
+ return 1;
+}
+
+/*
+ * This routine sets up parameters with dqs_gating_mode equal to 1 and two
+ * ranks enabled. It then configures the core and tests for 1 or 2 ranks and
+ * full or half DQ width. It then resets the parameters to the original values.
+ * dram_para2 is updated with the rank and width findings.
+ */
+static int auto_scan_dram_rank_width(const dram_para_t *para,
+ dram_config_t *config)
+{
+ unsigned int s1 = config->dram_tpr13;
+ unsigned int s2 = config->dram_para1;
+
+ config->dram_para1 = 0x00b000b0;
+ config->dram_para2 = (config->dram_para2 & ~0xf) | BIT(12);
+
+ /* set DQS probe mode */
+ config->dram_tpr13 = (config->dram_tpr13 & ~0x8) | BIT(2) | BIT(0);
+
+ mctl_core_init(para, config);
+
+ if (readl(0x3103010) & BIT(20))
+ return 0;
+
+ if (dqs_gate_detect(config) == 0)
+ return 0;
+
+ config->dram_tpr13 = s1;
+ config->dram_para1 = s2;
+
+ return 1;
+}
+
+/*
+ * This routine determines the SDRAM topology. It first establishes the number
+ * of ranks and the DQ width. Then it scans the SDRAM address lines to establish
+ * the size of each rank. It then updates dram_tpr13 to reflect that the sizes
+ * are now known: a re-init will not repeat the autoscan.
+ */
+static int auto_scan_dram_config(const dram_para_t *para,
+ dram_config_t *config)
+{
+ if (((config->dram_tpr13 & BIT(14)) == 0) &&
+ (auto_scan_dram_rank_width(para, config) == 0)) {
+ printf("ERROR: auto scan dram rank & width failed\n");
+ return 0;
+ }
+
+ if (((config->dram_tpr13 & BIT(0)) == 0) &&
+ (auto_scan_dram_size(para, config) == 0)) {
+ printf("ERROR: auto scan dram size failed\n");
+ return 0;
+ }
+
+ if ((config->dram_tpr13 & BIT(15)) == 0)
+ config->dram_tpr13 |= BIT(14) | BIT(13) | BIT(1) | BIT(0);
+
+ return 1;
+}
+
+static int init_DRAM(int type, const dram_para_t *para)
+{
+ dram_config_t config = {
+ .dram_para1 = 0x000010d2,
+ .dram_para2 = 0,
+ .dram_tpr13 = CONFIG_DRAM_SUNXI_TPR13,
+ };
+ u32 rc, mem_size_mb;
+
+ debug("DRAM BOOT DRIVE INFO: %s\n", "V0.24");
+ debug("DRAM CLK = %d MHz\n", para->dram_clk);
+ debug("DRAM Type = %d (2:DDR2,3:DDR3)\n", para->dram_type);
+ if ((para->dram_odt_en & 0x1) == 0)
+ debug("DRAMC read ODT off\n");
+ else
+ debug("DRAMC ZQ value: 0x%x\n", para->dram_zq);
+
+ /* Test ZQ status */
+ if (config.dram_tpr13 & BIT(16)) {
+ debug("DRAM only have internal ZQ\n");
+ setbits_le32(0x3000160, BIT(8));
+ writel(0, 0x3000168);
+ udelay(10);
+ } else {
+ clrbits_le32(0x3000160, 0x3);
+ writel(config.dram_tpr13 & BIT(16), 0x7010254);
+ udelay(10);
+ clrsetbits_le32(0x3000160, 0x108, BIT(1));
+ udelay(10);
+ setbits_le32(0x3000160, BIT(0));
+ udelay(20);
+ debug("ZQ value = 0x%x\n", readl(0x300016c));
+ }
+
+ dram_voltage_set(para);
+
+ /* Set SDRAM controller auto config */
+ if ((config.dram_tpr13 & BIT(0)) == 0) {
+ if (auto_scan_dram_config(para, &config) == 0) {
+ printf("auto_scan_dram_config() FAILED\n");
+ return 0;
+ }
+ }
+
+ /* report ODT */
+ rc = para->dram_mr1;
+ if ((rc & 0x44) == 0)
+ debug("DRAM ODT off\n");
+ else
+ debug("DRAM ODT value: 0x%x\n", rc);
+
+ /* Init core, final run */
+ if (mctl_core_init(para, &config) == 0) {
+ printf("DRAM initialisation error: 1\n");
+ return 0;
+ }
+
+ /* Get SDRAM size */
+ /* TODO: who ever puts a negative number in the top half? */
+ rc = config.dram_para2;
+ if (rc & BIT(31)) {
+ rc = (rc >> 16) & ~BIT(15);
+ } else {
+ rc = DRAMC_get_dram_size();
+ debug("DRAM: size = %dMB\n", rc);
+ config.dram_para2 = (config.dram_para2 & 0xffffU) | rc << 16;
+ }
+ mem_size_mb = rc;
+
+ /* Purpose ?? */
+ if (config.dram_tpr13 & BIT(30)) {
+ rc = para->dram_tpr8;
+ if (rc == 0)
+ rc = 0x10000200;
+ writel(rc, 0x31030a0);
+ writel(0x40a, 0x310309c);
+ setbits_le32(0x3103004, BIT(0));
+ debug("Enable Auto SR\n");
+ } else {
+ clrbits_le32(0x31030a0, 0xffff);
+ clrbits_le32(0x3103004, 0x1);
+ }
+
+ /* Purpose ?? */
+ if (config.dram_tpr13 & BIT(9)) {
+ clrsetbits_le32(0x3103100, 0xf000, 0x5000);
+ } else {
+ if (para->dram_type != SUNXI_DRAM_TYPE_LPDDR2)
+ clrbits_le32(0x3103100, 0xf000);
+ }
+
+ setbits_le32(0x3103140, BIT(31));
+
+ /* CHECK: is that really writing to a different register? */
+ if (config.dram_tpr13 & BIT(8))
+ writel(readl(0x3103140) | 0x300, 0x31030b8);
+
+ if (config.dram_tpr13 & BIT(16))
+ clrbits_le32(0x3103108, BIT(13));
+ else
+ setbits_le32(0x3103108, BIT(13));
+
+ /* Purpose ?? */
+ if (para->dram_type == SUNXI_DRAM_TYPE_LPDDR3)
+ clrsetbits_le32(0x310307c, 0xf0000, 0x1000);
+
+ dram_enable_all_master();
+ if (config.dram_tpr13 & BIT(28)) {
+ if ((readl(0x70005d4) & BIT(16)) ||
+ dramc_simple_wr_test(mem_size_mb, 4096))
+ return 0;
+ }
+
+ return mem_size_mb;
+}
+
+static const dram_para_t para = {
+ .dram_clk = CONFIG_DRAM_CLK,
+ .dram_type = CONFIG_SUNXI_DRAM_TYPE,
+ .dram_zq = CONFIG_DRAM_ZQ,
+ .dram_odt_en = CONFIG_DRAM_SUNXI_ODT_EN,
+ .dram_mr0 = 0x1c70,
+ .dram_mr1 = 0x42,
+ .dram_mr2 = 0x18,
+ .dram_mr3 = 0,
+ .dram_tpr0 = 0x004a2195,
+ .dram_tpr1 = 0x02423190,
+ .dram_tpr2 = 0x0008b061,
+ .dram_tpr3 = 0xb4787896, // unused
+ .dram_tpr4 = 0,
+ .dram_tpr5 = 0x48484848,
+ .dram_tpr6 = 0x00000048,
+ .dram_tpr7 = 0x1620121e, // unused
+ .dram_tpr8 = 0,
+ .dram_tpr9 = 0, // clock?
+ .dram_tpr10 = 0,
+ .dram_tpr11 = CONFIG_DRAM_SUNXI_TPR11,
+ .dram_tpr12 = CONFIG_DRAM_SUNXI_TPR12,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return init_DRAM(0, ¶) * 1024UL * 1024;
+};
+
+#ifdef CONFIG_RAM /* using the driver model */
+struct sunxi_ram_priv {
+ size_t size;
+};
+
+static int sunxi_ram_probe(struct udevice *dev)
+{
+ struct sunxi_ram_priv *priv = dev_get_priv(dev);
+ unsigned long dram_size;
+
+ debug("%s: %s: probing\n", __func__, dev->name);
+
+ dram_size = sunxi_dram_init();
+ if (!dram_size) {
+ printf("DRAM init failed\n");
+ return -ENODEV;
+ }
+
+ priv->size = dram_size;
+
+ return 0;
+}
+
+static int sunxi_ram_get_info(struct udevice *dev, struct ram_info *info)
+{
+ struct sunxi_ram_priv *priv = dev_get_priv(dev);
+
+ debug("%s: %s: getting info\n", __func__, dev->name);
+
+ info->base = CFG_SYS_SDRAM_BASE;
+ info->size = priv->size;
+
+ return 0;
+}
+
+static struct ram_ops sunxi_ram_ops = {
+ .get_info = sunxi_ram_get_info,
+};
+
+static const struct udevice_id sunxi_ram_ids[] = {
+ { .compatible = "allwinner,sun20i-d1-mbus" },
+ { }
+};
+
+U_BOOT_DRIVER(sunxi_ram) = {
+ .name = "sunxi_ram",
+ .id = UCLASS_RAM,
+ .of_match = sunxi_ram_ids,
+ .ops = &sunxi_ram_ops,
+ .probe = sunxi_ram_probe,
+ .priv_auto = sizeof(struct sunxi_ram_priv),
+};
+#endif /* CONFIG_RAM (using driver model) */
diff --git a/drivers/ram/sunxi/dram_sun20i_d1.h b/drivers/ram/sunxi/dram_sun20i_d1.h
new file mode 100644
index 0000000..91383f6
--- /dev/null
+++ b/drivers/ram/sunxi/dram_sun20i_d1.h
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * D1/R528/T113 DRAM controller register and constant defines
+ *
+ * (C) Copyright 2022 Arm Ltd.
+ * Based on H6 and H616 header, which are:
+ * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
+ * (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net>
+ *
+ */
+
+#ifndef _SUNXI_DRAM_SUN20I_D1_H
+#define _SUNXI_DRAM_SUN20I_D1_H
+
+enum sunxi_dram_type {
+ SUNXI_DRAM_TYPE_DDR2 = 2,
+ SUNXI_DRAM_TYPE_DDR3 = 3,
+ SUNXI_DRAM_TYPE_LPDDR2 = 6,
+ SUNXI_DRAM_TYPE_LPDDR3 = 7,
+};
+
+/*
+ * This structure contains a mixture of fixed configuration settings,
+ * variables that are used at runtime to communicate settings between
+ * different stages and functions, and unused values.
+ * This is copied from Allwinner's boot0 data structure, which can be
+ * found at offset 0x38 in any boot0 binary. To allow matching up some
+ * board specific settings, this struct is kept compatible, even though
+ * we don't need all members in our code.
+ */
+typedef struct dram_para {
+ /* normal configuration */
+ const u32 dram_clk;
+ const u32 dram_type;
+ const u32 dram_zq;
+ const u32 dram_odt_en;
+
+ /* timing configuration */
+ const u32 dram_mr0;
+ const u32 dram_mr1;
+ const u32 dram_mr2;
+ const u32 dram_mr3;
+ const u32 dram_tpr0; //DRAMTMG0
+ const u32 dram_tpr1; //DRAMTMG1
+ const u32 dram_tpr2; //DRAMTMG2
+ const u32 dram_tpr3; //DRAMTMG3
+ const u32 dram_tpr4; //DRAMTMG4
+ const u32 dram_tpr5; //DRAMTMG5
+ const u32 dram_tpr6; //DRAMTMG8
+ const u32 dram_tpr7;
+ const u32 dram_tpr8;
+ const u32 dram_tpr9;
+ const u32 dram_tpr10;
+ const u32 dram_tpr11;
+ const u32 dram_tpr12;
+} dram_para_t;
+
+typedef struct dram_config {
+ /* control configuration */
+ u32 dram_para1;
+ u32 dram_para2;
+ /* contains a bitfield of DRAM setup settings */
+ u32 dram_tpr13;
+} dram_config_t;
+
+static inline int ns_to_t(int nanoseconds)
+{
+ const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
+
+ return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
+}
+
+#endif /* _SUNXI_DRAM_SUN20I_D1_H */
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index 27e4a60..781de53 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2015
-# Texas Instruments Incorporated - http://www.ti.com/
+# Texas Instruments Incorporated - https://www.ti.com/
#
menu "Remote Processor drivers"
diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index fbe9c17..e09ed1a 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2015
-# Texas Instruments Incorporated - http://www.ti.com/
+# Texas Instruments Incorporated - https://www.ti.com/
#
obj-$(CONFIG_$(SPL_)REMOTEPROC) += rproc-uclass.o rproc-elf-loader.o
diff --git a/drivers/remoteproc/ipu_rproc.c b/drivers/remoteproc/ipu_rproc.c
index b4a06bc..996e658 100644
--- a/drivers/remoteproc/ipu_rproc.c
+++ b/drivers/remoteproc/ipu_rproc.c
@@ -2,7 +2,7 @@
/*
* IPU remoteproc driver for various SoCs
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* Angela Stegmaier <angelabaker@ti.com>
* Venkateswara Rao Mandela <venkat.mandela@ti.com>
* Keerthy <j-keerthy@ti.com>
diff --git a/drivers/remoteproc/k3_system_controller.c b/drivers/remoteproc/k3_system_controller.c
index e2affe6..071de40 100644
--- a/drivers/remoteproc/k3_system_controller.c
+++ b/drivers/remoteproc/k3_system_controller.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments' K3 System Controller Driver
*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c
index 924070a..6ec55e2 100644
--- a/drivers/remoteproc/pru_rproc.c
+++ b/drivers/remoteproc/pru_rproc.c
@@ -2,7 +2,7 @@
/*
* PRU-RTU remoteproc driver for various SoCs
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Keerthy <j-keerthy@ti.com>
*/
diff --git a/drivers/remoteproc/rproc-elf-loader.c b/drivers/remoteproc/rproc-elf-loader.c
index b185a6c..5e070e5 100644
--- a/drivers/remoteproc/rproc-elf-loader.c
+++ b/drivers/remoteproc/rproc-elf-loader.c
@@ -11,6 +11,7 @@
#include <asm/cache.h>
#include <dm/device_compat.h>
#include <linux/compat.h>
+#include <linux/printk.h>
/**
* struct resource_table - firmware resource table header
diff --git a/drivers/remoteproc/rproc-uclass.c b/drivers/remoteproc/rproc-uclass.c
index 50bcc90..28b362c 100644
--- a/drivers/remoteproc/rproc-uclass.c
+++ b/drivers/remoteproc/rproc-uclass.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2015
- * Texas Instruments Incorporated - http://www.ti.com/
+ * Texas Instruments Incorporated - https://www.ti.com/
*/
#define LOG_CATEGORY UCLASS_REMOTEPROC
@@ -20,6 +20,7 @@
#include <dm/uclass.h>
#include <dm/uclass-internal.h>
#include <linux/compat.h>
+#include <linux/printk.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -689,7 +690,7 @@
debug("alloc_mem(%#x, %d): %p\n", size, order, pa);
vring->da = (uintptr_t)pa;
- return !pa;
+ return 0;
}
static int handle_vdev(struct udevice *dev, struct fw_rsc_vdev *rsc,
diff --git a/drivers/remoteproc/sandbox_testproc.c b/drivers/remoteproc/sandbox_testproc.c
index 78b1081..f76f68e 100644
--- a/drivers/remoteproc/sandbox_testproc.c
+++ b/drivers/remoteproc/sandbox_testproc.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2015
- * Texas Instruments Incorporated - http://www.ti.com/
+ * Texas Instruments Incorporated - https://www.ti.com/
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <common.h>
@@ -10,6 +10,7 @@
#include <log.h>
#include <remoteproc.h>
#include <asm/io.h>
+#include <linux/printk.h>
/**
* enum sandbox_state - different device states
diff --git a/drivers/remoteproc/stm32_copro.c b/drivers/remoteproc/stm32_copro.c
index 5271f83..3e322c4 100644
--- a/drivers/remoteproc/stm32_copro.c
+++ b/drivers/remoteproc/stm32_copro.c
@@ -14,6 +14,7 @@
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/err.h>
+#include <linux/printk.h>
/**
* struct stm32_copro_privdata - power processor private data
diff --git a/drivers/remoteproc/ti_k3_arm64_rproc.c b/drivers/remoteproc/ti_k3_arm64_rproc.c
index 99f1100..767493c 100644
--- a/drivers/remoteproc/ti_k3_arm64_rproc.c
+++ b/drivers/remoteproc/ti_k3_arm64_rproc.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments' K3 ARM64 Remoteproc driver
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*
*/
diff --git a/drivers/remoteproc/ti_k3_dsp_rproc.c b/drivers/remoteproc/ti_k3_dsp_rproc.c
index 1a2e9dd..576de4b 100644
--- a/drivers/remoteproc/ti_k3_dsp_rproc.c
+++ b/drivers/remoteproc/ti_k3_dsp_rproc.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments' K3 DSP Remoteproc driver
*
- * Copyright (C) 2018-2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
* Suman Anna <s-anna@ti.com>
*/
diff --git a/drivers/remoteproc/ti_power_proc.c b/drivers/remoteproc/ti_power_proc.c
index 86d544c..f55df4a 100644
--- a/drivers/remoteproc/ti_power_proc.c
+++ b/drivers/remoteproc/ti_power_proc.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2015-2016
- * Texas Instruments Incorporated - http://www.ti.com/
+ * Texas Instruments Incorporated - https://www.ti.com/
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <common.h>
@@ -11,6 +11,7 @@
#include <log.h>
#include <remoteproc.h>
#include <asm/global_data.h>
+#include <linux/printk.h>
#include <mach/psc_defs.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/remoteproc/ti_sci_proc.h b/drivers/remoteproc/ti_sci_proc.h
index f8299d1..167a714 100644
--- a/drivers/remoteproc/ti_sci_proc.h
+++ b/drivers/remoteproc/ti_sci_proc.h
@@ -2,7 +2,7 @@
/*
* Texas Instruments TI-SCI Processor Controller Helper Functions
*
- * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
* Suman Anna <s-anna@ti.com>
*/
@@ -10,6 +10,7 @@
#ifndef REMOTEPROC_TI_SCI_PROC_H
#define REMOTEPROC_TI_SCI_PROC_H
+#include <linux/printk.h>
#define TISCI_INVALID_HOST 0xff
/**
diff --git a/drivers/reset/reset-dra7.c b/drivers/reset/reset-dra7.c
index a9589d4..05101a9 100644
--- a/drivers/reset/reset-dra7.c
+++ b/drivers/reset/reset-dra7.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments DRA7 reset driver
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* Author: Keerthy <j-keerthy@ti.com>
*/
diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
index 64bc696..9d0c8b3 100644
--- a/drivers/reset/reset-meson.c
+++ b/drivers/reset/reset-meson.c
@@ -13,18 +13,26 @@
#include <reset-uclass.h>
#include <regmap.h>
#include <linux/bitops.h>
+#include <linux/delay.h>
-#define REG_COUNT 8
#define BITS_PER_REG 32
-#define LEVEL_OFFSET 0x7c
+
+struct meson_reset_drvdata {
+ unsigned int reg_count;
+ unsigned int level_offset;
+};
struct meson_reset_priv {
struct regmap *regmap;
+ struct meson_reset_drvdata *drvdata;
};
static int meson_reset_request(struct reset_ctl *reset_ctl)
{
- if (reset_ctl->id > (REG_COUNT * BITS_PER_REG))
+ struct meson_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ struct meson_reset_drvdata *data = priv->drvdata;
+
+ if (reset_ctl->id > (data->reg_count * BITS_PER_REG))
return -EINVAL;
return 0;
@@ -33,9 +41,10 @@
static int meson_reset_level(struct reset_ctl *reset_ctl, bool assert)
{
struct meson_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ struct meson_reset_drvdata *data = priv->drvdata;
uint bank = reset_ctl->id / BITS_PER_REG;
uint offset = reset_ctl->id % BITS_PER_REG;
- uint reg_offset = LEVEL_OFFSET + (bank << 2);
+ uint reg_offset = data->level_offset + (bank << 2);
uint val;
regmap_read(priv->regmap, reg_offset, &val);
@@ -64,15 +73,36 @@
.rst_deassert = meson_reset_deassert,
};
+static const struct meson_reset_drvdata meson_gxbb_data = {
+ .reg_count = 8,
+ .level_offset = 0x7c,
+};
+
+static const struct meson_reset_drvdata meson_a1_data = {
+ .reg_count = 3,
+ .level_offset = 0x40,
+};
+
static const struct udevice_id meson_reset_ids[] = {
- { .compatible = "amlogic,meson-gxbb-reset" },
- { .compatible = "amlogic,meson-axg-reset" },
+ {
+ .compatible = "amlogic,meson-gxbb-reset",
+ .data = (ulong)&meson_gxbb_data,
+ },
+ {
+ .compatible = "amlogic,meson-axg-reset",
+ .data = (ulong)&meson_gxbb_data,
+ },
+ {
+ .compatible = "amlogic,meson-a1-reset",
+ .data = (ulong)&meson_a1_data,
+ },
{ }
};
static int meson_reset_probe(struct udevice *dev)
{
struct meson_reset_priv *priv = dev_get_priv(dev);
+ priv->drvdata = (struct meson_reset_drvdata *)dev_get_driver_data(dev);
return regmap_init_mem(dev_ofnode(dev), &priv->regmap);
}
diff --git a/drivers/reset/reset-scmi.c b/drivers/reset/reset-scmi.c
index 1225561..b76711f 100644
--- a/drivers/reset/reset-scmi.c
+++ b/drivers/reset/reset-scmi.c
@@ -13,17 +13,8 @@
#include <scmi_protocols.h>
#include <asm/types.h>
-/**
- * struct scmi_reset_priv - Private data for SCMI reset controller
- * @channel: Reference to the SCMI channel to use
- */
-struct scmi_reset_priv {
- struct scmi_channel *channel;
-};
-
static int scmi_reset_set_level(struct reset_ctl *rst, bool assert_not_deassert)
{
- struct scmi_reset_priv *priv = dev_get_priv(rst->dev);
struct scmi_rd_reset_in in = {
.domain_id = rst->id,
.flags = assert_not_deassert ? SCMI_RD_RESET_FLAG_ASSERT : 0,
@@ -35,7 +26,7 @@
in, out);
int ret;
- ret = devm_scmi_process_msg(rst->dev, priv->channel, &msg);
+ ret = devm_scmi_process_msg(rst->dev, &msg);
if (ret)
return ret;
@@ -54,7 +45,6 @@
static int scmi_reset_request(struct reset_ctl *rst)
{
- struct scmi_reset_priv *priv = dev_get_priv(rst->dev);
struct scmi_rd_attr_in in = {
.domain_id = rst->id,
};
@@ -68,7 +58,7 @@
* We don't really care about the attribute, just check
* the reset domain exists.
*/
- ret = devm_scmi_process_msg(rst->dev, priv->channel, &msg);
+ ret = devm_scmi_process_msg(rst->dev, &msg);
if (ret)
return ret;
@@ -83,9 +73,7 @@
static int scmi_reset_probe(struct udevice *dev)
{
- struct scmi_reset_priv *priv = dev_get_priv(dev);
-
- return devm_scmi_of_get_channel(dev, &priv->channel);
+ return devm_scmi_of_get_channel(dev);
}
U_BOOT_DRIVER(scmi_reset_domain) = {
@@ -93,5 +81,4 @@
.id = UCLASS_RESET,
.ops = &scmi_reset_domain_ops,
.probe = scmi_reset_probe,
- .priv_auto = sizeof(struct scmi_reset_priv *),
};
diff --git a/drivers/reset/reset-ti-sci.c b/drivers/reset/reset-ti-sci.c
index f353327..fd654a0 100644
--- a/drivers/reset/reset-ti-sci.c
+++ b/drivers/reset/reset-ti-sci.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments System Control Interface (TI SCI) reset driver
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Andreas Dannenberg <dannenberg@ti.com>
*
* Loosely based on Linux kernel reset-ti-sci.c...
diff --git a/drivers/reset/sti-reset.c b/drivers/reset/sti-reset.c
index ea449bb..5305270 100644
--- a/drivers/reset/sti-reset.c
+++ b/drivers/reset/sti-reset.c
@@ -16,6 +16,7 @@
#include <asm/global_data.h>
#include <dt-bindings/reset/stih407-resets.h>
#include <linux/bitops.h>
+#include <linux/printk.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index 5deb5db..a89c899 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -48,11 +48,19 @@
accessible to normal world but reserved and used by the OP-TEE
to avoid the weakness of a software PRNG.
-config RNG_STM32MP1
- bool "Enable random number generator for STM32MP1"
- depends on ARCH_STM32MP
+config RNG_RISCV_ZKR
+ bool "RISC-V Zkr random number generator"
+ depends on RISCV_SMODE
help
- Enable STM32MP1 rng driver.
+ This driver provides a Random Number Generator based on the
+ Zkr RISC-V ISA extension which provides an interface to an
+ NIST SP 800-90B or BSI AIS-31 compliant physical entropy source.
+
+config RNG_STM32
+ bool "Enable random number generator for STM32"
+ depends on ARCH_STM32 || ARCH_STM32MP
+ help
+ Enable STM32 rng driver.
config RNG_ROCKCHIP
bool "Enable random number generator for rockchip crypto rng"
@@ -76,6 +84,12 @@
Enable random number generator for platforms that support Arm
SMCCC TRNG interface.
+config RNG_ARM_RNDR
+ bool "Generic ARMv8.5 RNDR register"
+ depends on DM_RNG && ARM64
+ help
+ Use the ARMv8.5 RNDR register to provide random numbers.
+
config TPM_RNG
bool "Enable random number generator on TPM device"
depends on TPM
@@ -85,4 +99,10 @@
functionality. Enable random number generator on TPM
devices.
+config RNG_JH7110
+ bool "StarFive JH7110 Random Number Generator support"
+ depends on DM_RNG && STARFIVE_JH7110
+ help
+ Enable True Random Number Generator in StarFive JH7110 SoCs.
+
endif
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index 78f6105..7e64c4c 100644
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -9,8 +9,11 @@
obj-$(CONFIG_RNG_MSM) += msm_rng.o
obj-$(CONFIG_RNG_NPCM) += npcm_rng.o
obj-$(CONFIG_RNG_OPTEE) += optee_rng.o
-obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o
+obj-$(CONFIG_RNG_STM32) += stm32_rng.o
+obj-$(CONFIG_RNG_RISCV_ZKR) += riscv_zkr_rng.o
obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o
obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o
obj-$(CONFIG_RNG_SMCCC_TRNG) += smccc_trng.o
+obj-$(CONFIG_RNG_ARM_RNDR) += arm_rndr.o
obj-$(CONFIG_TPM_RNG) += tpm_rng.o
+obj-$(CONFIG_RNG_JH7110) += jh7110_rng.o
diff --git a/drivers/rng/arm_rndr.c b/drivers/rng/arm_rndr.c
new file mode 100644
index 0000000..5598974
--- /dev/null
+++ b/drivers/rng/arm_rndr.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023, Arm Ltd.
+ *
+ * Use the (optional) ARMv8.5 RNDR register to provide random numbers to
+ * U-Boot's UCLASS_RNG users.
+ * Detection is done at runtime using the CPU ID registers.
+ */
+
+#define LOG_CATEGORY UCLASS_RNG
+
+#include <common.h>
+#include <dm.h>
+#include <linux/kernel.h>
+#include <rng.h>
+#include <asm/system.h>
+
+#define DRIVER_NAME "arm-rndr"
+
+static bool cpu_has_rndr(void)
+{
+ uint64_t reg;
+
+ __asm__ volatile("mrs %0, ID_AA64ISAR0_EL1\n" : "=r" (reg));
+ return !!(reg & ID_AA64ISAR0_EL1_RNDR);
+}
+
+/*
+ * The system register name is RNDR, but this isn't widely known among older
+ * toolchains, and also triggers errors because of it being an architecture
+ * extension. Since we check the availability of the register before, it's
+ * fine to use here, though.
+ */
+#define RNDR "S3_3_C2_C4_0"
+
+static uint64_t read_rndr(void)
+{
+ uint64_t reg;
+
+ __asm__ volatile("mrs %0, " RNDR "\n" : "=r" (reg));
+
+ return reg;
+}
+
+static int arm_rndr_read(struct udevice *dev, void *data, size_t len)
+{
+ uint64_t random;
+
+ while (len) {
+ int tocopy = min(sizeof(uint64_t), len);
+
+ random = read_rndr();
+ memcpy(data, &random, tocopy);
+ len -= tocopy;
+ data += tocopy;
+ }
+
+ return 0;
+}
+
+static const struct dm_rng_ops arm_rndr_ops = {
+ .read = arm_rndr_read,
+};
+
+static int arm_rndr_probe(struct udevice *dev)
+{
+ if (!cpu_has_rndr())
+ return -ENODEV;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(arm_rndr) = {
+ .name = DRIVER_NAME,
+ .id = UCLASS_RNG,
+ .ops = &arm_rndr_ops,
+ .probe = arm_rndr_probe,
+};
+
+U_BOOT_DRVINFO(cpu_arm_rndr) = {
+ .name = DRIVER_NAME,
+};
diff --git a/drivers/rng/jh7110_rng.c b/drivers/rng/jh7110_rng.c
new file mode 100644
index 0000000..eb21afe
--- /dev/null
+++ b/drivers/rng/jh7110_rng.c
@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * TRNG driver for the StarFive JH7110 SoC
+ *
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <reset.h>
+#include <rng.h>
+#include <asm/io.h>
+#include <linux/iopoll.h>
+
+/* trng register offset */
+#define STARFIVE_CTRL 0x00
+#define STARFIVE_STAT 0x04
+#define STARFIVE_MODE 0x08
+#define STARFIVE_SMODE 0x0C
+#define STARFIVE_IE 0x10
+#define STARFIVE_ISTAT 0x14
+#define STARFIVE_RAND0 0x20
+#define STARFIVE_RAND1 0x24
+#define STARFIVE_RAND2 0x28
+#define STARFIVE_RAND3 0x2C
+#define STARFIVE_RAND4 0x30
+#define STARFIVE_RAND5 0x34
+#define STARFIVE_RAND6 0x38
+#define STARFIVE_RAND7 0x3C
+#define STARFIVE_AUTO_RQSTS 0x60
+#define STARFIVE_AUTO_AGE 0x64
+
+/* CTRL CMD */
+#define STARFIVE_CTRL_EXEC_NOP 0x0
+#define STARFIVE_CTRL_GENE_RANDNUM 0x1
+#define STARFIVE_CTRL_EXEC_RANDRESEED 0x2
+
+/* STAT */
+#define STARFIVE_STAT_NONCE_MODE BIT(2)
+#define STARFIVE_STAT_R256 BIT(3)
+#define STARFIVE_STAT_MISSION_MODE BIT(8)
+#define STARFIVE_STAT_SEEDED BIT(9)
+#define STARFIVE_STAT_LAST_RESEED(x) ((x) << 16)
+#define STARFIVE_STAT_SRVC_RQST BIT(27)
+#define STARFIVE_STAT_RAND_GENERATING BIT(30)
+#define STARFIVE_STAT_RAND_SEEDING BIT(31)
+#define STARFIVE_STAT_RUNNING (STARFIVE_STAT_RAND_GENERATING | \
+ STARFIVE_STAT_RAND_SEEDING)
+
+/* MODE */
+#define STARFIVE_MODE_R256 BIT(3)
+
+/* SMODE */
+#define STARFIVE_SMODE_NONCE_MODE BIT(2)
+#define STARFIVE_SMODE_MISSION_MODE BIT(8)
+#define STARFIVE_SMODE_MAX_REJECTS(x) ((x) << 16)
+
+/* IE */
+#define STARFIVE_IE_RAND_RDY_EN BIT(0)
+#define STARFIVE_IE_SEED_DONE_EN BIT(1)
+#define STARFIVE_IE_LFSR_LOCKUP_EN BIT(4)
+#define STARFIVE_IE_GLBL_EN BIT(31)
+
+#define STARFIVE_IE_ALL (STARFIVE_IE_GLBL_EN | \
+ STARFIVE_IE_RAND_RDY_EN | \
+ STARFIVE_IE_SEED_DONE_EN | \
+ STARFIVE_IE_LFSR_LOCKUP_EN)
+
+/* ISTAT */
+#define STARFIVE_ISTAT_RAND_RDY BIT(0)
+#define STARFIVE_ISTAT_SEED_DONE BIT(1)
+#define STARFIVE_ISTAT_LFSR_LOCKUP BIT(4)
+
+#define STARFIVE_RAND_LEN sizeof(u32)
+
+enum mode {
+ PRNG_128BIT,
+ PRNG_256BIT,
+};
+
+struct starfive_trng_plat {
+ void *base;
+ struct clk *hclk;
+ struct clk *ahb;
+ struct reset_ctl *rst;
+ u32 mode;
+};
+
+static inline int starfive_trng_wait_idle(struct starfive_trng_plat *trng)
+{
+ u32 stat;
+
+ return readl_relaxed_poll_timeout(trng->base + STARFIVE_STAT, stat,
+ !(stat & STARFIVE_STAT_RUNNING),
+ 100000);
+}
+
+static inline void starfive_trng_irq_mask_clear(struct starfive_trng_plat *trng)
+{
+ /* clear register: ISTAT */
+ u32 data = readl(trng->base + STARFIVE_ISTAT);
+
+ writel(data, trng->base + STARFIVE_ISTAT);
+}
+
+static int starfive_trng_cmd(struct starfive_trng_plat *trng, u32 cmd)
+{
+ u32 stat, flg;
+ int ret;
+
+ switch (cmd) {
+ case STARFIVE_CTRL_GENE_RANDNUM:
+ writel(cmd, trng->base + STARFIVE_CTRL);
+ flg = STARFIVE_ISTAT_RAND_RDY;
+ break;
+ case STARFIVE_CTRL_EXEC_RANDRESEED:
+ writel(cmd, trng->base + STARFIVE_CTRL);
+ flg = STARFIVE_ISTAT_SEED_DONE;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ ret = readl_relaxed_poll_timeout(trng->base + STARFIVE_ISTAT, stat,
+ (stat & flg), 1000);
+ writel(flg, trng->base + STARFIVE_ISTAT);
+
+ return ret;
+}
+
+static int starfive_trng_read(struct udevice *dev, void *data, size_t len)
+{
+ struct starfive_trng_plat *trng = dev_get_plat(dev);
+ u8 *buffer = data;
+ int iter_mask;
+
+ if (trng->mode == PRNG_256BIT)
+ iter_mask = 7;
+ else
+ iter_mask = 3;
+
+ for (int i = 0; len; ++i, i &= iter_mask) {
+ u32 val;
+ size_t step;
+ int ret;
+
+ if (!i) {
+ ret = starfive_trng_cmd(trng,
+ STARFIVE_CTRL_GENE_RANDNUM);
+ if (ret)
+ return ret;
+ }
+
+ val = readl(trng->base + STARFIVE_RAND0 +
+ (i * STARFIVE_RAND_LEN));
+ step = min_t(size_t, len, STARFIVE_RAND_LEN);
+ memcpy(buffer, &val, step);
+ buffer += step;
+ len -= step;
+ }
+
+ return 0;
+}
+
+static int starfive_trng_init(struct starfive_trng_plat *trng)
+{
+ u32 mode, intr = 0;
+
+ /* setup Auto Request/Age register */
+ writel(0, trng->base + STARFIVE_AUTO_AGE);
+ writel(0, trng->base + STARFIVE_AUTO_RQSTS);
+
+ /* clear register: ISTAT */
+ starfive_trng_irq_mask_clear(trng);
+
+ intr |= STARFIVE_IE_ALL;
+ writel(intr, trng->base + STARFIVE_IE);
+
+ mode = readl(trng->base + STARFIVE_MODE);
+
+ switch (trng->mode) {
+ case PRNG_128BIT:
+ mode &= ~STARFIVE_MODE_R256;
+ break;
+ case PRNG_256BIT:
+ mode |= STARFIVE_MODE_R256;
+ break;
+ default:
+ mode |= STARFIVE_MODE_R256;
+ break;
+ }
+
+ writel(mode, trng->base + STARFIVE_MODE);
+
+ return starfive_trng_cmd(trng, STARFIVE_CTRL_EXEC_RANDRESEED);
+}
+
+static int starfive_trng_probe(struct udevice *dev)
+{
+ struct starfive_trng_plat *pdata = dev_get_plat(dev);
+ int err;
+
+ err = clk_enable(pdata->hclk);
+ if (err)
+ return err;
+
+ err = clk_enable(pdata->ahb);
+ if (err)
+ goto err_ahb;
+
+ err = reset_deassert(pdata->rst);
+ if (err)
+ goto err_reset;
+
+ pdata->mode = PRNG_256BIT;
+
+ err = starfive_trng_init(pdata);
+ if (err)
+ goto err_trng_init;
+
+ return 0;
+
+err_trng_init:
+ reset_assert(pdata->rst);
+err_reset:
+ clk_disable(pdata->ahb);
+err_ahb:
+ clk_disable(pdata->hclk);
+
+ return err;
+}
+
+static int starfive_trng_of_to_plat(struct udevice *dev)
+{
+ struct starfive_trng_plat *pdata = dev_get_plat(dev);
+
+ pdata->base = (void *)dev_read_addr(dev);
+ if (!pdata->base)
+ return -ENODEV;
+
+ pdata->hclk = devm_clk_get(dev, "hclk");
+ if (IS_ERR(pdata->hclk))
+ return -ENODEV;
+
+ pdata->ahb = devm_clk_get(dev, "ahb");
+ if (IS_ERR(pdata->ahb))
+ return -ENODEV;
+
+ pdata->rst = devm_reset_control_get(dev, NULL);
+ if (IS_ERR(pdata->rst))
+ return -ENODEV;
+
+ return 0;
+}
+
+static const struct dm_rng_ops starfive_trng_ops = {
+ .read = starfive_trng_read,
+};
+
+static const struct udevice_id starfive_trng_match[] = {
+ {
+ .compatible = "starfive,jh7110-trng",
+ },
+ {},
+};
+
+U_BOOT_DRIVER(starfive_trng) = {
+ .name = "jh7110-trng",
+ .id = UCLASS_RNG,
+ .of_match = starfive_trng_match,
+ .probe = starfive_trng_probe,
+ .ops = &starfive_trng_ops,
+ .plat_auto = sizeof(struct starfive_trng_plat),
+ .of_to_plat = starfive_trng_of_to_plat,
+};
diff --git a/drivers/rng/meson-rng.c b/drivers/rng/meson-rng.c
index e0a1e8c..fd2988e 100644
--- a/drivers/rng/meson-rng.c
+++ b/drivers/rng/meson-rng.c
@@ -10,10 +10,23 @@
#include <dm.h>
#include <rng.h>
#include <asm/io.h>
+#include <linux/iopoll.h>
+
+#define RNG_DATA 0x00
+#define RNG_S4_DATA 0x08
+#define RNG_S4_CFG 0x00
+
+#define RUN_BIT BIT(0)
+#define SEED_READY_STS_BIT BIT(31)
+
+struct meson_rng_priv {
+ u32 (*read)(fdt_addr_t base);
+};
struct meson_rng_plat {
fdt_addr_t base;
struct clk clk;
+ struct meson_rng_priv *priv;
};
/**
@@ -27,10 +40,11 @@
static int meson_rng_read(struct udevice *dev, void *data, size_t len)
{
struct meson_rng_plat *pdata = dev_get_plat(dev);
+ struct meson_rng_priv *priv = pdata->priv;
char *buffer = (char *)data;
while (len) {
- u32 rand = readl(pdata->base);
+ u32 rand = priv->read(pdata->base);
size_t step;
if (len >= 4)
@@ -44,6 +58,47 @@
return 0;
}
+static int meson_rng_wait_status(void __iomem *cfg_addr, int bit)
+{
+ u32 status = 0;
+ int ret;
+
+ ret = readl_relaxed_poll_timeout(cfg_addr,
+ status, !(status & bit),
+ 10000);
+ if (ret)
+ return -EBUSY;
+
+ return 0;
+}
+
+static u32 meson_common_rng_read(fdt_addr_t base)
+{
+ return readl(base);
+}
+
+static u32 meson_s4_rng_read(fdt_addr_t base)
+{
+ void __iomem *cfg_addr = (void *)base + RNG_S4_CFG;
+ int err;
+
+ writel_relaxed(readl_relaxed(cfg_addr) | SEED_READY_STS_BIT, cfg_addr);
+
+ err = meson_rng_wait_status(cfg_addr, SEED_READY_STS_BIT);
+ if (err) {
+ pr_err("Seed isn't ready, try again\n");
+ return err;
+ }
+
+ err = meson_rng_wait_status(cfg_addr, RUN_BIT);
+ if (err) {
+ pr_err("Can't get random number, try again\n");
+ return err;
+ }
+
+ return readl_relaxed(base + RNG_S4_DATA);
+}
+
/**
* meson_rng_probe() - probe rng device
*
@@ -59,6 +114,8 @@
if (err)
return err;
+ pdata->priv = (struct meson_rng_priv *)dev_get_driver_data(dev);
+
return 0;
}
@@ -102,9 +159,22 @@
.read = meson_rng_read,
};
+static const struct meson_rng_priv meson_rng_priv = {
+ .read = meson_common_rng_read,
+};
+
+static const struct meson_rng_priv meson_rng_priv_s4 = {
+ .read = meson_s4_rng_read,
+};
+
static const struct udevice_id meson_rng_match[] = {
{
.compatible = "amlogic,meson-rng",
+ .data = (ulong)&meson_rng_priv,
+ },
+ {
+ .compatible = "amlogic,meson-s4-rng",
+ .data = (ulong)&meson_rng_priv_s4,
},
{},
};
diff --git a/drivers/rng/riscv_zkr_rng.c b/drivers/rng/riscv_zkr_rng.c
new file mode 100644
index 0000000..8c9e111
--- /dev/null
+++ b/drivers/rng/riscv_zkr_rng.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * The RISC-V Zkr extension provides CSR seed which provides access to a
+ * random number generator.
+ */
+
+#define LOG_CATEGORY UCLASS_RNG
+
+#include <dm.h>
+#include <interrupt.h>
+#include <log.h>
+#include <rng.h>
+
+#define DRIVER_NAME "riscv_zkr"
+
+enum opst {
+ /** @BIST: built in self test running */
+ BIST = 0b00,
+ /** @WAIT: sufficient amount of entropy is not yet available */
+ WAIT = 0b01,
+ /** @ES16: 16bits of entropy available */
+ ES16 = 0b10,
+ /** @DEAD: unrecoverable self-test error */
+ DEAD = 0b11,
+};
+
+static unsigned long read_seed(void)
+{
+ unsigned long ret;
+
+ __asm__ __volatile__("csrrw %0, seed, x0" : "=r" (ret) : : "memory");
+
+ return ret;
+}
+
+static int riscv_zkr_read(struct udevice *dev, void *data, size_t len)
+{
+ u8 *ptr = data;
+
+ while (len) {
+ u32 val;
+
+ val = read_seed();
+
+ switch (val >> 30) {
+ case BIST:
+ continue;
+ case WAIT:
+ continue;
+ case ES16:
+ *ptr++ = val & 0xff;
+ if (--len) {
+ *ptr++ = val >> 8;
+ --len;
+ }
+ break;
+ case DEAD:
+ return -ENODEV;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * riscv_zkr_probe() - check if the seed register is available
+ *
+ * If the SBI software has not set mseccfg.sseed=1 or the Zkr
+ * extension is not available this probe function will result
+ * in an exception. Currently we cannot recover from this.
+ *
+ * @dev: RNG device
+ * Return: 0 if successfully probed
+ */
+static int riscv_zkr_probe(struct udevice *dev)
+{
+ struct resume_data resume;
+ int ret;
+ u32 val;
+
+ /* Check if reading seed leads to interrupt */
+ set_resume(&resume);
+ ret = setjmp(resume.jump);
+ if (ret)
+ log_debug("Exception %ld reading seed CSR\n", resume.code);
+ else
+ val = read_seed();
+ set_resume(NULL);
+ if (ret)
+ return -ENODEV;
+
+ do {
+ val = read_seed();
+ val >>= 30;
+ } while (val == BIST || val == WAIT);
+
+ if (val == DEAD)
+ return -ENODEV;
+
+ return 0;
+}
+
+static const struct dm_rng_ops riscv_zkr_ops = {
+ .read = riscv_zkr_read,
+};
+
+U_BOOT_DRIVER(riscv_zkr) = {
+ .name = DRIVER_NAME,
+ .id = UCLASS_RNG,
+ .ops = &riscv_zkr_ops,
+ .probe = riscv_zkr_probe,
+};
+
+U_BOOT_DRVINFO(cpu_riscv_zkr) = {
+ .name = DRIVER_NAME,
+};
diff --git a/drivers/rng/stm32_rng.c b/drivers/rng/stm32_rng.c
new file mode 100644
index 0000000..c397b4d
--- /dev/null
+++ b/drivers/rng/stm32_rng.c
@@ -0,0 +1,408 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2019, Linaro Limited
+ */
+
+#define LOG_CATEGORY UCLASS_RNG
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <log.h>
+#include <reset.h>
+#include <rng.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+
+#include <asm/io.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+
+#define RNG_CR 0x00
+#define RNG_CR_RNGEN BIT(2)
+#define RNG_CR_CED BIT(5)
+#define RNG_CR_CONFIG1 GENMASK(11, 8)
+#define RNG_CR_NISTC BIT(12)
+#define RNG_CR_CONFIG2 GENMASK(15, 13)
+#define RNG_CR_CLKDIV_SHIFT 16
+#define RNG_CR_CLKDIV GENMASK(19, 16)
+#define RNG_CR_CONFIG3 GENMASK(25, 20)
+#define RNG_CR_CONDRST BIT(30)
+#define RNG_CR_ENTROPY_SRC_MASK (RNG_CR_CONFIG1 | RNG_CR_NISTC | RNG_CR_CONFIG2 | RNG_CR_CONFIG3)
+#define RNG_CR_CONFIG_MASK (RNG_CR_ENTROPY_SRC_MASK | RNG_CR_CED | RNG_CR_CLKDIV)
+
+#define RNG_SR 0x04
+#define RNG_SR_SEIS BIT(6)
+#define RNG_SR_CEIS BIT(5)
+#define RNG_SR_SECS BIT(2)
+#define RNG_SR_DRDY BIT(0)
+
+#define RNG_DR 0x08
+
+#define RNG_NSCR 0x0C
+#define RNG_NSCR_MASK GENMASK(17, 0)
+
+#define RNG_HTCR 0x10
+
+#define RNG_NB_RECOVER_TRIES 3
+
+/*
+ * struct stm32_rng_data - RNG compat data
+ *
+ * @max_clock_rate: Max RNG clock frequency, in Hertz
+ * @cr: Entropy source configuration
+ * @nscr: Noice sources control configuration
+ * @htcr: Health tests configuration
+ * @has_cond_reset: True if conditionnal reset is supported
+ *
+ */
+struct stm32_rng_data {
+ uint max_clock_rate;
+ u32 cr;
+ u32 nscr;
+ u32 htcr;
+ bool has_cond_reset;
+};
+
+struct stm32_rng_plat {
+ fdt_addr_t base;
+ struct clk clk;
+ struct reset_ctl rst;
+ const struct stm32_rng_data *data;
+ bool ced;
+};
+
+/*
+ * Extracts from the STM32 RNG specification when RNG supports CONDRST.
+ *
+ * When a noise source (or seed) error occurs, the RNG stops generating
+ * random numbers and sets to “1” both SEIS and SECS bits to indicate
+ * that a seed error occurred. (...)
+ *
+ * 1. Software reset by writing CONDRST at 1 and at 0 (see bitfield
+ * description for details). This step is needed only if SECS is set.
+ * Indeed, when SEIS is set and SECS is cleared it means RNG performed
+ * the reset automatically (auto-reset).
+ * 2. If SECS was set in step 1 (no auto-reset) wait for CONDRST
+ * to be cleared in the RNG_CR register, then confirm that SEIS is
+ * cleared in the RNG_SR register. Otherwise just clear SEIS bit in
+ * the RNG_SR register.
+ * 3. If SECS was set in step 1 (no auto-reset) wait for SECS to be
+ * cleared by RNG. The random number generation is now back to normal.
+ */
+static int stm32_rng_conceal_seed_error_cond_reset(struct stm32_rng_plat *pdata)
+{
+ u32 sr = readl_relaxed(pdata->base + RNG_SR);
+ u32 cr = readl_relaxed(pdata->base + RNG_CR);
+ int err;
+
+ if (sr & RNG_SR_SECS) {
+ /* Conceal by resetting the subsystem (step 1.) */
+ writel_relaxed(cr | RNG_CR_CONDRST, pdata->base + RNG_CR);
+ writel_relaxed(cr & ~RNG_CR_CONDRST, pdata->base + RNG_CR);
+ } else {
+ /* RNG auto-reset (step 2.) */
+ writel_relaxed(sr & ~RNG_SR_SEIS, pdata->base + RNG_SR);
+ return 0;
+ }
+
+ err = readl_relaxed_poll_timeout(pdata->base + RNG_SR, sr, !(sr & RNG_CR_CONDRST), 100000);
+ if (err) {
+ log_err("%s: timeout %x\n", __func__, sr);
+ return err;
+ }
+
+ /* Check SEIS is cleared (step 2.) */
+ if (readl_relaxed(pdata->base + RNG_SR) & RNG_SR_SEIS)
+ return -EINVAL;
+
+ err = readl_relaxed_poll_timeout(pdata->base + RNG_SR, sr, !(sr & RNG_SR_SECS), 100000);
+ if (err) {
+ log_err("%s: timeout %x\n", __func__, sr);
+ return err;
+ }
+
+ return 0;
+}
+
+/*
+ * Extracts from the STM32 RNG specification, when CONDRST is not supported
+ *
+ * When a noise source (or seed) error occurs, the RNG stops generating
+ * random numbers and sets to “1” both SEIS and SECS bits to indicate
+ * that a seed error occurred. (...)
+ *
+ * The following sequence shall be used to fully recover from a seed
+ * error after the RNG initialization:
+ * 1. Clear the SEIS bit by writing it to “0”.
+ * 2. Read out 12 words from the RNG_DR register, and discard each of
+ * them in order to clean the pipeline.
+ * 3. Confirm that SEIS is still cleared. Random number generation is
+ * back to normal.
+ */
+static int stm32_rng_conceal_seed_error_sw_reset(struct stm32_rng_plat *pdata)
+{
+ uint i = 0;
+ u32 sr = readl_relaxed(pdata->base + RNG_SR);
+
+ writel_relaxed(sr & ~RNG_SR_SEIS, pdata->base + RNG_SR);
+
+ for (i = 12; i != 0; i--)
+ (void)readl_relaxed(pdata->base + RNG_DR);
+
+ if (readl_relaxed(pdata->base + RNG_SR) & RNG_SR_SEIS)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int stm32_rng_conceal_seed_error(struct stm32_rng_plat *pdata)
+{
+ log_debug("Concealing RNG seed error\n");
+
+ if (pdata->data->has_cond_reset)
+ return stm32_rng_conceal_seed_error_cond_reset(pdata);
+ else
+ return stm32_rng_conceal_seed_error_sw_reset(pdata);
+};
+
+static int stm32_rng_read(struct udevice *dev, void *data, size_t len)
+{
+ int retval;
+ u32 sr, reg;
+ size_t increment;
+ struct stm32_rng_plat *pdata = dev_get_plat(dev);
+ uint tries = 0;
+
+ while (len > 0) {
+ retval = readl_poll_timeout(pdata->base + RNG_SR, sr,
+ sr, 10000);
+ if (retval) {
+ log_err("%s: Timeout RNG no data", __func__);
+ return retval;
+ }
+
+ if (sr != RNG_SR_DRDY) {
+ if (sr & RNG_SR_SEIS) {
+ retval = stm32_rng_conceal_seed_error(pdata);
+ tries++;
+ if (retval || tries > RNG_NB_RECOVER_TRIES) {
+ log_err("%s: Couldn't recover from seed error", __func__);
+ return -ENOTRECOVERABLE;
+ }
+
+ /* Start again */
+ continue;
+ }
+
+ if (sr & RNG_SR_CEIS) {
+ log_info("RNG clock too slow");
+ writel_relaxed(0, pdata->base + RNG_SR);
+ }
+ }
+
+ /*
+ * Once the DRDY bit is set, the RNG_DR register can
+ * be read up to four consecutive times.
+ */
+ reg = readl(pdata->base + RNG_DR);
+ /* Late seed error case: DR being 0 is an error status */
+ if (!reg) {
+ retval = stm32_rng_conceal_seed_error(pdata);
+ tries++;
+
+ if (retval || tries > RNG_NB_RECOVER_TRIES) {
+ log_err("%s: Couldn't recover from seed error", __func__);
+ return -ENOTRECOVERABLE;
+ }
+
+ /* Start again */
+ continue;
+ }
+
+ increment = min(len, sizeof(u32));
+ memcpy(data, ®, increment);
+ data += increment;
+ len -= increment;
+
+ tries = 0;
+ }
+
+ return 0;
+}
+
+static uint stm32_rng_clock_freq_restrain(struct stm32_rng_plat *pdata)
+{
+ ulong clock_rate = 0;
+ uint clock_div = 0;
+
+ clock_rate = clk_get_rate(&pdata->clk);
+
+ /*
+ * Get the exponent to apply on the CLKDIV field in RNG_CR register.
+ * No need to handle the case when clock-div > 0xF as it is physically
+ * impossible.
+ */
+ while ((clock_rate >> clock_div) > pdata->data->max_clock_rate)
+ clock_div++;
+
+ log_debug("RNG clk rate : %lu\n", clk_get_rate(&pdata->clk) >> clock_div);
+
+ return clock_div;
+}
+
+static int stm32_rng_init(struct stm32_rng_plat *pdata)
+{
+ int err;
+ u32 cr, sr;
+
+ err = clk_enable(&pdata->clk);
+ if (err)
+ return err;
+
+ cr = readl(pdata->base + RNG_CR);
+
+ /*
+ * Keep default RNG configuration if none was specified, that is when conf.cr is set to 0.
+ */
+ if (pdata->data->has_cond_reset && pdata->data->cr) {
+ uint clock_div = stm32_rng_clock_freq_restrain(pdata);
+
+ cr &= ~RNG_CR_CONFIG_MASK;
+ cr |= RNG_CR_CONDRST | (pdata->data->cr & RNG_CR_ENTROPY_SRC_MASK) |
+ (clock_div << RNG_CR_CLKDIV_SHIFT);
+ if (pdata->ced)
+ cr &= ~RNG_CR_CED;
+ else
+ cr |= RNG_CR_CED;
+ writel(cr, pdata->base + RNG_CR);
+
+ /* Health tests and noise control registers */
+ writel_relaxed(pdata->data->htcr, pdata->base + RNG_HTCR);
+ writel_relaxed(pdata->data->nscr & RNG_NSCR_MASK, pdata->base + RNG_NSCR);
+
+ cr &= ~RNG_CR_CONDRST;
+ cr |= RNG_CR_RNGEN;
+ writel(cr, pdata->base + RNG_CR);
+ err = readl_poll_timeout(pdata->base + RNG_CR, cr,
+ (!(cr & RNG_CR_CONDRST)), 10000);
+ if (err) {
+ log_err("%s: Timeout!", __func__);
+ return err;
+ }
+ } else {
+ if (pdata->data->has_cond_reset)
+ cr |= RNG_CR_CONDRST;
+
+ if (pdata->ced)
+ cr &= ~RNG_CR_CED;
+ else
+ cr |= RNG_CR_CED;
+
+ writel(cr, pdata->base + RNG_CR);
+
+ if (pdata->data->has_cond_reset)
+ cr &= ~RNG_CR_CONDRST;
+
+ cr |= RNG_CR_RNGEN;
+
+ writel(cr, pdata->base + RNG_CR);
+ }
+
+ /* clear error indicators */
+ writel(0, pdata->base + RNG_SR);
+
+ err = readl_poll_timeout(pdata->base + RNG_SR, sr,
+ sr & RNG_SR_DRDY, 10000);
+ if (err)
+ log_err("%s: Timeout!", __func__);
+
+ return err;
+}
+
+static int stm32_rng_cleanup(struct stm32_rng_plat *pdata)
+{
+ writel(0, pdata->base + RNG_CR);
+
+ return clk_disable(&pdata->clk);
+}
+
+static int stm32_rng_probe(struct udevice *dev)
+{
+ struct stm32_rng_plat *pdata = dev_get_plat(dev);
+
+ pdata->data = (struct stm32_rng_data *)dev_get_driver_data(dev);
+
+ reset_assert(&pdata->rst);
+ udelay(20);
+ reset_deassert(&pdata->rst);
+
+ return stm32_rng_init(pdata);
+}
+
+static int stm32_rng_remove(struct udevice *dev)
+{
+ struct stm32_rng_plat *pdata = dev_get_plat(dev);
+
+ return stm32_rng_cleanup(pdata);
+}
+
+static int stm32_rng_of_to_plat(struct udevice *dev)
+{
+ struct stm32_rng_plat *pdata = dev_get_plat(dev);
+ int err;
+
+ pdata->base = dev_read_addr(dev);
+ if (!pdata->base)
+ return -ENOMEM;
+
+ err = clk_get_by_index(dev, 0, &pdata->clk);
+ if (err)
+ return err;
+
+ err = reset_get_by_index(dev, 0, &pdata->rst);
+ if (err)
+ return err;
+
+ pdata->ced = dev_read_bool(dev, "clock-error-detect");
+
+ return 0;
+}
+
+static const struct dm_rng_ops stm32_rng_ops = {
+ .read = stm32_rng_read,
+};
+
+static const struct stm32_rng_data stm32mp13_rng_data = {
+ .has_cond_reset = true,
+ .max_clock_rate = 48000000,
+ .htcr = 0x969D,
+ .nscr = 0x2B5BB,
+ .cr = 0xF00D00,
+};
+
+static const struct stm32_rng_data stm32_rng_data = {
+ .has_cond_reset = false,
+ .max_clock_rate = 3000000,
+ /* Not supported */
+ .htcr = 0,
+ .nscr = 0,
+ .cr = 0,
+};
+
+static const struct udevice_id stm32_rng_match[] = {
+ {.compatible = "st,stm32mp13-rng", .data = (ulong)&stm32mp13_rng_data},
+ {.compatible = "st,stm32-rng", .data = (ulong)&stm32_rng_data},
+ {},
+};
+
+U_BOOT_DRIVER(stm32_rng) = {
+ .name = "stm32-rng",
+ .id = UCLASS_RNG,
+ .of_match = stm32_rng_match,
+ .ops = &stm32_rng_ops,
+ .probe = stm32_rng_probe,
+ .remove = stm32_rng_remove,
+ .plat_auto = sizeof(struct stm32_rng_plat),
+ .of_to_plat = stm32_rng_of_to_plat,
+};
diff --git a/drivers/rng/stm32mp1_rng.c b/drivers/rng/stm32mp1_rng.c
deleted file mode 100644
index 89da78c..0000000
--- a/drivers/rng/stm32mp1_rng.c
+++ /dev/null
@@ -1,198 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (c) 2019, Linaro Limited
- */
-
-#define LOG_CATEGORY UCLASS_RNG
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <log.h>
-#include <reset.h>
-#include <rng.h>
-#include <linux/bitops.h>
-#include <linux/delay.h>
-
-#include <asm/io.h>
-#include <linux/iopoll.h>
-#include <linux/kernel.h>
-
-#define RNG_CR 0x00
-#define RNG_CR_RNGEN BIT(2)
-#define RNG_CR_CED BIT(5)
-#define RNG_CR_CONDRST BIT(30)
-
-#define RNG_SR 0x04
-#define RNG_SR_SEIS BIT(6)
-#define RNG_SR_CEIS BIT(5)
-#define RNG_SR_SECS BIT(2)
-#define RNG_SR_DRDY BIT(0)
-
-#define RNG_DR 0x08
-
-struct stm32_rng_data {
- bool has_cond_reset;
-};
-
-struct stm32_rng_plat {
- fdt_addr_t base;
- struct clk clk;
- struct reset_ctl rst;
- const struct stm32_rng_data *data;
-};
-
-static int stm32_rng_read(struct udevice *dev, void *data, size_t len)
-{
- int retval, i;
- u32 sr, count, reg;
- size_t increment;
- struct stm32_rng_plat *pdata = dev_get_plat(dev);
-
- while (len > 0) {
- retval = readl_poll_timeout(pdata->base + RNG_SR, sr,
- sr & RNG_SR_DRDY, 10000);
- if (retval)
- return retval;
-
- if (sr & (RNG_SR_SEIS | RNG_SR_SECS)) {
- /* As per SoC TRM */
- clrbits_le32(pdata->base + RNG_SR, RNG_SR_SEIS);
- for (i = 0; i < 12; i++)
- readl(pdata->base + RNG_DR);
- if (readl(pdata->base + RNG_SR) & RNG_SR_SEIS) {
- log_err("RNG Noise");
- return -EIO;
- }
- /* start again */
- continue;
- }
-
- /*
- * Once the DRDY bit is set, the RNG_DR register can
- * be read four consecutive times.
- */
- count = 4;
- while (len && count) {
- reg = readl(pdata->base + RNG_DR);
- memcpy(data, ®, min(len, sizeof(u32)));
- increment = min(len, sizeof(u32));
- data += increment;
- len -= increment;
- count--;
- }
- }
-
- return 0;
-}
-
-static int stm32_rng_init(struct stm32_rng_plat *pdata)
-{
- int err;
- u32 cr, sr;
-
- err = clk_enable(&pdata->clk);
- if (err)
- return err;
-
- cr = readl(pdata->base + RNG_CR);
-
- /* Disable CED */
- cr |= RNG_CR_CED;
- if (pdata->data->has_cond_reset) {
- cr |= RNG_CR_CONDRST;
- writel(cr, pdata->base + RNG_CR);
- cr &= ~RNG_CR_CONDRST;
- writel(cr, pdata->base + RNG_CR);
- err = readl_poll_timeout(pdata->base + RNG_CR, cr,
- (!(cr & RNG_CR_CONDRST)), 10000);
- if (err)
- return err;
- }
-
- /* clear error indicators */
- writel(0, pdata->base + RNG_SR);
-
- cr |= RNG_CR_RNGEN;
- writel(cr, pdata->base + RNG_CR);
-
- err = readl_poll_timeout(pdata->base + RNG_SR, sr,
- sr & RNG_SR_DRDY, 10000);
- return err;
-}
-
-static int stm32_rng_cleanup(struct stm32_rng_plat *pdata)
-{
- writel(0, pdata->base + RNG_CR);
-
- return clk_disable(&pdata->clk);
-}
-
-static int stm32_rng_probe(struct udevice *dev)
-{
- struct stm32_rng_plat *pdata = dev_get_plat(dev);
-
- pdata->data = (struct stm32_rng_data *)dev_get_driver_data(dev);
-
- reset_assert(&pdata->rst);
- udelay(20);
- reset_deassert(&pdata->rst);
-
- return stm32_rng_init(pdata);
-}
-
-static int stm32_rng_remove(struct udevice *dev)
-{
- struct stm32_rng_plat *pdata = dev_get_plat(dev);
-
- return stm32_rng_cleanup(pdata);
-}
-
-static int stm32_rng_of_to_plat(struct udevice *dev)
-{
- struct stm32_rng_plat *pdata = dev_get_plat(dev);
- int err;
-
- pdata->base = dev_read_addr(dev);
- if (!pdata->base)
- return -ENOMEM;
-
- err = clk_get_by_index(dev, 0, &pdata->clk);
- if (err)
- return err;
-
- err = reset_get_by_index(dev, 0, &pdata->rst);
- if (err)
- return err;
-
- return 0;
-}
-
-static const struct dm_rng_ops stm32_rng_ops = {
- .read = stm32_rng_read,
-};
-
-static const struct stm32_rng_data stm32mp13_rng_data = {
- .has_cond_reset = true,
-};
-
-static const struct stm32_rng_data stm32_rng_data = {
- .has_cond_reset = false,
-};
-
-static const struct udevice_id stm32_rng_match[] = {
- {.compatible = "st,stm32mp13-rng", .data = (ulong)&stm32mp13_rng_data},
- {.compatible = "st,stm32-rng", .data = (ulong)&stm32_rng_data},
- {},
-};
-
-U_BOOT_DRIVER(stm32_rng) = {
- .name = "stm32-rng",
- .id = UCLASS_RNG,
- .of_match = stm32_rng_match,
- .ops = &stm32_rng_ops,
- .probe = stm32_rng_probe,
- .remove = stm32_rng_remove,
- .plat_auto = sizeof(struct stm32_rng_plat),
- .of_to_plat = stm32_rng_of_to_plat,
-};
diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c
index 0a3420b..1330482 100644
--- a/drivers/scsi/scsi.c
+++ b/drivers/scsi/scsi.c
@@ -14,6 +14,7 @@
#include <env.h>
#include <libata.h>
#include <log.h>
+#include <memalign.h>
#include <part.h>
#include <pci.h>
#include <scsi.h>
@@ -42,7 +43,7 @@
#endif
static struct scsi_cmd tempccb; /* temporary scsi command buffer */
-static unsigned char tempbuff[512]; /* temporary data buffer */
+DEFINE_CACHE_ALIGN_BUFFER(u8, tempbuff, 512); /* temporary data buffer */
#if !defined(CONFIG_DM_SCSI)
static int scsi_max_devs; /* number of highest available scsi device */
@@ -273,6 +274,18 @@
__func__, start, smallblks, buf_addr);
return blkcnt;
}
+
+#if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
+static int scsi_buffer_aligned(struct udevice *dev, struct bounce_buffer *state)
+{
+ struct scsi_ops *ops = scsi_get_ops(dev->parent);
+
+ if (ops->buffer_aligned)
+ return ops->buffer_aligned(dev->parent, state);
+
+ return 1;
+}
+#endif /* CONFIG_BOUNCE_BUFFER */
#endif
#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT) && \
@@ -361,6 +374,7 @@
pccb->cmd[0] = SCSI_RD_CAPAC10;
pccb->cmd[1] = pccb->lun << 5;
pccb->cmdlen = 10;
+ pccb->dma_dir = DMA_FROM_DEVICE;
pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
pccb->datalen = 8;
@@ -437,15 +451,15 @@
*/
static void scsi_init_dev_desc_priv(struct blk_desc *dev_desc)
{
+ memset(dev_desc, 0, sizeof(struct blk_desc));
dev_desc->target = 0xff;
dev_desc->lun = 0xff;
dev_desc->log2blksz =
LOG2_INVALID(typeof(dev_desc->log2blksz));
dev_desc->type = DEV_TYPE_UNKNOWN;
- dev_desc->vendor[0] = 0;
- dev_desc->product[0] = 0;
- dev_desc->revision[0] = 0;
- dev_desc->removable = false;
+#if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
+ dev_desc->bb = true;
+#endif /* CONFIG_BOUNCE_BUFFER */
}
#if !defined(CONFIG_DM_SCSI)
@@ -490,7 +504,7 @@
pccb->target = target;
pccb->lun = lun;
- pccb->pdata = (unsigned char *)&tempbuff;
+ pccb->pdata = tempbuff;
pccb->datalen = 512;
pccb->dma_dir = DMA_FROM_DEVICE;
scsi_setup_inquiry(pccb);
@@ -525,6 +539,7 @@
for (count = 0; count < 3; count++) {
pccb->datalen = 0;
+ pccb->dma_dir = DMA_NONE;
scsi_setup_test_unit_ready(pccb);
err = scsi_exec(dev, pccb);
if (!err)
@@ -593,6 +608,7 @@
bdesc->lun = lun;
bdesc->removable = bd.removable;
bdesc->type = bd.type;
+ bdesc->bb = bd.bb;
memcpy(&bdesc->vendor, &bd.vendor, sizeof(bd.vendor));
memcpy(&bdesc->product, &bd.product, sizeof(bd.product));
memcpy(&bdesc->revision, &bd.revision, sizeof(bd.revision));
@@ -719,6 +735,9 @@
static const struct blk_ops scsi_blk_ops = {
.read = scsi_read,
.write = scsi_write,
+#if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
+ .buffer_aligned = scsi_buffer_aligned,
+#endif /* CONFIG_BOUNCE_BUFFER */
};
U_BOOT_DRIVER(scsi_blk) = {
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 8c54bc9..6628a88 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -24,6 +24,21 @@
in the SPL stage (most drivers) or for choosing a default baudrate
in the absence of an environment setting (serial_mxc.c).
+config OF_SERIAL_BAUD
+ bool "Fetch serial baudrate from device tree"
+ depends on DM_SERIAL && SPL_ENV_SUPPORT
+ select DEFAULT_ENV_IS_RW
+ help
+ Select this to enable fetching and setting of the baudrate
+ configured in the DT. Replace the default baudrate with the DT
+ baudrate and also set it to the environment.
+
+config DEFAULT_ENV_IS_RW
+ bool "Make default environment as writable"
+ help
+ Select this to enable to make default environment writable. This
+ allows modifying the default environment.
+
config REQUIRE_SERIAL_CONSOLE
bool "Require a serial port for console"
# Running without a serial console is not supported by the
@@ -160,7 +175,6 @@
config SPL_DM_SERIAL
bool "Enable Driver Model for serial drivers in SPL"
depends on DM_SERIAL && SPL_DM
- select SYS_SPL_MALLOC_F
default y
help
Enable driver model for serial in SPL. This replaces
@@ -171,7 +185,6 @@
config TPL_DM_SERIAL
bool "Enable Driver Model for serial drivers in TPL"
depends on DM_SERIAL && TPL_DM
- select SYS_TPL_MALLOC_F
default y if TPL && DM_SERIAL
help
Enable driver model for serial in TPL. This replaces
@@ -485,8 +498,8 @@
config DEBUG_UART_BASE
hex "Base address of UART"
depends on DEBUG_UART
- default 0 if DEBUG_SBI_CONSOLE
- default 0 if DEBUG_UART_SANDBOX
+ default 0x0 if DEBUG_SBI_CONSOLE
+ default 0x0 if DEBUG_UART_SANDBOX
default 0xff000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQMP
default 0xe0000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQ
help
@@ -675,7 +688,7 @@
config COREBOOT_SERIAL_FROM_DBG2
bool "Obtain UART from ACPI tables"
depends on COREBOOT_SERIAL
- default y if !SPL
+ default y
help
Select this to try to find a DBG2 record in the ACPI tables, in the
event that coreboot does not provide information about the UART in the
@@ -1142,6 +1155,6 @@
config SYS_SDMR
hex "SDMR Value"
depends on MPC8XX_CONS
- default 0
+ default 0x0
endif
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 8328fcf..8305607 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -13,6 +13,7 @@
#include <ns16550.h>
#include <reset.h>
#include <serial.h>
+#include <spl.h>
#include <watchdog.h>
#include <asm/global_data.h>
#include <linux/err.h>
@@ -472,6 +473,10 @@
struct ns16550 *const com_port = dev_get_priv(dev);
struct ns16550_plat *plat = com_port->plat;
+ /* save code size */
+ if (!spl_in_proper())
+ return -ENOSYS;
+
info->type = SERIAL_CHIP_16550_COMPATIBLE;
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
info->addr_space = SERIAL_ADDRESS_SPACE_IO;
@@ -479,6 +484,7 @@
info->addr_space = SERIAL_ADDRESS_SPACE_MEMORY;
#endif
info->addr = plat->base;
+ info->size = plat->size;
info->reg_width = plat->reg_width;
info->reg_shift = plat->reg_shift;
info->reg_offset = plat->reg_offset;
@@ -487,7 +493,8 @@
return 0;
}
-static int ns16550_serial_assign_base(struct ns16550_plat *plat, fdt_addr_t base)
+static int ns16550_serial_assign_base(struct ns16550_plat *plat,
+ fdt_addr_t base, fdt_size_t size)
{
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
@@ -497,6 +504,7 @@
#else
plat->base = (unsigned long)map_physmem(base, 0, MAP_NOCACHE);
#endif
+ plat->size = size;
return 0;
}
@@ -507,6 +515,7 @@
struct ns16550 *const com_port = dev_get_priv(dev);
struct reset_ctl_bulk reset_bulk;
fdt_addr_t addr;
+ fdt_addr_t size;
int ret;
/*
@@ -514,8 +523,8 @@
* or via a PCI bridge, assign plat->base before probing hardware.
*/
if (device_is_on_pci_bus(dev)) {
- addr = devfdt_get_addr_pci(dev);
- ret = ns16550_serial_assign_base(plat, addr);
+ addr = devfdt_get_addr_pci(dev, &size);
+ ret = ns16550_serial_assign_base(plat, addr, size);
if (ret)
return ret;
}
@@ -542,12 +551,14 @@
{
struct ns16550_plat *plat = dev_get_plat(dev);
const u32 port_type = dev_get_driver_data(dev);
+ fdt_size_t size = 0;
fdt_addr_t addr;
struct clk clk;
int err;
- addr = dev_read_addr(dev);
- err = ns16550_serial_assign_base(plat, addr);
+ addr = spl_in_proper() ? dev_read_addr_size(dev, &size) :
+ dev_read_addr(dev);
+ err = ns16550_serial_assign_base(plat, addr, size);
if (err && !device_is_on_pci_bus(dev))
return err;
diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c
index f400381..f6ac3d2 100644
--- a/drivers/serial/sandbox.c
+++ b/drivers/serial/sandbox.c
@@ -280,7 +280,7 @@
.flags = DM_FLAG_PRE_RELOC,
};
-#if CONFIG_IS_ENABLED(OF_REAL)
+#if CONFIG_IS_ENABLED(OF_REAL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static const struct sandbox_serial_plat platdata_non_fdt = {
.colour = -1,
};
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 067fae2..e4fa393 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -151,15 +151,65 @@
#ifdef CONFIG_REQUIRE_SERIAL_CONSOLE
panic_str("No serial driver found");
#endif
+ gd->cur_serial_dev = NULL;
}
#endif /* CONFIG_SERIAL_PRESENT */
+/**
+ * check_valid_baudrate() - Check whether baudrate is valid or not
+ *
+ * @baud: baud rate to check
+ * Return: 0 if OK, -ve on error
+ */
+static int check_valid_baudrate(int baud)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(baudrate_table); ++i) {
+ if (baud == baudrate_table[i])
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+int fetch_baud_from_dtb(void)
+{
+ int baud_value, ret;
+
+ baud_value = ofnode_read_baud();
+ ret = check_valid_baudrate(baud_value);
+ if (ret)
+ return ret;
+
+ return baud_value;
+}
+
/* Called prior to relocation */
int serial_init(void)
{
#if CONFIG_IS_ENABLED(SERIAL_PRESENT)
serial_find_console_or_panic();
gd->flags |= GD_FLG_SERIAL_READY;
+
+ if (IS_ENABLED(CONFIG_OF_SERIAL_BAUD)) {
+ int ret = 0;
+ char *ptr = (char*)&default_environment[0];
+
+ /*
+ * Fetch the baudrate from the dtb and update the value in the
+ * default environment.
+ */
+ ret = fetch_baud_from_dtb();
+ if (ret != -EINVAL && ret != -EFAULT) {
+ gd->baudrate = ret;
+
+ while (*ptr != '\0' && *(ptr + 1) != '\0')
+ ptr++;
+ ptr += 2;
+ sprintf(ptr, "baudrate=%d", gd->baudrate);
+ }
+ }
serial_setbrg();
#endif
@@ -181,6 +231,16 @@
return serial_init();
}
+static void _serial_flush(struct udevice *dev)
+{
+ struct dm_serial_ops *ops = serial_get_ops(dev);
+
+ if (!ops->pending)
+ return;
+ while (ops->pending(dev, false) > 0)
+ ;
+}
+
static void _serial_putc(struct udevice *dev, char ch)
{
struct dm_serial_ops *ops = serial_get_ops(dev);
@@ -192,6 +252,9 @@
do {
err = ops->putc(dev, ch);
} while (err == -EAGAIN);
+
+ if (IS_ENABLED(CONFIG_CONSOLE_FLUSH_ON_NEWLINE) && ch == '\n')
+ _serial_flush(dev);
}
static int __serial_puts(struct udevice *dev, const char *str, size_t len)
@@ -230,22 +293,13 @@
if (*newline && __serial_puts(dev, "\r\n", 2))
return;
+ if (IS_ENABLED(CONFIG_CONSOLE_FLUSH_ON_NEWLINE) && *newline)
+ _serial_flush(dev);
+
str += len + !!*newline;
} while (*str);
}
-#ifdef CONFIG_CONSOLE_FLUSH_SUPPORT
-static void _serial_flush(struct udevice *dev)
-{
- struct dm_serial_ops *ops = serial_get_ops(dev);
-
- if (!ops->pending)
- return;
- while (ops->pending(dev, false) > 0)
- ;
-}
-#endif
-
static int __serial_getc(struct udevice *dev)
{
struct dm_serial_ops *ops = serial_get_ops(dev);
@@ -507,28 +561,6 @@
#endif
int ret;
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- if (ops->setbrg)
- ops->setbrg += gd->reloc_off;
- if (ops->getc)
- ops->getc += gd->reloc_off;
- if (ops->putc)
- ops->putc += gd->reloc_off;
- if (ops->pending)
- ops->pending += gd->reloc_off;
- if (ops->clear)
- ops->clear += gd->reloc_off;
- if (ops->getconfig)
- ops->getconfig += gd->reloc_off;
- if (ops->setconfig)
- ops->setconfig += gd->reloc_off;
-#if CFG_POST & CFG_SYS_POST_UART
- if (ops->loop)
- ops->loop += gd->reloc_off;
-#endif
- if (ops->getinfo)
- ops->getinfo += gd->reloc_off;
-#endif
/* Set the baud rate */
if (ops->setbrg) {
ret = ops->setbrg(dev, gd->baudrate);
@@ -541,7 +573,7 @@
return 0;
memset(&sdev, '\0', sizeof(sdev));
- strncpy(sdev.name, dev->name, sizeof(sdev.name));
+ strlcpy(sdev.name, dev->name, sizeof(sdev.name));
sdev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_DM;
sdev.priv = dev;
sdev.putc = serial_stub_putc;
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 9a380d7..787edd5 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -142,23 +142,6 @@
*/
void serial_register(struct serial_device *dev)
{
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
- if (dev->start)
- dev->start += gd->reloc_off;
- if (dev->stop)
- dev->stop += gd->reloc_off;
- if (dev->setbrg)
- dev->setbrg += gd->reloc_off;
- if (dev->getc)
- dev->getc += gd->reloc_off;
- if (dev->tstc)
- dev->tstc += gd->reloc_off;
- if (dev->putc)
- dev->putc += gd->reloc_off;
- if (dev->puts)
- dev->puts += gd->reloc_off;
-#endif
-
dev->next = serial_devices;
serial_devices = dev;
}
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index 51e66ab..ce08a6b 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -480,18 +480,30 @@
{
#if CONFIG_IS_ENABLED(CLK)
struct clk per_clk;
+ struct clk ipg_clk;
int ret;
ret = clk_get_by_name(dev, "per", &per_clk);
if (!ret) {
ret = clk_enable(&per_clk);
if (ret) {
- dev_err(dev, "Failed to get per clk: %d\n", ret);
+ dev_err(dev, "Failed to enable per clk: %d\n", ret);
return ret;
}
} else {
debug("%s: Failed to get per clk: %d\n", __func__, ret);
}
+
+ ret = clk_get_by_name(dev, "ipg", &ipg_clk);
+ if (!ret) {
+ ret = clk_enable(&ipg_clk);
+ if (ret) {
+ dev_err(dev, "Failed to enable ipg clk: %d\n", ret);
+ return ret;
+ }
+ } else {
+ debug("%s: Failed to get ipg clk: %d\n", __func__, ret);
+ }
#endif
if (is_lpuart32(dev))
diff --git a/drivers/serial/serial_meson.c b/drivers/serial/serial_meson.c
index 934de2a..be5f380 100644
--- a/drivers/serial/serial_meson.c
+++ b/drivers/serial/serial_meson.c
@@ -232,6 +232,7 @@
static const struct udevice_id meson_serial_ids[] = {
{ .compatible = "amlogic,meson-uart" },
{ .compatible = "amlogic,meson-gx-uart" },
+ { .compatible = "amlogic,meson-a1-uart" },
{ }
};
diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c
index 2dffa14..f146f2b 100644
--- a/drivers/serial/serial_mtk.c
+++ b/drivers/serial/serial_mtk.c
@@ -19,6 +19,7 @@
#include <asm/io.h>
#include <asm/types.h>
#include <linux/err.h>
+#include <linux/printk.h>
struct mtk_serial_regs {
u32 rbr;
diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c
index 26310b0..49ced8f 100644
--- a/drivers/serial/serial_omap.c
+++ b/drivers/serial/serial_omap.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments' OMAP serial driver
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index 7aeb8c0..7d04dcf 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -7,7 +7,6 @@
* based on drivers/serial/s3c64xx.c
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
@@ -21,32 +20,39 @@
#include <serial.h>
#include <clk.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
PORT_S5P = 0,
PORT_S5L
};
+#define UFCON_FIFO_EN BIT(0)
+#define UFCON_RX_FIFO_RESET BIT(1)
+#define UMCON_RESET_VAL 0x0
+#define ULCON_WORD_8_BIT 0x3
+#define UCON_RX_IRQ_OR_POLLING BIT(0)
+#define UCON_TX_IRQ_OR_POLLING BIT(2)
+#define UCON_RX_ERR_IRQ_EN BIT(6)
+#define UCON_TX_IRQ_LEVEL BIT(9)
+
#define S5L_RX_FIFO_COUNT_SHIFT 0
#define S5L_RX_FIFO_COUNT_MASK (0xf << S5L_RX_FIFO_COUNT_SHIFT)
-#define S5L_RX_FIFO_FULL (1 << 8)
+#define S5L_RX_FIFO_FULL BIT(8)
#define S5L_TX_FIFO_COUNT_SHIFT 4
#define S5L_TX_FIFO_COUNT_MASK (0xf << S5L_TX_FIFO_COUNT_SHIFT)
-#define S5L_TX_FIFO_FULL (1 << 9)
+#define S5L_TX_FIFO_FULL BIT(9)
#define S5P_RX_FIFO_COUNT_SHIFT 0
#define S5P_RX_FIFO_COUNT_MASK (0xff << S5P_RX_FIFO_COUNT_SHIFT)
-#define S5P_RX_FIFO_FULL (1 << 8)
+#define S5P_RX_FIFO_FULL BIT(8)
#define S5P_TX_FIFO_COUNT_SHIFT 16
#define S5P_TX_FIFO_COUNT_MASK (0xff << S5P_TX_FIFO_COUNT_SHIFT)
-#define S5P_TX_FIFO_FULL (1 << 24)
+#define S5P_TX_FIFO_FULL BIT(24)
/* Information about a serial port */
struct s5p_serial_plat {
- struct s5p_uart *reg; /* address of registers in physical memory */
- u8 reg_width; /* register width */
- u8 port_id; /* uart port number */
+ struct s5p_uart *reg; /* address of registers in physical memory */
+ u8 reg_width; /* register width */
+ u8 port_id; /* uart port number */
u8 rx_fifo_count_shift;
u8 tx_fifo_count_shift;
u32 rx_fifo_count_mask;
@@ -59,7 +65,7 @@
* The coefficient, used to calculate the baudrate on S5P UARTs is
* calculated as
* C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
- * however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1,
+ * however, section 31.6.11 of the datasheet doesn't recommend using 1 for 1,
* 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
*/
static const int udivslot[] = {
@@ -83,13 +89,15 @@
static void __maybe_unused s5p_serial_init(struct s5p_uart *uart)
{
- /* enable FIFOs, auto clear Rx FIFO */
- writel(0x3, &uart->ufcon);
- writel(0, &uart->umcon);
- /* 8N1 */
- writel(0x3, &uart->ulcon);
+ /* Enable FIFOs, auto clear Rx FIFO */
+ writel(UFCON_FIFO_EN | UFCON_RX_FIFO_RESET, &uart->ufcon);
+ /* No auto flow control, disable nRTS signal */
+ writel(UMCON_RESET_VAL, &uart->umcon);
+ /* 8N1, no parity bit */
+ writel(ULCON_WORD_8_BIT, &uart->ulcon);
/* No interrupts, no DMA, pure polling */
- writel(0x245, &uart->ucon);
+ writel(UCON_RX_IRQ_OR_POLLING | UCON_TX_IRQ_OR_POLLING |
+ UCON_RX_ERR_IRQ_EN | UCON_TX_IRQ_LEVEL, &uart->ucon);
}
static void __maybe_unused s5p_serial_baud(struct s5p_uart *uart, u8 reg_width,
@@ -118,7 +126,7 @@
#if IS_ENABLED(CONFIG_CLK_EXYNOS) || IS_ENABLED(CONFIG_ARCH_APPLE)
struct clk clk;
- u32 ret;
+ int ret;
ret = clk_get_by_index(dev, 1, &clk);
if (ret < 0)
@@ -213,16 +221,13 @@
{
struct s5p_serial_plat *plat = dev_get_plat(dev);
const ulong port_type = dev_get_driver_data(dev);
- fdt_addr_t addr;
- addr = dev_read_addr(dev);
- if (addr == FDT_ADDR_T_NONE)
+ plat->reg = dev_read_addr_ptr(dev);
+ if (!plat->reg)
return -EINVAL;
- plat->reg = (struct s5p_uart *)addr;
plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1);
- plat->port_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "id", dev_seq(dev));
+ plat->port_id = dev_read_u8_default(dev, "id", dev_seq(dev));
if (port_type == PORT_S5L) {
plat->rx_fifo_count_shift = S5L_RX_FIFO_COUNT_SHIFT;
@@ -244,10 +249,10 @@
}
static const struct dm_serial_ops s5p_serial_ops = {
- .putc = s5p_serial_putc,
- .pending = s5p_serial_pending,
- .getc = s5p_serial_getc,
- .setbrg = s5p_serial_setbrg,
+ .putc = s5p_serial_putc,
+ .pending = s5p_serial_pending,
+ .getc = s5p_serial_getc,
+ .setbrg = s5p_serial_setbrg,
};
static const struct udevice_id s5p_serial_ids[] = {
@@ -257,13 +262,13 @@
};
U_BOOT_DRIVER(serial_s5p) = {
- .name = "serial_s5p",
- .id = UCLASS_SERIAL,
- .of_match = s5p_serial_ids,
- .of_to_plat = s5p_serial_of_to_plat,
+ .name = "serial_s5p",
+ .id = UCLASS_SERIAL,
+ .of_match = s5p_serial_ids,
+ .of_to_plat = s5p_serial_of_to_plat,
.plat_auto = sizeof(struct s5p_serial_plat),
- .probe = s5p_serial_probe,
- .ops = &s5p_serial_ops,
+ .probe = s5p_serial_probe,
+ .ops = &s5p_serial_ops,
};
#endif
@@ -291,10 +296,12 @@
struct s5p_uart *uart = (struct s5p_uart *)CONFIG_VAL(DEBUG_UART_BASE);
#if IS_ENABLED(CONFIG_ARCH_APPLE)
- while (readl(&uart->ufstat) & S5L_TX_FIFO_FULL);
+ while (readl(&uart->ufstat) & S5L_TX_FIFO_FULL)
+ ;
writel(ch, &uart->utxh);
#else
- while (readl(&uart->ufstat) & S5P_TX_FIFO_FULL);
+ while (readl(&uart->ufstat) & S5P_TX_FIFO_FULL)
+ ;
writeb(ch, &uart->utxh);
#endif
}
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 20cda5d..e4cc4ee 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -6,17 +6,18 @@
* Copyright (C) 2002 - 2008 Paul Mundt
*/
-#include <common.h>
-#include <errno.h>
-#include <clk.h>
-#include <dm.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/processor.h>
-#include <serial.h>
-#include <linux/compiler.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
#include <dm/platform_data/serial_sh.h>
+#include <errno.h>
+#include <linux/compiler.h>
#include <linux/delay.h>
+#include <reset.h>
+#include <serial.h>
#include "serial_sh.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -58,8 +59,10 @@
sci_out(port, SCSPTR, 0x0003);
#endif
+#if IS_ENABLED(CONFIG_RCAR_GEN2) || IS_ENABLED(CONFIG_RCAR_GEN3) || IS_ENABLED(CONFIG_RCAR_GEN4)
if (port->type == PORT_HSCIF)
sci_out(port, HSSRR, HSSRR_SRE | HSSRR_SRCYC8);
+#endif
}
static void
@@ -77,10 +80,22 @@
static void handle_error(struct uart_port *port)
{
- sci_in(port, SCxSR);
- sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
+ /*
+ * Most errors are cleared by resetting the relevant error bits to zero
+ * in the FSR & LSR registers. For each register, a read followed by a
+ * write is needed according to the relevant datasheets.
+ */
+ unsigned short status = sci_in(port, SCxSR);
+ sci_out(port, SCxSR, status & ~SCxSR_ERRORS(port));
sci_in(port, SCLSR);
sci_out(port, SCLSR, 0x00);
+
+ /*
+ * To clear framing errors, we also need to read and discard a
+ * character.
+ */
+ if ((port->type != PORT_SCI) && (status & SCIF_FER))
+ sci_in(port, SCxRDR);
}
static int serial_raw_putc(struct uart_port *port, const char c)
@@ -185,12 +200,24 @@
{
struct sh_serial_plat *plat = dev_get_plat(dev);
struct uart_port *priv = dev_get_priv(dev);
+ struct reset_ctl rst;
+ int ret;
priv->membase = (unsigned char *)plat->base;
priv->mapbase = plat->base;
priv->type = plat->type;
priv->clk_mode = plat->clk_mode;
+ /* De-assert the module reset if it is defined. */
+ ret = reset_get_by_index(dev, 0, &rst);
+ if (!ret) {
+ ret = reset_deassert(&rst);
+ if (ret < 0) {
+ dev_err(dev, "failed to de-assert reset line\n");
+ return ret;
+ }
+ }
+
sh_serial_init_generic(priv);
return 0;
@@ -207,6 +234,7 @@
static const struct udevice_id sh_serial_id[] ={
{.compatible = "renesas,sci", .data = PORT_SCI},
{.compatible = "renesas,scif", .data = PORT_SCIF},
+ {.compatible = "renesas,scif-r9a07g044", .data = PORT_SCIFA},
{.compatible = "renesas,scifa", .data = PORT_SCIFA},
{.compatible = "renesas,hscif", .data = PORT_HSCIF},
{}
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 149ec1f..58c2d22 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -90,7 +90,7 @@
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
# define SCIF_ORER 0x0001 /* overrun error bit */
#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_64) || \
- defined(CONFIG_R7S72100)
+ defined(CONFIG_R7S72100) || defined(CONFIG_RZG2L)
# if defined(CFG_SCIF_A)
# define SCIF_ORER 0x0200
# else
@@ -312,6 +312,9 @@
sh4_scif_offset, sh4_scif_size)
#define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
+#elif defined(CONFIG_RZG2L)
+#define SCIF_FNS(reg_name, reg_offset, reg_size) \
+ CPU_SCIF_FNS(reg_name, reg_offset, reg_size)
#else
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
sh4_sci_offset, sh4_sci_size, \
@@ -387,6 +390,20 @@
#else
SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
#endif
+#elif defined(CONFIG_RZG2L)
+SCIF_FNS(SCSMR, 0x00, 16)
+SCIF_FNS(SCBRR, 0x02, 8)
+SCIF_FNS(SCSCR, 0x04, 16)
+SCIF_FNS(SCxTDR, 0x06, 8)
+SCIF_FNS(SCxSR, 0x08, 16)
+SCIF_FNS(SCxRDR, 0x0A, 8)
+SCIF_FNS(SCFCR, 0x0C, 16)
+SCIF_FNS(SCFDR, 0x0E, 16)
+SCIF_FNS(SCSPTR, 0x10, 16)
+SCIF_FNS(SCLSR, 0x12, 16)
+SCIF_FNS(SCSEMR, 0x14, 8)
+SCIF_FNS(SCxTCR, 0x16, 16)
+SCIF_FNS(DL, 0x00, 0)
#else
/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
/* name off sz off sz off sz off sz off sz*/
diff --git a/drivers/sm/Kconfig b/drivers/sm/Kconfig
new file mode 100644
index 0000000..926af28
--- /dev/null
+++ b/drivers/sm/Kconfig
@@ -0,0 +1,8 @@
+config SM
+ bool "Enable Secure Monitor driver support"
+
+config MESON_SM
+ bool "Amlogic Secure Monitor driver"
+ select SM
+ help
+ Say y here to enable the Amlogic secure monitor driver.
diff --git a/drivers/sm/Makefile b/drivers/sm/Makefile
new file mode 100644
index 0000000..da81ee8
--- /dev/null
+++ b/drivers/sm/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-y += sm-uclass.o
+obj-$(CONFIG_SANDBOX) += sandbox-sm.o
+obj-$(CONFIG_MESON_SM) += meson-sm.o
diff --git a/drivers/sm/meson-sm.c b/drivers/sm/meson-sm.c
new file mode 100644
index 0000000..15b3b0e
--- /dev/null
+++ b/drivers/sm/meson-sm.c
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 SberDevices, Inc.
+ *
+ * Author: Alexey Romanov <avromanov@salutedevices.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <regmap.h>
+#include <sm.h>
+#include <sm-uclass.h>
+#include <stdlib.h>
+#include <syscon.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#include <meson/sm.h>
+#include <linux/bitfield.h>
+#include <linux/err.h>
+#include <linux/sizes.h>
+
+struct meson_sm_cmd {
+ u32 smc_id;
+};
+
+#define SET_CMD(index, id) \
+ [index] = { \
+ .smc_id = (id), \
+ }
+
+struct meson_sm_data {
+ u32 cmd_get_shmem_in;
+ u32 cmd_get_shmem_out;
+ unsigned int shmem_size;
+ struct meson_sm_cmd cmd[];
+};
+
+struct meson_sm_priv {
+ void *sm_shmem_in;
+ void *sm_shmem_out;
+ const struct meson_sm_data *data;
+};
+
+static unsigned long __meson_sm_call(u32 cmd, const struct pt_regs *args)
+{
+ struct pt_regs r = *args;
+
+ r.regs[0] = cmd;
+ smc_call(&r);
+
+ return r.regs[0];
+};
+
+static u32 meson_sm_get_cmd(const struct meson_sm_data *data,
+ u32 cmd_index)
+{
+ struct meson_sm_cmd cmd;
+
+ if (cmd_index >= MESON_SMC_CMD_COUNT)
+ return 0;
+
+ cmd = data->cmd[cmd_index];
+ return cmd.smc_id;
+}
+
+static int meson_sm_call(struct udevice *dev, u32 cmd_index, s32 *retval,
+ struct pt_regs *args)
+{
+ struct meson_sm_priv *priv = dev_get_priv(dev);
+ u32 cmd, ret;
+
+ cmd = meson_sm_get_cmd(priv->data, cmd_index);
+ if (!cmd)
+ return -ENOENT;
+
+ ret = __meson_sm_call(cmd, args);
+ if (retval)
+ *retval = ret;
+
+ return 0;
+}
+
+static int meson_sm_call_read(struct udevice *dev, void *buffer, size_t size,
+ u32 cmd_index, struct pt_regs *args)
+{
+ struct meson_sm_priv *priv = dev_get_priv(dev);
+ s32 nbytes;
+ int ret;
+
+ if (!buffer || size > priv->data->shmem_size)
+ return -EINVAL;
+
+ ret = meson_sm_call(dev, cmd_index, &nbytes, args);
+ if (ret)
+ return ret;
+
+ if (nbytes < 0 || nbytes > size)
+ return -ENOBUFS;
+
+ /* In some cases (for example GET_CHIP_ID command),
+ * SMC doesn't return the number of bytes read, even
+ * though the bytes were actually read into sm_shmem_out.
+ * So this check is needed.
+ */
+ ret = nbytes;
+ if (!nbytes)
+ nbytes = size;
+
+ memcpy(buffer, priv->sm_shmem_out, nbytes);
+
+ return ret;
+}
+
+static int meson_sm_call_write(struct udevice *dev, void *buffer, size_t size,
+ u32 cmd_index, struct pt_regs *args)
+{
+ struct meson_sm_priv *priv = dev_get_priv(dev);
+ s32 nbytes;
+ int ret;
+
+ if (!buffer || size > priv->data->shmem_size)
+ return -EINVAL;
+
+ memcpy(priv->sm_shmem_in, buffer, size);
+
+ ret = meson_sm_call(dev, cmd_index, &nbytes, args);
+ if (ret)
+ return ret;
+
+ if (nbytes <= 0 || nbytes > size)
+ return -EIO;
+
+ return nbytes;
+}
+
+static int meson_sm_probe(struct udevice *dev)
+{
+ struct meson_sm_priv *priv = dev_get_priv(dev);
+ struct pt_regs regs = { 0 };
+
+ priv->data = (struct meson_sm_data *)dev_get_driver_data(dev);
+ if (!priv->data)
+ return -EINVAL;
+
+ priv->sm_shmem_in =
+ (void *)__meson_sm_call(priv->data->cmd_get_shmem_in, ®s);
+
+ if (!priv->sm_shmem_in)
+ return -ENOMEM;
+
+ priv->sm_shmem_out =
+ (void *)__meson_sm_call(priv->data->cmd_get_shmem_out, ®s);
+
+ if (!priv->sm_shmem_out)
+ return -ENOMEM;
+
+ pr_debug("meson sm driver probed\n"
+ "shmem_in addr: 0x%p, shmem_out addr: 0x%p\n",
+ priv->sm_shmem_in,
+ priv->sm_shmem_out);
+
+ return 0;
+}
+
+static const struct meson_sm_data meson_sm_gxbb_data = {
+ .cmd_get_shmem_in = 0x82000020,
+ .cmd_get_shmem_out = 0x82000021,
+ .shmem_size = SZ_4K,
+ .cmd = {
+ SET_CMD(MESON_SMC_CMD_EFUSE_READ, 0x82000030),
+ SET_CMD(MESON_SMC_CMD_EFUSE_WRITE, 0x82000031),
+ SET_CMD(MESON_SMC_CMD_CHIP_ID_GET, 0x82000044),
+ SET_CMD(MESON_SMC_CMD_PWRDM_SET, 0x82000093),
+ },
+};
+
+static const struct udevice_id meson_sm_ids[] = {
+ {
+ .compatible = "amlogic,meson-gxbb-sm",
+ .data = (ulong)&meson_sm_gxbb_data,
+ },
+ { }
+};
+
+static const struct sm_ops sm_ops = {
+ .sm_call = meson_sm_call,
+ .sm_call_read = meson_sm_call_read,
+ .sm_call_write = meson_sm_call_write,
+};
+
+U_BOOT_DRIVER(meson_sm) = {
+ .name = "meson_sm",
+ .id = UCLASS_SM,
+ .of_match = meson_sm_ids,
+ .probe = meson_sm_probe,
+ .bind = dm_scan_fdt_dev,
+ .priv_auto = sizeof(struct meson_sm_priv),
+ .ops = &sm_ops,
+};
diff --git a/drivers/sm/sandbox-sm.c b/drivers/sm/sandbox-sm.c
new file mode 100644
index 0000000..109ddb2
--- /dev/null
+++ b/drivers/sm/sandbox-sm.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 SberDevices, Inc.
+ *
+ * Author: Alexey Romanov <avromanov@salutedevices.com>
+ */
+
+#include <common.h>
+#include <sm.h>
+#include <sm-uclass.h>
+#include <sandbox-sm.h>
+#include <asm/ptrace.h>
+#include <dm/device.h>
+#include <linux/sizes.h>
+
+static u8 test_buffer[SZ_4K];
+
+static int sandbox_sm_call(struct udevice *dev, u32 cmd_index, s32 *smc_ret,
+ struct pt_regs *args)
+{
+ if (cmd_index >= SANDBOX_SMC_CMD_COUNT)
+ return -EINVAL;
+
+ if (smc_ret)
+ *smc_ret = 0;
+
+ return 0;
+}
+
+static int sandbox_sm_call_read(struct udevice *dev, void *buffer, size_t size,
+ u32 cmd_index, struct pt_regs *args)
+{
+ if (cmd_index >= SANDBOX_SMC_CMD_COUNT || !buffer)
+ return -EINVAL;
+
+ if (size > sizeof(test_buffer))
+ return -EINVAL;
+
+ memcpy(buffer, test_buffer, size);
+
+ return size;
+}
+
+static int sandbox_sm_call_write(struct udevice *dev, void *buffer, size_t size,
+ u32 cmd_index, struct pt_regs *args)
+{
+ if (cmd_index >= SANDBOX_SMC_CMD_COUNT || !buffer)
+ return -EINVAL;
+
+ if (size > sizeof(test_buffer))
+ return -EINVAL;
+
+ memcpy(test_buffer, buffer, size);
+
+ return size;
+}
+
+static const struct udevice_id sandbox_sm_ids[] = {
+ {
+ .compatible = "sandbox,sm",
+ },
+ {},
+};
+
+static const struct sm_ops sandbox_sm_ops = {
+ .sm_call = sandbox_sm_call,
+ .sm_call_read = sandbox_sm_call_read,
+ .sm_call_write = sandbox_sm_call_write,
+};
+
+U_BOOT_DRIVER(sm) = {
+ .name = "sm",
+ .id = UCLASS_SM,
+ .of_match = sandbox_sm_ids,
+ .ops = &sandbox_sm_ops,
+};
diff --git a/drivers/sm/sm-uclass.c b/drivers/sm/sm-uclass.c
new file mode 100644
index 0000000..6a8b702
--- /dev/null
+++ b/drivers/sm/sm-uclass.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 SberDevices, Inc.
+ *
+ * Author: Alexey Romanov <avromanov@salutedevices.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sm-uclass.h>
+
+static const struct sm_ops *get_sm_ops(struct udevice *dev)
+{
+ return (const struct sm_ops *)dev->driver->ops;
+}
+
+int sm_call(struct udevice *dev, u32 cmd, s32 *ret, struct pt_regs *args)
+{
+ const struct sm_ops *ops = get_sm_ops(dev);
+
+ if (ops->sm_call)
+ return ops->sm_call(dev, cmd, ret, args);
+
+ return -ENOSYS;
+}
+
+int sm_call_read(struct udevice *dev, void *buffer, size_t size,
+ u32 cmd, struct pt_regs *args)
+{
+ const struct sm_ops *ops = get_sm_ops(dev);
+
+ if (ops->sm_call_read)
+ return ops->sm_call_read(dev, buffer, size, cmd,
+ args);
+
+ return -ENOSYS;
+}
+
+int sm_call_write(struct udevice *dev, void *buffer, size_t size,
+ u32 cmd, struct pt_regs *args)
+{
+ const struct sm_ops *ops = get_sm_ops(dev);
+
+ if (ops->sm_call_write)
+ return ops->sm_call_write(dev, buffer, size, cmd,
+ args);
+
+ return -ENOSYS;
+}
+
+UCLASS_DRIVER(sm) = {
+ .name = "sm",
+ .id = UCLASS_SM,
+};
diff --git a/drivers/soc/soc-uclass.c b/drivers/soc/soc-uclass.c
index dfad32d..8b3044f 100644
--- a/drivers/soc/soc-uclass.c
+++ b/drivers/soc/soc-uclass.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2020 - Texas Instruments Incorporated - http://www.ti.com/
+ * (C) Copyright 2020 - Texas Instruments Incorporated - https://www.ti.com/
* Dave Gerlach <d-gerlach@ti.com>
*/
diff --git a/drivers/soc/soc_sandbox.c b/drivers/soc/soc_sandbox.c
index 5c82ad8..15fdd99 100644
--- a/drivers/soc/soc_sandbox.c
+++ b/drivers/soc/soc_sandbox.c
@@ -2,7 +2,7 @@
/*
* Sandbox driver for the SOC uclass
*
- * (C) Copyright 2020 - Texas Instruments Incorporated - http://www.ti.com/
+ * (C) Copyright 2020 - Texas Instruments Incorporated - https://www.ti.com/
* Dave Gerlach <d-gerlach@ti.com>
*/
diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index b720131..355a536 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
* Dave Gerlach <d-gerlach@ti.com>
*/
diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c
index f110d78..7a2fbb0 100644
--- a/drivers/soc/ti/k3-navss-ringacc.c
+++ b/drivers/soc/ti/k3-navss-ringacc.c
@@ -2,7 +2,7 @@
/*
* TI K3 AM65x NAVSS Ring accelerator Manager (RA) subsystem driver
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
*/
#include <common.h>
@@ -21,6 +21,7 @@
#include <linux/compat.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
+#include <linux/printk.h>
#include <linux/soc/ti/k3-navss-ringacc.h>
#include <linux/soc/ti/ti_sci_protocol.h>
#include <linux/soc/ti/cppi5.h>
@@ -986,10 +987,10 @@
if (!base_cfg)
return -EINVAL;
- base_rt = (uint32_t *)devfdt_get_addr_name(dev, "rt");
+ base_rt = dev_read_addr_name_ptr(dev, "rt");
pr_debug("rt %p\n", base_rt);
- if (IS_ERR(base_rt))
- return PTR_ERR(base_rt);
+ if (!base_rt)
+ return -EINVAL;
ringacc->rings = devm_kzalloc(dev,
sizeof(*ringacc->rings) *
@@ -1044,9 +1045,9 @@
ringacc->tisci = data->tisci;
ringacc->tisci_dev_id = data->tisci_dev_id;
- base_rt = (uint32_t *)devfdt_get_addr_name(dev, "ringrt");
- if (IS_ERR(base_rt))
- return base_rt;
+ base_rt = dev_read_addr_name_ptr(dev, "ringrt");
+ if (!base_rt)
+ return ERR_PTR(-EINVAL);
ringacc->rings = devm_kzalloc(dev,
sizeof(*ringacc->rings) *
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 854b8b8..69b184b 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -251,6 +251,15 @@
Enable the QSPI driver for Microchip FPGA QSPI controllers.
This driver can be used on Polarfire SoC.
+config MESON_SPIFC_A1
+ bool "Amlogic Meson A1 SPI Flash Controller driver"
+ depends on ARCH_MESON
+ help
+ Enable the Amlogic A1 SPI Flash Controller (SPIFC) driver.
+ This driver can be used to access the SPI NOR/NAND flash chips
+ with STR mode frequency up to 98MHz. Dual and quad modes are
+ supported by controller.
+
config MPC8XX_SPI
bool "MPC8XX SPI Driver"
depends on MPC8xx
@@ -451,7 +460,6 @@
config SPI_ASPEED_SMC
bool "ASPEED SPI flash controller driver"
depends on DM_SPI && SPI_MEM
- default n
help
Enable ASPEED SPI flash controller driver for AST2500
and AST2600 SoCs.
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index c27b332..14bdb97 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -41,6 +41,7 @@
obj-$(CONFIG_IPROC_QSPI) += iproc_qspi.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
+obj-$(CONFIG_MESON_SPIFC_A1) += meson_spifc_a1.o
obj-$(CONFIG_MICROCHIP_COREQSPI) += microchip_coreqspi.o
obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
index 702e225..aec6f4e 100644
--- a/drivers/spi/atmel_spi.c
+++ b/drivers/spi/atmel_spi.c
@@ -17,6 +17,7 @@
#include <asm/gpio.h>
#endif
#include <linux/bitops.h>
+#include <linux/printk.h>
/*
* Register definitions for the Atmel AT32/AT91 SPI Controller
diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c
index a7685a2..e02a3b3 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -44,8 +44,10 @@
priv->regbase + CQSPI_REG_INDIR_TRIG_ADDR_RANGE);
writel(CQSPI_DFLT_DMA_PERIPH_CFG,
priv->regbase + CQSPI_REG_DMA_PERIPH_CFG);
- writel((unsigned long)rxbuf, priv->regbase +
+ writel(lower_32_bits((unsigned long)rxbuf), priv->regbase +
CQSPI_DMA_DST_ADDR_REG);
+ writel(upper_32_bits((unsigned long)rxbuf), priv->regbase +
+ CQSPI_DMA_DST_ADDR_MSB_REG);
writel(priv->trigger_address, priv->regbase +
CQSPI_DMA_SRC_RD_ADDR_REG);
writel(bytes_to_dma, priv->regbase +
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index 9ebc4ed..25f5e9f 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
*
* Driver for SPI controller on DaVinci. Based on atmel_spi.c
* by Atmel Corporation
diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c
index 8e5cc55..f8ec268 100644
--- a/drivers/spi/fsl_dspi.c
+++ b/drivers/spi/fsl_dspi.c
@@ -26,6 +26,7 @@
#include <fsl_dspi.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <linux/printk.h>
/* linux/include/time.h */
#define NSEC_PER_SEC 1000000000L
diff --git a/drivers/spi/meson_spifc_a1.c b/drivers/spi/meson_spifc_a1.c
new file mode 100644
index 0000000..099c4c0
--- /dev/null
+++ b/drivers/spi/meson_spifc_a1.c
@@ -0,0 +1,383 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for Amlogic A1 SPI flash controller (SPIFC)
+ *
+ * Copyright (c) 2023, SberDevices. All Rights Reserved.
+ *
+ * Author: Martin Kurbanov <mmkurbanov@sberdevices.ru>
+ *
+ * Ported to u-boot:
+ * Author: Igor Prusov <ivprusov@sberdevices.ru>
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <spi.h>
+#include <spi-mem.h>
+#include <asm/io.h>
+#include <linux/log2.h>
+#include <linux/iopoll.h>
+#include <linux/bitfield.h>
+
+#define SPIFC_A1_AHB_CTRL_REG 0x0
+#define SPIFC_A1_AHB_BUS_EN BIT(31)
+
+#define SPIFC_A1_USER_CTRL0_REG 0x200
+#define SPIFC_A1_USER_REQUEST_ENABLE BIT(31)
+#define SPIFC_A1_USER_REQUEST_FINISH BIT(30)
+#define SPIFC_A1_USER_DATA_UPDATED BIT(0)
+
+#define SPIFC_A1_USER_CTRL1_REG 0x204
+#define SPIFC_A1_USER_CMD_ENABLE BIT(30)
+#define SPIFC_A1_USER_CMD_MODE GENMASK(29, 28)
+#define SPIFC_A1_USER_CMD_CODE GENMASK(27, 20)
+#define SPIFC_A1_USER_ADDR_ENABLE BIT(19)
+#define SPIFC_A1_USER_ADDR_MODE GENMASK(18, 17)
+#define SPIFC_A1_USER_ADDR_BYTES GENMASK(16, 15)
+#define SPIFC_A1_USER_DOUT_ENABLE BIT(14)
+#define SPIFC_A1_USER_DOUT_MODE GENMASK(11, 10)
+#define SPIFC_A1_USER_DOUT_BYTES GENMASK(9, 0)
+
+#define SPIFC_A1_USER_CTRL2_REG 0x208
+#define SPIFC_A1_USER_DUMMY_ENABLE BIT(31)
+#define SPIFC_A1_USER_DUMMY_MODE GENMASK(30, 29)
+#define SPIFC_A1_USER_DUMMY_CLK_SYCLES GENMASK(28, 23)
+
+#define SPIFC_A1_USER_CTRL3_REG 0x20c
+#define SPIFC_A1_USER_DIN_ENABLE BIT(31)
+#define SPIFC_A1_USER_DIN_MODE GENMASK(28, 27)
+#define SPIFC_A1_USER_DIN_BYTES GENMASK(25, 16)
+
+#define SPIFC_A1_USER_ADDR_REG 0x210
+
+#define SPIFC_A1_AHB_REQ_CTRL_REG 0x214
+#define SPIFC_A1_AHB_REQ_ENABLE BIT(31)
+
+#define SPIFC_A1_ACTIMING0_REG (0x0088 << 2)
+#define SPIFC_A1_TSLCH GENMASK(31, 30)
+#define SPIFC_A1_TCLSH GENMASK(29, 28)
+#define SPIFC_A1_TSHWL GENMASK(20, 16)
+#define SPIFC_A1_TSHSL2 GENMASK(15, 12)
+#define SPIFC_A1_TSHSL1 GENMASK(11, 8)
+#define SPIFC_A1_TWHSL GENMASK(7, 0)
+
+#define SPIFC_A1_DBUF_CTRL_REG 0x240
+#define SPIFC_A1_DBUF_DIR BIT(31)
+#define SPIFC_A1_DBUF_AUTO_UPDATE_ADDR BIT(30)
+#define SPIFC_A1_DBUF_ADDR GENMASK(7, 0)
+
+#define SPIFC_A1_DBUF_DATA_REG 0x244
+
+#define SPIFC_A1_USER_DBUF_ADDR_REG 0x248
+
+#define SPIFC_A1_BUFFER_SIZE 512U
+
+#define SPIFC_A1_MAX_HZ 200000000
+#define SPIFC_A1_MIN_HZ 1000000
+
+#define SPIFC_A1_USER_CMD(op) ( \
+ SPIFC_A1_USER_CMD_ENABLE | \
+ FIELD_PREP(SPIFC_A1_USER_CMD_CODE, (op)->cmd.opcode) | \
+ FIELD_PREP(SPIFC_A1_USER_CMD_MODE, ilog2((op)->cmd.buswidth)))
+
+#define SPIFC_A1_USER_ADDR(op) ( \
+ SPIFC_A1_USER_ADDR_ENABLE | \
+ FIELD_PREP(SPIFC_A1_USER_ADDR_MODE, ilog2((op)->addr.buswidth)) | \
+ FIELD_PREP(SPIFC_A1_USER_ADDR_BYTES, (op)->addr.nbytes - 1))
+
+#define SPIFC_A1_USER_DUMMY(op) ( \
+ SPIFC_A1_USER_DUMMY_ENABLE | \
+ FIELD_PREP(SPIFC_A1_USER_DUMMY_MODE, ilog2((op)->dummy.buswidth)) | \
+ FIELD_PREP(SPIFC_A1_USER_DUMMY_CLK_SYCLES, (op)->dummy.nbytes << 3))
+
+#define SPIFC_A1_TSLCH_VAL FIELD_PREP(SPIFC_A1_TSLCH, 1)
+#define SPIFC_A1_TCLSH_VAL FIELD_PREP(SPIFC_A1_TCLSH, 1)
+#define SPIFC_A1_TSHWL_VAL FIELD_PREP(SPIFC_A1_TSHWL, 7)
+#define SPIFC_A1_TSHSL2_VAL FIELD_PREP(SPIFC_A1_TSHSL2, 7)
+#define SPIFC_A1_TSHSL1_VAL FIELD_PREP(SPIFC_A1_TSHSL1, 7)
+#define SPIFC_A1_TWHSL_VAL FIELD_PREP(SPIFC_A1_TWHSL, 2)
+#define SPIFC_A1_ACTIMING0_VAL (SPIFC_A1_TSLCH_VAL | SPIFC_A1_TCLSH_VAL | \
+ SPIFC_A1_TSHWL_VAL | SPIFC_A1_TSHSL2_VAL | \
+ SPIFC_A1_TSHSL1_VAL | SPIFC_A1_TWHSL_VAL)
+
+struct amlogic_spifc_a1 {
+ struct clk clk;
+ void __iomem *base;
+ u32 curr_speed_hz;
+};
+
+static int amlogic_spifc_a1_request(struct amlogic_spifc_a1 *spifc, bool read)
+{
+ u32 mask = SPIFC_A1_USER_REQUEST_FINISH |
+ (read ? SPIFC_A1_USER_DATA_UPDATED : 0);
+ u32 val;
+
+ writel(SPIFC_A1_USER_REQUEST_ENABLE,
+ spifc->base + SPIFC_A1_USER_CTRL0_REG);
+
+ return readl_poll_timeout(spifc->base + SPIFC_A1_USER_CTRL0_REG,
+ val, (val & mask) == mask,
+ 200 * 1000);
+}
+
+static void amlogic_spifc_a1_drain_buffer(struct amlogic_spifc_a1 *spifc,
+ char *buf, u32 len)
+{
+ u32 data;
+ const u32 count = len / sizeof(data);
+ const u32 pad = len % sizeof(data);
+
+ writel(SPIFC_A1_DBUF_AUTO_UPDATE_ADDR,
+ spifc->base + SPIFC_A1_DBUF_CTRL_REG);
+ readsl(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count);
+
+ if (pad) {
+ data = readl(spifc->base + SPIFC_A1_DBUF_DATA_REG);
+ memcpy(buf + len - pad, &data, pad);
+ }
+}
+
+static void amlogic_spifc_a1_fill_buffer(struct amlogic_spifc_a1 *spifc,
+ const char *buf, u32 len)
+{
+ u32 data;
+ const u32 count = len / sizeof(data);
+ const u32 pad = len % sizeof(data);
+
+ writel(SPIFC_A1_DBUF_DIR | SPIFC_A1_DBUF_AUTO_UPDATE_ADDR,
+ spifc->base + SPIFC_A1_DBUF_CTRL_REG);
+ writesl(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count);
+
+ if (pad) {
+ memcpy(&data, buf + len - pad, pad);
+ writel(data, spifc->base + SPIFC_A1_DBUF_DATA_REG);
+ }
+}
+
+static void amlogic_spifc_a1_user_init(struct amlogic_spifc_a1 *spifc)
+{
+ writel(0, spifc->base + SPIFC_A1_USER_CTRL0_REG);
+ writel(0, spifc->base + SPIFC_A1_USER_CTRL1_REG);
+ writel(0, spifc->base + SPIFC_A1_USER_CTRL2_REG);
+ writel(0, spifc->base + SPIFC_A1_USER_CTRL3_REG);
+}
+
+static void amlogic_spifc_a1_set_cmd(struct amlogic_spifc_a1 *spifc,
+ u32 cmd_cfg)
+{
+ u32 val;
+
+ val = readl(spifc->base + SPIFC_A1_USER_CTRL1_REG);
+ val &= ~(SPIFC_A1_USER_CMD_MODE | SPIFC_A1_USER_CMD_CODE);
+ val |= cmd_cfg;
+ writel(val, spifc->base + SPIFC_A1_USER_CTRL1_REG);
+}
+
+static void amlogic_spifc_a1_set_addr(struct amlogic_spifc_a1 *spifc, u32 addr,
+ u32 addr_cfg)
+{
+ u32 val;
+
+ writel(addr, spifc->base + SPIFC_A1_USER_ADDR_REG);
+
+ val = readl(spifc->base + SPIFC_A1_USER_CTRL1_REG);
+ val &= ~(SPIFC_A1_USER_ADDR_MODE | SPIFC_A1_USER_ADDR_BYTES);
+ val |= addr_cfg;
+ writel(val, spifc->base + SPIFC_A1_USER_CTRL1_REG);
+}
+
+static void amlogic_spifc_a1_set_dummy(struct amlogic_spifc_a1 *spifc,
+ u32 dummy_cfg)
+{
+ u32 val = readl(spifc->base + SPIFC_A1_USER_CTRL2_REG);
+
+ val &= ~(SPIFC_A1_USER_DUMMY_MODE | SPIFC_A1_USER_DUMMY_CLK_SYCLES);
+ val |= dummy_cfg;
+ writel(val, spifc->base + SPIFC_A1_USER_CTRL2_REG);
+}
+
+static int amlogic_spifc_a1_read(struct amlogic_spifc_a1 *spifc, void *buf,
+ u32 size, u32 mode)
+{
+ u32 val = readl(spifc->base + SPIFC_A1_USER_CTRL3_REG);
+ int ret;
+
+ val &= ~(SPIFC_A1_USER_DIN_MODE | SPIFC_A1_USER_DIN_BYTES);
+ val |= SPIFC_A1_USER_DIN_ENABLE;
+ val |= FIELD_PREP(SPIFC_A1_USER_DIN_MODE, mode);
+ val |= FIELD_PREP(SPIFC_A1_USER_DIN_BYTES, size);
+ writel(val, spifc->base + SPIFC_A1_USER_CTRL3_REG);
+
+ ret = amlogic_spifc_a1_request(spifc, true);
+ if (!ret)
+ amlogic_spifc_a1_drain_buffer(spifc, buf, size);
+
+ return ret;
+}
+
+static int amlogic_spifc_a1_write(struct amlogic_spifc_a1 *spifc,
+ const void *buf, u32 size, u32 mode)
+{
+ u32 val;
+
+ amlogic_spifc_a1_fill_buffer(spifc, buf, size);
+
+ val = readl(spifc->base + SPIFC_A1_USER_CTRL1_REG);
+ val &= ~(SPIFC_A1_USER_DOUT_MODE | SPIFC_A1_USER_DOUT_BYTES);
+ val |= FIELD_PREP(SPIFC_A1_USER_DOUT_MODE, mode);
+ val |= FIELD_PREP(SPIFC_A1_USER_DOUT_BYTES, size);
+ val |= SPIFC_A1_USER_DOUT_ENABLE;
+ writel(val, spifc->base + SPIFC_A1_USER_CTRL1_REG);
+
+ return amlogic_spifc_a1_request(spifc, false);
+}
+
+static int amlogic_spifc_a1_set_freq(struct amlogic_spifc_a1 *spifc, u32 freq)
+{
+ int ret;
+
+ if (freq == spifc->curr_speed_hz)
+ return 0;
+
+ ret = clk_set_rate(&spifc->clk, freq);
+ if (ret)
+ return ret;
+
+ spifc->curr_speed_hz = freq;
+ return 0;
+}
+
+static int amlogic_spifc_a1_exec_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ struct amlogic_spifc_a1 *spifc = dev_get_priv(slave->dev->parent);
+ size_t data_size = op->data.nbytes;
+ int ret;
+
+ ret = amlogic_spifc_a1_set_freq(spifc, slave->max_hz);
+ if (ret)
+ return ret;
+
+ amlogic_spifc_a1_user_init(spifc);
+ amlogic_spifc_a1_set_cmd(spifc, SPIFC_A1_USER_CMD(op));
+
+ if (op->addr.nbytes)
+ amlogic_spifc_a1_set_addr(spifc, op->addr.val,
+ SPIFC_A1_USER_ADDR(op));
+
+ if (op->dummy.nbytes)
+ amlogic_spifc_a1_set_dummy(spifc, SPIFC_A1_USER_DUMMY(op));
+
+ if (data_size) {
+ u32 mode = ilog2(op->data.buswidth);
+
+ writel(0, spifc->base + SPIFC_A1_USER_DBUF_ADDR_REG);
+
+ if (op->data.dir == SPI_MEM_DATA_IN)
+ ret = amlogic_spifc_a1_read(spifc, op->data.buf.in,
+ data_size, mode);
+ else
+ ret = amlogic_spifc_a1_write(spifc, op->data.buf.out,
+ data_size, mode);
+ } else {
+ ret = amlogic_spifc_a1_request(spifc, false);
+ }
+
+ return ret;
+}
+
+static int amlogic_spifc_a1_adjust_op_size(struct spi_slave *slave,
+ struct spi_mem_op *op)
+{
+ op->data.nbytes = min(op->data.nbytes, SPIFC_A1_BUFFER_SIZE);
+ return 0;
+}
+
+static void amlogic_spifc_a1_hw_init(struct amlogic_spifc_a1 *spifc)
+{
+ u32 regv;
+
+ regv = readl(spifc->base + SPIFC_A1_AHB_REQ_CTRL_REG);
+ regv &= ~(SPIFC_A1_AHB_REQ_ENABLE);
+ writel(regv, spifc->base + SPIFC_A1_AHB_REQ_CTRL_REG);
+
+ regv = readl(spifc->base + SPIFC_A1_AHB_CTRL_REG);
+ regv &= ~(SPIFC_A1_AHB_BUS_EN);
+ writel(regv, spifc->base + SPIFC_A1_AHB_CTRL_REG);
+
+ writel(SPIFC_A1_ACTIMING0_VAL, spifc->base + SPIFC_A1_ACTIMING0_REG);
+
+ writel(0, spifc->base + SPIFC_A1_USER_DBUF_ADDR_REG);
+}
+
+static const struct spi_controller_mem_ops amlogic_spifc_a1_mem_ops = {
+ .exec_op = amlogic_spifc_a1_exec_op,
+ .adjust_op_size = amlogic_spifc_a1_adjust_op_size,
+};
+
+static int amlogic_spifc_a1_probe(struct udevice *dev)
+{
+ struct amlogic_spifc_a1 *spifc = dev_get_priv(dev);
+ int ret;
+ struct udevice *bus = dev;
+
+ spifc->base = dev_read_addr_ptr(dev);
+ if (!spifc->base)
+ return -EINVAL;
+
+ ret = clk_get_by_index(bus, 0, &spifc->clk);
+ if (ret) {
+ pr_err("can't get clk spifc_gate!\n");
+ return ret;
+ }
+
+ ret = clk_enable(&spifc->clk);
+ if (ret) {
+ pr_err("enable clk fail\n");
+ return ret;
+ }
+
+ amlogic_spifc_a1_hw_init(spifc);
+
+ return 0;
+}
+
+static int amlogic_spifc_a1_remove(struct udevice *dev)
+{
+ struct amlogic_spifc_a1 *spifc = dev_get_priv(dev);
+
+ clk_free(&spifc->clk);
+
+ return 0;
+}
+
+static const struct udevice_id meson_spifc_ids[] = {
+ { .compatible = "amlogic,a1-spifc", },
+ { }
+};
+
+int amlogic_spifc_a1_set_speed(struct udevice *bus, uint hz)
+{
+ return 0;
+}
+
+int amlogic_spifc_a1_set_mode(struct udevice *bus, uint mode)
+{
+ return 0;
+}
+
+static const struct dm_spi_ops amlogic_spifc_a1_ops = {
+ .mem_ops = &amlogic_spifc_a1_mem_ops,
+ .set_speed = amlogic_spifc_a1_set_speed,
+ .set_mode = amlogic_spifc_a1_set_mode,
+};
+
+U_BOOT_DRIVER(meson_spifc_a1) = {
+ .name = "meson_spifc_a1",
+ .id = UCLASS_SPI,
+ .of_match = meson_spifc_ids,
+ .ops = &amlogic_spifc_a1_ops,
+ .probe = amlogic_spifc_a1_probe,
+ .remove = amlogic_spifc_a1_remove,
+ .priv_auto = sizeof(struct amlogic_spifc_a1),
+};
diff --git a/drivers/spi/mt7621_spi.c b/drivers/spi/mt7621_spi.c
index eb09317..3d00809 100644
--- a/drivers/spi/mt7621_spi.c
+++ b/drivers/spi/mt7621_spi.c
@@ -16,6 +16,7 @@
#include <wait_bit.h>
#include <linux/bitops.h>
#include <linux/io.h>
+#include <linux/printk.h>
#define MT7621_RX_FIFO_LEN 32
#define MT7621_TX_FIFO_LEN 36
diff --git a/drivers/spi/mtk_spim.c b/drivers/spi/mtk_spim.c
index 418e586..90f4c3c 100644
--- a/drivers/spi/mtk_spim.c
+++ b/drivers/spi/mtk_spim.c
@@ -409,7 +409,7 @@
{
struct udevice *bus = dev_get_parent(slave->dev);
struct mtk_spim_priv *priv = dev_get_priv(bus);
- u32 sck_l, sck_h, clk_count, reg;
+ u32 pll_clk, sck_l, sck_h, clk_count, reg;
ulong us = 1;
int ret = 0;
@@ -418,11 +418,12 @@
else
clk_count = op->data.nbytes;
+ pll_clk = priv->pll_clk_rate;
sck_l = readl(priv->base + SPI_CFG2_REG) >> SPI_CFG2_SCK_LOW_OFFSET;
sck_h = readl(priv->base + SPI_CFG2_REG) & SPI_CFG2_SCK_HIGH_MASK;
- do_div(priv->pll_clk_rate, sck_l + sck_h + 2);
+ do_div(pll_clk, sck_l + sck_h + 2);
- us = CLK_TO_US(priv->pll_clk_rate, clk_count * 8);
+ us = CLK_TO_US(pll_clk, clk_count * 8);
us += 1000 * 1000; /* 1s tolerance */
if (us > UINT_MAX)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 840660f..33360a1 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -19,6 +19,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/spi.h>
+#include <linux/printk.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/spi/npcm_pspi.c b/drivers/spi/npcm_pspi.c
index 37bab70..eb14185 100644
--- a/drivers/spi/npcm_pspi.c
+++ b/drivers/spi/npcm_pspi.c
@@ -144,7 +144,7 @@
if (speed > priv->max_hz)
speed = priv->max_hz;
- divisor = DIV_ROUND_CLOSEST(apb_clock, (2 * speed) - 1);
+ divisor = DIV_ROUND_CLOSEST(apb_clock, (2 * speed)) - 1;
if (divisor > MAX_DIV)
divisor = MAX_DIV;
diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c
index 579d6ba..5db27f9 100644
--- a/drivers/spi/nxp_fspi.c
+++ b/drivers/spi/nxp_fspi.c
@@ -927,6 +927,13 @@
fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT,
base + FSPI_AHBCR);
+ /* Reset the flashx control1 registers */
+ reg = FSPI_FLSHXCR1_TCSH(0x3) | FSPI_FLSHXCR1_TCSS(0x3);
+ fspi_writel(f, reg, base + FSPI_FLSHA1CR1);
+ fspi_writel(f, reg, base + FSPI_FLSHA2CR1);
+ fspi_writel(f, reg, base + FSPI_FLSHB1CR1);
+ fspi_writel(f, reg, base + FSPI_FLSHB2CR1);
+
/* AHB Read - Set lut sequence ID for all CS. */
fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2);
fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2);
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index ff7b55f..5cce6ba 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -6,7 +6,7 @@
* Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
*
* Driver for McSPI controller on OMAP3. Based on davinci_spi.c
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
*
* Copyright (C) 2007 Atmel Corporation
*
diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c
index fc7388b..e2b49eb 100644
--- a/drivers/spi/pl022_spi.c
+++ b/drivers/spi/pl022_spi.c
@@ -18,6 +18,7 @@
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <spi.h>
+#include <linux/printk.h>
#define SSP_CR0 0x000
#define SSP_CR1 0x004
diff --git a/drivers/spi/spi-mem-nodm.c b/drivers/spi/spi-mem-nodm.c
index 77ddb19..6ee8413 100644
--- a/drivers/spi/spi-mem-nodm.c
+++ b/drivers/spi/spi-mem-nodm.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <log.h>
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index c929e7c..f4795e6 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -196,38 +196,6 @@
spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0);
}
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- struct dm_spi_ops *ops = spi_get_ops(bus);
- static int reloc_done;
-
- if (!reloc_done) {
- if (ops->claim_bus)
- ops->claim_bus += gd->reloc_off;
- if (ops->release_bus)
- ops->release_bus += gd->reloc_off;
- if (ops->set_wordlen)
- ops->set_wordlen += gd->reloc_off;
- if (ops->xfer)
- ops->xfer += gd->reloc_off;
- if (ops->set_speed)
- ops->set_speed += gd->reloc_off;
- if (ops->set_mode)
- ops->set_mode += gd->reloc_off;
- if (ops->cs_info)
- ops->cs_info += gd->reloc_off;
- if (ops->mem_ops) {
- struct spi_controller_mem_ops *mem_ops =
- (struct spi_controller_mem_ops *)ops->mem_ops;
- if (mem_ops->adjust_op_size)
- mem_ops->adjust_op_size += gd->reloc_off;
- if (mem_ops->supports_op)
- mem_ops->supports_op += gd->reloc_off;
- if (mem_ops->exec_op)
- mem_ops->exec_op += gd->reloc_off;
- }
- reloc_done++;
- }
-#endif
return 0;
}
diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index eb52ff7..2ffa201 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -22,6 +22,7 @@
#include <linux/delay.h>
#include <linux/iopoll.h>
#include <linux/ioport.h>
+#include <linux/printk.h>
#include <linux/sizes.h>
struct stm32_qspi_regs {
diff --git a/drivers/spi/stm32_spi.c b/drivers/spi/stm32_spi.c
index fe5419e..82f6ed7 100644
--- a/drivers/spi/stm32_spi.c
+++ b/drivers/spi/stm32_spi.c
@@ -18,6 +18,7 @@
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <asm/io.h>
#include <asm/gpio.h>
diff --git a/drivers/spi/uniphier_spi.c b/drivers/spi/uniphier_spi.c
index fcc1bfe..6402acb 100644
--- a/drivers/spi/uniphier_spi.c
+++ b/drivers/spi/uniphier_spi.c
@@ -17,6 +17,7 @@
#include <linux/io.h>
#include <spi.h>
#include <wait_bit.h>
+#include <linux/printk.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index c4aee27..a323994 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -5,6 +5,8 @@
* Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only)
*/
+#define LOG_CATEGORY UCLASS_SPI
+
#include <common.h>
#include <cpu_func.h>
#include <log.h>
@@ -192,8 +194,6 @@
{
struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
- debug("%s\n", __func__);
-
plat->regs = (struct zynqmp_qspi_regs *)(dev_read_addr(bus) +
GQSPI_REG_OFFSET);
plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
@@ -250,7 +250,7 @@
case 4:
return GQSPI_SPI_MODE_QSPI;
default:
- debug("Unsupported bus width %u\n", buswidth);
+ log_warning("Unsupported bus width %u\n", buswidth);
return GQSPI_SPI_MODE_SPI;
}
}
@@ -262,6 +262,8 @@
u32 config_reg, ier;
int ret = 0;
+ log_content("%s, GFIFO_CMD: 0x%X\n", __func__, gqspi_fifo_reg);
+
writel(gqspi_fifo_reg, ®s->genfifo);
config_reg = readl(®s->confr);
@@ -278,7 +280,7 @@
ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFEMTY_MASK, 1,
GQSPI_TIMEOUT, 1);
if (ret)
- printf("%s Timeout\n", __func__);
+ log_warning("%s, Timeout\n", __func__);
}
@@ -286,6 +288,8 @@
{
u32 gqspi_fifo_reg = 0;
+ log_debug("%s, assert: %d\r\n", __func__, is_on);
+
if (is_on) {
gqspi_fifo_reg = zynqmp_qspi_bus_select(priv);
gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI |
@@ -295,8 +299,6 @@
gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT;
}
- debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
-
zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
}
@@ -311,8 +313,8 @@
clk_rate = plat->frequency;
reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
- debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n",
- __func__, reqhz, clk_rate, baudrateval);
+ log_debug("%s, clk_rate:%d, baudrateval:%d, bus_clk: %d\n",
+ __func__, clk_rate, baudrateval, reqhz);
if (!(IS_ENABLED(CONFIG_ARCH_VERSAL) ||
IS_ENABLED(CONFIG_ARCH_VERSAL_NET))) {
@@ -362,7 +364,8 @@
u32 confr;
u8 baud_rate_val = 0;
- debug("%s\n", __func__);
+ log_debug("%s, Speed: %d, Max: %d\n", __func__, speed, plat->frequency);
+
if (speed > plat->frequency)
speed = plat->frequency;
@@ -383,9 +386,8 @@
confr &= ~GQSPI_BAUD_DIV_MASK;
confr |= (baud_rate_val << 3);
writel(confr, ®s->confr);
- zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
- debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz);
+ zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
}
return 0;
@@ -399,8 +401,6 @@
unsigned long clock;
int ret;
- debug("%s: bus:%p, priv:%p\n", __func__, bus, priv);
-
priv->regs = plat->regs;
priv->dma_regs = plat->dma_regs;
priv->io_mode = plat->io_mode;
@@ -416,7 +416,6 @@
dev_err(bus, "failed to get rate\n");
return clock;
}
- debug("%s: CLK %ld\n", __func__, clock);
ret = clk_enable(&clk);
if (ret) {
@@ -429,6 +428,8 @@
/* init the zynq spi hw */
zynqmp_qspi_init_hw(priv);
+ log_debug("%s, Rerence clock frequency: %ld\n", __func__, clock);
+
return 0;
}
@@ -438,7 +439,8 @@
struct zynqmp_qspi_regs *regs = priv->regs;
u32 confr;
- debug("%s\n", __func__);
+ log_debug("%s, 0x%X\n", __func__, mode);
+
/* Set the SPI Clock phase and polarities */
confr = readl(®s->confr);
confr &= ~(GQSPI_CONFIG_CPHA_MASK | GQSPI_CONFIG_CPOL_MASK);
@@ -461,16 +463,11 @@
u32 *buf = (u32 *)priv->tx_buf;
u32 len = size;
- debug("TxFIFO: 0x%x, size: 0x%x\n", readl(®s->isr),
- size);
-
while (size) {
ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_TXNFULL_MASK, 1,
GQSPI_TIMEOUT, 1);
- if (ret) {
- printf("%s: Timeout\n", __func__);
- return ret;
- }
+ if (ret)
+ return log_msg_ret("Timeout\n", ret);
if (size >= 4) {
writel(*buf, ®s->txd0r);
@@ -501,10 +498,8 @@
ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_TXFIFOEMPTY_MASK, 1,
GQSPI_TIMEOUT, 1);
- if (ret) {
- printf("%s: Timeout\n", __func__);
- return ret;
- }
+ if (ret)
+ return log_msg_ret("Timeout\n", ret);
priv->tx_buf += len;
return 0;
@@ -516,6 +511,9 @@
u32 gen_fifo_cmd;
u8 i, dummy_cycles, addr;
+ log_debug("%s, opcode: 0x%0X, addr.nbytes: %d, dummy.mbytes: %d\r\n",
+ __func__, op->cmd.opcode, op->addr.nbytes, op->dummy.nbytes);
+
/* Send opcode */
gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->cmd.buswidth);
@@ -532,8 +530,6 @@
gen_fifo_cmd |= GQSPI_GFIFO_TX;
gen_fifo_cmd |= addr;
- debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd);
-
zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
}
@@ -583,6 +579,8 @@
u32 len;
int ret = 0;
+ log_debug("%s, length: %d\r\n", __func__, priv->len);
+
gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_GFIFO_DATA_XFR_MASK;
@@ -591,8 +589,6 @@
len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
- debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd);
-
if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK)
ret = zynqmp_qspi_fill_tx_fifo(priv, 1 << len);
else
@@ -608,7 +604,6 @@
u32 gen_fifo_cmd, u32 *buf)
{
u32 len;
- u32 actuallen = priv->len;
u32 config_reg, ier, isr;
u32 timeout = GQSPI_TIMEOUT;
struct zynqmp_qspi_regs *regs = priv->regs;
@@ -623,7 +618,7 @@
else
priv->bytes_to_receive = len;
zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
- debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
+
/* Manual start */
config_reg = readl(®s->confr);
config_reg |= GQSPI_STRT_GEN_FIFO;
@@ -652,13 +647,8 @@
}
}
- debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
- (unsigned long)buf, (unsigned long)priv->rx_buf,
- *buf, actuallen);
- if (!timeout) {
- printf("IO timeout: %d\n", readl(®s->isr));
- return -1;
- }
+ if (!timeout)
+ return log_msg_retz("Timeout\n", timeout);
}
return 0;
@@ -690,29 +680,23 @@
writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
addr = (unsigned long)buf;
size = roundup(priv->len, GQSPI_DMA_ALIGN);
- flush_dcache_range(addr, addr + size);
+ invalidate_dcache_range(addr, addr + size);
while (priv->len) {
zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
-
- debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
}
ret = wait_for_bit_le32(&dma_regs->dmaisr,
GQSPI_DMA_DST_I_STS_DONE, 1,
GQSPI_TIMEOUT, 1);
- if (ret) {
- printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr));
- return -ETIMEDOUT;
- }
+ if (ret)
+ return log_msg_ret("Timeout:\n", ret);
+
+ invalidate_dcache_range(addr, addr + size);
writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr);
- debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
- (unsigned long)buf, (unsigned long)priv->rx_buf, *buf,
- actuallen);
-
if (buf != priv->rx_buf)
memcpy(priv->rx_buf, buf, actuallen);
@@ -729,6 +713,8 @@
u32 *buf;
u32 actuallen = priv->len;
+ log_debug("%s, length: %d\r\n", __func__, priv->len);
+
gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
gen_fifo_cmd |= GQSPI_GFIFO_RX | GQSPI_GFIFO_DATA_XFR_MASK;
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index bdbe2a9..0e52f99 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -74,6 +74,13 @@
example on Microblaze where reset logic can be controlled via GPIO
pin which triggers cpu reset.
+config SYSRESET_MAX77663
+ bool "Enable support for MAX77663 PMIC System Reset"
+ depends on DM_PMIC_MAX77663
+ select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
+ help
+ Enable system power management functions found in MAX77663 PMIC.
+
config SYSRESET_MICROBLAZE
bool "Enable support for Microblaze soft reset"
depends on MICROBLAZE
@@ -102,6 +109,13 @@
This enables the system reset driver support for Microchip/Atmel
SoCs in SPL.
+config SYSRESET_PALMAS
+ bool "Enable support for PALMAS System Reset"
+ depends on PMIC_PALMAS
+ select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
+ help
+ Enable system power management functions found in PLAMAS PMIC family.
+
config SYSRESET_PSCI
bool "Enable support for PSCI System Reset"
depends on ARM_PSCI_FW
@@ -137,6 +151,12 @@
This enables the system reset driver support for Intel SOCFPGA
SoC64 SoCs.
+config SYSRESET_TEGRA
+ bool "Tegra PMC system reset driver"
+ depends on ARCH_TEGRA
+ help
+ This enables the system reset ability of PMC used in Tegra SoCs.
+
config SYSRESET_TI_SCI
bool "TI System Control Interface (TI SCI) system reset driver"
depends on TI_SCI_PROTOCOL
@@ -144,6 +164,22 @@
This enables the system reset driver support over TI System Control
Interface available on some new TI's SoCs.
+config SYSRESET_TPS65910
+ bool "Enable support for TPS65910/TPS65911 PMIC System Reset"
+ depends on DM_PMIC_TPS65910
+ select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
+ help
+ Enable system power management functions found in TPS65910/TPS65911
+ PMICs.
+
+config SYSRESET_TPS80031
+ bool "Enable support for TPS80031/TPS80032 PMIC System Reset"
+ depends on DM_PMIC_TPS80031
+ select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
+ help
+ Enable system power management functions found in TPS80031/TPS80032
+ PMICs.
+
config SYSRESET_SYSCON
bool "Enable support for mfd syscon reboot driver"
select REGMAP
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 40c8767..c9f1c62 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -9,14 +9,19 @@
obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
obj-$(CONFIG_POWEROFF_GPIO) += poweroff_gpio.o
obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
+obj-$(CONFIG_$(SPL_TPL_)SYSRESET_MAX77663) += sysreset_max77663.o
obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o
+obj-$(CONFIG_$(SPL_TPL_)SYSRESET_PALMAS) += sysreset_palmas.o
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
obj-$(CONFIG_SYSRESET_SBI) += sysreset_sbi.o
obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
obj-$(CONFIG_SYSRESET_SOCFPGA_SOC64) += sysreset_socfpga_soc64.o
+obj-$(CONFIG_SYSRESET_TEGRA) += sysreset_tegra.o
obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
+obj-$(CONFIG_$(SPL_TPL_)SYSRESET_TPS65910) += sysreset_tps65910.o
+obj-$(CONFIG_$(SPL_TPL_)SYSRESET_TPS80031) += sysreset_tps80031.o
obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o
diff --git a/drivers/sysreset/sysreset-ti-sci.c b/drivers/sysreset/sysreset-ti-sci.c
index 81bfd67..5fc05c4 100644
--- a/drivers/sysreset/sysreset-ti-sci.c
+++ b/drivers/sysreset/sysreset-ti-sci.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments System Control Interface (TI SCI) system reset driver
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Andreas Dannenberg <dannenberg@ti.com>
*/
diff --git a/drivers/sysreset/sysreset-uclass.c b/drivers/sysreset/sysreset-uclass.c
index 279b087..6151b5f 100644
--- a/drivers/sysreset/sysreset-uclass.c
+++ b/drivers/sysreset/sysreset-uclass.c
@@ -158,23 +158,7 @@
}
#endif
-static int sysreset_post_bind(struct udevice *dev)
-{
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- struct sysreset_ops *ops = sysreset_get_ops(dev);
- static int reloc_done;
-
- if (!reloc_done) {
- if (ops->request)
- ops->request += gd->reloc_off;
- reloc_done++;
- }
-#endif
- return 0;
-}
-
UCLASS_DRIVER(sysreset) = {
.id = UCLASS_SYSRESET,
.name = "sysreset",
- .post_bind = sysreset_post_bind,
};
diff --git a/drivers/sysreset/sysreset_max77663.c b/drivers/sysreset/sysreset_max77663.c
new file mode 100644
index 0000000..8febcf8
--- /dev/null
+++ b/drivers/sysreset/sysreset_max77663.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <i2c.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <power/pmic.h>
+#include <power/max77663.h>
+
+static int max77663_sysreset_request(struct udevice *dev,
+ enum sysreset_t type)
+{
+ int val;
+
+ val = pmic_reg_read(dev->parent, MAX77663_REG_ONOFF_CFG1);
+ if (val < 0)
+ return val;
+
+ /* clear both bits */
+ val &= ~ONOFF_SFT_RST;
+ val &= ~ONOFF_PWR_OFF;
+
+ switch (type) {
+ case SYSRESET_POWER:
+ /* MAX77663: SFT_RST > ONOFF_CFG1 */
+ pmic_reg_write(dev->parent, MAX77663_REG_ONOFF_CFG1,
+ val | ONOFF_SFT_RST);
+ break;
+ case SYSRESET_POWER_OFF:
+ /* MAX77663: PWR_OFF > ONOFF_CFG1 */
+ pmic_reg_write(dev->parent, MAX77663_REG_ONOFF_CFG1,
+ val | ONOFF_PWR_OFF);
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops max77663_sysreset = {
+ .request = max77663_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_max77663) = {
+ .id = UCLASS_SYSRESET,
+ .name = MAX77663_RST_DRIVER,
+ .ops = &max77663_sysreset,
+};
diff --git a/drivers/sysreset/sysreset_palmas.c b/drivers/sysreset/sysreset_palmas.c
new file mode 100644
index 0000000..9e3aa40
--- /dev/null
+++ b/drivers/sysreset/sysreset_palmas.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <i2c.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <power/pmic.h>
+#include <power/palmas.h>
+
+static int palmas_sysreset_request(struct udevice *dev,
+ enum sysreset_t type)
+{
+ struct palmas_priv *priv = dev_get_priv(dev->parent);
+ int ret;
+
+ /*
+ * Mask INT3 on second page which detects vbus
+ * or device will immediately turn on.
+ */
+ ret = dm_i2c_reg_clrset(priv->chip2, PALMAS_INT3_MASK,
+ MASK_VBUS, MASK_VBUS);
+ if (ret < 0)
+ return ret;
+
+ switch (type) {
+ case SYSRESET_POWER:
+ /* PALMAS: SW_RST > DEV_CTRL */
+ pmic_reg_write(dev->parent, PALMAS_DEV_CTRL, SW_RST);
+ break;
+ case SYSRESET_POWER_OFF:
+ /* PALMAS: DEV_OFF > DEV_CTRL */
+ pmic_reg_write(dev->parent, PALMAS_DEV_CTRL, DEV_OFF);
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops palmas_sysreset = {
+ .request = palmas_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_palmas) = {
+ .id = UCLASS_SYSRESET,
+ .name = PALMAS_RST_DRIVER,
+ .ops = &palmas_sysreset,
+};
diff --git a/drivers/sysreset/sysreset_sandbox.c b/drivers/sysreset/sysreset_sandbox.c
index 3750c60..f485a13 100644
--- a/drivers/sysreset/sysreset_sandbox.c
+++ b/drivers/sysreset/sysreset_sandbox.c
@@ -132,7 +132,7 @@
.ops = &sandbox_warm_sysreset_ops,
};
-#if CONFIG_IS_ENABLED(OF_REAL)
+#if CONFIG_IS_ENABLED(OF_REAL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
/* This is here in case we don't have a device tree */
U_BOOT_DRVINFO(sysreset_sandbox_non_fdt) = {
.name = "sysreset_sandbox",
diff --git a/drivers/sysreset/sysreset_sti.c b/drivers/sysreset/sysreset_sti.c
index f0f445f..edd90aa 100644
--- a/drivers/sysreset/sysreset_sti.c
+++ b/drivers/sysreset/sysreset_sti.c
@@ -12,6 +12,7 @@
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
+#include <linux/printk.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/sysreset/sysreset_syscon.c b/drivers/sysreset/sysreset_syscon.c
index 525faf2..e468dac 100644
--- a/drivers/sysreset/sysreset_syscon.c
+++ b/drivers/sysreset/sysreset_syscon.c
@@ -14,6 +14,7 @@
#include <sysreset.h>
#include <syscon.h>
#include <linux/err.h>
+#include <linux/printk.h>
struct syscon_reboot_priv {
struct regmap *regmap;
diff --git a/drivers/sysreset/sysreset_tegra.c b/drivers/sysreset/sysreset_tegra.c
new file mode 100644
index 0000000..10bcd3a
--- /dev/null
+++ b/drivers/sysreset/sysreset_tegra.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <linux/err.h>
+#include <asm/arch-tegra/pmc.h>
+
+static int tegra_sysreset_request(struct udevice *dev,
+ enum sysreset_t type)
+{
+ u32 value;
+
+ switch (type) {
+ case SYSRESET_WARM:
+ case SYSRESET_COLD:
+ /* resets everything but scratch 0 and reset status */
+ value = tegra_pmc_readl(PMC_CNTRL);
+ value |= PMC_CNTRL_MAIN_RST;
+ tegra_pmc_writel(value, PMC_CNTRL);
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops tegra_sysreset = {
+ .request = tegra_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_tegra) = {
+ .id = UCLASS_SYSRESET,
+ .name = "sysreset_tegra",
+ .ops = &tegra_sysreset,
+};
+
+/* Link to Tegra PMC once there is a driver */
+U_BOOT_DRVINFO(sysreset_tegra) = {
+ .name = "sysreset_tegra"
+};
diff --git a/drivers/sysreset/sysreset_tps65910.c b/drivers/sysreset/sysreset_tps65910.c
new file mode 100644
index 0000000..98da566
--- /dev/null
+++ b/drivers/sysreset/sysreset_tps65910.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <i2c.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <power/pmic.h>
+#include <power/tps65910_pmic.h>
+
+static int tps65910_sysreset_request(struct udevice *dev,
+ enum sysreset_t type)
+{
+ int val;
+
+ val = pmic_reg_read(dev->parent, TPS65910_REG_DEVICE_CTRL);
+ if (val < 0)
+ return val;
+
+ /* define power-off to be sequential */
+ val |= PWR_OFF_SEQ;
+ pmic_reg_write(dev->parent, TPS65910_REG_DEVICE_CTRL, val);
+
+ val &= ~DEV_ON;
+
+ switch (type) {
+ case SYSRESET_POWER:
+ /* TPS65910: DEV_OFF_RST > DEVICE_CTRL */
+ pmic_reg_write(dev->parent, TPS65910_REG_DEVICE_CTRL,
+ val | DEV_OFF_RST);
+ break;
+ case SYSRESET_POWER_OFF:
+ /* TPS65910: DEV_OFF > DEVICE_CTRL */
+ pmic_reg_write(dev->parent, TPS65910_REG_DEVICE_CTRL,
+ val | DEV_OFF);
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops tps65910_sysreset = {
+ .request = tps65910_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_tps65910) = {
+ .id = UCLASS_SYSRESET,
+ .name = TPS65910_RST_DRIVER,
+ .ops = &tps65910_sysreset,
+};
diff --git a/drivers/sysreset/sysreset_tps80031.c b/drivers/sysreset/sysreset_tps80031.c
new file mode 100644
index 0000000..50024fe
--- /dev/null
+++ b/drivers/sysreset/sysreset_tps80031.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <i2c.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <power/pmic.h>
+#include <power/tps80031.h>
+
+static int tps80031_sysreset_request(struct udevice *dev,
+ enum sysreset_t type)
+{
+ switch (type) {
+ case SYSRESET_POWER:
+ /* TPS80031: SW_RESET > PHOENIX_DEV_ON */
+ pmic_reg_write(dev->parent, TPS80031_PHOENIX_DEV_ON, SW_RESET);
+ break;
+ case SYSRESET_POWER_OFF:
+ /* TPS80031: DEVOFF > PHOENIX_DEV_ON */
+ pmic_reg_write(dev->parent, TPS80031_PHOENIX_DEV_ON, DEVOFF);
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops tps80031_sysreset = {
+ .request = tps80031_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_tps80031) = {
+ .id = UCLASS_SYSRESET,
+ .name = TPS80031_RST_DRIVER,
+ .ops = &tps80031_sysreset,
+};
diff --git a/drivers/sysreset/sysreset_watchdog.c b/drivers/sysreset/sysreset_watchdog.c
index 8a659ee..ceada2e 100644
--- a/drivers/sysreset/sysreset_watchdog.c
+++ b/drivers/sysreset/sysreset_watchdog.c
@@ -10,6 +10,7 @@
#include <malloc.h>
#include <sysreset.h>
#include <wdt.h>
+#include <linux/printk.h>
struct wdt_reboot_plat {
struct udevice *wdt;
diff --git a/drivers/thermal/ti-bandgap.c b/drivers/thermal/ti-bandgap.c
index 0b533d4..0ea17a9 100644
--- a/drivers/thermal/ti-bandgap.c
+++ b/drivers/thermal/ti-bandgap.c
@@ -1,7 +1,7 @@
/*
* TI Bandgap temperature sensor driver
*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 915b2af..60519c3 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -59,7 +59,14 @@
config ANDES_PLMT_TIMER
bool
- depends on RISCV_MMODE || SPL_RISCV_MMODE
+ depends on RISCV_MMODE
+ help
+ The Andes PLMT block holds memory-mapped mtime register
+ associated with timer tick.
+
+config SPL_ANDES_PLMT_TIMER
+ bool
+ depends on SPL_RISCV_MMODE
help
The Andes PLMT block holds memory-mapped mtime register
associated with timer tick.
@@ -326,4 +333,11 @@
Select this to enable support for the timer found on
any Xilinx boards (axi timer).
+config STARFIVE_TIMER
+ bool "Starfive timer support"
+ depends on TIMER
+ help
+ Select this to enable support for the timer found on
+ Starfive SoC.
+
endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index 1ca7480..b93145e 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -4,7 +4,7 @@
obj-y += timer-uclass.o
obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
-obj-$(CONFIG_ANDES_PLMT_TIMER) += andes_plmt_timer.o
+obj-$(CONFIG_$(SPL_)ANDES_PLMT_TIMER) += andes_plmt_timer.o
obj-$(CONFIG_ARC_TIMER) += arc_timer.o
obj-$(CONFIG_ARM_TWD_TIMER) += arm_twd_timer.o
obj-$(CONFIG_AST_TIMER) += ast_timer.o
@@ -34,3 +34,4 @@
obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o
obj-$(CONFIG_IMX_GPT_TIMER) += imx-gpt-timer.o
obj-$(CONFIG_XILINX_TIMER) += xilinx-timer.o
+obj-$(CONFIG_STARFIVE_TIMER) += starfive-timer.o
diff --git a/drivers/timer/riscv_aclint_timer.c b/drivers/timer/riscv_aclint_timer.c
index e29d527..73fb879 100644
--- a/drivers/timer/riscv_aclint_timer.c
+++ b/drivers/timer/riscv_aclint_timer.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <clk.h>
+#include <div64.h>
#include <dm.h>
#include <timer.h>
#include <asm/io.h>
@@ -44,6 +45,28 @@
}
#endif
+#if CONFIG_IS_ENABLED(RISCV_MMODE) && CONFIG_IS_ENABLED(BOOTSTAGE)
+ulong timer_get_boot_us(void)
+{
+ int ret;
+ u64 ticks = 0;
+ u32 rate;
+
+ ret = dm_timer_init();
+ if (!ret) {
+ rate = timer_get_rate(gd->timer);
+ timer_get_count(gd->timer, &ticks);
+ } else {
+ rate = RISCV_MMODE_TIMER_FREQ;
+ ticks = readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE,
+ RISCV_MMODE_TIMEROFF));
+ }
+
+ /* Below is converted from time(us) = (tick / rate) * 10000000 */
+ return lldiv(ticks * 1000, (rate / 1000));
+}
+#endif
+
static const struct timer_ops riscv_aclint_timer_ops = {
.get_count = riscv_aclint_timer_get_count,
};
diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 28a6a68..169c03d 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -11,6 +11,7 @@
*/
#include <common.h>
+#include <div64.h>
#include <dm.h>
#include <errno.h>
#include <fdt_support.h>
@@ -51,6 +52,27 @@
}
#endif
+#if CONFIG_IS_ENABLED(RISCV_SMODE) && CONFIG_IS_ENABLED(BOOTSTAGE)
+ulong timer_get_boot_us(void)
+{
+ int ret;
+ u64 ticks = 0;
+ u32 rate;
+
+ ret = dm_timer_init();
+ if (!ret) {
+ rate = timer_get_rate(gd->timer);
+ timer_get_count(gd->timer, &ticks);
+ } else {
+ rate = RISCV_SMODE_TIMER_FREQ;
+ ticks = riscv_timer_get_count(NULL);
+ }
+
+ /* Below is converted from time(us) = (tick / rate) * 10000000 */
+ return lldiv(ticks * 1000, (rate / 1000));
+}
+#endif
+
static int riscv_timer_probe(struct udevice *dev)
{
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
diff --git a/drivers/timer/starfive-timer.c b/drivers/timer/starfive-timer.c
new file mode 100644
index 0000000..816402f
--- /dev/null
+++ b/drivers/timer/starfive-timer.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 StarFive, Inc. All rights reserved.
+ * Author: Lee Kuan Lim <kuanlim.lee@starfivetech.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <time.h>
+#include <timer.h>
+#include <asm/io.h>
+#include <dm/device-internal.h>
+#include <linux/err.h>
+
+#define STF_TIMER_INT_STATUS 0x00
+#define STF_TIMER_CTL 0x04
+#define STF_TIMER_LOAD 0x08
+#define STF_TIMER_ENABLE 0x10
+#define STF_TIMER_RELOAD 0x14
+#define STF_TIMER_VALUE 0x18
+#define STF_TIMER_INT_CLR 0x20
+#define STF_TIMER_INT_MASK 0x24
+
+struct starfive_timer_priv {
+ void __iomem *base;
+ u32 timer_size;
+};
+
+static u64 notrace starfive_get_count(struct udevice *dev)
+{
+ struct starfive_timer_priv *priv = dev_get_priv(dev);
+
+ /* Read decrement timer value and convert to increment value */
+ return priv->timer_size - readl(priv->base + STF_TIMER_VALUE);
+}
+
+static const struct timer_ops starfive_ops = {
+ .get_count = starfive_get_count,
+};
+
+static int starfive_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct starfive_timer_priv *priv = dev_get_priv(dev);
+ int timer_channel;
+ struct clk clk;
+ int ret;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ timer_channel = dev_read_u32_default(dev, "channel", 0);
+ priv->base = priv->base + (0x40 * timer_channel);
+
+ /* Get clock rate from channel selectecd*/
+ ret = clk_get_by_index(dev, timer_channel, &clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret)
+ return ret;
+ uc_priv->clock_rate = clk_get_rate(&clk);
+
+ /* Initiate timer, channel 0 */
+ /* Unmask Interrupt Mask */
+ writel(0, priv->base + STF_TIMER_INT_MASK);
+ /* Single run mode Setting */
+ if (dev_read_bool(dev, "single-run"))
+ writel(1, priv->base + STF_TIMER_CTL);
+ /* Set Reload value */
+ priv->timer_size = dev_read_u32_default(dev, "timer-size", 0xffffffff);
+ writel(priv->timer_size, priv->base + STF_TIMER_LOAD);
+ /* Enable to start timer */
+ writel(1, priv->base + STF_TIMER_ENABLE);
+
+ return 0;
+}
+
+static const struct udevice_id starfive_ids[] = {
+ { .compatible = "starfive,jh8100-timers" },
+ { }
+};
+
+U_BOOT_DRIVER(jh8100_starfive_timer) = {
+ .name = "jh8100_starfive_timer",
+ .id = UCLASS_TIMER,
+ .of_match = starfive_ids,
+ .probe = starfive_probe,
+ .ops = &starfive_ops,
+ .priv_auto = sizeof(struct starfive_timer_priv),
+};
diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c
index f4b871a..0c2018b 100644
--- a/drivers/timer/timer-uclass.c
+++ b/drivers/timer/timer-uclass.c
@@ -51,19 +51,6 @@
static int timer_pre_probe(struct udevice *dev)
{
- if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC) &&
- (gd->flags & GD_FLG_RELOC)) {
- struct timer_ops *ops = timer_get_ops(dev);
- static int reloc_done;
-
- if (!reloc_done) {
- if (ops->get_count)
- MANUAL_RELOC(ops->get_count);
-
- reloc_done++;
- }
- }
-
if (CONFIG_IS_ENABLED(OF_REAL)) {
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct clk timer_clk;
diff --git a/drivers/tpm/tpm2_tis_sandbox.c b/drivers/tpm/tpm2_tis_sandbox.c
index e4004cf..d15a28d 100644
--- a/drivers/tpm/tpm2_tis_sandbox.c
+++ b/drivers/tpm/tpm2_tis_sandbox.c
@@ -22,11 +22,6 @@
TPM2_HIERARCHY_NB,
};
-/* Subset of supported capabilities */
-enum tpm2_capability {
- TPM_CAP_TPM_PROPERTIES = 0x6,
-};
-
/* Subset of supported properties */
#define TPM2_PROPERTIES_OFFSET 0x0000020E
@@ -38,7 +33,8 @@
TPM2_PROPERTY_NB,
};
-#define SANDBOX_TPM_PCR_NB 1
+#define SANDBOX_TPM_PCR_NB TPM2_MAX_PCRS
+#define SANDBOX_TPM_PCR_SELECT_MAX ((SANDBOX_TPM_PCR_NB + 7) / 8)
/*
* Information about our TPM emulation. This is preserved in the sandbox
@@ -433,7 +429,7 @@
int i, j;
/* TPM2_GetProperty */
- u32 capability, property, property_count;
+ u32 capability, property, property_count, val;
/* TPM2_PCR_Read/Extend variables */
int pcr_index = 0;
@@ -542,19 +538,32 @@
case TPM2_CC_GET_CAPABILITY:
capability = get_unaligned_be32(sent);
sent += sizeof(capability);
- if (capability != TPM_CAP_TPM_PROPERTIES) {
- printf("Sandbox TPM only support TPM_CAPABILITIES\n");
- return TPM2_RC_HANDLE;
- }
-
property = get_unaligned_be32(sent);
sent += sizeof(property);
- property -= TPM2_PROPERTIES_OFFSET;
-
property_count = get_unaligned_be32(sent);
sent += sizeof(property_count);
- if (!property_count ||
- property + property_count > TPM2_PROPERTY_NB) {
+
+ switch (capability) {
+ case TPM2_CAP_PCRS:
+ break;
+ case TPM2_CAP_TPM_PROPERTIES:
+ if (!property_count) {
+ rc = TPM2_RC_HANDLE;
+ return sandbox_tpm2_fill_buf(recv, recv_len,
+ tag, rc);
+ }
+
+ if (property >= TPM2_PROPERTIES_OFFSET &&
+ ((property - TPM2_PROPERTIES_OFFSET) +
+ property_count > TPM2_PROPERTY_NB)) {
+ rc = TPM2_RC_HANDLE;
+ return sandbox_tpm2_fill_buf(recv, recv_len,
+ tag, rc);
+ }
+ break;
+ default:
+ printf("Sandbox TPM2 only supports TPM2_CAP_PCRS or "
+ "TPM2_CAP_TPM_PROPERTIES\n");
rc = TPM2_RC_HANDLE;
return sandbox_tpm2_fill_buf(recv, recv_len, tag, rc);
}
@@ -578,18 +587,53 @@
put_unaligned_be32(capability, recv);
recv += sizeof(capability);
- /* Give the number of properties that follow */
- put_unaligned_be32(property_count, recv);
- recv += sizeof(property_count);
+ switch (capability) {
+ case TPM2_CAP_PCRS:
+ /* Give the number of algorithms supported - just SHA256 */
+ put_unaligned_be32(1, recv);
+ recv += sizeof(u32);
- /* Fill with the properties */
- for (i = 0; i < property_count; i++) {
- put_unaligned_be32(TPM2_PROPERTIES_OFFSET + property +
- i, recv);
- recv += sizeof(property);
- put_unaligned_be32(tpm->properties[property + i],
- recv);
- recv += sizeof(property);
+ /* Give SHA256 algorithm */
+ put_unaligned_be16(TPM2_ALG_SHA256, recv);
+ recv += sizeof(u16);
+
+ /* Select the PCRs supported */
+ *recv = SANDBOX_TPM_PCR_SELECT_MAX;
+ recv++;
+
+ /* Activate all the PCR bits */
+ for (i = 0; i < SANDBOX_TPM_PCR_SELECT_MAX; ++i) {
+ *recv = 0xff;
+ recv++;
+ }
+ break;
+ case TPM2_CAP_TPM_PROPERTIES:
+ /* Give the number of properties that follow */
+ put_unaligned_be32(property_count, recv);
+ recv += sizeof(property_count);
+
+ /* Fill with the properties */
+ for (i = 0; i < property_count; i++) {
+ put_unaligned_be32(property + i, recv);
+ recv += sizeof(property);
+ if (property >= TPM2_PROPERTIES_OFFSET) {
+ val = tpm->properties[(property -
+ TPM2_PROPERTIES_OFFSET) + i];
+ } else {
+ switch (property) {
+ case TPM2_PT_PCR_COUNT:
+ val = SANDBOX_TPM_PCR_NB;
+ break;
+ default:
+ val = 0xffffffff;
+ break;
+ }
+ }
+
+ put_unaligned_be32(val, recv);
+ recv += sizeof(property);
+ }
+ break;
}
/* Add trailing \0 */
diff --git a/drivers/tpm/tpm_tis_infineon.c b/drivers/tpm/tpm_tis_infineon.c
index 525ad72..16f4af0 100644
--- a/drivers/tpm/tpm_tis_infineon.c
+++ b/drivers/tpm/tpm_tis_infineon.c
@@ -28,6 +28,7 @@
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/compiler.h>
+#include <linux/printk.h>
#include <linux/types.h>
#include <linux/unaligned/be_byteshift.h>
diff --git a/drivers/ufs/Kconfig b/drivers/ufs/Kconfig
index 69ea18e..0e0cc58 100644
--- a/drivers/ufs/Kconfig
+++ b/drivers/ufs/Kconfig
@@ -21,4 +21,13 @@
This selects the glue layer driver for Cadence controller
present on TI's J721E devices.
+config UFS_RENESAS
+ bool "Renesas specific hooks to UFS controller platform driver"
+ depends on UFS
+ select BOUNCE_BUFFER
+ help
+ This selects the Renesas specific additions to UFSHCD platform driver.
+ UFS host on Renesas needs some vendor specific configuration before
+ accessing the hardware.
+
endmenu
diff --git a/drivers/ufs/Makefile b/drivers/ufs/Makefile
index 62ed016..56a4b07 100644
--- a/drivers/ufs/Makefile
+++ b/drivers/ufs/Makefile
@@ -1,8 +1,9 @@
# SPDX-License-Identifier: GPL-2.0
#
-# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+# Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
#
obj-$(CONFIG_UFS) += ufs.o ufs-uclass.o
obj-$(CONFIG_CADENCE_UFS) += cdns-platform.o
obj-$(CONFIG_TI_J721E_UFS) += ti-j721e-ufs.o
+obj-$(CONFIG_UFS_RENESAS) += ufs-renesas.o
diff --git a/drivers/ufs/cdns-platform.c b/drivers/ufs/cdns-platform.c
index bad1bf7..9202b53 100644
--- a/drivers/ufs/cdns-platform.c
+++ b/drivers/ufs/cdns-platform.c
@@ -2,7 +2,7 @@
/**
* cdns-platform.c - Platform driver for Cadence UFSHCI device
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*/
#include <clk.h>
@@ -119,7 +119,7 @@
U_BOOT_DRIVER(cdns_ufs_pltfm) = {
.name = "cdns-ufs-pltfm",
- .id = UCLASS_UFS,
+ .id = UCLASS_UFS,
.of_match = cdns_ufs_pltfm_ids,
.probe = cdns_ufs_pltfm_probe,
.bind = cdns_ufs_pltfm_bind,
diff --git a/drivers/ufs/ti-j721e-ufs.c b/drivers/ufs/ti-j721e-ufs.c
index d875269..1860e0d 100644
--- a/drivers/ufs/ti-j721e-ufs.c
+++ b/drivers/ufs/ti-j721e-ufs.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <asm/io.h>
diff --git a/drivers/ufs/ufs-renesas.c b/drivers/ufs/ufs-renesas.c
new file mode 100644
index 0000000..ae05bdc
--- /dev/null
+++ b/drivers/ufs/ufs-renesas.c
@@ -0,0 +1,412 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Renesas UFS host controller driver
+ *
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <ufs.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/bug.h>
+#include <linux/iopoll.h>
+
+#include "ufs.h"
+
+struct ufs_renesas_priv {
+ struct clk_bulk clks;
+ bool initialized; /* The hardware needs initialization once */
+};
+
+enum {
+ SET_PHY_INDEX_LO = 0,
+ SET_PHY_INDEX_HI,
+ TIMER_INDEX,
+ MAX_INDEX
+};
+
+enum ufs_renesas_init_param_mode {
+ MODE_RESTORE,
+ MODE_SET,
+ MODE_SAVE,
+ MODE_POLL,
+ MODE_WAIT,
+ MODE_WRITE,
+};
+
+#define PARAM_RESTORE(_reg, _index) \
+ { .mode = MODE_RESTORE, .reg = _reg, .index = _index }
+#define PARAM_SET(_index, _set) \
+ { .mode = MODE_SET, .index = _index, .u.set = _set }
+#define PARAM_SAVE(_reg, _mask, _index) \
+ { .mode = MODE_SAVE, .reg = _reg, .mask = (u32)(_mask), \
+ .index = _index }
+#define PARAM_POLL(_reg, _expected, _mask) \
+ { .mode = MODE_POLL, .reg = _reg, .u.expected = _expected, \
+ .mask = (u32)(_mask) }
+#define PARAM_WAIT(_delay_us) \
+ { .mode = MODE_WAIT, .u.delay_us = _delay_us }
+
+#define PARAM_WRITE(_reg, _val) \
+ { .mode = MODE_WRITE, .reg = _reg, .u.val = _val }
+
+#define PARAM_WRITE_D0_D4(_d0, _d4) \
+ PARAM_WRITE(0xd0, _d0), PARAM_WRITE(0xd4, _d4)
+
+#define PARAM_WRITE_800_80C_POLL(_addr, _data_800) \
+ PARAM_WRITE_D0_D4(0x0000080c, 0x00000100), \
+ PARAM_WRITE_D0_D4(0x00000800, ((_data_800) << 16) | BIT(8) | (_addr)), \
+ PARAM_WRITE(0xd0, 0x0000080c), \
+ PARAM_POLL(0xd4, BIT(8), BIT(8))
+
+#define PARAM_RESTORE_800_80C_POLL(_index) \
+ PARAM_WRITE_D0_D4(0x0000080c, 0x00000100), \
+ PARAM_WRITE(0xd0, 0x00000800), \
+ PARAM_RESTORE(0xd4, (_index)), \
+ PARAM_WRITE(0xd0, 0x0000080c), \
+ PARAM_POLL(0xd4, BIT(8), BIT(8))
+
+#define PARAM_WRITE_804_80C_POLL(_addr, _data_804) \
+ PARAM_WRITE_D0_D4(0x0000080c, 0x00000100), \
+ PARAM_WRITE_D0_D4(0x00000804, ((_data_804) << 16) | BIT(8) | (_addr)), \
+ PARAM_WRITE(0xd0, 0x0000080c), \
+ PARAM_POLL(0xd4, BIT(8), BIT(8))
+
+#define PARAM_WRITE_828_82C_POLL(_data_828) \
+ PARAM_WRITE_D0_D4(0x0000082c, 0x0f000000), \
+ PARAM_WRITE_D0_D4(0x00000828, _data_828), \
+ PARAM_WRITE(0xd0, 0x0000082c), \
+ PARAM_POLL(0xd4, _data_828, _data_828)
+
+#define PARAM_WRITE_PHY(_addr16, _data16) \
+ PARAM_WRITE(0xf0, 1), \
+ PARAM_WRITE_800_80C_POLL(0x16, (_addr16) & 0xff), \
+ PARAM_WRITE_800_80C_POLL(0x17, ((_addr16) >> 8) & 0xff), \
+ PARAM_WRITE_800_80C_POLL(0x18, (_data16) & 0xff), \
+ PARAM_WRITE_800_80C_POLL(0x19, ((_data16) >> 8) & 0xff), \
+ PARAM_WRITE_800_80C_POLL(0x1c, 0x01), \
+ PARAM_WRITE_828_82C_POLL(0x0f000000), \
+ PARAM_WRITE(0xf0, 0)
+
+#define PARAM_SET_PHY(_addr16, _data16) \
+ PARAM_WRITE(0xf0, 1), \
+ PARAM_WRITE_800_80C_POLL(0x16, (_addr16) & 0xff), \
+ PARAM_WRITE_800_80C_POLL(0x17, ((_addr16) >> 8) & 0xff), \
+ PARAM_WRITE_800_80C_POLL(0x1c, 0x01), \
+ PARAM_WRITE_828_82C_POLL(0x0f000000), \
+ PARAM_WRITE_804_80C_POLL(0x1a, 0), \
+ PARAM_WRITE(0xd0, 0x00000808), \
+ PARAM_SAVE(0xd4, 0xff, SET_PHY_INDEX_LO), \
+ PARAM_WRITE_804_80C_POLL(0x1b, 0), \
+ PARAM_WRITE(0xd0, 0x00000808), \
+ PARAM_SAVE(0xd4, 0xff, SET_PHY_INDEX_HI), \
+ PARAM_WRITE_828_82C_POLL(0x0f000000), \
+ PARAM_WRITE(0xf0, 0), \
+ PARAM_WRITE(0xf0, 1), \
+ PARAM_WRITE_800_80C_POLL(0x16, (_addr16) & 0xff), \
+ PARAM_WRITE_800_80C_POLL(0x17, ((_addr16) >> 8) & 0xff), \
+ PARAM_SET(SET_PHY_INDEX_LO, (((_data16) & 0xff) << 16) | BIT(8) | 0x18), \
+ PARAM_RESTORE_800_80C_POLL(SET_PHY_INDEX_LO), \
+ PARAM_SET(SET_PHY_INDEX_HI, ((((_data16) >> 8) & 0xff) << 16) | BIT(8) | 0x19), \
+ PARAM_RESTORE_800_80C_POLL(SET_PHY_INDEX_HI), \
+ PARAM_WRITE_800_80C_POLL(0x1c, 0x01), \
+ PARAM_WRITE_828_82C_POLL(0x0f000000), \
+ PARAM_WRITE(0xf0, 0)
+
+#define PARAM_INDIRECT_WRITE(_gpio, _addr, _data_800) \
+ PARAM_WRITE(0xf0, _gpio), \
+ PARAM_WRITE_800_80C_POLL((_addr), _data_800), \
+ PARAM_WRITE_828_82C_POLL(0x0f000000), \
+ PARAM_WRITE(0xf0, 0)
+
+#define PARAM_INDIRECT_POLL(_gpio, _addr, _expected, _mask) \
+ PARAM_WRITE(0xf0, _gpio), \
+ PARAM_WRITE_800_80C_POLL((_addr), 0), \
+ PARAM_WRITE(0xd0, 0x00000808), \
+ PARAM_POLL(0xd4, (_expected), (_mask)), \
+ PARAM_WRITE(0xf0, 0)
+
+struct ufs_renesas_init_param {
+ enum ufs_renesas_init_param_mode mode;
+ u32 reg;
+ union {
+ u32 expected;
+ u32 delay_us;
+ u32 set;
+ u32 val;
+ } u;
+ u32 mask;
+ u32 index;
+};
+
+/* This setting is for SERIES B */
+static const struct ufs_renesas_init_param ufs_param[] = {
+ PARAM_WRITE(0xc0, 0x49425308),
+ PARAM_WRITE_D0_D4(0x00000104, 0x00000002),
+ PARAM_WAIT(1),
+ PARAM_WRITE_D0_D4(0x00000828, 0x00000200),
+ PARAM_WAIT(1),
+ PARAM_WRITE_D0_D4(0x00000828, 0x00000000),
+ PARAM_WRITE_D0_D4(0x00000104, 0x00000001),
+ PARAM_WRITE_D0_D4(0x00000940, 0x00000001),
+ PARAM_WAIT(1),
+ PARAM_WRITE_D0_D4(0x00000940, 0x00000000),
+
+ PARAM_WRITE(0xc0, 0x49425308),
+ PARAM_WRITE(0xc0, 0x41584901),
+
+ PARAM_WRITE_D0_D4(0x0000080c, 0x00000100),
+ PARAM_WRITE_D0_D4(0x00000804, 0x00000000),
+ PARAM_WRITE(0xd0, 0x0000080c),
+ PARAM_POLL(0xd4, BIT(8), BIT(8)),
+
+ PARAM_WRITE(REG_CONTROLLER_ENABLE, 0x00000001),
+
+ PARAM_WRITE(0xd0, 0x00000804),
+ PARAM_POLL(0xd4, BIT(8) | BIT(6) | BIT(0), BIT(8) | BIT(6) | BIT(0)),
+
+ PARAM_WRITE(0xd0, 0x00000d00),
+ PARAM_SAVE(0xd4, 0x0000ffff, TIMER_INDEX),
+ PARAM_WRITE(0xd4, 0x00000000),
+ PARAM_WRITE_D0_D4(0x0000082c, 0x0f000000),
+ PARAM_WRITE_D0_D4(0x00000828, 0x08000000),
+ PARAM_WRITE(0xd0, 0x0000082c),
+ PARAM_POLL(0xd4, BIT(27), BIT(27)),
+ PARAM_WRITE(0xd0, 0x00000d2c),
+ PARAM_POLL(0xd4, BIT(0), BIT(0)),
+
+ /* phy setup */
+ PARAM_INDIRECT_WRITE(1, 0x01, 0x001f),
+ PARAM_INDIRECT_WRITE(7, 0x5d, 0x0014),
+ PARAM_INDIRECT_WRITE(7, 0x5e, 0x0014),
+ PARAM_INDIRECT_WRITE(7, 0x0d, 0x0003),
+ PARAM_INDIRECT_WRITE(7, 0x0e, 0x0007),
+ PARAM_INDIRECT_WRITE(7, 0x5f, 0x0003),
+ PARAM_INDIRECT_WRITE(7, 0x60, 0x0003),
+ PARAM_INDIRECT_WRITE(7, 0x5b, 0x00a6),
+ PARAM_INDIRECT_WRITE(7, 0x5c, 0x0003),
+
+ PARAM_INDIRECT_POLL(7, 0x3c, 0, BIT(7)),
+ PARAM_INDIRECT_POLL(7, 0x4c, 0, BIT(4)),
+
+ PARAM_INDIRECT_WRITE(1, 0x32, 0x0080),
+ PARAM_INDIRECT_WRITE(1, 0x1f, 0x0001),
+ PARAM_INDIRECT_WRITE(0, 0x2c, 0x0001),
+ PARAM_INDIRECT_WRITE(0, 0x32, 0x0087),
+
+ PARAM_INDIRECT_WRITE(1, 0x4d, 0x0061),
+ PARAM_INDIRECT_WRITE(4, 0x9b, 0x0009),
+ PARAM_INDIRECT_WRITE(4, 0xa6, 0x0005),
+ PARAM_INDIRECT_WRITE(4, 0xa5, 0x0058),
+ PARAM_INDIRECT_WRITE(1, 0x39, 0x0027),
+ PARAM_INDIRECT_WRITE(1, 0x47, 0x004c),
+
+ PARAM_INDIRECT_WRITE(7, 0x0d, 0x0002),
+ PARAM_INDIRECT_WRITE(7, 0x0e, 0x0007),
+
+ PARAM_WRITE_PHY(0x0028, 0x0061),
+ PARAM_WRITE_PHY(0x4014, 0x0061),
+ PARAM_SET_PHY(0x401c, BIT(2)),
+ PARAM_WRITE_PHY(0x4000, 0x0000),
+ PARAM_WRITE_PHY(0x4001, 0x0000),
+
+ PARAM_WRITE_PHY(0x10ae, 0x0001),
+ PARAM_WRITE_PHY(0x10ad, 0x0000),
+ PARAM_WRITE_PHY(0x10af, 0x0001),
+ PARAM_WRITE_PHY(0x10b6, 0x0001),
+ PARAM_WRITE_PHY(0x10ae, 0x0000),
+
+ PARAM_WRITE_PHY(0x10ae, 0x0001),
+ PARAM_WRITE_PHY(0x10ad, 0x0000),
+ PARAM_WRITE_PHY(0x10af, 0x0002),
+ PARAM_WRITE_PHY(0x10b6, 0x0001),
+ PARAM_WRITE_PHY(0x10ae, 0x0000),
+
+ PARAM_WRITE_PHY(0x10ae, 0x0001),
+ PARAM_WRITE_PHY(0x10ad, 0x0080),
+ PARAM_WRITE_PHY(0x10af, 0x0000),
+ PARAM_WRITE_PHY(0x10b6, 0x0001),
+ PARAM_WRITE_PHY(0x10ae, 0x0000),
+
+ PARAM_WRITE_PHY(0x10ae, 0x0001),
+ PARAM_WRITE_PHY(0x10ad, 0x0080),
+ PARAM_WRITE_PHY(0x10af, 0x001a),
+ PARAM_WRITE_PHY(0x10b6, 0x0001),
+ PARAM_WRITE_PHY(0x10ae, 0x0000),
+
+ PARAM_INDIRECT_WRITE(7, 0x70, 0x0016),
+ PARAM_INDIRECT_WRITE(7, 0x71, 0x0016),
+ PARAM_INDIRECT_WRITE(7, 0x72, 0x0014),
+ PARAM_INDIRECT_WRITE(7, 0x73, 0x0014),
+ PARAM_INDIRECT_WRITE(7, 0x74, 0x0000),
+ PARAM_INDIRECT_WRITE(7, 0x75, 0x0000),
+ PARAM_INDIRECT_WRITE(7, 0x76, 0x0010),
+ PARAM_INDIRECT_WRITE(7, 0x77, 0x0010),
+ PARAM_INDIRECT_WRITE(7, 0x78, 0x00ff),
+ PARAM_INDIRECT_WRITE(7, 0x79, 0x0000),
+
+ PARAM_INDIRECT_WRITE(7, 0x19, 0x0007),
+
+ PARAM_INDIRECT_WRITE(7, 0x1a, 0x0007),
+
+ PARAM_INDIRECT_WRITE(7, 0x24, 0x000c),
+
+ PARAM_INDIRECT_WRITE(7, 0x25, 0x000c),
+
+ PARAM_INDIRECT_WRITE(7, 0x62, 0x0000),
+ PARAM_INDIRECT_WRITE(7, 0x63, 0x0000),
+ PARAM_INDIRECT_WRITE(7, 0x5d, 0x0014),
+ PARAM_INDIRECT_WRITE(7, 0x5e, 0x0017),
+ PARAM_INDIRECT_WRITE(7, 0x5d, 0x0004),
+ PARAM_INDIRECT_WRITE(7, 0x5e, 0x0017),
+ PARAM_INDIRECT_POLL(7, 0x55, 0, BIT(6)),
+ PARAM_INDIRECT_POLL(7, 0x41, 0, BIT(7)),
+ /* end of phy setup */
+
+ PARAM_WRITE(0xf0, 0),
+ PARAM_WRITE(0xd0, 0x00000d00),
+ PARAM_RESTORE(0xd4, TIMER_INDEX),
+};
+
+static void ufs_renesas_reg_control(struct ufs_hba *hba,
+ const struct ufs_renesas_init_param *p)
+{
+ static u32 save[MAX_INDEX];
+ int ret;
+ u32 val;
+
+ WARN_ON(p->index >= MAX_INDEX);
+
+ switch (p->mode) {
+ case MODE_RESTORE:
+ ufshcd_writel(hba, save[p->index], p->reg);
+ break;
+ case MODE_SET:
+ save[p->index] |= p->u.set;
+ break;
+ case MODE_SAVE:
+ save[p->index] = ufshcd_readl(hba, p->reg) & p->mask;
+ break;
+ case MODE_POLL:
+ ret = readl_poll_timeout(hba->mmio_base + p->reg, val,
+ (val & p->mask) == p->u.expected,
+ 10000);
+ if (ret)
+ dev_err(hba->dev, "%s: poll failed %d (%08x, %08x, %08x)\n",
+ __func__, ret, val, p->mask, p->u.expected);
+ break;
+ case MODE_WAIT:
+ if (p->u.delay_us > 1000)
+ mdelay(DIV_ROUND_UP(p->u.delay_us, 1000));
+ else
+ udelay(p->u.delay_us);
+ break;
+ case MODE_WRITE:
+ ufshcd_writel(hba, p->u.val, p->reg);
+ break;
+ default:
+ break;
+ }
+}
+
+static void ufs_renesas_pre_init(struct ufs_hba *hba)
+{
+ const struct ufs_renesas_init_param *p = ufs_param;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(ufs_param); i++)
+ ufs_renesas_reg_control(hba, &p[i]);
+}
+
+static int ufs_renesas_hce_enable_notify(struct ufs_hba *hba,
+ enum ufs_notify_change_status status)
+{
+ struct ufs_renesas_priv *priv = dev_get_priv(hba->dev);
+
+ if (priv->initialized)
+ return 0;
+
+ if (status == PRE_CHANGE)
+ ufs_renesas_pre_init(hba);
+
+ priv->initialized = true;
+
+ return 0;
+}
+
+static int ufs_renesas_init(struct ufs_hba *hba)
+{
+ hba->quirks |= UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS | UFSHCD_QUIRK_HIBERN_FASTAUTO;
+
+ return 0;
+}
+
+static struct ufs_hba_ops ufs_renesas_vops = {
+ .init = ufs_renesas_init,
+ .hce_enable_notify = ufs_renesas_hce_enable_notify,
+};
+
+static int ufs_renesas_pltfm_bind(struct udevice *dev)
+{
+ struct udevice *scsi_dev;
+
+ return ufs_scsi_bind(dev, &scsi_dev);
+}
+
+static int ufs_renesas_pltfm_probe(struct udevice *dev)
+{
+ struct ufs_renesas_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = clk_get_bulk(dev, &priv->clks);
+ if (err < 0)
+ return err;
+
+ err = clk_enable_bulk(&priv->clks);
+ if (err)
+ goto err_clk_enable;
+
+ err = ufshcd_probe(dev, &ufs_renesas_vops);
+ if (err) {
+ dev_err(dev, "ufshcd_probe() failed %d\n", err);
+ goto err_ufshcd_probe;
+ }
+
+ return 0;
+
+err_ufshcd_probe:
+ clk_disable_bulk(&priv->clks);
+err_clk_enable:
+ clk_release_bulk(&priv->clks);
+ return err;
+}
+
+static int ufs_renesas_pltfm_remove(struct udevice *dev)
+{
+ struct ufs_renesas_priv *priv = dev_get_priv(dev);
+
+ clk_disable_bulk(&priv->clks);
+ clk_release_bulk(&priv->clks);
+
+ return 0;
+}
+
+static const struct udevice_id ufs_renesas_pltfm_ids[] = {
+ { .compatible = "renesas,r8a779f0-ufs" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(ufs_renesas) = {
+ .name = "ufs-renesas",
+ .id = UCLASS_UFS,
+ .of_match = ufs_renesas_pltfm_ids,
+ .bind = ufs_renesas_pltfm_bind,
+ .probe = ufs_renesas_pltfm_probe,
+ .remove = ufs_renesas_pltfm_remove,
+ .priv_auto = sizeof(struct ufs_renesas_priv),
+};
diff --git a/drivers/ufs/ufs-uclass.c b/drivers/ufs/ufs-uclass.c
index ceea30c..e6478a9 100644
--- a/drivers/ufs/ufs-uclass.c
+++ b/drivers/ufs/ufs-uclass.c
@@ -2,7 +2,7 @@
/**
* ufs-uclass.c - Universal Flash Subsystem (UFS) Uclass driver
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*/
#define LOG_CATEGORY UCLASS_UFS
diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c
index 3bf1a95..346f0fd 100644
--- a/drivers/ufs/ufs.c
+++ b/drivers/ufs/ufs.c
@@ -5,9 +5,10 @@
* Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported
* to u-boot.
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*/
+#include <bouncebuf.h>
#include <charset.h>
#include <common.h>
#include <dm.h>
@@ -692,13 +693,29 @@
}
/**
+ * ufshcd_cache_flush_and_invalidate - Flush and invalidate cache
+ *
+ * Flush and invalidate cache in aligned address..address+size range.
+ * The invalidation is in place to avoid stale data in cache.
+ */
+static void ufshcd_cache_flush_and_invalidate(void *addr, unsigned long size)
+{
+ uintptr_t aaddr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1);
+ unsigned long asize = ALIGN(size, ARCH_DMA_MINALIGN);
+
+ flush_dcache_range(aaddr, aaddr + asize);
+ invalidate_dcache_range(aaddr, aaddr + asize);
+}
+
+/**
* ufshcd_prepare_req_desc_hdr() - Fills the requests header
* descriptor according to request
*/
-static void ufshcd_prepare_req_desc_hdr(struct utp_transfer_req_desc *req_desc,
+static void ufshcd_prepare_req_desc_hdr(struct ufs_hba *hba,
u32 *upiu_flags,
enum dma_data_direction cmd_dir)
{
+ struct utp_transfer_req_desc *req_desc = hba->utrdl;
u32 data_direction;
u32 dword_0;
@@ -733,6 +750,8 @@
req_desc->header.dword_3 = 0;
req_desc->prd_table_length = 0;
+
+ ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc));
}
static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
@@ -761,10 +780,15 @@
memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, QUERY_OSF_SIZE);
/* Copy the Descriptor */
- if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
+ if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) {
memcpy(ucd_req_ptr + 1, query->descriptor, len);
+ ufshcd_cache_flush_and_invalidate(ucd_req_ptr, 2 * sizeof(*ucd_req_ptr));
+ } else {
+ ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr));
+ }
memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
+ ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr));
}
static inline void ufshcd_prepare_utp_nop_upiu(struct ufs_hba *hba)
@@ -781,6 +805,9 @@
ucd_req_ptr->header.dword_2 = 0;
memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
+
+ ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr));
+ ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr));
}
/**
@@ -792,11 +819,10 @@
{
u32 upiu_flags;
int ret = 0;
- struct utp_transfer_req_desc *req_desc = hba->utrdl;
hba->dev_cmd.type = cmd_type;
- ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, DMA_NONE);
+ ufshcd_prepare_req_desc_hdr(hba, &upiu_flags, DMA_NONE);
switch (cmd_type) {
case DEV_CMD_TYPE_QUERY:
ufshcd_prepare_utp_query_req_upiu(hba, upiu_flags);
@@ -857,7 +883,9 @@
*/
static inline int ufshcd_get_tr_ocs(struct ufs_hba *hba)
{
- return le32_to_cpu(hba->utrdl->header.dword_2) & MASK_OCS;
+ struct utp_transfer_req_desc *req_desc = hba->utrdl;
+
+ return le32_to_cpu(req_desc->header.dword_2) & MASK_OCS;
}
static inline int ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
@@ -1406,6 +1434,8 @@
memcpy(ucd_req_ptr->sc.cdb, pccb->cmd, cdb_len);
memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
+ ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr));
+ ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr));
}
static inline void prepare_prdt_desc(struct ufshcd_sg_entry *entry,
@@ -1420,6 +1450,7 @@
{
struct utp_transfer_req_desc *req_desc = hba->utrdl;
struct ufshcd_sg_entry *prd_table = hba->ucd_prdt_ptr;
+ uintptr_t aaddr = (uintptr_t)(pccb->pdata) & ~(ARCH_DMA_MINALIGN - 1);
ulong datalen = pccb->datalen;
int table_length;
u8 *buf;
@@ -1427,9 +1458,19 @@
if (!datalen) {
req_desc->prd_table_length = 0;
+ ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc));
return;
}
+ if (pccb->dma_dir == DMA_TO_DEVICE) { /* Write to device */
+ flush_dcache_range(aaddr, aaddr +
+ ALIGN(datalen, ARCH_DMA_MINALIGN));
+ }
+
+ /* In any case, invalidate cache to avoid stale data in it. */
+ invalidate_dcache_range(aaddr, aaddr +
+ ALIGN(datalen, ARCH_DMA_MINALIGN));
+
table_length = DIV_ROUND_UP(pccb->datalen, MAX_PRDT_ENTRY);
buf = pccb->pdata;
i = table_length;
@@ -1443,17 +1484,18 @@
prepare_prdt_desc(&prd_table[table_length - i - 1], buf, datalen - 1);
req_desc->prd_table_length = table_length;
+ ufshcd_cache_flush_and_invalidate(prd_table, sizeof(*prd_table) * table_length);
+ ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc));
}
static int ufs_scsi_exec(struct udevice *scsi_dev, struct scsi_cmd *pccb)
{
struct ufs_hba *hba = dev_get_uclass_priv(scsi_dev->parent);
- struct utp_transfer_req_desc *req_desc = hba->utrdl;
u32 upiu_flags;
int ocs, result = 0;
u8 scsi_status;
- ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, pccb->dma_dir);
+ ufshcd_prepare_req_desc_hdr(hba, &upiu_flags, pccb->dma_dir);
ufshcd_prepare_utp_scsi_cmd_upiu(hba, pccb, upiu_flags);
prepare_prdt_table(hba, pccb);
@@ -1630,8 +1672,13 @@
if (hba->max_pwr_info.is_valid)
return 0;
- pwr_info->pwr_tx = FAST_MODE;
- pwr_info->pwr_rx = FAST_MODE;
+ if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) {
+ pwr_info->pwr_tx = FASTAUTO_MODE;
+ pwr_info->pwr_rx = FASTAUTO_MODE;
+ } else {
+ pwr_info->pwr_tx = FAST_MODE;
+ pwr_info->pwr_rx = FAST_MODE;
+ }
pwr_info->hs_rate = PA_HS_MODE_B;
/* Get the connected lane count */
@@ -1889,13 +1936,16 @@
/* Read capabilties registers */
hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
+ if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS)
+ hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT;
/* Get UFS version supported by the controller */
hba->version = ufshcd_get_ufs_version(hba);
if (hba->version != UFSHCI_VERSION_10 &&
hba->version != UFSHCI_VERSION_11 &&
hba->version != UFSHCI_VERSION_20 &&
- hba->version != UFSHCI_VERSION_21)
+ hba->version != UFSHCI_VERSION_21 &&
+ hba->version != UFSHCI_VERSION_30)
dev_err(hba->dev, "invalid UFS version 0x%x\n",
hba->version);
@@ -1942,8 +1992,31 @@
return ret;
}
+#if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
+static int ufs_scsi_buffer_aligned(struct udevice *scsi_dev, struct bounce_buffer *state)
+{
+#ifdef CONFIG_PHYS_64BIT
+ struct ufs_hba *hba = dev_get_uclass_priv(scsi_dev->parent);
+ uintptr_t ubuf = (uintptr_t)state->user_buffer;
+ size_t len = state->len_aligned;
+
+ /* Check if below 32bit boundary */
+ if ((hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS) &&
+ ((ubuf >> 32) || (ubuf + len) >> 32)) {
+ dev_dbg(scsi_dev, "Buffer above 32bit boundary %lx-%lx\n",
+ ubuf, ubuf + len);
+ return 0;
+ }
+#endif
+ return 1;
+}
+#endif /* CONFIG_BOUNCE_BUFFER */
+
static struct scsi_ops ufs_ops = {
.exec = ufs_scsi_exec,
+#if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
+ .buffer_aligned = ufs_scsi_buffer_aligned,
+#endif /* CONFIG_BOUNCE_BUFFER */
};
int ufs_probe_dev(int index)
diff --git a/drivers/ufs/ufs.h b/drivers/ufs/ufs.h
index 8a38832..9daaf03 100644
--- a/drivers/ufs/ufs.h
+++ b/drivers/ufs/ufs.h
@@ -717,7 +717,19 @@
* the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
* attribute of device to 0).
*/
-#define UFSHCD_QUIRK_BROKEN_LCC 0x1
+#define UFSHCD_QUIRK_BROKEN_LCC BIT(0)
+
+/*
+ * This quirk needs to be enabled if the host controller has
+ * 64-bit addressing supported capability but it doesn't work.
+ */
+#define UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS BIT(1)
+
+/*
+ * This quirk needs to be enabled if the host controller has
+ * auto-hibernate capability but it's FASTAUTO only.
+ */
+#define UFSHCD_QUIRK_HIBERN_FASTAUTO BIT(2)
/* Virtual memory reference */
struct utp_transfer_cmd_desc *ucdl;
@@ -769,6 +781,7 @@
UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
+ UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */
};
/* Interrupt disable masks */
diff --git a/drivers/usb/cdns3/cdns3-ti.c b/drivers/usb/cdns3/cdns3-ti.c
index 8958f01..92a7941 100644
--- a/drivers/usb/cdns3/cdns3-ti.c
+++ b/drivers/usb/cdns3/cdns3-ti.c
@@ -2,7 +2,7 @@
/**
* cdns_ti-ti.c - TI specific Glue layer for Cadence USB Controller
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*/
#include <common.h>
diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c
index cae570c..7aa0c6b 100644
--- a/drivers/usb/cdns3/gadget.c
+++ b/drivers/usb/cdns3/gadget.c
@@ -62,6 +62,7 @@
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
+#include <linux/printk.h>
#include <linux/usb/gadget.h>
#include <linux/compat.h>
#include <linux/iopoll.h>
diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c
index cff86a5..7137a56 100644
--- a/drivers/usb/common/common.c
+++ b/drivers/usb/common/common.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <dm.h>
#include <asm/global_data.h>
+#include <linux/printk.h>
#include <linux/usb/otg.h>
#include <linux/usb/ch9.h>
#include <linux/usb/phy.h>
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 49f6a19..3aec8b0 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -2,7 +2,7 @@
/**
* core.c - DesignWare USB3 DRD Controller Core file
*
- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Authors: Felipe Balbi <balbi@ti.com>,
* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
@@ -986,18 +986,18 @@
/**
* dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
- * @index: index of this controller
+ * @dev: device of this controller
*
* Invokes dwc3 gadget interrupts.
*
* Generally called from board file.
*/
-void dwc3_uboot_handle_interrupt(int index)
+void dwc3_uboot_handle_interrupt(struct udevice *dev)
{
struct dwc3 *dwc = NULL;
list_for_each_entry(dwc, &dwc3_list, list) {
- if (dwc->index != index)
+ if (dwc->dev != dev)
continue;
dwc3_gadget_uboot_handle_interrupt(dwc);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 532746d..4162a68 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -2,7 +2,7 @@
/**
* core.h - DesignWare USB3 DRD Core Header
*
- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Authors: Felipe Balbi <balbi@ti.com>,
* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 7f0af05..6fb2de8 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -17,6 +17,7 @@
#include <generic-phy.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <malloc.h>
@@ -541,8 +542,6 @@
} else if (ret != -ENOENT && ret != -ENODATA) {
debug("could not get phy (err %d)\n", ret);
return ret;
- } else {
- phy.dev = NULL;
}
glue->regs = dev_read_addr_size_index(dev, 0, &glue->size);
@@ -555,7 +554,7 @@
if (ret)
return ret;
- if (phy.dev) {
+ if (generic_phy_valid(&phy)) {
ret = generic_phy_power_on(&phy);
if (ret)
return ret;
@@ -611,6 +610,7 @@
{ .compatible = "rockchip,rk3328-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops },
+ { .compatible = "rockchip,rk3588-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "qcom,dwc3" },
{ .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
{ .compatible = "fsl,imx8mq-dwc3" },
diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c
index c62e42d..e0356e6 100644
--- a/drivers/usb/dwc3/dwc3-meson-g12a.c
+++ b/drivers/usb/dwc3/dwc3-meson-g12a.c
@@ -15,6 +15,7 @@
#include <dwc3-uboot.h>
#include <generic-phy.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <malloc.h>
@@ -28,6 +29,7 @@
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/compat.h>
+#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
/* USB2 Ports Control Registers */
@@ -102,10 +104,22 @@
PHY_COUNT,
};
-static const char *phy_names[PHY_COUNT] = {
+static const char *const dwc3_meson_g12a_phy_names[] = {
"usb2-phy0", "usb2-phy1", "usb3-phy0",
};
+static const char *const dwc3_meson_a1_phy_names[] = {
+ "usb2-phy0", "usb2-phy1"
+};
+
+struct dwc3_meson_g12a;
+
+struct dwc3_meson_g12a_drvdata {
+ const char *const *phy_names;
+ unsigned int phy_cnt;
+ int (*clk_init)(struct dwc3_meson_g12a *priv);
+};
+
struct dwc3_meson_g12a {
struct udevice *dev;
struct regmap *regmap;
@@ -119,6 +133,7 @@
#if CONFIG_IS_ENABLED(DM_REGULATOR)
struct udevice *vbus_supply;
#endif
+ struct dwc3_meson_g12a_drvdata *drvdata;
};
#define U2P_REG_SIZE 0x20
@@ -293,10 +308,11 @@
static int dwc3_meson_g12a_get_phys(struct dwc3_meson_g12a *priv)
{
+ struct dwc3_meson_g12a_drvdata *data = priv->drvdata;
int i, ret;
- for (i = 0 ; i < PHY_COUNT ; ++i) {
- ret = generic_phy_get_by_name(priv->dev, phy_names[i],
+ for (i = 0 ; i < data->phy_cnt; ++i) {
+ ret = generic_phy_get_by_name(priv->dev, data->phy_names[i],
&priv->phys[i]);
if (ret == -ENOENT || ret == -ENODATA)
continue;
@@ -354,18 +370,36 @@
return 0;
}
+static int dwc3_meson_a1_clk_init(struct dwc3_meson_g12a *priv)
+{
+ int ret;
+
+ ret = clk_get_by_name(priv->dev, "usb_bus", &priv->clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&priv->clk);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
static int dwc3_meson_g12a_probe(struct udevice *dev)
{
struct dwc3_meson_g12a *priv = dev_get_plat(dev);
+ struct dwc3_meson_g12a_drvdata *data =
+ (struct dwc3_meson_g12a_drvdata *)dev_get_driver_data(dev);
int ret, i;
+ priv->drvdata = data;
priv->dev = dev;
ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
if (ret)
return ret;
- ret = dwc3_meson_g12a_clk_init(priv);
+ ret = data->clk_init(priv);
if (ret)
return ret;
@@ -398,7 +432,7 @@
if (ret)
return ret;
- for (i = 0 ; i < PHY_COUNT ; ++i) {
+ for (i = 0 ; i < data->phy_cnt; ++i) {
if (!priv->phys[i].dev)
continue;
@@ -407,7 +441,7 @@
goto err_phy_init;
}
- for (i = 0; i < PHY_COUNT; ++i) {
+ for (i = 0; i < data->phy_cnt; ++i) {
if (!priv->phys[i].dev)
continue;
@@ -419,7 +453,7 @@
return 0;
err_phy_init:
- for (i = 0 ; i < PHY_COUNT ; ++i) {
+ for (i = 0 ; i < data->phy_cnt ; ++i) {
if (!priv->phys[i].dev)
continue;
@@ -432,20 +466,21 @@
static int dwc3_meson_g12a_remove(struct udevice *dev)
{
struct dwc3_meson_g12a *priv = dev_get_plat(dev);
+ struct dwc3_meson_g12a_drvdata *data = priv->drvdata;
int i;
reset_release_all(&priv->reset, 1);
clk_release_all(&priv->clk, 1);
- for (i = 0; i < PHY_COUNT; ++i) {
+ for (i = 0; i < data->phy_cnt; ++i) {
if (!priv->phys[i].dev)
continue;
generic_phy_power_off(&priv->phys[i]);
}
- for (i = 0 ; i < PHY_COUNT ; ++i) {
+ for (i = 0 ; i < data->phy_cnt; ++i) {
if (!priv->phys[i].dev)
continue;
@@ -455,11 +490,26 @@
return dm_scan_fdt_dev(dev);
}
+static const struct dwc3_meson_g12a_drvdata meson_g12a_drvdata = {
+ .phy_names = dwc3_meson_g12a_phy_names,
+ .phy_cnt = ARRAY_SIZE(dwc3_meson_g12a_phy_names),
+ .clk_init = dwc3_meson_g12a_clk_init,
+};
+
+static const struct dwc3_meson_g12a_drvdata meson_a1_drvdata = {
+ .phy_names = dwc3_meson_a1_phy_names,
+ .phy_cnt = ARRAY_SIZE(dwc3_meson_a1_phy_names),
+ .clk_init = dwc3_meson_a1_clk_init,
+};
+
static int dwc3_meson_g12a_child_pre_probe(struct udevice *dev)
{
if (ofnode_device_is_compatible(dev_ofnode(dev), "amlogic,meson-g12a-usb"))
return dwc3_meson_g12a_force_mode(dev->parent, USB_DR_MODE_PERIPHERAL);
+ if (ofnode_device_is_compatible(dev_ofnode(dev), "amlogic,meson-a1-usb"))
+ return dwc3_meson_g12a_force_mode(dev->parent, USB_DR_MODE_PERIPHERAL);
+
return 0;
}
@@ -468,11 +518,21 @@
if (ofnode_device_is_compatible(dev_ofnode(dev), "amlogic,meson-g12a-usb"))
return dwc3_meson_g12a_force_mode(dev->parent, USB_DR_MODE_HOST);
+ if (ofnode_device_is_compatible(dev_ofnode(dev), "amlogic,meson-a1-usb"))
+ return dwc3_meson_g12a_force_mode(dev->parent, USB_DR_MODE_HOST);
+
return 0;
}
static const struct udevice_id dwc3_meson_g12a_ids[] = {
- { .compatible = "amlogic,meson-g12a-usb-ctrl" },
+ {
+ .compatible = "amlogic,meson-g12a-usb-ctrl",
+ .data = (ulong)&meson_g12a_drvdata,
+ },
+ {
+ .compatible = "amlogic,meson-a1-usb-ctrl",
+ .data = (ulong)&meson_a1_drvdata,
+ },
{ }
};
diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c
index 9596bf1..4fadb4a 100644
--- a/drivers/usb/dwc3/dwc3-omap.c
+++ b/drivers/usb/dwc3/dwc3-omap.c
@@ -2,7 +2,7 @@
/**
* dwc3-omap.c - OMAP Specific Glue layer
*
- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Authors: Felipe Balbi <balbi@ti.com>,
* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
@@ -119,7 +119,7 @@
#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1)
struct dwc3_omap {
- struct device *dev;
+ struct udevice *dev;
void __iomem *base;
@@ -429,19 +429,19 @@
/**
* dwc3_omap_uboot_interrupt_status - check the status of interrupt
- * @index: index of this controller
+ * @dev: device of this controller
*
* Checks the status of interrupts and returns true if an interrupt
* is detected or false otherwise.
*
* Generally called from board file.
*/
-int dwc3_omap_uboot_interrupt_status(int index)
+int dwc3_omap_uboot_interrupt_status(struct udevice *dev)
{
struct dwc3_omap *omap = NULL;
list_for_each_entry(omap, &dwc3_omap_list, list)
- if (omap->index == index)
+ if (omap->dev == dev)
return dwc3_omap_interrupt(-1, omap);
return 0;
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 75ac993..1133cf8 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -2,7 +2,7 @@
/**
* ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
*
- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Authors: Felipe Balbi <balbi@ti.com>,
* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index eb416b8..406d36c 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -2,7 +2,7 @@
/**
* gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
*
- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Authors: Felipe Balbi <balbi@ti.com>,
* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
@@ -24,6 +24,7 @@
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/list.h>
+#include <linux/printk.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
diff --git a/drivers/usb/dwc3/gadget.h b/drivers/usb/dwc3/gadget.h
index 7806ce5..f28a975 100644
--- a/drivers/usb/dwc3/gadget.h
+++ b/drivers/usb/dwc3/gadget.h
@@ -2,7 +2,7 @@
/**
* gadget.h - DesignWare USB3 DRD Gadget Header
*
- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Authors: Felipe Balbi <balbi@ti.com>,
* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h
index 2407f82..04791d4 100644
--- a/drivers/usb/dwc3/io.h
+++ b/drivers/usb/dwc3/io.h
@@ -2,7 +2,7 @@
/**
* io.h - DesignWare USB3 DRD IO Header
*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com
*
* Authors: Felipe Balbi <balbi@ti.com>,
* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
diff --git a/drivers/usb/dwc3/linux-compat.h b/drivers/usb/dwc3/linux-compat.h
index 3bb0bda..563f872 100644
--- a/drivers/usb/dwc3/linux-compat.h
+++ b/drivers/usb/dwc3/linux-compat.h
@@ -2,7 +2,7 @@
/**
* linux-compat.h - DesignWare USB3 Linux Compatibiltiy Adapter Header
*
- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Authors: Kishon Vijay Abraham I <kishon@ti.com>
*
diff --git a/drivers/usb/dwc3/ti_usb_phy.c b/drivers/usb/dwc3/ti_usb_phy.c
index f476810..8ae1308 100644
--- a/drivers/usb/dwc3/ti_usb_phy.c
+++ b/drivers/usb/dwc3/ti_usb_phy.c
@@ -2,7 +2,7 @@
/**
* ti_usb_phy.c - USB3 and USB3 PHY programming for dwc3
*
- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Author: Kishon Vijay Abraham I <kishon@ti.com>
*
diff --git a/drivers/usb/eth/mcs7830.c b/drivers/usb/eth/mcs7830.c
index 8a256b3..d94204f 100644
--- a/drivers/usb/eth/mcs7830.c
+++ b/drivers/usb/eth/mcs7830.c
@@ -19,6 +19,7 @@
#include <malloc.h>
#include <memalign.h>
#include <usb.h>
+#include <linux/printk.h>
#include "usb_ether.h"
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 1cfe602..4eccc5e 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -160,7 +160,7 @@
config SDP_LOADADDR
hex "Default load address at SDP_WRITE and SDP_JUMP"
- default 0
+ default 0x0
# Selected by UDC drivers that support high-speed operation.
config USB_GADGET_DUALSPEED
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index 1feed41..e573a03 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -21,6 +21,7 @@
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/hardware.h>
+#include <linux/printk.h>
#include <mach/at91_matrix.h>
#include <linux/list.h>
#include <linux/usb/ch9.h>
@@ -1429,7 +1430,7 @@
};
#endif
-int usb_gadget_handle_interrupts(int index)
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
{
struct at91_udc *udc = controller;
diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index 7d51821..4c42074 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -13,6 +13,7 @@
#include <asm/gpio.h>
#include <asm/hardware.h>
#include <linux/list.h>
+#include <linux/printk.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/atmel_usba_udc.h>
@@ -57,13 +58,9 @@
req->submitted = 1;
next_fifo_transaction(ep, req);
- if (req->last_transaction) {
- usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
- usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
- } else {
+ if (ep_is_control(ep))
usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
- usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
- }
+ usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
}
static void submit_next_request(struct usba_ep *ep)
@@ -889,7 +886,6 @@
if (req) {
list_del_init(&req->queue);
request_complete(ep, req, 0);
- submit_next_request(ep);
}
usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
ep->state = WAIT_FOR_SETUP;
@@ -1036,7 +1032,6 @@
DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name);
if (list_empty(&ep->queue)) {
- DBG(DBG_INT, "ep_irq: queue empty\n");
usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
return;
}
@@ -1050,7 +1045,6 @@
if (req->last_transaction) {
list_del_init(&req->queue);
- submit_next_request(ep);
request_complete(ep, req, 0);
}
@@ -1198,14 +1192,13 @@
},
};
-int usb_gadget_handle_interrupts(int index)
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
{
struct usba_udc *udc = &controller;
return usba_udc_irq(udc);
}
-
int usb_gadget_register_driver(struct usb_gadget_driver *driver)
{
struct usba_udc *udc = &controller;
diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c
index b9258d7..750d471 100644
--- a/drivers/usb/gadget/ci_udc.c
+++ b/drivers/usb/gadget/ci_udc.c
@@ -13,6 +13,7 @@
#include <cpu_func.h>
#include <net.h>
#include <malloc.h>
+#include <wait_bit.h>
#include <asm/byteorder.h>
#include <asm/cache.h>
#include <linux/delay.h>
@@ -354,12 +355,49 @@
return 0;
}
+static int ep_disable(int num, int in)
+{
+ struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
+ unsigned int ep_bit, enable_bit;
+ int err;
+
+ if (in) {
+ ep_bit = EPT_TX(num);
+ enable_bit = CTRL_TXE;
+ } else {
+ ep_bit = EPT_RX(num);
+ enable_bit = CTRL_RXE;
+ }
+
+ /* clear primed buffers */
+ do {
+ writel(ep_bit, &udc->epflush);
+ err = wait_for_bit_le32(&udc->epflush, ep_bit, false, 1000, false);
+ if (err)
+ return err;
+ } while (readl(&udc->epstat) & ep_bit);
+
+ /* clear enable bit */
+ clrbits_le32(&udc->epctrl[num], enable_bit);
+
+ return 0;
+}
+
static int ci_ep_disable(struct usb_ep *ep)
{
struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
+ int num, in, err;
+
+ num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+ in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
+
+ err = ep_disable(num, in);
+ if (err)
+ return err;
ci_ep->desc = NULL;
ep->desc = NULL;
+ ci_ep->req_primed = false;
return 0;
}
@@ -869,10 +907,10 @@
}
}
-int usb_gadget_handle_interrupts(int index)
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
{
- u32 value;
struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
+ u32 value;
value = readl(&udc->usbsts);
if (value)
diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c
index 2bf7ed8..27082f5 100644
--- a/drivers/usb/gadget/dwc2_udc_otg.c
+++ b/drivers/usb/gadget/dwc2_udc_otg.c
@@ -28,6 +28,7 @@
#include <dm/devres.h>
#include <linux/bug.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <linux/errno.h>
#include <linux/list.h>
@@ -941,15 +942,12 @@
return 0;
}
-#if !CONFIG_IS_ENABLED(DM_USB_GADGET)
-
-int usb_gadget_handle_interrupts(int index)
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
{
return dwc2_udc_handle_interrupt();
}
-#else /* CONFIG_IS_ENABLED(DM_USB_GADGET) */
-
+#if CONFIG_IS_ENABLED(DM_USB_GADGET)
struct dwc2_priv_data {
struct clk_bulk clks;
struct reset_ctl_bulk resets;
@@ -957,11 +955,6 @@
struct udevice *usb33d_supply;
};
-int dm_usb_gadget_handle_interrupts(struct udevice *dev)
-{
- return dwc2_udc_handle_interrupt();
-}
-
static int dwc2_phy_setup(struct udevice *dev, struct phy_bulk *phys)
{
int ret;
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index 5ff06d3..36618f0 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -14,6 +14,7 @@
#include <part.h>
#include <linux/errno.h>
#include <linux/netdevice.h>
+#include <linux/printk.h>
#include <linux/usb/ch9.h>
#include <linux/usb/cdc.h>
#include <linux/usb/gadget.h>
@@ -1880,8 +1881,10 @@
}
}
-static int eth_stop(struct eth_dev *dev)
+static int eth_stop(struct udevice *udev)
{
+ struct ether_priv *priv = dev_get_priv(udev);
+ struct eth_dev *dev = &priv->ethdev;
#ifdef RNDIS_COMPLETE_SIGNAL_DISCONNECT
unsigned long ts;
unsigned long timeout = CONFIG_SYS_HZ; /* 1 sec to stop RNDIS */
@@ -1895,7 +1898,7 @@
/* Wait until host receives OID_GEN_MEDIA_CONNECT_STATUS */
ts = get_timer(0);
while (get_timer(ts) < timeout)
- usb_gadget_handle_interrupts(0);
+ dm_usb_gadget_handle_interrupts(udev->parent);
#endif
rndis_uninit(dev->rndis_config);
@@ -2300,7 +2303,7 @@
pr_err("The remote end did not respond in time.");
goto fail;
}
- usb_gadget_handle_interrupts(0);
+ dm_usb_gadget_handle_interrupts(udev->parent);
}
packet_received = 0;
@@ -2370,7 +2373,7 @@
printf("timeout sending packets to usb ethernet\n");
return -1;
}
- usb_gadget_handle_interrupts(0);
+ dm_usb_gadget_handle_interrupts(udev->parent);
}
free(rndis_pkt);
@@ -2400,13 +2403,13 @@
* 2) 'pullup' callback in your UDC driver can be improved to perform
* this deinitialization.
*/
- eth_stop(dev);
+ eth_stop(udev);
usb_gadget_disconnect(dev->gadget);
/* Clear pending interrupt */
if (dev->network_started) {
- usb_gadget_handle_interrupts(0);
+ dm_usb_gadget_handle_interrupts(udev->parent);
dev->network_started = 0;
}
}
@@ -2416,7 +2419,7 @@
struct ether_priv *priv = dev_get_priv(dev);
struct eth_dev *ethdev = &priv->ethdev;
- usb_gadget_handle_interrupts(0);
+ dm_usb_gadget_handle_interrupts(dev->parent);
if (packet_received) {
if (ethdev->rx_req) {
@@ -2467,7 +2470,7 @@
return ret;
}
- return usb_gadget_initialize(0);
+ return 0;
}
static int usb_eth_probe(struct udevice *dev)
@@ -2528,7 +2531,7 @@
static int usb_eth_unbind(struct udevice *dev)
{
- usb_gadget_release(0);
+ udc_device_put(dev->parent);
return 0;
}
diff --git a/drivers/usb/gadget/f_acm.c b/drivers/usb/gadget/f_acm.c
index b2ddd1a..de42e01 100644
--- a/drivers/usb/gadget/f_acm.c
+++ b/drivers/usb/gadget/f_acm.c
@@ -51,7 +51,7 @@
#define ACM_CTRL_RTS BIT(1) /* unused with full duplex */
#define ACM_CTRL_DTR BIT(0) /* host is ready for data r/w */
- int controller_index;
+ struct udevice *udc;
};
static struct f_acm *default_acm_function;
@@ -489,7 +489,7 @@
int len, ret;
do {
- usb_gadget_handle_interrupts(f_acm->controller_index);
+ dm_usb_gadget_handle_interrupts(f_acm->udc);
if (!(f_acm->handshake_bits & ACM_CTRL_DTR))
break;
@@ -520,7 +520,7 @@
struct f_acm *f_acm = stdio_to_acm(dev);
/* give a chance to process udc irq */
- usb_gadget_handle_interrupts(f_acm->controller_index);
+ dm_usb_gadget_handle_interrupts(f_acm->udc);
return f_acm->connected;
}
@@ -543,7 +543,10 @@
f_acm->usb_function.descriptors = acm_fs_function;
f_acm->usb_function.hs_descriptors = acm_hs_function;
f_acm->usb_function.setup = acm_setup;
- f_acm->controller_index = 0;
+
+ status = udc_device_get_by_index(0, &f_acm->udc);
+ if (status)
+ return status;
status = usb_add_function(c, &f_acm->usb_function);
if (status) {
@@ -567,7 +570,7 @@
{
struct f_acm *f_acm = stdio_to_acm(dev);
- usb_gadget_handle_interrupts(f_acm->controller_index);
+ dm_usb_gadget_handle_interrupts(f_acm->udc);
return (f_acm->rx_buf.size > 0);
}
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index 6d97b4b..9f322c9 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -17,6 +17,7 @@
#include <fastboot.h>
#include <log.h>
#include <malloc.h>
+#include <linux/printk.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/composite.h>
@@ -519,7 +520,7 @@
cmdbuf[req->actual] = '\0';
cmd = fastboot_handle_command(cmdbuf, response);
} else {
- pr_err("buffer overflow");
+ pr_err("buffer overflow\n");
fastboot_fail("buffer overflow", response);
}
diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
index f46829e..1d17331 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -435,7 +435,7 @@
static struct ums *ums;
static int ums_count;
static struct fsg_common *the_fsg_common;
-static unsigned int controller_index;
+static struct udevice *udcdev;
static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep)
{
@@ -680,7 +680,7 @@
k = 0;
}
- usb_gadget_handle_interrupts(controller_index);
+ dm_usb_gadget_handle_interrupts(udcdev);
}
common->thread_wakeup_needed = 0;
return rc;
@@ -2764,11 +2764,11 @@
return fsg_bind_config(c->cdev, c, fsg_common);
}
-int fsg_init(struct ums *ums_devs, int count, unsigned int controller_idx)
+int fsg_init(struct ums *ums_devs, int count, struct udevice *udc)
{
ums = ums_devs;
ums_count = count;
- controller_index = controller_idx;
+ udcdev = udc;
return 0;
}
diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c
index 4da5a16..ee9384f 100644
--- a/drivers/usb/gadget/f_sdp.c
+++ b/drivers/usb/gadget/f_sdp.c
@@ -22,6 +22,7 @@
#include <env.h>
#include <log.h>
#include <malloc.h>
+#include <linux/printk.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
@@ -33,6 +34,7 @@
#include <spl.h>
#include <image.h>
#include <imximage.h>
+#include <imx_container.h>
#include <watchdog.h>
#define HID_REPORT_ID_MASK 0x000000ff
@@ -702,7 +704,7 @@
return status;
}
-int sdp_init(int controller_index)
+int sdp_init(struct udevice *udc)
{
printf("SDP: initialize...\n");
while (!sdp_func->configuration_done) {
@@ -712,7 +714,7 @@
}
schedule();
- usb_gadget_handle_interrupts(controller_index);
+ dm_usb_gadget_handle_interrupts(udc);
}
return 0;
@@ -851,7 +853,8 @@
return SDP_EXIT;
}
#endif
- if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) {
+ if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) &&
+ valid_container_hdr((void *)header)) {
struct spl_load_info load;
load.dev = header;
@@ -911,9 +914,9 @@
}
#ifndef CONFIG_SPL_BUILD
-int sdp_handle(int controller_index)
+int sdp_handle(struct udevice *udc)
#else
-int spl_sdp_handle(int controller_index, struct spl_image_info *spl_image,
+int spl_sdp_handle(struct udevice *udc, struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
#endif
{
@@ -929,7 +932,7 @@
return 0;
schedule();
- usb_gadget_handle_interrupts(controller_index);
+ dm_usb_gadget_handle_interrupts(udc);
#ifdef CONFIG_SPL_BUILD
flag = sdp_handle_in_ep(spl_image, bootdev);
diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c
index 47ef55b..0e7529d 100644
--- a/drivers/usb/gadget/f_thor.c
+++ b/drivers/usb/gadget/f_thor.c
@@ -15,15 +15,17 @@
*/
#include <command.h>
-#include <errno.h>
#include <common.h>
#include <console.h>
+#include <dm.h>
+#include <errno.h>
#include <init.h>
#include <log.h>
#include <malloc.h>
#include <memalign.h>
#include <version.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/composite.h>
@@ -34,9 +36,9 @@
#include "f_thor.h"
-static void thor_tx_data(unsigned char *data, int len);
+static void thor_tx_data(struct udevice *udc, unsigned char *data, int len);
static void thor_set_dma(void *addr, int len);
-static int thor_rx_data(void);
+static int thor_rx_data(struct udevice *udc);
static struct f_thor *thor_func;
static inline struct f_thor *func_to_thor(struct usb_function *f)
@@ -56,15 +58,15 @@
static unsigned long long int thor_file_size;
static int alt_setting_num;
-static void send_rsp(const struct rsp_box *rsp)
+static void send_rsp(struct udevice *udc, const struct rsp_box *rsp)
{
memcpy(thor_tx_data_buf, rsp, sizeof(struct rsp_box));
- thor_tx_data(thor_tx_data_buf, sizeof(struct rsp_box));
+ thor_tx_data(udc, thor_tx_data_buf, sizeof(struct rsp_box));
debug("-RSP: %d, %d\n", rsp->rsp, rsp->rsp_data);
}
-static void send_data_rsp(s32 ack, s32 count)
+static void send_data_rsp(struct udevice *udc, s32 ack, s32 count)
{
ALLOC_CACHE_ALIGN_BUFFER(struct data_rsp_box, rsp,
sizeof(struct data_rsp_box));
@@ -73,12 +75,12 @@
rsp->count = count;
memcpy(thor_tx_data_buf, rsp, sizeof(struct data_rsp_box));
- thor_tx_data(thor_tx_data_buf, sizeof(struct data_rsp_box));
+ thor_tx_data(udc, thor_tx_data_buf, sizeof(struct data_rsp_box));
debug("-DATA RSP: %d, %d\n", ack, count);
}
-static int process_rqt_info(const struct rqt_box *rqt)
+static int process_rqt_info(struct udevice *udc, const struct rqt_box *rqt)
{
ALLOC_CACHE_ALIGN_BUFFER(struct rsp_box, rsp, sizeof(struct rsp_box));
memset(rsp, 0, sizeof(struct rsp_box));
@@ -111,11 +113,11 @@
return -EINVAL;
}
- send_rsp(rsp);
+ send_rsp(udc, rsp);
return true;
}
-static int process_rqt_cmd(const struct rqt_box *rqt)
+static int process_rqt_cmd(struct udevice *udc, const struct rqt_box *rqt)
{
ALLOC_CACHE_ALIGN_BUFFER(struct rsp_box, rsp, sizeof(struct rsp_box));
memset(rsp, 0, sizeof(struct rsp_box));
@@ -126,7 +128,7 @@
switch (rqt->rqt_data) {
case RQT_CMD_REBOOT:
debug("TARGET RESET\n");
- send_rsp(rsp);
+ send_rsp(udc, rsp);
g_dnl_unregister();
dfu_free_entities();
#ifdef CONFIG_THOR_RESET_OFF
@@ -136,7 +138,7 @@
break;
case RQT_CMD_POWEROFF:
case RQT_CMD_EFSCLEAR:
- send_rsp(rsp);
+ send_rsp(udc, rsp);
default:
printf("Command not supported -> cmd: %d\n", rqt->rqt_data);
return -EINVAL;
@@ -145,7 +147,8 @@
return true;
}
-static long long int download_head(unsigned long long total,
+static long long int download_head(struct udevice *udc,
+ unsigned long long total,
unsigned int packet_size,
long long int *left,
int *cnt)
@@ -166,7 +169,7 @@
while (total - rcv_cnt >= packet_size) {
thor_set_dma(buf, packet_size);
buf += packet_size;
- ret_rcv = thor_rx_data();
+ ret_rcv = thor_rx_data(udc);
if (ret_rcv < 0)
return ret_rcv;
rcv_cnt += ret_rcv;
@@ -184,7 +187,7 @@
}
buf = transfer_buffer;
}
- send_data_rsp(0, ++usb_pkt_cnt);
+ send_data_rsp(udc, 0, ++usb_pkt_cnt);
}
/* Calculate the amount of data to arrive from PC (in bytes) */
@@ -200,11 +203,11 @@
if (left_to_rcv) {
thor_set_dma(buf, packet_size);
- ret_rcv = thor_rx_data();
+ ret_rcv = thor_rx_data(udc);
if (ret_rcv < 0)
return ret_rcv;
rcv_cnt += ret_rcv;
- send_data_rsp(0, ++usb_pkt_cnt);
+ send_data_rsp(udc, 0, ++usb_pkt_cnt);
}
debug("%s: %llu total: %llu cnt: %d\n", __func__, rcv_cnt, total, *cnt);
@@ -254,7 +257,7 @@
return ret;
}
-static long long int process_rqt_download(const struct rqt_box *rqt)
+static long long int process_rqt_download(struct udevice *udc, const struct rqt_box *rqt)
{
ALLOC_CACHE_ALIGN_BUFFER(struct rsp_box, rsp, sizeof(struct rsp_box));
static long long int left, ret_head;
@@ -301,8 +304,8 @@
}
break;
case RQT_DL_FILE_START:
- send_rsp(rsp);
- ret_head = download_head(thor_file_size, THOR_PACKET_SIZE,
+ send_rsp(udc, rsp);
+ ret_head = download_head(udc, thor_file_size, THOR_PACKET_SIZE,
&left, &cnt);
if (ret_head < 0) {
left = 0;
@@ -324,11 +327,11 @@
ret = -ENOTSUPP;
}
- send_rsp(rsp);
+ send_rsp(udc, rsp);
return ret;
}
-static int process_data(void)
+static int process_data(struct udevice *udc)
{
ALLOC_CACHE_ALIGN_BUFFER(struct rqt_box, rqt, sizeof(struct rqt_box));
int ret = -EINVAL;
@@ -339,13 +342,13 @@
switch (rqt->rqt) {
case RQT_INFO:
- ret = process_rqt_info(rqt);
+ ret = process_rqt_info(udc, rqt);
break;
case RQT_CMD:
- ret = process_rqt_cmd(rqt);
+ ret = process_rqt_cmd(udc, rqt);
break;
case RQT_DL:
- ret = (int) process_rqt_download(rqt);
+ ret = (int) process_rqt_download(udc, rqt);
break;
case RQT_UL:
puts("RQT: UPLOAD not supported!\n");
@@ -536,7 +539,7 @@
return req;
}
-static int thor_rx_data(void)
+static int thor_rx_data(struct udevice *udc)
{
struct thor_dev *dev = thor_func->dev;
int data_to_rx, tmp, status;
@@ -557,7 +560,7 @@
}
while (!dev->rxdata) {
- usb_gadget_handle_interrupts(0);
+ dm_usb_gadget_handle_interrupts(udc);
if (ctrlc())
return -1;
}
@@ -568,7 +571,7 @@
return tmp;
}
-static void thor_tx_data(unsigned char *data, int len)
+static void thor_tx_data(struct udevice *udc, unsigned char *data, int len)
{
struct thor_dev *dev = thor_func->dev;
unsigned char *ptr = dev->in_req->buf;
@@ -591,7 +594,7 @@
/* Wait until tx interrupt received */
while (!dev->txdata)
- usb_gadget_handle_interrupts(0);
+ dm_usb_gadget_handle_interrupts(udc);
dev->txdata = 0;
}
@@ -685,18 +688,18 @@
dev->out_req->length = len;
}
-int thor_init(void)
+int thor_init(struct udevice *udc)
{
struct thor_dev *dev = thor_func->dev;
/* Wait for a device enumeration and configuration settings */
debug("THOR enumeration/configuration setting....\n");
while (!dev->configuration_done)
- usb_gadget_handle_interrupts(0);
+ dm_usb_gadget_handle_interrupts(udc);
thor_set_dma(thor_rx_data_buf, strlen("THOR"));
/* detect the download request from Host PC */
- if (thor_rx_data() < 0) {
+ if (thor_rx_data(udc) < 0) {
printf("%s: Data not received!\n", __func__);
return -1;
}
@@ -706,7 +709,7 @@
udelay(30 * 1000); /* 30 ms */
strcpy((char *)thor_tx_data_buf, "ROHT");
- thor_tx_data(thor_tx_data_buf, strlen("ROHT"));
+ thor_tx_data(udc, thor_tx_data_buf, strlen("ROHT"));
} else {
puts("Wrong reply information\n");
return -1;
@@ -715,17 +718,17 @@
return 0;
}
-int thor_handle(void)
+int thor_handle(struct udevice *udc)
{
int ret;
/* receive the data from Host PC */
while (1) {
thor_set_dma(thor_rx_data_buf, sizeof(struct rqt_box));
- ret = thor_rx_data();
+ ret = thor_rx_data(udc);
if (ret > 0) {
- ret = process_data();
+ ret = process_data(udc);
#ifdef CONFIG_THOR_RESET_OFF
if (ret == RESET_DONE)
break;
diff --git a/drivers/usb/gadget/udc/Makefile b/drivers/usb/gadget/udc/Makefile
index 95dbf0c..467c566 100644
--- a/drivers/usb/gadget/udc/Makefile
+++ b/drivers/usb/gadget/udc/Makefile
@@ -7,4 +7,4 @@
endif
obj-$(CONFIG_$(SPL_)DM_USB_GADGET) += udc-core.o
-obj-$(CONFIG_$(SPL_)DM) += udc-uclass.o
+obj-y += udc-uclass.o
diff --git a/drivers/usb/gadget/udc/udc-core.c b/drivers/usb/gadget/udc/udc-core.c
index 7f73926..eb0b359 100644
--- a/drivers/usb/gadget/udc/udc-core.c
+++ b/drivers/usb/gadget/udc/udc-core.c
@@ -2,7 +2,7 @@
/**
* udc-core.c - Core UDC Framework
*
- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Author: Felipe Balbi <balbi@ti.com>
*
diff --git a/drivers/usb/gadget/udc/udc-uclass.c b/drivers/usb/gadget/udc/udc-uclass.c
index de88618..30ee1ca 100644
--- a/drivers/usb/gadget/udc/udc-uclass.c
+++ b/drivers/usb/gadget/udc/udc-uclass.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
* Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
@@ -9,58 +9,58 @@
#include <common.h>
#include <dm.h>
#include <dm/device-internal.h>
+#include <linux/printk.h>
#include <linux/usb/gadget.h>
#if CONFIG_IS_ENABLED(DM_USB_GADGET)
-#define MAX_UDC_DEVICES 4
-static struct udevice *dev_array[MAX_UDC_DEVICES];
-int usb_gadget_initialize(int index)
+int udc_device_get_by_index(int index, struct udevice **udev)
{
- int ret;
struct udevice *dev = NULL;
+ int ret;
- if (index < 0 || index >= ARRAY_SIZE(dev_array))
- return -EINVAL;
- if (dev_array[index])
- return 0;
ret = uclass_get_device_by_seq(UCLASS_USB_GADGET_GENERIC, index, &dev);
- if (!dev || ret) {
- ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, index, &dev);
- if (!dev || ret) {
- pr_err("No USB device found\n");
- return -ENODEV;
- }
+ if (!ret && dev) {
+ *udev = dev;
+ return 0;
}
- dev_array[index] = dev;
- return 0;
+
+ ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, index, &dev);
+ if (!ret && dev) {
+ *udev = dev;
+ return 0;
+ }
+
+ pr_err("No USB device found\n");
+ return -ENODEV;
}
-int usb_gadget_release(int index)
+int udc_device_put(struct udevice *udev)
{
#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
- int ret;
- if (index < 0 || index >= ARRAY_SIZE(dev_array))
- return -EINVAL;
-
- ret = device_remove(dev_array[index], DM_REMOVE_NORMAL);
- if (!ret)
- dev_array[index] = NULL;
- return ret;
+ return device_remove(udev, DM_REMOVE_NORMAL);
#else
return -ENOSYS;
#endif
}
-
-int usb_gadget_handle_interrupts(int index)
+#else
+/* Backwards hardware compatibility -- switch to DM_USB_GADGET */
+static int legacy_index;
+int udc_device_get_by_index(int index, struct udevice **udev)
{
- if (index < 0 || index >= ARRAY_SIZE(dev_array))
- return -EINVAL;
- return dm_usb_gadget_handle_interrupts(dev_array[index]);
+ legacy_index = index;
+ return board_usb_init(index, USB_INIT_DEVICE);
+}
+
+int udc_device_put(struct udevice *udev)
+{
+ return board_usb_cleanup(legacy_index, USB_INIT_DEVICE);
}
#endif
+#if CONFIG_IS_ENABLED(DM)
UCLASS_DRIVER(usb_gadget_generic) = {
.id = UCLASS_USB_GADGET_GENERIC,
.name = "usb",
.flags = DM_UC_FLAG_SEQ_ALIAS,
};
+#endif
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 1a883ba..35610ff 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -90,7 +90,7 @@
config USB_XHCI_PCI
bool "Support for PCI-based xHCI USB controller"
- depends on DM_USB
+ depends on DM_USB && PCI
default y if X86
help
Enables support for the PCI-based xHCI controller.
@@ -231,7 +231,6 @@
config USB_EHCI_NPCM
bool "Support for Nuvoton NPCM on-chip EHCI USB controller"
depends on ARCH_NPCM
- default n
---help---
Enables support for the on-chip EHCI controller on
Nuvoton NPCM chips.
@@ -368,7 +367,6 @@
config USB_OHCI_NPCM
bool "Support for Nuvoton NPCM on-chip OHCI USB controller"
depends on ARCH_NPCM
- default n
---help---
Enables support for the on-chip OHCI controller on
Nuvoton NPCM chips.
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 9818f9b..637eb2d 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -194,8 +194,8 @@
return 0;
}
- ret = regulator_set_enable(priv->vbus_supply, true);
- if (ret) {
+ ret = regulator_set_enable_if_allowed(priv->vbus_supply, true);
+ if (ret && ret != -ENOSYS) {
dev_err(dev, "Error enabling vbus supply\n");
return ret;
}
@@ -208,12 +208,10 @@
struct dwc2_priv *priv = dev_get_priv(dev);
int ret;
- if (priv->vbus_supply) {
- ret = regulator_set_enable(priv->vbus_supply, false);
- if (ret) {
- dev_err(dev, "Error disabling vbus supply\n");
- return ret;
- }
+ ret = regulator_set_enable_if_allowed(priv->vbus_supply, false);
+ if (ret && ret != -ENOSYS) {
+ dev_err(dev, "Error disabling vbus supply\n");
+ return ret;
}
return 0;
diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c
index 66b3e96..f9df59d 100644
--- a/drivers/usb/host/dwc3-of-simple.c
+++ b/drivers/usb/host/dwc3-of-simple.c
@@ -2,7 +2,7 @@
/*
* dwc3-of-simple.c - OF glue layer for simple integrations
*
- * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (c) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Author: Felipe Balbi <balbi@ti.com>
*
diff --git a/drivers/usb/host/dwc3-sti-glue.c b/drivers/usb/host/dwc3-sti-glue.c
index 239b671..4a3ab61 100644
--- a/drivers/usb/host/dwc3-sti-glue.c
+++ b/drivers/usb/host/dwc3-sti-glue.c
@@ -17,6 +17,7 @@
#include <reset-uclass.h>
#include <syscon.h>
#include <usb.h>
+#include <linux/printk.h>
#include <linux/usb/dwc3.h>
#include <linux/usb/otg.h>
diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c
index a765a30..936e304 100644
--- a/drivers/usb/host/ehci-generic.c
+++ b/drivers/usb/host/ehci-generic.c
@@ -39,14 +39,10 @@
if (ret && ret != -ENOENT)
return ret;
- if (priv->vbus_supply) {
- ret = regulator_set_enable(priv->vbus_supply, true);
- if (ret) {
- dev_err(dev, "Error enabling VBUS supply (ret=%d)\n", ret);
- return ret;
- }
- } else {
- dev_dbg(dev, "No vbus supply\n");
+ ret = regulator_set_enable_if_allowed(priv->vbus_supply, true);
+ if (ret && ret != -ENOSYS) {
+ dev_err(dev, "Error enabling VBUS supply (ret=%d)\n", ret);
+ return ret;
}
return 0;
@@ -54,10 +50,13 @@
static int ehci_disable_vbus_supply(struct generic_ehci *priv)
{
- if (priv->vbus_supply)
- return regulator_set_enable(priv->vbus_supply, false);
- else
- return 0;
+ int ret;
+
+ ret = regulator_set_enable_if_allowed(priv->vbus_supply, false);
+ if (ret && ret != -ENOSYS)
+ return ret;
+
+ return 0;
}
static int ehci_usb_probe(struct udevice *dev)
diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c
index 147b2fa..ddf7cc2 100644
--- a/drivers/usb/host/ehci-mxs.c
+++ b/drivers/usb/host/ehci-mxs.c
@@ -136,11 +136,12 @@
struct usb_plat *plat = dev_get_plat(dev);
struct ehci_mxs_port *port = &priv->port;
u32 phandle, phy_reg, clk_reg, clk_id;
+ ofnode np = dev_ofnode(dev);
ofnode phy_node, clk_node;
const char *mode;
int ret;
- mode = ofnode_read_string(dev->node_, "dr_mode");
+ mode = ofnode_read_string(np, "dr_mode");
if (mode) {
if (strcmp(mode, "peripheral") == 0)
plat->init_type = USB_INIT_DEVICE;
@@ -151,12 +152,12 @@
}
/* Read base address of the USB IP block */
- ret = ofnode_read_u32(dev->node_, "reg", &port->usb_regs);
+ ret = ofnode_read_u32(np, "reg", &port->usb_regs);
if (ret)
return ret;
/* Read base address of the USB PHY IP block */
- ret = ofnode_read_u32(dev->node_, "fsl,usbphy", &phandle);
+ ret = ofnode_read_u32(np, "fsl,usbphy", &phandle);
if (ret)
return ret;
@@ -235,9 +236,9 @@
debug("%s: No vbus supply\n", dev->name);
if (!ret && priv->vbus_supply) {
- ret = regulator_set_enable(priv->vbus_supply,
- (type == USB_INIT_DEVICE) ?
- false : true);
+ ret = regulator_set_enable_if_allowed(priv->vbus_supply,
+ (type == USB_INIT_DEVICE) ?
+ false : true);
if (ret) {
puts("Error enabling VBUS supply\n");
return ret;
@@ -264,7 +265,7 @@
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (priv->vbus_supply) {
- ret = regulator_set_enable(priv->vbus_supply, false);
+ ret = regulator_set_enable_if_allowed(priv->vbus_supply, false);
if (ret) {
puts("Error disabling VBUS supply\n");
return ret;
diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c
index 2d8d38c..ceed191 100644
--- a/drivers/usb/host/ohci-generic.c
+++ b/drivers/usb/host/ohci-generic.c
@@ -16,75 +16,41 @@
struct generic_ohci {
ohci_t ohci;
- struct clk *clocks; /* clock list */
- struct reset_ctl *resets; /* reset list */
+ struct clk_bulk clocks; /* clock list */
+ struct reset_ctl_bulk resets; /* reset list */
struct phy phy;
- int clock_count; /* number of clock in clock list */
- int reset_count; /* number of reset in reset list */
};
static int ohci_usb_probe(struct udevice *dev)
{
struct ohci_regs *regs = dev_read_addr_ptr(dev);
struct generic_ohci *priv = dev_get_priv(dev);
- int i, err, ret, clock_nb, reset_nb;
+ int err, ret;
- err = 0;
- priv->clock_count = 0;
- clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells",
- 0);
- if (clock_nb > 0) {
- priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
- GFP_KERNEL);
- if (!priv->clocks)
- return -ENOMEM;
-
- for (i = 0; i < clock_nb; i++) {
- err = clk_get_by_index(dev, i, &priv->clocks[i]);
- if (err < 0)
- break;
-
- err = clk_enable(&priv->clocks[i]);
- if (err && err != -ENOSYS) {
- dev_err(dev, "failed to enable clock %d\n", i);
- clk_free(&priv->clocks[i]);
- goto clk_err;
- }
- priv->clock_count++;
- }
- } else if (clock_nb != -ENOENT) {
- dev_err(dev, "failed to get clock phandle(%d)\n", clock_nb);
- return clock_nb;
+ ret = clk_get_bulk(dev, &priv->clocks);
+ if (ret && ret != -ENOENT) {
+ dev_err(dev, "Failed to get clocks (ret=%d)\n", ret);
+ return ret;
}
- priv->reset_count = 0;
- reset_nb = dev_count_phandle_with_args(dev, "resets", "#reset-cells",
- 0);
- if (reset_nb > 0) {
- priv->resets = devm_kcalloc(dev, reset_nb,
- sizeof(struct reset_ctl),
- GFP_KERNEL);
- if (!priv->resets)
- return -ENOMEM;
-
- for (i = 0; i < reset_nb; i++) {
- err = reset_get_by_index(dev, i, &priv->resets[i]);
- if (err < 0)
- break;
-
- err = reset_deassert(&priv->resets[i]);
- if (err) {
- dev_err(dev, "failed to deassert reset %d\n", i);
- reset_free(&priv->resets[i]);
- goto reset_err;
- }
- priv->reset_count++;
- }
- } else if (reset_nb != -ENOENT) {
- dev_err(dev, "failed to get reset phandle(%d)\n", reset_nb);
+ err = clk_enable_bulk(&priv->clocks);
+ if (err) {
+ dev_err(dev, "Failed to enable clocks (err=%d)\n", err);
goto clk_err;
}
+ err = reset_get_bulk(dev, &priv->resets);
+ if (err && err != -ENOENT) {
+ dev_err(dev, "failed to get resets (err=%d)\n", err);
+ goto clk_err;
+ }
+
+ err = reset_deassert_bulk(&priv->resets);
+ if (err) {
+ dev_err(dev, "failed to deassert resets (err=%d)\n", err);
+ goto reset_err;
+ }
+
err = generic_setup_phy(dev, &priv->phy, 0);
if (err)
goto reset_err;
@@ -101,13 +67,13 @@
dev_err(dev, "failed to shutdown usb phy\n");
reset_err:
- ret = reset_release_all(priv->resets, priv->reset_count);
+ ret = reset_release_bulk(&priv->resets);
if (ret)
- dev_err(dev, "failed to assert all resets\n");
+ dev_err(dev, "failed to release resets (ret=%d)\n", ret);
clk_err:
- ret = clk_release_all(priv->clocks, priv->clock_count);
+ ret = clk_release_bulk(&priv->clocks);
if (ret)
- dev_err(dev, "failed to disable all clocks\n");
+ dev_err(dev, "failed to release clocks (ret=%d)\n", ret);
return err;
}
@@ -125,11 +91,11 @@
if (ret)
return ret;
- ret = reset_release_all(priv->resets, priv->reset_count);
+ ret = reset_release_bulk(&priv->resets);
if (ret)
return ret;
- return clk_release_all(priv->clocks, priv->clock_count);
+ return clk_release_bulk(&priv->clocks);
}
static const struct udevice_id ohci_usb_ids[] = {
diff --git a/drivers/usb/host/usb-sandbox.c b/drivers/usb/host/usb-sandbox.c
index d1103dc..3d4f8d6 100644
--- a/drivers/usb/host/usb-sandbox.c
+++ b/drivers/usb/host/usb-sandbox.c
@@ -124,11 +124,12 @@
return ret;
}
-int usb_gadget_handle_interrupts(int index)
+#if CONFIG_IS_ENABLED(DM_USB_GADGET)
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
{
return 0;
}
-
+#else
int usb_gadget_register_driver(struct usb_gadget_driver *driver)
{
struct sandbox_udc *dev = this_controller;
@@ -144,6 +145,7 @@
return 0;
}
+#endif
static int sandbox_alloc_device(struct udevice *dev, struct usb_device *udev)
{
diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c
index 7a03435..a1cd0ad 100644
--- a/drivers/usb/host/usb-uclass.c
+++ b/drivers/usb/host/usb-uclass.c
@@ -9,6 +9,7 @@
#define LOG_CATEGORY UCLASS_USB
#include <common.h>
+#include <bootdev.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
@@ -208,6 +209,13 @@
#ifdef CONFIG_USB_STORAGE
usb_stor_reset();
#endif
+ if (CONFIG_IS_ENABLED(BOOTSTD)) {
+ int ret;
+
+ ret = bootdev_unhunt(UCLASS_USB);
+ if (IS_ENABLED(CONFIG_BOOTSTD_FULL) && ret && ret != -EALREADY)
+ printf("failed to unhunt USB (err=%dE)\n", ret);
+ }
uc_priv->companion_device_count = 0;
usb_started = 0;
@@ -249,6 +257,37 @@
}
}
+static int usb_probe_companion(struct udevice *bus)
+{
+ struct udevice *companion_dev;
+ int ret;
+
+ /*
+ * Enforce optional companion controller is marked as such in order to
+ * 1st scan the primary controller, before the companion controller
+ * (ownership is given to companion when low or full speed devices
+ * have been detected).
+ */
+ ret = uclass_get_device_by_phandle(UCLASS_USB, bus, "companion", &companion_dev);
+ if (!ret) {
+ struct usb_bus_priv *companion_bus_priv;
+
+ debug("%s is the companion of %s\n", companion_dev->name, bus->name);
+ companion_bus_priv = dev_get_uclass_priv(companion_dev);
+ companion_bus_priv->companion = true;
+ } else if (ret && ret != -ENOENT && ret != -ENODEV) {
+ /*
+ * Treat everything else than no companion or disabled
+ * companion as an error. (It may not be enabled on boards
+ * that have a High-Speed HUB to handle FS and LS traffic).
+ */
+ printf("Failed to get companion (ret=%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
int usb_init(void)
{
int controllers_initialized = 0;
@@ -299,6 +338,11 @@
printf("probe failed, error %d\n", ret);
continue;
}
+
+ ret = usb_probe_companion(bus);
+ if (ret)
+ continue;
+
controllers_initialized++;
usb_started = true;
}
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index c8260cb..b60661f 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -202,6 +202,7 @@
bool more_trbs_coming, unsigned int *trb_fields)
{
struct xhci_generic_trb *trb;
+ dma_addr_t addr;
int i;
trb = &ring->enqueue->generic;
@@ -211,9 +212,11 @@
xhci_flush_cache((uintptr_t)trb, sizeof(struct xhci_generic_trb));
+ addr = xhci_trb_virt_to_dma(ring->enq_seg, (union xhci_trb *)trb);
+
inc_enq(ctrl, ring, more_trbs_coming);
- return xhci_trb_virt_to_dma(ring->enq_seg, (union xhci_trb *)trb);
+ return addr;
}
/**
@@ -243,7 +246,8 @@
puts("WARN waiting for error on ep to be cleared\n");
return -EINVAL;
case EP_STATE_HALTED:
- puts("WARN halted endpoint, queueing URB anyway.\n");
+ puts("WARN endpoint is halted\n");
+ return -EINVAL;
case EP_STATE_STOPPED:
case EP_STATE_RUNNING:
debug("EP STATE RUNNING.\n");
@@ -466,7 +470,8 @@
continue;
type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
- if (type == expected)
+ if (type == expected ||
+ (expected == TRB_NONE && type != TRB_PORT_STATUS))
return event;
if (type == TRB_PORT_STATUS)
@@ -492,8 +497,9 @@
if (expected == TRB_TRANSFER)
return NULL;
- printf("XHCI timeout on event type %d... cannot recover.\n", expected);
- BUG();
+ printf("XHCI timeout on event type %d...\n", expected);
+
+ return NULL;
}
/*
@@ -511,6 +517,9 @@
printf("Resetting EP %d...\n", ep_index);
xhci_queue_command(ctrl, 0, udev->slot_id, ep_index, TRB_RESET_EP);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ if (!event)
+ return;
+
field = le32_to_cpu(event->trans_event.flags);
BUG_ON(TRB_TO_SLOT_ID(field) != udev->slot_id);
xhci_acknowledge_event(ctrl);
@@ -519,6 +528,9 @@
(void *)((uintptr_t)ring->enqueue | ring->cycle_state));
xhci_queue_command(ctrl, addr, udev->slot_id, ep_index, TRB_SET_DEQ);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ if (!event)
+ return;
+
BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
!= udev->slot_id || GET_COMP_CODE(le32_to_cpu(
event->event_cmd.status)) != COMP_SUCCESS);
@@ -538,29 +550,49 @@
struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
struct xhci_ring *ring = ctrl->devs[udev->slot_id]->eps[ep_index].ring;
union xhci_trb *event;
+ xhci_comp_code comp;
+ trb_type type;
u64 addr;
u32 field;
xhci_queue_command(ctrl, 0, udev->slot_id, ep_index, TRB_STOP_RING);
- event = xhci_wait_for_event(ctrl, TRB_TRANSFER);
- field = le32_to_cpu(event->trans_event.flags);
- BUG_ON(TRB_TO_SLOT_ID(field) != udev->slot_id);
- BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
- BUG_ON(GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len
- != COMP_STOP)));
- xhci_acknowledge_event(ctrl);
+ event = xhci_wait_for_event(ctrl, TRB_NONE);
+ if (!event)
+ return;
- event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
- BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
- != udev->slot_id || GET_COMP_CODE(le32_to_cpu(
- event->event_cmd.status)) != COMP_SUCCESS);
+ type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
+ if (type == TRB_TRANSFER) {
+ field = le32_to_cpu(event->trans_event.flags);
+ BUG_ON(TRB_TO_SLOT_ID(field) != udev->slot_id);
+ BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
+ BUG_ON(GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len
+ != COMP_STOP)));
+ xhci_acknowledge_event(ctrl);
+
+ event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ if (!event)
+ return;
+ type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
+
+ } else {
+ printf("abort_td: Expected a TRB_TRANSFER TRB first\n");
+ }
+
+ comp = GET_COMP_CODE(le32_to_cpu(event->event_cmd.status));
+ BUG_ON(type != TRB_COMPLETION ||
+ TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
+ != udev->slot_id || (comp != COMP_SUCCESS && comp
+ != COMP_CTX_STATE));
xhci_acknowledge_event(ctrl);
addr = xhci_trb_virt_to_dma(ring->enq_seg,
(void *)((uintptr_t)ring->enqueue | ring->cycle_state));
xhci_queue_command(ctrl, addr, udev->slot_id, ep_index, TRB_SET_DEQ);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ if (!event)
+ return;
+
BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
!= udev->slot_id || GET_COMP_CODE(le32_to_cpu(
event->event_cmd.status)) != COMP_SUCCESS);
@@ -644,6 +676,14 @@
ep_ctx = xhci_get_ep_ctx(ctrl, virt_dev->out_ctx, ep_index);
+ /*
+ * If the endpoint was halted due to a prior error, resume it before
+ * the next transfer. It is the responsibility of the upper layer to
+ * have dealt with whatever caused the error.
+ */
+ if ((le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == EP_STATE_HALTED)
+ reset_ep(udev, ep_index);
+
ring = virt_dev->eps[ep_index].ring;
/*
* How much data is (potentially) left before the 64KB boundary?
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 5cacf07..d13cbff 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -451,6 +451,9 @@
xhci_queue_command(ctrl, in_ctx->dma, udev->slot_id, 0,
ctx_change ? TRB_EVAL_CONTEXT : TRB_CONFIG_EP);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ if (!event)
+ return -ETIMEDOUT;
+
BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
!= udev->slot_id);
@@ -647,6 +650,9 @@
xhci_queue_command(ctrl, virt_dev->in_ctx->dma,
slot_id, 0, TRB_ADDR_DEV);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ if (!event)
+ return -ETIMEDOUT;
+
BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id);
switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
@@ -722,6 +728,9 @@
xhci_queue_command(ctrl, 0, 0, 0, TRB_ENABLE_SLOT);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ if (!event)
+ return -ETIMEDOUT;
+
BUG_ON(GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))
!= COMP_SUCCESS);
diff --git a/drivers/usb/musb-new/mt85xx.c b/drivers/usb/musb-new/mt85xx.c
index 730045c..1e632dc 100644
--- a/drivers/usb/musb-new/mt85xx.c
+++ b/drivers/usb/musb-new/mt85xx.c
@@ -16,6 +16,7 @@
#include <dm/lists.h>
#include <dm/root.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <linux/usb/musb.h>
#include <usb.h>
#include "linux-compat.h"
diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c
index a42d98e..00da554 100644
--- a/drivers/usb/musb-new/musb_core.c
+++ b/drivers/usb/musb-new/musb_core.c
@@ -86,6 +86,7 @@
#include <linux/bitops.h>
#include <linux/bug.h>
#include <linux/errno.h>
+#include <linux/printk.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/musb.h>
diff --git a/drivers/usb/musb-new/musb_debug.h b/drivers/usb/musb-new/musb_debug.h
index c468bda..94375b7 100644
--- a/drivers/usb/musb-new/musb_debug.h
+++ b/drivers/usb/musb-new/musb_debug.h
@@ -10,6 +10,7 @@
#ifndef __MUSB_LINUX_DEBUG_H__
#define __MUSB_LINUX_DEBUG_H__
+#include <linux/printk.h>
#define yprintk(facility, format, args...) \
do { printk(facility "%s %d: " format , \
__func__, __LINE__ , ## args); } while (0)
diff --git a/drivers/usb/musb-new/musb_dsps.c b/drivers/usb/musb-new/musb_dsps.c
index d55a920..a8ff743 100644
--- a/drivers/usb/musb-new/musb_dsps.c
+++ b/drivers/usb/musb-new/musb_dsps.c
@@ -35,6 +35,7 @@
#include <dm.h>
#include <dm/device_compat.h>
#include <asm/omap_musb.h>
+#include <linux/printk.h>
#include "linux-compat.h"
#endif
diff --git a/drivers/usb/musb-new/musb_gadget.c b/drivers/usb/musb-new/musb_gadget.c
index 05bd948..c608396 100644
--- a/drivers/usb/musb-new/musb_gadget.c
+++ b/drivers/usb/musb-new/musb_gadget.c
@@ -26,6 +26,7 @@
#include <dm.h>
#include <dm/device_compat.h>
#include <linux/bug.h>
+#include <linux/printk.h>
#include <linux/usb/ch9.h>
#include "linux-compat.h"
#endif
diff --git a/drivers/usb/musb-new/musb_gadget_ep0.c b/drivers/usb/musb-new/musb_gadget_ep0.c
index 7fdd240..55ce8de 100644
--- a/drivers/usb/musb-new/musb_gadget_ep0.c
+++ b/drivers/usb/musb-new/musb_gadget_ep0.c
@@ -21,6 +21,7 @@
#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
+#include <linux/printk.h>
#include <asm/processor.h>
#include "linux-compat.h"
#endif
diff --git a/drivers/usb/musb-new/musb_uboot.c b/drivers/usb/musb-new/musb_uboot.c
index 62c5e8e..7cea9a2 100644
--- a/drivers/usb/musb-new/musb_uboot.c
+++ b/drivers/usb/musb-new/musb_uboot.c
@@ -376,7 +376,7 @@
#if defined(CONFIG_USB_MUSB_GADGET) && !CONFIG_IS_ENABLED(DM_USB_GADGET)
static struct musb *gadget;
-int usb_gadget_handle_interrupts(int index)
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
{
schedule();
if (!gadget || !gadget->isr)
diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c
index 482dfdc..308eff8 100644
--- a/drivers/usb/musb-new/omap2430.c
+++ b/drivers/usb/musb-new/omap2430.c
@@ -16,6 +16,7 @@
#include <dm/device_compat.h>
#include <dm/lists.h>
#include <linux/err.h>
+#include <linux/printk.h>
#include <linux/usb/otg.h>
#include <asm/global_data.h>
#include <asm/omap_common.h>
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index 485b9dc..91f082f 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -30,6 +30,7 @@
#include <dm/root.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include <linux/usb/musb.h>
#include "linux-compat.h"
#include "musb_core.h"
diff --git a/drivers/usb/musb-new/ti-musb.c b/drivers/usb/musb-new/ti-musb.c
index 3be3f93..ed5e519 100644
--- a/drivers/usb/musb-new/ti-musb.c
+++ b/drivers/usb/musb-new/ti-musb.c
@@ -12,6 +12,7 @@
#include <log.h>
#include <malloc.h>
#include <asm/global_data.h>
+#include <linux/printk.h>
#include <linux/usb/otg.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
diff --git a/drivers/usb/ulpi/omap-ulpi-viewport.c b/drivers/usb/ulpi/omap-ulpi-viewport.c
index 8d71db0..1b01cd4 100644
--- a/drivers/usb/ulpi/omap-ulpi-viewport.c
+++ b/drivers/usb/ulpi/omap-ulpi-viewport.c
@@ -3,7 +3,7 @@
* OMAP ulpi viewport support
* Based on drivers/usb/ulpi/ulpi-viewport.c
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com
* Author: Govindraj R <govindraj.raja@ti.com>
*/
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 69f4809..ab92764 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -66,7 +66,7 @@
hex "Default framebuffer size to use if no drivers request it"
default 0x1000000 if X86
default 0x800000 if !X86 && VIDEO_BOCHS
- default 0 if !X86 && !VIDEO_BOCHS
+ default 0x0 if !X86 && !VIDEO_BOCHS
help
Generally, video drivers request the amount of memory they need for
the frame buffer when they are bound, by setting the size field in
@@ -959,6 +959,14 @@
endif # SPLASH_SCREEN
+config BMP
+ bool "Enable bmp image display"
+ help
+ Enable bmp functions to display bmp image and get bmp info.
+
+ BMP is a simple graphics-image file format designed to store bitmap
+ images. It is primarily used on Windows devices.
+
config VIDEO_BMP_GZIP
bool "Gzip compressed BMP image support"
depends on BMP || SPLASH_SCREEN
@@ -1049,7 +1057,7 @@
hex "Default framebuffer size to use if no drivers request it at SPL"
default 0x1000000 if X86
default 0x800000 if !X86 && VIDEO_BOCHS
- default 0 if !X86 && !VIDEO_BOCHS
+ default 0x0 if !X86 && !VIDEO_BOCHS
help
Generally, video drivers request the amount of memory they need for
the frame buffer when they are bound, by setting the size field in
@@ -1162,6 +1170,14 @@
endif # SPL_SPLASH_SCREEN
+config SPL_BMP
+ bool "Enable bmp image display at SPL"
+ help
+ Enable bmp functions to display bmp image and get bmp info in SPL.
+
+ BMP is a simple graphics-image file format designed to store bitmap
+ images. It is primarily used on Windows devices.
+
config SPL_VIDEO_BMP_GZIP
bool "Gzip compressed BMP image support at SPL"
depends on SPL_SPLASH_SCREEN || SPL_BMP
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index d13af9f..fdc2937 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -25,6 +25,7 @@
obj-$(CONFIG_$(SPL_TPL_)SIMPLE_PANEL) += simple_panel.o
obj-$(CONFIG_VIDEO_LOGO) += u_boot_logo.o
+obj-$(CONFIG_$(SPL_TPL_)BMP) += bmp.o
endif
diff --git a/common/bmp.c b/drivers/video/bmp.c
similarity index 96%
rename from common/bmp.c
rename to drivers/video/bmp.c
index 57764f3..bab6fa7 100644
--- a/common/bmp.c
+++ b/drivers/video/bmp.c
@@ -81,13 +81,6 @@
return bmp;
}
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
-void bmp_reloc(void)
-{
- fixup_cmdtable(cmd_bmp_sub, ARRAY_SIZE(cmd_bmp_sub));
-}
-#endif
-
int bmp_info(ulong addr)
{
struct bmp_image *bmp = (struct bmp_image *)map_sysmem(addr, 0);
diff --git a/drivers/video/console_core.c b/drivers/video/console_core.c
index b5d0e3d..d17764d 100644
--- a/drivers/video/console_core.c
+++ b/drivers/video/console_core.c
@@ -176,6 +176,37 @@
return ret;
}
+int draw_cursor_vertically(void **line, struct video_priv *vid_priv,
+ uint height, bool direction)
+{
+ int step, line_step, pbytes, ret;
+ uint value;
+ void *dst;
+
+ ret = check_bpix_support(vid_priv->bpix);
+ if (ret)
+ return ret;
+
+ pbytes = VNBYTES(vid_priv->bpix);
+ if (direction) {
+ step = -pbytes;
+ line_step = -vid_priv->line_length;
+ } else {
+ step = pbytes;
+ line_step = vid_priv->line_length;
+ }
+
+ value = vid_priv->colour_fg;
+
+ for (int row = 0; row < height; row++) {
+ dst = *line;
+ for (int col = 0; col < VIDCONSOLE_CURSOR_WIDTH; col++)
+ fill_pixel_and_goto_next(&dst, value, pbytes, step);
+ *line += line_step;
+ }
+ return ret;
+}
+
int console_probe(struct udevice *dev)
{
return console_set_font(dev, fonts);
diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c
index 413c7ab..a023129 100644
--- a/drivers/video/console_normal.c
+++ b/drivers/video/console_normal.c
@@ -97,6 +97,34 @@
return VID_TO_POS(fontdata->width);
}
+static int console_set_cursor_visible(struct udevice *dev, bool visible,
+ uint x, uint y, uint index)
+{
+ struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev);
+ struct udevice *vid = dev->parent;
+ struct video_priv *vid_priv = dev_get_uclass_priv(vid);
+ struct console_simple_priv *priv = dev_get_priv(dev);
+ struct video_fontdata *fontdata = priv->fontdata;
+ int pbytes = VNBYTES(vid_priv->bpix);
+ void *start, *line;
+
+ /* for now, this is not used outside expo */
+ if (!IS_ENABLED(CONFIG_EXPO))
+ return -ENOSYS;
+
+ x += index * fontdata->width;
+ start = vid_priv->fb + y * vid_priv->line_length + x * pbytes;
+
+ /* place the cursor 1 pixel before the start of the next char */
+ x -= 1;
+
+ line = start;
+ draw_cursor_vertically(&line, vid_priv, vc_priv->y_charsize,
+ NORMAL_DIRECTION);
+
+ return 0;
+}
+
struct vidconsole_ops console_ops = {
.putc_xy = console_putc_xy,
.move_rows = console_move_rows,
@@ -104,6 +132,7 @@
.get_font_size = console_simple_get_font_size,
.get_font = console_simple_get_font,
.select_font = console_simple_select_font,
+ .set_cursor_visible = console_set_cursor_visible,
};
U_BOOT_DRIVER(vidconsole_normal) = {
diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c
index 0f9bb49..14fb81e 100644
--- a/drivers/video/console_truetype.c
+++ b/drivers/video/console_truetype.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <abuf.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
@@ -175,6 +176,17 @@
int pos_ptr;
};
+/**
+ * struct console_tt_store - Format used for save/restore of entry information
+ *
+ * @priv: Private data
+ * @cur: Current cursor position
+ */
+struct console_tt_store {
+ struct console_tt_priv priv;
+ struct pos_info cur;
+};
+
static int console_truetype_set_row(struct udevice *dev, uint row, int clr)
{
struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent);
@@ -706,8 +718,8 @@
return 0;
}
-int truetype_measure(struct udevice *dev, const char *name, uint size,
- const char *text, struct vidconsole_bbox *bbox)
+static int truetype_measure(struct udevice *dev, const char *name, uint size,
+ const char *text, struct vidconsole_bbox *bbox)
{
struct console_tt_metrics *met;
stbtt_fontinfo *font;
@@ -750,6 +762,177 @@
return 0;
}
+static int truetype_nominal(struct udevice *dev, const char *name, uint size,
+ uint num_chars, struct vidconsole_bbox *bbox)
+{
+ struct console_tt_metrics *met;
+ stbtt_fontinfo *font;
+ int lsb, advance;
+ int width;
+ int ret;
+
+ ret = get_metrics(dev, name, size, &met);
+ if (ret)
+ return log_msg_ret("sel", ret);
+
+ font = &met->font;
+ width = 0;
+
+ /* First get some basic metrics about this character */
+ stbtt_GetCodepointHMetrics(font, 'W', &advance, &lsb);
+
+ width = advance;
+
+ bbox->valid = true;
+ bbox->x0 = 0;
+ bbox->y0 = 0;
+ bbox->x1 = tt_ceil((double)width * num_chars * met->scale);
+ bbox->y1 = met->font_size;
+
+ return 0;
+}
+
+static int truetype_entry_save(struct udevice *dev, struct abuf *buf)
+{
+ struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev);
+ struct console_tt_priv *priv = dev_get_priv(dev);
+ struct console_tt_store store;
+ const uint size = sizeof(store);
+
+ /*
+ * store the whole priv structure as it is simpler that picking out
+ * what we need
+ */
+ if (!abuf_realloc(buf, size))
+ return log_msg_ret("sav", -ENOMEM);
+
+ store.priv = *priv;
+ store.cur.xpos_frac = vc_priv->xcur_frac;
+ store.cur.ypos = vc_priv->ycur;
+ memcpy(abuf_data(buf), &store, size);
+
+ return 0;
+}
+
+static int truetype_entry_restore(struct udevice *dev, struct abuf *buf)
+{
+ struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev);
+ struct console_tt_priv *priv = dev_get_priv(dev);
+ struct console_tt_store store;
+
+ memcpy(&store, abuf_data(buf), sizeof(store));
+
+ vc_priv->xcur_frac = store.cur.xpos_frac;
+ vc_priv->ycur = store.cur.ypos;
+ priv->pos_ptr = store.priv.pos_ptr;
+ memcpy(priv->pos, store.priv.pos,
+ store.priv.pos_ptr * sizeof(struct pos_info));
+
+ return 0;
+}
+
+static int truetype_set_cursor_visible(struct udevice *dev, bool visible,
+ uint x, uint y, uint index)
+{
+ struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev);
+ struct udevice *vid = dev->parent;
+ struct video_priv *vid_priv = dev_get_uclass_priv(vid);
+ struct console_tt_priv *priv = dev_get_priv(dev);
+ struct console_tt_metrics *met = priv->cur_met;
+ uint row, width, height, xoff;
+ void *start, *line;
+ uint out, val;
+ int ret;
+
+ if (!visible)
+ return 0;
+
+ /*
+ * figure out where to place the cursor. This driver ignores the
+ * passed-in values, since an entry_restore() must have been done before
+ * calling this function.
+ */
+ if (index < priv->pos_ptr)
+ x = VID_TO_PIXEL(priv->pos[index].xpos_frac);
+ else
+ x = VID_TO_PIXEL(vc_priv->xcur_frac);
+
+ y = vc_priv->ycur;
+ height = met->font_size;
+ xoff = 0;
+
+ val = vid_priv->colour_bg ? 0 : 255;
+ width = VIDCONSOLE_CURSOR_WIDTH;
+
+ /* Figure out where to write the cursor in the frame buffer */
+ start = vid_priv->fb + y * vid_priv->line_length +
+ x * VNBYTES(vid_priv->bpix);
+ line = start;
+
+ /* draw a vertical bar in the correct position */
+ for (row = 0; row < height; row++) {
+ switch (vid_priv->bpix) {
+ case VIDEO_BPP8:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP8)) {
+ u8 *dst = line + xoff;
+ int i;
+
+ out = val;
+ for (i = 0; i < width; i++) {
+ if (vid_priv->colour_fg)
+ *dst++ |= out;
+ else
+ *dst++ &= out;
+ }
+ }
+ break;
+ case VIDEO_BPP16: {
+ u16 *dst = (u16 *)line + xoff;
+ int i;
+
+ if (IS_ENABLED(CONFIG_VIDEO_BPP16)) {
+ for (i = 0; i < width; i++) {
+ out = val >> 3 |
+ (val >> 2) << 5 |
+ (val >> 3) << 11;
+ if (vid_priv->colour_fg)
+ *dst++ |= out;
+ else
+ *dst++ &= out;
+ }
+ }
+ break;
+ }
+ case VIDEO_BPP32: {
+ u32 *dst = (u32 *)line + xoff;
+ int i;
+
+ if (IS_ENABLED(CONFIG_VIDEO_BPP32)) {
+ for (i = 0; i < width; i++) {
+ int out;
+
+ out = val | val << 8 | val << 16;
+ if (vid_priv->colour_fg)
+ *dst++ |= out;
+ else
+ *dst++ &= out;
+ }
+ }
+ break;
+ }
+ default:
+ return -ENOSYS;
+ }
+
+ line += vid_priv->line_length;
+ }
+ ret = vidconsole_sync_copy(dev, start, line);
+ if (ret)
+ return ret;
+
+ return video_sync(vid, true);
+}
+
const char *console_truetype_get_font_size(struct udevice *dev, uint *sizep)
{
struct console_tt_priv *priv = dev_get_priv(dev);
@@ -802,6 +985,10 @@
.get_font_size = console_truetype_get_font_size,
.select_font = truetype_select_font,
.measure = truetype_measure,
+ .nominal = truetype_nominal,
+ .entry_save = truetype_entry_save,
+ .entry_restore = truetype_entry_restore,
+ .set_cursor_visible = truetype_set_cursor_visible
};
U_BOOT_DRIVER(vidconsole_truetype) = {
diff --git a/drivers/video/coreboot.c b/drivers/video/coreboot.c
index c586475..5b718ae 100644
--- a/drivers/video/coreboot.c
+++ b/drivers/video/coreboot.c
@@ -73,6 +73,17 @@
return ret;
}
+static int coreboot_video_bind(struct udevice *dev)
+{
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+
+ /* Set the maximum supported resolution */
+ uc_plat->size = 4096 * 2160 * 4;
+ log_debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
+
+ return 0;
+}
+
static const struct udevice_id coreboot_video_ids[] = {
{ .compatible = "coreboot-fb" },
{ }
@@ -82,5 +93,6 @@
.name = "coreboot_video",
.id = UCLASS_VIDEO,
.of_match = coreboot_video_ids,
+ .bind = coreboot_video_bind,
.probe = coreboot_video_probe,
};
diff --git a/drivers/video/hitachi_tx18d42vm_lcd.c b/drivers/video/hitachi_tx18d42vm_lcd.c
index 87c4d27..95984fe 100644
--- a/drivers/video/hitachi_tx18d42vm_lcd.c
+++ b/drivers/video/hitachi_tx18d42vm_lcd.c
@@ -10,6 +10,7 @@
#include <linux/delay.h>
#include <asm/gpio.h>
+#include <sunxi_gpio.h>
#include <errno.h>
/*
diff --git a/drivers/video/meson/meson_dw_hdmi.c b/drivers/video/meson/meson_dw_hdmi.c
index e5f2813..5db0190 100644
--- a/drivers/video/meson/meson_dw_hdmi.c
+++ b/drivers/video/meson/meson_dw_hdmi.c
@@ -14,6 +14,7 @@
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
#include <linux/bitops.h>
+#include <linux/printk.h>
#include <power/regulator.h>
#include <clk.h>
#include <linux/delay.h>
diff --git a/drivers/video/meson/meson_vclk.c b/drivers/video/meson/meson_vclk.c
index cd1e690..e718a00 100644
--- a/drivers/video/meson/meson_vclk.c
+++ b/drivers/video/meson/meson_vclk.c
@@ -10,6 +10,7 @@
#include <dm.h>
#include <edid.h>
#include <linux/bitops.h>
+#include <linux/printk.h>
#include "meson_vpu.h"
#include <log.h>
#include <linux/iopoll.h>
diff --git a/drivers/video/pwm_backlight.c b/drivers/video/pwm_backlight.c
index aa0e292..1c747d9 100644
--- a/drivers/video/pwm_backlight.c
+++ b/drivers/video/pwm_backlight.c
@@ -100,8 +100,8 @@
plat = dev_get_uclass_plat(priv->reg);
log_debug("Enable '%s', regulator '%s'/'%s'\n",
dev->name, priv->reg->name, plat->name);
- ret = regulator_set_enable(priv->reg, true);
- if (ret) {
+ ret = regulator_set_enable_if_allowed(priv->reg, true);
+ if (ret && ret != -ENOSYS) {
log_debug("Cannot enable regulator for PWM '%s'\n",
dev->name);
return log_ret(ret);
@@ -181,11 +181,10 @@
}
if (disable) {
dm_gpio_set_value(&priv->enable, 0);
- if (priv->reg) {
- ret = regulator_set_enable(priv->reg, false);
- if (ret)
- return log_ret(ret);
- }
+ ret = regulator_set_enable_if_allowed(priv->reg, false);
+ if (ret && ret != -ENOSYS)
+ return log_ret(ret);
+
priv->enabled = false;
}
diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
index 0852b53..1a5ab78 100644
--- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
+++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
@@ -377,7 +377,7 @@
struct dw_rockchip_dsi_priv *dsi = dev_get_priv(dev);
int ret, i, vco;
- if (dsi->phy.dev) {
+ if (generic_phy_valid(&dsi->phy)) {
ret = generic_phy_configure(&dsi->phy, &dsi->phy_opts);
if (ret) {
dev_err(dsi->dsi_host,
@@ -559,7 +559,7 @@
}
/* for external phy only the mipi_dphy_config is necessary */
- if (dsi->phy.dev) {
+ if (generic_phy_valid(&dsi->phy)) {
phy_mipi_dphy_get_default_config(timings->pixelclock.typ * 10 / 8,
bpp, lanes,
&dsi->phy_opts);
@@ -859,7 +859,7 @@
}
/* Get a ref clock only if not using an external phy. */
- if (priv->phy.dev) {
+ if (generic_phy_valid(&priv->phy)) {
dev_dbg(dev, "setting priv->ref to NULL\n");
priv->ref = NULL;
diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c
index 6a6473e..efb122b 100644
--- a/drivers/video/simple_panel.c
+++ b/drivers/video/simple_panel.c
@@ -114,11 +114,11 @@
const u32 dsi_data = dev_get_driver_data(dev);
int ret;
- if (CONFIG_IS_ENABLED(DM_REGULATOR) && priv->reg) {
- debug("%s: Enable regulator '%s'\n", __func__, priv->reg->name);
- ret = regulator_set_enable(priv->reg, true);
- if (ret)
- return ret;
+ ret = regulator_set_enable_if_allowed(priv->reg, true);
+ if (ret && ret != -ENOSYS) {
+ debug("%s: failed to enable regulator '%s' %d\n",
+ __func__, priv->reg->name, ret);
+ return ret;
}
switch (dsi_data) {
diff --git a/drivers/video/ssd2828.c b/drivers/video/ssd2828.c
index 4cdcbe7..948f5e7 100644
--- a/drivers/video/ssd2828.c
+++ b/drivers/video/ssd2828.c
@@ -12,7 +12,6 @@
#include <common.h>
#include <malloc.h>
#include <mipi_display.h>
-#include <asm/arch/gpio.h>
#include <asm/gpio.h>
#include <linux/delay.h>
diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c
index a7420fb..a18c1e0 100644
--- a/drivers/video/stm32/stm32_dsi.c
+++ b/drivers/video/stm32/stm32_dsi.c
@@ -26,6 +26,7 @@
#include <dm/lists.h>
#include <linux/bitops.h>
#include <linux/iopoll.h>
+#include <linux/printk.h>
#include <power/regulator.h>
#define HWVER_130 0x31333000 /* IP version 1.30 */
diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index f48badc..6fd90e3 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -20,6 +20,7 @@
#include <dm/device-internal.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
+#include <linux/printk.h>
struct stm32_ltdc_priv {
void __iomem *regs;
diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c
index 9110a48..8da44a1 100644
--- a/drivers/video/sunxi/sunxi_display.c
+++ b/drivers/video/sunxi/sunxi_display.c
@@ -31,6 +31,7 @@
#include <malloc.h>
#include <video.h>
#include <dm/uclass-internal.h>
+#include <sunxi_gpio.h>
#include "../videomodes.h"
#include "../anx9804.h"
#include "../hitachi_tx18d42vm_lcd.h"
diff --git a/drivers/video/sunxi/sunxi_lcd.c b/drivers/video/sunxi/sunxi_lcd.c
index 8b9c3b2..7a01cc3 100644
--- a/drivers/video/sunxi/sunxi_lcd.c
+++ b/drivers/video/sunxi/sunxi_lcd.c
@@ -17,6 +17,7 @@
#include <asm/arch/lcdc.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
+#include <sunxi_gpio.h>
struct sunxi_lcd_priv {
struct display_timing timing;
diff --git a/drivers/video/tegra124/sor.c b/drivers/video/tegra124/sor.c
index f291db3..2586851 100644
--- a/drivers/video/tegra124/sor.c
+++ b/drivers/video/tegra124/sor.c
@@ -15,6 +15,7 @@
#include <asm/arch/clock.h>
#include <asm/arch-tegra/dc.h>
#include <linux/delay.h>
+#include <linux/printk.h>
#include "displayport.h"
#include "sor.h"
#include <linux/err.h>
diff --git a/drivers/video/tegra20/tegra-dsi.c b/drivers/video/tegra20/tegra-dsi.c
index 8c3404e..b4cf4fa 100644
--- a/drivers/video/tegra20/tegra-dsi.c
+++ b/drivers/video/tegra20/tegra-dsi.c
@@ -831,11 +831,9 @@
tegra_dsi_get_format(device->format, &priv->format);
- if (priv->avdd) {
- ret = regulator_set_enable(priv->avdd, true);
- if (ret)
- return ret;
- }
+ ret = regulator_set_enable_if_allowed(priv->avdd, true);
+ if (ret && ret != -ENOSYS)
+ return ret;
tegra_dsi_init_clocks(dev);
diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c
index b5b3b66..22d55df 100644
--- a/drivers/video/vidconsole-uclass.c
+++ b/drivers/video/vidconsole-uclass.c
@@ -10,6 +10,7 @@
#define LOG_CATEGORY UCLASS_VIDEO_CONSOLE
#include <common.h>
+#include <abuf.h>
#include <command.h>
#include <console.h>
#include <log.h>
@@ -47,7 +48,7 @@
return ops->set_row(dev, row, clr);
}
-static int vidconsole_entry_start(struct udevice *dev)
+int vidconsole_entry_start(struct udevice *dev)
{
struct vidconsole_ops *ops = vidconsole_get_ops(dev);
@@ -618,6 +619,74 @@
return 0;
}
+int vidconsole_nominal(struct udevice *dev, const char *name, uint size,
+ uint num_chars, struct vidconsole_bbox *bbox)
+{
+ struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
+ struct vidconsole_ops *ops = vidconsole_get_ops(dev);
+ int ret;
+
+ if (ops->measure) {
+ ret = ops->nominal(dev, name, size, num_chars, bbox);
+ if (ret != -ENOSYS)
+ return ret;
+ }
+
+ bbox->valid = true;
+ bbox->x0 = 0;
+ bbox->y0 = 0;
+ bbox->x1 = priv->x_charsize * num_chars;
+ bbox->y1 = priv->y_charsize;
+
+ return 0;
+}
+
+int vidconsole_entry_save(struct udevice *dev, struct abuf *buf)
+{
+ struct vidconsole_ops *ops = vidconsole_get_ops(dev);
+ int ret;
+
+ if (ops->measure) {
+ ret = ops->entry_save(dev, buf);
+ if (ret != -ENOSYS)
+ return ret;
+ }
+
+ /* no data so make sure the buffer is empty */
+ abuf_realloc(buf, 0);
+
+ return 0;
+}
+
+int vidconsole_entry_restore(struct udevice *dev, struct abuf *buf)
+{
+ struct vidconsole_ops *ops = vidconsole_get_ops(dev);
+ int ret;
+
+ if (ops->measure) {
+ ret = ops->entry_restore(dev, buf);
+ if (ret != -ENOSYS)
+ return ret;
+ }
+
+ return 0;
+}
+
+int vidconsole_set_cursor_visible(struct udevice *dev, bool visible,
+ uint x, uint y, uint index)
+{
+ struct vidconsole_ops *ops = vidconsole_get_ops(dev);
+ int ret;
+
+ if (ops->set_cursor_visible) {
+ ret = ops->set_cursor_visible(dev, visible, x, y, index);
+ if (ret != -ENOSYS)
+ return ret;
+ }
+
+ return 0;
+}
+
void vidconsole_push_colour(struct udevice *dev, enum colour_idx fg,
enum colour_idx bg, struct vidconsole_colour *old)
{
diff --git a/drivers/video/vidconsole_internal.h b/drivers/video/vidconsole_internal.h
index c41edd4..0ec581b 100644
--- a/drivers/video/vidconsole_internal.h
+++ b/drivers/video/vidconsole_internal.h
@@ -93,6 +93,30 @@
struct video_fontdata *fontdata, bool direction);
/**
+ * draw_cursor_vertically() - Draw a simple vertical cursor
+ *
+ * @line: pointer to framebuffer buffer: upper left cursor corner
+ * @vid_priv: driver private data
+ * @height: height of the cursor in pixels
+ * @param direction controls cursor orientation. Can be normal or flipped.
+ * When normal: When flipped:
+ *|-----------------------------------------------|
+ *| * | line stepping |
+ *| ^ * * * * * | | |
+ *| | * * | v * * |
+ *| | | * * * * * |
+ *| line stepping | * |
+ *| | |
+ *| stepping -> | <<- stepping |
+ *|---!!we're starting from upper left char corner|
+ *|-----------------------------------------------|
+ *
+ * Return: 0, if success, or else error code.
+ */
+int draw_cursor_vertically(void **line, struct video_priv *vid_priv,
+ uint height, bool direction);
+
+/**
* console probe function.
*
* @param dev a pointer to device.
diff --git a/drivers/virtio/virtio_rng.c b/drivers/virtio/virtio_rng.c
index b85545c..786359a 100644
--- a/drivers/virtio/virtio_rng.c
+++ b/drivers/virtio/virtio_rng.c
@@ -20,7 +20,7 @@
static int virtio_rng_read(struct udevice *dev, void *data, size_t len)
{
int ret;
- unsigned int rsize;
+ unsigned int rsize = 1;
unsigned char buf[BUFFER_SIZE] __aligned(4);
unsigned char *ptr = data;
struct virtio_sg sg;
@@ -29,7 +29,12 @@
while (len) {
sg.addr = buf;
- sg.length = min(len, sizeof(buf));
+ /*
+ * Work around implementations which always return 8 bytes
+ * less than requested, down to 0 bytes, which would
+ * cause an endless loop otherwise.
+ */
+ sg.length = min(rsize ? len : len + 8, sizeof(buf));
sgs[0] = &sg;
ret = virtqueue_add(priv->rng_vq, sgs, 0, 1);
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 07fc494..5697261 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -344,6 +344,13 @@
Enable the STM32 watchdog (IWDG) driver. Enable support to
configure STM32's on-SoC watchdog.
+config WDT_STARFIVE
+ bool "StarFive watchdog timer support"
+ depends on WDT
+ imply WATCHDOG
+ help
+ Enable support for the watchdog timer of StarFive JH7110 SoC.
+
config WDT_SUNXI
bool "Allwinner sunxi watchdog timer support"
depends on WDT && ARCH_SUNXI
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index eef786f..5520d3d 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -44,6 +44,7 @@
obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o
obj-$(CONFIG_WDT_SL28CPLD) += sl28cpld-wdt.o
obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
+obj-$(CONFIG_WDT_STARFIVE) += starfive_wdt.o
obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o
obj-$(CONFIG_WDT_SUNXI) += sunxi_wdt.o
obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o
diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c
index e56aa0e..57b6121 100644
--- a/drivers/watchdog/npcm_wdt.c
+++ b/drivers/watchdog/npcm_wdt.c
@@ -69,15 +69,21 @@
static int npcm_wdt_reset(struct udevice *dev)
{
struct npcm_wdt_priv *priv = dev_get_priv(dev);
+ u32 val;
- writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, priv->regs);
+ val = readl(priv->regs);
+ writel(val | NPCM_WTR, priv->regs);
return 0;
}
static int npcm_wdt_expire_now(struct udevice *dev, ulong flags)
{
- return npcm_wdt_reset(dev);
+ struct npcm_wdt_priv *priv = dev_get_priv(dev);
+
+ writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, priv->regs);
+
+ return 0;
}
static int npcm_wdt_of_to_plat(struct udevice *dev)
diff --git a/drivers/watchdog/s5p_wdt.c b/drivers/watchdog/s5p_wdt.c
index 5ad7d26..80524a0 100644
--- a/drivers/watchdog/s5p_wdt.c
+++ b/drivers/watchdog/s5p_wdt.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <asm/io.h>
+#include <asm/arch/cpu.h>
#include <asm/arch/watchdog.h>
#define PRESCALER_VAL 255
diff --git a/drivers/watchdog/starfive_wdt.c b/drivers/watchdog/starfive_wdt.c
new file mode 100644
index 0000000..ee9ec4c
--- /dev/null
+++ b/drivers/watchdog/starfive_wdt.c
@@ -0,0 +1,329 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Starfive Watchdog driver
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <reset.h>
+#include <wdt.h>
+#include <linux/iopoll.h>
+
+/* JH7110 Watchdog register define */
+#define STARFIVE_WDT_JH7110_LOAD 0x000
+#define STARFIVE_WDT_JH7110_VALUE 0x004
+#define STARFIVE_WDT_JH7110_CONTROL 0x008 /*
+ * [0]: reset enable;
+ * [1]: interrupt enable && watchdog enable
+ * [31:2]: reserved.
+ */
+#define STARFIVE_WDT_JH7110_INTCLR 0x00c /* clear intterupt and reload the counter */
+#define STARFIVE_WDT_JH7110_IMS 0x014
+#define STARFIVE_WDT_JH7110_LOCK 0xc00 /* write 0x1ACCE551 to unlock */
+
+/* WDOGCONTROL */
+#define STARFIVE_WDT_ENABLE 0x1
+#define STARFIVE_WDT_EN_SHIFT 0
+#define STARFIVE_WDT_RESET_EN 0x1
+#define STARFIVE_WDT_JH7110_RST_EN_SHIFT 1
+
+/* WDOGLOCK */
+#define STARFIVE_WDT_JH7110_UNLOCK_KEY 0x1acce551
+
+/* WDOGINTCLR */
+#define STARFIVE_WDT_INTCLR 0x1
+#define STARFIVE_WDT_JH7100_INTCLR_AVA_SHIFT 1 /* Watchdog can clear interrupt when 0 */
+
+#define STARFIVE_WDT_MAXCNT 0xffffffff
+#define STARFIVE_WDT_DEFAULT_TIME (15)
+#define STARFIVE_WDT_DELAY_US 0
+#define STARFIVE_WDT_TIMEOUT_US 10000
+
+/* module parameter */
+#define STARFIVE_WDT_EARLY_ENA 0
+
+struct starfive_wdt_variant {
+ unsigned int control; /* Watchdog Control Resgister for reset enable */
+ unsigned int load; /* Watchdog Load register */
+ unsigned int reload; /* Watchdog Reload Control register */
+ unsigned int enable; /* Watchdog Enable Register */
+ unsigned int value; /* Watchdog Counter Value Register */
+ unsigned int int_clr; /* Watchdog Interrupt Clear Register */
+ unsigned int unlock; /* Watchdog Lock Register */
+ unsigned int int_status; /* Watchdog Interrupt Status Register */
+
+ u32 unlock_key;
+ char enrst_shift;
+ char en_shift;
+ bool intclr_check; /* whether need to check it before clearing interrupt */
+ char intclr_ava_shift;
+ bool double_timeout; /* The watchdog need twice timeout to reboot */
+};
+
+struct starfive_wdt_priv {
+ void __iomem *base;
+ struct clk *core_clk;
+ struct clk *apb_clk;
+ struct reset_ctl_bulk *rst;
+ const struct starfive_wdt_variant *variant;
+ unsigned long freq;
+ u32 count; /* count of timeout */
+ u32 reload; /* restore the count */
+};
+
+/* Register layout and configuration for the JH7110 */
+static const struct starfive_wdt_variant starfive_wdt_jh7110_variant = {
+ .control = STARFIVE_WDT_JH7110_CONTROL,
+ .load = STARFIVE_WDT_JH7110_LOAD,
+ .enable = STARFIVE_WDT_JH7110_CONTROL,
+ .value = STARFIVE_WDT_JH7110_VALUE,
+ .int_clr = STARFIVE_WDT_JH7110_INTCLR,
+ .unlock = STARFIVE_WDT_JH7110_LOCK,
+ .unlock_key = STARFIVE_WDT_JH7110_UNLOCK_KEY,
+ .int_status = STARFIVE_WDT_JH7110_IMS,
+ .enrst_shift = STARFIVE_WDT_JH7110_RST_EN_SHIFT,
+ .en_shift = STARFIVE_WDT_EN_SHIFT,
+ .intclr_check = false,
+ .double_timeout = true,
+};
+
+static int starfive_wdt_enable_clock(struct starfive_wdt_priv *wdt)
+{
+ int ret;
+
+ ret = clk_enable(wdt->apb_clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(wdt->core_clk);
+ if (ret) {
+ clk_disable(wdt->apb_clk);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void starfive_wdt_disable_clock(struct starfive_wdt_priv *wdt)
+{
+ clk_disable(wdt->core_clk);
+ clk_disable(wdt->apb_clk);
+}
+
+/* Write unlock-key to unlock. Write other value to lock. */
+static void starfive_wdt_unlock(struct starfive_wdt_priv *wdt)
+{
+ writel(wdt->variant->unlock_key, wdt->base + wdt->variant->unlock);
+}
+
+static void starfive_wdt_lock(struct starfive_wdt_priv *wdt)
+{
+ writel(~wdt->variant->unlock_key, wdt->base + wdt->variant->unlock);
+}
+
+/* enable watchdog interrupt to reset/reboot */
+static void starfive_wdt_enable_reset(struct starfive_wdt_priv *wdt)
+{
+ u32 val;
+
+ val = readl(wdt->base + wdt->variant->control);
+ val |= STARFIVE_WDT_RESET_EN << wdt->variant->enrst_shift;
+ writel(val, wdt->base + wdt->variant->control);
+}
+
+/* waiting interrupt can be free to clear */
+static int starfive_wdt_wait_int_free(struct starfive_wdt_priv *wdt)
+{
+ u32 value;
+
+ return readl_poll_timeout(wdt->base + wdt->variant->int_clr, value,
+ !(value & BIT(wdt->variant->intclr_ava_shift)),
+ STARFIVE_WDT_TIMEOUT_US);
+}
+
+/* clear interrupt signal before initialization or reload */
+static int starfive_wdt_int_clr(struct starfive_wdt_priv *wdt)
+{
+ int ret;
+
+ if (wdt->variant->intclr_check) {
+ ret = starfive_wdt_wait_int_free(wdt);
+ if (ret)
+ return ret;
+ }
+ writel(STARFIVE_WDT_INTCLR, wdt->base + wdt->variant->int_clr);
+
+ return 0;
+}
+
+static inline void starfive_wdt_set_count(struct starfive_wdt_priv *wdt,
+ u32 val)
+{
+ writel(val, wdt->base + wdt->variant->load);
+}
+
+/* enable watchdog */
+static inline void starfive_wdt_enable(struct starfive_wdt_priv *wdt)
+{
+ u32 val;
+
+ val = readl(wdt->base + wdt->variant->enable);
+ val |= STARFIVE_WDT_ENABLE << wdt->variant->en_shift;
+ writel(val, wdt->base + wdt->variant->enable);
+}
+
+/* disable watchdog */
+static inline void starfive_wdt_disable(struct starfive_wdt_priv *wdt)
+{
+ u32 val;
+
+ val = readl(wdt->base + wdt->variant->enable);
+ val &= ~(STARFIVE_WDT_ENABLE << wdt->variant->en_shift);
+ writel(val, wdt->base + wdt->variant->enable);
+}
+
+static inline void starfive_wdt_set_reload_count(struct starfive_wdt_priv *wdt,
+ u32 count)
+{
+ starfive_wdt_set_count(wdt, count);
+
+ /* 7100 need set any value to reload register and could reload value to counter */
+ if (wdt->variant->reload)
+ writel(0x1, wdt->base + wdt->variant->reload);
+}
+
+static int starfive_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+ int ret;
+ struct starfive_wdt_priv *wdt = dev_get_priv(dev);
+
+ starfive_wdt_unlock(wdt);
+ /* disable watchdog, to be safe */
+ starfive_wdt_disable(wdt);
+
+ starfive_wdt_enable_reset(wdt);
+ ret = starfive_wdt_int_clr(wdt);
+ if (ret)
+ goto exit;
+
+ wdt->count = (timeout_ms / 1000) * wdt->freq;
+ if (wdt->variant->double_timeout)
+ wdt->count /= 2;
+
+ starfive_wdt_set_count(wdt, wdt->count);
+ starfive_wdt_enable(wdt);
+
+exit:
+ starfive_wdt_lock(wdt);
+ return ret;
+}
+
+static int starfive_wdt_stop(struct udevice *dev)
+{
+ struct starfive_wdt_priv *wdt = dev_get_priv(dev);
+
+ starfive_wdt_unlock(wdt);
+ starfive_wdt_disable(wdt);
+ starfive_wdt_lock(wdt);
+
+ return 0;
+}
+
+static int starfive_wdt_reset(struct udevice *dev)
+{
+ int ret;
+ struct starfive_wdt_priv *wdt = dev_get_priv(dev);
+
+ starfive_wdt_unlock(wdt);
+ ret = starfive_wdt_int_clr(wdt);
+ if (ret)
+ goto exit;
+
+ starfive_wdt_set_reload_count(wdt, wdt->count);
+
+exit:
+ starfive_wdt_lock(wdt);
+
+ return ret;
+}
+
+static const struct wdt_ops starfive_wdt_ops = {
+ .start = starfive_wdt_start,
+ .stop = starfive_wdt_stop,
+ .reset = starfive_wdt_reset,
+};
+
+static int starfive_wdt_probe(struct udevice *dev)
+{
+ struct starfive_wdt_priv *wdt = dev_get_priv(dev);
+ int ret;
+
+ ret = starfive_wdt_enable_clock(wdt);
+ if (ret)
+ return ret;
+
+ ret = reset_deassert_bulk(wdt->rst);
+ if (ret)
+ goto err_reset;
+
+ wdt->variant = (const struct starfive_wdt_variant *)dev_get_driver_data(dev);
+
+ wdt->freq = clk_get_rate(wdt->core_clk);
+ if (!wdt->freq) {
+ ret = -EINVAL;
+ goto err_get_freq;
+ }
+
+ return 0;
+
+err_get_freq:
+ reset_assert_bulk(wdt->rst);
+err_reset:
+ starfive_wdt_disable_clock(wdt);
+
+ return ret;
+}
+
+static int starfive_wdt_of_to_plat(struct udevice *dev)
+{
+ struct starfive_wdt_priv *wdt = dev_get_priv(dev);
+
+ wdt->base = (void *)dev_read_addr(dev);
+ if (!wdt->base)
+ return -ENODEV;
+
+ wdt->apb_clk = devm_clk_get(dev, "apb");
+ if (IS_ERR(wdt->apb_clk))
+ return -ENODEV;
+
+ wdt->core_clk = devm_clk_get(dev, "core");
+ if (IS_ERR(wdt->core_clk))
+ return -ENODEV;
+
+ wdt->rst = devm_reset_bulk_get(dev);
+ if (IS_ERR(wdt->rst))
+ return -ENODEV;
+
+ return 0;
+}
+
+static const struct udevice_id starfive_wdt_ids[] = {
+ {
+ .compatible = "starfive,jh7110-wdt",
+ .data = (ulong)&starfive_wdt_jh7110_variant
+ }, {
+ /* sentinel */
+ }
+};
+
+U_BOOT_DRIVER(starfive_wdt) = {
+ .name = "starfive_wdt",
+ .id = UCLASS_WDT,
+ .of_match = starfive_wdt_ids,
+ .priv_auto = sizeof(struct starfive_wdt_priv),
+ .probe = starfive_wdt_probe,
+ .of_to_plat = starfive_wdt_of_to_plat,
+ .ops = &starfive_wdt_ops,
+};
diff --git a/drivers/watchdog/stm32mp_wdt.c b/drivers/watchdog/stm32mp_wdt.c
index 4be616c..7ebcd25 100644
--- a/drivers/watchdog/stm32mp_wdt.c
+++ b/drivers/watchdog/stm32mp_wdt.c
@@ -15,6 +15,7 @@
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/iopoll.h>
+#include <linux/printk.h>
/* IWDG registers */
#define IWDG_KR 0x00 /* Key register */
diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c
index 509896a..417e8d7 100644
--- a/drivers/watchdog/wdt-uclass.c
+++ b/drivers/watchdog/wdt-uclass.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <cyclic.h>
+#include <div64.h>
#include <dm.h>
#include <errno.h>
#include <hang.h>
@@ -141,7 +142,7 @@
printf("WDT: Started %s with%s servicing %s (%ds timeout)\n",
dev->name, IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out",
- str, priv->timeout);
+ str, (u32)lldiv(timeout_ms, 1000));
}
return ret;
@@ -236,28 +237,6 @@
}
#endif
-static int wdt_post_bind(struct udevice *dev)
-{
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- struct wdt_ops *ops = (struct wdt_ops *)device_get_ops(dev);
- static int reloc_done;
-
- if (!reloc_done) {
- if (ops->start)
- ops->start += gd->reloc_off;
- if (ops->stop)
- ops->stop += gd->reloc_off;
- if (ops->reset)
- ops->reset += gd->reloc_off;
- if (ops->expire_now)
- ops->expire_now += gd->reloc_off;
-
- reloc_done++;
- }
-#endif
- return 0;
-}
-
static int wdt_pre_probe(struct udevice *dev)
{
u32 timeout = WATCHDOG_TIMEOUT_SECS;
@@ -295,7 +274,6 @@
.id = UCLASS_WDT,
.name = "watchdog",
.flags = DM_UC_FLAG_SEQ_ALIAS,
- .post_bind = wdt_post_bind,
.pre_probe = wdt_pre_probe,
.per_device_auto = sizeof(struct wdt_priv),
};
diff --git a/dts/Kconfig b/dts/Kconfig
index 9152f58..00c0aef 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -410,12 +410,14 @@
declarations for each node. See of-plat.txt for more information.
config SPL_OF_REAL
- bool
+ bool "Support a real devicetree in SPL" if SANDBOX
+ depends on SPL_OF_CONTROL
+ select SPL_OF_LIBFDT
help
Indicates that a real devicetree is available which can be accessed
at runtime. This means that dev_read_...() functions can be used to
- read data from the devicetree for each device. This is true if
- SPL_OF_CONTROL is enabled and not SPL_OF_PLATDATA
+ read data from the devicetree for each device. You do not need to
+ enable this option if you have enabled SPL_OF_PLATDATA.
if SPL_OF_PLATDATA
diff --git a/env/Kconfig b/env/Kconfig
index 13e3210..f5f0969 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -571,23 +571,33 @@
default 0xE0000 if ARCH_ZYNQ
default 0x1E00000 if ARCH_ZYNQMP
default 0x7F40000 if ARCH_VERSAL || ARCH_VERSAL_NET
- default 0 if ARC
+ default 0x0 if ARC
default 0x140000 if ARCH_AT91
default 0x260000 if ARCH_OMAP2PLUS
default 0x1080000 if MICROBLAZE && ENV_IS_IN_SPI_FLASH
help
- Offset from the start of the device (or partition)
+ Offset from the start of the device (or partition).
+
+ This offset may be interpreted differently depending on the chosen
+ ENV_IS_IN_* options. For example, for ENV_IS_IN_MMC=y, this offset may
+ be negative to indicate an offset backwards from the end of the
+ partition. See the relevant help messages for more details.
config ENV_OFFSET_REDUND
hex "Redundant environment offset"
depends on (ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \
ENV_IS_IN_SPI_FLASH) && SYS_REDUNDAND_ENVIRONMENT
default 0x10C0000 if MICROBLAZE
- default 0
+ default 0x0
help
Offset from the start of the device (or partition) of the redundant
environment location.
+ This offset may be interpreted differently depending on the chosen
+ ENV_IS_IN_* options. For example, for ENV_IS_IN_MMC=y, this offset may
+ be negative to indicate an offset backwards from the end of the
+ partition. See the relevant help messages for more details.
+
config ENV_SIZE
hex "Environment Size"
default 0x40000 if ENV_IS_IN_SPI_FLASH && ARCH_ZYNQMP
@@ -645,7 +655,7 @@
config SYS_MMC_ENV_DEV
int "mmc device number"
- depends on ENV_IS_IN_MMC || ENV_IS_IN_FAT || SYS_LS_PPA_FW_IN_MMC || \
+ depends on ENV_IS_IN_MMC || ENV_IS_IN_FAT || \
CMD_MVEBU_BUBT || FMAN_ENET || QE || PHY_CORTINA
default 0
help
diff --git a/env/callback.c b/env/callback.c
index 638a02b..98ddba0 100644
--- a/env/callback.c
+++ b/env/callback.c
@@ -9,10 +9,6 @@
#include <env_internal.h>
#include <asm/global_data.h>
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
/*
* Look up a callback function pointer by name
*/
@@ -71,11 +67,7 @@
if (!ret && strlen(callback_name)) {
clbkp = find_env_callback(callback_name);
if (clbkp != NULL)
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- var_entry->callback = clbkp->callback + gd->reloc_off;
-#else
var_entry->callback = clbkp->callback;
-#endif
}
}
@@ -112,11 +104,7 @@
/* assign the requested callback */
clbkp = find_env_callback(value);
if (clbkp != NULL)
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- ep->callback = clbkp->callback + gd->reloc_off;
-#else
ep->callback = clbkp->callback;
-#endif
}
}
diff --git a/env/common.c b/env/common.c
index 0ecdb24..eb1a913 100644
--- a/env/common.c
+++ b/env/common.c
@@ -15,6 +15,7 @@
#include <log.h>
#include <sort.h>
#include <asm/global_data.h>
+#include <linux/printk.h>
#include <linux/stddef.h>
#include <search.h>
#include <errno.h>
@@ -428,11 +429,6 @@
void env_relocate(void)
{
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- env_reloc();
- env_fix_drivers();
- env_htab.change_ok += gd->reloc_off;
-#endif
if (gd->env_valid == ENV_INVALID) {
#if defined(CONFIG_ENV_IS_NOWHERE) || defined(CONFIG_SPL_BUILD)
/* Environment not changable */
diff --git a/env/env.c b/env/env.c
index 8ef2178..d004af1 100644
--- a/env/env.c
+++ b/env/env.c
@@ -14,29 +14,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
-void env_fix_drivers(void)
-{
- struct env_driver *drv;
- const int n_ents = ll_entry_count(struct env_driver, env_driver);
- struct env_driver *entry;
-
- drv = ll_entry_start(struct env_driver, env_driver);
- for (entry = drv; entry != drv + n_ents; entry++) {
- if (entry->name)
- entry->name += gd->reloc_off;
- if (entry->load)
- entry->load += gd->reloc_off;
- if (entry->save)
- entry->save += gd->reloc_off;
- if (entry->erase)
- entry->erase += gd->reloc_off;
- if (entry->init)
- entry->init += gd->reloc_off;
- }
-}
-#endif
-
static struct env_driver *_env_driver_lookup(enum env_location loc)
{
struct env_driver *drv;
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index 38e285b..4691612 100644
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
@@ -390,7 +390,7 @@
csize);
ret = btrfs_decompress(btrfs_file_extent_compression(leaf, fi),
cbuf, csize, dbuf, dsize);
- if (ret == (u32)-1) {
+ if (ret < 0) {
ret = -EIO;
goto out;
}
@@ -500,7 +500,7 @@
ret = btrfs_decompress(btrfs_file_extent_compression(leaf, fi), cbuf,
csize, dbuf, dsize);
- if (ret == (u32)-1) {
+ if (ret < 0) {
ret = -EIO;
goto out;
}
diff --git a/fs/btrfs/subvolume.c b/fs/btrfs/subvolume.c
index d446e7a..68ca7e4 100644
--- a/fs/btrfs/subvolume.c
+++ b/fs/btrfs/subvolume.c
@@ -199,6 +199,7 @@
ret = PTR_ERR(root);
if (ret == -ENOENT)
goto next;
+ goto out;
}
ret = list_one_subvol(root, result);
if (ret < 0)
diff --git a/fs/cramfs/cramfs.c b/fs/cramfs/cramfs.c
index 6c017ce..abb2de3 100644
--- a/fs/cramfs/cramfs.c
+++ b/fs/cramfs/cramfs.c
@@ -166,8 +166,7 @@
unsigned long ret;
char *link;
if (p && strlen(p)) {
- printf ("unsupported symlink to \
- non-terminal path\n");
+ printf ("unsupported symlink to non-terminal path\n");
return 0;
}
link = cramfs_uncompress_link (begin,
@@ -177,8 +176,7 @@
namelen, namelen, name);
return 0;
} else if (link[0] == '/') {
- printf ("unsupported symlink to \
- absolute path\n");
+ printf ("unsupported symlink to absolute path\n");
free (link);
return 0;
}
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index 9a9c520..f50de7c 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -2373,10 +2373,6 @@
struct ext2_data *data;
int status;
struct ext_filesystem *fs = get_fs();
-
- if (part_length < SUPERBLOCK_SIZE)
- return 0;
-
data = zalloc(SUPERBLOCK_SIZE);
if (!data)
return 0;
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index d1476aa..8ff1fd0 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -110,9 +110,7 @@
info.name[0] = 0;
info.type[0] = 0;
info.bootable = 0;
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- info.uuid[0] = 0;
-#endif
+ disk_partition_clr_uuid(&info);
}
return fat_set_blk_dev(dev_desc, &info);
diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
index a629441..8b5d669 100644
--- a/fs/fat/fat_write.c
+++ b/fs/fat/fat_write.c
@@ -690,8 +690,8 @@
static u8 *tmpbuf_cluster;
unsigned int bytesperclust = mydata->clust_size * mydata->sect_size;
__u32 startsect;
- loff_t wsize;
- int clustcount, i, ret;
+ loff_t clustcount, wsize;
+ int i, ret;
*gotsize = 0;
if (!size)
diff --git a/fs/fs.c b/fs/fs.c
index 2b815b1..4cb4310 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -237,7 +237,7 @@
.mkdir = fs_mkdir_unsupported,
},
#endif
-#ifdef CONFIG_SANDBOX
+#if IS_ENABLED(CONFIG_SANDBOX) && !IS_ENABLED(CONFIG_SPL_BUILD)
{
.fstype = FS_TYPE_SANDBOX,
.name = "sandbox",
@@ -422,22 +422,6 @@
{
struct fstype_info *info;
int part, i;
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
- static int relocated;
-
- if (!relocated) {
- for (i = 0, info = fstypes; i < ARRAY_SIZE(fstypes);
- i++, info++) {
- info->name += gd->reloc_off;
- info->probe += gd->reloc_off;
- info->close += gd->reloc_off;
- info->ls += gd->reloc_off;
- info->read += gd->reloc_off;
- info->write += gd->reloc_off;
- }
- relocated = 1;
- }
-#endif
part = part_get_info_by_dev_and_name_or_num(ifname, dev_part_str, &fs_dev_desc,
&fs_partition, 1);
diff --git a/fs/ubifs/Kconfig b/fs/ubifs/Kconfig
index 949b288..690e77e 100644
--- a/fs/ubifs/Kconfig
+++ b/fs/ubifs/Kconfig
@@ -8,7 +8,6 @@
config UBIFS_SILENCE_DEBUG_DUMP
bool "UBIFS silence debug dumps"
default y if UBIFS_SILENCE_MSG
- default n
help
Make the debug dumps from UBIFS stop printing.
This decreases size of U-Boot binary.
diff --git a/fs/ubifs/debug.c b/fs/ubifs/debug.c
index bede7d0..ff2a571 100644
--- a/fs/ubifs/debug.c
+++ b/fs/ubifs/debug.c
@@ -18,6 +18,7 @@
#include <hexdump.h>
#include <log.h>
#include <dm/devres.h>
+#include <linux/printk.h>
#ifndef __UBOOT__
#include <linux/module.h>
diff --git a/fs/ubifs/debug.h b/fs/ubifs/debug.h
index 0ecc2e0..d8324ae 100644
--- a/fs/ubifs/debug.h
+++ b/fs/ubifs/debug.h
@@ -12,6 +12,7 @@
#define __UBIFS_DEBUG_H__
/* Checking helper functions */
+#include <linux/printk.h>
typedef int (*dbg_leaf_callback)(struct ubifs_info *c,
struct ubifs_zbranch *zbr, void *priv);
typedef int (*dbg_znode_callback)(struct ubifs_info *c,
diff --git a/fs/ubifs/lpt_commit.c b/fs/ubifs/lpt_commit.c
index ba0b19a..2e50c08 100644
--- a/fs/ubifs/lpt_commit.c
+++ b/fs/ubifs/lpt_commit.c
@@ -24,6 +24,7 @@
#include <linux/compat.h>
#include <linux/err.h>
#include <linux/crc16.h>
+#include <linux/printk.h>
#endif
#include "ubifs.h"
diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c
index 034c41a..3e71603 100644
--- a/fs/ubifs/super.c
+++ b/fs/ubifs/super.c
@@ -35,6 +35,7 @@
#include <linux/bitops.h>
#include <linux/bug.h>
#include <linux/log2.h>
+#include <linux/printk.h>
#include <linux/stat.h>
#include <linux/err.h>
#include "ubifs.h"
diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c
index 609bdbf..a509584 100644
--- a/fs/ubifs/ubifs.c
+++ b/fs/ubifs/ubifs.c
@@ -201,12 +201,6 @@
{
ubifs_compressors[compr->compr_type] = compr;
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
- ubifs_compressors[compr->compr_type]->name += gd->reloc_off;
- ubifs_compressors[compr->compr_type]->capi_name += gd->reloc_off;
- ubifs_compressors[compr->compr_type]->decompress += gd->reloc_off;
-#endif
-
if (compr->capi_name) {
compr->cc = crypto_alloc_comp(compr->capi_name, 0, 0);
if (IS_ERR(compr->cc)) {
diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h
index 46dfbd0..67b13c8 100644
--- a/fs/ubifs/ubifs.h
+++ b/fs/ubifs/ubifs.h
@@ -35,6 +35,7 @@
#include <asm-generic/atomic-long.h>
#include <ubi_uboot.h>
#include <ubifs_uboot.h>
+#include <linux/printk.h>
#include <linux/ctype.h>
#include <linux/time.h>
diff --git a/fs/yaffs2/yaffs_uboot_glue.c b/fs/yaffs2/yaffs_uboot_glue.c
index ec8d028..0a92056 100644
--- a/fs/yaffs2/yaffs_uboot_glue.c
+++ b/fs/yaffs2/yaffs_uboot_glue.c
@@ -22,6 +22,7 @@
#include <common.h>
#include <div64.h>
#include <malloc.h>
+#include <linux/printk.h>
#include <config.h>
#include "nand.h"
diff --git a/include/abuf.h b/include/abuf.h
index 9badda6..be98ec7 100644
--- a/include/abuf.h
+++ b/include/abuf.h
@@ -91,6 +91,15 @@
bool abuf_realloc(struct abuf *abuf, size_t new_size);
/**
+ * abuf_realloc_inc() - Increment abuf size by a given amount
+ *
+ * @abuf: abuf to adjust
+ * @inc: Size incrmement to use (the buffer size will be increased by this much)
+ * Return: true if OK, false if out of memory
+ */
+bool abuf_realloc_inc(struct abuf *abuf, size_t inc);
+
+/**
* abuf_uninit_move() - Return the allocated contents and uninit the abuf
*
* This returns the abuf data to the caller, allocating it if necessary, so that
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index 7ed0443..1f85de0 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -883,6 +883,13 @@
*/
int acpi_add_table(struct acpi_ctx *ctx, void *table);
+static inline int acpi_add_fadt(struct acpi_ctx *ctx, struct acpi_fadt *fadt)
+{
+ acpi_add_table(ctx, fadt);
+ acpi_inc(ctx, sizeof(struct acpi_fadt));
+ return 0;
+}
+
/**
* acpi_write_rsdp() - Write out an RSDP indicating where the ACPI tables are
*
diff --git a/include/asm-generic/bitops/builtin-__ffs.h b/include/asm-generic/bitops/builtin-__ffs.h
new file mode 100644
index 0000000..87024da
--- /dev/null
+++ b/include/asm-generic/bitops/builtin-__ffs.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_GENERIC_BITOPS_BUILTIN___FFS_H_
+#define _ASM_GENERIC_BITOPS_BUILTIN___FFS_H_
+
+/**
+ * __ffs - find first bit in word.
+ * @word: The word to search
+ *
+ * Undefined if no bit exists, so code should check against 0 first.
+ */
+static __always_inline unsigned long __ffs(unsigned long word)
+{
+ return __builtin_ctzl(word);
+}
+
+#endif
diff --git a/include/asm-generic/bitops/builtin-__fls.h b/include/asm-generic/bitops/builtin-__fls.h
new file mode 100644
index 0000000..43a5aa9
--- /dev/null
+++ b/include/asm-generic/bitops/builtin-__fls.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_GENERIC_BITOPS_BUILTIN___FLS_H_
+#define _ASM_GENERIC_BITOPS_BUILTIN___FLS_H_
+
+/**
+ * __fls - find last (most-significant) set bit in a long word
+ * @word: the word to search
+ *
+ * Undefined if no set bit exists, so code should check against 0 first.
+ */
+static __always_inline unsigned long __fls(unsigned long word)
+{
+ return (sizeof(word) * 8) - 1 - __builtin_clzl(word);
+}
+
+#endif
diff --git a/include/asm-generic/bitops/builtin-ffs.h b/include/asm-generic/bitops/builtin-ffs.h
new file mode 100644
index 0000000..7b12932
--- /dev/null
+++ b/include/asm-generic/bitops/builtin-ffs.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_GENERIC_BITOPS_BUILTIN_FFS_H_
+#define _ASM_GENERIC_BITOPS_BUILTIN_FFS_H_
+
+/**
+ * ffs - find first bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from ffz (man ffs).
+ */
+#define ffs(x) __builtin_ffs(x)
+
+#endif
diff --git a/include/asm-generic/bitops/builtin-fls.h b/include/asm-generic/bitops/builtin-fls.h
new file mode 100644
index 0000000..c8455cc
--- /dev/null
+++ b/include/asm-generic/bitops/builtin-fls.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_GENERIC_BITOPS_BUILTIN_FLS_H_
+#define _ASM_GENERIC_BITOPS_BUILTIN_FLS_H_
+
+/**
+ * fls - find last (most-significant) bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as ffs.
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ */
+static __always_inline int fls(unsigned int x)
+{
+ return x ? sizeof(x) * 8 - __builtin_clz(x) : 0;
+}
+
+#endif
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 8fc205d..e8c6412 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -307,7 +307,7 @@
#if CONFIG_IS_ENABLED(CMD_BDINFO_EXTRA)
unsigned long malloc_start;
#endif
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
/**
* @malloc_base: base address of early malloc()
*/
@@ -552,6 +552,14 @@
#define gd_set_acpi_start(addr)
#endif
+#ifdef CONFIG_SMBIOS
+#define gd_smbios_start() gd->smbios_start
+#define gd_set_smbios_start(addr) gd->arch.smbios_start = addr
+#else
+#define gd_smbios_start() 0UL
+#define gd_set_smbios_start(addr)
+#endif
+
#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
#define gd_multi_dtb_fit() gd->multi_dtb_fit
#define gd_set_multi_dtb_fit(_dtb) gd->multi_dtb_fit = _dtb
@@ -573,6 +581,19 @@
#define gd_malloc_start() 0
#define gd_set_malloc_start(val)
#endif
+
+#if CONFIG_IS_ENABLED(PCI)
+#define gd_set_pci_ram_top(val) gd->pci_ram_top = val
+#else
+#define gd_set_pci_ram_top(val)
+#endif
+
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#define gd_malloc_ptr() gd->malloc_ptr
+#else
+#define gd_malloc_ptr() 0L
+#endif
+
/**
* enum gd_flags - global data flags
*
@@ -667,6 +688,15 @@
* @GD_FLG_OF_TAG_MIGRATE: Device tree has old u-boot,dm- tags
*/
GD_FLG_OF_TAG_MIGRATE = 0x200000,
+ /**
+ * @GD_FLG_DM_DEAD: Driver model is not accessible. This can be set when
+ * the memory used to holds its tables has been mapped out.
+ */
+ GD_FLG_DM_DEAD = 0x400000,
+ /**
+ * @GD_FLG_BLOBLIST_READY: bloblist is ready for use
+ */
+ GD_FLG_BLOBLIST_READY = 0x800000,
};
#endif /* __ASSEMBLY__ */
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index c4a7fd2..a21c606 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -414,6 +414,7 @@
* @gpio_base: Base GPIO number for this device. For the first active device
* this will be 0; the numbering for others will follow sequentially so that
* @gpio_base for device 1 will equal the number of GPIOs in device 0.
+ * @claimed: Array of bits indicating which GPIOs in the bank are claimed.
* @name: Array of pointers to the name for each GPIO in this bank. The
* value of the pointer will be NULL if the GPIO has not been claimed.
*/
@@ -421,6 +422,7 @@
const char *bank_name;
unsigned gpio_count;
unsigned gpio_base;
+ u32 *claimed;
char **name;
};
diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
index 267f1db..1e1657a 100644
--- a/include/asm-generic/sections.h
+++ b/include/asm-generic/sections.h
@@ -61,8 +61,12 @@
/* Start of U-Boot text region */
extern char __text_start[];
-/* This marks the end of the text region which must be relocated */
-extern char __image_copy_end[];
+/* This marks the text region which must be relocated */
+extern char __image_copy_start[], __image_copy_end[];
+
+extern char __bss_end[];
+extern char __rel_dyn_start[], __rel_dyn_end[];
+extern char _image_binary_end[];
/*
* This is the U-Boot entry point - prior to relocation it should be same
@@ -70,30 +74,4 @@
*/
extern void _start(void);
-/*
- * ARM defines its symbols as char[]. Other arches define them as ulongs.
- */
-#ifdef CONFIG_ARM
-
-extern char __bss_start[];
-extern char __bss_end[];
-extern char __image_copy_start[];
-extern char __image_copy_end[];
-extern char _image_binary_end[];
-extern char __rel_dyn_start[];
-extern char __rel_dyn_end[];
-
-#else /* don't use offsets: */
-
-/* Exports from the Linker Script */
-extern ulong __data_end;
-extern ulong __rel_dyn_start;
-extern ulong __rel_dyn_end;
-extern ulong __bss_end;
-extern ulong _image_binary_end;
-
-extern ulong _TEXT_BASE; /* code start */
-
-#endif
-
#endif /* _ASM_GENERIC_SECTIONS_H_ */
diff --git a/include/axp_pmic.h b/include/axp_pmic.h
index 4ac6486..aabafc8 100644
--- a/include/axp_pmic.h
+++ b/include/axp_pmic.h
@@ -32,6 +32,7 @@
AXP209_ID,
AXP221_ID,
AXP223_ID,
+ AXP313_ID,
AXP803_ID,
AXP806_ID,
AXP809_ID,
diff --git a/include/blk.h b/include/blk.h
index 2c9c798..7c7cf7f 100644
--- a/include/blk.h
+++ b/include/blk.h
@@ -7,6 +7,7 @@
#ifndef BLK_H
#define BLK_H
+#include <bouncebuf.h>
#include <dm/uclass-id.h>
#include <efi.h>
@@ -20,6 +21,8 @@
#define LBAF "%" LBAFlength "x"
#define LBAFU "%" LBAFlength "u"
+#define DEFAULT_BLKSZ 512
+
struct udevice;
static inline bool blk_enabled(void)
@@ -65,6 +68,7 @@
/* device can use 48bit addr (ATA/ATAPI v7) */
bool lba48;
unsigned char atapi; /* Use ATAPI protocol */
+ unsigned char bb; /* Use bounce buffer */
lbaint_t lba; /* number of blocks */
unsigned long blksz; /* block size */
int log2blksz; /* for convenience: log2(blksz) */
@@ -104,12 +108,6 @@
(PAD_SIZE(size, blk_desc->blksz))
#if CONFIG_IS_ENABLED(BLOCK_CACHE)
-
-/**
- * blkcache_init() - initialize the block cache list pointers
- */
-int blkcache_init(void);
-
/**
* blkcache_read() - attempt to read a set of blocks from cache
*
@@ -260,9 +258,25 @@
* @return 0 if OK, -ve on error
*/
int (*select_hwpart)(struct udevice *dev, int hwpart);
-};
-#define blk_get_ops(dev) ((struct blk_ops *)(dev)->driver->ops)
+#if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
+ /**
+ * buffer_aligned() - test memory alignment of block operation buffer
+ *
+ * Some devices have limited DMA capabilities and require that the
+ * buffers passed to them fit specific properties. This optional
+ * callback can be used to indicate whether a buffer alignment is
+ * suitable for the device DMA or not, and trigger use of generic
+ * bounce buffer implementation to help use of unsuitable buffers
+ * at the expense of performance degradation.
+ *
+ * @dev: Block device associated with the request
+ * @state: Bounce buffer state
+ * @return 1 if OK, 0 if unaligned
+ */
+ int (*buffer_aligned)(struct udevice *dev, struct bounce_buffer *state);
+#endif /* CONFIG_BOUNCE_BUFFER */
+};
/*
* These functions should take struct udevice instead of struct blk_desc,
@@ -502,6 +516,18 @@
*/
struct blk_desc *blk_get_by_device(struct udevice *dev);
+/**
+ * blk_get_desc() - Get the block device descriptor for the given device number
+ *
+ * @uclass_id: Interface type
+ * @devnum: Device number (0 = first)
+ * @descp: Returns block device descriptor on success
+ * Return: 0 on success, -ENODEV if there is no such device and no device
+ * with a higher device number, -ENOENT if there is no such device but there
+ * is one with a higher number, or other -ve on other error.
+ */
+int blk_get_desc(enum uclass_id uclass_id, int devnum, struct blk_desc **descp);
+
#else
#include <errno.h>
/*
@@ -705,32 +731,6 @@
int blk_print_part_devnum(enum uclass_id uclass_id, int devnum);
/**
- * blk_read_devnum() - read blocks from a device
- *
- * @uclass_id: Block device type
- * @devnum: Device number
- * @start: Start block number to read (0=first)
- * @blkcnt: Number of blocks to read
- * @buffer: Address to write data to
- * Return: number of blocks read, or -ve error number on error
- */
-ulong blk_read_devnum(enum uclass_id uclass_id, int devnum, lbaint_t start,
- lbaint_t blkcnt, void *buffer);
-
-/**
- * blk_write_devnum() - write blocks to a device
- *
- * @uclass_id: Block device type
- * @devnum: Device number
- * @start: Start block number to write (0=first)
- * @blkcnt: Number of blocks to write
- * @buffer: Address to read data from
- * Return: number of blocks written, or -ve error number on error
- */
-ulong blk_write_devnum(enum uclass_id uclass_id, int devnum, lbaint_t start,
- lbaint_t blkcnt, const void *buffer);
-
-/**
* blk_select_hwpart_devnum() - select a hardware partition
*
* This is similar to blk_dselect_hwpart() but it looks up the interface and
diff --git a/include/bloblist.h b/include/bloblist.h
index 7ea72c6..080cc46 100644
--- a/include/bloblist.h
+++ b/include/bloblist.h
@@ -413,8 +413,26 @@
* standard passage. The size is detected automatically so CONFIG_BLOBLIST_SIZE
* can be 0.
*
+ * Sets GD_FLG_BLOBLIST_READY in global_data flags on success
+ *
* Return: 0 if OK, -ve on error
*/
int bloblist_init(void);
+#if CONFIG_IS_ENABLED(BLOBLIST)
+/**
+ * bloblist_maybe_init() - Init the bloblist system if not already done
+ *
+ * Calls bloblist_init() if the GD_FLG_BLOBLIST_READY flag is not et
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int bloblist_maybe_init(void);
+#else
+static inline int bloblist_maybe_init(void)
+{
+ return 0;
+}
+#endif /* BLOBLIST */
+
#endif /* __BLOBLIST_H */
diff --git a/include/bootdev.h b/include/bootdev.h
index 8482331..35fa25a 100644
--- a/include/bootdev.h
+++ b/include/bootdev.h
@@ -65,7 +65,7 @@
*
* @info: Info structure describing this hunter
* @show: true to show information from the hunter
- * Returns: 0 if OK, -ve on error
+ * Returns: 0 if OK, -ENOENT on device not found, otherwise -ve on error
*/
typedef int (*bootdev_hunter_func)(struct bootdev_hunter *info, bool show);
@@ -321,6 +321,15 @@
int bootdev_hunt_prio(enum bootdev_prio_t prio, bool show);
/**
+ * bootdev_unhunt() - Mark a device as needing to be hunted again
+ *
+ * @id: uclass ID to update
+ * Return: 0 if done, -EALREADY if already in this state, -ENOENT if no hunter
+ * found for that uclass
+ */
+int bootdev_unhunt(enum uclass_id id);
+
+/**
* bootdev_hunt_and_find_by_label() - Hunt for bootdevs by label
*
* Runs the hunter for the label, then tries to find the bootdev, possible
diff --git a/include/bootflow.h b/include/bootflow.h
index 4152577..4211287 100644
--- a/include/bootflow.h
+++ b/include/bootflow.h
@@ -43,9 +43,14 @@
* and it is using the prior-stage FDT, which is the U-Boot control FDT.
* This is only possible with the EFI bootmeth (distro-efi) and only when
* CONFIG_OF_HAS_PRIOR_STAGE is enabled
+ * @BOOTFLOWF_STATIC_BUF: Indicates that @bflow->buf is statically set, rather
+ * than being allocated by malloc().
+ * @BOOTFLOWF_USE_BUILTIN_FDT : Indicates that current bootflow uses built-in FDT
*/
enum bootflow_flags_t {
BOOTFLOWF_USE_PRIOR_FDT = 1 << 0,
+ BOOTFLOWF_STATIC_BUF = 1 << 1,
+ BOOTFLOWF_USE_BUILTIN_FDT = 1 << 2,
};
/**
@@ -72,7 +77,7 @@
* @fname: Filename of bootflow file (allocated)
* @logo: Logo to display for this bootflow (BMP format)
* @logo_size: Size of the logo in bytes
- * @buf: Bootflow file contents (allocated)
+ * @buf: Bootflow file contents (allocated unless @flags & BOOTFLOWF_STATIC_BUF)
* @size: Size of bootflow file in bytes
* @err: Error number received (0 if OK)
* @os_name: Name of the OS / distro being booted, or NULL if not known
@@ -83,6 +88,7 @@
* @flags: Flags for the bootflow (see enum bootflow_flags_t)
* @cmdline: OS command line, or NULL if not known (allocated)
* @x86_setup: Pointer to x86 setup block inside @buf, NULL if not present
+ * @bootmeth_priv: Private data for the bootmeth
*/
struct bootflow {
struct list_head bm_node;
@@ -107,7 +113,8 @@
ulong fdt_addr;
int flags;
char *cmdline;
- char *x86_setup;
+ void *x86_setup;
+ void *bootmeth_priv;
};
/**
@@ -351,6 +358,17 @@
int bootflow_boot(struct bootflow *bflow);
/**
+ * bootflow_read_all() - Read all bootflow files
+ *
+ * Some bootmeths delay reading of large files until booting is requested. This
+ * causes those files to be read.
+ *
+ * @bflow: Bootflow to read
+ * Return: result of trying to read
+ */
+int bootflow_read_all(struct bootflow *bflow);
+
+/**
* bootflow_run_boot() - Try to boot a bootflow
*
* @iter: Current iteration (or NULL if none). Used to disable a bootmeth if the
diff --git a/include/bootm.h b/include/bootm.h
index 044a479..10a1bd6 100644
--- a/include/bootm.h
+++ b/include/bootm.h
@@ -9,6 +9,7 @@
#include <image.h>
+struct boot_params;
struct cmd_tbl;
#define BOOTM_ERR_RESET (-1)
@@ -55,6 +56,17 @@
int bootm_find_images(int flag, int argc, char *const argv[], ulong start,
ulong size);
+/*
+ * Measure the boot images. Measurement is the process of hashing some binary
+ * data and storing it into secure memory, i.e. TPM PCRs. In addition, each
+ * measurement is logged into the platform event log such that the operating
+ * system can access it and perform attestation of the boot.
+ *
+ * @images: The structure containing the various images to boot (linux,
+ * initrd, dts, etc.)
+ */
+int bootm_measure(struct bootm_headers *images);
+
int do_bootm_states(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[], int states, struct bootm_headers *images,
int boot_progress);
@@ -124,4 +136,50 @@
*/
int bootm_process_cmdline_env(int flags);
+/**
+ * zboot_start() - Boot a zimage
+ *
+ * Boot a zimage, given the component parts
+ *
+ * @addr: Address where the bzImage is moved before booting, either
+ * BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR
+ * @base: Pointer to the boot parameters, typically at address
+ * DEFAULT_SETUP_BASE
+ * @initrd: Address of the initial ramdisk, or 0 if none
+ * @initrd_size: Size of the initial ramdisk, or 0 if none
+ * @cmdline: Command line to use for booting
+ * Return: -EFAULT on error (normally it does not return)
+ */
+int zboot_start(ulong addr, ulong size, ulong initrd, ulong initrd_size,
+ ulong base, char *cmdline);
+
+/*
+ * zimage_get_kernel_version() - Get the version string from a kernel
+ *
+ * @params: boot_params pointer
+ * @kernel_base: base address of kernel
+ * Return: Kernel version as a NUL-terminated string
+ */
+const char *zimage_get_kernel_version(struct boot_params *params,
+ void *kernel_base);
+
+/**
+ * zimage_dump() - Dump the metadata of a zimage
+ *
+ * This shows all available information in a zimage that has been loaded.
+ *
+ * @base_ptr: Pointer to the boot parameters, typically at address
+ * DEFAULT_SETUP_BASE
+ * @show_cmdline: true to show the full command line
+ */
+void zimage_dump(struct boot_params *base_ptr, bool show_cmdline);
+
+/*
+ * bootm_boot_start() - Boot an image at the given address
+ *
+ * @addr: Image address
+ * @cmdline: Command line to set
+ */
+int bootm_boot_start(ulong addr, const char *cmdline);
+
#endif
diff --git a/include/bootmeth.h b/include/bootmeth.h
index 7cb7da3..0fc3610 100644
--- a/include/bootmeth.h
+++ b/include/bootmeth.h
@@ -16,9 +16,12 @@
* enum bootmeth_flags - Flags for bootmeths
*
* @BOOTMETHF_GLOBAL: bootmeth handles bootdev selection automatically
+ * @BOOTMETHF_ANY_PART: bootmeth is willing to check any partition, even if it
+ * has no filesystem
*/
enum bootmeth_flags {
BOOTMETHF_GLOBAL = BIT(0),
+ BOOTMETHF_ANY_PART = BIT(1),
};
/**
@@ -119,7 +122,16 @@
*/
int (*read_file)(struct udevice *dev, struct bootflow *bflow,
const char *file_path, ulong addr, ulong *sizep);
-
+#if CONFIG_IS_ENABLED(BOOTSTD_FULL)
+ /**
+ * readall() - read all files for a bootflow
+ *
+ * @dev: Bootmethod device to boot
+ * @bflow: Bootflow to read
+ * Return: 0 if OK, -EIO on I/O error, other -ve on other error
+ */
+ int (*read_all)(struct udevice *dev, struct bootflow *bflow);
+#endif /* BOOTSTD_FULL */
/**
* boot() - boot a bootflow
*
@@ -224,6 +236,20 @@
const char *file_path, ulong addr, ulong *sizep);
/**
+ * bootmeth_read_all() - read all bootflow files
+ *
+ * Some bootmeths delay reading of large files until booting is requested. This
+ * causes those files to be read.
+ *
+ * @dev: Bootmethod device to use
+ * @bflow: Bootflow to read
+ * Return: does not return on success, since it should boot the
+ * Operating Systemn. Returns -EFAULT if that fails, other -ve on
+ * other error
+ */
+int bootmeth_read_all(struct udevice *dev, struct bootflow *bflow);
+
+/**
* bootmeth_boot() - boot a bootflow
*
* @dev: Bootmethod device to boot
diff --git a/include/bootstage.h b/include/bootstage.h
index 685939c..affb0e5 100644
--- a/include/bootstage.h
+++ b/include/bootstage.h
@@ -11,6 +11,7 @@
#ifndef _BOOTSTAGE_H
#define _BOOTSTAGE_H
+#include <linux/types.h>
#include <linux/kconfig.h>
/* Flags for each bootstage record */
@@ -244,6 +245,8 @@
#ifdef ENABLE_BOOTSTAGE
+#include <mapmem.h>
+
/* This is the full bootstage implementation */
/**
@@ -452,6 +455,26 @@
#endif /* ENABLE_BOOTSTAGE */
+/* helpers for SPL */
+int _bootstage_stash_default(void);
+int _bootstage_unstash_default(void);
+
+static inline int bootstage_stash_default(void)
+{
+ if (CONFIG_IS_ENABLED(BOOTSTAGE) && IS_ENABLED(CONFIG_BOOTSTAGE_STASH))
+ return _bootstage_stash_default();
+
+ return 0;
+}
+
+static inline int bootstage_unstash_default(void)
+{
+ if (CONFIG_IS_ENABLED(BOOTSTAGE) && IS_ENABLED(CONFIG_BOOTSTAGE_STASH))
+ return _bootstage_unstash_default();
+
+ return 0;
+}
+
/* Helper macro for adding a bootstage to a line of code */
#define BOOTSTAGE_MARKER() \
bootstage_mark_code(__FILE__, __func__, __LINE__)
diff --git a/include/cache.h b/include/cache.h
index b12fec2..296ae3c 100644
--- a/include/cache.h
+++ b/include/cache.h
@@ -6,6 +6,8 @@
#ifndef __CACHE_H
#define __CACHE_H
+#include <linux/types.h>
+
struct udevice;
/*
diff --git a/include/cbfs.h b/include/cbfs.h
index 38efb1d..2bc5de2 100644
--- a/include/cbfs.h
+++ b/include/cbfs.h
@@ -22,7 +22,7 @@
enum cbfs_filetype {
CBFS_TYPE_BOOTBLOCK = 0x01,
CBFS_TYPE_CBFSHEADER = 0x02,
- CBFS_TYPE_STAGE = 0x10,
+ CBFS_TYPE_LEGACY_STAGE = 0x10,
CBFS_TYPE_PAYLOAD = 0x20,
CBFS_TYPE_SELF = CBFS_TYPE_PAYLOAD,
diff --git a/include/cedit.h b/include/cedit.h
new file mode 100644
index 0000000..f43cafa
--- /dev/null
+++ b/include/cedit.h
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __CEDIT_H
+#define __CEDIT_H
+
+#include <dm/ofnode_decl.h>
+
+struct abuf;
+struct expo;
+struct scene;
+struct video_priv;
+
+enum {
+ /* size increment for writing FDT */
+ CEDIT_SIZE_INC = 1024,
+};
+
+/* Name of the cedit node in the devicetree */
+#define CEDIT_NODE_NAME "cedit-values"
+
+extern struct expo *cur_exp;
+
+/**
+ * cedit_arange() - Arrange objects in a configuration-editor scene
+ *
+ * @exp: Expo to update
+ * @vid_priv: Private info of the video device
+ * @scene_id: scene ID to arrange
+ * Returns: 0 if OK, -ve on error
+ */
+int cedit_arange(struct expo *exp, struct video_priv *vid_priv, uint scene_id);
+
+/**
+ * cedit_run() - Run a configuration editor
+ *
+ * This accepts input until the user quits with Escape
+ *
+ * @exp: Expo to use
+ * Returns: 0 if OK, -ve on error
+ */
+int cedit_run(struct expo *exp);
+
+/**
+ * cedit_prepare() - Prepare to run a cedit
+ *
+ * Set up the video device, select the first scene and highlight the first item.
+ * This ensures that all menus have a selected item.
+ *
+ * @exp: Expo to use
+ * @vid_privp: Set to private data for the video device
+ * @scnp: Set to the first scene
+ * Return: scene ID of first scene if OK, -ve on error
+ */
+int cedit_prepare(struct expo *exp, struct video_priv **vid_privp,
+ struct scene **scnp);
+
+/**
+ * cedit_write_settings() - Write settings in FDT format
+ *
+ * Sets up an FDT with the settings
+ *
+ * @exp: Expo to write settings from
+ * @buf: Returns abuf containing the settings FDT (inited by this function)
+ * Return: 0 if OK, -ve on error
+ */
+int cedit_write_settings(struct expo *exp, struct abuf *buf);
+
+/**
+ * cedit_read_settings() - Read settings in FDT format
+ *
+ * Read an FDT with the settings
+ *
+ * @exp: Expo to read settings into
+ * @tree: Tree to read from
+ * Return: 0 if OK, -ve on error
+ */
+int cedit_read_settings(struct expo *exp, oftree tree);
+
+/**
+ * cedit_write_settings_env() - Write settings to envrionment variables
+ *
+ * @exp: Expo to write settings from
+ * @verbose: true to print each var as it is set
+ * Return: 0 if OK, -ve on error
+ */
+int cedit_write_settings_env(struct expo *exp, bool verbose);
+
+/*
+ * cedit_read_settings_env() - Read settings from the environment
+ *
+ * @exp: Expo to read settings into
+ * @verbose: true to print each var before it is read
+ */
+int cedit_read_settings_env(struct expo *exp, bool verbose);
+
+/**
+ * cedit_write_settings_cmos() - Write settings to CMOS RAM
+ *
+ * Write settings to the defined places in CMOS RAM
+ *
+ * @exp: Expo to write settings from
+ * @dev: UCLASS_RTC device containing space for this information
+ * Returns 0 if OK, -ve on error
+ * @verbose: true to print a summary at the end
+ */
+int cedit_write_settings_cmos(struct expo *exp, struct udevice *dev,
+ bool verbose);
+
+/**
+ * cedit_read_settings_cmos() - Read settings from CMOS RAM
+ *
+ * Read settings from the defined places in CMO RAM
+ *
+ * @exp: Expo to read settings into
+ * @dev: RTC device to read settings from
+ * @verbose: true to print a summary at the end
+ */
+int cedit_read_settings_cmos(struct expo *exp, struct udevice *dev,
+ bool verbose);
+
+#endif /* __CEDIT_H */
diff --git a/include/cli.h b/include/cli.h
index eeb94f7..c1db47f 100644
--- a/include/cli.h
+++ b/include/cli.h
@@ -8,6 +8,7 @@
#define __CLI_H
#include <stdbool.h>
+#include <linux/types.h>
/**
* struct cli_ch_state - state information for reading cmdline characters
@@ -25,6 +26,29 @@
};
/**
+ * struct cli_line_state - state of the line editor
+ *
+ * @num: Current cursor position, where 0 is the start
+ * @eol_num: Number of characters in the buffer
+ * @insert: true if in 'insert' mode
+ * @history: true if history should be accessible
+ * @cmd_complete: true if tab completion should be enabled (requires @prompt to
+ * be set)
+ * @buf: Buffer containing line
+ * @prompt: Prompt for the line
+ */
+struct cli_line_state {
+ uint num;
+ uint eol_num;
+ uint len;
+ bool insert;
+ bool history;
+ bool cmd_complete;
+ char *buf;
+ const char *prompt;
+};
+
+/**
* Go into the command loop
*
* This will return if we get a timeout waiting for a command. See
@@ -225,4 +249,31 @@
*/
int cli_ch_process(struct cli_ch_state *cch, int ichar);
+/**
+ * cread_line_process_ch() - Process a character for line input
+ *
+ * @cls: CLI line state
+ * @ichar: Character to process
+ * Return: 0 if input is complete, with line in cls->buf, -EINTR if input was
+ * cancelled with Ctrl-C, -EAGAIN if more characters are needed
+ */
+int cread_line_process_ch(struct cli_line_state *cls, char ichar);
+
+/**
+ * cli_cread_init() - Set up a new cread struct
+ *
+ * Sets up a new cread state, with history and cmd_complete set to false
+ *
+ * After calling this, you can use cread_line_process_ch() to process characters
+ * received from the user.
+ *
+ * @cls: CLI line state
+ * @buf: Text buffer containing the initial text
+ * @buf_size: Buffer size, including nul terminator
+ */
+void cli_cread_init(struct cli_line_state *cls, char *buf, uint buf_size);
+
+/** cread_print_hist_list() - Print the command-line history list */
+void cread_print_hist_list(void);
+
#endif
diff --git a/include/clk.h b/include/clk.h
index d912852..249c0e0 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -223,9 +223,11 @@
static inline struct clk *devm_clk_get_optional(struct udevice *dev,
const char *id)
{
+ int ret;
struct clk *clk = devm_clk_get(dev, id);
- if (PTR_ERR(clk) == -ENODATA)
+ ret = PTR_ERR(clk);
+ if (ret == -ENODATA || ret == -ENOENT)
return NULL;
return clk;
@@ -243,7 +245,7 @@
*
* Return: zero on success, or -ve error code.
*/
-int clk_release_all(struct clk *clk, int count);
+int clk_release_all(struct clk *clk, unsigned int count);
/**
* devm_clk_put - "free" a managed clock source
@@ -307,7 +309,7 @@
return -ENOSYS;
}
-static inline int clk_release_all(struct clk *clk, int count)
+static inline int clk_release_all(struct clk *clk, unsigned int count)
{
return -ENOSYS;
}
@@ -335,7 +337,7 @@
int ret;
ret = clk_get_by_name(dev, name, clk);
- if (ret == -ENODATA)
+ if (ret == -ENODATA || ret == -ENOENT)
return 0;
return ret;
@@ -359,7 +361,7 @@
int ret;
ret = clk_get_by_name_nodev(node, name, clk);
- if (ret == -ENODATA)
+ if (ret == -ENODATA || ret == -ENOENT)
return 0;
return ret;
diff --git a/include/command.h b/include/command.h
index c4e3170..6262365 100644
--- a/include/command.h
+++ b/include/command.h
@@ -25,6 +25,10 @@
#endif
#ifndef __ASSEMBLY__
+
+/* For ARRAY_SIZE() */
+#include <linux/kernel.h>
+
/*
* Monitor Command Table
*/
@@ -91,6 +95,12 @@
char *cmdv[]);
int cmd_auto_complete(const char *const prompt, char *buf, int *np,
int *colp);
+#else
+static inline int cmd_auto_complete(const char *const prompt, char *buf,
+ int *np, int *colp)
+{
+ return 0;
+}
#endif
/**
@@ -318,23 +328,8 @@
# define _CMD_HELP(x)
#endif
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
-#define U_BOOT_SUBCMDS_RELOC(_cmdname) \
- static void _cmdname##_subcmds_reloc(void) \
- { \
- static int relocated; \
- \
- if (relocated) \
- return; \
- \
- fixup_cmdtable(_cmdname##_subcmds, \
- ARRAY_SIZE(_cmdname##_subcmds)); \
- relocated = 1; \
- }
-#else
-#define U_BOOT_SUBCMDS_RELOC(_cmdname) \
- static void _cmdname##_subcmds_reloc(void) { }
-#endif
+#define U_BOOT_LONGHELP(_cmdname, text) \
+ static __maybe_unused const char _cmdname##_help_text[] = text
#define U_BOOT_SUBCMDS_DO_CMD(_cmdname) \
static int do_##_cmdname(struct cmd_tbl *cmdtp, int flag, \
@@ -343,8 +338,6 @@
{ \
struct cmd_tbl *subcmd; \
\
- _cmdname##_subcmds_reloc(); \
- \
/* We need at least the cmd and subcmd names. */ \
if (argc < 2 || argc > CONFIG_SYS_MAXARGS) \
return CMD_RET_USAGE; \
@@ -379,7 +372,6 @@
#define U_BOOT_SUBCMDS(_cmdname, ...) \
static struct cmd_tbl _cmdname##_subcmds[] = { __VA_ARGS__ }; \
- U_BOOT_SUBCMDS_RELOC(_cmdname) \
U_BOOT_SUBCMDS_DO_CMD(_cmdname) \
U_BOOT_SUBCMDS_COMPLETE(_cmdname)
diff --git a/include/common.h b/include/common.h
index 25c317f..a79c2bb 100644
--- a/include/common.h
+++ b/include/common.h
@@ -17,7 +17,6 @@
#include <errno.h>
#include <time.h>
#include <linux/types.h>
-#include <linux/printk.h>
#include <linux/string.h>
#include <stdarg.h>
#include <stdio.h>
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 504b1f0..67f4656 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -1,7 +1,7 @@
/*
* am335x_evm.h
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h
index ee6f622..dedef91 100644
--- a/include/configs/am335x_shc.h
+++ b/include/configs/am335x_shc.h
@@ -6,7 +6,7 @@
* Based on:
* am335x_evm.h
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __CONFIG_AM335X_SHC_H
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 7ee7b7e..9834289 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -2,7 +2,7 @@
/*
* am43xx_evm.h
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __CONFIG_AM43XX_EVM_H
diff --git a/include/configs/am62x_evm.h b/include/configs/am62x_evm.h
index 44180dc..c8fe59b 100644
--- a/include/configs/am62x_evm.h
+++ b/include/configs/am62x_evm.h
@@ -9,12 +9,6 @@
#ifndef __CONFIG_AM625_EVM_H
#define __CONFIG_AM625_EVM_H
-#include <config_distro_bootcmd.h>
-#include <env/ti/mmc.h>
-
-/* DDR Configuration */
-#define CFG_SYS_SDRAM_BASE1 0x880000000
-
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h
index 062102a..f9f8c7b 100644
--- a/include/configs/am64x_evm.h
+++ b/include/configs/am64x_evm.h
@@ -9,15 +9,6 @@
#ifndef __CONFIG_AM642_EVM_H
#define __CONFIG_AM642_EVM_H
-#include <linux/sizes.h>
-#include <config_distro_bootcmd.h>
-#include <env/ti/mmc.h>
-#include <asm/arch/am64_hardware.h>
-#include <env/ti/k3_dfu.h>
-
-/* DDR Configuration */
-#define CFG_SYS_SDRAM_BASE1 0x880000000
-
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h
index 9e90239..811dc0f 100644
--- a/include/configs/am65x_evm.h
+++ b/include/configs/am65x_evm.h
@@ -2,7 +2,7 @@
/*
* Configuration header file for K3 AM654 EVM
*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
diff --git a/include/configs/arbel.h b/include/configs/arbel.h
index 891257b..576ee37 100644
--- a/include/configs/arbel.h
+++ b/include/configs/arbel.h
@@ -7,11 +7,15 @@
#define __CONFIG_ARBEL_H
#define CFG_SYS_SDRAM_BASE 0x0
-#define CFG_SYS_BOOTMAPSZ (30 << 20)
+#define CFG_SYS_BOOTMAPSZ (128 << 20)
#define CFG_SYS_BOOTM_LEN (20 << 20)
#define CFG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE
#define CFG_SYS_INIT_RAM_SIZE 0x8000
+#define CFG_SYS_BAUDRATE_TABLE \
+ { 9600, 14400, 19200, 38400, 57600, 115200, 230400, 380400, 460800, 921600 }
+
+
/* Default environemnt variables */
#define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80400000\0" \
"stdin=serial\0" \
diff --git a/include/configs/arndale.h b/include/configs/arndale.h
index b56effc..fa64256 100644
--- a/include/configs/arndale.h
+++ b/include/configs/arndale.h
@@ -18,7 +18,4 @@
#define CFG_SMP_PEN_ADDR 0x02020000
-/* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
-#define CFG_ARM_GIC_BASE_ADDRESS 0x10480000
-
#endif /* __CONFIG_H */
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index e794638..cc54b51 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -1,7 +1,7 @@
/*
* am335x_evm.h
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index 03f8ed1..7a9f4af 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -101,7 +101,6 @@
UBI_BOOTCMD
#elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC)
#define MODULE_EXTRA_ENV_SETTINGS \
- "variant=-emmc\0" \
EMMC_ANDROID_BOOTCMD
#endif
diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h
index 3347c11..3ada21c 100644
--- a/include/configs/corstone1000.h
+++ b/include/configs/corstone1000.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * (C) Copyright 2022 ARM Limited
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
* (C) Copyright 2022 Linaro
* Rui Miguel Silva <rui.silva@linaro.org>
* Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
@@ -29,5 +29,6 @@
#include <config_distro_bootcmd.h>
+#define CFG_EXTRA_ENV_SETTINGS BOOTENV
#endif
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index cef4042..416aa96 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
*
* Based on davinci_dvevm.h. Original Copyrights follow:
*
diff --git a/include/configs/draco.h b/include/configs/draco.h
index 4c67174..8f993ce 100644
--- a/include/configs/draco.h
+++ b/include/configs/draco.h
@@ -6,7 +6,7 @@
* Based on:
* U-Boot file:/include/configs/am335x_evm.h
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __CONFIG_DRACO_H
diff --git a/include/configs/ds116.h b/include/configs/ds116.h
index 031f4f6..0883ec4 100644
--- a/include/configs/ds116.h
+++ b/include/configs/ds116.h
@@ -20,15 +20,8 @@
*/
#include "mv-common.h"
-/* Include the common distro boot environment */
#ifndef CONFIG_SPL_BUILD
-#define BOOT_TARGET_DEVICES(func) \
- func(USB, usb, 0) \
- func(SCSI, scsi, 0) \
- func(PXE, pxe, na) \
- func(DHCP, dhcp, na)
-
#define KERNEL_ADDR_R __stringify(0x1000000)
#define FDT_ADDR_R __stringify(0x2000000)
#define RAMDISK_ADDR_R __stringify(0x2200000)
@@ -42,14 +35,11 @@
"scriptaddr=" SCRIPT_ADDR_R "\0" \
"pxefile_addr_r=" PXEFILE_ADDR_R "\0"
-#include <config_distro_bootcmd.h>
-
#define CFG_EXTRA_ENV_SETTINGS \
RELOCATION_LIMITS_ENV_SETTINGS \
LOAD_ADDRESS_ENV_SETTINGS \
"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
- "console=ttyS0,115200\0" \
- BOOTENV
+ "console=ttyS0,115200\0"
#endif /* CONFIG_SPL_BUILD */
diff --git a/include/configs/etamin.h b/include/configs/etamin.h
index d07b4e9..97585a4 100644
--- a/include/configs/etamin.h
+++ b/include/configs/etamin.h
@@ -6,7 +6,7 @@
* Based on:
* U-Boot file:/include/configs/am335x_evm.h
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __CONFIG_ETAMIN_H
diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h
index 0ba4efe..1b97ae2 100644
--- a/include/configs/gardena-smart-gateway-mt7688.h
+++ b/include/configs/gardena-smart-gateway-mt7688.h
@@ -11,10 +11,6 @@
#define CFG_SYS_INIT_SP_OFFSET 0x400000
-/* SPL */
-
-#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
-
/* Dummy value */
#define CFG_SYS_UBOOT_BASE 0
diff --git a/include/configs/imxrt1020-evk.h b/include/configs/imxrt1020-evk.h
index e180387..cd6af93 100644
--- a/include/configs/imxrt1020-evk.h
+++ b/include/configs/imxrt1020-evk.h
@@ -18,10 +18,4 @@
#define DMAMEM_BASE (PHYS_SDRAM + PHYS_SDRAM_SIZE - \
DMAMEM_SZ_ALL)
-/*
- * Configuration of the external SDRAM memory
- */
-
-#define CFG_SYS_UBOOT_START 0x800023FD
-
#endif /* __IMXRT1020_EVK_H */
diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h
index 7688464..2af2dde 100644
--- a/include/configs/imxrt1050-evk.h
+++ b/include/configs/imxrt1050-evk.h
@@ -25,10 +25,4 @@
"stderr=serial,vidconsole\0"
#endif
-/*
- * Configuration of the external SDRAM memory
- */
-
-#define CFG_SYS_UBOOT_START 0x800023FD
-
#endif /* __IMXRT1050_EVK_H */
diff --git a/include/configs/imxrt1170-evk.h b/include/configs/imxrt1170-evk.h
index f834290..1ccaa15 100644
--- a/include/configs/imxrt1170-evk.h
+++ b/include/configs/imxrt1170-evk.h
@@ -22,8 +22,5 @@
#define DMAMEM_SZ_ALL (1 * 1024 * 1024)
#define DMAMEM_BASE (PHYS_SDRAM + PHYS_SDRAM_SIZE - \
DMAMEM_SZ_ALL)
-/* For SPL */
-#define CFG_SYS_UBOOT_START 0x202403FD
-/* For SPL ends */
#endif /* __IMXRT1170_EVK_H */
diff --git a/include/configs/inteno_xg6846.h b/include/configs/inteno_xg6846.h
new file mode 100644
index 0000000..4f2a2f8
--- /dev/null
+++ b/include/configs/inteno_xg6846.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 Linus Walleij <linusw@kernel.org>
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6328.h>
+
diff --git a/include/configs/iot2050.h b/include/configs/iot2050.h
index 4968722..94a9c76 100644
--- a/include/configs/iot2050.h
+++ b/include/configs/iot2050.h
@@ -15,6 +15,15 @@
#include <configs/ti_armv7_common.h>
+/* allow up to 3 USB storage devices */
+#ifdef CONFIG_CMD_USB
+#undef BOOT_TARGET_USB
+#define BOOT_TARGET_USB(func) \
+ func(USB, usb, 0) \
+ func(USB, usb, 1) \
+ func(USB, usb, 2)
+#endif
+
/*
* This defines all MMC devices, even if the basic variant has no mmc1.
* The non-supported device will be removed from the boot targets during
diff --git a/include/configs/kstr-sama5d27.h b/include/configs/kstr-sama5d27.h
new file mode 100644
index 0000000..772a073
--- /dev/null
+++ b/include/configs/kstr-sama5d27.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2021-2023 Conclusive Engineering Sp. z o. o.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "at91-sama5_common.h"
+
+/* SDRAM */
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x10000000
+
+#endif
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
index ff96658..a50f948 100644
--- a/include/configs/legoev3.h
+++ b/include/configs/legoev3.h
@@ -4,7 +4,7 @@
*
* Based on da850evm.h
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
*
* Based on davinci_dvevm.h. Original Copyrights follow:
*
diff --git a/include/configs/libretech-ac.h b/include/configs/libretech-ac.h
index bf20d31..16239f2 100644
--- a/include/configs/libretech-ac.h
+++ b/include/configs/libretech-ac.h
@@ -11,6 +11,7 @@
#define BOOT_TARGET_DEVICES(func) \
func(ROMUSB, romusb, na) \
+ func(USB_DFU, usbdfu, na) \
func(MMC, mmc, 0) \
BOOT_TARGET_DEVICES_USB(func) \
func(PXE, pxe, na) \
diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h
index f16c7e9..e8f7a59 100644
--- a/include/configs/linkit-smart-7688.h
+++ b/include/configs/linkit-smart-7688.h
@@ -11,10 +11,6 @@
#define CFG_SYS_INIT_SP_OFFSET 0x400000
-/* SPL */
-
-#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
-
/* Dummy value */
#define CFG_SYS_UBOOT_BASE 0
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index 38fb1d4..867b098 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -21,8 +21,7 @@
(defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT))
#define SPL_NO_MMC
#endif
-#if defined(CONFIG_SPL_BUILD) && \
- !defined(CONFIG_SPL_FSL_LS_PPA)
+#if defined(CONFIG_SPL_BUILD)
#define SPL_NO_IFC
#endif
diff --git a/include/configs/meson64.h b/include/configs/meson64.h
index 801cdae..efab9a6 100644
--- a/include/configs/meson64.h
+++ b/include/configs/meson64.h
@@ -53,6 +53,30 @@
#define BOOTENV_DEV_NAME_ROMUSB(devtypeu, devtypel, instance) \
"romusb "
+/*
+ * Fallback to "USB DFU" boot if script is not at scriptaddr
+ *
+ * DFU will expose the kernel_addr_r memory range as DFU entry,
+ * then with `dfu-util --detach`, booting the uploaded image
+ * will be attempted:
+ * $ dfu-util -a 0 -D fitImage
+ * $ dfu-util -a 0 -e
+ */
+#if CONFIG_IS_ENABLED(USB_GADGET) && CONFIG_IS_ENABLED(DFU_RAM)
+ #define BOOTENV_DEV_USB_DFU(devtypeu, devtypel, instance) \
+ "bootcmd_usbdfu=" \
+ "if test \"${boot_source}\" = \"usb\"; then " \
+ "dfu 0 ram 0 60;" \
+ "bootm ${kernel_addr_r};" \
+ "fi\0"
+
+ #define BOOTENV_DEV_NAME_USB_DFU(devtypeu, devtypel, instance) \
+ "usbdfu "
+#else
+ #define BOOTENV_DEV_USB_DFU(devtypeu, devtypel, instance)
+ #define BOOTENV_DEV_NAME_USB_DFU(devtypeu, devtypel, instance)
+#endif
+
#ifdef CONFIG_CMD_USB
#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
#else
@@ -74,6 +98,7 @@
#ifndef BOOT_TARGET_DEVICES
#define BOOT_TARGET_DEVICES(func) \
func(ROMUSB, romusb, na) \
+ func(USB_DFU, usbdfu, na) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
func(MMC, mmc, 2) \
@@ -84,6 +109,15 @@
func(DHCP, dhcp, na)
#endif
+#define BOOTM_SIZE __stringify(0x1700000)
+#define KERNEL_ADDR_R __stringify(0x08080000)
+#define KERNEL_COMP_ADDR_R __stringify(0x0d080000)
+#define FDT_ADDR_R __stringify(0x08008000)
+#define SCRIPT_ADDR_R __stringify(0x08000000)
+#define PXEFILE_ADDR_R __stringify(0x01080000)
+#define FDTOVERLAY_ADDR_R __stringify(0x01000000)
+#define RAMDISK_ADDR_R __stringify(0x13000000)
+
#include <config_distro_bootcmd.h>
#ifndef CFG_EXTRA_ENV_SETTINGS
@@ -91,15 +125,16 @@
"stdin=" STDIN_CFG "\0" \
"stdout=" STDOUT_CFG "\0" \
"stderr=" STDOUT_CFG "\0" \
- "kernel_comp_addr_r=0x0d080000\0" \
+ "kernel_comp_addr_r=" KERNEL_COMP_ADDR_R "\0" \
"kernel_comp_size=0x2000000\0" \
- "fdt_addr_r=0x08008000\0" \
- "scriptaddr=0x08000000\0" \
- "kernel_addr_r=0x08080000\0" \
- "pxefile_addr_r=0x01080000\0" \
- "fdtoverlay_addr_r=0x01000000\0" \
- "ramdisk_addr_r=0x13000000\0" \
+ "fdt_addr_r=" FDT_ADDR_R "\0" \
+ "scriptaddr=" SCRIPT_ADDR_R "\0" \
+ "kernel_addr_r=" KERNEL_ADDR_R "\0" \
+ "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \
+ "fdtoverlay_addr_r=" FDTOVERLAY_ADDR_R "\0" \
+ "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \
"fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "dfu_alt_info=fitimage ram " KERNEL_ADDR_R " 0x4000000 \0" \
BOOTENV
#endif
diff --git a/include/configs/mt7620.h b/include/configs/mt7620.h
index d69d35f..3bc0c18 100644
--- a/include/configs/mt7620.h
+++ b/include/configs/mt7620.h
@@ -12,9 +12,6 @@
#define CFG_SYS_INIT_SP_OFFSET 0x400000
-/* SPL */
-#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
-
/* Dummy value */
#define CFG_SYS_UBOOT_BASE 0
diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h
index 0ac376d..1df0681 100644
--- a/include/configs/mt7628.h
+++ b/include/configs/mt7628.h
@@ -22,9 +22,6 @@
#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 460800, 921600 }
-/* SPL */
-#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
-
/* Dummy value */
#define CFG_SYS_UBOOT_BASE 0
diff --git a/include/configs/mt8512.h b/include/configs/mt8512.h
index c0fc868..4e70291 100644
--- a/include/configs/mt8512.h
+++ b/include/configs/mt8512.h
@@ -10,8 +10,6 @@
#define __MT8512_H
/* Uboot definition */
-#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
-
#define ENV_BOOT_READ_IMAGE \
"boot_rd_img=mmc dev 0" \
";mmc read ${loadaddr} 0x27000 0x8000" \
diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h
index 76e148f..18b55be 100644
--- a/include/configs/mvebu_armada-37xx.h
+++ b/include/configs/mvebu_armada-37xx.h
@@ -30,7 +30,6 @@
/*
* Environment
*/
-#define DEFAULT_ENV_IS_RW /* required for configuring default fdtfile= */
#ifdef CONFIG_MMC
#define BOOT_TARGET_DEVICES_MMC(func, i) func(MMC, mmc, i)
diff --git a/include/configs/n2350.h b/include/configs/n2350.h
index 92b2270..d8a9814 100644
--- a/include/configs/n2350.h
+++ b/include/configs/n2350.h
@@ -20,15 +20,8 @@
*/
#include "mv-common.h"
-/* Include the common distro boot environment */
#ifndef CONFIG_SPL_BUILD
-#define BOOT_TARGET_DEVICES(func) \
- func(SCSI, scsi, 0) \
- func(USB, usb, 0) \
- func(PXE, pxe, na) \
- func(DHCP, dhcp, na)
-
#define KERNEL_ADDR_R __stringify(0x1000000)
#define FDT_ADDR_R __stringify(0x2000000)
#define RAMDISK_ADDR_R __stringify(0x2200000)
@@ -42,14 +35,11 @@
"scriptaddr=" SCRIPT_ADDR_R "\0" \
"pxefile_addr_r=" PXEFILE_ADDR_R "\0"
-#include <config_distro_bootcmd.h>
-
#define CFG_EXTRA_ENV_SETTINGS \
RELOCATION_LIMITS_ENV_SETTINGS \
LOAD_ADDRESS_ENV_SETTINGS \
"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
- "console=ttyS0,115200\0" \
- BOOTENV
+ "console=ttyS0,115200\0"
#endif /* CONFIG_SPL_BUILD */
diff --git a/include/configs/nanopc-t6-rk3588.h b/include/configs/nanopc-t6-rk3588.h
new file mode 100644
index 0000000..1ece6f9
--- /dev/null
+++ b/include/configs/nanopc-t6-rk3588.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __NANOPCT6_RK3588_H
+#define __NANOPCT6_RK3588_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#include <configs/rk3588_common.h>
+
+#endif /* __NANOPCT6_RK3588_H */
diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h
index fa029a1..8c4d035 100644
--- a/include/configs/nsa310s.h
+++ b/include/configs/nsa310s.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2015, 2021-2022 Tony Dinh <mibodhi@gmail.com>
+ * Copyright (C) 2015, 2021-2023 Tony Dinh <mibodhi@gmail.com>
* Copyright (C) 2015
* Gerald Kerma <dreagle@doukki.net>
* Luka Perkov <luka.perkov@sartura.hr>
@@ -15,14 +15,6 @@
*/
#include "mv-common.h"
-/* Include the common distro boot environment */
-#ifndef CONFIG_SPL_BUILD
-
-#define BOOT_TARGET_DEVICES(func) \
- func(USB, usb, 0) \
- func(SATA, sata, 0) \
- func(DHCP, dhcp, na)
-
#define KERNEL_ADDR_R __stringify(0x800000)
#define FDT_ADDR_R __stringify(0x2c00000)
#define RAMDISK_ADDR_R __stringify(0x01100000)
@@ -34,16 +26,11 @@
"ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \
"scriptaddr=" SCRIPT_ADDR_R "\0"
-#include <config_distro_bootcmd.h>
-
#define CFG_EXTRA_ENV_SETTINGS \
"console=console=ttyS0,115200\0" \
"kernel=/boot/zImage\0" \
"fdt=/boot/nsa310s.dtb\0" \
"bootargs_root=ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw\0" \
- LOAD_ADDRESS_ENV_SETTINGS \
- BOOTENV
-
-#endif /* CONFIG_SPL_BUILD */
+ LOAD_ADDRESS_ENV_SETTINGS
#endif /* _CONFIG_NSA310S_H */
diff --git a/include/configs/nsa325.h b/include/configs/nsa325.h
new file mode 100644
index 0000000..00a148c
--- /dev/null
+++ b/include/configs/nsa325.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016-2023 Tony Dinh <mibodhi@gmail.com>
+ * (C) Copyright 2014 Jason Plum <jplum@archlinuxarm.org>
+ *
+ * Based on
+ * Copyright (C) 2012 Peter Schildmann <linux@schildmann.info>
+ *
+ * Based on guruplug.h originally written by
+ * Siddarth Gore <gores@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ */
+
+#ifndef _CONFIG_NSA325_H
+#define _CONFIG_NSA325_H
+
+#include "mv-common.h"
+
+#define KERNEL_ADDR_R __stringify(0x800000)
+#define FDT_ADDR_R __stringify(0x2c00000)
+#define RAMDISK_ADDR_R __stringify(0x01100000)
+#define SCRIPT_ADDR_R __stringify(0x200000)
+
+#define LOAD_ADDRESS_ENV_SETTINGS \
+ "kernel_addr_r=" KERNEL_ADDR_R "\0" \
+ "fdt_addr_r=" FDT_ADDR_R "\0" \
+ "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \
+ "scriptaddr=" SCRIPT_ADDR_R "\0"
+
+#define CFG_EXTRA_ENV_SETTINGS \
+ LOAD_ADDRESS_ENV_SETTINGS \
+ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+ "console=ttyS0,115200\0"
+
+#endif /* _CONFIG_NSA325_H */
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index f449677..2cb2e52 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -2,7 +2,7 @@
/*
* Configuration settings for the TI OMAP3 EVM board.
*
- * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2006-2011 Texas Instruments Incorporated - https://www.ti.com/
*
* Author :
* Manikandan Pillai <mani.pillai@ti.com>
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index fc2655a..5b7eb0b 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
*
* Based on davinci_dvevm.h. Original Copyrights follow:
*
diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h
index 80b14b0..24d7dcd 100644
--- a/include/configs/pdu001.h
+++ b/include/configs/pdu001.h
@@ -4,7 +4,7 @@
*
* Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __CONFIG_PDU001_H
diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h
index 8668da6..060a150 100644
--- a/include/configs/phycore_am335x_r2.h
+++ b/include/configs/phycore_am335x_r2.h
@@ -4,7 +4,7 @@
*
* Phytec phyCORE-AM335x R2 (PCL060 / PCM060) boards information header
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
* Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
* Copyright (C) 2019 DENX Software Engineering GmbH
*/
diff --git a/include/configs/pogo_v4.h b/include/configs/pogo_v4.h
index 3371579..d500353 100644
--- a/include/configs/pogo_v4.h
+++ b/include/configs/pogo_v4.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2014-2022 Tony Dinh <mibodhi@gmail.com>
+ * Copyright (C) 2014-2023 Tony Dinh <mibodhi@gmail.com>
*
* Based on
* Copyright (C) 2012
@@ -21,33 +21,6 @@
*/
#include "mv-common.h"
-/* Include the common distro boot environment */
-#ifndef CONFIG_SPL_BUILD
-
-#ifdef CONFIG_MMC
-#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
-#else
-#define BOOT_TARGET_DEVICES_MMC(func)
-#endif
-
-#ifdef CONFIG_SATA
-#define BOOT_TARGET_DEVICES_SATA(func) func(SATA, sata, 0)
-#else
-#define BOOT_TARGET_DEVICES_SATA(func)
-#endif
-
-#ifdef CONFIG_USB_STORAGE
-#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
-#else
-#define BOOT_TARGET_DEVICES_USB(func)
-#endif
-
-#define BOOT_TARGET_DEVICES(func) \
- BOOT_TARGET_DEVICES_MMC(func) \
- BOOT_TARGET_DEVICES_USB(func) \
- BOOT_TARGET_DEVICES_SATA(func) \
- func(DHCP, dhcp, na)
-
#define KERNEL_ADDR_R __stringify(0x800000)
#define FDT_ADDR_R __stringify(0x2c00000)
#define RAMDISK_ADDR_R __stringify(0x01100000)
@@ -59,14 +32,10 @@
"ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \
"scriptaddr=" SCRIPT_ADDR_R "\0"
-#include <config_distro_bootcmd.h>
-
#define CFG_EXTRA_ENV_SETTINGS \
LOAD_ADDRESS_ENV_SETTINGS \
"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- "console=ttyS0,115200\0" \
- BOOTENV
-#endif /* CONFIG_SPL_BUILD */
+ "console=ttyS0,115200\0"
#endif /* _CONFIG_POGO_V4_H */
diff --git a/include/configs/poleg.h b/include/configs/poleg.h
index 1e96e83..2a2d85c 100644
--- a/include/configs/poleg.h
+++ b/include/configs/poleg.h
@@ -13,6 +13,8 @@
#define CFG_SYS_BOOTMAPSZ (0x30 << 20)
#define CFG_SYS_SDRAM_BASE 0x0
+#define CFG_SYS_BAUDRATE_TABLE { 57600, 115200, 230400, 460800 }
+
/* Default environemnt variables */
#define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \
"stdin=serial\0" \
diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h
index b701e52..040178b 100644
--- a/include/configs/pxm2.h
+++ b/include/configs/pxm2.h
@@ -7,7 +7,7 @@
* Based on:
* U-Boot file:/include/configs/am335x_evm.h
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __CONFIG_PXM2_H
diff --git a/include/configs/quartzpro64-rk3588.h b/include/configs/quartzpro64-rk3588.h
new file mode 100644
index 0000000..a1faa2a
--- /dev/null
+++ b/include/configs/quartzpro64-rk3588.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ * Copyright 2023 Google, Inc
+ */
+
+#ifndef __QUARTZPRO64_RK3588_H
+#define __QUARTZPRO64_RK3588_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#include <configs/rk3588_common.h>
+
+#endif /* __QUARTZPRO64_RK3588_H */
diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h
index 2efb4d2..0991ebf 100644
--- a/include/configs/rastaban.h
+++ b/include/configs/rastaban.h
@@ -6,7 +6,7 @@
* Based on:
* U-Boot file:/include/configs/am335x_evm.h
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __CONFIG_RASTABAN_H
diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h
index 7d55fcd..861154f 100644
--- a/include/configs/rk3308_common.h
+++ b/include/configs/rk3308_common.h
@@ -16,11 +16,13 @@
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00500000\0" \
"pxefile_addr_r=0x00600000\0" \
- "fdt_addr_r=0x02800000\0" \
+ "fdt_addr_r=0x03e00000\0" \
+ "fdtoverlay_addr_r=0x03f00000\0" \
"kernel_addr_r=0x00680000\0" \
"ramdisk_addr_r=0x04000000\0"
#define CFG_EXTRA_ENV_SETTINGS \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
ENV_MEM_LAYOUT_SETTINGS \
"partitions=" PARTS_DEFAULT \
ROCKCHIP_DEVICE_SETTINGS \
diff --git a/include/configs/rut.h b/include/configs/rut.h
index 4002bc4..7cc2bd5 100644
--- a/include/configs/rut.h
+++ b/include/configs/rut.h
@@ -7,7 +7,7 @@
* Based on:
* U-Boot file:/include/configs/am335x_evm.h
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __CONFIG_RUT_H
diff --git a/include/configs/rzg2l-smarc.h b/include/configs/rzg2l-smarc.h
new file mode 100644
index 0000000..ea57d28
--- /dev/null
+++ b/include/configs/rzg2l-smarc.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 Renesas Electronics Corporation
+ */
+
+#ifndef __RENESAS_RZG2L_H
+#define __RENESAS_RZG2L_H
+
+#include <asm/arch/rmobile.h>
+
+/* console */
+#define CFG_SYS_BAUDRATE_TABLE { 115200, 38400 }
+
+#endif /* __RENESAS_RZG2L_H */
diff --git a/include/configs/sama5d29_curiosity.h b/include/configs/sama5d29_curiosity.h
new file mode 100644
index 0000000..ef09b8b
--- /dev/null
+++ b/include/configs/sama5d29_curiosity.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration file for the SAMA5D29 CURIOSITY board.
+ *
+ * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Mihai Sain <mihai.sain@microchip.com>
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 24000000
+
+#endif
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 4e5653d..2372485 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -18,4 +18,7 @@
#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
+/* Unused but necessary to build */
+#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
+
#endif
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 7def657..6b1d5ca 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -7,7 +7,7 @@
* Based on:
* U-Boot file:/include/configs/am335x_evm.h
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __CONFIG_SIEMENS_AM33X_COMMON_H
diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
index 74150b7..de8bfc1 100644
--- a/include/configs/sifive-unmatched.h
+++ b/include/configs/sifive-unmatched.h
@@ -36,7 +36,7 @@
"name=system,size=-,bootable,type=${type_guid_gpt_system};"
#define CFG_EXTRA_ENV_SETTINGS \
- "kernel_addr_r=0x84000000\0" \
+ "kernel_addr_r=0x80200000\0" \
"kernel_comp_addr_r=0x88000000\0" \
"kernel_comp_size=0x4000000\0" \
"fdt_addr_r=0x8c000000\0" \
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 0c96c9c..4838bfd 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -18,7 +18,7 @@
#define CFG_SYS_INIT_RAM_ADDR 0xFFE00000
/* SPL memory allocation configuration, this is for FAT implementation */
#define CFG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
- CONFIG_SYS_SPL_MALLOC_SIZE)
+ CONFIG_SPL_SYS_MALLOC_SIZE)
#endif
/*
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index 66ecb16..820372c 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -112,7 +112,7 @@
* SDRAM
* 0x0000_0000 ...... Start of SDRAM_1
* unused / empty space for image loading
- * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
+ * Size 64MB ...... MALLOC (size CONFIG_SPL_SYS_MALLOC_SIZE)
* Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
* 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
*
diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h
index 4ee02b8..29c7447 100644
--- a/include/configs/starfive-visionfive2.h
+++ b/include/configs/starfive-visionfive2.h
@@ -18,6 +18,9 @@
/* Environment options */
#define BOOT_TARGET_DEVICES(func) \
+ func(NVME, nvme, 0) \
+ func(USB, usb, 0) \
+ func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
func(DHCP, dhcp, na)
@@ -37,6 +40,7 @@
"kernel_comp_addr_r=0x88000000\0" \
"kernel_comp_size=0x4000000\0" \
"fdt_addr_r=0x46000000\0" \
+ "fdtoverlay_addr_r=0x45800000\0" \
"scriptaddr=0x43900000\0" \
"pxefile_addr_r=0x45900000\0" \
"ramdisk_addr_r=0x46100000\0" \
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index 9bf01ca..00ec9ef 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -23,6 +23,10 @@
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
+#define STM32F746_BOARD_EXTRA_ENV \
+ "splashimage=0xC0448000\0" \
+ "splashpos=m,m\0"
+
#include <config_distro_bootcmd.h>
#define CFG_EXTRA_ENV_SETTINGS \
"kernel_addr_r=0xC0008000\0" \
@@ -31,7 +35,8 @@
"scriptaddr=0xC0418000\0" \
"pxefile_addr_r=0xC0428000\0" \
"ramdisk_addr_r=0xC0438000\0" \
- BOOTENV
+ BOOTENV \
+ STM32F746_BOARD_EXTRA_ENV
#define CFG_SYS_UBOOT_BASE (CFG_SYS_FLASH_BASE + \
CONFIG_SPL_PAD_TO)
diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h
index 7c59c69..5b0658c 100644
--- a/include/configs/stm32mp13_common.h
+++ b/include/configs/stm32mp13_common.h
@@ -35,16 +35,27 @@
#define BOOT_TARGET_MMC1(func)
#endif
+#ifdef CONFIG_CMD_USB
+#define BOOT_TARGET_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_USB(func)
+#endif
+
#define BOOT_TARGET_DEVICES(func) \
BOOT_TARGET_MMC1(func) \
- BOOT_TARGET_MMC0(func)
+ BOOT_TARGET_MMC0(func) \
+ BOOT_TARGET_USB(func)
/*
* default bootcmd for stm32mp13:
+ * for serial/usb: execute the stm32prog command
* for mmc boot (eMMC, SD card), distro boot on the same mmc device
*/
#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \
"echo \"Boot over ${boot_device}${boot_instance}!\";" \
+ "if test ${boot_device} = serial || test ${boot_device} = usb;" \
+ "then stm32prog ${boot_device} ${boot_instance}; " \
+ "else " \
"run env_check;" \
"if test ${boot_device} = mmc;" \
"then env set boot_targets \"mmc${boot_instance}\"; fi;" \
diff --git a/include/configs/stm32mp15_dh_dhsom.h b/include/configs/stm32mp15_dh_dhsom.h
index 9192169..8ff8822 100644
--- a/include/configs/stm32mp15_dh_dhsom.h
+++ b/include/configs/stm32mp15_dh_dhsom.h
@@ -20,7 +20,26 @@
#define STM32MP_BOARD_EXTRA_ENV \
"usb_pgood_delay=1000\0" \
- "update_sf=" /* Erase SPI NOR and install U-Boot from SD */ \
+ "dh_update_sd_to_emmc=" /* Install U-Boot from SD to eMMC */ \
+ "setexpr loadaddr1 ${loadaddr} + 0x1000000 && " \
+ "load mmc 0:4 ${loadaddr1} boot/u-boot-spl.stm32 && " \
+ "setexpr sblkcnt ${filesize} + 0x1ff && " \
+ "setexpr sblkcnt ${sblkcnt} / 0x200 && " \
+ "load mmc 0:4 ${loadaddr} boot/u-boot.itb && " \
+ "setexpr ublkcnt ${filesize} + 0x1ff && " \
+ "setexpr ublkcnt ${ublkcnt} / 0x200 && " \
+ "mmc partconf 1 1 1 1 && mmc dev 1 1 && " \
+ "mmc write ${loadaddr1} 0 ${sblkcnt} && " \
+ "mmc dev 1 2 && " \
+ "mmc write ${loadaddr1} 0 ${sblkcnt} && " \
+ "mmc dev 1 && " \
+ "gpt write mmc 1 'name=ssbl,size=2MiB' && " \
+ "mmc write ${loadaddr} 0x22 ${ublkcnt} && " \
+ "mmc partconf 1 1 1 0 && " \
+ "setenv loadaddr1 && " \
+ "setenv sblkcnt && " \
+ "setenv ublkcnt\0" \
+ "dh_update_sd_to_sf=" /* Erase SPI NOR and install U-Boot from SD */ \
"setexpr loadaddr1 ${loadaddr} + 0x1000000 && " \
"load mmc 0:4 ${loadaddr1} /boot/u-boot-spl.stm32 && " \
"env set filesize1 ${filesize} && " \
@@ -29,7 +48,9 @@
"sf update ${loadaddr1} 0 ${filesize1} && " \
"sf update ${loadaddr1} 0x40000 ${filesize1} && " \
"sf update ${loadaddr} 0x80000 ${filesize} && " \
- "env set filesize1 && env set loadaddr1\0"
+ "env set filesize1 && env set loadaddr1\0" \
+ "update_sf=run dh_update_sd_to_sf\0"
+
#include <configs/stm32mp15_common.h>
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index d2d70f0..b8ca77d 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -12,7 +12,6 @@
#ifndef _SUNXI_COMMON_CONFIG_H
#define _SUNXI_COMMON_CONFIG_H
-#include <asm/arch/cpu.h>
#include <linux/stringify.h>
/* Serial & console */
@@ -24,6 +23,7 @@
#define CFG_SYS_NS16550_CLK 24000000
#endif
#if !CONFIG_IS_ENABLED(DM_SERIAL)
+#include <asm/arch/serial.h>
# define CFG_SYS_NS16550_COM1 SUNXI_UART0_BASE
# define CFG_SYS_NS16550_COM2 SUNXI_UART1_BASE
# define CFG_SYS_NS16550_COM3 SUNXI_UART2_BASE
diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h
index cd7359c..e36e63e 100644
--- a/include/configs/synquacer.h
+++ b/include/configs/synquacer.h
@@ -41,20 +41,6 @@
/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
#ifdef CONFIG_FWU_MULTI_BANK_UPDATE
-#define DEFAULT_DFU_ALT_INFO
-#else
-#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \
- "mtd nor1=u-boot.bin raw 200000 100000;" \
- "fip.bin raw 180000 78000;" \
- "optee.bin raw 500000 100000\0"
-#endif
-
-/* GUIDs for capsule updatable firmware images */
-#define DEVELOPERBOX_UBOOT_IMAGE_GUID \
- EFI_GUID(0x53a92e83, 0x4ef4, 0x473a, 0x8b, 0x0d, \
- 0xb5, 0xd8, 0xc7, 0xb2, 0xd6, 0x00)
-
-#ifdef CONFIG_FWU_MULTI_BANK_UPDATE
#define DEVELOPERBOX_FIP_IMAGE_GUID \
EFI_GUID(0x7d6dc310, 0x52ca, 0x43b8, 0xb7, 0xb9, \
0xf9, 0xd6, 0xc5, 0x01, 0xd1, 0x08)
@@ -64,10 +50,6 @@
0x33, 0xe0, 0xb9, 0x16, 0xf3, 0x98)
#endif
-#define DEVELOPERBOX_OPTEE_IMAGE_GUID \
- EFI_GUID(0xc1b629f1, 0xce0e, 0x4894, 0x82, 0xbf, \
- 0xf0, 0xa3, 0x83, 0x87, 0xe6, 0x30)
-
/* Distro boot settings */
#ifdef CONFIG_CMD_USB
#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0)
@@ -107,7 +89,6 @@
"ramdisk_addr_r=0xa0000000\0" \
"scriptaddr=0x88000000\0" \
"pxefile_addr_r=0x88100000\0" \
- DEFAULT_DFU_ALT_INFO \
BOOTENV
#endif /* __CONFIG_H */
diff --git a/include/configs/thuban.h b/include/configs/thuban.h
index a5913e1..f4c04c5 100644
--- a/include/configs/thuban.h
+++ b/include/configs/thuban.h
@@ -6,7 +6,7 @@
* Based on:
* U-Boot file:/include/configs/am335x_evm.h
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __CONFIG_THUBAN_H
diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h
index 20f8643..c827a9c 100644
--- a/include/configs/ti_am335x_common.h
+++ b/include/configs/ti_am335x_common.h
@@ -2,10 +2,10 @@
/*
* ti_am335x_common.h
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*
* For more details, please see the technical documents listed at
- * http://www.ti.com/product/am3359#technicaldocuments
+ * https://www.ti.com/product/am3359#technicaldocuments
*/
#ifndef __CONFIG_TI_AM335X_COMMON_H__
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index dbbeff3..3def7b1 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -2,7 +2,7 @@
/*
* ti_armv7_common.h
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*
* The various ARMv7 SoCs from TI all share a number of IP blocks when
* implementing a given feature. Rather than define these in every
@@ -200,7 +200,7 @@
#define CFG_EXTRA_ENV_SETTINGS \
BOOTENV
-#endif
+#endif /* CONFIG_DISTRO_DEFAULTS */
#endif /* CONFIG_ARM64 */
diff --git a/include/configs/ti_armv7_omap.h b/include/configs/ti_armv7_omap.h
index d34042a..0b8b1ac 100644
--- a/include/configs/ti_armv7_omap.h
+++ b/include/configs/ti_armv7_omap.h
@@ -2,7 +2,7 @@
/*
* ti_armv7_omap.h
*
- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com/
*
* The various ARMv7 SoCs from TI all share a number of IP blocks when
* implementing a given feature. This is meant to isolate the features
diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h
index 36a05b6..45f7179 100644
--- a/include/configs/ti_omap3_common.h
+++ b/include/configs/ti_omap3_common.h
@@ -2,12 +2,12 @@
/*
* ti_omap3_common.h
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*
* For more details, please see the technical documents listed at
- * http://www.ti.com/product/omap3530
- * http://www.ti.com/product/omap3630
- * http://www.ti.com/product/dm3730
+ * https://www.ti.com/product/omap3530
+ * https://www.ti.com/product/omap3630
+ * https://www.ti.com/product/dm3730
*/
#ifndef __CONFIG_TI_OMAP3_COMMON_H__
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 4e5aa74..26494ae 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -10,7 +10,7 @@
* TI OMAP5 AND DRA7XX common configuration settings
*
* For more details, please see the technical documents listed at
- * http://www.ti.com/product/omap5432
+ * https://www.ti.com/product/omap5432
*/
#ifndef __CONFIG_TI_OMAP5_COMMON_H
diff --git a/include/configs/transformer-common.h b/include/configs/transformer-common.h
index dcdda1e..3b7db0a 100644
--- a/include/configs/transformer-common.h
+++ b/include/configs/transformer-common.h
@@ -64,19 +64,14 @@
"else echo SPI flash backup FAILED! Aborting ...;" \
"poweroff; fi\0"
-#define TRANSFORMER_REFRESH_USB \
- "refresh_usb=usb start; usb reset; usb tree; usb info;" \
- "pause 'Press ANY key to return to bootmenu...'; bootmenu\0"
-
#define TRANSFORMER_BOOTMENU \
TRANSFORMER_FLASH_UBOOT \
TRANSFORMER_FLASH_SPI \
- TRANSFORMER_REFRESH_USB \
"bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \
"bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu\0" \
"bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \
"bootmenu_3=update bootloader=run flash_uboot\0" \
- "bootmenu_4=refresh USB=run refresh_usb\0" \
+ "bootmenu_4=enter console=usb start; setenv skip_boot 1; exit\0" \
"bootmenu_5=reboot RCM=enterrcm\0" \
"bootmenu_6=reboot=reset\0" \
"bootmenu_7=power off=poweroff\0" \
diff --git a/include/configs/verdin-am62.h b/include/configs/verdin-am62.h
index 7990ea8..9d2e37f 100644
--- a/include/configs/verdin-am62.h
+++ b/include/configs/verdin-am62.h
@@ -13,8 +13,7 @@
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CFG_SYS_SDRAM_BASE1 0x880000000
-#define CFG_SYS_SDRAM_SIZE SZ_2G /* Maximum supported size */
+#define CFG_SYS_SDRAM_SIZE SZ_2G /* Maximum supported size, auto-detection is used */
#define MEM_LAYOUT_ENV_SETTINGS \
"fdt_addr_r=0x90200000\0" \
@@ -46,10 +45,20 @@
"fdt_board=dev\0" \
"setup=setenv setupargs console=tty1 console=${console},${baudrate} " \
"consoleblank=0 earlycon=ns16550a,mmio32,0x02800000\0" \
- "update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \
+ "update_tiboot3=askenv confirm Did you load tiboot3.bin (y/N)?; " \
"if test \"$confirm\" = \"y\"; then " \
"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
"${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \
+ "${blkcnt}; fi\0" \
+ "update_tispl=askenv confirm Did you load tispl.bin (y/N)?; " \
+ "if test \"$confirm\" = \"y\"; then " \
+ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
+ "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x400 " \
+ "${blkcnt}; fi\0" \
+ "update_uboot=askenv confirm Did you load u-boot.img (y/N)?; " \
+ "if test \"$confirm\" = \"y\"; then " \
+ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
+ "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x1400 " \
"${blkcnt}; fi\0"
#endif /* __VERDIN_AM62_H */
diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h
index 8cb1f1a..8072d5d 100644
--- a/include/configs/verdin-imx8mm.h
+++ b/include/configs/verdin-imx8mm.h
@@ -37,7 +37,6 @@
#define CFG_EXTRA_ENV_SETTINGS \
BOOTENV \
MEM_LAYOUT_ENV_SETTINGS \
- "bootcmd_mfg=fastboot 0\0" \
"boot_file=Image\0" \
"boot_script_dhcp=boot.scr\0" \
"console=ttymxc0\0" \
diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h
index 942081a..256bab0 100644
--- a/include/configs/verdin-imx8mp.h
+++ b/include/configs/verdin-imx8mp.h
@@ -36,20 +36,13 @@
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
-#if defined(CONFIG_TDX_EASY_INSTALLER)
-# define BOOT_SCRIPT "boot-tezi.scr"
-#else
-# define BOOT_SCRIPT "boot.scr"
-#endif
-
/* Initial environment variables */
#define CFG_EXTRA_ENV_SETTINGS \
BOOTENV \
MEM_LAYOUT_ENV_SETTINGS \
- "bootcmd_mfg=fastboot 0\0" \
"boot_file=Image\0" \
- "boot_scripts=" BOOT_SCRIPT "\0" \
- "boot_script_dhcp=" BOOT_SCRIPT "\0" \
+ "boot_scripts=boot.scr\0" \
+ "boot_script_dhcp=boot.scr\0" \
"console=ttymxc2\0" \
"fdt_board=dev\0" \
"initrd_addr=0x43800000\0" \
diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h
index 43f7e45..24d8ca0 100644
--- a/include/configs/vexpress_aemv8.h
+++ b/include/configs/vexpress_aemv8.h
@@ -148,6 +148,12 @@
#define FUNC_VIRTIO(func)
#endif
+#ifdef CONFIG_CMD_MMC
+#define FUNC_MMC(func) func(MMC, mmc, 0)
+#else
+#define FUNC_MMC(func)
+#endif
+
/*
* Boot by loading an Android image, or kernel, initrd and FDT through
* semihosting into DRAM.
@@ -204,6 +210,7 @@
func(SMH, smh, na) \
func(MEM, mem, na) \
FUNC_VIRTIO(func) \
+ FUNC_MMC(func) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h
index 43050d6..eb87633 100644
--- a/include/configs/vocore2.h
+++ b/include/configs/vocore2.h
@@ -11,10 +11,6 @@
#define CFG_SYS_INIT_SP_OFFSET 0x400000
-/* SPL */
-
-#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
-
/* Dummy value */
#define CFG_SYS_UBOOT_BASE 0
diff --git a/include/configs/xenguest_arm64.h b/include/configs/xenguest_arm64.h
index bc268d2..3dce25b 100644
--- a/include/configs/xenguest_arm64.h
+++ b/include/configs/xenguest_arm64.h
@@ -14,9 +14,15 @@
#undef CFG_SYS_SDRAM_BASE
#undef CFG_EXTRA_ENV_SETTINGS
+
+#ifdef CONFIG_VIRTIO_BLK
#define CFG_EXTRA_ENV_SETTINGS \
- "loadimage=ext4load pvblock 0 0x90000000 /boot/Image;\0" \
- "pvblockboot=run loadimage;" \
+ "virtioboot=virtio scan; ext4load virtio 0 0x90000000 /boot/Image;" \
+ "booti 0x90000000 - ${fdtcontroladdr};\0"
+#else
+#define CFG_EXTRA_ENV_SETTINGS \
+ "pvblockboot=ext4load pvblock 0 0x90000000 /boot/Image;" \
"booti 0x90000000 - 0x88000000;\0"
+#endif
#endif /* __XENGUEST_ARM64_H */
diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h
index a403999..b634bb1 100644
--- a/include/configs/xilinx_versal.h
+++ b/include/configs/xilinx_versal.h
@@ -40,10 +40,11 @@
"kernel_size_r=0x10000000\0" \
"kernel_comp_addr_r=0x30000000\0" \
"kernel_comp_size=0x3C00000\0" \
- "scriptaddr=0x20000000\0" \
"ramdisk_addr_r=0x02100000\0" \
"script_size_f=0x80000\0"
+#if defined(CONFIG_DISTRO_DEFAULTS)
+
#if defined(CONFIG_MMC_SDHCI_ZYNQ)
# define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
#else
@@ -125,6 +126,10 @@
#include <config_distro_bootcmd.h>
+#else /* CONFIG_DISTRO_DEFAULTS */
+# define BOOTENV
+#endif /* CONFIG_DISTRO_DEFAULTS */
+
/* Initial environment variables */
#ifndef CFG_EXTRA_ENV_SETTINGS
#define CFG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/xilinx_versal_net.h b/include/configs/xilinx_versal_net.h
index 613cce4..2b441da 100644
--- a/include/configs/xilinx_versal_net.h
+++ b/include/configs/xilinx_versal_net.h
@@ -54,10 +54,11 @@
"kernel_size_r=0x10000000\0" \
"kernel_comp_addr_r=0x30000000\0" \
"kernel_comp_size=0x3C00000\0" \
- "scriptaddr=0x20000000\0" \
"ramdisk_addr_r=0x02100000\0" \
"script_size_f=0x80000\0"
+#if defined(CONFIG_DISTRO_DEFAULTS)
+
#if defined(CONFIG_MMC_SDHCI_ZYNQ)
# define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
#else
@@ -126,6 +127,10 @@
#include <config_distro_bootcmd.h>
+#else /* CONFIG_DISTRO_DEFAULTS */
+# define BOOTENV
+#endif /* CONFIG_DISTRO_DEFAULTS */
+
/* Initial environment variables */
#ifndef CFG_EXTRA_ENV_SETTINGS
#define CFG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 74264b7..5bc117e 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -29,7 +29,7 @@
/* Miscellaneous configurable options */
-#if defined(CONFIG_ZYNQMP_USB)
+#if defined(CONFIG_USB_STORAGE)
#define DFU_DEFAULT_POLL_TIMEOUT 300
# define PARTS_DEFAULT \
@@ -57,13 +57,14 @@
"kernel_size_r=0x10000000\0" \
"kernel_comp_addr_r=0x30000000\0" \
"kernel_comp_size=0x3C00000\0" \
- "scriptaddr=0x20000000\0" \
"ramdisk_addr_r=0x02100000\0" \
"script_size_f=0x80000\0" \
"stdin=serial\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0" \
+#if defined(CONFIG_DISTRO_DEFAULTS)
+
#if defined(CONFIG_MMC_SDHCI_ZYNQ)
# define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
#else
@@ -76,7 +77,7 @@
# define BOOT_TARGET_DEVICES_SCSI(func)
#endif
-#if defined(CONFIG_ZYNQMP_USB)
+#if defined(CONFIG_USB_STORAGE)
# define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) func(USB, usb, 1)
#else
# define BOOT_TARGET_DEVICES_USB(func)
@@ -175,6 +176,10 @@
#include <config_distro_bootcmd.h>
+#else /* CONFIG_DISTRO_DEFAULTS */
+# define BOOTENV
+#endif /* CONFIG_DISTRO_DEFAULTS */
+
/* Initial environment variables */
#ifndef CFG_EXTRA_ENV_SETTINGS
#define CFG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index e372e90..553bb1b 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -172,12 +172,10 @@
/* Default environment */
#ifndef CFG_EXTRA_ENV_SETTINGS
#define CFG_EXTRA_ENV_SETTINGS \
- "scriptaddr=0x20000\0" \
"script_size_f=0x40000\0" \
"fdt_addr_r=0x1f00000\0" \
"pxefile_addr_r=0x2000000\0" \
"kernel_addr_r=0x2000000\0" \
- "scriptaddr=0x3000000\0" \
"ramdisk_addr_r=0x3100000\0" \
BOOTENV
#endif
diff --git a/include/cpsw.h b/include/cpsw.h
index 786f8b3..5e05099 100644
--- a/include/cpsw.h
+++ b/include/cpsw.h
@@ -1,7 +1,7 @@
/*
* CPSW Ethernet Switch Driver
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/include/cpu.h b/include/cpu.h
index be02a16..2077ff3 100644
--- a/include/cpu.h
+++ b/include/cpu.h
@@ -7,6 +7,8 @@
#ifndef __CPU_H
#define __CPU_H
+#include <linux/types.h>
+
struct udevice;
/**
diff --git a/include/crypto/pkcs7_parser.h b/include/crypto/pkcs7_parser.h
index 906033a..2c45cce 100644
--- a/include/crypto/pkcs7_parser.h
+++ b/include/crypto/pkcs7_parser.h
@@ -11,6 +11,7 @@
#include <linux/oid_registry.h>
#include <crypto/pkcs7.h>
#include <crypto/x509_parser.h>
+#include <linux/printk.h>
#define kenter(FMT, ...) \
pr_devel("==> %s("FMT")\n", __func__, ##__VA_ARGS__)
diff --git a/include/dm/device.h b/include/dm/device.h
index e54cb6b..add67f9 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -1005,7 +1005,8 @@
*/
static inline bool device_is_on_pci_bus(const struct udevice *dev)
{
- return dev->parent && device_get_uclass_id(dev->parent) == UCLASS_PCI;
+ return CONFIG_IS_ENABLED(PCI) && dev->parent &&
+ device_get_uclass_id(dev->parent) == UCLASS_PCI;
}
/**
diff --git a/include/dm/device_compat.h b/include/dm/device_compat.h
index 82d7a7d..aa9a6fb 100644
--- a/include/dm/device_compat.h
+++ b/include/dm/device_compat.h
@@ -14,6 +14,7 @@
#include <log.h>
#include <linux/build_bug.h>
#include <linux/compat.h>
+#include <linux/printk.h>
/*
* Define a new identifier which can be tested on by C code. A similar
diff --git a/include/dm/fdtaddr.h b/include/dm/fdtaddr.h
index dcdc191..bf8132d 100644
--- a/include/dm/fdtaddr.h
+++ b/include/dm/fdtaddr.h
@@ -19,7 +19,7 @@
*
* @dev: Pointer to a device
*
- * Return: addr
+ * Return: Address, or FDT_ADDR_T_NONE if there is no such property
*/
fdt_addr_t devfdt_get_addr(const struct udevice *dev);
@@ -59,7 +59,7 @@
* devfdt_remap_addr_name() - Get the reg property of a device, indexed by
* name, as a memory-mapped I/O pointer
* @name: the 'reg' property can hold a list of <addr, size> pairs, with the
- * 'reg-names' property providing named-based identification. @index
+ * 'reg-names' property providing named-based identification. @name
* indicates the value to search for in 'reg-names'.
*
* @dev: Pointer to a device
@@ -87,7 +87,7 @@
* @index: the 'reg' property can hold a list of <addr, size> pairs
* and @index is used to select which one is required
*
- * Return: addr
+ * Return: Address, or FDT_ADDR_T_NONE if there is no such property
*/
fdt_addr_t devfdt_get_addr_index(const struct udevice *dev, int index);
@@ -114,7 +114,7 @@
* @size: Pointer to size variable - this function returns the size
* specified in the 'reg' property here
*
- * Return: addr
+ * Return: Address, or FDT_ADDR_T_NONE if there is no such property
*/
fdt_addr_t devfdt_get_addr_size_index(const struct udevice *dev, int index,
fdt_size_t *size);
@@ -139,14 +139,27 @@
*
* @dev: Pointer to a device
* @name: the 'reg' property can hold a list of <addr, size> pairs, with the
- * 'reg-names' property providing named-based identification. @index
+ * 'reg-names' property providing named-based identification. @name
* indicates the value to search for in 'reg-names'.
*
- * Return: addr
+ * Return: Address, or FDT_ADDR_T_NONE if there is no such property
*/
fdt_addr_t devfdt_get_addr_name(const struct udevice *dev, const char *name);
/**
+ * devfdt_get_addr_name_ptr() - Get the reg property of a device as a pointer,
+ * indexed by name
+ *
+ * @dev: Pointer to a device
+ * @name: the 'reg' property can hold a list of <addr, size> pairs, with the
+ * 'reg-names' property providing named-based identification. @name
+ * indicates the value to search for in 'reg-names'.
+ *
+ * Return: Pointer to addr, or NULL if there is no such property
+ */
+void *devfdt_get_addr_name_ptr(const struct udevice *dev, const char *name);
+
+/**
* devfdt_get_addr_size_name() - Get the reg property and its size for a device,
* indexed by name
*
@@ -154,22 +167,41 @@
*
* @dev: Pointer to a device
* @name: the 'reg' property can hold a list of <addr, size> pairs, with the
- * 'reg-names' property providing named-based identification. @index
+ * 'reg-names' property providing named-based identification. @name
* indicates the value to search for in 'reg-names'.
* @size: Pointer to size variable - this function returns the size
* specified in the 'reg' property here
*
- * Return: addr
+ * Return: Address, or FDT_ADDR_T_NONE if there is no such property
*/
fdt_addr_t devfdt_get_addr_size_name(const struct udevice *dev,
const char *name, fdt_size_t *size);
/**
+ * devfdt_get_addr_size_name_ptr() - Get the reg property for a device as a
+ * pointer, indexed by name
+ *
+ * Returns the address and size specified in the 'reg' property of a device.
+ *
+ * @dev: Pointer to a device
+ * @name: the 'reg' property can hold a list of <addr, size> pairs, with the
+ * 'reg-names' property providing named-based identification. @name
+ * indicates the value to search for in 'reg-names'.
+ * @size: Pointer to size variable - this function returns the size
+ * specified in the 'reg' property here
+ *
+ * Return: Pointer to addr, or NULL if there is no such property
+ */
+void *devfdt_get_addr_size_name_ptr(const struct udevice *dev,
+ const char *name, fdt_size_t *size);
+
+/**
* devfdt_get_addr_pci() - Read an address and handle PCI address translation
*
* @dev: Device to read from
+ * @sizep: If non-NULL, returns size of address space
* Return: address or FDT_ADDR_T_NONE if not found
*/
-fdt_addr_t devfdt_get_addr_pci(const struct udevice *dev);
+fdt_addr_t devfdt_get_addr_pci(const struct udevice *dev, fdt_size_t *sizep);
#endif
diff --git a/include/dm/of_access.h b/include/dm/of_access.h
index c556a18..de740d4 100644
--- a/include/dm/of_access.h
+++ b/include/dm/of_access.h
@@ -334,6 +334,25 @@
int index, u32 *outp);
/**
+ * of_read_u64_index() - Find and read a 64-bit value from a multi-value
+ * property
+ *
+ * @np: device node from which the property value is to be read.
+ * @propname: name of the property to be searched.
+ * @index: index of the u32 in the list of values
+ * @outp: pointer to return value, modified only if return value is 0.
+ *
+ * Search for a property in a device node and read a 64-bit value from
+ * it.
+ *
+ * Return:
+ * 0 on success, -EINVAL if the property does not exist, or -EOVERFLOW if the
+ * property data isn't large enough.
+ */
+int of_read_u64_index(const struct device_node *np, const char *propname,
+ int index, u64 *outp);
+
+/**
* of_read_u64() - Find and read a 64-bit integer from a property
*
* Search for a property in a device node and read a 64-bit value from
@@ -578,4 +597,22 @@
int of_add_subnode(struct device_node *node, const char *name, int len,
struct device_node **subnodep);
+/**
+ * of_remove_property() - Remove a property from a node
+ *
+ * @np: Node to remove from
+ * @prop: Pointer to property to remove
+ * Return 0 if OK, -ENODEV if the property could not be found in the node
+ */
+int of_remove_property(struct device_node *np, struct property *prop);
+
+/**
+ * of_remove_node() - Remove a node from the tree
+ *
+ * @to_remove: Node to remove
+ * Return: 0 if OK, -EPERM if it is the root node (wWhich cannot be removed),
+ * -ENOENT if the tree is broken (to_remove is not a child of its parent)
+ */
+int of_remove_node(struct device_node *to_remove);
+
#endif
diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index 0f38b3e..5795115 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -17,9 +17,11 @@
/* Enable checks to protect against invalid calls */
#undef OF_CHECKS
+struct abuf;
struct resource;
#include <dm/ofnode_decl.h>
+#include <linux/errno.h>
struct ofnode_phandle_args {
ofnode node;
@@ -127,6 +129,27 @@
#endif /* OFNODE_MULTI_TREE */
/**
+ * oftree_new() - Create a new, empty tree
+ *
+ * @treep: Returns a pointer to the tree, on success
+ * Returns: 0 on success, -ENOMEM if out of memory, -E2BIG if !OF_LIVE and
+ * there are too many (flattrees) already
+ */
+int oftree_new(oftree *treep);
+
+/**
+ * oftree_to_fdt() - Convert an oftree to a flat FDT
+ *
+ * @tree: tree to flatten (if livetree) or copy (if not)
+ * @buf: Returns inited buffer containing the newly created flat tree. Note
+ * that for flat tree the buffer is not allocated. In either case the caller
+ * must call abut_uninit() to free any memory used by @buf
+ * Return: 0 on success, -ENOMEM if out of memory, other -ve value for any other
+ * error
+ */
+int oftree_to_fdt(oftree tree, struct abuf *buf);
+
+/**
* ofnode_to_np() - convert an ofnode to a live DT node pointer
*
* This cannot be called if the reference contains an offset.
@@ -435,6 +458,18 @@
u32 *outp);
/**
+ * ofnode_read_u64_index() - Read a 64-bit integer from a multi-value property
+ *
+ * @node: valid node reference to read property from
+ * @propname: name of the property to read from
+ * @index: index of the integer to return
+ * @outp: place to put value (if found)
+ * Return: 0 if OK, -ve on error
+ */
+int ofnode_read_u64_index(ofnode node, const char *propname, int index,
+ u64 *outp);
+
+/**
* ofnode_read_s32() - Read a 32-bit integer from a property
*
* @node: valid node reference to read property from
@@ -942,12 +977,22 @@
ofnode ofnode_get_chosen_node(const char *propname);
/**
+ * ofnode_read_baud() - get the baudrate from string value of chosen property
+ *
+ * This looks for stdout-path property within the /chosen node and parses its
+ * value to return baudrate.
+ *
+ * This only works with the control FDT.
+ *
+ * Return: baudrate value if found, else -ve error code
+ */
+int ofnode_read_baud(void);
+
+/**
* ofnode_read_aliases_prop() - get the value of a aliases property
*
* This looks for a property within the /aliases node and returns its value
*
- * This only works with the control FDT.
- *
* @propname: Property name to look for
* @sizep: Returns size of property, or `FDT_ERR_...` error code if function
* returns NULL
@@ -1002,11 +1047,20 @@
* @node: node to read
* @propname: property to read
* @lenp: place to put length on success
- * Return: pointer to property, or NULL if not found
+ * Return: pointer to property value, or NULL if not found or empty
*/
const void *ofnode_get_property(ofnode node, const char *propname, int *lenp);
/**
+ * ofnode_has_property() - check if a node has a named property
+ *
+ * @node: node to read
+ * @propname: property to read
+ * Return: true if the property exists in the node, false if not
+ */
+bool ofnode_has_property(ofnode node, const char *propname);
+
+/**
* ofnode_first_property()- get the reference of the first property
*
* Get reference to the first property of the node, it is used to iterate
@@ -1109,13 +1163,15 @@
* @type: pci address type (FDT_PCI_SPACE_xxx)
* @propname: name of property to find
* @addr: returns pci address in the form of fdt_pci_addr
+ * @size: if non-null, returns register-space size
* Return:
* 0 if ok, -ENOENT if the property did not exist, -EINVAL if the
* format of the property was invalid, -ENXIO if the requested
* address type was not found
*/
int ofnode_read_pci_addr(ofnode node, enum fdt_pci_space type,
- const char *propname, struct fdt_pci_addr *addr);
+ const char *propname, struct fdt_pci_addr *addr,
+ fdt_size_t *size);
/**
* ofnode_read_pci_vendev() - look up PCI vendor and device id
@@ -1198,15 +1254,15 @@
* determine if a node was bound in one of SPL/TPL stages.
*
* There are 4 settings currently in use
- * - bootph-some-ram: U-Boot proper pre-relocation only
+ * - bootph-some-ram: U-Boot proper pre-relocation phase
* - bootph-all: all phases
* Existing platforms only use it to indicate nodes needed in
* SPL. Should probably be replaced by bootph-pre-ram for new platforms.
- * - bootph-pre-ram: SPL and U-Boot pre-relocation
- * - bootph-pre-sram: TPL and U-Boot pre-relocation
+ * - bootph-pre-ram: SPL phase
+ * - bootph-pre-sram: TPL phase
*
* @node: node to check
- * Return: true if node is needed in SPL/TL, false otherwise
+ * Return: true if node should be or was bound, false otherwise
*/
bool ofnode_pre_reloc(ofnode node);
@@ -1418,6 +1474,37 @@
int ofnode_write_u32(ofnode node, const char *propname, u32 value);
/**
+ * ofnode_write_u64() - Set an integer property of an ofnode
+ *
+ * @node: The node for whose string property should be set
+ * @propname: The name of the string property to set
+ * @value: The new value of the 64-bit integer property
+ * Return: 0 if successful, -ve on error
+ */
+int ofnode_write_u64(ofnode node, const char *propname, u64 value);
+
+/**
+ * ofnode_write_bool() - Set a boolean property of an ofnode
+ *
+ * This either adds or deleted a property with a zero-length value
+ *
+ * @node: The node for whose string property should be set
+ * @propname: The name of the string property to set
+ * @value: The new value of the boolean property
+ * Return: 0 if successful, -ve on error
+ */
+int ofnode_write_bool(ofnode node, const char *propname, bool value);
+
+/**
+ * ofnode_delete_prop() - Delete a property
+ *
+ * @node: Node containing the property to delete
+ * @propname: Name of property to delete
+ * Return: 0 if successful, -ve on error
+ */
+int ofnode_delete_prop(ofnode node, const char *propname);
+
+/**
* ofnode_set_enabled() - Enable or disable a device tree node given by its
* ofnode
*
@@ -1500,6 +1587,47 @@
*/
const char *ofnode_conf_read_str(const char *prop_name);
+/**
+ * ofnode_read_bootscript_address() - Read bootscr-address or bootscr-ram-offset
+ *
+ * @bootscr_address: pointer to 64bit address where bootscr-address property value
+ * is stored
+ * @bootscr_offset: pointer to 64bit offset address where bootscr-ram-offset
+ * property value is stored
+ *
+ * This reads a bootscr-address or bootscr-ram-offset property from
+ * the /options/u-boot/ node of the devicetree. bootscr-address holds the full
+ * address of the boot script file. bootscr-ram-offset holds the boot script
+ * file offset from the start of the ram base address. When bootscr-address is
+ * defined, bootscr-ram-offset property is ignored.
+ *
+ * This only works with the control FDT.
+ *
+ * Return: 0 if OK, -EINVAL if property is not found.
+ */
+int ofnode_read_bootscript_address(u64 *bootscr_address, u64 *bootscr_offset);
+
+/**
+ * ofnode_read_bootscript_flash() - Read bootscr-flash-offset/size
+ *
+ * @bootscr_flash_offset: pointer to 64bit offset where bootscr-flash-offset
+ * property value is stored
+ * @bootscr_flash_size: pointer to 64bit size where bootscr-flash-size property
+ * value is stored
+ *
+ * This reads a bootscr-flash-offset and bootscr-flash-size properties from
+ * the /options/u-boot/ node of the devicetree. bootscr-flash-offset holds
+ * the offset of the boot script file from start of flash. bootscr-flash-size
+ * holds the boot script size in flash. When bootscr-flash-size is not defined,
+ * bootscr-flash-offset property is cleaned.
+ *
+ * This only works with the control FDT.
+ *
+ * Return: 0 if OK, -EINVAL if property is not found or incorrect.
+ */
+int ofnode_read_bootscript_flash(u64 *bootscr_flash_offset,
+ u64 *bootscr_flash_size);
+
#else /* CONFIG_DM */
static inline bool ofnode_conf_read_bool(const char *prop_name)
{
@@ -1516,6 +1644,17 @@
return NULL;
}
+static inline int ofnode_read_bootscript_address(u64 *bootscr_address, u64 *bootscr_offset)
+{
+ return -EINVAL;
+}
+
+static inline int ofnode_read_bootscript_flash(u64 *bootscr_flash_offset,
+ u64 *bootscr_flash_size)
+{
+ return -EINVAL;
+}
+
#endif /* CONFIG_DM */
/**
@@ -1533,7 +1672,7 @@
/**
* ofnode_copy_props() - copy all properties from one node to another
*
- * Makes a copy of all properties from the source note in the destination node.
+ * Makes a copy of all properties from the source node to the destination node.
* Existing properties in the destination node remain unchanged, except that
* any with the same name are overwritten, including changing the size of the
* property.
@@ -1541,9 +1680,37 @@
* For livetree, properties are copied / allocated, so the source tree does not
* need to be present afterwards.
*
+ * @dst: Destination node to write properties to
* @src: Source node to read properties from
- * @dst: Destination node to write properties too
*/
-int ofnode_copy_props(ofnode src, ofnode dst);
+int ofnode_copy_props(ofnode dst, ofnode src);
+
+/**
+ * ofnode_copy_node() - Copy a node to another place
+ *
+ * If a node with this name already exists in dst_parent, this returns an
+ * .error
+ *
+ * @dst_parent: Parent of the newly copied node
+ * @name: Name to give the new node
+ * @src: Source node to copy
+ * @nodep: Returns the new node, or the existing node if there is one
+ * Return: 0 if OK, -EEXIST if dst_parent already has a node with this parent
+ */
+int ofnode_copy_node(ofnode dst_parent, const char *name, ofnode src,
+ ofnode *nodep);
+
+/**
+ * ofnode_delete() - Delete a node
+ *
+ * Delete a node from the tree
+ *
+ * @nodep: Pointer to node to delete (set to ofnode_null() on success)
+ * Return: 0 if OK, -ENOENT if the node does not exist, -EPERM if it is the root
+ * node (wWhich cannot be removed), -EFAULT if the tree is broken (to_remove is
+ * not a child of its parent),
+ *
+ */
+int ofnode_delete(ofnode *nodep);
#endif
diff --git a/include/dm/pinctrl.h b/include/dm/pinctrl.h
index e3e50afe..70d8cc5 100644
--- a/include/dm/pinctrl.h
+++ b/include/dm/pinctrl.h
@@ -7,7 +7,7 @@
#define __PINCTRL_H
#define PINNAME_SIZE 10
-#define PINMUX_SIZE 80
+#define PINMUX_SIZE 90
/**
* struct pinconf_param - pin config parameters
diff --git a/include/dm/read.h b/include/dm/read.h
index c2615f7..894bc69 100644
--- a/include/dm/read.h
+++ b/include/dm/read.h
@@ -277,7 +277,7 @@
*
* @dev: Device to read from
* @name: the 'reg' property can hold a list of <addr, size> pairs, with the
- * 'reg-names' property providing named-based identification. @index
+ * 'reg-names' property providing named-based identification. @name
* indicates the value to search for in 'reg-names'.
*
* Return: address or FDT_ADDR_T_NONE if not found
@@ -285,11 +285,24 @@
fdt_addr_t dev_read_addr_name(const struct udevice *dev, const char *name);
/**
+ * dev_read_addr_name_ptr() - Get the reg property of a device as a pointer,
+ * indexed by name
+ *
+ * @dev: Device to read from
+ * @name: the 'reg' property can hold a list of <addr, size> pairs, with the
+ * 'reg-names' property providing named-based identification. @name
+ * indicates the value to search for in 'reg-names'.
+ *
+ * Return: pointer or NULL if not found
+ */
+void *dev_read_addr_name_ptr(const struct udevice *dev, const char *name);
+
+/**
* dev_read_addr_size_name() - Get the reg property of a device, indexed by name
*
* @dev: Device to read from
* @name: the 'reg' property can hold a list of <addr, size> pairs, with the
- * 'reg-names' property providing named-based identification. @index
+ * 'reg-names' property providing named-based identification. @name
* indicates the value to search for in 'reg-names'.
* @size: place to put size value (on success)
*
@@ -299,12 +312,27 @@
fdt_size_t *size);
/**
+ * dev_read_addr_size_name_ptr() - Get the reg property of a device as a pointer,
+ * indexed by name
+ *
+ * @dev: Device to read from
+ * @name: the 'reg' property can hold a list of <addr, size> pairs, with the
+ * 'reg-names' property providing named-based identification. @name
+ * indicates the value to search for in 'reg-names'.
+ * @size: place to put size value (on success)
+ *
+ * Return: pointer or NULL if not found
+ */
+void *dev_read_addr_size_name_ptr(const struct udevice *dev, const char *name,
+ fdt_size_t *size);
+
+/**
* dev_remap_addr_name() - Get the reg property of a device, indexed by name,
* as a memory-mapped I/O pointer
*
* @dev: Device to read from
* @name: the 'reg' property can hold a list of <addr, size> pairs, with the
- * 'reg-names' property providing named-based identification. @index
+ * 'reg-names' property providing named-based identification. @name
* indicates the value to search for in 'reg-names'.
*
* Return: pointer or NULL if not found
@@ -346,9 +374,10 @@
* fdtdec_get_addr() and friends.
*
* @dev: Device to read from
+ * @sizep: If non-NULL, returns size of address space found
* Return: address or FDT_ADDR_T_NONE if not found
*/
-fdt_addr_t dev_read_addr_pci(const struct udevice *dev);
+fdt_addr_t dev_read_addr_pci(const struct udevice *dev, fdt_size_t *sizep);
/**
* dev_remap_addr() - Get the reg property of a device as a
@@ -979,6 +1008,12 @@
return devfdt_get_addr_name(dev, name);
}
+static inline void *dev_read_addr_name_ptr(const struct udevice *dev,
+ const char *name)
+{
+ return devfdt_get_addr_name_ptr(dev, name);
+}
+
static inline fdt_addr_t dev_read_addr_size_name(const struct udevice *dev,
const char *name,
fdt_size_t *size)
@@ -986,6 +1021,13 @@
return devfdt_get_addr_size_name(dev, name, size);
}
+static inline void *dev_read_addr_size_name_ptr(const struct udevice *dev,
+ const char *name,
+ fdt_size_t *size)
+{
+ return devfdt_get_addr_size_name_ptr(dev, name, size);
+}
+
static inline fdt_addr_t dev_read_addr(const struct udevice *dev)
{
return devfdt_get_addr(dev);
@@ -996,9 +1038,10 @@
return devfdt_get_addr_ptr(dev);
}
-static inline fdt_addr_t dev_read_addr_pci(const struct udevice *dev)
+static inline fdt_addr_t dev_read_addr_pci(const struct udevice *dev,
+ fdt_size_t *sizep)
{
- return devfdt_get_addr_pci(dev);
+ return devfdt_get_addr_pci(dev, sizep);
}
static inline void *dev_remap_addr(const struct udevice *dev)
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 0432c95..5271e64 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -89,6 +89,7 @@
UCLASS_MDIO, /* MDIO bus */
UCLASS_MDIO_MUX, /* MDIO MUX/switch */
UCLASS_MEMORY, /* Memory Controller device */
+ UCLASS_SM, /* Secure Monitor driver */
UCLASS_MISC, /* Miscellaneous device */
UCLASS_MMC, /* SD / MMC card or chip */
UCLASS_MOD_EXP, /* RSA Mod Exp device */
@@ -120,9 +121,11 @@
UCLASS_REGULATOR, /* Regulator device */
UCLASS_REMOTEPROC, /* Remote Processor device */
UCLASS_RESET, /* Reset controller device */
+ UCLASS_RKMTD, /* Rockchip MTD device */
UCLASS_RNG, /* Random Number Generator */
UCLASS_RTC, /* Real time clock device */
UCLASS_SCMI_AGENT, /* Interface with an SCMI server */
+ UCLASS_SCMI_BASE, /* Interface for SCMI Base protocol */
UCLASS_SCSI, /* SCSI device */
UCLASS_SERIAL, /* Serial UART */
UCLASS_SIMPLE_BUS, /* Bus with child devices */
diff --git a/include/dm/util.h b/include/dm/util.h
index 4bb49e9..95c3527 100644
--- a/include/dm/util.h
+++ b/include/dm/util.h
@@ -11,9 +11,7 @@
#if CONFIG_IS_ENABLED(DM_WARN)
#define dm_warn(fmt...) log(LOGC_DM, LOGL_WARNING, ##fmt)
#else
-static inline void dm_warn(const char *fmt, ...)
-{
-}
+#define dm_warn(fmt...) log(LOGC_DM, LOGL_DEBUG, ##fmt)
#endif
struct list_head;
@@ -27,14 +25,21 @@
int list_count_items(struct list_head *head);
/**
- * Dump out a tree of all devices
+ * Dump out a tree of all devices starting @uclass
*
+ * @dev_name: udevice name
+ * @extended: true if forword-matching expected
* @sort: Sort by uclass name
*/
-void dm_dump_tree(bool sort);
+void dm_dump_tree(char *dev_name, bool extended, bool sort);
-/* Dump out a list of uclasses and their devices */
-void dm_dump_uclass(void);
+/*
+ * Dump out a list of uclasses and their devices
+ *
+ * @uclass: uclass name
+ * @extended: true if forword-matching expected
+ */
+void dm_dump_uclass(char *uclass, bool extended);
#ifdef CONFIG_DEBUG_DEVRES
/* Dump out a list of device resources */
diff --git a/include/dt-bindings/ata/ahci.h b/include/dt-bindings/ata/ahci.h
new file mode 100644
index 0000000..b3f3b7c
--- /dev/null
+++ b/include/dt-bindings/ata/ahci.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * This header provides constants for most AHCI bindings.
+ */
+
+#ifndef _DT_BINDINGS_ATA_AHCI_H
+#define _DT_BINDINGS_ATA_AHCI_H
+
+/* Host Bus Adapter generic platform capabilities */
+#define HBA_SSS (1 << 27)
+#define HBA_SMPS (1 << 28)
+
+/* Host Bus Adapter port-specific platform capabilities */
+#define HBA_PORT_HPCP (1 << 18)
+#define HBA_PORT_MPSP (1 << 19)
+#define HBA_PORT_CPD (1 << 20)
+#define HBA_PORT_ESP (1 << 21)
+#define HBA_PORT_FBSCP (1 << 22)
+
+#endif
diff --git a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
new file mode 100644
index 0000000..06f198e
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
@@ -0,0 +1,168 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ * Author: Jian Hu <jian.hu@amlogic.com>
+ *
+ * Copyright (c) 2023, SberDevices. All Rights Reserved.
+ * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
+ */
+
+#ifndef __A1_PERIPHERALS_CLKC_H
+#define __A1_PERIPHERALS_CLKC_H
+
+#define CLKID_XTAL_IN 0
+#define CLKID_FIXPLL_IN 1
+#define CLKID_USB_PHY_IN 2
+#define CLKID_USB_CTRL_IN 3
+#define CLKID_HIFIPLL_IN 4
+#define CLKID_SYSPLL_IN 5
+#define CLKID_DDS_IN 6
+#define CLKID_SYS 7
+#define CLKID_CLKTREE 8
+#define CLKID_RESET_CTRL 9
+#define CLKID_ANALOG_CTRL 10
+#define CLKID_PWR_CTRL 11
+#define CLKID_PAD_CTRL 12
+#define CLKID_SYS_CTRL 13
+#define CLKID_TEMP_SENSOR 14
+#define CLKID_AM2AXI_DIV 15
+#define CLKID_SPICC_B 16
+#define CLKID_SPICC_A 17
+#define CLKID_MSR 18
+#define CLKID_AUDIO 19
+#define CLKID_JTAG_CTRL 20
+#define CLKID_SARADC_EN 21
+#define CLKID_PWM_EF 22
+#define CLKID_PWM_CD 23
+#define CLKID_PWM_AB 24
+#define CLKID_CEC 25
+#define CLKID_I2C_S 26
+#define CLKID_IR_CTRL 27
+#define CLKID_I2C_M_D 28
+#define CLKID_I2C_M_C 29
+#define CLKID_I2C_M_B 30
+#define CLKID_I2C_M_A 31
+#define CLKID_ACODEC 32
+#define CLKID_OTP 33
+#define CLKID_SD_EMMC_A 34
+#define CLKID_USB_PHY 35
+#define CLKID_USB_CTRL 36
+#define CLKID_SYS_DSPB 37
+#define CLKID_SYS_DSPA 38
+#define CLKID_DMA 39
+#define CLKID_IRQ_CTRL 40
+#define CLKID_NIC 41
+#define CLKID_GIC 42
+#define CLKID_UART_C 43
+#define CLKID_UART_B 44
+#define CLKID_UART_A 45
+#define CLKID_SYS_PSRAM 46
+#define CLKID_RSA 47
+#define CLKID_CORESIGHT 48
+#define CLKID_AM2AXI_VAD 49
+#define CLKID_AUDIO_VAD 50
+#define CLKID_AXI_DMC 51
+#define CLKID_AXI_PSRAM 52
+#define CLKID_RAMB 53
+#define CLKID_RAMA 54
+#define CLKID_AXI_SPIFC 55
+#define CLKID_AXI_NIC 56
+#define CLKID_AXI_DMA 57
+#define CLKID_CPU_CTRL 58
+#define CLKID_ROM 59
+#define CLKID_PROC_I2C 60
+#define CLKID_DSPA_SEL 61
+#define CLKID_DSPB_SEL 62
+#define CLKID_DSPA_EN 63
+#define CLKID_DSPA_EN_NIC 64
+#define CLKID_DSPB_EN 65
+#define CLKID_DSPB_EN_NIC 66
+#define CLKID_RTC 67
+#define CLKID_CECA_32K 68
+#define CLKID_CECB_32K 69
+#define CLKID_24M 70
+#define CLKID_12M 71
+#define CLKID_FCLK_DIV2_DIVN 72
+#define CLKID_GEN 73
+#define CLKID_SARADC_SEL 74
+#define CLKID_SARADC 75
+#define CLKID_PWM_A 76
+#define CLKID_PWM_B 77
+#define CLKID_PWM_C 78
+#define CLKID_PWM_D 79
+#define CLKID_PWM_E 80
+#define CLKID_PWM_F 81
+#define CLKID_SPICC 82
+#define CLKID_TS 83
+#define CLKID_SPIFC 84
+#define CLKID_USB_BUS 85
+#define CLKID_SD_EMMC 86
+#define CLKID_PSRAM 87
+#define CLKID_DMC 88
+#define CLKID_SYS_A_SEL 89
+#define CLKID_SYS_A_DIV 90
+#define CLKID_SYS_A 91
+#define CLKID_SYS_B_SEL 92
+#define CLKID_SYS_B_DIV 93
+#define CLKID_SYS_B 94
+#define CLKID_DSPA_A_SEL 95
+#define CLKID_DSPA_A_DIV 96
+#define CLKID_DSPA_A 97
+#define CLKID_DSPA_B_SEL 98
+#define CLKID_DSPA_B_DIV 99
+#define CLKID_DSPA_B 100
+#define CLKID_DSPB_A_SEL 101
+#define CLKID_DSPB_A_DIV 102
+#define CLKID_DSPB_A 103
+#define CLKID_DSPB_B_SEL 104
+#define CLKID_DSPB_B_DIV 105
+#define CLKID_DSPB_B 106
+#define CLKID_RTC_32K_IN 107
+#define CLKID_RTC_32K_DIV 108
+#define CLKID_RTC_32K_XTAL 109
+#define CLKID_RTC_32K_SEL 110
+#define CLKID_CECB_32K_IN 111
+#define CLKID_CECB_32K_DIV 112
+#define CLKID_CECB_32K_SEL_PRE 113
+#define CLKID_CECB_32K_SEL 114
+#define CLKID_CECA_32K_IN 115
+#define CLKID_CECA_32K_DIV 116
+#define CLKID_CECA_32K_SEL_PRE 117
+#define CLKID_CECA_32K_SEL 118
+#define CLKID_DIV2_PRE 119
+#define CLKID_24M_DIV2 120
+#define CLKID_GEN_SEL 121
+#define CLKID_GEN_DIV 122
+#define CLKID_SARADC_DIV 123
+#define CLKID_PWM_A_SEL 124
+#define CLKID_PWM_A_DIV 125
+#define CLKID_PWM_B_SEL 126
+#define CLKID_PWM_B_DIV 127
+#define CLKID_PWM_C_SEL 128
+#define CLKID_PWM_C_DIV 129
+#define CLKID_PWM_D_SEL 130
+#define CLKID_PWM_D_DIV 131
+#define CLKID_PWM_E_SEL 132
+#define CLKID_PWM_E_DIV 133
+#define CLKID_PWM_F_SEL 134
+#define CLKID_PWM_F_DIV 135
+#define CLKID_SPICC_SEL 136
+#define CLKID_SPICC_DIV 137
+#define CLKID_SPICC_SEL2 138
+#define CLKID_TS_DIV 139
+#define CLKID_SPIFC_SEL 140
+#define CLKID_SPIFC_DIV 141
+#define CLKID_SPIFC_SEL2 142
+#define CLKID_USB_BUS_SEL 143
+#define CLKID_USB_BUS_DIV 144
+#define CLKID_SD_EMMC_SEL 145
+#define CLKID_SD_EMMC_DIV 146
+#define CLKID_SD_EMMC_SEL2 147
+#define CLKID_PSRAM_SEL 148
+#define CLKID_PSRAM_DIV 149
+#define CLKID_PSRAM_SEL2 150
+#define CLKID_DMC_SEL 151
+#define CLKID_DMC_DIV 152
+#define CLKID_DMC_SEL2 153
+
+#endif /* __A1_PERIPHERALS_CLKC_H */
diff --git a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h
new file mode 100644
index 0000000..2b660c0
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ * Author: Jian Hu <jian.hu@amlogic.com>
+ *
+ * Copyright (c) 2023, SberDevices. All Rights Reserved.
+ * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
+ */
+
+#ifndef __A1_PLL_CLKC_H
+#define __A1_PLL_CLKC_H
+
+#define CLKID_FIXED_PLL_DCO 0
+#define CLKID_FIXED_PLL 1
+#define CLKID_FCLK_DIV2_DIV 2
+#define CLKID_FCLK_DIV3_DIV 3
+#define CLKID_FCLK_DIV5_DIV 4
+#define CLKID_FCLK_DIV7_DIV 5
+#define CLKID_FCLK_DIV2 6
+#define CLKID_FCLK_DIV3 7
+#define CLKID_FCLK_DIV5 8
+#define CLKID_FCLK_DIV7 9
+#define CLKID_HIFI_PLL 10
+
+#endif /* __A1_PLL_CLKC_H */
diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h
index 8e02859..35a1f62 100644
--- a/include/dt-bindings/clock/imx93-clock.h
+++ b/include/dt-bindings/clock/imx93-clock.h
@@ -199,6 +199,10 @@
#define IMX93_CLK_MU1_B_GATE 194
#define IMX93_CLK_MU2_A_GATE 195
#define IMX93_CLK_MU2_B_GATE 196
-#define IMX93_CLK_END 197
+#define IMX93_CLK_NIC_AXI 197
+#define IMX93_CLK_ARM_PLL 198
+#define IMX93_CLK_A55_SEL 199
+#define IMX93_CLK_A55_CORE 200
+#define IMX93_CLK_END 201
#endif
diff --git a/include/dt-bindings/clock/r8a779f0-cpg-mssr.h b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h
index f2ae1c6..c34be56 100644
--- a/include/dt-bindings/clock/r8a779f0-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h
new file mode 100644
index 0000000..0bb17ff
--- /dev/null
+++ b/include/dt-bindings/clock/r9a07g044-cpg.h
@@ -0,0 +1,220 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
+#define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A07G044 CPG Core Clocks */
+#define R9A07G044_CLK_I 0
+#define R9A07G044_CLK_I2 1
+#define R9A07G044_CLK_G 2
+#define R9A07G044_CLK_S0 3
+#define R9A07G044_CLK_S1 4
+#define R9A07G044_CLK_SPI0 5
+#define R9A07G044_CLK_SPI1 6
+#define R9A07G044_CLK_SD0 7
+#define R9A07G044_CLK_SD1 8
+#define R9A07G044_CLK_M0 9
+#define R9A07G044_CLK_M1 10
+#define R9A07G044_CLK_M2 11
+#define R9A07G044_CLK_M3 12
+#define R9A07G044_CLK_M4 13
+#define R9A07G044_CLK_HP 14
+#define R9A07G044_CLK_TSU 15
+#define R9A07G044_CLK_ZT 16
+#define R9A07G044_CLK_P0 17
+#define R9A07G044_CLK_P1 18
+#define R9A07G044_CLK_P2 19
+#define R9A07G044_CLK_AT 20
+#define R9A07G044_OSCCLK 21
+#define R9A07G044_CLK_P0_DIV2 22
+
+/* R9A07G044 Module Clocks */
+#define R9A07G044_CA55_SCLK 0
+#define R9A07G044_CA55_PCLK 1
+#define R9A07G044_CA55_ATCLK 2
+#define R9A07G044_CA55_GICCLK 3
+#define R9A07G044_CA55_PERICLK 4
+#define R9A07G044_CA55_ACLK 5
+#define R9A07G044_CA55_TSCLK 6
+#define R9A07G044_GIC600_GICCLK 7
+#define R9A07G044_IA55_CLK 8
+#define R9A07G044_IA55_PCLK 9
+#define R9A07G044_MHU_PCLK 10
+#define R9A07G044_SYC_CNT_CLK 11
+#define R9A07G044_DMAC_ACLK 12
+#define R9A07G044_DMAC_PCLK 13
+#define R9A07G044_OSTM0_PCLK 14
+#define R9A07G044_OSTM1_PCLK 15
+#define R9A07G044_OSTM2_PCLK 16
+#define R9A07G044_MTU_X_MCK_MTU3 17
+#define R9A07G044_POE3_CLKM_POE 18
+#define R9A07G044_GPT_PCLK 19
+#define R9A07G044_POEG_A_CLKP 20
+#define R9A07G044_POEG_B_CLKP 21
+#define R9A07G044_POEG_C_CLKP 22
+#define R9A07G044_POEG_D_CLKP 23
+#define R9A07G044_WDT0_PCLK 24
+#define R9A07G044_WDT0_CLK 25
+#define R9A07G044_WDT1_PCLK 26
+#define R9A07G044_WDT1_CLK 27
+#define R9A07G044_WDT2_PCLK 28
+#define R9A07G044_WDT2_CLK 29
+#define R9A07G044_SPI_CLK2 30
+#define R9A07G044_SPI_CLK 31
+#define R9A07G044_SDHI0_IMCLK 32
+#define R9A07G044_SDHI0_IMCLK2 33
+#define R9A07G044_SDHI0_CLK_HS 34
+#define R9A07G044_SDHI0_ACLK 35
+#define R9A07G044_SDHI1_IMCLK 36
+#define R9A07G044_SDHI1_IMCLK2 37
+#define R9A07G044_SDHI1_CLK_HS 38
+#define R9A07G044_SDHI1_ACLK 39
+#define R9A07G044_GPU_CLK 40
+#define R9A07G044_GPU_AXI_CLK 41
+#define R9A07G044_GPU_ACE_CLK 42
+#define R9A07G044_ISU_ACLK 43
+#define R9A07G044_ISU_PCLK 44
+#define R9A07G044_H264_CLK_A 45
+#define R9A07G044_H264_CLK_P 46
+#define R9A07G044_CRU_SYSCLK 47
+#define R9A07G044_CRU_VCLK 48
+#define R9A07G044_CRU_PCLK 49
+#define R9A07G044_CRU_ACLK 50
+#define R9A07G044_MIPI_DSI_PLLCLK 51
+#define R9A07G044_MIPI_DSI_SYSCLK 52
+#define R9A07G044_MIPI_DSI_ACLK 53
+#define R9A07G044_MIPI_DSI_PCLK 54
+#define R9A07G044_MIPI_DSI_VCLK 55
+#define R9A07G044_MIPI_DSI_LPCLK 56
+#define R9A07G044_LCDC_CLK_A 57
+#define R9A07G044_LCDC_CLK_P 58
+#define R9A07G044_LCDC_CLK_D 59
+#define R9A07G044_SSI0_PCLK2 60
+#define R9A07G044_SSI0_PCLK_SFR 61
+#define R9A07G044_SSI1_PCLK2 62
+#define R9A07G044_SSI1_PCLK_SFR 63
+#define R9A07G044_SSI2_PCLK2 64
+#define R9A07G044_SSI2_PCLK_SFR 65
+#define R9A07G044_SSI3_PCLK2 66
+#define R9A07G044_SSI3_PCLK_SFR 67
+#define R9A07G044_SRC_CLKP 68
+#define R9A07G044_USB_U2H0_HCLK 69
+#define R9A07G044_USB_U2H1_HCLK 70
+#define R9A07G044_USB_U2P_EXR_CPUCLK 71
+#define R9A07G044_USB_PCLK 72
+#define R9A07G044_ETH0_CLK_AXI 73
+#define R9A07G044_ETH0_CLK_CHI 74
+#define R9A07G044_ETH1_CLK_AXI 75
+#define R9A07G044_ETH1_CLK_CHI 76
+#define R9A07G044_I2C0_PCLK 77
+#define R9A07G044_I2C1_PCLK 78
+#define R9A07G044_I2C2_PCLK 79
+#define R9A07G044_I2C3_PCLK 80
+#define R9A07G044_SCIF0_CLK_PCK 81
+#define R9A07G044_SCIF1_CLK_PCK 82
+#define R9A07G044_SCIF2_CLK_PCK 83
+#define R9A07G044_SCIF3_CLK_PCK 84
+#define R9A07G044_SCIF4_CLK_PCK 85
+#define R9A07G044_SCI0_CLKP 86
+#define R9A07G044_SCI1_CLKP 87
+#define R9A07G044_IRDA_CLKP 88
+#define R9A07G044_RSPI0_CLKB 89
+#define R9A07G044_RSPI1_CLKB 90
+#define R9A07G044_RSPI2_CLKB 91
+#define R9A07G044_CANFD_PCLK 92
+#define R9A07G044_GPIO_HCLK 93
+#define R9A07G044_ADC_ADCLK 94
+#define R9A07G044_ADC_PCLK 95
+#define R9A07G044_TSU_PCLK 96
+
+/* R9A07G044 Resets */
+#define R9A07G044_CA55_RST_1_0 0
+#define R9A07G044_CA55_RST_1_1 1
+#define R9A07G044_CA55_RST_3_0 2
+#define R9A07G044_CA55_RST_3_1 3
+#define R9A07G044_CA55_RST_4 4
+#define R9A07G044_CA55_RST_5 5
+#define R9A07G044_CA55_RST_6 6
+#define R9A07G044_CA55_RST_7 7
+#define R9A07G044_CA55_RST_8 8
+#define R9A07G044_CA55_RST_9 9
+#define R9A07G044_CA55_RST_10 10
+#define R9A07G044_CA55_RST_11 11
+#define R9A07G044_CA55_RST_12 12
+#define R9A07G044_GIC600_GICRESET_N 13
+#define R9A07G044_GIC600_DBG_GICRESET_N 14
+#define R9A07G044_IA55_RESETN 15
+#define R9A07G044_MHU_RESETN 16
+#define R9A07G044_DMAC_ARESETN 17
+#define R9A07G044_DMAC_RST_ASYNC 18
+#define R9A07G044_SYC_RESETN 19
+#define R9A07G044_OSTM0_PRESETZ 20
+#define R9A07G044_OSTM1_PRESETZ 21
+#define R9A07G044_OSTM2_PRESETZ 22
+#define R9A07G044_MTU_X_PRESET_MTU3 23
+#define R9A07G044_POE3_RST_M_REG 24
+#define R9A07G044_GPT_RST_C 25
+#define R9A07G044_POEG_A_RST 26
+#define R9A07G044_POEG_B_RST 27
+#define R9A07G044_POEG_C_RST 28
+#define R9A07G044_POEG_D_RST 29
+#define R9A07G044_WDT0_PRESETN 30
+#define R9A07G044_WDT1_PRESETN 31
+#define R9A07G044_WDT2_PRESETN 32
+#define R9A07G044_SPI_RST 33
+#define R9A07G044_SDHI0_IXRST 34
+#define R9A07G044_SDHI1_IXRST 35
+#define R9A07G044_GPU_RESETN 36
+#define R9A07G044_GPU_AXI_RESETN 37
+#define R9A07G044_GPU_ACE_RESETN 38
+#define R9A07G044_ISU_ARESETN 39
+#define R9A07G044_ISU_PRESETN 40
+#define R9A07G044_H264_X_RESET_VCP 41
+#define R9A07G044_H264_CP_PRESET_P 42
+#define R9A07G044_CRU_CMN_RSTB 43
+#define R9A07G044_CRU_PRESETN 44
+#define R9A07G044_CRU_ARESETN 45
+#define R9A07G044_MIPI_DSI_CMN_RSTB 46
+#define R9A07G044_MIPI_DSI_ARESET_N 47
+#define R9A07G044_MIPI_DSI_PRESET_N 48
+#define R9A07G044_LCDC_RESET_N 49
+#define R9A07G044_SSI0_RST_M2_REG 50
+#define R9A07G044_SSI1_RST_M2_REG 51
+#define R9A07G044_SSI2_RST_M2_REG 52
+#define R9A07G044_SSI3_RST_M2_REG 53
+#define R9A07G044_SRC_RST 54
+#define R9A07G044_USB_U2H0_HRESETN 55
+#define R9A07G044_USB_U2H1_HRESETN 56
+#define R9A07G044_USB_U2P_EXL_SYSRST 57
+#define R9A07G044_USB_PRESETN 58
+#define R9A07G044_ETH0_RST_HW_N 59
+#define R9A07G044_ETH1_RST_HW_N 60
+#define R9A07G044_I2C0_MRST 61
+#define R9A07G044_I2C1_MRST 62
+#define R9A07G044_I2C2_MRST 63
+#define R9A07G044_I2C3_MRST 64
+#define R9A07G044_SCIF0_RST_SYSTEM_N 65
+#define R9A07G044_SCIF1_RST_SYSTEM_N 66
+#define R9A07G044_SCIF2_RST_SYSTEM_N 67
+#define R9A07G044_SCIF3_RST_SYSTEM_N 68
+#define R9A07G044_SCIF4_RST_SYSTEM_N 69
+#define R9A07G044_SCI0_RST 70
+#define R9A07G044_SCI1_RST 71
+#define R9A07G044_IRDA_RST 72
+#define R9A07G044_RSPI0_RST 73
+#define R9A07G044_RSPI1_RST 74
+#define R9A07G044_RSPI2_RST 75
+#define R9A07G044_CANFD_RSTP_N 76
+#define R9A07G044_CANFD_RSTC_N 77
+#define R9A07G044_GPIO_RSTN 78
+#define R9A07G044_GPIO_PORT_RESETN 79
+#define R9A07G044_GPIO_SPARE_RESETN 80
+#define R9A07G044_ADC_PRESETN 81
+#define R9A07G044_ADC_ADRST_N 82
+#define R9A07G044_TSU_PRESETN 83
+
+#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h
index 25e8cfd..0a5324b 100644
--- a/include/dt-bindings/clock/stm32mp1-clks.h
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
diff --git a/include/dt-bindings/clock/stm32mp13-clks.h b/include/dt-bindings/clock/stm32mp13-clks.h
index da4cb75..0bd7b54 100644
--- a/include/dt-bindings/clock/stm32mp13-clks.h
+++ b/include/dt-bindings/clock/stm32mp13-clks.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2020 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
diff --git a/include/dt-bindings/clock/sun20i-d1-ccu.h b/include/dt-bindings/clock/sun20i-d1-ccu.h
new file mode 100644
index 0000000..fdbfb40
--- /dev/null
+++ b/include/dt-bindings/clock/sun20i-d1-ccu.h
@@ -0,0 +1,158 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (C) 2020 huangzhenwei@allwinnertech.com
+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
+#define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
+
+#define CLK_PLL_CPUX 0
+#define CLK_PLL_DDR0 1
+#define CLK_PLL_PERIPH0_4X 2
+#define CLK_PLL_PERIPH0_2X 3
+#define CLK_PLL_PERIPH0_800M 4
+#define CLK_PLL_PERIPH0 5
+#define CLK_PLL_PERIPH0_DIV3 6
+#define CLK_PLL_VIDEO0_4X 7
+#define CLK_PLL_VIDEO0_2X 8
+#define CLK_PLL_VIDEO0 9
+#define CLK_PLL_VIDEO1_4X 10
+#define CLK_PLL_VIDEO1_2X 11
+#define CLK_PLL_VIDEO1 12
+#define CLK_PLL_VE 13
+#define CLK_PLL_AUDIO0_4X 14
+#define CLK_PLL_AUDIO0_2X 15
+#define CLK_PLL_AUDIO0 16
+#define CLK_PLL_AUDIO1 17
+#define CLK_PLL_AUDIO1_DIV2 18
+#define CLK_PLL_AUDIO1_DIV5 19
+#define CLK_CPUX 20
+#define CLK_CPUX_AXI 21
+#define CLK_CPUX_APB 22
+#define CLK_PSI_AHB 23
+#define CLK_APB0 24
+#define CLK_APB1 25
+#define CLK_MBUS 26
+#define CLK_DE 27
+#define CLK_BUS_DE 28
+#define CLK_DI 29
+#define CLK_BUS_DI 30
+#define CLK_G2D 31
+#define CLK_BUS_G2D 32
+#define CLK_CE 33
+#define CLK_BUS_CE 34
+#define CLK_VE 35
+#define CLK_BUS_VE 36
+#define CLK_BUS_DMA 37
+#define CLK_BUS_MSGBOX0 38
+#define CLK_BUS_MSGBOX1 39
+#define CLK_BUS_MSGBOX2 40
+#define CLK_BUS_SPINLOCK 41
+#define CLK_BUS_HSTIMER 42
+#define CLK_AVS 43
+#define CLK_BUS_DBG 44
+#define CLK_BUS_PWM 45
+#define CLK_BUS_IOMMU 46
+#define CLK_DRAM 47
+#define CLK_MBUS_DMA 48
+#define CLK_MBUS_VE 49
+#define CLK_MBUS_CE 50
+#define CLK_MBUS_TVIN 51
+#define CLK_MBUS_CSI 52
+#define CLK_MBUS_G2D 53
+#define CLK_MBUS_RISCV 54
+#define CLK_BUS_DRAM 55
+#define CLK_MMC0 56
+#define CLK_MMC1 57
+#define CLK_MMC2 58
+#define CLK_BUS_MMC0 59
+#define CLK_BUS_MMC1 60
+#define CLK_BUS_MMC2 61
+#define CLK_BUS_UART0 62
+#define CLK_BUS_UART1 63
+#define CLK_BUS_UART2 64
+#define CLK_BUS_UART3 65
+#define CLK_BUS_UART4 66
+#define CLK_BUS_UART5 67
+#define CLK_BUS_I2C0 68
+#define CLK_BUS_I2C1 69
+#define CLK_BUS_I2C2 70
+#define CLK_BUS_I2C3 71
+#define CLK_SPI0 72
+#define CLK_SPI1 73
+#define CLK_BUS_SPI0 74
+#define CLK_BUS_SPI1 75
+#define CLK_EMAC_25M 76
+#define CLK_BUS_EMAC 77
+#define CLK_IR_TX 78
+#define CLK_BUS_IR_TX 79
+#define CLK_BUS_GPADC 80
+#define CLK_BUS_THS 81
+#define CLK_I2S0 82
+#define CLK_I2S1 83
+#define CLK_I2S2 84
+#define CLK_I2S2_ASRC 85
+#define CLK_BUS_I2S0 86
+#define CLK_BUS_I2S1 87
+#define CLK_BUS_I2S2 88
+#define CLK_SPDIF_TX 89
+#define CLK_SPDIF_RX 90
+#define CLK_BUS_SPDIF 91
+#define CLK_DMIC 92
+#define CLK_BUS_DMIC 93
+#define CLK_AUDIO_DAC 94
+#define CLK_AUDIO_ADC 95
+#define CLK_BUS_AUDIO 96
+#define CLK_USB_OHCI0 97
+#define CLK_USB_OHCI1 98
+#define CLK_BUS_OHCI0 99
+#define CLK_BUS_OHCI1 100
+#define CLK_BUS_EHCI0 101
+#define CLK_BUS_EHCI1 102
+#define CLK_BUS_OTG 103
+#define CLK_BUS_LRADC 104
+#define CLK_BUS_DPSS_TOP 105
+#define CLK_HDMI_24M 106
+#define CLK_HDMI_CEC_32K 107
+#define CLK_HDMI_CEC 108
+#define CLK_BUS_HDMI 109
+#define CLK_MIPI_DSI 110
+#define CLK_BUS_MIPI_DSI 111
+#define CLK_TCON_LCD0 112
+#define CLK_BUS_TCON_LCD0 113
+#define CLK_TCON_TV 114
+#define CLK_BUS_TCON_TV 115
+#define CLK_TVE 116
+#define CLK_BUS_TVE_TOP 117
+#define CLK_BUS_TVE 118
+#define CLK_TVD 119
+#define CLK_BUS_TVD_TOP 120
+#define CLK_BUS_TVD 121
+#define CLK_LEDC 122
+#define CLK_BUS_LEDC 123
+#define CLK_CSI_TOP 124
+#define CLK_CSI_MCLK 125
+#define CLK_BUS_CSI 126
+#define CLK_TPADC 127
+#define CLK_BUS_TPADC 128
+#define CLK_BUS_TZMA 129
+#define CLK_DSP 130
+#define CLK_BUS_DSP_CFG 131
+#define CLK_RISCV 132
+#define CLK_RISCV_AXI 133
+#define CLK_BUS_RISCV_CFG 134
+#define CLK_FANOUT_24M 135
+#define CLK_FANOUT_12M 136
+#define CLK_FANOUT_16M 137
+#define CLK_FANOUT_25M 138
+#define CLK_FANOUT_32K 139
+#define CLK_FANOUT_27M 140
+#define CLK_FANOUT_PCLK 141
+#define CLK_FANOUT0 142
+#define CLK_FANOUT1 143
+#define CLK_FANOUT2 144
+#define CLK_BUS_CAN0 145
+#define CLK_BUS_CAN1 146
+
+#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */
diff --git a/include/dt-bindings/clock/sun20i-d1-r-ccu.h b/include/dt-bindings/clock/sun20i-d1-r-ccu.h
new file mode 100644
index 0000000..f95c170
--- /dev/null
+++ b/include/dt-bindings/clock/sun20i-d1-r-ccu.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_
+#define _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_
+
+#define CLK_R_AHB 0
+
+#define CLK_BUS_R_TIMER 2
+#define CLK_BUS_R_TWD 3
+#define CLK_BUS_R_PPU 4
+#define CLK_R_IR_RX 5
+#define CLK_BUS_R_IR_RX 6
+#define CLK_BUS_R_RTC 7
+#define CLK_BUS_R_CPUCFG 8
+
+#endif /* _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ */
diff --git a/include/dt-bindings/clock/sun50i-h6-ccu.h b/include/dt-bindings/clock/sun50i-h6-ccu.h
index a1545cd..ef9123d 100644
--- a/include/dt-bindings/clock/sun50i-h6-ccu.h
+++ b/include/dt-bindings/clock/sun50i-h6-ccu.h
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
*/
diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h
index 1191aca..6f8f01e 100644
--- a/include/dt-bindings/clock/sun50i-h616-ccu.h
+++ b/include/dt-bindings/clock/sun50i-h616-ccu.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (C) 2020 Arm Ltd.
*/
diff --git a/include/dt-bindings/clock/sun6i-rtc.h b/include/dt-bindings/clock/sun6i-rtc.h
index c845493..3bd3aa3 100644
--- a/include/dt-bindings/clock/sun6i-rtc.h
+++ b/include/dt-bindings/clock/sun6i-rtc.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
#ifndef _DT_BINDINGS_CLK_SUN6I_RTC_H_
#define _DT_BINDINGS_CLK_SUN6I_RTC_H_
diff --git a/include/dt-bindings/interrupt-controller/irqc-rzg2l.h b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h
new file mode 100644
index 0000000..34ce778
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for Renesas RZ/G2L family IRQC bindings.
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ *
+ */
+
+#ifndef __DT_BINDINGS_IRQC_RZG2L_H
+#define __DT_BINDINGS_IRQC_RZG2L_H
+
+/* NMI maps to SPI0 */
+#define RZG2L_NMI 0
+
+/* IRQ0-7 map to SPI1-8 */
+#define RZG2L_IRQ0 1
+#define RZG2L_IRQ1 2
+#define RZG2L_IRQ2 3
+#define RZG2L_IRQ3 4
+#define RZG2L_IRQ4 5
+#define RZG2L_IRQ5 6
+#define RZG2L_IRQ6 7
+#define RZG2L_IRQ7 8
+
+#endif /* __DT_BINDINGS_IRQC_RZG2L_H */
diff --git a/include/dt-bindings/leds/common.h b/include/dt-bindings/leds/common.h
index 3be89a7..9a0d33d 100644
--- a/include/dt-bindings/leds/common.h
+++ b/include/dt-bindings/leds/common.h
@@ -33,7 +33,12 @@
#define LED_COLOR_ID_MULTI 8 /* For multicolor LEDs */
#define LED_COLOR_ID_RGB 9 /* For multicolor LEDs that can do arbitrary color,
so this would include RGBW and similar */
-#define LED_COLOR_ID_MAX 10
+#define LED_COLOR_ID_PURPLE 10
+#define LED_COLOR_ID_ORANGE 11
+#define LED_COLOR_ID_PINK 12
+#define LED_COLOR_ID_CYAN 13
+#define LED_COLOR_ID_LIME 14
+#define LED_COLOR_ID_MAX 15
/* Standard LED functions */
/* Keyboard LEDs, usually it would be input4::capslock etc. */
diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h
index ba5cb74..a4e4f92 100644
--- a/include/dt-bindings/mfd/stm32f7-rcc.h
+++ b/include/dt-bindings/mfd/stm32f7-rcc.h
@@ -64,6 +64,7 @@
#define STM32F7_RCC_APB1_TIM14 8
#define STM32F7_RCC_APB1_LPTIM1 9
#define STM32F7_RCC_APB1_WWDG 11
+#define STM32F7_RCC_APB1_CAN3 13
#define STM32F7_RCC_APB1_SPI2 14
#define STM32F7_RCC_APB1_SPI3 15
#define STM32F7_RCC_APB1_SPDIFRX 16
diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h
index d3116c5..b0b1091 100644
--- a/include/dt-bindings/mux/ti-serdes.h
+++ b/include/dt-bindings/mux/ti-serdes.h
@@ -6,6 +6,14 @@
#ifndef _DT_BINDINGS_MUX_TI_SERDES
#define _DT_BINDINGS_MUX_TI_SERDES
+/*
+ * These bindings are deprecated, because they do not match the actual
+ * concept of bindings but rather contain pure constants values used only
+ * in DTS board files.
+ * Instead include the header in the DTS source directory.
+ */
+#warning "These bindings are deprecated. Instead, use the header in the DTS source directory."
+
/* J721E */
#define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0
@@ -117,4 +125,66 @@
#define J721S2_SERDES0_LANE3_USB 0x2
#define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3
+/* J784S4 */
+
+#define J784S4_SERDES0_LANE0_IP1_UNUSED 0x0
+#define J784S4_SERDES0_LANE0_PCIE1_LANE0 0x1
+#define J784S4_SERDES0_LANE0_IP3_UNUSED 0x2
+#define J784S4_SERDES0_LANE0_IP4_UNUSED 0x3
+
+#define J784S4_SERDES0_LANE1_IP1_UNUSED 0x0
+#define J784S4_SERDES0_LANE1_PCIE1_LANE1 0x1
+#define J784S4_SERDES0_LANE1_IP3_UNUSED 0x2
+#define J784S4_SERDES0_LANE1_IP4_UNUSED 0x3
+
+#define J784S4_SERDES0_LANE2_PCIE3_LANE0 0x0
+#define J784S4_SERDES0_LANE2_PCIE1_LANE2 0x1
+#define J784S4_SERDES0_LANE2_IP3_UNUSED 0x2
+#define J784S4_SERDES0_LANE2_IP4_UNUSED 0x3
+
+#define J784S4_SERDES0_LANE3_PCIE3_LANE1 0x0
+#define J784S4_SERDES0_LANE3_PCIE1_LANE3 0x1
+#define J784S4_SERDES0_LANE3_USB 0x2
+#define J784S4_SERDES0_LANE3_IP4_UNUSED 0x3
+
+#define J784S4_SERDES1_LANE0_QSGMII_LANE3 0x0
+#define J784S4_SERDES1_LANE0_PCIE0_LANE0 0x1
+#define J784S4_SERDES1_LANE0_IP3_UNUSED 0x2
+#define J784S4_SERDES1_LANE0_IP4_UNUSED 0x3
+
+#define J784S4_SERDES1_LANE1_QSGMII_LANE4 0x0
+#define J784S4_SERDES1_LANE1_PCIE0_LANE1 0x1
+#define J784S4_SERDES1_LANE1_IP3_UNUSED 0x2
+#define J784S4_SERDES1_LANE1_IP4_UNUSED 0x3
+
+#define J784S4_SERDES1_LANE2_QSGMII_LANE1 0x0
+#define J784S4_SERDES1_LANE2_PCIE0_LANE2 0x1
+#define J784S4_SERDES1_LANE2_PCIE2_LANE0 0x2
+#define J784S4_SERDES1_LANE2_IP4_UNUSED 0x3
+
+#define J784S4_SERDES1_LANE3_QSGMII_LANE2 0x0
+#define J784S4_SERDES1_LANE3_PCIE0_LANE3 0x1
+#define J784S4_SERDES1_LANE3_PCIE2_LANE1 0x2
+#define J784S4_SERDES1_LANE3_IP4_UNUSED 0x3
+
+#define J784S4_SERDES2_LANE0_QSGMII_LANE5 0x0
+#define J784S4_SERDES2_LANE0_IP2_UNUSED 0x1
+#define J784S4_SERDES2_LANE0_IP3_UNUSED 0x2
+#define J784S4_SERDES2_LANE0_IP4_UNUSED 0x3
+
+#define J784S4_SERDES2_LANE1_QSGMII_LANE6 0x0
+#define J784S4_SERDES2_LANE1_IP2_UNUSED 0x1
+#define J784S4_SERDES2_LANE1_IP3_UNUSED 0x2
+#define J784S4_SERDES2_LANE1_IP4_UNUSED 0x3
+
+#define J784S4_SERDES2_LANE2_QSGMII_LANE7 0x0
+#define J784S4_SERDES2_LANE2_QSGMII_LANE1 0x1
+#define J784S4_SERDES2_LANE2_IP3_UNUSED 0x2
+#define J784S4_SERDES2_LANE2_IP4_UNUSED 0x3
+
+#define J784S4_SERDES2_LANE3_QSGMII_LANE8 0x0
+#define J784S4_SERDES2_LANE3_QSGMII_LANE2 0x1
+#define J784S4_SERDES2_LANE3_IP3_UNUSED 0x2
+#define J784S4_SERDES2_LANE3_IP4_UNUSED 0x3
+
#endif /* _DT_BINDINGS_MUX_TI_SERDES */
diff --git a/include/dt-bindings/net/mscc-phy-vsc8531.h b/include/dt-bindings/net/mscc-phy-vsc8531.h
index 61f5287..c340437 100644
--- a/include/dt-bindings/net/mscc-phy-vsc8531.h
+++ b/include/dt-bindings/net/mscc-phy-vsc8531.h
@@ -28,13 +28,4 @@
#define VSC8531_FORCE_LED_OFF 14
#define VSC8531_FORCE_LED_ON 15
-#define VSC8531_RGMII_CLK_DELAY_0_2_NS 0
-#define VSC8531_RGMII_CLK_DELAY_0_8_NS 1
-#define VSC8531_RGMII_CLK_DELAY_1_1_NS 2
-#define VSC8531_RGMII_CLK_DELAY_1_7_NS 3
-#define VSC8531_RGMII_CLK_DELAY_2_0_NS 4
-#define VSC8531_RGMII_CLK_DELAY_2_3_NS 5
-#define VSC8531_RGMII_CLK_DELAY_2_6_NS 6
-#define VSC8531_RGMII_CLK_DELAY_3_4_NS 7
-
#endif
diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h
index b543eeb..765c385 100644
--- a/include/dt-bindings/pinctrl/dra.h
+++ b/include/dt-bindings/pinctrl/dra.h
@@ -1,7 +1,7 @@
/*
* This header provides constants for DRA pinctrl bindings.
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
* Author: Rajendra Nayak <rnayak@ti.com>
*
* This program is free software; you can redistribute it and/or modify
diff --git a/include/dt-bindings/pinctrl/rzg2l-pinctrl.h b/include/dt-bindings/pinctrl/rzg2l-pinctrl.h
new file mode 100644
index 0000000..c78ed5e
--- /dev/null
+++ b/include/dt-bindings/pinctrl/rzg2l-pinctrl.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for Renesas RZ/G2L family pinctrl bindings.
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ *
+ */
+
+#ifndef __DT_BINDINGS_RZG2L_PINCTRL_H
+#define __DT_BINDINGS_RZG2L_PINCTRL_H
+
+#define RZG2L_PINS_PER_PORT 8
+
+/*
+ * Create the pin index from its bank and position numbers and store in
+ * the upper 16 bits the alternate function identifier
+ */
+#define RZG2L_PORT_PINMUX(b, p, f) ((b) * RZG2L_PINS_PER_PORT + (p) | ((f) << 16))
+
+/* Convert a port and pin label to its global pin index */
+#define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
+
+#endif /* __DT_BINDINGS_RZG2L_PINCTRL_H */
diff --git a/include/dt-bindings/power/r8a7795-sysc.h b/include/dt-bindings/power/r8a7795-sysc.h
index eea6ad6..ff53238 100644
--- a/include/dt-bindings/power/r8a7795-sysc.h
+++ b/include/dt-bindings/power/r8a7795-sysc.h
@@ -30,7 +30,6 @@
#define R8A7795_PD_CA53_SCU 21
#define R8A7795_PD_3DG_E 22
#define R8A7795_PD_A3IR 24
-#define R8A7795_PD_A2VC0 25 /* ES1.x only */
#define R8A7795_PD_A2VC1 26
/* Always-on power area */
diff --git a/include/dt-bindings/power/r8a779f0-sysc.h b/include/dt-bindings/power/r8a779f0-sysc.h
index 0ec8ad7..cde1536 100644
--- a/include/dt-bindings/power/r8a779f0-sysc.h
+++ b/include/dt-bindings/power/r8a779f0-sysc.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
diff --git a/include/dt-bindings/regulator/st,stm32mp13-regulator.h b/include/dt-bindings/regulator/st,stm32mp13-regulator.h
new file mode 100644
index 0000000..b3a974df
--- /dev/null
+++ b/include/dt-bindings/regulator/st,stm32mp13-regulator.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef __DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H
+#define __DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H
+
+/* SCMI voltage domains identifiers */
+
+/* SOC Internal regulators */
+#define VOLTD_SCMI_REG11 0
+#define VOLTD_SCMI_REG18 1
+#define VOLTD_SCMI_USB33 2
+#define VOLTD_SCMI_SDMMC1_IO 3
+#define VOLTD_SCMI_SDMMC2_IO 4
+#define VOLTD_SCMI_VREFBUF 5
+
+/* STPMIC1 regulators */
+#define VOLTD_SCMI_STPMIC1_BUCK1 6
+#define VOLTD_SCMI_STPMIC1_BUCK2 7
+#define VOLTD_SCMI_STPMIC1_BUCK3 8
+#define VOLTD_SCMI_STPMIC1_BUCK4 9
+#define VOLTD_SCMI_STPMIC1_LDO1 10
+#define VOLTD_SCMI_STPMIC1_LDO2 11
+#define VOLTD_SCMI_STPMIC1_LDO3 12
+#define VOLTD_SCMI_STPMIC1_LDO4 13
+#define VOLTD_SCMI_STPMIC1_LDO5 14
+#define VOLTD_SCMI_STPMIC1_LDO6 15
+#define VOLTD_SCMI_STPMIC1_VREFDDR 16
+#define VOLTD_SCMI_STPMIC1_BOOST 17
+#define VOLTD_SCMI_STPMIC1_PWR_SW1 18
+#define VOLTD_SCMI_STPMIC1_PWR_SW2 19
+
+/* External regulators */
+#define VOLTD_SCMI_REGU0 20
+#define VOLTD_SCMI_REGU1 21
+#define VOLTD_SCMI_REGU2 22
+#define VOLTD_SCMI_REGU3 23
+#define VOLTD_SCMI_REGU4 24
+
+#endif /*__DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H */
diff --git a/include/dt-bindings/reset/amlogic,meson-a1-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-reset.h
new file mode 100644
index 0000000..2c749c6
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-a1-reset.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen <xingyu.chen@amlogic.com>
+ *
+ * Copyright (c) 2023, SberDevices, Inc.
+ * Author: Alexey Romanov <avromanov@salutedevices.com>
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H
+
+/* RESET0 */
+/* 0 */
+#define RESET_AM2AXI_VAD 1
+/* 2-3 */
+#define RESET_PSRAM 4
+#define RESET_PAD_CTRL 5
+/* 6 */
+#define RESET_TEMP_SENSOR 7
+#define RESET_AM2AXI_DEV 8
+/* 9 */
+#define RESET_SPICC_A 10
+#define RESET_MSR_CLK 11
+#define RESET_AUDIO 12
+#define RESET_ANALOG_CTRL 13
+#define RESET_SAR_ADC 14
+#define RESET_AUDIO_VAD 15
+#define RESET_CEC 16
+#define RESET_PWM_EF 17
+#define RESET_PWM_CD 18
+#define RESET_PWM_AB 19
+/* 20 */
+#define RESET_IR_CTRL 21
+#define RESET_I2C_S_A 22
+/* 23 */
+#define RESET_I2C_M_D 24
+#define RESET_I2C_M_C 25
+#define RESET_I2C_M_B 26
+#define RESET_I2C_M_A 27
+#define RESET_I2C_PROD_AHB 28
+#define RESET_I2C_PROD 29
+/* 30-31 */
+
+/* RESET1 */
+#define RESET_ACODEC 32
+#define RESET_DMA 33
+#define RESET_SD_EMMC_A 34
+/* 35 */
+#define RESET_USBCTRL 36
+/* 37 */
+#define RESET_USBPHY 38
+/* 39-41 */
+#define RESET_RSA 42
+#define RESET_DMC 43
+/* 44 */
+#define RESET_IRQ_CTRL 45
+/* 46 */
+#define RESET_NIC_VAD 47
+#define RESET_NIC_AXI 48
+#define RESET_RAMA 49
+#define RESET_RAMB 50
+/* 51-52 */
+#define RESET_ROM 53
+#define RESET_SPIFC 54
+#define RESET_GIC 55
+#define RESET_UART_C 56
+#define RESET_UART_B 57
+#define RESET_UART_A 58
+#define RESET_OSC_RING 59
+/* 60-63 */
+
+/* RESET2 */
+/* 64-95 */
+
+#endif
diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h
index 4ffa7c3..9071f13 100644
--- a/include/dt-bindings/reset/stm32mp1-resets.h
+++ b/include/dt-bindings/reset/stm32mp1-resets.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
diff --git a/include/dt-bindings/reset/stm32mp13-resets.h b/include/dt-bindings/reset/stm32mp13-resets.h
index 1b83a01..ecb37c7 100644
--- a/include/dt-bindings/reset/stm32mp13-resets.h
+++ b/include/dt-bindings/reset/stm32mp13-resets.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
diff --git a/include/dt-bindings/reset/sun20i-d1-ccu.h b/include/dt-bindings/reset/sun20i-d1-ccu.h
new file mode 100644
index 0000000..79e52ac
--- /dev/null
+++ b/include/dt-bindings/reset/sun20i-d1-ccu.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2020 huangzhenwei@allwinnertech.com
+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN20I_D1_CCU_H_
+#define _DT_BINDINGS_RST_SUN20I_D1_CCU_H_
+
+#define RST_MBUS 0
+#define RST_BUS_DE 1
+#define RST_BUS_DI 2
+#define RST_BUS_G2D 3
+#define RST_BUS_CE 4
+#define RST_BUS_VE 5
+#define RST_BUS_DMA 6
+#define RST_BUS_MSGBOX0 7
+#define RST_BUS_MSGBOX1 8
+#define RST_BUS_MSGBOX2 9
+#define RST_BUS_SPINLOCK 10
+#define RST_BUS_HSTIMER 11
+#define RST_BUS_DBG 12
+#define RST_BUS_PWM 13
+#define RST_BUS_DRAM 14
+#define RST_BUS_MMC0 15
+#define RST_BUS_MMC1 16
+#define RST_BUS_MMC2 17
+#define RST_BUS_UART0 18
+#define RST_BUS_UART1 19
+#define RST_BUS_UART2 20
+#define RST_BUS_UART3 21
+#define RST_BUS_UART4 22
+#define RST_BUS_UART5 23
+#define RST_BUS_I2C0 24
+#define RST_BUS_I2C1 25
+#define RST_BUS_I2C2 26
+#define RST_BUS_I2C3 27
+#define RST_BUS_SPI0 28
+#define RST_BUS_SPI1 29
+#define RST_BUS_EMAC 30
+#define RST_BUS_IR_TX 31
+#define RST_BUS_GPADC 32
+#define RST_BUS_THS 33
+#define RST_BUS_I2S0 34
+#define RST_BUS_I2S1 35
+#define RST_BUS_I2S2 36
+#define RST_BUS_SPDIF 37
+#define RST_BUS_DMIC 38
+#define RST_BUS_AUDIO 39
+#define RST_USB_PHY0 40
+#define RST_USB_PHY1 41
+#define RST_BUS_OHCI0 42
+#define RST_BUS_OHCI1 43
+#define RST_BUS_EHCI0 44
+#define RST_BUS_EHCI1 45
+#define RST_BUS_OTG 46
+#define RST_BUS_LRADC 47
+#define RST_BUS_DPSS_TOP 48
+#define RST_BUS_HDMI_SUB 49
+#define RST_BUS_HDMI_MAIN 50
+#define RST_BUS_MIPI_DSI 51
+#define RST_BUS_TCON_LCD0 52
+#define RST_BUS_TCON_TV 53
+#define RST_BUS_LVDS0 54
+#define RST_BUS_TVE 55
+#define RST_BUS_TVE_TOP 56
+#define RST_BUS_TVD 57
+#define RST_BUS_TVD_TOP 58
+#define RST_BUS_LEDC 59
+#define RST_BUS_CSI 60
+#define RST_BUS_TPADC 61
+#define RST_DSP 62
+#define RST_BUS_DSP_CFG 63
+#define RST_BUS_DSP_DBG 64
+#define RST_BUS_RISCV_CFG 65
+#define RST_BUS_CAN0 66
+#define RST_BUS_CAN1 67
+
+#endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun20i-d1-r-ccu.h b/include/dt-bindings/reset/sun20i-d1-r-ccu.h
new file mode 100644
index 0000000..e20babc
--- /dev/null
+++ b/include/dt-bindings/reset/sun20i-d1-r-ccu.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_
+#define _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_
+
+#define RST_BUS_R_TIMER 0
+#define RST_BUS_R_TWD 1
+#define RST_BUS_R_PPU 2
+#define RST_BUS_R_IR_RX 3
+#define RST_BUS_R_RTC 4
+#define RST_BUS_R_CPUCFG 5
+
+#endif /* _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun50i-h6-ccu.h b/include/dt-bindings/reset/sun50i-h6-ccu.h
index 81106f4..d038ddf 100644
--- a/include/dt-bindings/reset/sun50i-h6-ccu.h
+++ b/include/dt-bindings/reset/sun50i-h6-ccu.h
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
*/
diff --git a/include/dt-bindings/reset/sun50i-h6-r-ccu.h b/include/dt-bindings/reset/sun50i-h6-r-ccu.h
index 7950e79..d541ade 100644
--- a/include/dt-bindings/reset/sun50i-h6-r-ccu.h
+++ b/include/dt-bindings/reset/sun50i-h6-r-ccu.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
*/
diff --git a/include/dt-bindings/reset/sun50i-h616-ccu.h b/include/dt-bindings/reset/sun50i-h616-ccu.h
index cb6285a..1bd8bb0 100644
--- a/include/dt-bindings/reset/sun50i-h616-ccu.h
+++ b/include/dt-bindings/reset/sun50i-h616-ccu.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (C) 2020 Arm Ltd.
*/
diff --git a/include/dt-bindings/reset/ti-syscon.h b/include/dt-bindings/reset/ti-syscon.h
index 884fd91..1427ff1 100644
--- a/include/dt-bindings/reset/ti-syscon.h
+++ b/include/dt-bindings/reset/ti-syscon.h
@@ -1,7 +1,7 @@
/*
* TI Syscon Reset definitions
*
- * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/include/dwc3-omap-uboot.h b/include/dwc3-omap-uboot.h
index 7c982e3..ed92bfc 100644
--- a/include/dwc3-omap-uboot.h
+++ b/include/dwc3-omap-uboot.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* include/dwc3_omap_uboot.h
*
- * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (c) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Designware SuperSpeed OMAP Glue uboot init
*/
@@ -27,5 +27,5 @@
int dwc3_omap_uboot_init(struct dwc3_omap_device *dev);
void dwc3_omap_uboot_exit(int index);
-int dwc3_omap_uboot_interrupt_status(int index);
+int dwc3_omap_uboot_interrupt_status(struct udevice *dev);
#endif /* __DWC3_OMAP_UBOOT_H_ */
diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h
index e08530e..35cfbb9 100644
--- a/include/dwc3-uboot.h
+++ b/include/dwc3-uboot.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* include/dwc3-uboot.h
*
- * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (c) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Designware SuperSpeed USB uboot init
*/
@@ -44,7 +44,7 @@
int dwc3_uboot_init(struct dwc3_device *dev);
void dwc3_uboot_exit(int index);
-void dwc3_uboot_handle_interrupt(int index);
+void dwc3_uboot_handle_interrupt(struct udevice *dev);
struct phy;
#if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 4a29dda..e244105 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -149,8 +149,8 @@
/* GUID for the auto generated boot menu entry */
#define EFICONFIG_AUTO_GENERATED_ENTRY_GUID \
- EFI_GUID(0x38c1acc1, 0x9fc0, 0x41f0, \
- 0xb9, 0x01, 0xfa, 0x74, 0xd6, 0xd6, 0xe4, 0xde)
+ EFI_GUID(0x8108ac4e, 0x9f11, 0x4d59, \
+ 0x85, 0x0e, 0xe2, 0x1a, 0x52, 0x2c, 0x59, 0xb2)
/* Use internal device tree when starting UEFI application */
#define EFI_FDT_USE_INTERNAL NULL
diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h
index b1c3abd..b21c5cb 100644
--- a/include/efi_tcg2.h
+++ b/include/efi_tcg2.h
@@ -129,50 +129,6 @@
#define BOOT_SERVICE_CAPABILITY_MIN \
offsetof(struct efi_tcg2_boot_service_capability, number_of_pcr_banks)
-#define TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03 "Spec ID Event03"
-#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2 2
-#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2 0
-#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2 2
-
-/**
- * struct TCG_EfiSpecIdEventAlgorithmSize - hashing algorithm information
- *
- * @algorithm_id: algorithm defined in enum tpm2_algorithms
- * @digest_size: size of the algorithm
- */
-struct tcg_efi_spec_id_event_algorithm_size {
- u16 algorithm_id;
- u16 digest_size;
-} __packed;
-
-/**
- * struct TCG_EfiSpecIDEventStruct - content of the event log header
- *
- * @signature: signature, set to Spec ID Event03
- * @platform_class: class defined in TCG ACPI Specification
- * Client Common Header.
- * @spec_version_minor: minor version
- * @spec_version_major: major version
- * @spec_version_errata: major version
- * @uintn_size: size of the efi_uintn_t fields used in various
- * data structures used in this specification.
- * 0x01 indicates u32 and 0x02 indicates u64
- * @number_of_algorithms: hashing algorithms used in this event log
- * @digest_sizes: array of number_of_algorithms pairs
- * 1st member defines the algorithm id
- * 2nd member defines the algorithm size
- */
-struct tcg_efi_spec_id_event {
- u8 signature[16];
- u32 platform_class;
- u8 spec_version_minor;
- u8 spec_version_major;
- u8 spec_errata;
- u8 uintn_size;
- u32 number_of_algorithms;
- struct tcg_efi_spec_id_event_algorithm_size digest_sizes[];
-} __packed;
-
/**
* struct tdEFI_TCG2_FINAL_EVENTS_TABLE - log entries after Get Event Log
* @version: version number for this structure
diff --git a/include/env.h b/include/env.h
index 1480efa..430c4fa 100644
--- a/include/env.h
+++ b/include/env.h
@@ -240,11 +240,6 @@
int eth_env_set_enetaddr(const char *name, const uint8_t *enetaddr);
/**
- * env_fix_drivers() - Updates envdriver as per relocation
- */
-void env_fix_drivers(void);
-
-/**
* env_set_default_vars() - reset variables to their default value
*
* This resets individual variables to their value in the default environment
@@ -357,14 +352,6 @@
void env_set_default(const char *s, int flags);
/**
- * env_reloc() - Relocate the 'env' sub-commands
- *
- * This is used for those unfortunate archs with crappy toolchains
- */
-void env_reloc(void);
-
-
-/**
* env_import_fdt() - Import environment values from device tree blob
*
* This uses the value of the environment variable "env_fdt_path" as a
diff --git a/include/env/ti/default_findfdt.env b/include/env/ti/default_findfdt.env
new file mode 100644
index 0000000..a2b51dd
--- /dev/null
+++ b/include/env/ti/default_findfdt.env
@@ -0,0 +1,12 @@
+default_device_tree=CONFIG_DEFAULT_DEVICE_TREE
+default_device_tree_arch=ti
+#ifdef CONFIG_ARM64
+findfdt=
+ setenv name_fdt ${default_device_tree_arch}/${default_device_tree}.dtb;
+ setenv fdtfile ${name_fdt}
+#else
+default_device_tree_subarch=omap
+findfdt=
+ setenv name_fdt ${default_device_tree_arch}/${default_device_tree_subarch}/${default_device_tree}.dtb;
+ setenv fdtfile ${name_fdt}
+#endif
diff --git a/include/env/ti/dfu.h b/include/env/ti/dfu.h
index 3c90570..10bcf33 100644
--- a/include/env/ti/dfu.h
+++ b/include/env/ti/dfu.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com
*
* Environment variable definitions for DFU on TI boards.
*/
diff --git a/include/env/ti/k3_dfu.h b/include/env/ti/k3_dfu.h
index a16a3ad..098f5f5 100644
--- a/include/env/ti/k3_dfu.h
+++ b/include/env/ti/k3_dfu.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*
* Environment variable definitions for DFU on TI K3 SoCs.
*
diff --git a/include/env/ti/k3_rproc.h b/include/env/ti/k3_rproc.h
index 3418cb4..a467d75 100644
--- a/include/env/ti/k3_rproc.h
+++ b/include/env/ti/k3_rproc.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*
* rproc environment variable definitions for various TI K3 SoCs.
*/
diff --git a/include/env/ti/mmc.env b/include/env/ti/mmc.env
index 6fb47fb..0256a2d 100644
--- a/include/env/ti/mmc.env
+++ b/include/env/ti/mmc.env
@@ -5,7 +5,9 @@
${optargs}
root=PARTUUID=${uuid} rw
rootfstype=${mmcrootfstype}
+#ifndef CONFIG_BOOTSTD
loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr
+#endif
bootscript=echo Running bootscript from mmc${mmcdev} ...;
source ${loadaddr}
bootenvfile=uEnv.txt
@@ -15,10 +17,10 @@
loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}
loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/dtb/${fdtfile}
get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/dtb/${name_fdt}
-envboot=mmc dev ${mmcdev};
+envboot=if mmc dev ${mmcdev}; then
if mmc rescan; then
echo SD/MMC found on device ${mmcdev};
- if run loadbootscript; then
+ if test -n "${loadbootscript}" && run loadbootscript; then
run bootscript;
else
if run loadbootenv; then
@@ -31,6 +33,7 @@
fi;
fi;
fi;
+ fi;
mmcloados=
if test ${boot_fdt} = yes || test ${boot_fdt} = try; then
if run get_fdt_mmc; then
@@ -45,7 +48,7 @@
else
bootz;
fi;
-mmcboot=mmc dev ${mmcdev};
+mmcboot=if mmc dev ${mmcdev}; then
devnum=${mmcdev};
devtype=mmc;
if mmc rescan; then
@@ -58,7 +61,8 @@
run mmcloados;
fi;
fi;
-fi;
+ fi;
+ fi;
init_mmc=run args_all args_mmc
get_overlay_mmc=
diff --git a/include/env/ti/mmc.h b/include/env/ti/mmc.h
index 769ea9d..d07189b 100644
--- a/include/env/ti/mmc.h
+++ b/include/env/ti/mmc.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com
*
* Environment variable definitions for MMC/SD on TI boards.
*/
diff --git a/include/env/ti/nand.h b/include/env/ti/nand.h
index 7d00afa..0e0da45 100644
--- a/include/env/ti/nand.h
+++ b/include/env/ti/nand.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*
* Environment variable definitions for NAND on TI boards.
*/
diff --git a/include/env/ti/ti_armv7_common.env b/include/env/ti/ti_common.env
similarity index 100%
rename from include/env/ti/ti_armv7_common.env
rename to include/env/ti/ti_common.env
diff --git a/include/env/ti/ufs.h b/include/env/ti/ufs.h
index 6619ec9..c192f3a 100644
--- a/include/env/ti/ufs.h
+++ b/include/env/ti/ufs.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*
* Environment variable definitions for UFS on TI boards.
*/
diff --git a/include/env_default.h b/include/env_default.h
index b16c22d..2ca4a08 100644
--- a/include/env_default.h
+++ b/include/env_default.h
@@ -21,7 +21,7 @@
{
#elif defined(DEFAULT_ENV_INSTANCE_STATIC)
static char default_environment[] = {
-#elif defined(DEFAULT_ENV_IS_RW)
+#elif defined(CONFIG_DEFAULT_ENV_IS_RW)
char default_environment[] = {
#else
const char default_environment[] = {
@@ -42,7 +42,7 @@
#if defined(CONFIG_BOOTDELAY)
"bootdelay=" __stringify(CONFIG_BOOTDELAY) "\0"
#endif
-#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
+#if !defined(CONFIG_OF_SERIAL_BAUD) && defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
"baudrate=" __stringify(CONFIG_BAUDRATE) "\0"
#endif
#ifdef CONFIG_LOADS_ECHO
@@ -119,6 +119,10 @@
#ifdef CFG_EXTRA_ENV_SETTINGS
CFG_EXTRA_ENV_SETTINGS
#endif
+#ifdef CONFIG_OF_SERIAL_BAUD
+ /* Padding for baudrate at the end when environment is writable */
+ "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
+#endif
"\0"
#else /* CONFIG_USE_DEFAULT_ENV_FILE */
#include "generated/defaultenv_autogenerated.h"
diff --git a/include/env_internal.h b/include/env_internal.h
index 6a69494..fcb4642 100644
--- a/include/env_internal.h
+++ b/include/env_internal.h
@@ -89,7 +89,7 @@
extern env_t embedded_environment;
#endif /* ENV_IS_EMBEDDED */
-#ifdef DEFAULT_ENV_IS_RW
+#ifdef CONFIG_DEFAULT_ENV_IS_RW
extern char default_environment[];
#else
extern const char default_environment[];
diff --git a/include/event.h b/include/event.h
index f5c5d30..a8f046d 100644
--- a/include/event.h
+++ b/include/event.h
@@ -95,6 +95,37 @@
EVT_MISC_INIT_F,
/**
+ * @EVT_FSP_INIT_F:
+ * This event is triggered before relocation to set up Firmware Support
+ * Package.
+ * Where U-Boot relies on binary blobs to handle part of the system
+ * init, this event can be used to set up the blobs. This is used on
+ * some Intel platforms
+ */
+ EVT_FSP_INIT_F,
+
+ /**
+ * @EVT_SETTINGS_R:
+ * This event is triggered post-relocation and before console init.
+ * This gives an option to perform any platform-dependent setup, which
+ * needs to take place before show_board_info() (e.g. readout of EEPROM
+ * stored settings).
+ */
+ EVT_SETTINGS_R,
+
+ /**
+ * @EVT_LAST_STAGE_INIT:
+ * This event is triggered just before jumping to the main loop.
+ * Some boards need to perform initialisation immediately before control
+ * is passed to the command-line interpreter (e.g. for init that depend
+ * on later phases in the init sequence).
+ *
+ * Some parts can be only initialized if all others (like Interrupts)
+ * are up and running (e.g. the PC-style ISA keyboard).
+ */
+ EVT_LAST_STAGE_INIT,
+
+ /**
* @EVT_FPGA_LOAD:
* The FPGA load hook is called after loading an FPGA with a new binary.
* Its parameter is of type struct event_fpga_load and contains
@@ -185,19 +216,48 @@
union event_data data;
};
+/* Flags for event spy */
+enum evspy_flags {
+ EVSPYF_SIMPLE = 1 << 0,
+};
+
/** Function type for event handlers */
typedef int (*event_handler_t)(void *ctx, struct event *event);
+/** Function type for simple event handlers */
+typedef int (*event_handler_simple_t)(void);
+
/**
* struct evspy_info - information about an event spy
*
* @func: Function to call when the event is activated (must be first)
* @type: Event type
+ * @flags: Flags for this spy
* @id: Event id string
*/
struct evspy_info {
event_handler_t func;
- enum event_t type;
+ u8 type;
+ u8 flags;
+#if CONFIG_IS_ENABLED(EVENT_DEBUG)
+ const char *id;
+#endif
+};
+
+/**
+ * struct evspy_info_simple - information about an event spy
+ *
+ * THis is the 'simple' record, the only difference being the handler function
+ *
+ * @func: Function to call when the event is activated (must be first)
+ * @type: Event type
+ * @flags: Flags for this spy
+ * @id: Event id string
+ */
+struct evspy_info_simple {
+ event_handler_simple_t func;
+ u8 type;
+ u8 flags;
#if CONFIG_IS_ENABLED(EVENT_DEBUG)
const char *id;
#endif
@@ -205,9 +265,11 @@
/* Declare a new event spy */
#if CONFIG_IS_ENABLED(EVENT_DEBUG)
-#define _ESPY_REC(_type, _func) { _func, _type, #_func, }
+#define _ESPY_REC(_type, _func) { _func, _type, 0, #_func, }
+#define _ESPY_REC_SIMPLE(_type, _func) { _func, _type, EVSPYF_SIMPLE, #_func, }
#else
#define _ESPY_REC(_type, _func) { _func, _type, }
+#define _ESPY_REC_SIMPLE(_type, _func) { _func, _type, EVSPYF_SIMPLE }
#endif
static inline const char *event_spy_id(struct evspy_info *spy)
@@ -229,9 +291,9 @@
* {
* return sandbox_early_getopt_check();
* }
- * EVENT_SPY(EVT_MISC_INIT_F, sandbox_misc_init_f);
+ * EVENT_SPY_FULL(EVT_MISC_INIT_F, sandbox_misc_init_f);
*
- * where EVENT_SPY uses ll_entry_declare()
+ * where EVENT_SPY_FULL uses ll_entry_declare()
*
* In this case, LTO decides to drop the sandbox_misc_init_f() function
* (which is fine) but then drops the linker-list entry too. This means
@@ -250,10 +312,16 @@
* away the linker-list entry sometimes, e.g. with the EVT_FT_FIXUP entry in
* vbe_simple.c - so for now, make it global.
*/
-#define EVENT_SPY(_type, _func) \
+#define EVENT_SPY_FULL(_type, _func) \
__used ll_entry_declare(struct evspy_info, _type ## _3_ ## _func, \
evspy_info) = _ESPY_REC(_type, _func)
+/* Simple spy with no function arguemnts */
+#define EVENT_SPY_SIMPLE(_type, _func) \
+ __used ll_entry_declare(struct evspy_info_simple, \
+ _type ## _3_ ## _func, \
+ evspy_info) = _ESPY_REC_SIMPLE(_type, _func)
+
/**
* event_register - register a new spy
*
@@ -270,14 +338,12 @@
void event_show_spy_list(void);
/**
- * event_manual_reloc() - Relocate event handler pointers
+ * event_type_name() - Get the name of an event type
*
- * Relocate event handler pointers for all static event spies. It is called
- * during the generic board init sequence, after relocation.
- *
- * Return: 0 if OK
+ * @type: Type to check
+ * Return: Name of event, or "(unknown)" if not known
*/
-int event_manual_reloc(void);
+const char *event_type_name(enum event_t type);
/**
* event_notify() - notify spies about an event
diff --git a/include/expo.h b/include/expo.h
index e8f7d7d..264745f 100644
--- a/include/expo.h
+++ b/include/expo.h
@@ -4,14 +4,16 @@
* Written by Simon Glass <sjg@chromium.org>
*/
-#ifndef __SCENE_H
-#define __SCENE_H
+#ifndef __EXPO_H
+#define __EXPO_H
+#include <abuf.h>
#include <dm/ofnode_decl.h>
#include <linux/list.h>
struct udevice;
-struct video_priv;
+
+#include <cli.h>
/**
* enum expoact_type - types of actions reported by the expo
@@ -122,6 +124,9 @@
* @id: ID number of the scene
* @title_id: String ID of title of the scene (allocated)
* @highlight_id: ID of highlighted object, if any
+ * @cls: cread state to use for input
+ * @buf: Buffer for input
+ * @entry_save: Buffer to hold vidconsole text-entry information
* @sibling: Node to link this scene to its siblings
* @obj_head: List of objects in the scene
*/
@@ -131,6 +136,9 @@
uint id;
uint title_id;
uint highlight_id;
+ struct cli_line_state cls;
+ struct abuf buf;
+ struct abuf entry_save;
struct list_head sibling;
struct list_head obj_head;
};
@@ -142,12 +150,16 @@
* @SCENEOBJT_IMAGE: Image data to render
* @SCENEOBJT_TEXT: Text line to render
* @SCENEOBJT_MENU: Menu containing items the user can select
+ * @SCENEOBJT_TEXTLINE: Line of text the user can edit
*/
enum scene_obj_t {
SCENEOBJT_NONE = 0,
SCENEOBJT_IMAGE,
SCENEOBJT_TEXT,
+
+ /* types from here on can be highlighted */
SCENEOBJT_MENU,
+ SCENEOBJT_TEXTLINE,
};
/**
@@ -179,6 +191,11 @@
SCENEOF_OPEN = 1 << 2,
};
+enum {
+ /* Maximum number of characters allowed in an line editor */
+ EXPO_MAX_CHARS = 250,
+};
+
/**
* struct scene_obj - information about an object in a scene
*
@@ -188,6 +205,8 @@
* @type: Type of this object
* @dim: Dimensions for this object
* @flags: Flags for this object
+ * @bit_length: Number of bits used for this object in CMOS RAM
+ * @start_bit: Start bit to use for this object in CMOS RAM
* @sibling: Node to link this object to its siblings
*/
struct scene_obj {
@@ -196,10 +215,18 @@
uint id;
enum scene_obj_t type;
struct scene_dim dim;
- int flags;
+ u8 flags;
+ u8 bit_length;
+ u16 start_bit;
struct list_head sibling;
};
+/* object can be highlighted when moving around expo */
+static inline bool scene_obj_can_highlight(const struct scene_obj *obj)
+{
+ return obj->type >= SCENEOBJT_MENU;
+}
+
/**
* struct scene_obj_img - information about an image object in a scene
*
@@ -294,6 +321,27 @@
};
/**
+ * struct scene_obj_textline - information about a textline in a scene
+ *
+ * A textline has a prompt and a line of editable text
+ *
+ * @obj: Basic object information
+ * @label_id: ID of the label text, or 0 if none
+ * @edit_id: ID of the editable text
+ * @max_chars: Maximum number of characters allowed
+ * @buf: Text buffer containing current text
+ * @pos: Cursor position
+ */
+struct scene_obj_textline {
+ struct scene_obj obj;
+ uint label_id;
+ uint edit_id;
+ uint max_chars;
+ struct abuf buf;
+ uint pos;
+};
+
+/**
* expo_new() - create a new expo
*
* Allocates a new expo
@@ -502,7 +550,7 @@
struct scene_obj_txt **txtp);
/**
- * scene_txt_str() - add a new string to expr and text object to a scene
+ * scene_txt_str() - add a new string to expo and text object to a scene
*
* @scn: Scene to update
* @name: Name to use (this is allocated by this call)
@@ -528,6 +576,19 @@
struct scene_obj_menu **menup);
/**
+ * scene_textline() - create a textline
+ *
+ * @scn: Scene to update
+ * @name: Name to use (this is allocated by this call)
+ * @id: ID to use for the new object (0 to allocate one)
+ * @max_chars: Maximum length of the textline in characters
+ * @tlinep: If non-NULL, returns the new object
+ * Returns: ID number for the object (typically @id), or -ve on error
+ */
+int scene_textline(struct scene *scn, const char *name, uint id, uint max_chars,
+ struct scene_obj_textline **tlinep);
+
+/**
* scene_txt_set_font() - Set the font for an object
*
* @scn: Scene to update
@@ -676,24 +737,4 @@
*/
int expo_build(ofnode root, struct expo **expp);
-/**
- * cedit_arange() - Arrange objects in a configuration-editor scene
- *
- * @exp: Expo to update
- * @vid_priv: Private info of the video device
- * @scene_id: scene ID to arrange
- * Returns: 0 if OK, -ve on error
- */
-int cedit_arange(struct expo *exp, struct video_priv *vid_priv, uint scene_id);
-
-/**
- * cedit_run() - Run a configuration editor
- *
- * This accepts input until the user quits with Escape
- *
- * @exp: Expo to use
- * Returns: 0 if OK, -ve on error
- */
-int cedit_run(struct expo *exp);
-
-#endif /*__SCENE_H */
+#endif /*__EXPO_H */
diff --git a/include/ext4fs.h b/include/ext4fs.h
index cb5d9cc..dd66d27 100644
--- a/include/ext4fs.h
+++ b/include/ext4fs.h
@@ -31,6 +31,7 @@
struct disk_partition;
#define EXT4_INDEX_FL 0x00001000 /* Inode uses hash tree index */
+#define EXT4_TOPDIR_FL 0x00020000 /* Top of directory hierarchies*/
#define EXT4_EXTENTS_FL 0x00080000 /* Inode uses extents */
#define EXT4_EXT_MAGIC 0xf30a
#define EXT4_FEATURE_RO_COMPAT_GDT_CSUM 0x0010
diff --git a/include/ext_common.h b/include/ext_common.h
index 30a0c24..b09bbde 100644
--- a/include/ext_common.h
+++ b/include/ext_common.h
@@ -35,6 +35,16 @@
#define EXT2_PATH_MAX 4096
/* Maximum nesting of symlinks, used to prevent a loop. */
#define EXT2_MAX_SYMLINKCNT 8
+/* Maximum file name length */
+#define EXT2_NAME_LEN 255
+
+/*
+ * Revision levels
+ */
+#define EXT2_GOOD_OLD_REV 0 /* The good old (original) format */
+#define EXT2_DYNAMIC_REV 1 /* V2 format w/ dynamic inode sizes */
+
+#define EXT2_GOOD_OLD_INODE_SIZE 128
/* Filetype used in directory entry. */
#define FILETYPE_UNKNOWN 0
@@ -48,6 +58,10 @@
#define FILETYPE_INO_DIRECTORY 0040000
#define FILETYPE_INO_SYMLINK 0120000
#define EXT2_ROOT_INO 2 /* Root inode */
+#define EXT2_BOOT_LOADER_INO 5 /* Boot loader inode */
+
+/* First non-reserved inode for old ext2 filesystems */
+#define EXT2_GOOD_OLD_FIRST_INO 11
/* The size of an ext2 block in bytes. */
#define EXT2_BLOCK_SIZE(data) (1 << LOG2_BLOCK_SIZE(data))
diff --git a/include/fpga.h b/include/fpga.h
index ed688cc..44f2755 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -60,8 +60,16 @@
int fpga_count(void);
const fpga_desc *const fpga_get_desc(int devnum);
int fpga_is_partial_data(int devnum, size_t img_len);
+#if CONFIG_IS_ENABLED(FPGA)
int fpga_load(int devnum, const void *buf, size_t bsize,
bitstream_type bstype, int flags);
+#else
+static inline int fpga_load(int devnum, const void *buf, size_t bsize,
+ bitstream_type bstype, int flags)
+{
+ return FPGA_FAIL;
+}
+#endif
int fpga_fsload(int devnum, const void *buf, size_t size,
fpga_fs_info *fpga_fsinfo);
int fpga_loads(int devnum, const void *buf, size_t size,
diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h
index c701dc1..258738d 100644
--- a/include/fsl-mc/fsl_mc.h
+++ b/include/fsl-mc/fsl_mc.h
@@ -66,6 +66,7 @@
int get_dpl_apply_status(void);
int is_lazy_dpl_addr_valid(void);
void fdt_fixup_mc_ddr(u64 *base, u64 *size);
+void fdt_reserve_mc_mem(void *blob, u32 mc_icid);
#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
int get_aiop_apply_status(void);
#endif
diff --git a/include/generic-phy.h b/include/generic-phy.h
index bee4de8..eaab749 100644
--- a/include/generic-phy.h
+++ b/include/generic-phy.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
* Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/include/i2c.h b/include/i2c.h
index ef3820e..4e59009 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -538,6 +538,18 @@
struct udevice **devp);
/**
+ * i2c_get_chip_by_phandle() - get a device to use to access a chip
+ * based on a phandle property pointing to it
+ *
+ * @parent: Parent device containing the phandle pointer
+ * @name: Name of phandle property in the parent device node
+ * @devp: Returns pointer to new device or NULL if not found
+ * Return: 0 on success, -ve on failure
+ */
+int i2c_get_chip_by_phandle(const struct udevice *parent, const char *prop_name,
+ struct udevice **devp);
+
+/**
* i2c_chip_of_to_plat() - Decode standard I2C platform data
*
* This decodes the chip address from a device tree node and puts it into
diff --git a/include/image.h b/include/image.h
index 925e6a3..078e5af 100644
--- a/include/image.h
+++ b/include/image.h
@@ -231,6 +231,7 @@
IH_TYPE_SUNXI_TOC0, /* Allwinner TOC0 Boot Image */
IH_TYPE_FDT_LEGACY, /* Binary Flat Device Tree Blob in a Legacy Image */
IH_TYPE_RENESAS_SPKG, /* Renesas SPKG image */
+ IH_TYPE_STARFIVE_SPL, /* StarFive SPL image */
IH_TYPE_COUNT, /* Number of image types */
};
@@ -408,6 +409,7 @@
#define BOOTM_STATE_OS_FAKE_GO 0x00000200 /* 'Almost' run the OS */
#define BOOTM_STATE_OS_GO 0x00000400
#define BOOTM_STATE_PRE_LOAD 0x00000800
+#define BOOTM_STATE_MEASURE 0x00001000
int state;
#if defined(CONFIG_LMB) && !defined(USE_HOSTCC)
diff --git a/arch/arm/include/asm/mach-imx/image.h b/include/imx_container.h
similarity index 82%
rename from arch/arm/include/asm/mach-imx/image.h
rename to include/imx_container.h
index ee67ca9..54cd684 100644
--- a/arch/arm/include/asm/mach-imx/image.h
+++ b/include/imx_container.h
@@ -18,6 +18,9 @@
#define CONTAINER_HDR_QSPI_OFFSET SZ_4K
#define CONTAINER_HDR_NAND_OFFSET SZ_128M
+#define CONTAINER_HDR_TAG 0x87
+#define CONTAINER_HDR_VERSION 0
+
struct container_hdr {
u8 version;
u8 length_lsb;
@@ -66,4 +69,10 @@
} __packed;
int get_container_size(ulong addr, u16 *header_length);
+
+static inline bool valid_container_hdr(struct container_hdr *container)
+{
+ return container->tag == CONTAINER_HDR_TAG &&
+ container->version == CONTAINER_HDR_VERSION;
+}
#endif
diff --git a/include/init.h b/include/init.h
index 3bf3047..d57a24f 100644
--- a/include/init.h
+++ b/include/init.h
@@ -58,17 +58,6 @@
int mach_cpu_init(void);
/**
- * arch_fsp_init() - perform firmware support package init
- *
- * Where U-Boot relies on binary blobs to handle part of the system init, this
- * function can be used to set up the blobs. This is used on some Intel
- * platforms.
- *
- * Return: 0
- */
-int arch_fsp_init(void);
-
-/**
* arch_fsp_init() - perform post-relocation firmware support package init
*
* Where U-Boot relies on binary blobs to handle part of the system init, this
@@ -281,15 +270,25 @@
__attribute__ ((noreturn));
int cpu_init_r(void);
-int last_stage_init(void);
int mac_read_from_eeprom(void);
+
+/**
+ * serial_read_from_eeprom - read the serial number from EEPROM
+ *
+ * This function reads the serial number from the EEPROM and sets the
+ * appropriate environment variable.
+ *
+ * The environment variable is only set if it has not been set
+ * already. This ensures that any user-saved variables are never
+ * overwritten.
+ *
+ * This function must be called after relocation.
+ */
+int serial_read_from_eeprom(int devnum);
int set_cpu_clk_info(void);
int update_flash_size(int flash_size);
int arch_early_init_r(void);
int misc_init_r(void);
-#if defined(CONFIG_VID)
-int init_func_vid(void);
-#endif
/* common/board_info.c */
int checkboard(void);
diff --git a/include/initcall.h b/include/initcall.h
index 69ce268..62d3bb6 100644
--- a/include/initcall.h
+++ b/include/initcall.h
@@ -6,52 +6,33 @@
#ifndef __INITCALL_H
#define __INITCALL_H
+#include <asm/types.h>
+#include <event.h>
+
+_Static_assert(EVT_COUNT < 256, "Can only support 256 event types with 8 bits");
+
+/**
+ * init_fnc_t - Init function
+ *
+ * Return: 0 if OK -ve on error
+ */
typedef int (*init_fnc_t)(void);
-#include <log.h>
-#ifdef CONFIG_EFI_APP
-#include <efi.h>
-#endif
-#include <asm/global_data.h>
+/* Top bit indicates that the initcall is an event */
+#define INITCALL_IS_EVENT GENMASK(BITS_PER_LONG - 1, 8)
+#define INITCALL_EVENT_TYPE GENMASK(7, 0)
-/*
- * To enable debugging. add #define DEBUG at the top of the including file.
+#define INITCALL_EVENT(_type) (void *)((_type) | INITCALL_IS_EVENT)
+
+/**
+ * initcall_run_list() - Run through a list of function calls
*
- * To find a symbol, use grep on u-boot.map
+ * This calls functions one after the other, stopping at the first error, or
+ * when NULL is obtained.
+ *
+ * @init_sequence: NULL-terminated init sequence to run
+ * Return: 0 if OK, or -ve error code from the first failure
*/
-static inline int initcall_run_list(const init_fnc_t init_sequence[])
-{
- const init_fnc_t *init_fnc_ptr;
-
- for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
- unsigned long reloc_ofs = 0;
- int ret;
-
- /*
- * Sandbox is relocated by the OS, so symbols always appear at
- * the relocated address.
- */
- if (IS_ENABLED(CONFIG_SANDBOX) || (gd->flags & GD_FLG_RELOC))
- reloc_ofs = gd->reloc_off;
-#ifdef CONFIG_EFI_APP
- reloc_ofs = (unsigned long)image_base;
-#endif
- if (reloc_ofs)
- debug("initcall: %p (relocated to %p)\n",
- (char *)*init_fnc_ptr - reloc_ofs,
- (char *)*init_fnc_ptr);
- else
- debug("initcall: %p\n", (char *)*init_fnc_ptr - reloc_ofs);
-
- ret = (*init_fnc_ptr)();
- if (ret) {
- printf("initcall sequence %p failed at call %p (err=%d)\n",
- init_sequence,
- (char *)*init_fnc_ptr - reloc_ofs, ret);
- return -1;
- }
- }
- return 0;
-}
+int initcall_run_list(const init_fnc_t init_sequence[]);
#endif
diff --git a/include/interrupt.h b/include/interrupt.h
new file mode 100644
index 0000000..46ef2e1
--- /dev/null
+++ b/include/interrupt.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <asm/setjmp.h>
+
+/**
+ * struct resume_data - data for resume after interrupt
+ */
+struct resume_data {
+ /** @jump: longjmp buffer */
+ jmp_buf jump;
+ /** @code: exception code */
+ ulong code;
+};
+
+/**
+ * set_resume() - set longjmp buffer for resuming after exception
+ *
+ * By calling this function it is possible to use a long jump to catch an
+ * exception. The caller sets the long jump buffer with set_resume() and then
+ * executes setjmp(). If an exception occurs, the code will return to the
+ * setjmp caller(). The exception code will be returned in @data->code.
+ *
+ * After the critical operation call set_resume(NULL) so that an exception in
+ * another part of the code will not accidently invoke the long jump.
+ *
+ * .. code-block:: c
+ *
+ * // This example shows how to use set_resume().
+ *
+ * struct resume_data resume;
+ * int ret;
+ *
+ * set_resume(&resume);
+ * ret = setjmp(resume.jump);
+ * if (ret) {
+ * printf("An exception %ld occurred\n", resume.code);
+ * } else {
+ * // Do what might raise an exception here.
+ * }
+ * set_resume(NULL);
+ *
+ * @data: pointer to structure with longjmp address
+ * Return: 0 before an exception, 1 after an exception occurred
+ */
+void set_resume(struct resume_data *data);
diff --git a/include/k3-avs.h b/include/k3-avs.h
index e3c3caf..1014d5d 100644
--- a/include/k3-avs.h
+++ b/include/k3-avs.h
@@ -2,7 +2,7 @@
/*
* Texas Instruments' K3 Adaptive Voltage Scaling driver
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* Tero Kristo <t-kristo@ti.com>
*
*/
diff --git a/include/k3-clk.h b/include/k3-clk.h
index 49ba53d..1b6ab8f 100644
--- a/include/k3-clk.h
+++ b/include/k3-clk.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * (C) Copyright 2020-2021 Texas Instruments Incorporated - http://www.ti.com
+ * (C) Copyright 2020-2021 Texas Instruments Incorporated - https://www.ti.com
* Tero Kristo <t-kristo@ti.com>
*/
diff --git a/include/k3-dev.h b/include/k3-dev.h
index d288ae3..072e10b 100644
--- a/include/k3-dev.h
+++ b/include/k3-dev.h
@@ -2,7 +2,7 @@
/*
* Texas Instruments K3 Device Platform Data
*
- * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __K3_DEV_H__
#define __K3_DEV_H__
diff --git a/include/linux/compat.h b/include/linux/compat.h
index 921e698..f8e3570 100644
--- a/include/linux/compat.h
+++ b/include/linux/compat.h
@@ -271,6 +271,8 @@
#define __devinit
#define __devinitdata
#define __devinitconst
+#define __initconst
+#define __initdata
#define kthread_create(...) __builtin_return_address(0)
#define kthread_stop(...) do { } while (0)
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index aeb38de..651f870 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -19,6 +19,7 @@
* @oobsize: OOB area size
* @pages_per_eraseblock: number of pages per eraseblock
* @eraseblocks_per_lun: number of eraseblocks per LUN (Logical Unit Number)
+ * @max_bad_eraseblocks_per_lun: maximum number of eraseblocks per LUN
* @planes_per_lun: number of planes per LUN
* @luns_per_target: number of LUN per target (target is a synonym for die)
* @ntargets: total number of targets exposed by the NAND device
@@ -29,18 +30,20 @@
unsigned int oobsize;
unsigned int pages_per_eraseblock;
unsigned int eraseblocks_per_lun;
+ unsigned int max_bad_eraseblocks_per_lun;
unsigned int planes_per_lun;
unsigned int luns_per_target;
unsigned int ntargets;
};
-#define NAND_MEMORG(bpc, ps, os, ppe, epl, ppl, lpt, nt) \
+#define NAND_MEMORG(bpc, ps, os, ppe, epl, mbb, ppl, lpt, nt) \
{ \
.bits_per_cell = (bpc), \
.pagesize = (ps), \
.oobsize = (os), \
.pages_per_eraseblock = (ppe), \
.eraseblocks_per_lun = (epl), \
+ .max_bad_eraseblocks_per_lun = (mbb), \
.planes_per_lun = (ppl), \
.luns_per_target = (lpt), \
.ntargets = (nt), \
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
index 15bcd59..e8d6feb 100644
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -39,9 +39,9 @@
SPI_MEM_OP_NO_DUMMY, \
SPI_MEM_OP_NO_DATA)
-#define SPINAND_READID_OP(ndummy, buf, len) \
+#define SPINAND_READID_OP(naddr, ndummy, buf, len) \
SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \
- SPI_MEM_OP_NO_ADDR, \
+ SPI_MEM_OP_ADDR(naddr, 0, 1), \
SPI_MEM_OP_DUMMY(ndummy, 1), \
SPI_MEM_OP_DATA_IN(len, buf, 1))
@@ -75,30 +75,60 @@
SPI_MEM_OP_DUMMY(ndummy, 1), \
SPI_MEM_OP_DATA_IN(len, buf, 1))
+#define SPINAND_PAGE_READ_FROM_CACHE_OP_3A(fast, addr, ndummy, buf, len) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \
+ SPI_MEM_OP_ADDR(3, addr, 1), \
+ SPI_MEM_OP_DUMMY(ndummy, 1), \
+ SPI_MEM_OP_DATA_IN(len, buf, 1))
+
#define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len) \
SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
SPI_MEM_OP_ADDR(2, addr, 1), \
SPI_MEM_OP_DUMMY(ndummy, 1), \
SPI_MEM_OP_DATA_IN(len, buf, 2))
+#define SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(addr, ndummy, buf, len) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
+ SPI_MEM_OP_ADDR(3, addr, 1), \
+ SPI_MEM_OP_DUMMY(ndummy, 1), \
+ SPI_MEM_OP_DATA_IN(len, buf, 2))
+
#define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len) \
SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
SPI_MEM_OP_ADDR(2, addr, 1), \
SPI_MEM_OP_DUMMY(ndummy, 1), \
SPI_MEM_OP_DATA_IN(len, buf, 4))
+#define SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(addr, ndummy, buf, len) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
+ SPI_MEM_OP_ADDR(3, addr, 1), \
+ SPI_MEM_OP_DUMMY(ndummy, 1), \
+ SPI_MEM_OP_DATA_IN(len, buf, 4))
+
#define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len) \
SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
SPI_MEM_OP_ADDR(2, addr, 2), \
SPI_MEM_OP_DUMMY(ndummy, 2), \
SPI_MEM_OP_DATA_IN(len, buf, 2))
+#define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP_3A(addr, ndummy, buf, len) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
+ SPI_MEM_OP_ADDR(3, addr, 2), \
+ SPI_MEM_OP_DUMMY(ndummy, 2), \
+ SPI_MEM_OP_DATA_IN(len, buf, 2))
+
#define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(addr, ndummy, buf, len) \
SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
SPI_MEM_OP_ADDR(2, addr, 4), \
SPI_MEM_OP_DUMMY(ndummy, 4), \
SPI_MEM_OP_DATA_IN(len, buf, 4))
+#define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP_3A(addr, ndummy, buf, len) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
+ SPI_MEM_OP_ADDR(3, addr, 4), \
+ SPI_MEM_OP_DUMMY(ndummy, 4), \
+ SPI_MEM_OP_DATA_IN(len, buf, 4))
+
#define SPINAND_PROG_EXEC_OP(addr) \
SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \
SPI_MEM_OP_ADDR(3, addr, 1), \
@@ -153,37 +183,46 @@
* @data: buffer containing the id bytes. Currently 4 bytes large, but can
* be extended if required
* @len: ID length
- *
- * struct_spinand_id->data contains all bytes returned after a READ_ID command,
- * including dummy bytes if the chip does not emit ID bytes right after the
- * READ_ID command. The responsibility to extract real ID bytes is left to
- * struct_manufacurer_ops->detect().
*/
struct spinand_id {
u8 data[SPINAND_MAX_ID_LEN];
int len;
};
+enum spinand_readid_method {
+ SPINAND_READID_METHOD_OPCODE,
+ SPINAND_READID_METHOD_OPCODE_ADDR,
+ SPINAND_READID_METHOD_OPCODE_DUMMY,
+};
+
+/**
+ * struct spinand_devid - SPI NAND device id structure
+ * @id: device id of current chip
+ * @len: number of bytes in device id
+ * @method: method to read chip id
+ * There are 3 possible variants:
+ * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately
+ * after read_id opcode.
+ * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after
+ * read_id opcode + 1-byte address.
+ * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after
+ * read_id opcode + 1 dummy byte.
+ */
+struct spinand_devid {
+ const u8 *id;
+ const u8 len;
+ const enum spinand_readid_method method;
+};
+
/**
* struct manufacurer_ops - SPI NAND manufacturer specific operations
- * @detect: detect a SPI NAND device. Every time a SPI NAND device is probed
- * the core calls the struct_manufacurer_ops->detect() hook of each
- * registered manufacturer until one of them return 1. Note that
- * the first thing to check in this hook is that the manufacturer ID
- * in struct_spinand_device->id matches the manufacturer whose
- * ->detect() hook has been called. Should return 1 if there's a
- * match, 0 if the manufacturer ID does not match and a negative
- * error code otherwise. When true is returned, the core assumes
- * that properties of the NAND chip (spinand->base.memorg and
- * spinand->base.eccreq) have been filled
* @init: initialize a SPI NAND device
* @cleanup: cleanup a SPI NAND device
*
* Each SPI NAND manufacturer driver should implement this interface so that
- * NAND chips coming from this vendor can be detected and initialized properly.
+ * NAND chips coming from this vendor can be initialized properly.
*/
struct spinand_manufacturer_ops {
- int (*detect)(struct spinand_device *spinand);
int (*init)(struct spinand_device *spinand);
void (*cleanup)(struct spinand_device *spinand);
};
@@ -192,11 +231,16 @@
* struct spinand_manufacturer - SPI NAND manufacturer instance
* @id: manufacturer ID
* @name: manufacturer name
+ * @devid_len: number of bytes in device ID
+ * @chips: supported SPI NANDs under current manufacturer
+ * @nchips: number of SPI NANDs available in chips array
* @ops: manufacturer operations
*/
struct spinand_manufacturer {
u8 id;
char *name;
+ const struct spinand_info *chips;
+ const size_t nchips;
const struct spinand_manufacturer_ops *ops;
};
@@ -204,6 +248,7 @@
extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
extern const struct spinand_manufacturer macronix_spinand_manufacturer;
extern const struct spinand_manufacturer micron_spinand_manufacturer;
+extern const struct spinand_manufacturer paragon_spinand_manufacturer;
extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
extern const struct spinand_manufacturer winbond_spinand_manufacturer;
@@ -268,7 +313,7 @@
*/
struct spinand_info {
const char *model;
- u8 devid;
+ struct spinand_devid devid;
u32 flags;
struct nand_memory_organization memorg;
struct nand_ecc_req eccreq;
@@ -282,6 +327,13 @@
unsigned int target);
};
+#define SPINAND_ID(__method, ...) \
+ { \
+ .id = (const u8[]){ __VA_ARGS__ }, \
+ .len = sizeof((u8[]){ __VA_ARGS__ }), \
+ .method = __method, \
+ }
+
#define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \
{ \
.read_cache = __read, \
@@ -440,9 +492,10 @@
}
#endif /* __UBOOT__ */
-int spinand_match_and_init(struct spinand_device *dev,
+int spinand_match_and_init(struct spinand_device *spinand,
const struct spinand_info *table,
- unsigned int table_size, u8 devid);
+ unsigned int table_size,
+ enum spinand_readid_method rdid_method);
int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
int spinand_select_target(struct spinand_device *spinand, unsigned int target);
diff --git a/include/linux/soc/ti/cppi5.h b/include/linux/soc/ti/cppi5.h
index cfdf7ea..c5d7ebd 100644
--- a/include/linux/soc/ti/cppi5.h
+++ b/include/linux/soc/ti/cppi5.h
@@ -2,7 +2,7 @@
/*
* CPPI5 descriptors interface
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
*/
#ifndef __TI_CPPI5_H__
@@ -11,6 +11,7 @@
#include <hexdump.h>
#include <linux/bitops.h>
#include <linux/bug.h>
+#include <linux/printk.h>
/**
* Descriptor header, present in all types of descriptors
diff --git a/include/linux/soc/ti/k3-navss-ringacc.h b/include/linux/soc/ti/k3-navss-ringacc.h
index 0ad8f20..30fb903 100644
--- a/include/linux/soc/ti/k3-navss-ringacc.h
+++ b/include/linux/soc/ti/k3-navss-ringacc.h
@@ -2,7 +2,7 @@
/*
* TI K3 AM65x NAVSS Ring accelerator Manager (RA) subsystem driver
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
*/
#ifndef __SOC_TI_K3_NAVSS_RINGACC_API_H_
diff --git a/include/linux/soc/ti/k3-sec-proxy.h b/include/linux/soc/ti/k3-sec-proxy.h
index f34854c..c3a83f1 100644
--- a/include/linux/soc/ti/k3-sec-proxy.h
+++ b/include/linux/soc/ti/k3-sec-proxy.h
@@ -2,7 +2,7 @@
/*
* Texas Instruments' K3 Secure proxy
*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*
*/
diff --git a/include/linux/soc/ti/ti-udma.h b/include/linux/soc/ti/ti-udma.h
index 04e354f..89faf69 100644
--- a/include/linux/soc/ti/ti-udma.h
+++ b/include/linux/soc/ti/ti-udma.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
*/
diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h
index 7f99418..8e4c43c 100644
--- a/include/linux/soc/ti/ti_sci_protocol.h
+++ b/include/linux/soc/ti/ti_sci_protocol.h
@@ -3,7 +3,7 @@
* Texas Instruments System Control Interface Protocol
* Based on include/linux/soc/ti/ti_sci_protocol.h from Linux.
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Nishanth Menon
* Lokesh Vutla <lokeshvutla@ti.com>
*/
diff --git a/include/linux/usb/dwc3-omap.h b/include/linux/usb/dwc3-omap.h
index 62180e3..d5737ed 100644
--- a/include/linux/usb/dwc3-omap.h
+++ b/include/linux/usb/dwc3-omap.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* include/linux/usb/dwc3-omap.h
*
- * Copyright (c) 2014 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (c) 2014 Texas Instruments Incorporated - https://www.ti.com
*
* Designware SuperSpeed Glue
*/
diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h
index b3f4b8d..36572be 100644
--- a/include/linux/usb/gadget.h
+++ b/include/linux/usb/gadget.h
@@ -968,23 +968,23 @@
extern void usb_ep_autoconfig_reset(struct usb_gadget *);
-extern int usb_gadget_handle_interrupts(int index);
+extern int dm_usb_gadget_handle_interrupts(struct udevice *);
-#if CONFIG_IS_ENABLED(DM_USB_GADGET)
-int usb_gadget_initialize(int index);
-int usb_gadget_release(int index);
-int dm_usb_gadget_handle_interrupts(struct udevice *dev);
-#else
-#include <usb.h>
-static inline int usb_gadget_initialize(int index)
-{
- return board_usb_init(index, USB_INIT_DEVICE);
-}
+/**
+ * udc_device_get_by_index() - Get UDC udevice by index
+ * @index: UDC device index
+ * @udev: UDC udevice matching the index (if found)
+ *
+ * Return: 0 if Ok, -ve on error
+ */
+int udc_device_get_by_index(int index, struct udevice **udev);
-static inline int usb_gadget_release(int index)
-{
- return board_usb_cleanup(index, USB_INIT_DEVICE);
-}
-#endif
+/**
+ * udc_device_put() - Put UDC udevice
+ * @udev: UDC udevice
+ *
+ * Return: 0 if Ok, -ve on error
+ */
+int udc_device_put(struct udevice *udev);
#endif /* __LINUX_USB_GADGET_H */
diff --git a/include/linux/usb/otg.h b/include/linux/usb/otg.h
index 5d0dac9..e7e3d25 100644
--- a/include/linux/usb/otg.h
+++ b/include/linux/usb/otg.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* include/linux/usb/otg.h
*
- * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (c) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* USB OTG (On The Go) defines
*/
diff --git a/include/menu.h b/include/menu.h
index 64ce89b..6571c39 100644
--- a/include/menu.h
+++ b/include/menu.h
@@ -50,12 +50,17 @@
BKEY_DOWN,
BKEY_SELECT,
BKEY_QUIT,
+ BKEY_SAVE,
+
+ /* 'extra' keys, which are used by menus but not cedit */
BKEY_PLUS,
BKEY_MINUS,
BKEY_SPACE,
- BKEY_SAVE,
BKEY_COUNT,
+
+ /* Keys from here on are not used by cedit */
+ BKEY_FIRST_EXTRA = BKEY_PLUS,
};
/**
diff --git a/include/meson/sm.h b/include/meson/sm.h
new file mode 100644
index 0000000..fbaab1f
--- /dev/null
+++ b/include/meson/sm.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2023 SberDevices, Inc.
+ *
+ * Author: Alexey Romanov <avromanov@salutedevices.com>
+ */
+
+#ifndef __MESON_SM_CMD_H__
+#define __MESON_SM_CMD_H__
+
+enum meson_smc_cmd {
+ MESON_SMC_CMD_EFUSE_READ, /* read efuse memory */
+ MESON_SMC_CMD_EFUSE_WRITE, /* write efuse memory */
+ MESON_SMC_CMD_CHIP_ID_GET, /* readh chip unique id */
+ MESON_SMC_CMD_PWRDM_SET, /* do command at specified power domain */
+ MESON_SMC_CMD_COUNT,
+};
+
+#endif
diff --git a/include/mux-internal.h b/include/mux-internal.h
index 93e3a5c..67fa289 100644
--- a/include/mux-internal.h
+++ b/include/mux-internal.h
@@ -5,7 +5,7 @@
* Copyright (C) 2017 Axentia Technologies AB
* Author: Peter Rosin <peda@axentia.se>
*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/include/mux.h b/include/mux.h
index c92d887..e5deaba 100644
--- a/include/mux.h
+++ b/include/mux.h
@@ -10,7 +10,7 @@
* Copyright (C) 2017 Axentia Technologies AB
* Author: Peter Rosin <peda@axentia.se>
*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/include/net.h b/include/net.h
index 87b2ac7..3586c5c 100644
--- a/include/net.h
+++ b/include/net.h
@@ -16,6 +16,7 @@
#include <asm/cache.h>
#include <asm/byteorder.h> /* for nton* / ntoh* stuff */
#include <env.h>
+#include <hexdump.h>
#include <log.h>
#include <time.h>
#include <linux/if_ether.h>
@@ -29,6 +30,7 @@
#define DEBUG_DEV_PKT 0 /* Packets or info directed to the device */
#define DEBUG_NET_PKT 0 /* Packets on info on the network at large */
#define DEBUG_INT_STATE 0 /* Internal network state changes */
+#define DEBUG_NET_PKT_TRACE 0 /* Trace all packet data */
/*
* The number of receive packet buffers, and the required packet buffer
@@ -640,6 +642,8 @@
/* Transmit a packet */
static inline void net_send_packet(uchar *pkt, int len)
{
+ if (DEBUG_NET_PKT_TRACE)
+ print_hex_dump_bytes("tx: ", DUMP_PREFIX_OFFSET, pkt, len);
/* Currently no way to return errors from eth_send() */
(void) eth_send(pkt, len);
}
diff --git a/include/net/wget.h b/include/net/wget.h
index da0920d..6714f7e 100644
--- a/include/net/wget.h
+++ b/include/net/wget.h
@@ -17,6 +17,5 @@
};
#define DEBUG_WGET 0 /* Set to 1 for debug messages */
-#define SERVER_PORT 80
#define WGET_RETRY_COUNT 30
#define WGET_TIMEOUT 2000UL
diff --git a/include/ns16550.h b/include/ns16550.h
index e7e6866..7f48130 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -58,6 +58,7 @@
* struct ns16550_plat - information about a NS16550 port
*
* @base: Base register address
+ * @size: Size of register area in bytes
* @reg_width: IO accesses size of registers (in bytes, 1 or 4)
* @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...)
* @reg_offset: Offset to start of registers (normally 0)
@@ -67,7 +68,8 @@
* @bdf: PCI slot/function (pci_dev_t)
*/
struct ns16550_plat {
- unsigned long base;
+ ulong base;
+ ulong size;
int reg_width;
int reg_shift;
int reg_offset;
diff --git a/include/nvmxip.h b/include/nvmxip.h
index f4ef377..726fffe 100644
--- a/include/nvmxip.h
+++ b/include/nvmxip.h
@@ -29,4 +29,16 @@
lbaint_t lba;
};
+/**
+ * nvmxip_bind() - post binding treatments
+ * @dev: the NVMXIP device
+ *
+ * Create and probe a child block device.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int nvmxip_probe(struct udevice *udev);
+
#endif /* __DRIVER_NVMXIP_H__ */
diff --git a/include/of_live.h b/include/of_live.h
index 05e86ac..67bd5f0 100644
--- a/include/of_live.h
+++ b/include/of_live.h
@@ -9,6 +9,7 @@
#ifndef _OF_LIVE_H
#define _OF_LIVE_H
+struct abuf;
struct device_node;
/**
@@ -46,4 +47,21 @@
*/
void of_live_free(struct device_node *root);
+/**
+ * of_live_create_empty() - Create a new, empty tree
+ *
+ * @rootp: Returns the root node of the created tree
+ * Return: 0 if OK, -ENOMEM if out of memory
+ */
+int of_live_create_empty(struct device_node **rootp);
+
+/**
+ * of_live_flatten() - Create an FDT from a hierarchical tree
+ *
+ * @root: Root node of tree to convert
+ * @buf: Buffer to return the tree (inited by this function)
+ * Return: 0 if OK, -ENOMEM if out of memory
+ */
+int of_live_flatten(const struct device_node *root, struct abuf *buf);
+
#endif
diff --git a/include/os.h b/include/os.h
index 968412b..fc8a1b1 100644
--- a/include/os.h
+++ b/include/os.h
@@ -98,6 +98,16 @@
*/
int os_unlink(const char *pathname);
+/** os_persistent_fname() - Find the path to a test file
+ *
+ * @buf: Buffer to hold path
+ * @maxsize: Maximum size of buffer
+ * @fname: Leaf filename to find
+ * Returns: 0 on success, -ENOENT if file is not found, -ENOSPC if the buffer is
+ * too small
+ */
+int os_persistent_file(char *buf, int maxsize, const char *fname);
+
/**
* os_exit() - access to the OS exit() system call
*
diff --git a/include/part.h b/include/part.h
index 8504c0c..7374ec4 100644
--- a/include/part.h
+++ b/include/part.h
@@ -80,6 +80,93 @@
#endif
};
+/* Accessors for struct disk_partition field ->uuid */
+extern char *__invalid_use_of_disk_partition_uuid;
+
+static inline const char *disk_partition_uuid(const struct disk_partition *info)
+{
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
+ return info->uuid;
+#else
+ return __invalid_use_of_disk_partition_uuid;
+#endif
+}
+
+static inline void disk_partition_set_uuid(struct disk_partition *info,
+ const char *val)
+{
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
+ strlcpy(info->uuid, val, UUID_STR_LEN + 1);
+#endif
+}
+
+static inline void disk_partition_clr_uuid(struct disk_partition *info)
+{
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
+ *info->uuid = '\0';
+#endif
+}
+
+/* Accessors for struct disk_partition field ->type_guid */
+extern char *__invalid_use_of_disk_partition_type_guid;
+
+/**
+ * disk_partition_type_guid() - get partition type GUID
+ *
+ * By using this function to get the partition type GUID we can use
+ * 'if (IS_ENABLED(CONFIG_PARTITION_TYPE_GUID))' instead of
+ * '#ifdef CONFIG_PARTITION_TYPE_GUID'.
+ *
+ * @info: partition information
+ * Return: partition type GUID
+ */
+static inline const
+char *disk_partition_type_guid(const struct disk_partition *info)
+{
+#ifdef CONFIG_PARTITION_TYPE_GUID
+ return info->type_guid;
+#else
+ return __invalid_use_of_disk_partition_type_guid;
+#endif
+}
+
+/**
+ * disk_partition_set_type_guid() - set partition type GUID
+ *
+ * By using this function to set the partition type GUID we can use
+ * 'if (IS_ENABLED(CONFIG_PARTITION_TYPE_GUID))' instead of
+ * '#ifdef CONFIG_PARTITION_TYPE_GUID'.
+ *
+ * @info: partition information
+ * @val: partition type GUID as string
+ */
+static inline void disk_partition_set_type_guid(struct disk_partition *info,
+ const char *val)
+{
+#ifdef CONFIG_PARTITION_TYPE_GUID
+ strlcpy(info->type_guid, val, UUID_STR_LEN + 1);
+#endif
+}
+
+static inline void disk_partition_clr_type_guid(struct disk_partition *info)
+{
+#ifdef CONFIG_PARTITION_TYPE_GUID
+ *info->type_guid = '\0';
+#endif
+}
+
+/* Accessors for struct disk_partition field ->sys_ind */
+extern int __invalid_use_of_disk_partition_sys_ind;
+
+static inline uint disk_partition_sys_ind(const struct disk_partition *info)
+{
+#ifdef CONFIG_DOS_PARTITION
+ return info->sys_ind;
+#else
+ return __invalid_use_of_disk_partition_sys_ind;
+#endif
+}
+
struct disk_part {
int partnum;
struct disk_partition gpt_part_info;
@@ -113,7 +200,7 @@
* contained with the interface's data structure. There is no global
* numbering for block devices, so the interface name must be provided.
*
- * @dev_desc: Block device descriptor
+ * @desc: Block device descriptor
* @part: Partition number to read
* @part_type: Partition driver to use, or PART_TYPE_UNKNOWN to automatically
* choose a driver
@@ -121,24 +208,24 @@
*
* Return: 0 on success, negative errno on failure
*/
-int part_get_info_by_type(struct blk_desc *dev_desc, int part, int part_type,
+int part_get_info_by_type(struct blk_desc *desc, int part, int part_type,
struct disk_partition *info);
-int part_get_info(struct blk_desc *dev_desc, int part,
+int part_get_info(struct blk_desc *desc, int part,
struct disk_partition *info);
/**
* part_get_info_whole_disk() - get partition info for the special case of
* a partition occupying the entire disk.
*
- * @dev_desc: block device descriptor
+ * @desc: block device descriptor
* @info: returned partition information
* Return: 0 on success
*/
-int part_get_info_whole_disk(struct blk_desc *dev_desc,
+int part_get_info_whole_disk(struct blk_desc *desc,
struct disk_partition *info);
-void part_print(struct blk_desc *dev_desc);
-void part_init(struct blk_desc *dev_desc);
-void dev_print(struct blk_desc *dev_desc);
+void part_print(struct blk_desc *desc);
+void part_init(struct blk_desc *desc);
+void dev_print(struct blk_desc *desc);
/**
* blk_get_device_by_str() - Get a block device given its interface/hw partition
@@ -162,11 +249,11 @@
* containing the device number (e.g. "2") or the device number
* and hardware partition number (e.g. "2.4") for devices that
* support it (currently only MMC).
- * @dev_desc: Returns a pointer to the block device on success
+ * @desc: Returns a pointer to the block device on success
* Return: block device number (local to the interface), or -1 on error
*/
int blk_get_device_by_str(const char *ifname, const char *dev_str,
- struct blk_desc **dev_desc);
+ struct blk_desc **desc);
/**
* blk_get_device_part_str() - Get a block device and partition
@@ -196,7 +283,7 @@
*
* @ifname: Interface name (e.g. "ide", "scsi")
* @dev_part_str: Device and partition string
- * @dev_desc: Returns a pointer to the block device on success
+ * @desc: Returns a pointer to the block device on success
* @info: Returns partition information
* @allow_whole_dev: true to allow the user to select partition 0
* (which means the whole device), false to require a valid
@@ -205,22 +292,22 @@
*
*/
int blk_get_device_part_str(const char *ifname, const char *dev_part_str,
- struct blk_desc **dev_desc,
+ struct blk_desc **desc,
struct disk_partition *info, int allow_whole_dev);
/**
* part_get_info_by_name() - Search for a partition by name
* among all available registered partitions
*
- * @dev_desc: block device descriptor
+ * @desc: block device descriptor
* @name: the specified table entry name
* @info: returns the disk partition info
*
* Return: the partition number on match (starting on 1), -1 on no match,
* otherwise error
*/
-int part_get_info_by_name(struct blk_desc *dev_desc,
- const char *name, struct disk_partition *info);
+int part_get_info_by_name(struct blk_desc *desc, const char *name,
+ struct disk_partition *info);
/**
* Get partition info from device number and partition name.
@@ -252,11 +339,11 @@
* (like "device_num#partition_name") or a device number plus a partition number
* separated by a ":". For example both "0#misc" and "0:1" can be valid
* partition descriptions for a given interface. If the partition is found, sets
- * dev_desc and part_info accordingly with the information of the partition.
+ * desc and part_info accordingly with the information of the partition.
*
* @dev_iface: Device interface
* @dev_part_str: Input partition description, like "0#misc" or "0:1"
- * @dev_desc: Place to store the device description pointer
+ * @desc: Place to store the device description pointer
* @part_info: Place to store the partition information
* @allow_whole_dev: true to allow the user to select partition 0
* (which means the whole device), false to require a valid
@@ -265,7 +352,7 @@
*/
int part_get_info_by_dev_and_name_or_num(const char *dev_iface,
const char *dev_part_str,
- struct blk_desc **dev_desc,
+ struct blk_desc **desc,
struct disk_partition *part_info,
int allow_whole_dev);
@@ -276,12 +363,12 @@
* (DOS, ISO). Generates partition name out of the device type and partition
* number.
*
- * @dev_desc: pointer to the block device
+ * @desc: pointer to the block device
* @part_num: partition number for which the name is generated
* @name: buffer where the name is written
*/
-void part_set_generic_name(const struct blk_desc *dev_desc,
- int part_num, char *name);
+void part_set_generic_name(const struct blk_desc *desc, int part_num,
+ char *name);
extern const struct block_drvr block_drvr[];
#else
@@ -289,26 +376,25 @@
{ return NULL; }
static inline struct blk_desc *mg_disk_get_dev(int dev) { return NULL; }
-static inline int part_get_info(struct blk_desc *dev_desc, int part,
+static inline int part_get_info(struct blk_desc *desc, int part,
struct disk_partition *info) { return -1; }
-static inline int part_get_info_whole_disk(struct blk_desc *dev_desc,
+static inline int part_get_info_whole_disk(struct blk_desc *desc,
struct disk_partition *info)
{ return -1; }
-static inline void part_print(struct blk_desc *dev_desc) {}
-static inline void part_init(struct blk_desc *dev_desc) {}
-static inline void dev_print(struct blk_desc *dev_desc) {}
+static inline void part_print(struct blk_desc *desc) {}
+static inline void part_init(struct blk_desc *desc) {}
+static inline void dev_print(struct blk_desc *desc) {}
static inline int blk_get_device_by_str(const char *ifname, const char *dev_str,
- struct blk_desc **dev_desc)
+ struct blk_desc **desc)
{ return -1; }
static inline int blk_get_device_part_str(const char *ifname,
const char *dev_part_str,
- struct blk_desc **dev_desc,
+ struct blk_desc **desc,
struct disk_partition *info,
int allow_whole_dev)
-{ *dev_desc = NULL; return -1; }
+{ *desc = NULL; return -1; }
-static inline int part_get_info_by_name(struct blk_desc *dev_desc,
- const char *name,
+static inline int part_get_info_by_name(struct blk_desc *desc, const char *name,
struct disk_partition *info)
{
return -ENOENT;
@@ -317,34 +403,17 @@
static inline int
part_get_info_by_dev_and_name_or_num(const char *dev_iface,
const char *dev_part_str,
- struct blk_desc **dev_desc,
+ struct blk_desc **desc,
struct disk_partition *part_info,
int allow_whole_dev)
{
- *dev_desc = NULL;
+ *desc = NULL;
return -ENOSYS;
}
#endif
-/**
- * part_get_bootable() - Find the first bootable partition
- *
- * @desc: Block-device descriptor
- * @return first bootable partition, or 0 if there is none
- */
-int part_get_bootable(struct blk_desc *desc);
-
struct udevice;
/**
- * part_create_block_devices - Create block devices for disk partitions
- *
- * Create UCLASS_PARTITION udevices for each of disk partitions in @parent
- *
- * @blk_dev: Whole disk device
- */
-int part_create_block_devices(struct udevice *blk_dev);
-
-/**
* disk_blk_read() - read blocks from a disk partition
*
* @dev: Device to read from (UCLASS_PARTITION)
@@ -411,29 +480,29 @@
/**
* @get_info: Get information about a partition
*
- * @get_info.dev_desc: Block device descriptor
+ * @get_info.desc: Block device descriptor
* @get_info.part: Partition number (1 = first)
* @get_info.info: Returns partition information
*/
- int (*get_info)(struct blk_desc *dev_desc, int part,
+ int (*get_info)(struct blk_desc *desc, int part,
struct disk_partition *info);
/**
* @print: Print partition information
*
- * @print.dev_desc: Block device descriptor
+ * @print.desc: Block device descriptor
*/
- void (*print)(struct blk_desc *dev_desc);
+ void (*print)(struct blk_desc *desc);
/**
* @test: Test if a device contains this partition type
*
- * @test.dev_desc: Block device descriptor
+ * @test.desc: Block device descriptor
* @test.Return:
* 0 if the block device appears to contain this partition type,
* -ve if not
*/
- int (*test)(struct blk_desc *dev_desc);
+ int (*test)(struct blk_desc *desc);
};
/* Declare a new U-Boot partition 'driver' */
@@ -447,19 +516,18 @@
/**
* write_gpt_table() - Write the GUID Partition Table to disk
*
- * @dev_desc: block device descriptor
+ * @desc: block device descriptor
* @gpt_h: pointer to GPT header representation
* @gpt_e: pointer to GPT partition table entries
*
* Return: zero on success, otherwise error
*/
-int write_gpt_table(struct blk_desc *dev_desc,
- gpt_header *gpt_h, gpt_entry *gpt_e);
+int write_gpt_table(struct blk_desc *desc, gpt_header *gpt_h, gpt_entry *gpt_e);
/**
* gpt_fill_pte() - Fill the GPT partition table entry
*
- * @dev_desc: block device descriptor
+ * @desc: block device descriptor
* @gpt_h: GPT header representation
* @gpt_e: GPT partition table entries
* @partitions: list of partitions
@@ -467,55 +535,54 @@
*
* Return: zero on success
*/
-int gpt_fill_pte(struct blk_desc *dev_desc,
- gpt_header *gpt_h, gpt_entry *gpt_e,
+int gpt_fill_pte(struct blk_desc *desc, gpt_header *gpt_h, gpt_entry *gpt_e,
struct disk_partition *partitions, int parts);
/**
* gpt_fill_header() - Fill the GPT header
*
- * @dev_desc: block device descriptor
+ * @desc: block device descriptor
* @gpt_h: GPT header representation
* @str_guid: disk guid string representation
* @parts_count: number of partitions
*
* Return: error on str_guid conversion error
*/
-int gpt_fill_header(struct blk_desc *dev_desc, gpt_header *gpt_h,
- char *str_guid, int parts_count);
+int gpt_fill_header(struct blk_desc *desc, gpt_header *gpt_h, char *str_guid,
+ int parts_count);
/**
* gpt_restore() - Restore GPT partition table
*
- * @dev_desc: block device descriptor
+ * @desc: block device descriptor
* @str_disk_guid: disk GUID
* @partitions: list of partitions
* @parts_count: number of partitions
*
* Return: 0 on success
*/
-int gpt_restore(struct blk_desc *dev_desc, char *str_disk_guid,
+int gpt_restore(struct blk_desc *desc, char *str_disk_guid,
struct disk_partition *partitions, const int parts_count);
/**
* is_valid_gpt_buf() - Ensure that the Primary GPT information is valid
*
- * @dev_desc: block device descriptor
+ * @desc: block device descriptor
* @buf: buffer which contains the MBR and Primary GPT info
*
* Return: 0 on success, otherwise error
*/
-int is_valid_gpt_buf(struct blk_desc *dev_desc, void *buf);
+int is_valid_gpt_buf(struct blk_desc *desc, void *buf);
/**
* write_mbr_and_gpt_partitions() - write MBR, Primary GPT and Backup GPT
*
- * @dev_desc: block device descriptor
+ * @desc: block device descriptor
* @buf: buffer which contains the MBR and Primary GPT info
*
* Return: 0 on success, otherwise error
*/
-int write_mbr_and_gpt_partitions(struct blk_desc *dev_desc, void *buf);
+int write_mbr_and_gpt_partitions(struct blk_desc *desc, void *buf);
/**
* gpt_verify_headers() - Read and check CRC32 of the GPT's header
@@ -523,24 +590,24 @@
*
* As a side effect if sets gpt_head and gpt_pte so they point to GPT data.
*
- * @dev_desc: block device descriptor
+ * @desc: block device descriptor
* @gpt_head: pointer to GPT header data read from medium
* @gpt_pte: pointer to GPT partition table enties read from medium
*
* Return: 0 on success, otherwise error
*/
-int gpt_verify_headers(struct blk_desc *dev_desc, gpt_header *gpt_head,
+int gpt_verify_headers(struct blk_desc *desc, gpt_header *gpt_head,
gpt_entry **gpt_pte);
/**
* gpt_repair_headers() - Function to repair the GPT's header
* and partition table entries (PTE)
*
- * @dev_desc: block device descriptor
+ * @desc: block device descriptor
*
* Return: 0 on success, otherwise error
*/
-int gpt_repair_headers(struct blk_desc *dev_desc);
+int gpt_repair_headers(struct blk_desc *desc);
/**
* gpt_verify_partitions() - Function to check if partitions' name, start and
@@ -550,7 +617,7 @@
* provided in '$partitions' environment variable. Specificially, name, start
* and size of the partition is checked.
*
- * @dev_desc: block device descriptor
+ * @desc: block device descriptor
* @partitions: partition data read from '$partitions' env variable
* @parts: number of partitions read from '$partitions' env variable
* @gpt_head: pointer to GPT header data read from medium
@@ -558,7 +625,7 @@
*
* Return: 0 on success, otherwise error
*/
-int gpt_verify_partitions(struct blk_desc *dev_desc,
+int gpt_verify_partitions(struct blk_desc *desc,
struct disk_partition *partitions, int parts,
gpt_header *gpt_head, gpt_entry **gpt_pte);
@@ -569,12 +636,12 @@
* This function reads the GUID string from a block device whose descriptor
* is provided.
*
- * @dev_desc: block device descriptor
+ * @desc: block device descriptor
* @guid: pre-allocated string in which to return the GUID
*
* Return: 0 on success, otherwise error
*/
-int get_disk_guid(struct blk_desc *dev_desc, char *guid);
+int get_disk_guid(struct blk_desc *desc, char *guid);
#endif
@@ -591,12 +658,12 @@
/**
* write_mbr_sector() - write DOS MBR
*
- * @dev_desc: block device descriptor
+ * @desc: block device descriptor
* @buf: buffer which contains the MBR
*
* Return: 0 on success, otherwise error
*/
-int write_mbr_sector(struct blk_desc *dev_desc, void *buf);
+int write_mbr_sector(struct blk_desc *desc, void *buf);
int write_mbr_partitions(struct blk_desc *dev,
struct disk_partition *p, int count, unsigned int disksig);
@@ -635,12 +702,24 @@
*/
int part_get_type_by_name(const char *name);
+/**
+ * part_get_bootable() - Find the first bootable partition
+ *
+ * @desc: Block-device descriptor
+ * @return first bootable partition, or 0 if there is none
+ */
+int part_get_bootable(struct blk_desc *desc);
+
#else
static inline int part_driver_get_count(void)
{ return 0; }
static inline struct part_driver *part_driver_get_first(void)
{ return NULL; }
+
+static inline bool part_get_bootable(struct blk_desc *desc)
+{ return false; }
+
#endif /* CONFIG_PARTITIONS */
#endif /* _PART_H */
diff --git a/include/part_efi.h b/include/part_efi.h
index c68529b..59b7895 100644
--- a/include/part_efi.h
+++ b/include/part_efi.h
@@ -60,6 +60,20 @@
EFI_GUID( 0x3de21764, 0x95bd, 0x54bd, \
0xa5, 0xc3, 0x4a, 0xbe, 0x78, 0x6f, 0x38, 0xa8)
+/* Special ChromiumOS things */
+#define PARTITION_CROS_KERNEL \
+ EFI_GUID(0xfe3a2a5d, 0x4f32, 0x41a7, \
+ 0xb7, 0x25, 0xac, 0xcc, 0x32, 0x85, 0xa3, 0x09)
+#define PARTITION_CROS_ROOT \
+ EFI_GUID(0x3cb8e202, 0x3b7e, 0x47dd, \
+ 0x8a, 0x3c, 0x7f, 0xf2, 0xa1, 0x3c, 0xfc, 0xec)
+#define PARTITION_CROS_FIRMWARE \
+ EFI_GUID(0xcab6e88e, 0xabf3, 0x4102, \
+ 0xa0, 0x7a, 0xd4, 0xbb, 0x9b, 0xe3, 0xc1, 0xd3)
+#define PARTITION_CROS_RESERVED \
+ EFI_GUID(0x2e0a753d, 0x9e48, 0x43b0, \
+ 0x83, 0x37, 0xb1, 0x51, 0x92, 0xcb, 0x1b, 0x5e)
+
/* linux/include/efi.h */
typedef u16 efi_char16_t;
diff --git a/include/phy.h b/include/phy.h
index f023a3c..27effdb 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -172,14 +172,6 @@
};
/**
- * phy_init() - Initializes the PHY drivers
- * This function registers all available PHY drivers
- *
- * @return: 0 if OK, -ve on error
- */
-int phy_init(void);
-
-/**
* phy_reset() - Resets the specified PHY
* Issues a reset of the PHY and waits for it to complete
*
diff --git a/include/post.h b/include/post.h
index 4112069..6e88d55 100644
--- a/include/post.h
+++ b/include/post.h
@@ -105,9 +105,6 @@
int post_run (char *name, int flags);
int post_info (char *name);
int post_log (char *format, ...);
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
-void post_reloc (void);
-#endif
unsigned long post_time_ms (unsigned long base);
/**
diff --git a/include/power/max77663.h b/include/power/max77663.h
new file mode 100644
index 0000000..b3ae3da
--- /dev/null
+++ b/include/power/max77663.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#ifndef _MAX77663_H_
+#define _MAX77663_H_
+
+#define MAX77663_LDO_NUM 9
+#define MAX77663_SD_NUM 5
+
+/* Drivers name */
+#define MAX77663_LDO_DRIVER "max77663_ldo"
+#define MAX77663_SD_DRIVER "max77663_sd"
+#define MAX77663_RST_DRIVER "max77663_rst"
+
+/* Step-Down (SD) Regulator calculations */
+#define SD_STATUS_MASK 0x30
+
+#define SD0_VOLT_MAX_HEX 0x40
+#define SD1_VOLT_MAX_HEX 0x4c
+#define SD_VOLT_MAX_HEX 0xff
+#define SD_VOLT_MIN_HEX 0x02
+
+#define SD0_VOLT_MAX 1400000
+#define SD1_VOLT_MAX 1550000
+#define SD_VOLT_MAX 3787500
+#define SD_VOLT_MIN 625000
+
+#define SD_VOLT_BASE 600000
+
+/* Low-Dropout Linear (LDO) Regulator calculations */
+#define LDO_STATUS_MASK 0xc0
+#define LDO_VOLT_MASK 0x3f
+#define LDO_VOLT_MAX_HEX 0x3f
+
+#define LDO01_VOLT_MAX 2375000
+#define LDO4_VOLT_MAX 1587500
+#define LDO_VOLT_MAX 3950000
+
+#define LDO_VOLT_BASE 800000
+
+#define MAX77663_REG_ONOFF_CFG1 0x41
+#define ONOFF_SFT_RST BIT(7)
+#define ONOFF_PWR_OFF BIT(1)
+
+#endif /* _MAX77663_H_ */
diff --git a/include/power/palmas.h b/include/power/palmas.h
index df5f15c..0a61205 100644
--- a/include/power/palmas.h
+++ b/include/power/palmas.h
@@ -2,6 +2,10 @@
#define TPS659038 0x1
#define TPS65917 0x2
+struct palmas_priv {
+ struct udevice *chip2;
+};
+
/* I2C device address for pmic palmas */
#define PALMAS_I2C_ADDR (0x12 >> 1)
#define PALMAS_LDO_NUM 11
@@ -10,6 +14,7 @@
/* Drivers name */
#define PALMAS_LDO_DRIVER "palmas_ldo"
#define PALMAS_SMPS_DRIVER "palmas_smps"
+#define PALMAS_RST_DRIVER "palmas_rst"
#define PALMAS_SMPS_VOLT_MASK 0x7F
#define PALMAS_SMPS_RANGE_MASK 0x80
@@ -24,3 +29,9 @@
#define PALMAS_LDO_MODE_MASK 0x1
#define PALMAS_LDO_STATUS_MASK 0x10
#define PALMAS_LDO_BYPASS_EN 0x40
+
+#define PALMAS_DEV_CTRL 0xA0
+#define SW_RST BIT(1)
+#define DEV_OFF 0x00
+#define PALMAS_INT3_MASK 0x1B
+#define MASK_VBUS BIT(7)
diff --git a/include/power/regulator.h b/include/power/regulator.h
index ff1bfc2..200652c 100644
--- a/include/power/regulator.h
+++ b/include/power/regulator.h
@@ -134,6 +134,7 @@
enum regulator_flag {
REGULATOR_FLAG_AUTOSET_UV = 1 << 0,
REGULATOR_FLAG_AUTOSET_UA = 1 << 1,
+ REGULATOR_FLAG_AUTOSET_DONE = 1 << 2,
};
/**
diff --git a/include/power/tps62362.h b/include/power/tps62362.h
index f0fc538..df06c28 100644
--- a/include/power/tps62362.h
+++ b/include/power/tps62362.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * (C) Copyright 2014 Texas Instruments Incorporated - http://www.ti.com
+ * (C) Copyright 2014 Texas Instruments Incorporated - https://www.ti.com
* Author: Felipe Balbi <balbi@ti.com>
*/
diff --git a/include/power/tps65217.h b/include/power/tps65217.h
index 669a94a..7862b31 100644
--- a/include/power/tps65217.h
+++ b/include/power/tps65217.h
@@ -3,7 +3,7 @@
* (C) Copyright 2011-2013
* Texas Instruments, <www.ti.com>
*
- * For more details, please see the TRM at http://www.ti.com/product/tps65217a
+ * For more details, please see the TRM at https://www.ti.com/product/tps65217a
*/
#ifndef __POWER_TPS65217_H__
diff --git a/include/power/tps65910.h b/include/power/tps65910.h
index 21b2a21..ccc759a 100644
--- a/include/power/tps65910.h
+++ b/include/power/tps65910.h
@@ -3,7 +3,7 @@
* (C) Copyright 2011-2013
* Texas Instruments, <www.ti.com>
*
- * For more details, please see the TRM at http://www.ti.com/product/tps65910
+ * For more details, please see the TRM at https://www.ti.com/product/tps65910
*/
#ifndef __POWER_TPS65910_H__
#define __POWER_TPS65910_H__
diff --git a/include/power/tps65910_pmic.h b/include/power/tps65910_pmic.h
index 6621478..2026ec2 100644
--- a/include/power/tps65910_pmic.h
+++ b/include/power/tps65910_pmic.h
@@ -17,6 +17,12 @@
#define TPS65910_SUPPLY_STATE_OFF 0x0
#define TPS65910_SUPPLY_STATE_ON 0x1
+/* TPS65910 DEVICE_CTRL bits */
+#define PWR_OFF_SEQ BIT(7)
+#define DEV_OFF_RST BIT(3)
+#define DEV_ON BIT(2)
+#define DEV_OFF BIT(0)
+
/* i2c registers */
enum {
TPS65910_REG_RTC_SEC = 0x00,
@@ -125,5 +131,50 @@
#define TPS65910_BUCK_DRIVER "tps65910_buck"
#define TPS65910_BOOST_DRIVER "tps65910_boost"
#define TPS65910_LDO_DRIVER "tps65910_ldo"
+#define TPS65910_RST_DRIVER "tps65910_rst"
+
+/* tps65911 i2c registers */
+enum {
+ TPS65911_REG_VIO = 0x20,
+ TPS65911_REG_VDD1,
+ TPS65911_REG_VDD1_OP,
+ TPS65911_REG_VDD1_SR,
+ TPS65911_REG_VDD2,
+ TPS65911_REG_VDD2_OP,
+ TPS65911_REG_VDD2_SR,
+ TPS65911_REG_VDDCTRL,
+ TPS65911_REG_VDDCTRL_OP,
+ TPS65911_REG_VDDCTRL_SR,
+ TPS65911_REG_LDO1 = 0x30,
+ TPS65911_REG_LDO2,
+ TPS65911_REG_LDO5,
+ TPS65911_REG_LDO8,
+ TPS65911_REG_LDO7,
+ TPS65911_REG_LDO6,
+ TPS65911_REG_LDO4,
+ TPS65911_REG_LDO3,
+};
+
+#define TPS65911_VDD_NUM 4
+#define TPS65911_LDO_NUM 8
+
+#define TPS65911_VDD_VOLT_MAX 1500000
+#define TPS65911_VDD_VOLT_MIN 600000
+#define TPS65911_VDD_VOLT_BASE 562500
+
+#define TPS65911_LDO_VOLT_MAX 3300000
+#define TPS65911_LDO_VOLT_BASE 800000
+
+#define TPS65911_LDO_SEL_MASK (0x3f << 2)
+
+#define TPS65911_LDO124_VOLT_MAX_HEX 0x32
+#define TPS65911_LDO358_VOLT_MAX_HEX 0x19
+#define TPS65911_LDO358_VOLT_MIN_HEX 0x02
+
+#define TPS65911_LDO124_VOLT_STEP 50000
+#define TPS65911_LDO358_VOLT_STEP 100000
+
+#define TPS65911_VDD_DRIVER "tps65911_vdd"
+#define TPS65911_LDO_DRIVER "tps65911_ldo"
#endif /* __TPS65910_PMIC_H_ */
diff --git a/include/power/tps80031.h b/include/power/tps80031.h
new file mode 100644
index 0000000..983c841
--- /dev/null
+++ b/include/power/tps80031.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#ifndef _TPS80031_H_
+#define _TPS80031_H_
+
+#define TPS80031_LDO_NUM 9
+#define TPS80031_SMPS_NUM 5
+
+/* Drivers name */
+#define TPS80031_LDO_DRIVER "tps80031_ldo"
+#define TPS80031_SMPS_DRIVER "tps80031_smps"
+#define TPS80031_RST_DRIVER "tps80031_rst"
+
+#define TPS80031_SMPS_OFFSET 0xe0
+#define TPS80031_OFFSET_FLAG BIT(0)
+
+#define REGULATOR_STATUS_MASK 0x3
+#define REGULATOR_MODE_ON 0x1
+
+/* Switched-Mode Power Supply Regulator calculations */
+#define SMPS_VOLT_MASK 0x3f
+#define SMPS_VOLT_LINEAR_HEX 0x39
+#define SMPS_VOLT_NLINEAR_HEX 0x3a
+#define SMPS_VOLT_LINEAR 1300000
+#define SMPS_VOLT_BASE 600000
+#define SMPS_VOLT_BASE_OFFSET 700000
+
+/* Low-Dropout Linear (LDO) Regulator calculations */
+#define LDO_VOLT_MASK 0x3f
+#define LDO_VOLT_MAX_HEX 0x18
+#define LDO_VOLT_MIN_HEX 0x01
+#define LDO_VOLT_MAX 3360000
+#define LDO_VOLT_MIN 1018000
+#define LDO_VOLT_BASE 916000
+
+#define TPS80031_PHOENIX_DEV_ON 0x25
+#define SW_RESET BIT(6)
+#define DEVOFF BIT(0)
+
+/* register groups */
+enum {
+ CTRL,
+ VOLT,
+ OFFSET,
+};
+
+#endif /* _TPS80031_H_ */
diff --git a/include/relocate.h b/include/relocate.h
index 2dbfd90..8ca25e1 100644
--- a/include/relocate.h
+++ b/include/relocate.h
@@ -39,28 +39,4 @@
*/
int do_elf_reloc_fixups(void);
-/**
- * manual_reloc() - Manually relocate a pointer if needed
- *
- * This is a nop in almost all cases, except for the systems with a broken gcc
- * which need to manually relocate some things.
- *
- * @ptr: Pointer to relocate
- * Return: new pointer value
- */
-static inline void *manual_reloc(void *ptr)
-{
-#ifndef USE_HOSTCC
- if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC))
- return ptr + gd->reloc_off;
-#endif
- return ptr;
-}
-
-#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC)
-#define MANUAL_RELOC(ptr) (ptr) = manual_reloc(ptr)
-#else
-#define MANUAL_RELOC(ptr) (void)(ptr)
-#endif
-
#endif /* _RELOCATE_H_ */
diff --git a/include/remoteproc.h b/include/remoteproc.h
index f48054d..a11dc8a 100644
--- a/include/remoteproc.h
+++ b/include/remoteproc.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) Copyright 2015
- * Texas Instruments Incorporated - http://www.ti.com/
+ * Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef _RPROC_H_
diff --git a/include/renesas/rzg2l-pfc.h b/include/renesas/rzg2l-pfc.h
new file mode 100644
index 0000000..2df17ec
--- /dev/null
+++ b/include/renesas/rzg2l-pfc.h
@@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * RZ/G2L Pin Function Controller
+ *
+ * Copyright (C) 2021-2023 Renesas Electronics Corp.
+ */
+
+#ifndef RENESAS_RZG2L_PFC_H
+#define RENESAS_RZG2L_PFC_H
+
+/* PIN capabilities */
+#define PIN_CFG_IOLH_A BIT(0)
+#define PIN_CFG_IOLH_B BIT(1)
+#define PIN_CFG_SR BIT(2)
+#define PIN_CFG_IEN BIT(3)
+#define PIN_CFG_PUPD BIT(4)
+#define PIN_CFG_IO_VMC_SD0 BIT(5)
+#define PIN_CFG_IO_VMC_SD1 BIT(6)
+#define PIN_CFG_IO_VMC_QSPI BIT(7)
+#define PIN_CFG_IO_VMC_ETH0 BIT(8)
+#define PIN_CFG_IO_VMC_ETH1 BIT(9)
+#define PIN_CFG_FILONOFF BIT(10)
+#define PIN_CFG_FILNUM BIT(11)
+#define PIN_CFG_FILCLKSEL BIT(12)
+
+#define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \
+ PIN_CFG_SR | \
+ PIN_CFG_PUPD | \
+ PIN_CFG_FILONOFF | \
+ PIN_CFG_FILNUM | \
+ PIN_CFG_FILCLKSEL)
+
+#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \
+ PIN_CFG_FILONOFF | \
+ PIN_CFG_FILNUM | \
+ PIN_CFG_FILCLKSEL)
+
+/* GPIO port data macros:
+ * n indicates number of pins in the port, a is the register index
+ * and f is pin configuration capabilities supported.
+ */
+#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f))
+#define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28)
+#define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >> 20)
+#define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0))
+
+/* Dedicated pin data macros:
+ * BIT(31) indicates dedicated pin, p is the register index while
+ * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits
+ * (b * 8) and f is the pin configuration capabilities supported.
+ */
+#define RZG2L_SINGLE_PIN BIT(31)
+#define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \
+ ((p) << 24) | ((b) << 20) | (f))
+#define RZG2L_SINGLE_PIN_GET_PORT_OFFSET(x) (((x) & GENMASK(30, 24)) >> 24)
+#define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20)
+#define RZG2L_SINGLE_PIN_GET_CFGS(x) ((x) & GENMASK(19, 0))
+
+/* Pinmux data encoded in the device tree uses:
+ * 16 lower bits [15:0] for pin identifier
+ * 16 higher bits [31:16] for pin mux function
+ */
+#define MUX_PIN_ID_MASK GENMASK(15, 0)
+#define MUX_FUNC_MASK GENMASK(31, 16)
+#define RZG2L_PINS_PER_PORT 8
+#define RZG2L_PINMUX_TO_PORT(conf) (((conf) & MUX_PIN_ID_MASK) / RZG2L_PINS_PER_PORT)
+#define RZG2L_PINMUX_TO_PIN(conf) (((conf) & MUX_PIN_ID_MASK) % RZG2L_PINS_PER_PORT)
+#define RZG2L_PINMUX_TO_FUNC(conf) (((conf) & MUX_FUNC_MASK) >> 16)
+
+/* Register offsets and values. */
+#define P(n) (0x0000 + 0x10 + (n))
+#define PM(n) (0x0100 + 0x20 + (n) * 2)
+#define PMC(n) (0x0200 + 0x10 + (n))
+#define PFC(n) (0x0400 + 0x40 + (n) * 4)
+#define PIN(n) (0x0800 + 0x10 + (n))
+#define IOLH(n) (0x1000 + (n) * 8)
+#define IEN(n) (0x1800 + (n) * 8)
+#define PWPR 0x3014
+#define SD_CH(n) (0x3000 + (n) * 4)
+#define QSPI 0x3008
+
+#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
+#define PVDD_3300 0 /* I/O domain voltage >= 3.3V */
+
+#define PWPR_B0WI BIT(7) /* Bit Write Disable */
+#define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */
+
+#define PM_MASK 0x03
+#define PVDD_MASK 0x01
+#define PFC_MASK 0x07
+#define IEN_MASK 0x01
+#define IOLH_MASK 0x03
+
+#define PM_HIGH_Z 0x0
+#define PM_INPUT 0x1
+#define PM_OUTPUT 0x2
+#define PM_OUTPUT_IEN 0x3
+
+struct rzg2l_pfc_data {
+ void __iomem *base;
+ uint num_dedicated_pins;
+ uint num_ports;
+ uint num_pins;
+ const u32 *gpio_configs;
+};
+
+int rzg2l_pfc_enable(struct udevice *dev);
+bool rzg2l_port_validate(const struct rzg2l_pfc_data *data, u32 port, u8 pin);
+
+#endif /* RENESAS_RZG2L_PFC_H */
diff --git a/include/rkmtd.h b/include/rkmtd.h
new file mode 100644
index 0000000..145fede
--- /dev/null
+++ b/include/rkmtd.h
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Driver interface derived from:
+ * /include/sandbox_host.h
+ * Copyright 2022 Google LLC
+ *
+ * Copyright 2023 Johan Jonker <jbx6244@gmail.com>
+ */
+
+#ifndef __RKMTD__
+#define __RKMTD__
+
+#include <part_efi.h>
+#include <uuid.h>
+
+#define LBA 64 + 512 + 33
+
+#define RK_TAG 0xFCDC8C3B
+#define NFC_SYS_DATA_SIZE 4
+#define BLK_SIZE 2048
+#define STEP_SIZE 1024
+#define BUF_SIZE 512 * 512
+
+struct nand_para_info {
+ u8 id_bytes;
+ u8 nand_id[6];
+ u8 vendor;
+ u8 die_per_chip;
+ u8 sec_per_page;
+ u16 page_per_blk;
+ u8 cell;
+ u8 plane_per_die;
+ u16 blk_per_plane;
+ u16 operation_opt;
+ u8 lsb_mode;
+ u8 read_retry_mode;
+ u8 ecc_bits;
+ u8 access_freq;
+ u8 opt_mode;
+ u8 die_gap;
+ u8 bad_block_mode;
+ u8 multi_plane_mode;
+ u8 slc_mode;
+ u8 reserved[5];
+};
+
+struct bootblk {
+ int blk;
+ int boot_size;
+ int offset;
+};
+
+struct rkmtd_dev {
+ struct udevice *dev;
+ struct blk_desc *desc;
+ char *label;
+ legacy_mbr *mbr;
+ gpt_header *gpt_h;
+ gpt_header *gpt_h2;
+ gpt_entry *gpt_e;
+ char *check;
+ char *idb;
+ char *str;
+ char uuid_part_str[UUID_STR_LEN + 1];
+ char uuid_disk_str[UUID_STR_LEN + 1];
+ char *datbuf;
+ char *oobbuf;
+ struct mtd_info *mtd;
+ struct nand_para_info *info;
+ u16 page_table[512];
+ u32 idb_need_write_back;
+ struct bootblk idblock[5];
+ u32 blk_counter;
+ u32 boot_blks;
+ u32 offset;
+ u32 boot_size;
+ u32 lsb_mode;
+};
+
+struct sector0 {
+ u32 magic;
+ u8 reserved[4];
+ u32 rc4_flag;
+ u16 boot_code1_offset;
+ u16 boot_code2_offset;
+ u8 reserved1[490];
+ u16 flash_data_size;
+ u16 flash_boot_size;
+ u8 reserved2[2];
+} __packed;
+
+/**
+ * rkmtd_rc4() - Rockchip specific RC4 Encryption Algorithm
+ *
+ * Encrypt Rockchip boot block header version 1 and data
+ *
+ * @buf: Pointer to data buffer
+ * @len: Data buffer size
+ */
+void rkmtd_rc4(u8 *buf, u32 len);
+
+/**
+ * struct rkmtd_ops - operations supported by UCLASS_RKMTD
+ */
+struct rkmtd_ops {
+ /**
+ * @attach_mtd: - Attach a new rkmtd driver to the device structure
+ *
+ * @attach_mtd.dev: Device to update
+ * @attach_mtd.Returns: 0 if OK, -EEXIST if a driver is already attached,
+ * other -ve on other error
+ */
+ int (*attach_mtd)(struct udevice *dev);
+
+ /**
+ * @detach_mtd: - Detach a rkmtd driver from the device structure
+ *
+ * @detach_mtd.dev: Device to detach from
+ * @detach_mtd.Returns: 0 if OK, -ENOENT if no driver is attached,
+ * other -ve on other error
+ */
+ int (*detach_mtd)(struct udevice *dev);
+};
+
+#define rkmtd_get_ops(dev) ((struct rkmtd_ops *)(dev)->driver->ops)
+
+/**
+ * rkmtd_get_cur_dev() - Get the current device
+ *
+ * Returns current device, or NULL if none
+ */
+struct udevice *rkmtd_get_cur_dev(void);
+
+/**
+ * rkmtd_set_cur_dev() - Set the current device
+ *
+ * Sets the current device, or clears it if @dev is NULL
+ *
+ * @dev: Device to set as the current one
+ */
+void rkmtd_set_cur_dev(struct udevice *dev);
+
+/**
+ * rkmtd_find_by_label() - Find a rkmtd device by label
+ *
+ * Searches all rkmtd devices to find one with the given label
+ *
+ * @label: Label to find
+ * Returns: associated device, or NULL if not found
+ */
+struct udevice *rkmtd_find_by_label(const char *label);
+
+/**
+ * rkmtd_attach() - Attach a new rkmtd driver to the device structure
+ *
+ * @dev: Device to update
+ * Returns: 0 if OK, -EEXIST if a file is already attached, other -ve on
+ * other error
+ */
+int rkmtd_attach(struct udevice *dev);
+
+/**
+ * rkmtd_detach() - Detach a rkmtd driver from the device structure
+ *
+ * @dev: Device to detach from
+ * Returns: 0 if OK, -ENOENT if no file is attached, other -ve on other
+ * error
+ */
+int rkmtd_detach(struct udevice *dev);
+
+/**
+ * rkmtd_create_device() - Create a new rkmtd device
+ *
+ * Any existing device with the same label is removed and unbound first
+ *
+ * @label: Label of the attachment, e.g. "test1"
+ * @devp: Returns the device created, on success
+ * Returns: 0 if OK, -ve on error
+ */
+int rkmtd_create_device(const char *label, struct udevice **devp);
+
+/**
+ * rkmtd_create_attach_mtd() - Create a new rkmtd device and attach driver
+ *
+ * @label: Label of the attachment, e.g. "test1"
+ * @devp: Returns the device created, on success
+ * Returns: 0 if OK, -ve on error
+ */
+int rkmtd_create_attach_mtd(const char *label, struct udevice **devp);
+
+#endif /* __RKMTD__ */
diff --git a/include/sandbox-sm.h b/include/sandbox-sm.h
new file mode 100644
index 0000000..91c30d5
--- /dev/null
+++ b/include/sandbox-sm.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2023 SberDevices, Inc.
+ *
+ * Author: Alexey Romanov <avromanov@salutedevices.com>
+ */
+
+#ifndef __SANDBOX_SM_H__
+#define __SANDBOX_SM_H__
+
+enum sandbox_smc_cmd {
+ SANDBOX_SMC_CMD_READ_MEM,
+ SANDBOX_SMC_CMD_WRITE_MEM,
+ SANDBOX_SMC_CMD_COMMON,
+ SANDBOX_SMC_CMD_COUNT,
+};
+
+#endif
diff --git a/include/sandbox_efi_capsule.h b/include/sandbox_efi_capsule.h
new file mode 100644
index 0000000..3e288e8
--- /dev/null
+++ b/include/sandbox_efi_capsule.h
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#if !defined(_SANDBOX_EFI_CAPSULE_H_)
+#define _SANDBOX_EFI_CAPSULE_H_
+
+#define SANDBOX_UBOOT_IMAGE_GUID "09d7cf52-0720-4710-91d1-08469b7fe9c8"
+#define SANDBOX_UBOOT_ENV_IMAGE_GUID "5a7021f5-fef2-48b4-aaba-832e777418c0"
+#define SANDBOX_FIT_IMAGE_GUID "3673b45d-6a7c-46f3-9e60-adabb03f7937"
+#define SANDBOX_INCORRECT_GUID "058b7d83-50d5-4c47-a195-60d86ad341c4"
+
+#define UBOOT_FIT_IMAGE "u-boot_bin_env.itb"
+
+#define CAPSULE_PRIV_KEY "capsule_priv_key_good.key"
+#define CAPSULE_PUB_KEY "capsule_pub_key_good.crt"
+#define CAPSULE_INVAL_KEY "capsule_priv_key_bad.key"
+#define CAPSULE_INVAL_PUB_KEY "capsule_pub_key_bad.crt"
+
+#endif /* _SANDBOX_EFI_CAPSULE_H_ */
diff --git a/include/sandbox_host.h b/include/sandbox_host.h
index ebd7d99..f7a5fc6 100644
--- a/include/sandbox_host.h
+++ b/include/sandbox_host.h
@@ -74,10 +74,11 @@
* @label: Label of the attachment, e.g. "test1"
* @removable: true if the device should be marked as removable, false
* if it is fixed. See enum blk_flag_t
+ * @blksz: logical block size of the device
* @devp: Returns the device created, on success
* Returns: 0 if OK, -ve on error
*/
-int host_create_device(const char *label, bool removable,
+int host_create_device(const char *label, bool removable, unsigned long blksz,
struct udevice **devp);
/**
@@ -87,11 +88,13 @@
* @filename: Name of the file, e.g. "/path/to/disk.img"
* @removable: true if the device should be marked as removable, false
* if it is fixed. See enum blk_flag_t
+ * @blksz: logical block size of the device
* @devp: Returns the device created, on success
* Returns: 0 if OK, -ve on error
*/
int host_create_attach_file(const char *label, const char *filename,
- bool removable, struct udevice **devp);
+ bool removable, unsigned long blksz,
+ struct udevice **devp);
/**
* host_find_by_label() - Find a host by label
diff --git a/include/sata.h b/include/sata.h
index d89f7a8..6111cf6 100644
--- a/include/sata.h
+++ b/include/sata.h
@@ -21,4 +21,10 @@
int sata_probe(int devnum);
int sata_remove(int devnum);
+/*
+ * Remove existing AHCI SATA device uclass and all of its children,
+ * if any, and probe it again.
+ */
+int sata_rescan(bool verbose);
+
#endif
diff --git a/include/scmi_agent-uclass.h b/include/scmi_agent-uclass.h
index b1c9353..33e0e18 100644
--- a/include/scmi_agent-uclass.h
+++ b/include/scmi_agent-uclass.h
@@ -5,27 +5,110 @@
#ifndef _SCMI_AGENT_UCLASS_H
#define _SCMI_AGENT_UCLASS_H
-struct udevice;
+#include <scmi_protocols.h>
+#include <dm/device.h>
+
struct scmi_msg;
struct scmi_channel;
/**
+ * struct scmi_agent_priv - private data maintained by agent instance
+ * @version: Version
+ * @num_agents: Number of agents
+ * @num_protocols: Number of protocols
+ * @impl_version: Implementation version
+ * @protocols: Array of protocol IDs
+ * @vendor: Vendor name
+ * @sub_vendor: Sub-vendor name
+ * @agent_name: Agent name
+ * @agent_id: Identifier of agent
+ * @base_dev: SCMI base protocol device
+ * @pwdom_dev: SCMI power domain management protocol device
+ * @clock_dev: SCMI clock protocol device
+ * @resetdom_dev: SCMI reset domain protocol device
+ * @voltagedom_dev: SCMI voltage domain protocol device
+ */
+struct scmi_agent_priv {
+ u32 version;
+ u32 num_agents;
+ u32 num_protocols;
+ u32 impl_version;
+ u8 *protocols;
+ u8 *vendor;
+ u8 *sub_vendor;
+ u8 *agent_name;
+ u32 agent_id;
+ struct udevice *base_dev;
+ struct udevice *pwdom_dev;
+ struct udevice *clock_dev;
+ struct udevice *resetdom_dev;
+ struct udevice *voltagedom_dev;
+};
+
+static inline u32 scmi_version(struct udevice *dev)
+{
+ return ((struct scmi_agent_priv *)dev_get_uclass_plat(dev))->version;
+}
+
+static inline u32 scmi_num_agents(struct udevice *dev)
+{
+ return ((struct scmi_agent_priv *)dev_get_uclass_plat(dev))->num_agents;
+}
+
+static inline u32 scmi_num_protocols(struct udevice *dev)
+{
+ return ((struct scmi_agent_priv *)dev_get_uclass_plat(dev))->num_protocols;
+}
+
+static inline u32 scmi_impl_version(struct udevice *dev)
+{
+ return ((struct scmi_agent_priv *)dev_get_uclass_plat(dev))->impl_version;
+}
+
+static inline u8 *scmi_protocols(struct udevice *dev)
+{
+ return ((struct scmi_agent_priv *)dev_get_uclass_plat(dev))->protocols;
+}
+
+static inline u8 *scmi_vendor(struct udevice *dev)
+{
+ return ((struct scmi_agent_priv *)dev_get_uclass_plat(dev))->vendor;
+}
+
+static inline u8 *scmi_sub_vendor(struct udevice *dev)
+{
+ return ((struct scmi_agent_priv *)dev_get_uclass_plat(dev))->sub_vendor;
+}
+
+static inline u8 *scmi_agent_name(struct udevice *dev)
+{
+ return ((struct scmi_agent_priv *)dev_get_uclass_plat(dev))->agent_name;
+}
+
+static inline u32 scmi_agent_id(struct udevice *dev)
+{
+ return ((struct scmi_agent_priv *)dev_get_uclass_plat(dev))->agent_id;
+}
+
+/**
* struct scmi_transport_ops - The functions that a SCMI transport layer must implement.
*/
struct scmi_agent_ops {
/*
* of_get_channel - Get SCMI channel from SCMI agent device tree node
*
- * @dev: SCMI protocol device using the transport
+ * @dev: SCMI agent device using the transport
+ * @protocol: SCMI protocol device using the transport
* @channel: Output reference to SCMI channel upon success
* Return 0 upon success and a negative errno on failure
*/
- int (*of_get_channel)(struct udevice *dev, struct scmi_channel **channel);
+ int (*of_get_channel)(struct udevice *dev, struct udevice *protocol,
+ struct scmi_channel **channel);
/*
* process_msg - Request transport to get the SCMI message processed
*
- * @dev: SCMI protocol device using the transport
+ * @dev: SCMI agent device using the transport
* @msg: SCMI message to be transmitted
*/
int (*process_msg)(struct udevice *dev, struct scmi_channel *channel,
diff --git a/include/scmi_agent.h b/include/scmi_agent.h
index ee62863..755986d 100644
--- a/include/scmi_agent.h
+++ b/include/scmi_agent.h
@@ -10,11 +10,20 @@
#ifndef SCMI_AGENT_H
#define SCMI_AGENT_H
+#include <scmi_protocols.h>
#include <asm/types.h>
struct udevice;
struct scmi_channel;
+/**
+ * struct scmi_agent_proto_priv - Private data in device for SCMI agent
+ * @channel: Reference to the SCMI channel to use
+ */
+struct scmi_agent_proto_priv {
+ struct scmi_channel *channel;
+};
+
/*
* struct scmi_msg - Context of a SCMI message sent and the response received
*
@@ -49,10 +58,9 @@
* devm_scmi_of_get_channel() - Get SCMI channel handle from SCMI agent DT node
*
* @dev: Device requesting a channel
- * @channel: Output reference to the SCMI channel upon success
* @return 0 on success and a negative errno on failure
*/
-int devm_scmi_of_get_channel(struct udevice *dev, struct scmi_channel **channel);
+int devm_scmi_of_get_channel(struct udevice *dev);
/**
* devm_scmi_process_msg() - Send and process an SCMI message
@@ -62,12 +70,23 @@
* On return, scmi_msg::out_msg_sz stores the response payload size.
*
* @dev: SCMI device
- * @channel: Communication channel for the device
* @msg: Message structure reference
* Return: 0 on success and a negative errno on failure
*/
-int devm_scmi_process_msg(struct udevice *dev, struct scmi_channel *channel,
- struct scmi_msg *msg);
+int devm_scmi_process_msg(struct udevice *dev, struct scmi_msg *msg);
+
+/**
+ * scmi_get_protocol() - get protocol instance
+ *
+ * @dev: SCMI agent device
+ * @id: SCMI protocol ID
+ *
+ * Obtain the device instance for given protocol ID, @id.
+ *
+ * Return: Pointer to the device if found, null otherwise
+ */
+struct udevice *scmi_get_protocol(struct udevice *dev,
+ enum scmi_std_protocol id);
/**
* scmi_to_linux_errno() - Convert an SCMI error code into a Linux errno code
diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h
index a220cb2..7abb2a6 100644
--- a/include/scmi_protocols.h
+++ b/include/scmi_protocols.h
@@ -50,6 +50,679 @@
};
/*
+ * SCMI Base Protocol
+ */
+#define SCMI_BASE_PROTOCOL_VERSION 0x20000
+
+enum scmi_base_message_id {
+ SCMI_BASE_DISCOVER_VENDOR = 0x3,
+ SCMI_BASE_DISCOVER_SUB_VENDOR = 0x4,
+ SCMI_BASE_DISCOVER_IMPL_VERSION = 0x5,
+ SCMI_BASE_DISCOVER_LIST_PROTOCOLS = 0x6,
+ SCMI_BASE_DISCOVER_AGENT = 0x7,
+ SCMI_BASE_NOTIFY_ERRORS = 0x8,
+ SCMI_BASE_SET_DEVICE_PERMISSIONS = 0x9,
+ SCMI_BASE_SET_PROTOCOL_PERMISSIONS = 0xa,
+ SCMI_BASE_RESET_AGENT_CONFIGURATION = 0xb,
+};
+
+#define SCMI_BASE_NAME_LENGTH_MAX 16
+
+/**
+ * struct scmi_protocol_version_out - Response for SCMI_PROTOCOL_VERSION
+ * command
+ * @status: SCMI command status
+ * @version: Protocol version
+ */
+struct scmi_protocol_version_out {
+ s32 status;
+ u32 version;
+};
+
+/**
+ * struct scmi_protocol_attrs_out - Response for SCMI_PROTOCOL_ATTRIBUTES
+ * command
+ * @status: SCMI command status
+ * @attributes: Protocol attributes or implementation details
+ */
+struct scmi_protocol_attrs_out {
+ s32 status;
+ u32 attributes;
+};
+
+#define SCMI_PROTOCOL_ATTRS_NUM_AGENTS(attributes) \
+ (((attributes) & GENMASK(15, 8)) >> 8)
+#define SCMI_PROTOCOL_ATTRS_NUM_PROTOCOLS(attributes) \
+ ((attributes) & GENMASK(7, 0))
+
+/**
+ * struct scmi_protocol_msg_attrs_out - Response for
+ * SCMI_PROTOCOL_MESSAGE_ATTRIBUTES command
+ * @status: SCMI command status
+ * @attributes: Message-specific attributes
+ */
+struct scmi_protocol_msg_attrs_out {
+ s32 status;
+ u32 attributes;
+};
+
+/**
+ * struct scmi_base_discover_vendor_out - Response for
+ * SCMI_BASE_DISCOVER_VENDOR or
+ * SCMI_BASE_DISCOVER_SUB_VENDOR command
+ * @status: SCMI command status
+ * @vendor_identifier: Name of vendor or sub-vendor in string
+ */
+struct scmi_base_discover_vendor_out {
+ s32 status;
+ u8 vendor_identifier[SCMI_BASE_NAME_LENGTH_MAX];
+};
+
+/**
+ * struct scmi_base_discover_impl_version_out - Response for
+ * SCMI_BASE_DISCOVER_IMPL_VERSION command
+ * @status: SCMI command status
+ * @impl_version: Vendor-specific implementation version
+ */
+struct scmi_base_discover_impl_version_out {
+ s32 status;
+ u32 impl_version;
+};
+
+/**
+ * struct scmi_base_discover_list_protocols_out - Response for
+ * SCMI_BASE_DISCOVER_LIST_PROTOCOLS command
+ * @status: SCMI command status
+ * @num_protocols: Number of SCMI protocols in @protocol
+ * @protocols: Array of packed SCMI protocol ID's
+ */
+struct scmi_base_discover_list_protocols_out {
+ s32 status;
+ u32 num_protocols;
+ u32 protocols[3];
+};
+
+/**
+ * struct scmi_base_discover_agent_out - Response for
+ * SCMI_BASE_DISCOVER_AGENT command
+ * @status: SCMI command status
+ * @agent_id: SCMI agent ID
+ * @name: Name of agent in string
+ */
+struct scmi_base_discover_agent_out {
+ s32 status;
+ u32 agent_id;
+ u8 name[SCMI_BASE_NAME_LENGTH_MAX];
+};
+
+#define SCMI_BASE_NOTIFY_ERRORS_ENABLE BIT(0)
+
+/**
+ * struct scmi_base_set_device_permissions_in - Parameters for
+ * SCMI_BASE_SET_DEVICE_PERMISSIONS command
+ * @agent_id: SCMI agent ID
+ * @device_id: device ID
+ * @flags: A set of flags
+ */
+struct scmi_base_set_device_permissions_in {
+ u32 agent_id;
+ u32 device_id;
+ u32 flags;
+};
+
+#define SCMI_BASE_SET_DEVICE_PERMISSIONS_ACCESS BIT(0)
+
+/**
+ * struct scmi_base_set_protocol_permissions_in - Parameters for
+ * SCMI_BASE_SET_PROTOCOL_PERMISSIONS command
+ * @agent_id: SCMI agent ID
+ * @device_id: device ID
+ * @command_id: command ID
+ * @flags: A set of flags
+ */
+struct scmi_base_set_protocol_permissions_in {
+ u32 agent_id;
+ u32 device_id;
+ u32 command_id;
+ u32 flags;
+};
+
+#define SCMI_BASE_SET_PROTOCOL_PERMISSIONS_COMMAND GENMASK(7, 0)
+#define SCMI_BASE_SET_PROTOCOL_PERMISSIONS_ACCESS BIT(0)
+
+/**
+ * struct scmi_base_reset_agent_configuration_in - Parameters for
+ * SCMI_BASE_RESET_AGENT_CONFIGURATION command
+ * @agent_id: SCMI agent ID
+ * @flags: A set of flags
+ */
+struct scmi_base_reset_agent_configuration_in {
+ u32 agent_id;
+ u32 flags;
+};
+
+#define SCMI_BASE_RESET_ALL_ACCESS_PERMISSIONS BIT(0)
+
+/**
+ * struct scmi_base_ops - SCMI base protocol interfaces
+ */
+struct scmi_base_ops {
+ /**
+ * protocol_version - get Base protocol version
+ * @dev: SCMI protocol device
+ * @version: Pointer to SCMI protocol version
+ *
+ * Obtain the protocol version number in @version for Base protocol.
+ *
+ * Return: 0 on success, error code on failure
+ */
+ int (*protocol_version)(struct udevice *dev, u32 *version);
+ /**
+ * protocol_attrs - get protocol attributes
+ * @dev: SCMI protocol device
+ * @num_agents: Number of SCMI agents
+ * @num_protocols: Number of SCMI protocols
+ *
+ * Obtain the protocol attributes, the number of agents and the number
+ * of protocols, in @num_agents and @num_protocols respectively, that
+ * the device provides.
+ *
+ * Return: 0 on success, error code on failure
+ */
+ int (*protocol_attrs)(struct udevice *dev, u32 *num_agents,
+ u32 *num_protocols);
+ /**
+ * protocol_message_attrs - get message-specific attributes
+ * @dev: SCMI protocol device
+ * @message_id: SCMI message ID
+ * @attributes: Message-specific attributes
+ *
+ * Obtain the message-specific attributes in @attributes.
+ * This command succeeds if the message is implemented and available.
+ *
+ * Return: 0 on success, error code on failure
+ */
+ int (*protocol_message_attrs)(struct udevice *dev, u32 message_id,
+ u32 *attributes);
+ /**
+ * base_discover_vendor - get vendor name
+ * @dev: SCMI protocol device
+ * @vendor: Pointer to vendor name
+ *
+ * Obtain the vendor's name in @vendor.
+ * It is a caller's responsibility to free @vendor.
+ *
+ * Return: 0 on success, error code on failure
+ */
+ int (*base_discover_vendor)(struct udevice *dev, u8 **vendor);
+ /**
+ * base_discover_sub_vendor - get sub-vendor name
+ * @dev: SCMI protocol device
+ * @sub_vendor: Pointer to sub-vendor name
+ *
+ * Obtain the sub-vendor's name in @sub_vendor.
+ * It is a caller's responsibility to free @sub_vendor.
+ *
+ * Return: 0 on success, error code on failure
+ */
+ int (*base_discover_sub_vendor)(struct udevice *dev, u8 **sub_vendor);
+ /**
+ * base_discover_impl_version - get implementation version
+ * @dev: SCMI protocol device
+ * @impl_version: Pointer to implementation version
+ *
+ * Obtain the implementation version number in @impl_version.
+ *
+ * Return: 0 on success, error code on failure
+ */
+ int (*base_discover_impl_version)(struct udevice *dev,
+ u32 *impl_version);
+ /**
+ * base_discover_list_protocols - get list of protocols
+ * @dev: SCMI protocol device
+ * @protocols: Pointer to array of SCMI protocols
+ *
+ * Obtain the list of protocols provided in @protocols.
+ * The number of elements in @protocols always match to the number of
+ * protocols returned by smci_protocol_attrs() when this function
+ * succeeds.
+ * It is a caller's responsibility to free @protocols.
+ *
+ * Return: the number of protocols in @protocols on success,
+ * error code on failure
+ */
+ int (*base_discover_list_protocols)(struct udevice *dev,
+ u8 **protocols);
+ /**
+ * base_discover_agent - identify agent
+ * @dev: SCMI protocol device
+ * @agent_id: SCMI agent ID
+ * @ret_agent_id: Pointer to SCMI agent ID
+ * @name: Pointer to SCMI agent name
+ *
+ * Obtain the agent's name in @name. If @agent_id is equal to
+ * 0xffffffff, * this function returns the caller's agent id in
+ * @ret_agent_id.
+ * It is a caller's responsibility to free @name.
+ *
+ * Return: 0 on success, error code on failure
+ */
+ int (*base_discover_agent)(struct udevice *dev, u32 agent_id,
+ u32 *ret_agent_id, u8 **name);
+ /**
+ * base_notify_errors - configure error notification
+ * @dev: SCMI protocol device
+ * @enable: Operation
+ *
+ * Enable or disable error notification from SCMI firmware.
+ *
+ * Return: 0 on success, error code on failure
+ */
+ int (*base_notify_errors)(struct udevice *dev, u32 enable);
+ /**
+ * base_set_device_permissions - configure access permission to device
+ * @dev: SCMI protocol device
+ * @agent_id: SCMI agent ID
+ * @device_id: ID of device to access
+ * @flags: A set of flags
+ *
+ * Ask for allowing or denying access permission to the device,
+ * @device_id. The meaning of @flags is defined in SCMI specification.
+ *
+ * Return: 0 on success, error code on failure
+ */
+ int (*base_set_device_permissions)(struct udevice *dev, u32 agent_id,
+ u32 device_id, u32 flags);
+ /**
+ * base_set_protocol_permissions - configure access permission to
+ * protocol on device
+ * @dev: SCMI protocol device
+ * @agent_id: SCMI agent ID
+ * @device_id: ID of device to access
+ * @command_id: command ID
+ * @flags: A set of flags
+ *
+ * Ask for allowing or denying access permission to the protocol,
+ * @command_id, on the device, @device_id.
+ * The meaning of @flags is defined in SCMI specification.
+ *
+ * Return: 0 on success, error code on failure
+ */
+ int (*base_set_protocol_permissions)(struct udevice *dev, u32 agent_id,
+ u32 device_id, u32 command_id,
+ u32 flags);
+ /**
+ * base_reset_agent_configuration - reset resource settings
+ * @dev: SCMI protocol device
+ * @agent_id: SCMI agent ID
+ * @flags: A set of flags
+ *
+ * Reset all the resource settings against @agent_id.
+ * The meaning of @flags is defined in SCMI specification.
+ *
+ * Return: 0 on success, error code on failure
+ */
+ int (*base_reset_agent_configuration)(struct udevice *dev, u32 agent_id,
+ u32 flags);
+};
+
+/**
+ * scmi_generic_protocol_version - get protocol version
+ * @dev: SCMI protocol device
+ * @id: SCMI protocol ID
+ * @version: Pointer to SCMI protocol version
+ *
+ * Obtain the protocol version number in @version.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int scmi_generic_protocol_version(struct udevice *dev,
+ enum scmi_std_protocol id, u32 *version);
+
+/**
+ * scmi_base_protocol_version - get Base protocol version
+ * @dev: SCMI protocol device
+ * @version: Pointer to SCMI protocol version
+ *
+ * Obtain the protocol version number in @version for Base protocol.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int scmi_base_protocol_version(struct udevice *dev, u32 *version);
+
+/**
+ * scmi_protocol_attrs - get protocol attributes
+ * @dev: SCMI protocol device
+ * @num_agents: Number of SCMI agents
+ * @num_protocols: Number of SCMI protocols
+ *
+ * Obtain the protocol attributes, the number of agents and the number
+ * of protocols, in @num_agents and @num_protocols respectively, that
+ * the device provides.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int scmi_base_protocol_attrs(struct udevice *dev, u32 *num_agents,
+ u32 *num_protocols);
+
+/**
+ * scmi_protocol_message_attrs - get message-specific attributes
+ * @dev: SCMI protocol device
+ * @message_id: SCMI message ID
+ * @attributes: Message-specific attributes
+ *
+ * Obtain the message-specific attributes in @attributes.
+ * This command succeeds if the message is implemented and available.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int scmi_base_protocol_message_attrs(struct udevice *dev, u32 message_id,
+ u32 *attributes);
+
+/**
+ * scmi_base_discover_vendor - get vendor name
+ * @dev: SCMI protocol device
+ * @vendor: Pointer to vendor name
+ *
+ * Obtain the vendor's name in @vendor.
+ * It is a caller's responsibility to free @vendor.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int scmi_base_discover_vendor(struct udevice *dev, u8 **vendor);
+
+/**
+ * scmi_base_discover_sub_vendor - get sub-vendor name
+ * @dev: SCMI protocol device
+ * @sub_vendor: Pointer to sub-vendor name
+ *
+ * Obtain the sub-vendor's name in @sub_vendor.
+ * It is a caller's responsibility to free @sub_vendor.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int scmi_base_discover_sub_vendor(struct udevice *dev, u8 **sub_vendor);
+
+/**
+ * scmi_base_discover_impl_version - get implementation version
+ * @dev: SCMI protocol device
+ * @impl_version: Pointer to implementation version
+ *
+ * Obtain the implementation version number in @impl_version.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int scmi_base_discover_impl_version(struct udevice *dev, u32 *impl_version);
+
+/**
+ * scmi_base_discover_list_protocols - get list of protocols
+ * @dev: SCMI protocol device
+ * @protocols: Pointer to array of SCMI protocols
+ *
+ * Obtain the list of protocols provided in @protocols.
+ * The number of elements in @protocols always match to the number of
+ * protocols returned by smci_protocol_attrs() when this function succeeds.
+ * It is a caller's responsibility to free @protocols.
+ *
+ * Return: the number of protocols in @protocols on success, error code on
+ * failure
+ */
+int scmi_base_discover_list_protocols(struct udevice *dev, u8 **protocols);
+
+/**
+ * scmi_base_discover_agent - identify agent
+ * @dev: SCMI protocol device
+ * @agent_id: SCMI agent ID
+ * @ret_agent_id: Pointer to SCMI agent ID
+ * @name: Pointer to SCMI agent name
+ *
+ * Obtain the agent's name in @name. If @agent_id is equal to 0xffffffff,
+ * this function returns the caller's agent id in @ret_agent_id.
+ * It is a caller's responsibility to free @name.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int scmi_base_discover_agent(struct udevice *dev, u32 agent_id,
+ u32 *ret_agent_id, u8 **name);
+
+/**
+ * scmi_base_notify_errors - configure error notification
+ * @dev: SCMI protocol device
+ * @enable: Operation
+ *
+ * Enable or disable error notification from SCMI firmware.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int scmi_base_notify_errors(struct udevice *dev, u32 enable);
+
+/**
+ * scmi_base_set_device_permissions - configure access permission to device
+ * @dev: SCMI protocol device
+ * @agent_id: SCMI agent ID
+ * @device_id: ID of device to access
+ * @flags: A set of flags
+ *
+ * Ask for allowing or denying access permission to the device, @device_id.
+ * The meaning of @flags is defined in SCMI specification.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int scmi_base_set_device_permissions(struct udevice *dev, u32 agent_id,
+ u32 device_id, u32 flags);
+
+/**
+ * scmi_base_set_protocol_permissions - configure access permission to
+ * protocol on device
+ * @dev: SCMI protocol device
+ * @agent_id: SCMI agent ID
+ * @device_id: ID of device to access
+ * @command_id: SCMI command ID
+ * @flags: A set of flags
+ *
+ * Ask for allowing or denying access permission to the protocol, @command_id,
+ * on the device, @device_id.
+ * The meaning of @flags is defined in SCMI specification.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int scmi_base_set_protocol_permissions(struct udevice *dev,
+ u32 agent_id, u32 device_id,
+ u32 command_id, u32 flags);
+
+/**
+ * scmi_base_reset_agent_configuration - reset resource settings
+ * @dev: SCMI protocol device
+ * @agent_id: SCMI agent ID
+ * @flags: A set of flags
+ *
+ * Reset all the resource settings against @agent_id.
+ * The meaning of @flags is defined in SCMI specification.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int scmi_base_reset_agent_configuration(struct udevice *dev, u32 agent_id,
+ u32 flags);
+
+/*
+ * SCMI Power Domain Management Protocol
+ */
+
+#define SCMI_PWD_PROTOCOL_VERSION 0x30000
+#define SCMI_PWD_PSTATE_TYPE_LOST BIT(30)
+#define SCMI_PWD_PSTATE_ID GENMASK(27, 0)
+
+enum scmi_power_domain_message_id {
+ SCMI_PWD_ATTRIBUTES = 0x3,
+ SCMI_PWD_STATE_SET = 0x4,
+ SCMI_PWD_STATE_GET = 0x5,
+ SCMI_PWD_STATE_NOTIFY = 0x6,
+ SCMI_PWD_STATE_CHANGE_REQUESTED_NOTIFY = 0x7,
+ SCMI_PWD_NAME_GET = 0x8,
+};
+
+/**
+ * struct scmi_pwd_protocol_attrs_out
+ * @status: SCMI command status
+ * @attributes: Protocol attributes
+ * @stats_addr_low: Lower 32 bits of address of statistics memory region
+ * @stats_addr_high: Higher 32 bits of address of statistics memory region
+ * @stats_len: Length of statistics memory region
+ */
+struct scmi_pwd_protocol_attrs_out {
+ s32 status;
+ u32 attributes;
+ u32 stats_addr_low;
+ u32 stats_addr_high;
+ u32 stats_len;
+};
+
+#define SCMI_PWD_PROTO_ATTRS_NUM_PWD(attributes) ((attributes) & GENMASK(15, 0))
+
+/**
+ * struct scmi_pwd_protocol_msg_attrs_out
+ * @status: SCMI command status
+ * @attributes: Message-specific attributes
+ */
+struct scmi_pwd_protocol_msg_attrs_out {
+ s32 status;
+ u32 attributes;
+};
+
+#define SCMI_PWD_NAME_LENGTH_MAX 16
+
+/**
+ * struct scmi_pwd_attrs_out
+ * @status: SCMI command status
+ * @attributes: Power domain attributes
+ * @name: Name of power domain
+ */
+struct scmi_pwd_attrs_out {
+ s32 status;
+ u32 attributes;
+ u8 name[SCMI_PWD_NAME_LENGTH_MAX];
+};
+
+#define SCMI_PWD_ATTR_PSTATE_CHANGE_NOTIFY BIT(31)
+#define SCMI_PWD_ATTR_PSTATE_ASYNC BIT(30)
+#define SCMI_PWD_ATTR_PSTATE_SYNC BIT(29)
+#define SCMI_PWD_ATTR_PSTATE_CHANGE_RQ_NOTIFY BIT(28)
+#define SCMI_PWD_ATTR_EXTENDED_NAME BIT(27)
+
+/**
+ * struct scmi_pwd_state_set_in
+ * @flags: Flags
+ * @domain_id: Identifier of power domain
+ * @pstate: Power state of the domain
+ */
+struct scmi_pwd_state_set_in {
+ u32 flags;
+ u32 domain_id;
+ u32 pstate;
+};
+
+#define SCMI_PWD_SET_FLAGS_ASYNC BIT(0)
+
+/**
+ * struct scmi_pwd_state_get_out
+ * @status: SCMI command status
+ * @pstate: Power state of the domain
+ */
+struct scmi_pwd_state_get_out {
+ s32 status;
+ u32 pstate;
+};
+
+#define SCMI_PWD_EXTENDED_NAME_MAX 64
+/**
+ * struct scmi_pwd_name_get_out
+ * @status: SCMI command status
+ * @flags: Parameter flags
+ * @extended_name: Extended name of power domain
+ */
+struct scmi_pwd_name_get_out {
+ s32 status;
+ u32 flags;
+ u8 extended_name[SCMI_PWD_EXTENDED_NAME_MAX];
+};
+
+/**
+ * scmi_pwd_protocol_attrs - get protocol attributes
+ * @dev: SCMI protocol device
+ * @num_pwdoms: Number of power domains
+ * @stats_addr: Address of statistics memory region
+ * @stats_len: Length of statistics memory region
+ *
+ * Obtain the protocol attributes, the number of power domains and
+ * the information of statistics memory region.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int scmi_pwd_protocol_attrs(struct udevice *dev, int *num_pwdoms,
+ u64 *stats_addr, size_t *stats_len);
+/**
+ * scmi_pwd_protocol_message_attrs - get message-specific attributes
+ * @dev: SCMI protocol device
+ * @message_id: SCMI message ID
+ * @attributes: Message-specific attributes
+ *
+ * Obtain the message-specific attributes in @attributes.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int scmi_pwd_protocol_message_attrs(struct udevice *dev, s32 message_id,
+ u32 *attributes);
+/**
+ * scmi_pwd_attrs - get power domain attributes
+ * @dev: SCMI protocol device
+ * @domain_id: Identifier of power domain
+ * @attributes: Power domain attributes
+ * @name: Name of power domain
+ *
+ * Obtain the attributes of the given power domain, @domain_id, in @attributes
+ * as well as its name in @name.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int scmi_pwd_attrs(struct udevice *dev, u32 message_id, u32 *attributes,
+ u8 **name);
+/**
+ * scmi_pwd_state_set - set power state
+ * @dev: SCMI protocol device
+ * @flags: Parameter flags
+ * @domain_id: Identifier of power domain
+ * @pstate: Power state
+ *
+ * Change the power state of the given power domain, @domain_id.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int scmi_pwd_state_set(struct udevice *dev, u32 flags, u32 domain_id,
+ u32 pstate);
+/**
+ * scmi_pwd_state_get - get power state
+ * @dev: SCMI protocol device
+ * @domain_id: Identifier of power domain
+ * @pstate: Power state
+ *
+ * Obtain the power state of the given power domain, @domain_id.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int scmi_pwd_state_get(struct udevice *dev, u32 domain_id, u32 *pstate);
+/**
+ * scmi_pwd_name_get - get extended name
+ * @dev: SCMI protocol device
+ * @domain_id: Identifier of power domain
+ * @name: Extended name of the domain
+ *
+ * Obtain the extended name of the given power domain, @domain_id, in @name.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int scmi_pwd_name_get(struct udevice *dev, u32 domain_id, u8 **name);
+
+/*
* SCMI Clock Protocol
*/
diff --git a/include/scsi.h b/include/scsi.h
index 9efefea..ee9d622 100644
--- a/include/scsi.h
+++ b/include/scsi.h
@@ -7,6 +7,7 @@
#define _SCSI_H
#include <asm/cache.h>
+#include <bouncebuf.h>
#include <linux/dma-direction.h>
/* Fix this to the maximum */
@@ -298,6 +299,24 @@
* @return 0 if OK, -ve on error
*/
int (*bus_reset)(struct udevice *dev);
+
+#if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
+ /**
+ * buffer_aligned() - test memory alignment of block operation buffer
+ *
+ * Some devices have limited DMA capabilities and require that the
+ * buffers passed to them fit specific properties. This optional
+ * callback can be used to indicate whether a buffer alignment is
+ * suitable for the device DMA or not, and trigger use of generic
+ * bounce buffer implementation to help use of unsuitable buffers
+ * at the expense of performance degradation.
+ *
+ * @dev: Block device associated with the request
+ * @state: Bounce buffer state
+ * @return 1 if OK, 0 if unaligned
+ */
+ int (*buffer_aligned)(struct udevice *dev, struct bounce_buffer *state);
+#endif /* CONFIG_BOUNCE_BUFFER */
};
#define scsi_get_ops(dev) ((struct scsi_ops *)(dev)->driver->ops)
diff --git a/include/sdhci.h b/include/sdhci.h
index 70fefca..a1b74e3 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -57,6 +57,7 @@
#define SDHCI_PRESENT_STATE 0x24
#define SDHCI_CMD_INHIBIT BIT(0)
#define SDHCI_DATA_INHIBIT BIT(1)
+#define SDHCI_DAT_ACTIVE BIT(2)
#define SDHCI_DOING_WRITE BIT(8)
#define SDHCI_DOING_READ BIT(9)
#define SDHCI_SPACE_AVAILABLE BIT(10)
diff --git a/include/sdp.h b/include/sdp.h
index 6d89baa..5492f9c 100644
--- a/include/sdp.h
+++ b/include/sdp.h
@@ -9,15 +9,15 @@
#ifndef __SDP_H_
#define __SDP_H_
-int sdp_init(int controller_index);
+int sdp_init(struct udevice *udc);
#ifdef CONFIG_SPL_BUILD
#include <spl.h>
-int spl_sdp_handle(int controller_index, struct spl_image_info *spl_image,
+int spl_sdp_handle(struct udevice *udc, struct spl_image_info *spl_image,
struct spl_boot_device *bootdev);
#else
-int sdp_handle(int controller_index);
+int sdp_handle(struct udevice *udc);
#endif
#endif /* __SDP_H_ */
diff --git a/include/serial.h b/include/serial.h
index 42bdf37..d129dc3 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -137,6 +137,7 @@
* @type: type of the UART chip
* @addr_space: address space to access the registers
* @addr: physical address of the registers
+ * @size: size of the register area in bytes
* @reg_width: size (in bytes) of the IO accesses to the registers
* @reg_offset: offset to apply to the @addr from the start of the registers
* @reg_shift: quantity to shift the register offsets by
@@ -147,6 +148,7 @@
enum serial_chip_type type;
enum adr_space_type addr_space;
ulong addr;
+ ulong size;
u8 reg_width;
u8 reg_offset;
u8 reg_shift;
@@ -337,6 +339,13 @@
*/
int serial_getinfo(struct udevice *dev, struct serial_device_info *info);
+/**
+ * fetch_baud_from_dtb() - Fetch the baudrate value from DT
+ *
+ * Return: baudrate if OK, -ve on error
+ */
+int fetch_baud_from_dtb(void);
+
void atmel_serial_initialize(void);
void mcf_serial_initialize(void);
void mpc85xx_serial_initialize(void);
diff --git a/include/sm-uclass.h b/include/sm-uclass.h
new file mode 100644
index 0000000..c114484
--- /dev/null
+++ b/include/sm-uclass.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2023 SberDevices, Inc.
+ *
+ * Author: Alexey Romanov <avromanov@salutedevices.com>
+ */
+
+#ifndef __SM_UCLASS_H__
+#define __SM_UCLASS_H__
+
+#include <asm/types.h>
+#include <asm/ptrace.h>
+
+struct udevice;
+
+/**
+ * struct sm_ops - The functions that a SM driver must implement.
+ *
+ * @sm_call: Request a secure monitor call with specified command.
+ *
+ * @sm_call_read: Request a secure monitor call and retrieve data
+ * from secure-monitor (depends on specified command).
+ *
+ * @sm_call_write: Request a secure monitor call and send data
+ * to secure-monitor (depends on specified command).
+ *
+ * The individual methods are described more fully below.
+ */
+struct sm_ops {
+ /**
+ * sm_call - generic SMC call to the secure-monitor
+ *
+ * @dev: Pointer to UCLASS_SM device
+ * @cmd_index: Index of the SMC function ID
+ * @smc_ret: Returned value from secure world
+ * @args: SMC arguments
+ *
+ * @return: 0 on success, a negative value on error
+ */
+ int (*sm_call)(struct udevice *dev, u32 cmd, s32 *smc_ret,
+ struct pt_regs *args);
+
+ /**
+ * sm_call_write - send data to secure-monitor
+ *
+ * @dev: Pointer to UCLASS_SM device
+ * @buffer: Buffer containing data to send
+ * @size: Size of the buffer
+ * @cmd: Index of the SMC function ID
+ * @args: SMC arguments
+ *
+ * @return: size of sent data on success, a negative value on error
+ */
+ int (*sm_call_write)(struct udevice *dev, void *buffer,
+ size_t size, u32 cmd, struct pt_regs *args);
+
+ /**
+ * sm_call_read - retrieve data from secure-monitor
+ *
+ * @dev: Pointer to UCLASS_SM device
+ * @buffer: Buffer to store the retrieved data
+ * @size: Size of the buffer
+ * @cmd: Index of the SMC function ID
+ * @args: SMC arguments
+ *
+ * @return: size of read data on success, a negative value on error
+ */
+ int (*sm_call_read)(struct udevice *dev, void *buffer,
+ size_t size, u32 cmd, struct pt_regs *args);
+};
+
+#endif /* __SM_UCLASS_H__ */
diff --git a/include/sm.h b/include/sm.h
new file mode 100644
index 0000000..afa9c89
--- /dev/null
+++ b/include/sm.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2023 SberDevices, Inc.
+ *
+ * Author: Alexey Romanov <avromanov@salutedevices.ru>
+ */
+
+#ifndef __SM_H__
+#define __SM_H__
+
+/*
+ * NOTE: UCLASS_SM is designed with the idea that
+ * each driver should convert @cmd to some raw
+ * value, which is known only for driver, and set this
+ * value to the first element of the @args->regs array.
+ * Therefore, it is necessary to pass the remaining
+ * arguments starting at index = 1. Anyway, driver
+ * implementation may vary, so, please, check the specific
+ * implementation of the driver you are using.
+ */
+
+#include <asm/types.h>
+#include <asm/ptrace.h>
+
+struct udevice;
+
+/**
+ * sm_call - generic SMC call to the secure-monitor
+ *
+ * @dev: Pointer to UCLASS_SM device
+ * @cmd_index: Index of the SMC function ID
+ * @smc_ret: Returned value from secure world
+ * @args: SMC arguments
+ *
+ * @return: 0 on success, a negative value on error
+ */
+int sm_call(struct udevice *dev, u32 cmd, s32 *ret, struct pt_regs *args);
+
+/**
+ * sm_call_read - retrieve data from secure-monitor
+ *
+ * @dev: Pointer to UCLASS_MESON_SM device
+ * @buffer: Buffer to store the retrieved data
+ * @size: Size of the buffer
+ * @cmd: Index of the SMC function ID
+ * @args: SMC arguments
+ *
+ * @return: size of read data on success, a negative value on error
+ */
+int sm_call_read(struct udevice *dev, void *buffer, size_t size,
+ u32 cmd, struct pt_regs *args);
+
+/**
+ * sm_call_write - send data to secure-monitor
+ *
+ * @dev: Pointer to UCLASS_SM device
+ * @buffer: Buffer containing data to send
+ * @size: Size of the buffer
+ * @cmd: Index of the SMC function ID
+ * @args: SMC arguments
+ *
+ * @return: size of sent data on success, a negative value on error
+ */
+int sm_call_write(struct udevice *dev, void *buffer, size_t size,
+ u32 cmd, struct pt_regs *args);
+
+#endif /* __SM_H__ */
diff --git a/include/soc.h b/include/soc.h
index a52a300..850db28 100644
--- a/include/soc.h
+++ b/include/soc.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * (C) Copyright 2020 - Texas Instruments Incorporated - http://www.ti.com/
+ * (C) Copyright 2020 - Texas Instruments Incorporated - https://www.ti.com/
* Dave Gerlach <d-gerlach@ti.com>
*/
diff --git a/include/spl.h b/include/spl.h
index 95bf3b7..d21d469 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -132,6 +132,16 @@
#endif
}
+/* returns true if in U-Boot proper, false if in SPL */
+static inline bool spl_in_proper(void)
+{
+#ifdef CONFIG_SPL_BUILD
+ return false;
+#endif
+
+ return true;
+}
+
/**
* spl_prev_phase() - Figure out the previous U-Boot phase
*
@@ -263,6 +273,15 @@
#endif
};
+static inline void *spl_image_fdt_addr(struct spl_image_info *info)
+{
+#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
+ return info->fdt_addr;
+#else
+ return 0;
+#endif
+}
+
/**
* Information required to load data from a device
*
@@ -397,6 +416,16 @@
void preloader_console_init(void);
u32 spl_boot_device(void);
+struct spi_flash;
+
+/**
+ * spl_spi_get_uboot_offs() - Lookup function for the SPI boot offset
+ * @flash: The spi flash to boot from
+ *
+ * Return: The offset of U-Boot within the SPI flash
+ */
+unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash);
+
/**
* spl_spi_boot_bus() - Lookup function for the SPI boot bus source.
*
@@ -468,6 +497,32 @@
void spl_set_bd(void);
/**
+ * spl_mmc_get_uboot_raw_sector() - Provide raw sector of the start of U-Boot (architecture override)
+ *
+ * This is a weak function which by default will provide the raw sector that is
+ * where the start of the U-Boot image has been written to.
+ *
+ * @mmc: struct mmc that describes the devie where U-Boot resides
+ * @raw_sect: The raw sector number where U-Boot is by default.
+ * Return: The raw sector location that U-Boot resides at
+ */
+unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
+ unsigned long raw_sect);
+
+/**
+ * spl_mmc_get_uboot_raw_sector() - Provide raw sector of the start of U-Boot (board override)
+ *
+ * This is a weak function which by default will provide the raw sector that is
+ * where the start of the U-Boot image has been written to.
+ *
+ * @mmc: struct mmc that describes the devie where U-Boot resides
+ * @raw_sect: The raw sector number where U-Boot is by default.
+ * Return: The raw sector location that U-Boot resides at
+ */
+unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
+ unsigned long raw_sect);
+
+/**
* spl_mmc_get_uboot_raw_sector() - Provide raw sector of the start of U-Boot
*
* This is a weak function which by default will provide the raw sector that is
@@ -484,7 +539,7 @@
* spl_set_header_raw_uboot() - Set up a standard SPL image structure
*
* This sets up the given spl_image which the standard values obtained from
- * config options: CONFIG_SYS_MONITOR_LEN, CFG_SYS_UBOOT_START,
+ * config options: CONFIG_SYS_MONITOR_LEN, CONFIG_SYS_UBOOT_START,
* CONFIG_TEXT_BASE.
*
* @spl_image: Image description to set up
@@ -654,7 +709,23 @@
}
#endif
+#define SPL_LOAD_IMAGE_GET(_priority, _boot_device, _method) \
+ ll_entry_get(struct spl_image_loader, \
+ _boot_device ## _priority ## _method, spl_image_loader)
+
/* SPL FAT image functions */
+
+/**
+ * spl_fat_force_reregister() - Force reregistration of FAT block devices
+ *
+ * To avoid repeatedly looking up block devices, spl_load_image_fat keeps track
+ * of whether it has already registered a block device. This is fine for most
+ * cases, but when running unit tests all devices are removed and recreated
+ * in-between tests. This function will force re-registration of any block
+ * devices, ensuring that we don't try to use an invalid block device.
+ */
+void spl_fat_force_reregister(void);
+
int spl_load_image_fat(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev,
struct blk_desc *block_dev, int partition,
@@ -707,9 +778,13 @@
*/
int spl_init(void);
-#ifdef CONFIG_SPL_BOARD_INIT
+/*
+ * spl_board_init() - Do board-specific init in SPL
+ *
+ * If xPL_BOARD_INIT is enabled, this is called from board_init_r() before
+ * jumping to the next phase.
+ */
void spl_board_init(void);
-#endif
/**
* spl_was_boot_source() - check if U-Boot booted from SPL
@@ -730,6 +805,16 @@
*/
int spl_dfu_cmd(int usbctrl, char *dfu_alt_info, char *interface, char *devstr);
+/**
+ * spl_mmc_clear_cache() - Clear cached MMC devices
+ *
+ * To avoid reinitializing MMCs, spl_mmc_load caches the most-recently-used MMC
+ * device. This is fine for most cases, but when running unit tests all devices
+ * are removed and recreated in-between tests. This function will clear any
+ * cached state, ensuring that we don't try to use an invalid MMC.
+ */
+void spl_mmc_clear_cache(void);
+
int spl_mmc_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev);
@@ -770,7 +855,7 @@
/**
* spl_invoke_atf - boot using an ARM trusted firmware image
*/
-void spl_invoke_atf(struct spl_image_info *spl_image);
+void __noreturn spl_invoke_atf(struct spl_image_info *spl_image);
/**
* bl2_plat_get_bl31_params() - return params for bl31.
@@ -895,6 +980,42 @@
*/
struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size);
+/**
+ * board_spl_fit_append_fdt_skip(): test whether DTO application should be skipped
+ * @name: DTO node name within fitImage images node
+ *
+ * A board-specific function used to indicate whether a DTO from fitImage
+ * configuration node 'fdt' property DT and DTO list should be applied onto
+ * the base DT or not applied.
+ *
+ * This is useful in case of DTOs which implement e.g. different board revision
+ * details, where such DTO should be applied on one board revision, and should
+ * not be applied on another board revision.
+ *
+ * Return: 0 to indicate DTO is not skipped, all else to indicate DTO is skipped.
+ */
+int board_spl_fit_append_fdt_skip(const char *name);
+
void board_boot_order(u32 *spl_boot_list);
void spl_save_restore_data(void);
+
+/**
+ * spl_load_fit_image() - Fully parse and a FIT image in SPL
+ *
+ * @spl_image: SPL Image data to fill in
+ * @header: Pointer to FIT image
+ * Return 0 if OK, -ve on error
+ */
+int spl_load_fit_image(struct spl_image_info *spl_image,
+ const struct legacy_img_hdr *header);
+
+/*
+ * spl_decompression_enabled() - check decompression support is enabled for SPL build
+ *
+ * Returns true if decompression support is enabled, else False
+ */
+static inline bool spl_decompression_enabled(void)
+{
+ return IS_ENABLED(CONFIG_SPL_GZIP) || IS_ENABLED(CONFIG_SPL_LZMA);
+}
#endif
diff --git a/include/st_logo_data.h b/include/st_logo_data.h
deleted file mode 100644
index b53fa1c..0000000
--- a/include/st_logo_data.h
+++ /dev/null
@@ -1,3265 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
- * Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
- * Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
- */
-
-/*
- * file generated from picture
- * tools/logos/stmicroelectronics_uboot_logo_8bit_rle.bmp
- */
-
-unsigned char stmicroelectronics_uboot_logo_8bit_rle[] = {
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-0x21, 0x21, 0x04, 0x16, 0x04, 0x13, 0x05, 0x2a, 0x06, 0x0f, 0x03, 0x4c,
-0x04, 0x41, 0x04, 0x49, 0x01, 0x67, 0x01, 0x67, 0x05, 0x78, 0x05, 0x3d,
-0x06, 0x55, 0x05, 0x50, 0x04, 0x5e, 0x05, 0x46, 0x01, 0x64, 0x01, 0x46,
-0x04, 0x64, 0x03, 0x60, 0x04, 0x4e, 0x05, 0x56, 0x07, 0x48, 0x01, 0x5f,
-0x01, 0x48, 0x04, 0x5f, 0x09, 0x48, 0x04, 0x56, 0x06, 0x4e, 0x06, 0x64,
-0x07, 0x46, 0x04, 0x5e, 0x06, 0x50, 0x05, 0x55, 0x05, 0x3d, 0x05, 0x78,
-0x03, 0x67, 0x05, 0x49, 0x01, 0x41, 0x01, 0x41, 0x04, 0x4c, 0x05, 0x0f,
-0x04, 0x2a, 0x04, 0x13, 0x03, 0x16, 0x01, 0x10, 0x01, 0x10, 0x04, 0x21,
-0x01, 0x47, 0x05, 0x18, 0x00, 0x04, 0x23, 0x23, 0x06, 0x06, 0x03, 0x54,
-0x01, 0x1d, 0x01, 0x1d, 0x04, 0x08, 0x00, 0x05, 0x1f, 0x1f, 0x38, 0x32,
-0x32, 0x00, 0x03, 0x01, 0x01, 0x62, 0x01, 0x62, 0x03, 0x04, 0x01, 0x20,
-0x01, 0x20, 0x03, 0x0c, 0x04, 0x14, 0x00, 0x07, 0x02, 0xaa, 0x74, 0x81,
-0x88, 0x74, 0x90, 0x00, 0x2b, 0x00, 0x00, 0x00, 0x83, 0x00, 0x00, 0x05,
-0x6b, 0x8b, 0xf4, 0xa6, 0xb4, 0x00, 0x04, 0xb8, 0x00, 0x0b, 0xb4, 0x7b,
-0x27, 0x29, 0x29, 0x27, 0x7b, 0x27, 0x7b, 0x12, 0x5a, 0x00, 0x03, 0x12,
-0x05, 0x02, 0x03, 0x14, 0x03, 0x0c, 0x01, 0x20, 0x01, 0x20, 0x03, 0x04,
-0x04, 0x62, 0x00, 0x04, 0x01, 0x01, 0x32, 0x38, 0x03, 0x1f, 0x03, 0x08,
-0x00, 0x04, 0x1d, 0x1d, 0x54, 0x54, 0x03, 0x06, 0x01, 0x23, 0x01, 0x23,
-0x04, 0x18, 0x03, 0x47, 0x01, 0x21, 0x01, 0x21, 0x03, 0x10, 0x03, 0x16,
-0x04, 0x13, 0x04, 0x2a, 0x05, 0x0f, 0x04, 0x4c, 0x04, 0x41, 0x04, 0x49,
-0x01, 0x67, 0x01, 0x67, 0x04, 0x78, 0x07, 0x3d, 0x05, 0x55, 0x06, 0x50,
-0x04, 0x5e, 0x05, 0x46, 0x06, 0x64, 0x01, 0x60, 0x01, 0x60, 0x05, 0x4e,
-0x05, 0x56, 0x14, 0x48, 0x05, 0x56, 0x06, 0x4e, 0x06, 0x64, 0x06, 0x46,
-0x05, 0x5e, 0x06, 0x50, 0x05, 0x55, 0x06, 0x3d, 0x03, 0x78, 0x03, 0x67,
-0x05, 0x49, 0x03, 0x41, 0x04, 0x4c, 0x05, 0x0f, 0x03, 0x2a, 0x05, 0x13,
-0x03, 0x16, 0x01, 0x10, 0x01, 0x10, 0x04, 0x21, 0x00, 0x07, 0x47, 0x47,
-0x18, 0x18, 0x58, 0x23, 0x23, 0x00, 0x03, 0x06, 0x03, 0x54, 0x01, 0x1d,
-0x01, 0x1d, 0x04, 0x08, 0x00, 0x05, 0x1f, 0x1f, 0x38, 0x32, 0x32, 0x00,
-0x03, 0x01, 0x01, 0x62, 0x01, 0x62, 0x03, 0x04, 0x01, 0x20, 0x01, 0x20,
-0x03, 0x0c, 0x04, 0x14, 0x00, 0x08, 0x02, 0x02, 0xc1, 0x6c, 0x6c, 0x74,
-0xa7, 0x6b, 0x2a, 0x00, 0x00, 0x00, 0x85, 0x00, 0x00, 0x05, 0xad, 0xea,
-0xb8, 0x37, 0xb4, 0x00, 0x04, 0xb8, 0x00, 0x04, 0xaf, 0xb4, 0xb4, 0x7b,
-0x04, 0x27, 0x01, 0x5a, 0x03, 0x12, 0x06, 0x02, 0x03, 0x14, 0x00, 0x04,
-0x0c, 0x0c, 0x20, 0x20, 0x03, 0x04, 0x03, 0x62, 0x00, 0x05, 0x01, 0x01,
-0x32, 0x32, 0x38, 0x00, 0x04, 0x1f, 0x00, 0x06, 0x08, 0x08, 0x1d, 0x1d,
-0x54, 0x54, 0x03, 0x06, 0x01, 0x23, 0x01, 0x23, 0x04, 0x18, 0x00, 0x04,
-0x47, 0x47, 0x21, 0x47, 0x03, 0x21, 0x00, 0x04, 0x10, 0x10, 0x16, 0x16,
-0x04, 0x13, 0x04, 0x2a, 0x06, 0x0f, 0x03, 0x4c, 0x03, 0x41, 0x03, 0x49,
-0x01, 0x67, 0x01, 0x49, 0x03, 0x67, 0x04, 0x78, 0x06, 0x3d, 0x06, 0x55,
-0x04, 0x50, 0x05, 0x5e, 0x05, 0x46, 0x04, 0x64, 0x01, 0x60, 0x03, 0x64,
-0x06, 0x4e, 0x05, 0x56, 0x12, 0x48, 0x06, 0x56, 0x05, 0x4e, 0x07, 0x64,
-0x06, 0x46, 0x04, 0x5e, 0x07, 0x50, 0x05, 0x55, 0x03, 0x3d, 0x00, 0x03,
-0x78, 0x3d, 0x3d, 0x00, 0x03, 0x78, 0x03, 0x67, 0x04, 0x49, 0x05, 0x41,
-0x01, 0x4c, 0x01, 0x4c, 0x06, 0x0f, 0x03, 0x2a, 0x05, 0x13, 0x03, 0x16,
-0x01, 0x10, 0x01, 0x10, 0x04, 0x21, 0x01, 0x47, 0x04, 0x18, 0x01, 0x23,
-0x01, 0x23, 0x03, 0x06, 0x03, 0x54, 0x01, 0x1d, 0x01, 0x1d, 0x04, 0x08,
-0x00, 0x05, 0x1f, 0x38, 0x38, 0x32, 0x32, 0x00, 0x03, 0x01, 0x01, 0x62,
-0x03, 0x04, 0x03, 0x20, 0x03, 0x0c, 0x04, 0x14, 0x00, 0x0a, 0x02, 0x5a,
-0xaa, 0x91, 0x6c, 0x6c, 0x81, 0xd9, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00,
-0x87, 0x00, 0x00, 0x05, 0xb2, 0xea, 0xa8, 0xb4, 0xb4, 0x00, 0x03, 0xaf,
-0x01, 0xa8, 0x03, 0xaf, 0x00, 0x04, 0xb4, 0xb4, 0x12, 0x7b, 0x03, 0x5a,
-0x01, 0x02, 0x01, 0x12, 0x04, 0x02, 0x01, 0x14, 0x01, 0x14, 0x04, 0x0c,
-0x01, 0x20, 0x01, 0x20, 0x04, 0x04, 0x03, 0x01, 0x00, 0x05, 0x32, 0x32,
-0x38, 0x38, 0x1f, 0x00, 0x05, 0x08, 0x00, 0x03, 0x1d, 0x54, 0x1d, 0x00,
-0x03, 0x06, 0x03, 0x23, 0x01, 0x18, 0x01, 0x18, 0x03, 0x47, 0x01, 0x21,
-0x01, 0x47, 0x04, 0x21, 0x00, 0x04, 0x10, 0x10, 0x16, 0x16, 0x04, 0x13,
-0x04, 0x2a, 0x05, 0x0f, 0x01, 0x4c, 0x01, 0x4c, 0x05, 0x41, 0x04, 0x49,
-0x04, 0x67, 0x01, 0x78, 0x01, 0x78, 0x08, 0x3d, 0x05, 0x55, 0x05, 0x50,
-0x04, 0x5e, 0x07, 0x46, 0x04, 0x64, 0x08, 0x4e, 0x03, 0x56, 0x13, 0x48,
-0x06, 0x56, 0x06, 0x4e, 0x01, 0x64, 0x01, 0x4e, 0x04, 0x64, 0x07, 0x46,
-0x05, 0x5e, 0x04, 0x50, 0x04, 0x55, 0x01, 0x3d, 0x01, 0x55, 0x03, 0x3d,
-0x06, 0x78, 0x04, 0x67, 0x01, 0x49, 0x01, 0x49, 0x05, 0x41, 0x03, 0x4c,
-0x05, 0x0f, 0x04, 0x2a, 0x03, 0x13, 0x04, 0x16, 0x00, 0x04, 0x10, 0x10,
-0x21, 0x21, 0x05, 0x47, 0x01, 0x58, 0x01, 0x58, 0x03, 0x23, 0x04, 0x06,
-0x04, 0x1d, 0x04, 0x08, 0x03, 0x38, 0x00, 0x03, 0x32, 0x01, 0x01, 0x00,
-0x05, 0x04, 0x06, 0x0c, 0x07, 0x02, 0x00, 0x08, 0x5a, 0x5a, 0x74, 0x8f,
-0x8f, 0x80, 0xd0, 0x4d, 0x29, 0x00, 0x00, 0x00, 0x85, 0x00, 0x00, 0x07,
-0x03, 0x00, 0x00, 0x0d, 0x75, 0x8b, 0x88, 0x00, 0x04, 0xaf, 0x06, 0xa8,
-0x03, 0xaf, 0x03, 0xaa, 0x03, 0x14, 0x0c, 0xaa, 0x01, 0x62, 0x06, 0x01,
-0x07, 0x1f, 0x06, 0x54, 0x01, 0x06, 0x04, 0xb7, 0x03, 0x18, 0x03, 0x16,
-0x01, 0x10, 0x03, 0x16, 0x04, 0xf3, 0x00, 0x04, 0x13, 0xf3, 0xf3, 0x2a,
-0x08, 0x0f, 0x00, 0x05, 0x4c, 0x4c, 0xfb, 0xfb, 0x41, 0x00, 0x06, 0x49,
-0x01, 0x67, 0x01, 0x67, 0x09, 0x78, 0x03, 0x3d, 0x07, 0x55, 0x05, 0x50,
-0x06, 0x5e, 0x06, 0x46, 0x03, 0x64, 0x05, 0x60, 0x07, 0x4e, 0x10, 0x56,
-0x04, 0x4e, 0x00, 0x04, 0x60, 0x60, 0x4e, 0x4e, 0x04, 0x60, 0x04, 0x64,
-0x0a, 0x46, 0x01, 0x5e, 0x01, 0x5e, 0x05, 0x50, 0x07, 0x55, 0x03, 0x3d,
-0x00, 0x03, 0x78, 0x3d, 0x3d, 0x00, 0x07, 0x78, 0x01, 0x67, 0x01, 0x67,
-0x06, 0x49, 0x01, 0x41, 0x07, 0x4c, 0x05, 0x0f, 0x03, 0x2a, 0x06, 0x13,
-0x06, 0x16, 0x00, 0x03, 0xb7, 0xb7, 0x16, 0x00, 0x08, 0xb7, 0x06, 0x54,
-0x08, 0x1f, 0x04, 0x01, 0x00, 0x04, 0x62, 0xaa, 0x62, 0xaa, 0x03, 0x20,
-0x03, 0xaa, 0x00, 0x0b, 0x14, 0x14, 0x02, 0xf8, 0x8f, 0xcc, 0x8f, 0xcc,
-0xe7, 0x00, 0x03, 0x00, 0x27, 0x00, 0x00, 0x00, 0x86, 0x00, 0x01, 0x0d,
-0x01, 0x11, 0x03, 0x00, 0x00, 0x05, 0x6b, 0x7e, 0xcf, 0x88, 0xa8, 0x00,
-0x03, 0xaf, 0x03, 0xa8, 0x03, 0x72, 0x06, 0xa8, 0x00, 0x06, 0x72, 0xa8,
-0xa8, 0x72, 0x72, 0xa8, 0x23, 0x72, 0x1d, 0x74, 0x13, 0x80, 0x00, 0x04,
-0x81, 0x80, 0x80, 0x81, 0x04, 0x80, 0x1b, 0x81, 0x00, 0x04, 0x91, 0x91,
-0x81, 0x91, 0x34, 0x6c, 0x03, 0x7a, 0x01, 0x6c, 0x22, 0x7a, 0x03, 0x77,
-0x00, 0x03, 0x7a, 0x7a, 0x77, 0x00, 0x03, 0x7a, 0x05, 0x77, 0x01, 0x7a,
-0x2a, 0x77, 0x03, 0xcc, 0x00, 0x04, 0x91, 0xd9, 0x00, 0x03, 0x27, 0x00,
-0x00, 0x00, 0x8e, 0x00, 0x00, 0x0b, 0x8e, 0x7e, 0xea, 0x8f, 0x88, 0xa8,
-0xaf, 0xaf, 0xa8, 0x72, 0x72, 0x00, 0x3d, 0x88, 0x2c, 0x81, 0x01, 0x6c,
-0x09, 0x81, 0x01, 0x6c, 0x03, 0x81, 0x2e, 0x6c, 0x28, 0x8f, 0x1c, 0xcc,
-0x01, 0xa7, 0x03, 0xcc, 0x00, 0x05, 0xa7, 0xcc, 0xa7, 0xa7, 0xcc, 0x00,
-0x14, 0xa7, 0x13, 0x9d, 0x00, 0x07, 0xa7, 0x9d, 0x9d, 0x77, 0xec, 0x00,
-0x03, 0x00, 0x27, 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x08, 0x6b, 0xb2,
-0x7d, 0xd0, 0xea, 0xcc, 0x81, 0x88, 0x12, 0xc1, 0x00, 0x03, 0x72, 0x72,
-0xc1, 0x00, 0x24, 0x72, 0x01, 0x74, 0x03, 0x72, 0x01, 0x74, 0x01, 0x72,
-0x27, 0x74, 0x2c, 0x80, 0x01, 0x91, 0x01, 0x80, 0x23, 0x91, 0x05, 0x7a,
-0x01, 0x91, 0x18, 0x7a, 0x04, 0x77, 0x01, 0x7a, 0x1b, 0x77, 0x01, 0x60,
-0x01, 0x64, 0x24, 0x60, 0x00, 0x05, 0x77, 0xfa, 0x6b, 0x00, 0x0d, 0x00,
-0x27, 0x00, 0x00, 0x00, 0x95, 0x00, 0x00, 0x08, 0x71, 0x7c, 0xe7, 0xec,
-0x7e, 0x7d, 0x68, 0x90, 0x45, 0x8b, 0x00, 0x03, 0x90, 0x90, 0x8b, 0x00,
-0x2b, 0x90, 0x01, 0x68, 0x04, 0x90, 0x4d, 0x68, 0x00, 0x03, 0x7d, 0x7d,
-0x68, 0x00, 0x4f, 0x7d, 0x00, 0x04, 0xd9, 0x8e, 0x00, 0x0d, 0x28, 0x00,
-0x00, 0x00, 0x9d, 0x00, 0xff, 0x0d, 0x18, 0x0d, 0x2c, 0x00, 0x00, 0x00,
-0x95, 0x00, 0x01, 0x0d, 0x03, 0x03, 0x00, 0x03, 0x11, 0x11, 0x0d, 0x00,
-0xff, 0x00, 0x1a, 0x00, 0x01, 0x0d, 0x2a, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x01
-};
diff --git a/include/stdio_dev.h b/include/stdio_dev.h
index 7f18102..4e3c470 100644
--- a/include/stdio_dev.h
+++ b/include/stdio_dev.h
@@ -17,6 +17,7 @@
#define DEV_FLAGS_INPUT 0x00000001 /* Device can be used as input console */
#define DEV_FLAGS_OUTPUT 0x00000002 /* Device can be used as output console */
#define DEV_FLAGS_DM 0x00000004 /* Device priv is a struct udevice * */
+#define STDIO_NAME_LEN 32
int stdio_file_to_flags(const int file);
@@ -24,7 +25,7 @@
struct stdio_dev {
int flags; /* Device flags: input/output/system */
int ext; /* Supported extensions */
- char name[32]; /* Device name */
+ char name[STDIO_NAME_LEN]; /* Device name */
/* GENERAL functions */
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/include/sunxi_gpio.h
similarity index 75%
rename from arch/arm/include/asm/arch-sunxi/gpio.h
rename to include/sunxi_gpio.h
index 6eaeece..db3742c 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/include/sunxi_gpio.h
@@ -3,13 +3,29 @@
* (C) Copyright 2007-2012
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
* Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Definitions that are shared between the Allwinner pinctrl and GPIO drivers,
+ * also used by some non-DM SPL code directly.
*/
#ifndef _SUNXI_GPIO_H
#define _SUNXI_GPIO_H
#include <linux/types.h>
-#include <asm/arch/cpu.h>
+
+#if defined(CONFIG_MACH_SUN9I)
+#define SUNXI_PIO_BASE 0x06000800
+#define SUNXI_R_PIO_BASE 0x08002c00
+#elif defined(CONFIG_SUN50I_GEN_H6)
+#define SUNXI_PIO_BASE 0x0300b000
+#define SUNXI_R_PIO_BASE 0x07022000
+#elif defined(CONFIG_SUNXI_GEN_NCAT2)
+#define SUNXI_PIO_BASE 0x02000000
+#define SUNXI_R_PIO_BASE 0x07022000
+#else
+#define SUNXI_PIO_BASE 0x01c20800
+#define SUNXI_R_PIO_BASE 0x01f02c00
+#endif
/*
* sunxi has 9 banks of gpio, they are:
@@ -29,13 +45,6 @@
#define SUNXI_GPIO_I 8
/*
- * This defines the number of GPIO banks for the _main_ GPIO controller.
- * You should fix up the padding in struct sunxi_gpio_reg below if you
- * change this.
- */
-#define SUNXI_GPIO_BANKS 9
-
-/*
* sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO)
* at a different register offset.
*
@@ -52,47 +61,9 @@
#define SUNXI_GPIO_M 12
#define SUNXI_GPIO_N 13
-struct sunxi_gpio {
- u32 cfg[4];
- u32 dat;
- u32 drv[2];
- u32 pull[2];
-};
-
-/* gpio interrupt control */
-struct sunxi_gpio_int {
- u32 cfg[3];
- u32 ctl;
- u32 sta;
- u32 deb; /* interrupt debounce */
-};
-
-struct sunxi_gpio_reg {
- struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS];
- u8 res[0xbc];
- struct sunxi_gpio_int gpio_int;
-};
-
#define SUN50I_H6_GPIO_POW_MOD_SEL 0x340
#define SUN50I_H6_GPIO_POW_MOD_VAL 0x348
-#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \
- &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
- &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L])
-
-#define GPIO_BANK(pin) ((pin) >> 5)
-#define GPIO_NUM(pin) ((pin) & 0x1f)
-
-#define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3)
-#define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1f) & 0x7) << 2)
-
-#define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4)
-#define GPIO_DRV_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1)
-
-#define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4)
-#define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1)
-
-/* GPIO bank sizes */
#define SUNXI_GPIOS_PER_BANK 32
#define SUNXI_GPIO_NEXT(__gpio) \
@@ -133,7 +104,6 @@
/* GPIO pin function config */
#define SUNXI_GPIO_INPUT 0
#define SUNXI_GPIO_OUTPUT 1
-#define SUNXI_GPIO_DISABLE 7
#define SUN8I_H3_GPA_UART0 2
#define SUN8I_H3_GPA_UART2 2
@@ -202,6 +172,14 @@
#define SUN9I_GPN_R_RSB 3
+#ifdef CONFIG_SUNXI_NEW_PINCTRL
+ #define SUNXI_PINCTRL_BANK_SIZE 0x30
+ #define SUNXI_GPIO_DISABLE 0xf
+#else
+ #define SUNXI_PINCTRL_BANK_SIZE 0x24
+ #define SUNXI_GPIO_DISABLE 0x7
+#endif
+
/* GPIO pin pull-up/down config */
#define SUNXI_GPIO_PULL_DISABLE 0
#define SUNXI_GPIO_PULL_UP 1
@@ -213,18 +191,19 @@
#define SUNXI_GPIO_AXP0_GPIO_COUNT 6
struct sunxi_gpio_plat {
- struct sunxi_gpio *regs;
+ void *regs;
char bank_name[3];
};
-void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
+/* prototypes for the non-DM GPIO/pinctrl functions, used in the SPL */
+void sunxi_gpio_set_cfgbank(void *bank_base, int pin_offset, u32 val);
void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
-int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
+int sunxi_gpio_get_cfgbank(void *bank_base, int pin_offset);
int sunxi_gpio_get_cfgpin(u32 pin);
void sunxi_gpio_set_drv(u32 pin, u32 val);
-void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val);
+void sunxi_gpio_set_drv_bank(void *bank_base, u32 pin_offset, u32 val);
void sunxi_gpio_set_pull(u32 pin, u32 val);
-void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val);
+void sunxi_gpio_set_pull_bank(void *bank_base, int pin_offset, u32 val);
int sunxi_name_to_gpio(const char *name);
#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
diff --git a/include/system-constants.h b/include/system-constants.h
index 0d6b71b..5937156 100644
--- a/include/system-constants.h
+++ b/include/system-constants.h
@@ -22,11 +22,23 @@
/*
* Typically, we have the SPL malloc pool at the end of the BSS area.
*/
-#ifdef CONFIG_HAS_CUSTOM_SPL_MALLOC_START
-#define SYS_SPL_MALLOC_START CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR
-#else
-#define SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+#ifdef CONFIG_SPL_HAS_CUSTOM_MALLOC_START
+#define SPL_SYS_MALLOC_START CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR
+#elif defined(CONFIG_SPL_BSS_START_ADDR)
+#define SPL_SYS_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
CONFIG_SPL_BSS_MAX_SIZE)
+#else
+/* feature not enabled: this value avoids compiler errors but is not used */
+#define SPL_SYS_MALLOC_START 0
+#endif
+#define SPL_SYS_MALLOC_SIZE \
+ IF_ENABLED_INT(CONFIG_SPL_SYS_MALLOC, CONFIG_SPL_SYS_MALLOC_SIZE)
+
+/* deal with an optional value */
+#ifdef CONFIG_SPL_OS_BOOT
+#define SPL_PAYLOAD_ARGS_ADDR CONFIG_SPL_PAYLOAD_ARGS_ADDR
+#else
+#define SPL_PAYLOAD_ARGS_ADDR 0
#endif
#endif
diff --git a/include/test/cedit-test.h b/include/test/cedit-test.h
index 349df75..475ecc9 100644
--- a/include/test/cedit-test.h
+++ b/include/test/cedit-test.h
@@ -24,6 +24,9 @@
#define ID_AC_ON 11
#define ID_AC_MEMORY 12
-#define ID_DYNAMIC_START 13
+#define ID_MACHINE_NAME 13
+#define ID_MACHINE_NAME_EDIT 14
+
+#define ID_DYNAMIC_START 15
#endif
diff --git a/include/test/spl.h b/include/test/spl.h
new file mode 100644
index 0000000..c1f6465
--- /dev/null
+++ b/include/test/spl.h
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 Sean Anderson <seanga2@gmail.com>
+ */
+
+#ifndef TEST_SPL_H
+#define TEST_SPL_H
+
+struct unit_test_state;
+struct spl_image_info;
+
+/* Declare a new SPL test */
+#define SPL_TEST(_name, _flags) UNIT_TEST(_name, _flags, spl_test)
+
+/**
+ * generate_data() - Generate some test payload data
+ * @data: The location to fill
+ * @size: The size of @data
+ * @test_name: The seed for the data
+ *
+ * Fill @data with data. The upper nibbles will be an incrementing counter
+ * (0x00, 0x10, 0x20...) to make the data identifiable in a hex dump. The lower
+ * nibbles are random bits seeded with @test_name.
+ */
+void generate_data(char *data, size_t size, const char *test_name);
+
+/**
+ * enum spl_test_image - Image types for testing
+ * @LEGACY: "Legacy" uImages
+ * @LEGACY_LZMA: "Legacy" uImages, LZMA compressed
+ * @IMX8: i.MX8 Container images
+ * @FIT_INTERNAL: FITs with internal data
+ * @FIT_EXTERNAL: FITs with external data
+ */
+enum spl_test_image {
+ LEGACY,
+ LEGACY_LZMA,
+ IMX8,
+ FIT_INTERNAL,
+ FIT_EXTERNAL,
+};
+
+/**
+ * create_image() - Create an image for testing
+ * @dst: The location to create the image at
+ * @type: The type of image to create
+ * @info: Image parameters
+ * @data_offset: Offset of payload data within the image
+ *
+ * Create a new image at @dst. @dst must be initialized to all zeros. @info
+ * should already have name and size filled in. All other parameters will be
+ * filled in by this function. @info can later be passed to check_image_info().
+ *
+ * If @dst is %NULL, then no data is written. Otherwise, @dst must be
+ * initialized to zeros, except payload data which must already be present at
+ * @data_offset. @data_offset may be %NULL if unnecessary.
+ *
+ * Typically, this function will be called as follows:
+ *
+ * size = create_image(NULL, type, &info, &off);
+ * img = calloc(size, 1);
+ * generate_data(img + off, ...);
+ * create_image(img, type, &info, NULL);
+ *
+ * Return: The size of the image, or 0 on error
+ */
+size_t create_image(void *dst, enum spl_test_image type,
+ struct spl_image_info *info, size_t *data_offset);
+
+/**
+ * check_image_info() - Check image info after loading
+ * @uts: Current unit test state
+ * @info1: The base, known good info
+ * @info2: The info to check
+ *
+ * Check @info2 against @info1. This function is typically called after calling
+ * a function to load/parse an image. Image data is not checked.
+ *
+ * Return: 0 on success, or 1 on failure
+ */
+int check_image_info(struct unit_test_state *uts, struct spl_image_info *info1,
+ struct spl_image_info *info2);
+
+/**
+ * typedef write_image_t - Callback for writing an image
+ * @uts: Current unit test state
+ * @img: Image to write
+ * @size: Size of @img
+ *
+ * Write @img to a location which will be read by a &struct spl_image_loader.
+ *
+ * Return: 0 on success or 1 on failure
+ */
+typedef int write_image_t(struct unit_test_state *its, void *img, size_t size);
+
+/**
+ * do_spl_test_load() - Test loading with an SPL image loader
+ * @uts: Current unit test state
+ * @test_name: Name of the current test
+ * @type: Type of image to try loading
+ * @loader: The loader to test
+ * @write_image: Callback to write the image to the backing storage
+ *
+ * Test @loader, performing the common tasks of setting up the image and
+ * checking it was loaded correctly. The caller must supply a @write_image
+ * callback to write the image to a location which will be read by @loader.
+ *
+ * Return: 0 on success or 1 on failure
+ */
+int do_spl_test_load(struct unit_test_state *uts, const char *test_name,
+ enum spl_test_image type, struct spl_image_loader *loader,
+ write_image_t write_image);
+
+/**
+ * image_supported() - Determine whether an image type is supported
+ * @type: The image type to check
+ *
+ * Return: %true if supported and %false otherwise
+ */
+static inline bool image_supported(enum spl_test_image type)
+{
+ switch (type) {
+ case LEGACY_LZMA:
+ if (!IS_ENABLED(CONFIG_SPL_LZMA))
+ return false;
+ case LEGACY:
+ return IS_ENABLED(CONFIG_SPL_LEGACY_IMAGE_FORMAT);
+ case IMX8:
+ return IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER);
+ case FIT_INTERNAL:
+ case FIT_EXTERNAL:
+ return IS_ENABLED(CONFIG_SPL_LOAD_FIT) ||
+ IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL);
+ }
+
+ return false;
+}
+
+/* Declare an image test (skipped if the image type is unsupported) */
+#define SPL_IMG_TEST(func, type, flags) \
+static int func##_##type(struct unit_test_state *uts) \
+{ \
+ if (!image_supported(type)) \
+ return -EAGAIN; \
+ return func(uts, __func__, type); \
+} \
+SPL_TEST(func##_##type, flags)
+
+/* More than a couple blocks, and will not be aligned to anything */
+#define SPL_TEST_DATA_SIZE 4099
+
+/* Flags necessary for accessing DM devices */
+#define DM_FLAGS (UT_TESTF_DM | UT_TESTF_SCAN_FDT)
+
+#endif /* TEST_SPL_H */
diff --git a/include/test/suites.h b/include/test/suites.h
index 1c7dc65..ad4fc92 100644
--- a/include/test/suites.h
+++ b/include/test/suites.h
@@ -45,6 +45,8 @@
int do_ut_lib(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
int do_ut_loadm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
int do_ut_log(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]);
+int do_ut_mbr(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
+int do_ut_measurement(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]);
int do_ut_mem(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
int do_ut_optee(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
int do_ut_overlay(struct cmd_tbl *cmdtp, int flag, int argc,
diff --git a/include/thor.h b/include/thor.h
index ee67ab0..3cb56b6 100644
--- a/include/thor.h
+++ b/include/thor.h
@@ -14,7 +14,7 @@
#define THOR_DFU_REINIT_NEEDED 0xFFFFFFFE
-int thor_handle(void);
-int thor_init(void);
+int thor_handle(struct udevice *udc);
+int thor_init(struct udevice *udc);
int thor_add(struct usb_configuration *c);
#endif /* __THOR_H_ */
diff --git a/include/ti-usb-phy-uboot.h b/include/ti-usb-phy-uboot.h
index cd2ba40..feeddb8 100644
--- a/include/ti-usb-phy-uboot.h
+++ b/include/ti-usb-phy-uboot.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* include/ti_usb_phy_uboot.h
*
- * Copyright (c) 2014 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (c) 2014 Texas Instruments Incorporated - https://www.ti.com
*
* USB2 and USB3 PHY uboot init
*/
diff --git a/include/tpm-v2.h b/include/tpm-v2.h
index 2b6980e..33dd103 100644
--- a/include/tpm-v2.h
+++ b/include/tpm-v2.h
@@ -169,7 +169,7 @@
/**
* Definition of TPMU_HA Union
*/
-union tmpu_ha {
+union tpmu_ha {
u8 sha1[TPM2_SHA1_DIGEST_SIZE];
u8 sha256[TPM2_SHA256_DIGEST_SIZE];
u8 sm3_256[TPM2_SM3_256_DIGEST_SIZE];
@@ -185,7 +185,7 @@
*/
struct tpmt_ha {
u16 hash_alg;
- union tmpu_ha digest;
+ union tpmu_ha digest;
} __packed;
/**
@@ -217,6 +217,50 @@
} __packed;
/**
+ * struct TCG_EfiSpecIdEventAlgorithmSize - hashing algorithm information
+ *
+ * @algorithm_id: algorithm defined in enum tpm2_algorithms
+ * @digest_size: size of the algorithm
+ */
+struct tcg_efi_spec_id_event_algorithm_size {
+ u16 algorithm_id;
+ u16 digest_size;
+} __packed;
+
+#define TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03 "Spec ID Event03"
+#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2 2
+#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2 0
+#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2 2
+
+/**
+ * struct TCG_EfiSpecIDEventStruct - content of the event log header
+ *
+ * @signature: signature, set to Spec ID Event03
+ * @platform_class: class defined in TCG ACPI Specification
+ * Client Common Header.
+ * @spec_version_minor: minor version
+ * @spec_version_major: major version
+ * @spec_version_errata: major version
+ * @uintn_size: size of the efi_uintn_t fields used in various
+ * data structures used in this specification.
+ * 0x01 indicates u32 and 0x02 indicates u64
+ * @number_of_algorithms: hashing algorithms used in this event log
+ * @digest_sizes: array of number_of_algorithms pairs
+ * 1st member defines the algorithm id
+ * 2nd member defines the algorithm size
+ */
+struct tcg_efi_spec_id_event {
+ u8 signature[16];
+ u32 platform_class;
+ u8 spec_version_minor;
+ u8 spec_version_major;
+ u8 spec_errata;
+ u8 uintn_size;
+ u32 number_of_algorithms;
+ struct tcg_efi_spec_id_event_algorithm_size digest_sizes[];
+} __packed;
+
+/**
* TPM2 Structure Tags for command/response buffers.
*
* @TPM2_ST_NO_SESSIONS: the command does not need an authentication.
@@ -342,6 +386,26 @@
TPM2_ALG_SM3_256 = 0x12,
};
+extern const enum tpm2_algorithms tpm2_supported_algorithms[4];
+
+static inline u16 tpm2_algorithm_to_len(enum tpm2_algorithms a)
+{
+ switch (a) {
+ case TPM2_ALG_SHA1:
+ return TPM2_SHA1_DIGEST_SIZE;
+ case TPM2_ALG_SHA256:
+ return TPM2_SHA256_DIGEST_SIZE;
+ case TPM2_ALG_SHA384:
+ return TPM2_SHA384_DIGEST_SIZE;
+ case TPM2_ALG_SHA512:
+ return TPM2_SHA512_DIGEST_SIZE;
+ default:
+ return 0;
+ }
+}
+
+#define tpm2_algorithm_to_mask(a) (1 << (a))
+
/* NV index attributes */
enum tpm_index_attrs {
TPMA_NV_PPWRITE = 1UL << 0,
@@ -422,6 +486,188 @@
};
/**
+ * struct tcg2_event_log - Container for managing the platform event log
+ *
+ * @log: Address of the log
+ * @log_position: Current entry position
+ * @log_size: Log space available
+ * @found: Boolean indicating if an existing log was discovered
+ */
+struct tcg2_event_log {
+ u8 *log;
+ u32 log_position;
+ u32 log_size;
+ bool found;
+};
+
+/**
+ * Create a list of digests of the supported PCR banks for a given input data
+ *
+ * @dev TPM device
+ * @input Data
+ * @length Length of the data to calculate the digest
+ * @digest_list List of digests to fill in
+ *
+ * Return: zero on success, negative errno otherwise
+ */
+int tcg2_create_digest(struct udevice *dev, const u8 *input, u32 length,
+ struct tpml_digest_values *digest_list);
+
+/**
+ * Get the event size of the specified digests
+ *
+ * @digest_list List of digests for the event
+ *
+ * Return: Size in bytes of the event
+ */
+u32 tcg2_event_get_size(struct tpml_digest_values *digest_list);
+
+/**
+ * tcg2_get_active_pcr_banks
+ *
+ * @dev TPM device
+ * @active_pcr_banks Bitmask of PCR algorithms supported
+ *
+ * Return: zero on success, negative errno otherwise
+ */
+int tcg2_get_active_pcr_banks(struct udevice *dev, u32 *active_pcr_banks);
+
+/**
+ * tcg2_log_append - Append an event to an event log
+ *
+ * @pcr_index Index of the PCR
+ * @event_type Type of event
+ * @digest_list List of digests to add
+ * @size Size of event
+ * @event Event data
+ * @log Log buffer to append the event to
+ */
+void tcg2_log_append(u32 pcr_index, u32 event_type,
+ struct tpml_digest_values *digest_list, u32 size,
+ const u8 *event, u8 *log);
+
+/**
+ * Extend the PCR with specified digests
+ *
+ * @dev TPM device
+ * @pcr_index Index of the PCR
+ * @digest_list List of digests to extend
+ *
+ * Return: zero on success, negative errno otherwise
+ */
+int tcg2_pcr_extend(struct udevice *dev, u32 pcr_index,
+ struct tpml_digest_values *digest_list);
+
+/**
+ * Read the PCR into a list of digests
+ *
+ * @dev TPM device
+ * @pcr_index Index of the PCR
+ * @digest_list List of digests to extend
+ *
+ * Return: zero on success, negative errno otherwise
+ */
+int tcg2_pcr_read(struct udevice *dev, u32 pcr_index,
+ struct tpml_digest_values *digest_list);
+
+/**
+ * Measure data into the TPM PCRs and the platform event log.
+ *
+ * @dev TPM device
+ * @log Platform event log
+ * @pcr_index Index of the PCR
+ * @size Size of the data or 0 for event only
+ * @data Pointer to the data or NULL for event only
+ * @event_type Event log type
+ * @event_size Size of the event
+ * @event Pointer to the event
+ *
+ * Return: zero on success, negative errno otherwise
+ */
+int tcg2_measure_data(struct udevice *dev, struct tcg2_event_log *elog,
+ u32 pcr_index, u32 size, const u8 *data, u32 event_type,
+ u32 event_size, const u8 *event);
+
+#define tcg2_measure_event(dev, elog, pcr_index, event_type, size, event) \
+ tcg2_measure_data(dev, elog, pcr_index, 0, NULL, event_type, size, \
+ event)
+
+/**
+ * Prepare the event log buffer. This function tries to discover an existing
+ * event log in memory from a previous bootloader stage. If such a log exists
+ * and the PCRs are not extended, the log is "replayed" to extend the PCRs.
+ * If no log is discovered, create the log header.
+ *
+ * @dev TPM device
+ * @elog Platform event log. The log pointer and log_size
+ * members must be initialized to either 0 or to a valid
+ * memory region, in which case any existing log
+ * discovered will be copied to the specified memory
+ * region.
+ * @ignore_existing_log Boolean to indicate whether or not to ignore an
+ * existing platform log in memory
+ *
+ * Return: zero on success, negative errno otherwise
+ */
+int tcg2_log_prepare_buffer(struct udevice *dev, struct tcg2_event_log *elog,
+ bool ignore_existing_log);
+
+/**
+ * Begin measurements.
+ *
+ * @dev TPM device
+ * @elog Platform event log. The log pointer and log_size
+ * members must be initialized to either 0 or to a valid
+ * memory region, in which case any existing log
+ * discovered will be copied to the specified memory
+ * region.
+ * @ignore_existing_log Boolean to indicate whether or not to ignore an
+ * existing platform log in memory
+ *
+ * Return: zero on success, negative errno otherwise
+ */
+int tcg2_measurement_init(struct udevice **dev, struct tcg2_event_log *elog,
+ bool ignore_existing_log);
+
+/**
+ * Stop measurements and record separator events.
+ *
+ * @dev TPM device
+ * @elog Platform event log
+ * @error Boolean to indicate whether an error ocurred or not
+ */
+void tcg2_measurement_term(struct udevice *dev, struct tcg2_event_log *elog,
+ bool error);
+
+/**
+ * Get the platform event log address and size.
+ *
+ * @dev TPM device
+ * @addr Address of the log
+ * @size Size of the log
+ *
+ * Return: zero on success, negative errno otherwise
+ */
+int tcg2_platform_get_log(struct udevice *dev, void **addr, u32 *size);
+
+/**
+ * Get the first TPM2 device found.
+ *
+ * @dev TPM device
+ *
+ * Return: zero on success, negative errno otherwise
+ */
+int tcg2_platform_get_tpm2(struct udevice **dev);
+
+/**
+ * Platform-specific function for handling TPM startup errors
+ *
+ * @dev TPM device
+ * @rc The TPM response code
+ */
+void tcg2_platform_startup_error(struct udevice *dev, int rc);
+
+/**
* Issue a TPM2_Startup command.
*
* @dev TPM device
@@ -541,6 +787,19 @@
void *buf, size_t prop_count);
/**
+ * tpm2_get_pcr_info() - get the supported, active PCRs and number of banks
+ *
+ * @dev: TPM device
+ * @supported_pcr: bitmask with the algorithms supported
+ * @active_pcr: bitmask with the active algorithms
+ * @pcr_banks: number of PCR banks
+ *
+ * @return 0 on success, code of operation or negative errno on failure
+ */
+int tpm2_get_pcr_info(struct udevice *dev, u32 *supported_pcr, u32 *active_pcr,
+ u32 *pcr_banks);
+
+/**
* Issue a TPM2_DictionaryAttackLockReset command.
*
* @dev TPM device
diff --git a/include/usb/xhci.h b/include/usb/xhci.h
index 4a4ac10..04d16a2 100644
--- a/include/usb/xhci.h
+++ b/include/usb/xhci.h
@@ -901,6 +901,8 @@
/* TRB type IDs */
typedef enum {
+ /* reserved, used as a software sentinel */
+ TRB_NONE = 0,
/* bulk, interrupt, isoc scatter/gather, and control data stage */
TRB_NORMAL = 1,
/* setup stage for control transfers */
diff --git a/include/usb_mass_storage.h b/include/usb_mass_storage.h
index 08ccc97..83ab93b 100644
--- a/include/usb_mass_storage.h
+++ b/include/usb_mass_storage.h
@@ -25,7 +25,7 @@
struct blk_desc block_dev;
};
-int fsg_init(struct ums *ums_devs, int count, unsigned int controller_idx);
+int fsg_init(struct ums *ums_devs, int count, struct udevice *udc);
void fsg_cleanup(void);
int fsg_main_thread(void *);
int fsg_add(struct usb_configuration *c);
diff --git a/include/uuid.h b/include/uuid.h
index 89b93e6..f5a9412 100644
--- a/include/uuid.h
+++ b/include/uuid.h
@@ -12,6 +12,51 @@
#include <linux/bitops.h>
+/*
+ * UUID - Universally Unique IDentifier - 128 bits unique number.
+ * There are 5 versions and one variant of UUID defined by RFC4122
+ * specification. A UUID contains a set of fields. The set varies
+ * depending on the version of the UUID, as shown below:
+ * - time, MAC address(v1),
+ * - user ID(v2),
+ * - MD5 of name or URL(v3),
+ * - random data(v4),
+ * - SHA-1 of name or URL(v5),
+ *
+ * Layout of UUID:
+ * timestamp - 60-bit: time_low, time_mid, time_hi_and_version
+ * version - 4 bit (bit 4 through 7 of the time_hi_and_version)
+ * clock seq - 14 bit: clock_seq_hi_and_reserved, clock_seq_low
+ * variant: - bit 6 and 7 of clock_seq_hi_and_reserved
+ * node - 48 bit
+ *
+ * source: https://www.ietf.org/rfc/rfc4122.txt
+ *
+ * UUID binary format (16 bytes):
+ *
+ * 4B-2B-2B-2B-6B (big endian - network byte order)
+ *
+ * UUID string is 36 length of characters (36 bytes):
+ *
+ * 0 9 14 19 24
+ * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
+ * be be be be be
+ *
+ * where x is a hexadecimal character. Fields are separated by '-'s.
+ * When converting to a binary UUID, le means the field should be converted
+ * to little endian and be means it should be converted to big endian.
+ *
+ * UUID is also used as GUID (Globally Unique Identifier) with the same binary
+ * format but it differs in string format like below.
+ *
+ * GUID:
+ * 0 9 14 19 24
+ * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
+ * le le le be be
+ *
+ * GUID is used e.g. in GPT (GUID Partition Table) as a partiions unique id.
+ */
+
/* This is structure is in big-endian */
struct uuid {
unsigned int time_low;
@@ -40,20 +85,78 @@
#define UUID_VARIANT 0x1
int uuid_str_valid(const char *uuid);
+
+/*
+ * uuid_str_to_bin() - convert string UUID or GUID to big endian binary data.
+ *
+ * @param uuid_str - pointer to UUID or GUID string [37B] or GUID shorcut
+ * @param uuid_bin - pointer to allocated array for big endian output [16B]
+ * @str_format - UUID string format: 0 - UUID; 1 - GUID
+ * Return: 0 if OK, -EINVAL if the string is not a valid UUID
+ */
int uuid_str_to_bin(const char *uuid_str, unsigned char *uuid_bin,
int str_format);
+
+/*
+ * uuid_bin_to_str() - convert big endian binary data to string UUID or GUID.
+ *
+ * @param uuid_bin: pointer to binary data of UUID (big endian) [16B]
+ * @param uuid_str: pointer to allocated array for output string [37B]
+ * @str_format: bit 0: 0 - UUID; 1 - GUID
+ * bit 1: 0 - lower case; 2 - upper case
+ */
void uuid_bin_to_str(const unsigned char *uuid_bin, char *uuid_str,
int str_format);
+
+/*
+ * uuid_guid_get_bin() - this function get GUID bin for string
+ *
+ * @param guid_str - pointer to partition type string
+ * @param guid_bin - pointer to allocated array for big endian output [16B]
+ */
int uuid_guid_get_bin(const char *guid_str, unsigned char *guid_bin);
+
+/*
+ * uuid_guid_get_str() - this function get string for GUID.
+ *
+ * @param guid_bin - pointer to string with partition type guid [16B]
+ *
+ * Returns NULL if the type GUID is not known.
+ */
const char *uuid_guid_get_str(const unsigned char *guid_bin);
+
+/*
+ * gen_rand_uuid() - this function generates a random binary UUID version 4.
+ * In this version all fields beside 4 bits of version and
+ * 2 bits of variant are randomly generated.
+ *
+ * @param uuid_bin - pointer to allocated array [16B]. Output is in big endian.
+ */
void gen_rand_uuid(unsigned char *uuid_bin);
+
+/*
+ * gen_rand_uuid_str() - this function generates UUID v4 (random) in two string
+ * formats UUID or GUID.
+ *
+ * @param uuid_str - pointer to allocated array [37B].
+ * @param - uuid output type: UUID - 0, GUID - 1
+ */
void gen_rand_uuid_str(char *uuid_str, int str_format);
/**
* uuid_str_to_le_bin() - Convert string UUID to little endian binary data.
* @uuid_str: pointer to UUID string
* @uuid_bin: pointer to allocated array for little endian output [16B]
+ *
+ * UUID string is 36 characters (36 bytes):
+ *
+ * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
+ *
+ * where x is a hexadecimal character. Fields are separated by '-'s.
+ * When converting to a little endian binary UUID, the string fields are reversed.
+ *
* Return:
+ *
* uuid_bin filled with little endian UUID data
* On success 0 is returned. Otherwise, failure code.
*/
diff --git a/include/video.h b/include/video.h
index 16f7a83..4d8df9b 100644
--- a/include/video.h
+++ b/include/video.h
@@ -21,9 +21,12 @@
* @align: Frame-buffer alignment, indicating the memory boundary the frame
* buffer should start on. If 0, 1MB is assumed
* @size: Frame-buffer size, in bytes
- * @base: Base address of frame buffer, 0 if not yet known
- * @copy_base: Base address of a hardware copy of the frame buffer. See
- * CONFIG_VIDEO_COPY.
+ * @base: Base address of frame buffer, 0 if not yet known. If CONFIG_VIDEO_COPY
+ * is enabled, this is the software copy, so writes to this will not be
+ * visible until vidconsole_sync_copy() is called. If CONFIG_VIDEO_COPY is
+ * disabled, this is the hardware framebuffer.
+ * @copy_base: Base address of a hardware copy of the frame buffer. If
+ * CONFIG_VIDEO_COPY is disabled, this is not used.
* @copy_size: Size of copy framebuffer, used if @size is 0
* @hide_logo: Hide the logo (used for testing)
*/
@@ -58,7 +61,7 @@
* Convert enum video_log2_bpp to bytes and bits. Note we omit the outer
* brackets to allow multiplication by fractional pixels.
*/
-#define VNBYTES(bpix) (1 << (bpix)) / 8
+#define VNBYTES(bpix) ((1 << (bpix)) / 8)
#define VNBITS(bpix) (1 << (bpix))
diff --git a/include/video_console.h b/include/video_console.h
index 2694e44..bde67fa 100644
--- a/include/video_console.h
+++ b/include/video_console.h
@@ -8,6 +8,7 @@
#include <video.h>
+struct abuf;
struct video_priv;
#define VID_FRAC_DIV 256
@@ -15,6 +16,11 @@
#define VID_TO_PIXEL(x) ((x) / VID_FRAC_DIV)
#define VID_TO_POS(x) ((x) * VID_FRAC_DIV)
+enum {
+ /* cursor width in pixels */
+ VIDCONSOLE_CURSOR_WIDTH = 2,
+};
+
/**
* struct vidconsole_priv - uclass-private data about a console device
*
@@ -224,6 +230,60 @@
*/
int (*measure)(struct udevice *dev, const char *name, uint size,
const char *text, struct vidconsole_bbox *bbox);
+
+ /**
+ * nominal() - Measure the expected width of a line of text
+ *
+ * Uses an average font width and nominal height
+ *
+ * @dev: Console device to use
+ * @name: Font name, NULL for default
+ * @size: Font size, ignored if @name is NULL
+ * @num_chars: Number of characters to use
+ * @bbox: Returns nounding box of @num_chars characters
+ * Returns: 0 if OK, -ve on error
+ */
+ int (*nominal)(struct udevice *dev, const char *name, uint size,
+ uint num_chars, struct vidconsole_bbox *bbox);
+
+ /**
+ * entry_save() - Save any text-entry information for later use
+ *
+ * Saves text-entry context such as a list of positions for each
+ * character in the string.
+ *
+ * @dev: Console device to use
+ * @buf: Buffer to hold saved data
+ * Return: 0 if OK, -ENOMEM if out of memory
+ */
+ int (*entry_save)(struct udevice *dev, struct abuf *buf);
+
+ /**
+ * entry_restore() - Restore text-entry information for current use
+ *
+ * Restores text-entry context such as a list of positions for each
+ * character in the string.
+ *
+ * @dev: Console device to use
+ * @buf: Buffer containing data to restore
+ * Return: 0 if OK, -ve on error
+ */
+ int (*entry_restore)(struct udevice *dev, struct abuf *buf);
+
+ /**
+ * set_cursor_visible() - Show or hide the cursor
+ *
+ * Shows or hides a cursor at the current position
+ *
+ * @dev: Console device to use
+ * @visible: true to show the cursor, false to hide it
+ * @x: X position in pixels
+ * @y: Y position in pixels
+ * @index: Character position (0 = at start)
+ * Return: 0 if OK, -ve on error
+ */
+ int (*set_cursor_visible)(struct udevice *dev, bool visible,
+ uint x, uint y, uint index);
};
/* Get a pointer to the driver operations for a video console device */
@@ -264,6 +324,60 @@
const char *text, struct vidconsole_bbox *bbox);
/**
+ * vidconsole_nominal() - Measure the expected width of a line of text
+ *
+ * Uses an average font width and nominal height
+ *
+ * @dev: Console device to use
+ * @name: Font name, NULL for default
+ * @size: Font size, ignored if @name is NULL
+ * @num_chars: Number of characters to use
+ * @bbox: Returns nounding box of @num_chars characters
+ * Returns: 0 if OK, -ve on error
+ */
+int vidconsole_nominal(struct udevice *dev, const char *name, uint size,
+ uint num_chars, struct vidconsole_bbox *bbox);
+
+/**
+ * vidconsole_entry_save() - Save any text-entry information for later use
+ *
+ * Saves text-entry context such as a list of positions for each
+ * character in the string.
+ *
+ * @dev: Console device to use
+ * @buf: Buffer to hold saved data
+ * Return: 0 if OK, -ENOMEM if out of memory
+ */
+int vidconsole_entry_save(struct udevice *dev, struct abuf *buf);
+
+/**
+ * entry_restore() - Restore text-entry information for current use
+ *
+ * Restores text-entry context such as a list of positions for each
+ * character in the string.
+ *
+ * @dev: Console device to use
+ * @buf: Buffer containing data to restore
+ * Return: 0 if OK, -ve on error
+ */
+int vidconsole_entry_restore(struct udevice *dev, struct abuf *buf);
+
+/**
+ * vidconsole_set_cursor_visible() - Show or hide the cursor
+ *
+ * Shows or hides a cursor at the current position
+ *
+ * @dev: Console device to use
+ * @visible: true to show the cursor, false to hide it
+ * @x: X position in pixels
+ * @y: Y position in pixels
+ * @index: Character position (0 = at start)
+ * Return: 0 if OK, -ve on error
+ */
+int vidconsole_set_cursor_visible(struct udevice *dev, bool visible,
+ uint x, uint y, uint index);
+
+/**
* vidconsole_push_colour() - Temporarily change the font colour
*
* @dev: Device to adjust
@@ -321,6 +435,15 @@
int vidconsole_set_row(struct udevice *dev, uint row, int clr);
/**
+ * vidconsole_entry_start() - Set the start position of a vidconsole line
+ *
+ * Marks the current cursor position as the start of a line
+ *
+ * @dev: Device to adjust
+ */
+int vidconsole_entry_start(struct udevice *dev);
+
+/**
* vidconsole_put_char() - Output a character to the current console position
*
* Outputs a character to the console and advances the cursor. This function
diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h
index 18a87d2..73198a6 100644
--- a/include/zynqmp_firmware.h
+++ b/include/zynqmp_firmware.h
@@ -456,6 +456,7 @@
int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
int zynqmp_mmio_read(const u32 address, u32 *value);
int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
+int zynqmp_pm_feature(const u32 api_id);
/* Type of Config Object */
#define PM_CONFIG_OBJECT_TYPE_BASE 0x1U
@@ -492,6 +493,8 @@
/* PM API versions */
#define PM_API_VERSION_2 2
+#define PM_PINCTRL_PARAM_SET_VERSION 2
+
struct zynqmp_ipi_msg {
size_t len;
u32 *buf;
diff --git a/lib/Kconfig b/lib/Kconfig
index c555bc5..31cea98 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -289,6 +289,14 @@
not necessarily include generation of tables
(see GENERATE_ACPI_TABLE), but allows for tables to be located.
+config SPL_ACPI
+ bool "Enable support for ACPI libraries in SPL"
+ depends on SPL && SUPPORT_ACPI
+ help
+ Provides library functions for dealing with ACPI tables in SPL. This
+ does not necessarily include generation of tables
+ (see GENERATE_ACPI_TABLE), but allows for tables to be located.
+
config GENERATE_ACPI_TABLE
bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
depends on ACPI
@@ -423,6 +431,10 @@
bool "Trusted Platform Module (TPM) Support"
depends on DM
imply DM_RNG
+ select SHA1
+ select SHA256
+ select SHA384
+ select SHA512
help
This enables support for TPMs which can be used to provide security
features for your board. The TPM can be connected via LPC or I2C
@@ -693,6 +705,12 @@
checksum with feedback to produce an 8-bit result. The code is small
and it does not require a lookup table (unlike CRC32).
+config SPL_CRC16
+ bool "Support CRC16 in SPL"
+ depends on SPL
+ help
+ Enables CRC16 support in SPL. This is not normally required.
+
config CRC32
def_bool y
help
@@ -876,7 +894,7 @@
config OF_LIBFDT_ASSUME_MASK
hex "Mask of conditions to assume for libfdt"
depends on OF_LIBFDT || FIT
- default 0
+ default 0x0
help
Use this to change the assumptions made by libfdt about the
device tree it is working with. A value of 0 means that no assumptions
@@ -967,15 +985,6 @@
0xff means all assumptions are made and any invalid data may cause
unsafe execution. See FDT_ASSUME_PERFECT, etc. in libfdt_internal.h
-config FDT_FIXUP_PARTITIONS
- bool "overwrite MTD partitions in DTS through defined in 'mtdparts'"
- depends on OF_LIBFDT
- depends on CMD_MTDPARTS
- help
- Allow overwriting defined partitions in the device tree blob
- using partition info defined in the 'mtdparts' environment
- variable.
-
menu "System tables"
depends on (!EFI && !SYS_COREBOOT) || (ARM && EFI_LOADER)
@@ -990,8 +999,8 @@
config GENERATE_SMBIOS_TABLE
bool "Generate an SMBIOS (System Management BIOS) table"
+ depends on SMBIOS
default y
- depends on X86 || EFI_LOADER
help
The System Management BIOS (SMBIOS) specification addresses how
motherboard and system vendors present management information about
@@ -1000,9 +1009,11 @@
Check http://www.dmtf.org/standards/smbios for details.
- See also SMBIOS_SYSINFO which allows SMBIOS values to be provided in
+ See also SYSINFO_SMBIOS which allows SMBIOS values to be provided in
the devicetree.
+endmenu
+
config LIB_RATIONAL
bool "enable continued fraction calculation routines"
@@ -1010,8 +1021,6 @@
bool "enable continued fraction calculation routines for SPL"
depends on SPL
-endmenu
-
config ASN1_COMPILER
bool
help
@@ -1060,6 +1069,20 @@
unambiguous persistent name (https://en.wikipedia.org/wiki/Object_identifier).
Enable fast lookup object identifier registry in the SPL.
+config SMBIOS
+ bool "SMBIOS support"
+ depends on X86 || EFI_LOADER
+ default y
+ select LAST_STAGE_INIT
+ help
+ Indicates that this platform can support System Management BIOS
+ (SMBIOS) tables. These provide various pieces of information about
+ the board, such as the manufacturer and the model name.
+
+ See GENERATE_SMBIOS_TABLE which controls whether U-Boot actually
+ creates these tables, rather than them coming from a previous firmware
+ stage.
+
config SMBIOS_PARSER
bool "SMBIOS parser"
help
@@ -1132,8 +1155,4 @@
endmenu
-menu "FWU Multi Bank Updates"
-
source lib/fwu_updates/Kconfig
-
-endmenu
diff --git a/lib/Makefile b/lib/Makefile
index 7fddbfbb..134b439 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -44,6 +44,7 @@
obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += smbios.o
obj-$(CONFIG_SMBIOS_PARSER) += smbios-parser.o
obj-$(CONFIG_IMAGE_SPARSE) += image-sparse.o
+obj-y += initcall.o
obj-y += ldiv.o
obj-$(CONFIG_XXHASH) += xxhash.o
obj-y += net_utils.o
@@ -63,6 +64,7 @@
endif
obj-$(CONFIG_$(SPL_TPL_)CRC8) += crc8.o
+obj-$(CONFIG_$(SPL_TPL_)CRC16) += crc16.o
obj-y += crypto/
diff --git a/lib/abuf.c b/lib/abuf.c
index bd27046..ce2cff5 100644
--- a/lib/abuf.c
+++ b/lib/abuf.c
@@ -82,6 +82,11 @@
}
}
+bool abuf_realloc_inc(struct abuf *abuf, size_t inc)
+{
+ return abuf_realloc(abuf, abuf->size + inc);
+}
+
void *abuf_uninit_move(struct abuf *abuf, size_t *sizep)
{
void *ptr;
diff --git a/lib/addr_map.c b/lib/addr_map.c
index 9b3e0a5..86e932e 100644
--- a/lib/addr_map.c
+++ b/lib/addr_map.c
@@ -59,7 +59,7 @@
void addrmap_set_entry(unsigned long vaddr, phys_addr_t paddr,
phys_size_t size, int idx)
{
- if (idx > CONFIG_SYS_NUM_ADDR_MAP)
+ if (idx >= CONFIG_SYS_NUM_ADDR_MAP)
return;
address_map[idx].vaddr = vaddr;
diff --git a/lib/asm-offsets.c b/lib/asm-offsets.c
index 0808cd4..216d971 100644
--- a/lib/asm-offsets.c
+++ b/lib/asm-offsets.c
@@ -32,7 +32,7 @@
DEFINE(GD_FLAGS, offsetof(struct global_data, flags));
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
DEFINE(GD_MALLOC_BASE, offsetof(struct global_data, malloc_base));
#endif
diff --git a/lib/asn1_decoder.c b/lib/asn1_decoder.c
index bcb0390..1191fc3 100644
--- a/lib/asn1_decoder.c
+++ b/lib/asn1_decoder.c
@@ -8,6 +8,7 @@
#ifdef __UBOOT__
#include <log.h>
#include <linux/compat.h>
+#include <linux/printk.h>
#else
#include <linux/export.h>
#endif
diff --git a/lib/bch.c b/lib/bch.c
index de66b1a..72b4fdc 100644
--- a/lib/bch.c
+++ b/lib/bch.c
@@ -61,6 +61,7 @@
#include <dm/devres.h>
#include <linux/bitops.h>
+#include <linux/printk.h>
#else
#include <errno.h>
#if defined(__FreeBSD__)
diff --git a/lib/charset.c b/lib/charset.c
index b184275..5e4c4f9 100644
--- a/lib/charset.c
+++ b/lib/charset.c
@@ -444,14 +444,14 @@
size_t u16_strlcat(u16 *dest, const u16 *src, size_t count)
{
- size_t destlen = u16_strlen(dest);
+ size_t destlen = u16_strnlen(dest, count);
size_t srclen = u16_strlen(src);
- size_t ret = destlen + srclen + 1;
+ size_t ret = destlen + srclen;
if (destlen >= count)
return ret;
- if (ret > count)
- srclen -= ret - count;
+ if (ret >= count)
+ srclen -= (ret - count + 1);
memcpy(&dest[destlen], src, 2 * srclen);
dest[destlen + srclen] = 0x0000;
diff --git a/lib/crc32.c b/lib/crc32.c
index aa94d70..f6fad8c 100644
--- a/lib/crc32.c
+++ b/lib/crc32.c
@@ -10,7 +10,6 @@
#ifdef USE_HOSTCC
#include <arpa/inet.h>
-#include <u-boot/crc.h>
#else
#include <common.h>
#include <efi_loader.h>
diff --git a/lib/crypto/asymmetric_type.c b/lib/crypto/asymmetric_type.c
index 1d0532d..24c2d15 100644
--- a/lib/crypto/asymmetric_type.c
+++ b/lib/crypto/asymmetric_type.c
@@ -18,6 +18,7 @@
#include <linux/compat.h>
#include <linux/ctype.h>
#include <linux/err.h>
+#include <linux/printk.h>
#include <linux/string.h>
#else
#include <linux/seq_file.h>
diff --git a/lib/crypto/pkcs7_parser.c b/lib/crypto/pkcs7_parser.c
index 0b85fe8..d5efa82 100644
--- a/lib/crypto/pkcs7_parser.c
+++ b/lib/crypto/pkcs7_parser.c
@@ -11,6 +11,7 @@
#include <dm/devres.h>
#include <linux/bitops.h>
#include <linux/compat.h>
+#include <linux/printk.h>
#endif
#include <linux/kernel.h>
#ifndef __UBOOT__
diff --git a/lib/crypto/pkcs7_verify.c b/lib/crypto/pkcs7_verify.c
index b832f01..9d7b9f6 100644
--- a/lib/crypto/pkcs7_verify.c
+++ b/lib/crypto/pkcs7_verify.c
@@ -15,6 +15,7 @@
#include <linux/bitops.h>
#include <linux/compat.h>
#include <linux/asn1.h>
+#include <linux/printk.h>
#include <u-boot/hash-checksum.h>
#include <crypto/public_key.h>
#include <crypto/pkcs7_parser.h>
diff --git a/lib/crypto/public_key.c b/lib/crypto/public_key.c
index 3671ed1..6efe951 100644
--- a/lib/crypto/public_key.c
+++ b/lib/crypto/public_key.c
@@ -13,6 +13,7 @@
#include <linux/bug.h>
#include <linux/compat.h>
#include <linux/err.h>
+#include <linux/printk.h>
#else
#include <linux/module.h>
#include <linux/export.h>
diff --git a/lib/crypto/rsa_helper.c b/lib/crypto/rsa_helper.c
index cc0c0d6..c941d40 100644
--- a/lib/crypto/rsa_helper.c
+++ b/lib/crypto/rsa_helper.c
@@ -15,6 +15,7 @@
#include <linux/fips.h>
#endif
#include <crypto/internal/rsa.h>
+#include <linux/printk.h>
#include "rsapubkey.asn1.h"
#ifndef __UBOOT__
#include "rsaprivkey.asn1.h"
diff --git a/lib/crypto/x509_cert_parser.c b/lib/crypto/x509_cert_parser.c
index eb24349..a0f0689 100644
--- a/lib/crypto/x509_cert_parser.c
+++ b/lib/crypto/x509_cert_parser.c
@@ -16,6 +16,7 @@
#include <linux/err.h>
#include <linux/oid_registry.h>
#ifdef __UBOOT__
+#include <linux/printk.h>
#include <linux/string.h>
#endif
#include <crypto/public_key.h>
diff --git a/lib/crypto/x509_public_key.c b/lib/crypto/x509_public_key.c
index 5c0e2b6..3007123 100644
--- a/lib/crypto/x509_public_key.c
+++ b/lib/crypto/x509_public_key.c
@@ -13,6 +13,7 @@
#include <linux/compat.h>
#include <linux/err.h>
#include <linux/errno.h>
+#include <linux/printk.h>
#else
#include <linux/module.h>
#endif
diff --git a/lib/efi/efi_app.c b/lib/efi/efi_app.c
index 2209410..c5eb816 100644
--- a/lib/efi/efi_app.c
+++ b/lib/efi/efi_app.c
@@ -12,18 +12,21 @@
#include <cpu_func.h>
#include <debug_uart.h>
#include <dm.h>
+#include <efi.h>
+#include <efi_api.h>
#include <errno.h>
#include <init.h>
#include <malloc.h>
+#include <sysreset.h>
+#include <uuid.h>
#include <asm/global_data.h>
#include <linux/err.h>
#include <linux/types.h>
-#include <efi.h>
-#include <efi_api.h>
-#include <sysreset.h>
+#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dm/root.h>
+#include <mapmem.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -320,6 +323,19 @@
return 0;
}
+static void scan_tables(struct efi_system_table *sys_table)
+{
+ efi_guid_t acpi = EFI_ACPI_TABLE_GUID;
+ uint i;
+
+ for (i = 0; i < sys_table->nr_tables; i++) {
+ struct efi_configuration_table *tab = &sys_table->tables[i];
+
+ if (!memcmp(&tab->guid, &acpi, sizeof(efi_guid_t)))
+ gd_set_acpi_start(map_to_sysmem(tab->table));
+ }
+}
+
/**
* efi_main() - Start an EFI image
*
@@ -354,6 +370,8 @@
return ret;
}
+ scan_tables(priv->sys_table);
+
/*
* We could store the EFI memory map here, but it changes all the time,
* so this is only useful for debugging.
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 9989e3f..2e39354 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -133,18 +133,20 @@
config EFI_VAR_BUF_SIZE
int "Memory size of the UEFI variable store"
- default 16384 if EFI_MM_COMM_TEE
- default 65536
+ default 131072
range 4096 2147483647
help
This defines the size in bytes of the memory area reserved for keeping
UEFI variables.
- When using StandAloneMM (CONFIG_EFI_MM_COMM_TEE=y) this value should
- match the value of PcdFlashNvStorageVariableSize used to compile the
- StandAloneMM module.
+ When using StandAloneMM (CONFIG_EFI_MM_COMM_TEE=y) is used the
+ available size for storing variables is defined in
+ PcdFlashNvStorageVariableSize.
+ That value is probed at runtime from U-Boot. In that case,
+ EFI_VAR_BUF_SIZE represents the memory U-Boot reserves to present
+ runtime variables to the OS.
- Minimum 4096, default 65536, or 16384 when using StandAloneMM.
+ Minimum 4096, default 131072
config EFI_GET_TIME
bool "GetTime() runtime service"
@@ -272,6 +274,14 @@
Select the max capsule index value used for capsule report
variables. This value is used to create CapsuleMax variable.
+config EFI_CAPSULE_ESL_FILE
+ string "Path to the EFI Signature List File"
+ depends on EFI_CAPSULE_AUTHENTICATE
+ help
+ Provides the path to the EFI Signature List file which will
+ be embedded in the platform's device tree and used for
+ capsule authentication at the time of capsule update.
+
config EFI_DEVICE_PATH_TO_TEXT
bool "Device path to text protocol"
default y
@@ -371,8 +381,6 @@
bool "EFI_TCG2_PROTOCOL support"
default y
depends on TPM_V2
- # Sandbox TPM currently fails on GetCapabilities needed for TCG2
- depends on !SANDBOX
select SHA1
select SHA256
select SHA384
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index 1a8c8d7..d476df1 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -51,9 +51,7 @@
obj-y += efi_device_path.o
obj-$(CONFIG_EFI_DEVICE_PATH_TO_TEXT) += efi_device_path_to_text.o
obj-$(CONFIG_EFI_DEVICE_PATH_UTIL) += efi_device_path_utilities.o
-ifeq ($(CONFIG_GENERATE_ACPI_TABLE),)
obj-y += efi_dt_fixup.o
-endif
obj-y += efi_file.o
obj-$(CONFIG_EFI_LOADER_HII) += efi_hii.o
obj-y += efi_image_loader.o
@@ -78,8 +76,8 @@
obj-$(CONFIG_VIDEO) += efi_gop.o
obj-$(CONFIG_BLK) += efi_disk.o
obj-$(CONFIG_NETDEVICES) += efi_net.o
-obj-$(CONFIG_GENERATE_ACPI_TABLE) += efi_acpi.o
-obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += efi_smbios.o
+obj-$(CONFIG_ACPI) += efi_acpi.o
+obj-$(CONFIG_SMBIOS) += efi_smbios.o
obj-$(CONFIG_EFI_RNG_PROTOCOL) += efi_rng.o
obj-$(CONFIG_EFI_TCG2_PROTOCOL) += efi_tcg2.o
obj-$(CONFIG_EFI_RISCV_BOOT_PROTOCOL) += efi_riscv.o
diff --git a/lib/efi_loader/capsule_esl.dtsi.in b/lib/efi_loader/capsule_esl.dtsi.in
new file mode 100644
index 0000000..61a9f2b
--- /dev/null
+++ b/lib/efi_loader/capsule_esl.dtsi.in
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+/**
+ * Devicetree file with the public key EFI Signature List(ESL)
+ * node. This file is used to generate the dtsi file to be
+ * included into the DTB.
+*/
+/ {
+ signature {
+ capsule-key = /incbin/("ESL_BIN_FILE");
+ };
+};
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 0b7579c..fad0476 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -1339,7 +1339,7 @@
const efi_guid_t *protocol,
efi_handle_t child_handle)
{
- efi_uintn_t number_of_drivers, tmp;
+ efi_uintn_t number_of_drivers;
efi_handle_t *driver_handle_buffer;
efi_status_t r, ret;
@@ -1350,27 +1350,13 @@
if (!number_of_drivers)
return EFI_SUCCESS;
- tmp = number_of_drivers;
while (number_of_drivers) {
- ret = EFI_CALL(efi_disconnect_controller(
+ r = EFI_CALL(efi_disconnect_controller(
handle,
driver_handle_buffer[--number_of_drivers],
child_handle));
- if (ret != EFI_SUCCESS)
- goto reconnect;
- }
-
- free(driver_handle_buffer);
- return ret;
-
-reconnect:
- /* Reconnect all disconnected drivers */
- for (; number_of_drivers < tmp; number_of_drivers++) {
- r = EFI_CALL(efi_connect_controller(handle,
- &driver_handle_buffer[number_of_drivers],
- NULL, true));
if (r != EFI_SUCCESS)
- EFI_PRINT("Failed to reconnect controller\n");
+ ret = r;
}
free(driver_handle_buffer);
@@ -1409,6 +1395,13 @@
r = efi_disconnect_all_drivers(handle, protocol, NULL);
if (r != EFI_SUCCESS) {
r = EFI_ACCESS_DENIED;
+ /*
+ * This will reconnect all controllers of the handle, even ones
+ * that were not connected before. This can be done better
+ * but we are following the EDKII implementation on this for
+ * now
+ */
+ EFI_CALL(efi_connect_controller(handle, NULL, NULL, true));
goto out;
}
/* Close protocol */
diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c
index 778b693..a09db31 100644
--- a/lib/efi_loader/efi_gop.c
+++ b/lib/efi_loader/efi_gop.c
@@ -10,6 +10,7 @@
#include <efi_loader.h>
#include <log.h>
#include <malloc.h>
+#include <mapmem.h>
#include <video.h>
#include <asm/global_data.h>
@@ -467,10 +468,10 @@
struct efi_gop_obj *gopobj;
u32 bpix, format, col, row;
u64 fb_base, fb_size;
- void *fb;
efi_status_t ret;
struct udevice *vdev;
struct video_priv *priv;
+ struct video_uc_plat *plat;
/* We only support a single video output device for now */
if (uclass_first_device_err(UCLASS_VIDEO, &vdev)) {
@@ -483,9 +484,10 @@
format = priv->format;
col = video_get_xsize(vdev);
row = video_get_ysize(vdev);
- fb_base = (uintptr_t)priv->fb;
- fb_size = priv->fb_size;
- fb = priv->fb;
+
+ plat = dev_get_uclass_plat(vdev);
+ fb_base = IS_ENABLED(CONFIG_VIDEO_COPY) ? plat->copy_base : plat->base;
+ fb_size = plat->size;
switch (bpix) {
case VIDEO_BPP16:
@@ -547,7 +549,7 @@
}
gopobj->info.pixels_per_scanline = col;
gopobj->bpix = bpix;
- gopobj->fb = fb;
+ gopobj->fb = map_sysmem(fb_base, fb_size);
return EFI_SUCCESS;
}
diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c
index 58d4e13..e6de685 100644
--- a/lib/efi_loader/efi_setup.c
+++ b/lib/efi_loader/efi_setup.c
@@ -321,16 +321,16 @@
if (ret != EFI_SUCCESS)
goto out;
#endif
-#ifdef CONFIG_GENERATE_ACPI_TABLE
- ret = efi_acpi_register();
- if (ret != EFI_SUCCESS)
- goto out;
-#endif
-#ifdef CONFIG_GENERATE_SMBIOS_TABLE
- ret = efi_smbios_register();
- if (ret != EFI_SUCCESS)
- goto out;
-#endif
+ if (IS_ENABLED(CONFIG_ACPI)) {
+ ret = efi_acpi_register();
+ if (ret != EFI_SUCCESS)
+ goto out;
+ }
+ if (IS_ENABLED(CONFIG_SMBIOS)) {
+ ret = efi_smbios_register();
+ if (ret != EFI_SUCCESS)
+ goto out;
+ }
ret = efi_watchdog_register();
if (ret != EFI_SUCCESS)
goto out;
diff --git a/lib/efi_loader/efi_smbios.c b/lib/efi_loader/efi_smbios.c
index 306c0bc..0fbf51b 100644
--- a/lib/efi_loader/efi_smbios.c
+++ b/lib/efi_loader/efi_smbios.c
@@ -10,8 +10,14 @@
#include <common.h>
#include <efi_loader.h>
#include <log.h>
+#include <malloc.h>
#include <mapmem.h>
#include <smbios.h>
+#include <linux/sizes.h>
+
+enum {
+ TABLE_SIZE = SZ_4K,
+};
/*
* Install the SMBIOS table as a configuration table.
@@ -20,36 +26,52 @@
*/
efi_status_t efi_smbios_register(void)
{
- /* Map within the low 32 bits, to allow for 32bit SMBIOS tables */
- u64 dmi_addr = U32_MAX;
+ ulong addr;
efi_status_t ret;
- void *dmi;
- /* Reserve 4kiB page for SMBIOS */
- ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
- EFI_RUNTIME_SERVICES_DATA, 1, &dmi_addr);
-
- if (ret != EFI_SUCCESS) {
- /* Could not find space in lowmem, use highmem instead */
- ret = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES,
- EFI_RUNTIME_SERVICES_DATA, 1,
- &dmi_addr);
-
- if (ret != EFI_SUCCESS)
- return ret;
+ addr = gd->arch.smbios_start;
+ if (!addr) {
+ log_err("No SMBIOS tables to install\n");
+ return EFI_NOT_FOUND;
}
- /*
- * Generate SMBIOS tables - we know that efi_allocate_pages() returns
- * a 4k-aligned address, so it is safe to assume that
- * write_smbios_table() will write the table at that address.
- */
- assert(!(dmi_addr & 0xf));
- dmi = (void *)(uintptr_t)dmi_addr;
- if (write_smbios_table(map_to_sysmem(dmi)))
- /* Install SMBIOS information as configuration table */
- return efi_install_configuration_table(&smbios_guid, dmi);
- efi_free_pages(dmi_addr, 1);
- log_err("Cannot create SMBIOS table\n");
- return EFI_SUCCESS;
+ /* Mark space used for tables */
+ ret = efi_add_memory_map(addr, TABLE_SIZE, EFI_RUNTIME_SERVICES_DATA);
+ if (ret)
+ return ret;
+
+ log_debug("EFI using SMBIOS tables at %lx\n", addr);
+
+ /* Install SMBIOS information as configuration table */
+ return efi_install_configuration_table(&smbios_guid,
+ map_sysmem(addr, 0));
}
+
+static int install_smbios_table(void)
+{
+ u64 addr;
+ efi_status_t ret;
+
+ if (!IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE) || IS_ENABLED(CONFIG_X86))
+ return 0;
+
+ addr = SZ_4G;
+ ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
+ EFI_RUNTIME_SERVICES_DATA,
+ efi_size_in_pages(TABLE_SIZE), &addr);
+ if (ret != EFI_SUCCESS)
+ return log_msg_ret("mem", -ENOMEM);
+
+ addr = map_to_sysmem((void *)(uintptr_t)addr);
+ if (!write_smbios_table(addr)) {
+ log_err("Failed to write SMBIOS table\n");
+ return log_msg_ret("smbios", -EINVAL);
+ }
+
+ /* Make a note of where we put it */
+ log_debug("SMBIOS tables written to %llx\n", addr);
+ gd->arch.smbios_start = addr;
+
+ return 0;
+}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, install_smbios_table);
diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c
index 7b7926a..463ea4c 100644
--- a/lib/efi_loader/efi_tcg2.c
+++ b/lib/efi_loader/efi_tcg2.c
@@ -66,35 +66,6 @@
static const efi_guid_t efi_guid_tcg2_protocol = EFI_TCG2_PROTOCOL_GUID;
static const efi_guid_t efi_guid_final_events = EFI_TCG2_FINAL_EVENTS_TABLE_GUID;
-struct digest_info {
- u16 hash_alg;
- u32 hash_mask;
- u16 hash_len;
-};
-
-static const struct digest_info hash_algo_list[] = {
- {
- TPM2_ALG_SHA1,
- EFI_TCG2_BOOT_HASH_ALG_SHA1,
- TPM2_SHA1_DIGEST_SIZE,
- },
- {
- TPM2_ALG_SHA256,
- EFI_TCG2_BOOT_HASH_ALG_SHA256,
- TPM2_SHA256_DIGEST_SIZE,
- },
- {
- TPM2_ALG_SHA384,
- EFI_TCG2_BOOT_HASH_ALG_SHA384,
- TPM2_SHA384_DIGEST_SIZE,
- },
- {
- TPM2_ALG_SHA512,
- EFI_TCG2_BOOT_HASH_ALG_SHA512,
- TPM2_SHA512_DIGEST_SIZE,
- },
-};
-
struct variable_info {
const u16 *name;
bool accept_empty;
@@ -113,46 +84,6 @@
{u"AuditMode", false, 1},
};
-#define MAX_HASH_COUNT ARRAY_SIZE(hash_algo_list)
-
-/**
- * alg_to_mask - Get a TCG hash mask for algorithms
- *
- * @hash_alg: TCG defined algorithm
- *
- * @Return: TCG hashing algorithm bitmaps, 0 if the algorithm is not supported
- */
-static u32 alg_to_mask(u16 hash_alg)
-{
- size_t i;
-
- for (i = 0; i < MAX_HASH_COUNT; i++) {
- if (hash_algo_list[i].hash_alg == hash_alg)
- return hash_algo_list[i].hash_mask;
- }
-
- return 0;
-}
-
-/**
- * alg_to_len - Get a TCG hash len for algorithms
- *
- * @hash_alg: TCG defined algorithm
- *
- * @Return: len of chosen algorithm, 0 if the algorithm is not supported
- */
-static u16 alg_to_len(u16 hash_alg)
-{
- size_t i;
-
- for (i = 0; i < MAX_HASH_COUNT; i++) {
- if (hash_algo_list[i].hash_alg == hash_alg)
- return hash_algo_list[i].hash_len;
- }
-
- return 0;
-}
-
static bool is_tcg2_protocol_installed(void)
{
struct efi_handler *handler;
@@ -162,145 +93,6 @@
return ret == EFI_SUCCESS;
}
-static u32 tcg_event_final_size(struct tpml_digest_values *digest_list)
-{
- u32 len;
- size_t i;
-
- len = offsetof(struct tcg_pcr_event2, digests);
- len += offsetof(struct tpml_digest_values, digests);
- for (i = 0; i < digest_list->count; i++) {
- u16 hash_alg = digest_list->digests[i].hash_alg;
-
- len += offsetof(struct tpmt_ha, digest);
- len += alg_to_len(hash_alg);
- }
- len += sizeof(u32); /* tcg_pcr_event2 event_size*/
-
- return len;
-}
-
-/* tcg2_pcr_extend - Extend PCRs for a TPM2 device for a given tpml_digest_values
- *
- * @dev: device
- * @digest_list: list of digest algorithms to extend
- *
- * @Return: status code
- */
-static efi_status_t tcg2_pcr_extend(struct udevice *dev, u32 pcr_index,
- struct tpml_digest_values *digest_list)
-{
- u32 rc;
- size_t i;
-
- for (i = 0; i < digest_list->count; i++) {
- u32 alg = digest_list->digests[i].hash_alg;
-
- rc = tpm2_pcr_extend(dev, pcr_index, alg,
- (u8 *)&digest_list->digests[i].digest,
- alg_to_len(alg));
- if (rc) {
- EFI_PRINT("Failed to extend PCR\n");
- return EFI_DEVICE_ERROR;
- }
- }
-
- return EFI_SUCCESS;
-}
-
-/* tcg2_pcr_read - Read PCRs for a TPM2 device for a given tpml_digest_values
- *
- * @dev: device
- * @pcr_index: PCR index
- * @digest_list: list of digest algorithms to extend
- *
- * @Return: status code
- */
-static efi_status_t tcg2_pcr_read(struct udevice *dev, u32 pcr_index,
- struct tpml_digest_values *digest_list)
-{
- struct tpm_chip_priv *priv;
- unsigned int updates, pcr_select_min;
- u32 rc;
- size_t i;
-
- priv = dev_get_uclass_priv(dev);
- if (!priv)
- return EFI_DEVICE_ERROR;
-
- pcr_select_min = priv->pcr_select_min;
-
- for (i = 0; i < digest_list->count; i++) {
- u16 hash_alg = digest_list->digests[i].hash_alg;
- u8 *digest = (u8 *)&digest_list->digests[i].digest;
-
- rc = tpm2_pcr_read(dev, pcr_index, pcr_select_min,
- hash_alg, digest, alg_to_len(hash_alg),
- &updates);
- if (rc) {
- EFI_PRINT("Failed to read PCR\n");
- return EFI_DEVICE_ERROR;
- }
- }
-
- return EFI_SUCCESS;
-}
-
-/* put_event - Append an agile event to an eventlog
- *
- * @pcr_index: PCR index
- * @event_type: type of event added
- * @digest_list: list of digest algorithms to add
- * @size: size of event
- * @event: event to add
- * @log: log buffer to append the event
- *
- */
-static void put_event(u32 pcr_index, u32 event_type,
- struct tpml_digest_values *digest_list, u32 size,
- u8 event[], void *log)
-{
- size_t pos;
- size_t i;
- u32 event_size;
-
- /*
- * size refers to the length of event[] only, we need to check against
- * the final tcg_pcr_event2 size
- */
- event_size = size + tcg_event_final_size(digest_list);
-
- put_unaligned_le32(pcr_index, log);
- pos = offsetof(struct tcg_pcr_event2, event_type);
- put_unaligned_le32(event_type, (void *)((uintptr_t)log + pos));
- pos = offsetof(struct tcg_pcr_event2, digests); /* count */
- put_unaligned_le32(digest_list->count, (void *)((uintptr_t)log + pos));
-
- pos += offsetof(struct tpml_digest_values, digests);
- for (i = 0; i < digest_list->count; i++) {
- u16 hash_alg = digest_list->digests[i].hash_alg;
- u8 *digest = (u8 *)&digest_list->digests[i].digest;
-
- put_unaligned_le16(hash_alg, (void *)((uintptr_t)log + pos));
- pos += offsetof(struct tpmt_ha, digest);
- memcpy((void *)((uintptr_t)log + pos), digest, alg_to_len(hash_alg));
- pos += alg_to_len(hash_alg);
- }
-
- put_unaligned_le32(size, (void *)((uintptr_t)log + pos));
- pos += sizeof(u32); /* tcg_pcr_event2 event_size*/
- memcpy((void *)((uintptr_t)log + pos), event, size);
- pos += size;
-
- /*
- * make sure the calculated buffer is what we checked against
- * This check should never fail. It checks the code above is
- * calculating the right length for the event we are adding
- */
- if (pos != event_size)
- log_err("Appending to the EventLog failed\n");
-}
-
/* tcg2_agile_log_append - Append an agile event to an eventlog
*
* @pcr_index: PCR index
@@ -317,7 +109,7 @@
u32 size, u8 event[])
{
void *log = (void *)((uintptr_t)event_log.buffer + event_log.pos);
- u32 event_size = size + tcg_event_final_size(digest_list);
+ u32 event_size = size + tcg2_event_get_size(digest_list);
struct efi_tcg2_final_events_table *final_event;
efi_status_t ret = EFI_SUCCESS;
@@ -328,7 +120,7 @@
event_log.truncated = true;
return EFI_VOLUME_FULL;
}
- put_event(pcr_index, event_type, digest_list, size, event, log);
+ tcg2_log_append(pcr_index, event_type, digest_list, size, event, log);
event_log.pos += event_size;
event_log.last_event_size = event_size;
}
@@ -341,7 +133,7 @@
return EFI_VOLUME_FULL;
log = (void *)((uintptr_t)event_log.final_buffer + event_log.final_pos);
- put_event(pcr_index, event_type, digest_list, size, event, log);
+ tcg2_log_append(pcr_index, event_type, digest_list, size, event, log);
final_event = event_log.final_buffer;
final_event->number_of_events++;
@@ -351,66 +143,6 @@
}
/**
- * platform_get_tpm_device() - retrieve TPM device
- *
- * This function retrieves the udevice implementing a TPM
- *
- * This function may be overridden if special initialization is needed.
- *
- * @dev: udevice
- * Return: status code
- */
-__weak efi_status_t platform_get_tpm2_device(struct udevice **dev)
-{
- for_each_tpm_device(*dev) {
- /* Only support TPMv2 devices */
- if (tpm_get_version(*dev) == TPM_V2)
- return EFI_SUCCESS;
- }
-
- return EFI_NOT_FOUND;
-}
-
-/**
- * platform_get_eventlog() - retrieve the eventlog address and size
- *
- * This function retrieves the eventlog address and size if the underlying
- * firmware has done some measurements and passed them.
- *
- * This function may be overridden based on platform specific method of
- * passing the eventlog address and size.
- *
- * @dev: udevice
- * @addr: eventlog address
- * @sz: eventlog size
- * Return: status code
- */
-__weak efi_status_t platform_get_eventlog(struct udevice *dev, u64 *addr,
- u32 *sz)
-{
- const u64 *basep;
- const u32 *sizep;
-
- basep = dev_read_prop(dev, "tpm_event_log_addr", NULL);
- if (!basep)
- return EFI_NOT_FOUND;
-
- *addr = be64_to_cpup((__force __be64 *)basep);
-
- sizep = dev_read_prop(dev, "tpm_event_log_size", NULL);
- if (!sizep)
- return EFI_NOT_FOUND;
-
- *sz = be32_to_cpup((__force __be32 *)sizep);
- if (*sz == 0) {
- log_debug("event log empty\n");
- return EFI_NOT_FOUND;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
* tpm2_get_max_command_size() - get the supported max command size
*
* @dev: TPM device
@@ -486,238 +218,6 @@
}
/**
- * tpm2_get_num_pcr() - get the number of PCRs
- *
- * @dev: TPM device
- * @manufacturer_id: output buffer for the number
- *
- * Return: 0 on success, -1 on error
- */
-static int tpm2_get_num_pcr(struct udevice *dev, u32 *num_pcr)
-{
- u8 response[TPM2_RESPONSE_BUFFER_SIZE];
- u32 ret;
-
- memset(response, 0, sizeof(response));
- ret = tpm2_get_capability(dev, TPM2_CAP_TPM_PROPERTIES,
- TPM2_PT_PCR_COUNT, response, 1);
- if (ret)
- return -1;
-
- *num_pcr = get_unaligned_be32(response + properties_offset);
- if (*num_pcr > TPM2_MAX_PCRS)
- return -1;
-
- return 0;
-}
-
-/**
- * is_active_pcr() - Check if a supported algorithm is active
- *
- * @dev: TPM device
- * @selection: struct of PCR information
- *
- * Return: true if PCR is active
- */
-static bool is_active_pcr(struct tpms_pcr_selection *selection)
-{
- int i;
- /*
- * check the pcr_select. If at least one of the PCRs supports the
- * algorithm add it on the active ones
- */
- for (i = 0; i < selection->size_of_select; i++) {
- if (selection->pcr_select[i])
- return true;
- }
-
- return false;
-}
-
-/**
- * tpm2_get_pcr_info() - get the supported, active PCRs and number of banks
- *
- * @dev: TPM device
- * @supported_pcr: bitmask with the algorithms supported
- * @active_pcr: bitmask with the active algorithms
- * @pcr_banks: number of PCR banks
- *
- * Return: 0 on success, -1 on error
- */
-static int tpm2_get_pcr_info(struct udevice *dev, u32 *supported_pcr,
- u32 *active_pcr, u32 *pcr_banks)
-{
- u8 response[TPM2_RESPONSE_BUFFER_SIZE];
- struct tpml_pcr_selection pcrs;
- u32 ret, num_pcr;
- size_t i;
- int tpm_ret;
-
- *supported_pcr = 0;
- *active_pcr = 0;
- *pcr_banks = 0;
- memset(response, 0, sizeof(response));
- ret = tpm2_get_capability(dev, TPM2_CAP_PCRS, 0, response, 1);
- if (ret)
- goto out;
-
- pcrs.count = get_unaligned_be32(response);
- /*
- * We only support 5 algorithms for now so check against that
- * instead of TPM2_NUM_PCR_BANKS
- */
- if (pcrs.count > MAX_HASH_COUNT || pcrs.count < 1)
- goto out;
-
- tpm_ret = tpm2_get_num_pcr(dev, &num_pcr);
- if (tpm_ret)
- goto out;
-
- for (i = 0; i < pcrs.count; i++) {
- /*
- * Definition of TPMS_PCR_SELECTION Structure
- * hash: u16
- * size_of_select: u8
- * pcr_select: u8 array
- *
- * The offsets depend on the number of the device PCRs
- * so we have to calculate them based on that
- */
- u32 hash_offset = offsetof(struct tpml_pcr_selection, selection) +
- i * offsetof(struct tpms_pcr_selection, pcr_select) +
- i * ((num_pcr + 7) / 8);
- u32 size_select_offset =
- hash_offset + offsetof(struct tpms_pcr_selection,
- size_of_select);
- u32 pcr_select_offset =
- hash_offset + offsetof(struct tpms_pcr_selection,
- pcr_select);
-
- pcrs.selection[i].hash =
- get_unaligned_be16(response + hash_offset);
- pcrs.selection[i].size_of_select =
- __get_unaligned_be(response + size_select_offset);
- if (pcrs.selection[i].size_of_select > TPM2_PCR_SELECT_MAX)
- goto out;
- /* copy the array of pcr_select */
- memcpy(pcrs.selection[i].pcr_select, response + pcr_select_offset,
- pcrs.selection[i].size_of_select);
- }
-
- for (i = 0; i < pcrs.count; i++) {
- u32 hash_mask = alg_to_mask(pcrs.selection[i].hash);
-
- if (hash_mask) {
- *supported_pcr |= hash_mask;
- if (is_active_pcr(&pcrs.selection[i]))
- *active_pcr |= hash_mask;
- } else {
- EFI_PRINT("Unknown algorithm %x\n", pcrs.selection[i].hash);
- }
- }
-
- *pcr_banks = pcrs.count;
-
- return 0;
-out:
- return -1;
-}
-
-/**
- * __get_active_pcr_banks() - returns the currently active PCR banks
- *
- * @active_pcr_banks: pointer for receiving the bitmap of currently
- * active PCR banks
- *
- * Return: status code
- */
-static efi_status_t __get_active_pcr_banks(u32 *active_pcr_banks)
-{
- struct udevice *dev;
- u32 active = 0, supported = 0, pcr_banks = 0;
- efi_status_t ret;
- int err;
-
- ret = platform_get_tpm2_device(&dev);
- if (ret != EFI_SUCCESS)
- goto out;
-
- err = tpm2_get_pcr_info(dev, &supported, &active, &pcr_banks);
- if (err) {
- ret = EFI_DEVICE_ERROR;
- goto out;
- }
-
- *active_pcr_banks = active;
-
-out:
- return ret;
-}
-
-/* tcg2_create_digest - create a list of digests of the supported PCR banks
- * for a given memory range
- *
- * @input: input memory
- * @length: length of buffer to calculate the digest
- * @digest_list: list of digests to fill in
- *
- * Return: status code
- */
-static efi_status_t tcg2_create_digest(const u8 *input, u32 length,
- struct tpml_digest_values *digest_list)
-{
- sha1_context ctx;
- sha256_context ctx_256;
- sha512_context ctx_512;
- u8 final[TPM2_SHA512_DIGEST_SIZE];
- efi_status_t ret;
- u32 active;
- size_t i;
-
- ret = __get_active_pcr_banks(&active);
- if (ret != EFI_SUCCESS)
- return ret;
-
- digest_list->count = 0;
- for (i = 0; i < MAX_HASH_COUNT; i++) {
- u16 hash_alg = hash_algo_list[i].hash_alg;
-
- if (!(active & alg_to_mask(hash_alg)))
- continue;
- switch (hash_alg) {
- case TPM2_ALG_SHA1:
- sha1_starts(&ctx);
- sha1_update(&ctx, input, length);
- sha1_finish(&ctx, final);
- break;
- case TPM2_ALG_SHA256:
- sha256_starts(&ctx_256);
- sha256_update(&ctx_256, input, length);
- sha256_finish(&ctx_256, final);
- break;
- case TPM2_ALG_SHA384:
- sha384_starts(&ctx_512);
- sha384_update(&ctx_512, input, length);
- sha384_finish(&ctx_512, final);
- break;
- case TPM2_ALG_SHA512:
- sha512_starts(&ctx_512);
- sha512_update(&ctx_512, input, length);
- sha512_finish(&ctx_512, final);
- break;
- default:
- continue;
- }
- digest_list->digests[digest_list->count].hash_alg = hash_alg;
- memcpy(&digest_list->digests[digest_list->count].digest, final,
- (u32)alg_to_len(hash_alg));
- digest_list->count++;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
* efi_tcg2_get_capability() - protocol capability information and state information
*
* @this: TCG2 protocol instance
@@ -758,7 +258,7 @@
capability->protocol_version.major = 1;
capability->protocol_version.minor = 1;
- efi_ret = platform_get_tpm2_device(&dev);
+ efi_ret = tcg2_platform_get_tpm2(&dev);
if (efi_ret != EFI_SUCCESS) {
capability->supported_event_logs = 0;
capability->hash_algorithm_bitmap = 0;
@@ -854,7 +354,7 @@
goto out;
}
- ret = platform_get_tpm2_device(&dev);
+ ret = tcg2_platform_get_tpm2(&dev);
if (ret != EFI_SUCCESS) {
event_log_location = NULL;
event_log_last_entry = NULL;
@@ -889,6 +389,7 @@
struct efi_image_regions *regs = NULL;
void *new_efi = NULL;
u8 hash[TPM2_SHA512_DIGEST_SIZE];
+ struct udevice *dev;
efi_status_t ret;
u32 active;
int i;
@@ -904,16 +405,20 @@
goto out;
}
- ret = __get_active_pcr_banks(&active);
+ ret = tcg2_platform_get_tpm2(&dev);
+ if (ret != EFI_SUCCESS)
+ goto out;
+
+ ret = tcg2_get_active_pcr_banks(dev, &active);
if (ret != EFI_SUCCESS) {
goto out;
}
digest_list->count = 0;
- for (i = 0; i < MAX_HASH_COUNT; i++) {
- u16 hash_alg = hash_algo_list[i].hash_alg;
+ for (i = 0; i < ARRAY_SIZE(tpm2_supported_algorithms); i++) {
+ u16 hash_alg = tpm2_supported_algorithms[i];
- if (!(active & alg_to_mask(hash_alg)))
+ if (!(active & tpm2_algorithm_to_mask(hash_alg)))
continue;
switch (hash_alg) {
case TPM2_ALG_SHA1:
@@ -933,7 +438,7 @@
}
digest_list->digests[digest_list->count].hash_alg = hash_alg;
memcpy(&digest_list->digests[digest_list->count].digest, hash,
- (u32)alg_to_len(hash_alg));
+ (u32)tpm2_algorithm_to_len(hash_alg));
digest_list->count++;
}
@@ -973,7 +478,7 @@
if (!is_tcg2_protocol_installed())
return EFI_SUCCESS;
- ret = platform_get_tpm2_device(&dev);
+ ret = tcg2_platform_get_tpm2(&dev);
if (ret != EFI_SUCCESS)
return EFI_SECURITY_VIOLATION;
@@ -1082,7 +587,7 @@
goto out;
}
- ret = platform_get_tpm2_device(&dev);
+ ret = tcg2_platform_get_tpm2(&dev);
if (ret != EFI_SUCCESS)
goto out;
@@ -1117,7 +622,7 @@
ret = tcg2_hash_pe_image((void *)(uintptr_t)data_to_hash,
data_to_hash_len, &digest_list);
} else {
- ret = tcg2_create_digest((u8 *)(uintptr_t)data_to_hash,
+ ret = tcg2_create_digest(dev, (u8 *)(uintptr_t)data_to_hash,
data_to_hash_len, &digest_list);
}
@@ -1180,7 +685,7 @@
goto out;
}
- ret = platform_get_tpm2_device(&dev);
+ ret = tcg2_platform_get_tpm2(&dev);
if (ret != EFI_SUCCESS)
goto out;
@@ -1209,15 +714,20 @@
efi_tcg2_get_active_pcr_banks(struct efi_tcg2_protocol *this,
u32 *active_pcr_banks)
{
+ struct udevice *dev;
efi_status_t ret;
+ EFI_ENTRY("%p, %p", this, active_pcr_banks);
+
if (!this || !active_pcr_banks) {
ret = EFI_INVALID_PARAMETER;
goto out;
}
+ ret = tcg2_platform_get_tpm2(&dev);
+ if (ret != EFI_SUCCESS)
+ goto out;
- EFI_ENTRY("%p, %p", this, active_pcr_banks);
- ret = __get_active_pcr_banks(active_pcr_banks);
+ ret = tcg2_get_active_pcr_banks(dev, active_pcr_banks);
out:
return EFI_EXIT(ret);
@@ -1269,397 +779,6 @@
};
/**
- * parse_event_log_header() - Parse and verify the event log header fields
- *
- * @buffer: Pointer to the start of the eventlog
- * @size: Size of the eventlog
- * @pos: Return offset of the next event in buffer right
- * after the event header i.e specID
- *
- * Return: status code
- */
-static efi_status_t parse_event_log_header(void *buffer, u32 size, u32 *pos)
-{
- struct tcg_pcr_event *event_header = (struct tcg_pcr_event *)buffer;
- int i = 0;
-
- if (size < sizeof(*event_header))
- return EFI_COMPROMISED_DATA;
-
- if (get_unaligned_le32(&event_header->pcr_index) != 0 ||
- get_unaligned_le32(&event_header->event_type) != EV_NO_ACTION)
- return EFI_COMPROMISED_DATA;
-
- for (i = 0; i < sizeof(event_header->digest); i++) {
- if (event_header->digest[i])
- return EFI_COMPROMISED_DATA;
- }
-
- *pos += sizeof(*event_header);
-
- return EFI_SUCCESS;
-}
-
-/**
- * parse_specid_event() - Parse and verify the specID Event in the eventlog
- *
- * @dev: udevice
- * @buffer: Pointer to the start of the eventlog
- * @log_size: Size of the eventlog
- * @pos: [in] Offset of specID event in the eventlog buffer
- * [out] Return offset of the next event in the buffer
- * after the specID
- * @digest_list: list of digests in the event
- *
- * Return: status code
- * @pos Offset in the eventlog where the specID event ends
- * @digest_list: list of digests in the event
- */
-static efi_status_t parse_specid_event(struct udevice *dev, void *buffer,
- u32 log_size, u32 *pos,
- struct tpml_digest_values *digest_list)
-{
- struct tcg_efi_spec_id_event *spec_event;
- struct tcg_pcr_event *event_header = (struct tcg_pcr_event *)buffer;
- size_t spec_event_size;
- u32 active = 0, supported = 0, pcr_count = 0, alg_count = 0;
- u32 spec_active = 0;
- u16 hash_alg;
- u8 vendor_sz;
- int err, i;
-
- if (*pos >= log_size || (*pos + sizeof(*spec_event)) > log_size)
- return EFI_COMPROMISED_DATA;
-
- /* Check specID event data */
- spec_event = (struct tcg_efi_spec_id_event *)((uintptr_t)buffer + *pos);
- /* Check for signature */
- if (memcmp(spec_event->signature, TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03,
- sizeof(TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03))) {
- log_err("specID Event: Signature mismatch\n");
- return EFI_COMPROMISED_DATA;
- }
-
- if (spec_event->spec_version_minor !=
- TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2 ||
- spec_event->spec_version_major !=
- TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2)
- return EFI_COMPROMISED_DATA;
-
- if (spec_event->number_of_algorithms > MAX_HASH_COUNT ||
- spec_event->number_of_algorithms < 1) {
- log_err("specID Event: Number of algorithms incorrect\n");
- return EFI_COMPROMISED_DATA;
- }
-
- alg_count = spec_event->number_of_algorithms;
-
- err = tpm2_get_pcr_info(dev, &supported, &active, &pcr_count);
- if (err)
- return EFI_DEVICE_ERROR;
-
- digest_list->count = 0;
- /*
- * We have to take care that the sequence of algorithms that we record
- * in digest_list matches the sequence in eventlog.
- */
- for (i = 0; i < alg_count; i++) {
- hash_alg =
- get_unaligned_le16(&spec_event->digest_sizes[i].algorithm_id);
-
- if (!(supported & alg_to_mask(hash_alg))) {
- log_err("specID Event: Unsupported algorithm\n");
- return EFI_COMPROMISED_DATA;
- }
- digest_list->digests[digest_list->count++].hash_alg = hash_alg;
-
- spec_active |= alg_to_mask(hash_alg);
- }
-
- /*
- * TCG specification expects the event log to have hashes for all
- * active PCR's
- */
- if (spec_active != active) {
- /*
- * Previous stage bootloader should know all the active PCR's
- * and use them in the Eventlog.
- */
- log_err("specID Event: All active hash alg not present\n");
- return EFI_COMPROMISED_DATA;
- }
-
- /*
- * the size of the spec event and placement of vendor_info_size
- * depends on supported algoriths
- */
- spec_event_size =
- offsetof(struct tcg_efi_spec_id_event, digest_sizes) +
- alg_count * sizeof(spec_event->digest_sizes[0]);
-
- if (*pos + spec_event_size >= log_size)
- return EFI_COMPROMISED_DATA;
-
- vendor_sz = *(uint8_t *)((uintptr_t)buffer + *pos + spec_event_size);
-
- spec_event_size += sizeof(vendor_sz) + vendor_sz;
- *pos += spec_event_size;
-
- if (get_unaligned_le32(&event_header->event_size) != spec_event_size) {
- log_err("specID event: header event size mismatch\n");
- /* Right way to handle this can be to call SetActive PCR's */
- return EFI_COMPROMISED_DATA;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- * tcg2_parse_event() - Parse the event in the eventlog
- *
- * @dev: udevice
- * @buffer: Pointer to the start of the eventlog
- * @log_size: Size of the eventlog
- * @offset: [in] Offset of the event in the eventlog buffer
- * [out] Return offset of the next event in the buffer
- * @digest_list: list of digests in the event
- * @pcr Index of the PCR in the event
- *
- * Return: status code
- */
-static efi_status_t tcg2_parse_event(struct udevice *dev, void *buffer,
- u32 log_size, u32 *offset,
- struct tpml_digest_values *digest_list,
- u32 *pcr)
-{
- struct tcg_pcr_event2 *event = NULL;
- u32 count, size, event_size;
- size_t pos;
-
- event_size = tcg_event_final_size(digest_list);
- if (*offset >= log_size || *offset + event_size > log_size) {
- log_err("Event exceeds log size\n");
- return EFI_COMPROMISED_DATA;
- }
-
- event = (struct tcg_pcr_event2 *)((uintptr_t)buffer + *offset);
- *pcr = get_unaligned_le32(&event->pcr_index);
-
- /* get the count */
- count = get_unaligned_le32(&event->digests.count);
- if (count != digest_list->count)
- return EFI_COMPROMISED_DATA;
-
- pos = offsetof(struct tcg_pcr_event2, digests);
- pos += offsetof(struct tpml_digest_values, digests);
-
- for (int i = 0; i < digest_list->count; i++) {
- u16 alg;
- u16 hash_alg = digest_list->digests[i].hash_alg;
- u8 *digest = (u8 *)&digest_list->digests[i].digest;
-
- alg = get_unaligned_le16((void *)((uintptr_t)event + pos));
-
- if (alg != hash_alg)
- return EFI_COMPROMISED_DATA;
-
- pos += offsetof(struct tpmt_ha, digest);
- memcpy(digest, (void *)((uintptr_t)event + pos), alg_to_len(hash_alg));
- pos += alg_to_len(hash_alg);
- }
-
- size = get_unaligned_le32((void *)((uintptr_t)event + pos));
- event_size += size;
- pos += sizeof(u32); /* tcg_pcr_event2 event_size*/
- pos += size;
-
- /* make sure the calculated buffer is what we checked against */
- if (pos != event_size)
- return EFI_COMPROMISED_DATA;
-
- if (pos > log_size)
- return EFI_COMPROMISED_DATA;
-
- *offset += pos;
-
- return EFI_SUCCESS;
-}
-
-/**
- * tcg2_get_fw_eventlog() - Get the eventlog address and size
- *
- * If the previous firmware has passed some eventlog, this function get it's
- * location and check for it's validity.
- *
- * @dev: udevice
- * @log_buffer: eventlog address
- * @log_sz: eventlog size
- *
- * Return: status code
- */
-static efi_status_t tcg2_get_fw_eventlog(struct udevice *dev, void *log_buffer,
- size_t *log_sz)
-{
- struct tpml_digest_values digest_list;
- void *buffer;
- efi_status_t ret;
- u32 pcr, pos;
- u64 base;
- u32 sz;
- bool extend_pcr = false;
- int i;
-
- ret = platform_get_eventlog(dev, &base, &sz);
- if (ret != EFI_SUCCESS)
- return ret;
-
- if (sz > TPM2_EVENT_LOG_SIZE)
- return EFI_VOLUME_FULL;
-
- buffer = (void *)(uintptr_t)base;
- pos = 0;
- /* Parse the eventlog to check for its validity */
- ret = parse_event_log_header(buffer, sz, &pos);
- if (ret)
- return ret;
-
- ret = parse_specid_event(dev, buffer, sz, &pos, &digest_list);
- if (ret) {
- log_err("Error parsing SPEC ID Event\n");
- return ret;
- }
-
- ret = tcg2_pcr_read(dev, 0, &digest_list);
- if (ret) {
- log_err("Error reading PCR 0\n");
- return ret;
- }
-
- /*
- * If PCR0 is 0, previous firmware didn't have the capability
- * to extend the PCR. In this scenario, extend the PCR as
- * the eventlog is parsed.
- */
- for (i = 0; i < digest_list.count; i++) {
- u8 hash_buf[TPM2_SHA512_DIGEST_SIZE] = { 0 };
- u16 hash_alg = digest_list.digests[i].hash_alg;
-
- if (!memcmp((u8 *)&digest_list.digests[i].digest, hash_buf,
- alg_to_len(hash_alg)))
- extend_pcr = true;
- }
-
- while (pos < sz) {
- ret = tcg2_parse_event(dev, buffer, sz, &pos, &digest_list,
- &pcr);
- if (ret) {
- log_err("Error parsing event\n");
- return ret;
- }
- if (extend_pcr) {
- ret = tcg2_pcr_extend(dev, pcr, &digest_list);
- if (ret != EFI_SUCCESS) {
- log_err("Error in extending PCR\n");
- return ret;
- }
-
- /* Clear the digest for next event */
- for (i = 0; i < digest_list.count; i++) {
- u16 hash_alg = digest_list.digests[i].hash_alg;
- u8 *digest =
- (u8 *)&digest_list.digests[i].digest;
-
- memset(digest, 0, alg_to_len(hash_alg));
- }
- }
- }
-
- memcpy(log_buffer, buffer, sz);
- *log_sz = sz;
-
- return ret;
-}
-
-/**
- * create_specid_event() - Create the first event in the eventlog
- *
- * @dev: tpm device
- * @event_header: Pointer to the final event header
- * @event_size: final spec event size
- *
- * Return: status code
- */
-static efi_status_t create_specid_event(struct udevice *dev, void *buffer,
- size_t *event_size)
-{
- struct tcg_efi_spec_id_event *spec_event;
- size_t spec_event_size;
- efi_status_t ret = EFI_DEVICE_ERROR;
- u32 active = 0, supported = 0, pcr_count = 0, alg_count = 0;
- int err;
- size_t i;
-
- /*
- * Create Spec event. This needs to be the first event in the log
- * according to the TCG EFI protocol spec
- */
-
- /* Setup specID event data */
- spec_event = (struct tcg_efi_spec_id_event *)buffer;
- memcpy(spec_event->signature, TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03,
- sizeof(spec_event->signature));
- put_unaligned_le32(0, &spec_event->platform_class); /* type client */
- spec_event->spec_version_minor =
- TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2;
- spec_event->spec_version_major =
- TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2;
- spec_event->spec_errata =
- TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2;
- spec_event->uintn_size = sizeof(efi_uintn_t) / sizeof(u32);
-
- err = tpm2_get_pcr_info(dev, &supported, &active, &pcr_count);
-
- if (err)
- goto out;
-
- for (i = 0; i < pcr_count; i++) {
- u16 hash_alg = hash_algo_list[i].hash_alg;
- u16 hash_len = hash_algo_list[i].hash_len;
-
- if (active & alg_to_mask(hash_alg)) {
- put_unaligned_le16(hash_alg,
- &spec_event->digest_sizes[alg_count].algorithm_id);
- put_unaligned_le16(hash_len,
- &spec_event->digest_sizes[alg_count].digest_size);
- alg_count++;
- }
- }
-
- spec_event->number_of_algorithms = alg_count;
- if (spec_event->number_of_algorithms > MAX_HASH_COUNT ||
- spec_event->number_of_algorithms < 1)
- goto out;
-
- /*
- * the size of the spec event and placement of vendor_info_size
- * depends on supported algoriths
- */
- spec_event_size =
- offsetof(struct tcg_efi_spec_id_event, digest_sizes) +
- spec_event->number_of_algorithms * sizeof(spec_event->digest_sizes[0]);
- /* no vendor info for us */
- memset(buffer + spec_event_size, 0, 1);
- /* add a byte for vendor_info_size in the spec event */
- spec_event_size += 1;
- *event_size = spec_event_size;
-
- return EFI_SUCCESS;
-
-out:
- return ret;
-}
-
-/**
* tcg2_uninit - remove the final event table and free efi memory on failures
*/
void tcg2_uninit(void)
@@ -1720,7 +839,7 @@
}
/**
- * tcg2_measure_event() - common function to add event log and extend PCR
+ * measure_event() - common function to add event log and extend PCR
*
* @dev: TPM device
* @pcr_index: PCR index
@@ -1730,14 +849,13 @@
*
* Return: status code
*/
-static efi_status_t
-tcg2_measure_event(struct udevice *dev, u32 pcr_index, u32 event_type,
- u32 size, u8 event[])
+static efi_status_t measure_event(struct udevice *dev, u32 pcr_index,
+ u32 event_type, u32 size, u8 event[])
{
struct tpml_digest_values digest_list;
efi_status_t ret;
- ret = tcg2_create_digest(event, size, &digest_list);
+ ret = tcg2_create_digest(dev, event, size, &digest_list);
if (ret != EFI_SUCCESS)
goto out;
@@ -1764,9 +882,8 @@
{
efi_status_t ret;
- ret = tcg2_measure_event(dev, 0, EV_S_CRTM_VERSION,
- strlen(version_string) + 1,
- (u8 *)version_string);
+ ret = measure_event(dev, 0, EV_S_CRTM_VERSION,
+ strlen(version_string) + 1, (u8 *)version_string);
return ret;
}
@@ -1782,12 +899,11 @@
* vendor_info_size is currently set to 0, we need to change the length
* and allocate the flexible array member if this changes
*/
- struct tcg_pcr_event *event_header = NULL;
+ struct tcg2_event_log elog;
struct udevice *dev;
- size_t spec_event_size;
efi_status_t ret;
- ret = platform_get_tpm2_device(&dev);
+ ret = tcg2_platform_get_tpm2(&dev);
if (ret != EFI_SUCCESS)
return ret;
@@ -1806,7 +922,6 @@
* The log header is defined to be in SHA1 event log entry format.
* Setup event header
*/
- event_header = (struct tcg_pcr_event *)event_log.buffer;
event_log.pos = 0;
event_log.last_event_size = 0;
event_log.get_event_called = false;
@@ -1817,35 +932,24 @@
* Check if earlier firmware have passed any eventlog. Different
* platforms can use different ways to do so.
*/
- ret = tcg2_get_fw_eventlog(dev, event_log.buffer, &event_log.pos);
- /*
- * If earlier firmware hasn't passed any eventlog, go ahead and
- * create the eventlog header.
- */
- if (ret == EFI_NOT_FOUND) {
- put_unaligned_le32(0, &event_header->pcr_index);
- put_unaligned_le32(EV_NO_ACTION, &event_header->event_type);
- memset(&event_header->digest, 0, sizeof(event_header->digest));
- ret = create_specid_event(dev,
- (void *)((uintptr_t)event_log.buffer +
- sizeof(*event_header)),
- &spec_event_size);
- if (ret != EFI_SUCCESS)
- goto free_pool;
- put_unaligned_le32(spec_event_size, &event_header->event_size);
- event_log.pos = spec_event_size + sizeof(*event_header);
- event_log.last_event_size = event_log.pos;
-
- /*
- * Add SCRTM version to the log if previous firmmware
- * doesn't pass an eventlog.
- */
- ret = efi_append_scrtm_version(dev);
- }
-
+ elog.log = event_log.buffer;
+ elog.log_size = TPM2_EVENT_LOG_SIZE;
+ ret = tcg2_log_prepare_buffer(dev, &elog, false);
if (ret != EFI_SUCCESS)
goto free_pool;
+ event_log.pos = elog.log_position;
+
+ /*
+ * Add SCRTM version to the log if previous firmmware
+ * doesn't pass an eventlog.
+ */
+ if (!elog.found) {
+ ret = efi_append_scrtm_version(dev);
+ if (ret != EFI_SUCCESS)
+ goto free_pool;
+ }
+
ret = create_final_event();
if (ret != EFI_SUCCESS)
goto free_pool;
@@ -1897,8 +1001,8 @@
memcpy((u16 *)event->unicode_name + event->unicode_name_length,
data, data_size);
}
- ret = tcg2_measure_event(dev, pcr_index, event_type, event_size,
- (u8 *)event);
+ ret = measure_event(dev, pcr_index, event_type, event_size,
+ (u8 *)event);
free(event);
return ret;
}
@@ -2009,8 +1113,8 @@
smbios_prepare_measurement(entry, smbios_copy);
- ret = tcg2_measure_event(dev, 1, EV_EFI_HANDOFF_TABLES2, event_size,
- (u8 *)event);
+ ret = measure_event(dev, 1, EV_EFI_HANDOFF_TABLES2, event_size,
+ (u8 *)event);
if (ret != EFI_SUCCESS)
goto out;
@@ -2161,7 +1265,7 @@
gpt_e = (gpt_entry *)((u8 *)gpt_e + gpt_h->sizeof_partition_entry);
}
- ret = tcg2_measure_event(dev, 5, EV_EFI_GPT_EVENT, event_size, (u8 *)event);
+ ret = measure_event(dev, 5, EV_EFI_GPT_EVENT, event_size, (u8 *)event);
out2:
free(gpt_h);
@@ -2215,7 +1319,7 @@
if (!is_tcg2_protocol_installed())
return EFI_SUCCESS;
- ret = platform_get_tpm2_device(&dev);
+ ret = tcg2_platform_get_tpm2(&dev);
if (ret != EFI_SUCCESS)
return EFI_SECURITY_VIOLATION;
@@ -2240,7 +1344,7 @@
sha256_update(&hash_ctx, (u8 *)dtb + fdt_off_mem_rsvmap(dtb), rsvmap_size);
sha256_finish(&hash_ctx, blob->data + blob->blob_description_size);
- ret = tcg2_measure_event(dev, 0, EV_POST_CODE, event_size, (u8 *)blob);
+ ret = measure_event(dev, 0, EV_POST_CODE, event_size, (u8 *)blob);
free(blob);
return ret;
@@ -2265,7 +1369,7 @@
if (tcg2_efi_app_invoked)
return EFI_SUCCESS;
- ret = platform_get_tpm2_device(&dev);
+ ret = tcg2_platform_get_tpm2(&dev);
if (ret != EFI_SUCCESS)
return EFI_SECURITY_VIOLATION;
@@ -2273,9 +1377,9 @@
if (ret != EFI_SUCCESS)
goto out;
- ret = tcg2_measure_event(dev, 4, EV_EFI_ACTION,
- strlen(EFI_CALLING_EFI_APPLICATION),
- (u8 *)EFI_CALLING_EFI_APPLICATION);
+ ret = measure_event(dev, 4, EV_EFI_ACTION,
+ strlen(EFI_CALLING_EFI_APPLICATION),
+ (u8 *)EFI_CALLING_EFI_APPLICATION);
if (ret != EFI_SUCCESS)
goto out;
@@ -2291,8 +1395,8 @@
goto out;
for (pcr_index = 0; pcr_index <= 7; pcr_index++) {
- ret = tcg2_measure_event(dev, pcr_index, EV_SEPARATOR,
- sizeof(event), (u8 *)&event);
+ ret = measure_event(dev, pcr_index, EV_SEPARATOR,
+ sizeof(event), (u8 *)&event);
if (ret != EFI_SUCCESS)
goto out;
}
@@ -2315,13 +1419,13 @@
if (!is_tcg2_protocol_installed())
return EFI_SUCCESS;
- ret = platform_get_tpm2_device(&dev);
+ ret = tcg2_platform_get_tpm2(&dev);
if (ret != EFI_SUCCESS)
return ret;
- ret = tcg2_measure_event(dev, 4, EV_EFI_ACTION,
- strlen(EFI_RETURNING_FROM_EFI_APPLICATION),
- (u8 *)EFI_RETURNING_FROM_EFI_APPLICATION);
+ ret = measure_event(dev, 4, EV_EFI_ACTION,
+ strlen(EFI_RETURNING_FROM_EFI_APPLICATION),
+ (u8 *)EFI_RETURNING_FROM_EFI_APPLICATION);
return ret;
}
@@ -2346,19 +1450,19 @@
goto out;
}
- ret = platform_get_tpm2_device(&dev);
+ ret = tcg2_platform_get_tpm2(&dev);
if (ret != EFI_SUCCESS)
goto out;
- ret = tcg2_measure_event(dev, 5, EV_EFI_ACTION,
- strlen(EFI_EXIT_BOOT_SERVICES_INVOCATION),
- (u8 *)EFI_EXIT_BOOT_SERVICES_INVOCATION);
+ ret = measure_event(dev, 5, EV_EFI_ACTION,
+ strlen(EFI_EXIT_BOOT_SERVICES_INVOCATION),
+ (u8 *)EFI_EXIT_BOOT_SERVICES_INVOCATION);
if (ret != EFI_SUCCESS)
goto out;
- ret = tcg2_measure_event(dev, 5, EV_EFI_ACTION,
- strlen(EFI_EXIT_BOOT_SERVICES_SUCCEEDED),
- (u8 *)EFI_EXIT_BOOT_SERVICES_SUCCEEDED);
+ ret = measure_event(dev, 5, EV_EFI_ACTION,
+ strlen(EFI_EXIT_BOOT_SERVICES_SUCCEEDED),
+ (u8 *)EFI_EXIT_BOOT_SERVICES_SUCCEEDED);
out:
EFI_EXIT(ret);
@@ -2378,19 +1482,19 @@
if (!is_tcg2_protocol_installed())
return EFI_SUCCESS;
- ret = platform_get_tpm2_device(&dev);
+ ret = tcg2_platform_get_tpm2(&dev);
if (ret != EFI_SUCCESS)
goto out;
- ret = tcg2_measure_event(dev, 5, EV_EFI_ACTION,
- strlen(EFI_EXIT_BOOT_SERVICES_INVOCATION),
- (u8 *)EFI_EXIT_BOOT_SERVICES_INVOCATION);
+ ret = measure_event(dev, 5, EV_EFI_ACTION,
+ strlen(EFI_EXIT_BOOT_SERVICES_INVOCATION),
+ (u8 *)EFI_EXIT_BOOT_SERVICES_INVOCATION);
if (ret != EFI_SUCCESS)
goto out;
- ret = tcg2_measure_event(dev, 5, EV_EFI_ACTION,
- strlen(EFI_EXIT_BOOT_SERVICES_FAILED),
- (u8 *)EFI_EXIT_BOOT_SERVICES_FAILED);
+ ret = measure_event(dev, 5, EV_EFI_ACTION,
+ strlen(EFI_EXIT_BOOT_SERVICES_FAILED),
+ (u8 *)EFI_EXIT_BOOT_SERVICES_FAILED);
out:
return ret;
@@ -2460,7 +1564,7 @@
if (!is_tcg2_protocol_installed())
return EFI_SUCCESS;
- ret = platform_get_tpm2_device(&dev);
+ ret = tcg2_platform_get_tpm2(&dev);
if (ret != EFI_SUCCESS)
return EFI_SECURITY_VIOLATION;
@@ -2486,7 +1590,7 @@
struct efi_event *event;
u32 err;
- ret = platform_get_tpm2_device(&dev);
+ ret = tcg2_platform_get_tpm2(&dev);
if (ret != EFI_SUCCESS) {
log_warning("Missing TPMv2 device for EFI_TCG_PROTOCOL\n");
return EFI_SUCCESS;
diff --git a/lib/efi_loader/efi_var_file.c b/lib/efi_loader/efi_var_file.c
index 62e071b..d7dba05 100644
--- a/lib/efi_loader/efi_var_file.c
+++ b/lib/efi_loader/efi_var_file.c
@@ -204,8 +204,11 @@
* File ubootefi.var is read from the EFI system partitions and the variables
* stored in the file are created.
*
- * In case the file does not exist yet or a variable cannot be set EFI_SUCCESS
- * is returned.
+ * On first boot the file ubootefi.var does not exist yet. This is why we must
+ * return EFI_SUCCESS in this case.
+ *
+ * If the variable file is corrupted, e.g. incorrect CRC32, we do not want to
+ * stop the boot process. We deliberately return EFI_SUCCESS in this case, too.
*
* Return: status code
*/
diff --git a/lib/efi_selftest/efi_selftest_bitblt.c b/lib/efi_selftest/efi_selftest_bitblt.c
index 1def843..605078b 100644
--- a/lib/efi_selftest/efi_selftest_bitblt.c
+++ b/lib/efi_selftest/efi_selftest_bitblt.c
@@ -14,6 +14,12 @@
#define HEIGHT 120
#define DEPTH 60
+struct pos {
+ efi_uintn_t x;
+ efi_uintn_t y;
+ int redrawn;
+};
+
static const struct efi_gop_pixel BLACK = { 0, 0, 0, 0};
static const struct efi_gop_pixel RED = { 0, 0, 255, 0};
static const struct efi_gop_pixel ORANGE = { 0, 128, 255, 0};
@@ -27,7 +33,7 @@
static struct efi_gop *gop;
static struct efi_gop_pixel *bitmap;
static struct efi_event *event;
-static efi_uintn_t xpos;
+static struct pos pos;
static void ellipse(efi_uintn_t x, efi_uintn_t y,
efi_uintn_t x0, efi_uintn_t y0,
@@ -62,31 +68,33 @@
*/
static void EFIAPI notify(struct efi_event *event, void *context)
{
- efi_uintn_t *pos = context;
+ struct pos *pos = context;
efi_uintn_t dx, sx, width;
if (!pos)
return;
/* Increment position */
- *pos += 5;
- if (*pos >= WIDTH + gop->mode->info->width)
- *pos = 0;
+ pos->x += 5;
+ if (pos->x >= WIDTH + gop->mode->info->width)
+ pos->x = 0;
width = WIDTH;
- dx = *pos - WIDTH;
+ dx = pos->x - WIDTH;
sx = 0;
- if (*pos >= gop->mode->info->width) {
- width = WIDTH + gop->mode->info->width - *pos;
- } else if (*pos < WIDTH) {
+ if (pos->x >= gop->mode->info->width) {
+ width = WIDTH + gop->mode->info->width - pos->x;
+ } else if (pos->x < WIDTH) {
dx = 0;
- sx = WIDTH - *pos;
- width = *pos;
+ sx = WIDTH - pos->x;
+ width = pos->x;
}
/* Copy image to video */
- gop->blt(gop, bitmap, EFI_BLT_BUFFER_TO_VIDEO, sx, 0, dx, DEPTH,
+ gop->blt(gop, bitmap, EFI_BLT_BUFFER_TO_VIDEO, sx, 0, dx, pos->y,
width, HEIGHT, WIDTH * sizeof(struct efi_gop_pixel));
+
+ pos->redrawn = 1;
}
/*
@@ -107,7 +115,7 @@
/* Create event */
ret = boottime->create_event(EVT_TIMER | EVT_NOTIFY_SIGNAL,
- TPL_CALLBACK, notify, (void *)&xpos,
+ TPL_CALLBACK, notify, (void *)&pos,
&event);
if (ret != EFI_SUCCESS) {
efi_st_error("could not create event\n");
@@ -247,6 +255,9 @@
return EFI_ST_FAILURE;
}
+ con_out->set_attribute(con_out, EFI_WHITE | EFI_BACKGROUND_BLUE);
+ con_out->clear_screen(con_out);
+
/* Fill background */
ret = gop->blt(gop, bitmap, EFI_BLT_VIDEO_FILL, 0, 0, 0, 0,
info->width, info->height, 0);
@@ -281,21 +292,53 @@
return EFI_ST_FAILURE;
}
- /* Set 250ms timer */
- xpos = WIDTH;
+ /* Set 25ms timer */
+ pos.x = WIDTH;
+ pos.y = DEPTH;
ret = boottime->set_timer(event, EFI_TIMER_PERIODIC, 250000);
if (ret != EFI_SUCCESS) {
efi_st_error("Could not set timer\n");
return EFI_ST_FAILURE;
}
- con_out->set_cursor_position(con_out, 0, 0);
- con_out->set_attribute(con_out, EFI_WHITE | EFI_BACKGROUND_BLUE);
efi_st_printf("The submarine should have three yellow port holes.\n");
- efi_st_printf("Press any key to continue");
- efi_st_get_key();
+ efi_st_printf("UP, DOWN to navigate, any other key to quit");
+ for (;;) {
+ struct efi_input_key input_key;
+
+ ret = boottime->check_event(con_in->wait_for_key);
+ if (ret == EFI_NOT_READY)
+ continue;
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("CheckEvent failed %x\n",
+ (unsigned int)ret);
+ return EFI_ST_FAILURE;
+ }
+ ret = con_in->read_key_stroke(con_in, &input_key);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Key not available %x\n",
+ (unsigned int)ret);
+ return EFI_ST_FAILURE;
+ }
+ switch (input_key.scan_code) {
+ case 0x01: /* UP */
+ if (pos.redrawn && pos.y >= 5) {
+ pos.y -= 5;
+ pos.redrawn = 0;
+ }
+ continue;
+ case 0x02: /* DOWN */
+ if (pos.redrawn &&
+ pos.y + HEIGHT + 5 < gop->mode->info->height) {
+ pos.y += 5;
+ pos.redrawn = 0;
+ }
+ continue;
+ }
+ break;
+ }
con_out->set_attribute(con_out, EFI_LIGHTGRAY);
- efi_st_printf("\n");
+ con_out->clear_screen(con_out);
return EFI_ST_SUCCESS;
}
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index c60972d..7a69167 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1230,12 +1230,12 @@
#ifdef CONFIG_SPL_BUILD
/* FDT is at end of BSS unless it is in a different memory region */
if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
- fdt_blob = (ulong *)&_image_binary_end;
+ fdt_blob = (ulong *)_image_binary_end;
else
- fdt_blob = (ulong *)&__bss_end;
+ fdt_blob = (ulong *)__bss_end;
#else
/* FDT is at end of image */
- fdt_blob = (ulong *)&_end;
+ fdt_blob = (ulong *)_end;
if (_DEBUG && !fdtdec_prepare_fdt(fdt_blob)) {
int stack_ptr;
diff --git a/lib/fwu_updates/Kconfig b/lib/fwu_updates/Kconfig
index 71f3479..d35247d 100644
--- a/lib/fwu_updates/Kconfig
+++ b/lib/fwu_updates/Kconfig
@@ -1,4 +1,4 @@
-config FWU_MULTI_BANK_UPDATE
+menuconfig FWU_MULTI_BANK_UPDATE
bool "Enable FWU Multi Bank Update Feature"
depends on EFI_CAPSULE_ON_DISK
select PARTITION_TYPE_GUID
@@ -10,24 +10,25 @@
multiple banks(copies) of the firmware images. One of the
bank is selected for updating all the firmware components
+if FWU_MULTI_BANK_UPDATE
+
config FWU_NUM_BANKS
int "Number of Banks defined by the platform"
- depends on FWU_MULTI_BANK_UPDATE
help
Define the number of banks of firmware images on a platform
config FWU_NUM_IMAGES_PER_BANK
int "Number of firmware images per bank"
- depends on FWU_MULTI_BANK_UPDATE
help
Define the number of firmware images per bank. This value
should be the same for all the banks.
config FWU_TRIAL_STATE_CNT
int "Number of times system boots in Trial State"
- depends on FWU_MULTI_BANK_UPDATE
default 3
help
With FWU Multi Bank Update feature enabled, number of times
the platform is allowed to boot in Trial State after an
update.
+
+endif
diff --git a/lib/fwu_updates/fwu.c b/lib/fwu_updates/fwu.c
index 4d0c8b8..b580574 100644
--- a/lib/fwu_updates/fwu.c
+++ b/lib/fwu_updates/fwu.c
@@ -618,23 +618,23 @@
return ret;
}
-static int fwu_boottime_checks(void *ctx, struct event *event)
+static int fwu_boottime_checks(void)
{
int ret;
u32 boot_idx, active_idx;
- /* Don't have boot time checks on sandbox */
- if (IS_ENABLED(CONFIG_SANDBOX)) {
- boottime_check = 1;
- return 0;
- }
-
ret = uclass_first_device_err(UCLASS_FWU_MDATA, &g_dev);
if (ret) {
log_debug("Cannot find fwu device\n");
return ret;
}
+ /* Don't have boot time checks on sandbox */
+ if (IS_ENABLED(CONFIG_SANDBOX)) {
+ boottime_check = 1;
+ return 0;
+ }
+
ret = fwu_get_mdata(NULL);
if (ret) {
log_debug("Unable to read meta-data\n");
@@ -682,4 +682,4 @@
return 0;
}
-EVENT_SPY(EVT_MAIN_LOOP, fwu_boottime_checks);
+EVENT_SPY_SIMPLE(EVT_MAIN_LOOP, fwu_boottime_checks);
diff --git a/lib/image-sparse.c b/lib/image-sparse.c
index 8f8a67e..323aad9 100644
--- a/lib/image-sparse.c
+++ b/lib/image-sparse.c
@@ -289,8 +289,8 @@
case CHUNK_TYPE_CRC32:
if (chunk_header->total_sz !=
- sparse_header->chunk_hdr_sz) {
- info->mssg("Bogus chunk size for chunk type Dont Care",
+ sparse_header->chunk_hdr_sz + sizeof(uint32_t)) {
+ info->mssg("Bogus chunk size for chunk type CRC32",
response);
return -1;
}
diff --git a/lib/initcall.c b/lib/initcall.c
new file mode 100644
index 0000000..33b7d76
--- /dev/null
+++ b/lib/initcall.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 The Chromium OS Authors.
+ */
+
+#include <common.h>
+#include <efi.h>
+#include <initcall.h>
+#include <log.h>
+#include <relocate.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong calc_reloc_ofs(void)
+{
+#ifdef CONFIG_EFI_APP
+ return (ulong)image_base;
+#endif
+ /*
+ * Sandbox is relocated by the OS, so symbols always appear at
+ * the relocated address.
+ */
+ if (IS_ENABLED(CONFIG_SANDBOX) || (gd->flags & GD_FLG_RELOC))
+ return gd->reloc_off;
+
+ return 0;
+}
+
+/**
+ * initcall_is_event() - Get the event number for an initcall
+ *
+ * func: Function pointer to check
+ * Return: Event number, if this is an event, else 0
+ */
+static int initcall_is_event(init_fnc_t func)
+{
+ ulong val = (ulong)func;
+
+ if ((val & INITCALL_IS_EVENT) == INITCALL_IS_EVENT)
+ return val & INITCALL_EVENT_TYPE;
+
+ return 0;
+}
+
+/*
+ * To enable debugging. add #define DEBUG at the top of the including file.
+ *
+ * To find a symbol, use grep on u-boot.map
+ */
+int initcall_run_list(const init_fnc_t init_sequence[])
+{
+ ulong reloc_ofs = calc_reloc_ofs();
+ const init_fnc_t *ptr;
+ enum event_t type;
+ init_fnc_t func;
+ int ret = 0;
+
+ for (ptr = init_sequence; func = *ptr, !ret && func; ptr++) {
+ type = initcall_is_event(func);
+
+ if (type) {
+ if (!CONFIG_IS_ENABLED(EVENT))
+ continue;
+ debug("initcall: event %d/%s\n", type,
+ event_type_name(type));
+ } else if (reloc_ofs) {
+ debug("initcall: %p (relocated to %p)\n",
+ (char *)func - reloc_ofs, (char *)func);
+ } else {
+ debug("initcall: %p\n", (char *)func - reloc_ofs);
+ }
+
+ ret = type ? event_notify_null(type) : func();
+ }
+
+ if (ret) {
+ if (CONFIG_IS_ENABLED(EVENT)) {
+ char buf[60];
+
+ /* don't worry about buf size as we are dying here */
+ if (type) {
+ sprintf(buf, "event %d/%s", type,
+ event_type_name(type));
+ } else {
+ sprintf(buf, "call %p", func);
+ }
+
+ printf("initcall failed at %s (err=%dE)\n", buf, ret);
+ } else {
+ printf("initcall failed at call %p (err=%d)\n",
+ (char *)func - reloc_ofs, ret);
+ }
+
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/lib/list_sort.c b/lib/list_sort.c
index 58e1e16..1c9e061 100644
--- a/lib/list_sort.c
+++ b/lib/list_sort.c
@@ -8,6 +8,7 @@
#include <linux/compat.h>
#include <common.h>
#include <malloc.h>
+#include <linux/printk.h>
#endif
#include <linux/list.h>
#include <linux/list_sort.h>
diff --git a/lib/lmb.c b/lib/lmb.c
index b2c233e..da924c6 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -74,6 +74,16 @@
return 0;
}
+static long lmb_regions_overlap(struct lmb_region *rgn, unsigned long r1,
+ unsigned long r2)
+{
+ phys_addr_t base1 = rgn->region[r1].base;
+ phys_size_t size1 = rgn->region[r1].size;
+ phys_addr_t base2 = rgn->region[r2].base;
+ phys_size_t size2 = rgn->region[r2].size;
+
+ return lmb_addrs_overlap(base1, size1, base2, size2);
+}
static long lmb_regions_adjacent(struct lmb_region *rgn, unsigned long r1,
unsigned long r2)
{
@@ -81,7 +91,6 @@
phys_size_t size1 = rgn->region[r1].size;
phys_addr_t base2 = rgn->region[r2].base;
phys_size_t size2 = rgn->region[r2].size;
-
return lmb_addrs_adjacent(base1, size1, base2, size2);
}
@@ -105,6 +114,23 @@
lmb_remove_region(rgn, r2);
}
+/*Assumption : base addr of region 1 < base addr of region 2*/
+static void lmb_fix_over_lap_regions(struct lmb_region *rgn, unsigned long r1,
+ unsigned long r2)
+{
+ phys_addr_t base1 = rgn->region[r1].base;
+ phys_size_t size1 = rgn->region[r1].size;
+ phys_addr_t base2 = rgn->region[r2].base;
+ phys_size_t size2 = rgn->region[r2].size;
+
+ if (base1 + size1 > base2 + size2) {
+ printf("This will not be a case any time\n");
+ return;
+ }
+ rgn->region[r1].size = base2 + size2 - base1;
+ lmb_remove_region(rgn, r2);
+}
+
void lmb_init(struct lmb *lmb)
{
#if IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS)
@@ -249,7 +275,6 @@
phys_size_t rgnflags = rgn->region[i].flags;
phys_addr_t end = base + size - 1;
phys_addr_t rgnend = rgnbase + rgnsize - 1;
-
if (rgnbase <= base && end <= rgnend) {
if (flags == rgnflags)
/* Already have this region, so we're done */
@@ -278,10 +303,14 @@
}
}
- if ((i < rgn->cnt - 1) && lmb_regions_adjacent(rgn, i, i + 1)) {
- if (rgn->region[i].flags == rgn->region[i + 1].flags) {
+ if (i < rgn->cnt - 1 && rgn->region[i].flags == rgn->region[i + 1].flags) {
+ if (lmb_regions_adjacent(rgn, i, i + 1)) {
lmb_coalesce_regions(rgn, i, i + 1);
coalesced++;
+ } else if (lmb_regions_overlap(rgn, i, i + 1)) {
+ /* fix overlapping area */
+ lmb_fix_over_lap_regions(rgn, i, i + 1);
+ coalesced++;
}
}
diff --git a/lib/of_live.c b/lib/of_live.c
index 25f7af6..812c488 100644
--- a/lib/of_live.c
+++ b/lib/of_live.c
@@ -8,13 +8,21 @@
* Copyright (c) 2017 Google, Inc
*/
+#define LOG_CATEGORY LOGC_DT
+
#include <common.h>
+#include <abuf.h>
#include <log.h>
#include <linux/libfdt.h>
#include <of_live.h>
#include <malloc.h>
#include <dm/of_access.h>
#include <linux/err.h>
+#include <linux/sizes.h>
+
+enum {
+ BUF_STEP = SZ_64K,
+};
static void *unflatten_dt_alloc(void **mem, unsigned long size,
unsigned long align)
@@ -336,3 +344,136 @@
/* the tree is stored as a contiguous block of memory */
free(root);
}
+
+int of_live_create_empty(struct device_node **rootp)
+{
+ struct device_node *root;
+
+ root = calloc(1, sizeof(struct device_node));
+ if (!root)
+ return -ENOMEM;
+ root->name = strdup("");
+ if (!root->name) {
+ free(root);
+ return -ENOMEM;
+ }
+ root->type = "<NULL>";
+ root->full_name = "";
+ *rootp = root;
+
+ return 0;
+}
+
+static int check_space(int ret, struct abuf *buf)
+{
+ if (ret == -FDT_ERR_NOSPACE) {
+ if (!abuf_realloc_inc(buf, BUF_STEP))
+ return log_msg_ret("spc", -ENOMEM);
+ ret = fdt_resize(abuf_data(buf), abuf_data(buf),
+ abuf_size(buf));
+ if (ret)
+ return log_msg_ret("res", -EFAULT);
+
+ return -EAGAIN;
+ }
+
+ return 0;
+}
+
+/**
+ * flatten_node() - Write out the node and its properties into a flat tree
+ */
+static int flatten_node(struct abuf *buf, const struct device_node *node)
+{
+ const struct device_node *np;
+ const struct property *pp;
+ int ret;
+
+ ret = fdt_begin_node(abuf_data(buf), node->name);
+ ret = check_space(ret, buf);
+ if (ret == -EAGAIN) {
+ ret = fdt_begin_node(abuf_data(buf), node->name);
+ if (ret) {
+ log_debug("Internal error a %d\n", ret);
+ return -EFAULT;
+ }
+ }
+ if (ret)
+ return log_msg_ret("beg", ret);
+
+ /* First write out the properties */
+ for (pp = node->properties; !ret && pp; pp = pp->next) {
+ ret = fdt_property(abuf_data(buf), pp->name, pp->value,
+ pp->length);
+ ret = check_space(ret, buf);
+ if (ret == -EAGAIN) {
+ ret = fdt_property(abuf_data(buf), pp->name, pp->value,
+ pp->length);
+ }
+ }
+
+ /* Next write out the subnodes */
+ for (np = node->child; np; np = np->sibling) {
+ ret = flatten_node(buf, np);
+ if (ret)
+ return log_msg_ret("sub", ret);
+ }
+
+ ret = fdt_end_node(abuf_data(buf));
+ ret = check_space(ret, buf);
+ if (ret == -EAGAIN) {
+ ret = fdt_end_node(abuf_data(buf));
+ if (ret) {
+ log_debug("Internal error b %d\n", ret);
+ return -EFAULT;
+ }
+ }
+ if (ret)
+ return log_msg_ret("end", ret);
+
+ return 0;
+}
+
+int of_live_flatten(const struct device_node *root, struct abuf *buf)
+{
+ int ret;
+
+ abuf_init(buf);
+ if (!abuf_realloc(buf, BUF_STEP))
+ return log_msg_ret("ini", -ENOMEM);
+
+ ret = fdt_create(abuf_data(buf), abuf_size(buf));
+ if (!ret)
+ ret = fdt_finish_reservemap(abuf_data(buf));
+ if (ret) {
+ log_debug("Failed to start FDT (err=%d)\n", ret);
+ return log_msg_ret("sta", -EINVAL);
+ }
+
+ ret = flatten_node(buf, root);
+ if (ret)
+ return log_msg_ret("flt", ret);
+
+ ret = fdt_finish(abuf_data(buf));
+ ret = check_space(ret, buf);
+ if (ret == -EAGAIN) {
+ ret = fdt_finish(abuf_data(buf));
+ if (ret) {
+ log_debug("Internal error c %d\n", ret);
+ return -EFAULT;
+ }
+ }
+ if (ret)
+ return log_msg_ret("fin", ret);
+
+ ret = fdt_pack(abuf_data(buf));
+ if (ret) {
+ log_debug("Failed to pack (err=%d)\n", ret);
+ return log_msg_ret("pac", -EFAULT);
+ }
+
+ if (!abuf_realloc(buf, fdt_totalsize(abuf_data(buf))))
+ return log_msg_ret("abu", -EFAULT);
+
+ return 0;
+}
diff --git a/lib/string.c b/lib/string.c
index ecea755..f2c6147 100644
--- a/lib/string.c
+++ b/lib/string.c
@@ -116,20 +116,18 @@
* of course, the buffer size is zero). It does not pad
* out the result like strncpy() does.
*
- * Return: the number of bytes copied
+ * Return: strlen(src)
*/
size_t strlcpy(char *dest, const char *src, size_t size)
{
- if (size) {
- size_t srclen = strlen(src);
- size_t len = (srclen >= size) ? size - 1 : srclen;
+ size_t ret = strlen(src);
+ if (size) {
+ size_t len = (ret >= size) ? size - 1 : ret;
memcpy(dest, src, len);
dest[len] = '\0';
- return len + 1;
}
-
- return 0;
+ return ret;
}
#endif
@@ -191,6 +189,8 @@
* Compatible with *BSD: the result is always a valid NUL-terminated string that
* fits in the buffer (unless, of course, the buffer size is zero). It does not
* write past @size like strncat() does.
+ *
+ * Return: min(strlen(dest), size) + strlen(src)
*/
size_t strlcat(char *dest, const char *src, size_t size)
{
diff --git a/lib/tpm-v2.c b/lib/tpm-v2.c
index 9ab5b46..bd0fb07 100644
--- a/lib/tpm-v2.c
+++ b/lib/tpm-v2.c
@@ -1,16 +1,705 @@
// SPDX-License-Identifier: GPL-2.0+
/*
+ * Copyright (c) 2023 Linaro Limited
* Copyright (c) 2018 Bootlin
* Author: Miquel Raynal <miquel.raynal@bootlin.com>
*/
#include <common.h>
#include <dm.h>
+#include <dm/of_access.h>
+#include <tpm_api.h>
#include <tpm-common.h>
#include <tpm-v2.h>
+#include <u-boot/sha1.h>
+#include <u-boot/sha256.h>
+#include <u-boot/sha512.h>
+#include <version_string.h>
+#include <asm/io.h>
#include <linux/bitops.h>
+#include <linux/unaligned/be_byteshift.h>
+#include <linux/unaligned/generic.h>
+#include <linux/unaligned/le_byteshift.h>
+
#include "tpm-utils.h"
+const enum tpm2_algorithms tpm2_supported_algorithms[4] = {
+ TPM2_ALG_SHA1,
+ TPM2_ALG_SHA256,
+ TPM2_ALG_SHA384,
+ TPM2_ALG_SHA512,
+};
+
+int tcg2_get_active_pcr_banks(struct udevice *dev, u32 *active_pcr_banks)
+{
+ u32 supported = 0;
+ u32 pcr_banks = 0;
+ u32 active = 0;
+ int rc;
+
+ rc = tpm2_get_pcr_info(dev, &supported, &active, &pcr_banks);
+ if (rc)
+ return rc;
+
+ *active_pcr_banks = active;
+
+ return 0;
+}
+
+u32 tcg2_event_get_size(struct tpml_digest_values *digest_list)
+{
+ u32 len;
+ size_t i;
+
+ len = offsetof(struct tcg_pcr_event2, digests);
+ len += offsetof(struct tpml_digest_values, digests);
+ for (i = 0; i < digest_list->count; ++i) {
+ u16 l = tpm2_algorithm_to_len(digest_list->digests[i].hash_alg);
+
+ if (!l)
+ continue;
+
+ len += l + offsetof(struct tpmt_ha, digest);
+ }
+ len += sizeof(u32);
+
+ return len;
+}
+
+int tcg2_create_digest(struct udevice *dev, const u8 *input, u32 length,
+ struct tpml_digest_values *digest_list)
+{
+ u8 final[sizeof(union tpmu_ha)];
+ sha256_context ctx_256;
+ sha512_context ctx_512;
+ sha1_context ctx;
+ u32 active;
+ size_t i;
+ u32 len;
+ int rc;
+
+ rc = tcg2_get_active_pcr_banks(dev, &active);
+ if (rc)
+ return rc;
+
+ digest_list->count = 0;
+ for (i = 0; i < ARRAY_SIZE(tpm2_supported_algorithms); ++i) {
+ u32 mask =
+ tpm2_algorithm_to_mask(tpm2_supported_algorithms[i]);
+
+ if (!(active & mask))
+ continue;
+
+ switch (tpm2_supported_algorithms[i]) {
+ case TPM2_ALG_SHA1:
+ sha1_starts(&ctx);
+ sha1_update(&ctx, input, length);
+ sha1_finish(&ctx, final);
+ len = TPM2_SHA1_DIGEST_SIZE;
+ break;
+ case TPM2_ALG_SHA256:
+ sha256_starts(&ctx_256);
+ sha256_update(&ctx_256, input, length);
+ sha256_finish(&ctx_256, final);
+ len = TPM2_SHA256_DIGEST_SIZE;
+ break;
+ case TPM2_ALG_SHA384:
+ sha384_starts(&ctx_512);
+ sha384_update(&ctx_512, input, length);
+ sha384_finish(&ctx_512, final);
+ len = TPM2_SHA384_DIGEST_SIZE;
+ break;
+ case TPM2_ALG_SHA512:
+ sha512_starts(&ctx_512);
+ sha512_update(&ctx_512, input, length);
+ sha512_finish(&ctx_512, final);
+ len = TPM2_SHA512_DIGEST_SIZE;
+ break;
+ default:
+ printf("%s: unsupported algorithm %x\n", __func__,
+ tpm2_supported_algorithms[i]);
+ continue;
+ }
+
+ digest_list->digests[digest_list->count].hash_alg =
+ tpm2_supported_algorithms[i];
+ memcpy(&digest_list->digests[digest_list->count].digest, final,
+ len);
+ digest_list->count++;
+ }
+
+ return 0;
+}
+
+void tcg2_log_append(u32 pcr_index, u32 event_type,
+ struct tpml_digest_values *digest_list, u32 size,
+ const u8 *event, u8 *log)
+{
+ size_t len;
+ size_t pos;
+ u32 i;
+
+ pos = offsetof(struct tcg_pcr_event2, pcr_index);
+ put_unaligned_le32(pcr_index, log);
+ pos = offsetof(struct tcg_pcr_event2, event_type);
+ put_unaligned_le32(event_type, log + pos);
+ pos = offsetof(struct tcg_pcr_event2, digests) +
+ offsetof(struct tpml_digest_values, count);
+ put_unaligned_le32(digest_list->count, log + pos);
+
+ pos = offsetof(struct tcg_pcr_event2, digests) +
+ offsetof(struct tpml_digest_values, digests);
+ for (i = 0; i < digest_list->count; ++i) {
+ u16 hash_alg = digest_list->digests[i].hash_alg;
+
+ len = tpm2_algorithm_to_len(hash_alg);
+ if (!len)
+ continue;
+
+ pos += offsetof(struct tpmt_ha, hash_alg);
+ put_unaligned_le16(hash_alg, log + pos);
+ pos += offsetof(struct tpmt_ha, digest);
+ memcpy(log + pos, (u8 *)&digest_list->digests[i].digest, len);
+ pos += len;
+ }
+
+ put_unaligned_le32(size, log + pos);
+ pos += sizeof(u32);
+ memcpy(log + pos, event, size);
+}
+
+static int tcg2_log_append_check(struct tcg2_event_log *elog, u32 pcr_index,
+ u32 event_type,
+ struct tpml_digest_values *digest_list,
+ u32 size, const u8 *event)
+{
+ u32 event_size;
+ u8 *log;
+
+ event_size = size + tcg2_event_get_size(digest_list);
+ if (elog->log_position + event_size > elog->log_size) {
+ printf("%s: log too large: %u + %u > %u\n", __func__,
+ elog->log_position, event_size, elog->log_size);
+ return -ENOBUFS;
+ }
+
+ log = elog->log + elog->log_position;
+ elog->log_position += event_size;
+
+ tcg2_log_append(pcr_index, event_type, digest_list, size, event, log);
+
+ return 0;
+}
+
+static int tcg2_log_init(struct udevice *dev, struct tcg2_event_log *elog)
+{
+ struct tcg_efi_spec_id_event *ev;
+ struct tcg_pcr_event *log;
+ u32 event_size;
+ u32 count = 0;
+ u32 log_size;
+ u32 active;
+ u32 mask;
+ size_t i;
+ u16 len;
+ int rc;
+
+ rc = tcg2_get_active_pcr_banks(dev, &active);
+ if (rc)
+ return rc;
+
+ event_size = offsetof(struct tcg_efi_spec_id_event, digest_sizes);
+ for (i = 0; i < ARRAY_SIZE(tpm2_supported_algorithms); ++i) {
+ mask = tpm2_algorithm_to_mask(tpm2_supported_algorithms[i]);
+
+ if (!(active & mask))
+ continue;
+
+ switch (tpm2_supported_algorithms[i]) {
+ case TPM2_ALG_SHA1:
+ case TPM2_ALG_SHA256:
+ case TPM2_ALG_SHA384:
+ case TPM2_ALG_SHA512:
+ count++;
+ break;
+ default:
+ continue;
+ }
+ }
+
+ event_size += 1 +
+ (sizeof(struct tcg_efi_spec_id_event_algorithm_size) * count);
+ log_size = offsetof(struct tcg_pcr_event, event) + event_size;
+
+ if (log_size > elog->log_size) {
+ printf("%s: log too large: %u > %u\n", __func__, log_size,
+ elog->log_size);
+ return -ENOBUFS;
+ }
+
+ log = (struct tcg_pcr_event *)elog->log;
+ put_unaligned_le32(0, &log->pcr_index);
+ put_unaligned_le32(EV_NO_ACTION, &log->event_type);
+ memset(&log->digest, 0, sizeof(log->digest));
+ put_unaligned_le32(event_size, &log->event_size);
+
+ ev = (struct tcg_efi_spec_id_event *)log->event;
+ strlcpy((char *)ev->signature, TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03,
+ sizeof(ev->signature));
+ put_unaligned_le32(0, &ev->platform_class);
+ ev->spec_version_minor = TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2;
+ ev->spec_version_major = TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2;
+ ev->spec_errata = TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2;
+ ev->uintn_size = sizeof(size_t) / sizeof(u32);
+ put_unaligned_le32(count, &ev->number_of_algorithms);
+
+ count = 0;
+ for (i = 0; i < ARRAY_SIZE(tpm2_supported_algorithms); ++i) {
+ mask = tpm2_algorithm_to_mask(tpm2_supported_algorithms[i]);
+
+ if (!(active & mask))
+ continue;
+
+ len = tpm2_algorithm_to_len(tpm2_supported_algorithms[i]);
+ if (!len)
+ continue;
+
+ put_unaligned_le16(tpm2_supported_algorithms[i],
+ &ev->digest_sizes[count].algorithm_id);
+ put_unaligned_le16(len, &ev->digest_sizes[count].digest_size);
+ count++;
+ }
+
+ *((u8 *)ev + (event_size - 1)) = 0;
+ elog->log_position = log_size;
+
+ return 0;
+}
+
+static int tcg2_replay_eventlog(struct tcg2_event_log *elog,
+ struct udevice *dev,
+ struct tpml_digest_values *digest_list,
+ u32 log_position)
+{
+ const u32 offset = offsetof(struct tcg_pcr_event2, digests) +
+ offsetof(struct tpml_digest_values, digests);
+ u32 event_size;
+ u32 count;
+ u16 algo;
+ u32 pcr;
+ u32 pos;
+ u16 len;
+ u8 *log;
+ int rc;
+ u32 i;
+
+ while (log_position + offset < elog->log_size) {
+ log = elog->log + log_position;
+
+ pos = offsetof(struct tcg_pcr_event2, pcr_index);
+ pcr = get_unaligned_le32(log + pos);
+ pos = offsetof(struct tcg_pcr_event2, event_type);
+ if (!get_unaligned_le32(log + pos))
+ return 0;
+
+ pos = offsetof(struct tcg_pcr_event2, digests) +
+ offsetof(struct tpml_digest_values, count);
+ count = get_unaligned_le32(log + pos);
+ if (count > ARRAY_SIZE(tpm2_supported_algorithms) ||
+ (digest_list->count && digest_list->count != count))
+ return 0;
+
+ pos = offsetof(struct tcg_pcr_event2, digests) +
+ offsetof(struct tpml_digest_values, digests);
+ for (i = 0; i < count; ++i) {
+ pos += offsetof(struct tpmt_ha, hash_alg);
+ if (log_position + pos + sizeof(u16) >= elog->log_size)
+ return 0;
+
+ algo = get_unaligned_le16(log + pos);
+ pos += offsetof(struct tpmt_ha, digest);
+ switch (algo) {
+ case TPM2_ALG_SHA1:
+ case TPM2_ALG_SHA256:
+ case TPM2_ALG_SHA384:
+ case TPM2_ALG_SHA512:
+ len = tpm2_algorithm_to_len(algo);
+ break;
+ default:
+ return 0;
+ }
+
+ if (digest_list->count) {
+ if (algo != digest_list->digests[i].hash_alg ||
+ log_position + pos + len >= elog->log_size)
+ return 0;
+
+ memcpy(digest_list->digests[i].digest.sha512,
+ log + pos, len);
+ }
+
+ pos += len;
+ }
+
+ if (log_position + pos + sizeof(u32) >= elog->log_size)
+ return 0;
+
+ event_size = get_unaligned_le32(log + pos);
+ pos += event_size + sizeof(u32);
+ if (log_position + pos > elog->log_size)
+ return 0;
+
+ if (digest_list->count) {
+ rc = tcg2_pcr_extend(dev, pcr, digest_list);
+ if (rc)
+ return rc;
+ }
+
+ log_position += pos;
+ }
+
+ elog->log_position = log_position;
+ elog->found = true;
+ return 0;
+}
+
+static int tcg2_log_parse(struct udevice *dev, struct tcg2_event_log *elog)
+{
+ struct tpml_digest_values digest_list;
+ struct tcg_efi_spec_id_event *event;
+ struct tcg_pcr_event *log;
+ u32 log_active;
+ u32 calc_size;
+ u32 active;
+ u32 count;
+ u32 evsz;
+ u32 mask;
+ u16 algo;
+ u16 len;
+ int rc;
+ u32 i;
+ u16 j;
+
+ if (elog->log_size <= offsetof(struct tcg_pcr_event, event))
+ return 0;
+
+ log = (struct tcg_pcr_event *)elog->log;
+ if (get_unaligned_le32(&log->pcr_index) != 0 ||
+ get_unaligned_le32(&log->event_type) != EV_NO_ACTION)
+ return 0;
+
+ for (i = 0; i < sizeof(log->digest); i++) {
+ if (log->digest[i])
+ return 0;
+ }
+
+ evsz = get_unaligned_le32(&log->event_size);
+ if (evsz < offsetof(struct tcg_efi_spec_id_event, digest_sizes) ||
+ evsz + offsetof(struct tcg_pcr_event, event) > elog->log_size)
+ return 0;
+
+ event = (struct tcg_efi_spec_id_event *)log->event;
+ if (memcmp(event->signature, TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03,
+ sizeof(TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03)))
+ return 0;
+
+ if (event->spec_version_minor != TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2 ||
+ event->spec_version_major != TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2)
+ return 0;
+
+ count = get_unaligned_le32(&event->number_of_algorithms);
+ if (count > ARRAY_SIZE(tpm2_supported_algorithms))
+ return 0;
+
+ calc_size = offsetof(struct tcg_efi_spec_id_event, digest_sizes) +
+ (sizeof(struct tcg_efi_spec_id_event_algorithm_size) * count) +
+ 1;
+ if (evsz != calc_size)
+ return 0;
+
+ rc = tcg2_get_active_pcr_banks(dev, &active);
+ if (rc)
+ return rc;
+
+ digest_list.count = 0;
+ log_active = 0;
+
+ for (i = 0; i < count; ++i) {
+ algo = get_unaligned_le16(&event->digest_sizes[i].algorithm_id);
+ mask = tpm2_algorithm_to_mask(algo);
+
+ if (!(active & mask))
+ return 0;
+
+ switch (algo) {
+ case TPM2_ALG_SHA1:
+ case TPM2_ALG_SHA256:
+ case TPM2_ALG_SHA384:
+ case TPM2_ALG_SHA512:
+ len = get_unaligned_le16(&event->digest_sizes[i].digest_size);
+ if (tpm2_algorithm_to_len(algo) != len)
+ return 0;
+ digest_list.digests[digest_list.count++].hash_alg = algo;
+ break;
+ default:
+ return 0;
+ }
+
+ log_active |= mask;
+ }
+
+ /* Ensure the previous firmware extended all the PCRs. */
+ if (log_active != active)
+ return 0;
+
+ /* Read PCR0 to check if previous firmware extended the PCRs or not. */
+ rc = tcg2_pcr_read(dev, 0, &digest_list);
+ if (rc)
+ return rc;
+
+ for (i = 0; i < digest_list.count; ++i) {
+ len = tpm2_algorithm_to_len(digest_list.digests[i].hash_alg);
+ for (j = 0; j < len; ++j) {
+ if (digest_list.digests[i].digest.sha512[j])
+ break;
+ }
+
+ /* PCR is non-zero; it has been extended, so skip extending. */
+ if (j != len) {
+ digest_list.count = 0;
+ break;
+ }
+ }
+
+ return tcg2_replay_eventlog(elog, dev, &digest_list,
+ offsetof(struct tcg_pcr_event, event) +
+ evsz);
+}
+
+int tcg2_pcr_extend(struct udevice *dev, u32 pcr_index,
+ struct tpml_digest_values *digest_list)
+{
+ u32 rc;
+ u32 i;
+
+ for (i = 0; i < digest_list->count; i++) {
+ u32 alg = digest_list->digests[i].hash_alg;
+
+ rc = tpm2_pcr_extend(dev, pcr_index, alg,
+ (u8 *)&digest_list->digests[i].digest,
+ tpm2_algorithm_to_len(alg));
+ if (rc) {
+ printf("%s: error pcr:%u alg:%08x\n", __func__,
+ pcr_index, alg);
+ return rc;
+ }
+ }
+
+ return 0;
+}
+
+int tcg2_pcr_read(struct udevice *dev, u32 pcr_index,
+ struct tpml_digest_values *digest_list)
+{
+ struct tpm_chip_priv *priv;
+ u32 rc;
+ u32 i;
+
+ priv = dev_get_uclass_priv(dev);
+ if (!priv)
+ return -ENODEV;
+
+ for (i = 0; i < digest_list->count; i++) {
+ u32 alg = digest_list->digests[i].hash_alg;
+ u8 *digest = (u8 *)&digest_list->digests[i].digest;
+
+ rc = tpm2_pcr_read(dev, pcr_index, priv->pcr_select_min, alg,
+ digest, tpm2_algorithm_to_len(alg), NULL);
+ if (rc) {
+ printf("%s: error pcr:%u alg:%08x\n", __func__,
+ pcr_index, alg);
+ return rc;
+ }
+ }
+
+ return 0;
+}
+
+int tcg2_measure_data(struct udevice *dev, struct tcg2_event_log *elog,
+ u32 pcr_index, u32 size, const u8 *data, u32 event_type,
+ u32 event_size, const u8 *event)
+{
+ struct tpml_digest_values digest_list;
+ int rc;
+
+ if (data)
+ rc = tcg2_create_digest(dev, data, size, &digest_list);
+ else
+ rc = tcg2_create_digest(dev, event, event_size, &digest_list);
+ if (rc)
+ return rc;
+
+ rc = tcg2_pcr_extend(dev, pcr_index, &digest_list);
+ if (rc)
+ return rc;
+
+ return tcg2_log_append_check(elog, pcr_index, event_type, &digest_list,
+ event_size, event);
+}
+
+int tcg2_log_prepare_buffer(struct udevice *dev, struct tcg2_event_log *elog,
+ bool ignore_existing_log)
+{
+ struct tcg2_event_log log;
+ int rc;
+
+ elog->log_position = 0;
+ elog->found = false;
+
+ rc = tcg2_platform_get_log(dev, (void **)&log.log, &log.log_size);
+ if (!rc) {
+ log.log_position = 0;
+ log.found = false;
+
+ if (!ignore_existing_log) {
+ rc = tcg2_log_parse(dev, &log);
+ if (rc)
+ return rc;
+ }
+
+ if (elog->log_size) {
+ if (log.found) {
+ if (elog->log_size < log.log_position)
+ return -ENOSPC;
+
+ /*
+ * Copy the discovered log into the user buffer
+ * if there's enough space.
+ */
+ memcpy(elog->log, log.log, log.log_position);
+ }
+
+ unmap_physmem(log.log, MAP_NOCACHE);
+ } else {
+ elog->log = log.log;
+ elog->log_size = log.log_size;
+ }
+
+ elog->log_position = log.log_position;
+ elog->found = log.found;
+ }
+
+ /*
+ * Initialize the log buffer if no log was discovered and the buffer is
+ * valid. User's can pass in their own buffer as a fallback if no
+ * memory region is found.
+ */
+ if (!elog->found && elog->log_size)
+ rc = tcg2_log_init(dev, elog);
+
+ return rc;
+}
+
+int tcg2_measurement_init(struct udevice **dev, struct tcg2_event_log *elog,
+ bool ignore_existing_log)
+{
+ int rc;
+
+ rc = tcg2_platform_get_tpm2(dev);
+ if (rc)
+ return rc;
+
+ rc = tpm_auto_start(*dev);
+ if (rc)
+ return rc;
+
+ rc = tcg2_log_prepare_buffer(*dev, elog, ignore_existing_log);
+ if (rc) {
+ tcg2_measurement_term(*dev, elog, true);
+ return rc;
+ }
+
+ rc = tcg2_measure_event(*dev, elog, 0, EV_S_CRTM_VERSION,
+ strlen(version_string) + 1,
+ (u8 *)version_string);
+ if (rc) {
+ tcg2_measurement_term(*dev, elog, true);
+ return rc;
+ }
+
+ return 0;
+}
+
+void tcg2_measurement_term(struct udevice *dev, struct tcg2_event_log *elog,
+ bool error)
+{
+ u32 event = error ? 0x1 : 0xffffffff;
+ int i;
+
+ for (i = 0; i < 8; ++i)
+ tcg2_measure_event(dev, elog, i, EV_SEPARATOR, sizeof(event),
+ (const u8 *)&event);
+
+ if (elog->log)
+ unmap_physmem(elog->log, MAP_NOCACHE);
+}
+
+__weak int tcg2_platform_get_log(struct udevice *dev, void **addr, u32 *size)
+{
+ const __be32 *addr_prop;
+ const __be32 *size_prop;
+ int asize;
+ int ssize;
+
+ *addr = NULL;
+ *size = 0;
+
+ addr_prop = dev_read_prop(dev, "tpm_event_log_addr", &asize);
+ if (!addr_prop)
+ addr_prop = dev_read_prop(dev, "linux,sml-base", &asize);
+
+ size_prop = dev_read_prop(dev, "tpm_event_log_size", &ssize);
+ if (!size_prop)
+ size_prop = dev_read_prop(dev, "linux,sml-size", &ssize);
+
+ if (addr_prop && size_prop) {
+ u64 a = of_read_number(addr_prop, asize / sizeof(__be32));
+ u64 s = of_read_number(size_prop, ssize / sizeof(__be32));
+
+ *addr = map_physmem(a, s, MAP_NOCACHE);
+ *size = (u32)s;
+ } else {
+ struct ofnode_phandle_args args;
+ phys_addr_t a;
+ fdt_size_t s;
+
+ if (dev_read_phandle_with_args(dev, "memory-region", NULL, 0,
+ 0, &args))
+ return -ENODEV;
+
+ a = ofnode_get_addr_size(args.node, "reg", &s);
+ if (a == FDT_ADDR_T_NONE)
+ return -ENOMEM;
+
+ *addr = map_physmem(a, s, MAP_NOCACHE);
+ *size = (u32)s;
+ }
+
+ return 0;
+}
+
+__weak int tcg2_platform_get_tpm2(struct udevice **dev)
+{
+ for_each_tpm_device(*dev) {
+ if (tpm_get_version(*dev) == TPM_V2)
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
+__weak void tcg2_platform_startup_error(struct udevice *dev, int rc) {}
+
u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode)
{
const u8 command_v2[12] = {
@@ -359,6 +1048,131 @@
return 0;
}
+static int tpm2_get_num_pcr(struct udevice *dev, u32 *num_pcr)
+{
+ u8 response[(sizeof(struct tpms_capability_data) -
+ offsetof(struct tpms_capability_data, data))];
+ u32 properties_offset =
+ offsetof(struct tpml_tagged_tpm_property, tpm_property) +
+ offsetof(struct tpms_tagged_property, value);
+ u32 ret;
+
+ memset(response, 0, sizeof(response));
+ ret = tpm2_get_capability(dev, TPM2_CAP_TPM_PROPERTIES,
+ TPM2_PT_PCR_COUNT, response, 1);
+ if (ret)
+ return ret;
+
+ *num_pcr = get_unaligned_be32(response + properties_offset);
+ if (*num_pcr > TPM2_MAX_PCRS) {
+ printf("%s: too many pcrs: %u\n", __func__, *num_pcr);
+ return -E2BIG;
+ }
+
+ return 0;
+}
+
+static bool tpm2_is_active_pcr(struct tpms_pcr_selection *selection)
+{
+ int i;
+
+ /*
+ * check the pcr_select. If at least one of the PCRs supports the
+ * algorithm add it on the active ones
+ */
+ for (i = 0; i < selection->size_of_select; i++) {
+ if (selection->pcr_select[i])
+ return true;
+ }
+
+ return false;
+}
+
+int tpm2_get_pcr_info(struct udevice *dev, u32 *supported_pcr, u32 *active_pcr,
+ u32 *pcr_banks)
+{
+ u8 response[(sizeof(struct tpms_capability_data) -
+ offsetof(struct tpms_capability_data, data))];
+ struct tpml_pcr_selection pcrs;
+ u32 num_pcr;
+ size_t i;
+ u32 ret;
+
+ *supported_pcr = 0;
+ *active_pcr = 0;
+ *pcr_banks = 0;
+ memset(response, 0, sizeof(response));
+ ret = tpm2_get_capability(dev, TPM2_CAP_PCRS, 0, response, 1);
+ if (ret)
+ return ret;
+
+ pcrs.count = get_unaligned_be32(response);
+ /*
+ * We only support 5 algorithms for now so check against that
+ * instead of TPM2_NUM_PCR_BANKS
+ */
+ if (pcrs.count > ARRAY_SIZE(tpm2_supported_algorithms) ||
+ pcrs.count < 1) {
+ printf("%s: too many pcrs: %u\n", __func__, pcrs.count);
+ return -EMSGSIZE;
+ }
+
+ ret = tpm2_get_num_pcr(dev, &num_pcr);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < pcrs.count; i++) {
+ /*
+ * Definition of TPMS_PCR_SELECTION Structure
+ * hash: u16
+ * size_of_select: u8
+ * pcr_select: u8 array
+ *
+ * The offsets depend on the number of the device PCRs
+ * so we have to calculate them based on that
+ */
+ u32 hash_offset = offsetof(struct tpml_pcr_selection, selection) +
+ i * offsetof(struct tpms_pcr_selection, pcr_select) +
+ i * ((num_pcr + 7) / 8);
+ u32 size_select_offset =
+ hash_offset + offsetof(struct tpms_pcr_selection,
+ size_of_select);
+ u32 pcr_select_offset =
+ hash_offset + offsetof(struct tpms_pcr_selection,
+ pcr_select);
+
+ pcrs.selection[i].hash =
+ get_unaligned_be16(response + hash_offset);
+ pcrs.selection[i].size_of_select =
+ __get_unaligned_be(response + size_select_offset);
+ if (pcrs.selection[i].size_of_select > TPM2_PCR_SELECT_MAX) {
+ printf("%s: pcrs selection too large: %u\n", __func__,
+ pcrs.selection[i].size_of_select);
+ return -ENOBUFS;
+ }
+ /* copy the array of pcr_select */
+ memcpy(pcrs.selection[i].pcr_select, response + pcr_select_offset,
+ pcrs.selection[i].size_of_select);
+ }
+
+ for (i = 0; i < pcrs.count; i++) {
+ u32 hash_mask = tpm2_algorithm_to_mask(pcrs.selection[i].hash);
+
+ if (hash_mask) {
+ *supported_pcr |= hash_mask;
+ if (tpm2_is_active_pcr(&pcrs.selection[i]))
+ *active_pcr |= hash_mask;
+ } else {
+ printf("%s: unknown algorithm %x\n", __func__,
+ pcrs.selection[i].hash);
+ }
+ }
+
+ *pcr_banks = pcrs.count;
+
+ return 0;
+}
+
u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz)
{
u8 command_v2[COMMAND_BUFFER_SIZE] = {
diff --git a/lib/trace.c b/lib/trace.c
index 1091a57..4874bef 100644
--- a/lib/trace.c
+++ b/lib/trace.c
@@ -51,7 +51,7 @@
uintptr_t offset = (uintptr_t)func_ptr;
#ifdef CONFIG_SANDBOX
- offset -= (uintptr_t)&_init;
+ offset -= (uintptr_t)_init;
#else
if (gd->flags & GD_FLG_RELOC)
offset -= gd->relocaddr;
diff --git a/lib/uuid.c b/lib/uuid.c
index d018700..afb40bf 100644
--- a/lib/uuid.c
+++ b/lib/uuid.c
@@ -7,6 +7,8 @@
* Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
*/
+#define LOG_CATEGOT LOGC_CORE
+
#include <common.h>
#include <command.h>
#include <efi_api.h>
@@ -23,50 +25,6 @@
#include <dm/uclass.h>
#include <rng.h>
-/*
- * UUID - Universally Unique IDentifier - 128 bits unique number.
- * There are 5 versions and one variant of UUID defined by RFC4122
- * specification. A UUID contains a set of fields. The set varies
- * depending on the version of the UUID, as shown below:
- * - time, MAC address(v1),
- * - user ID(v2),
- * - MD5 of name or URL(v3),
- * - random data(v4),
- * - SHA-1 of name or URL(v5),
- *
- * Layout of UUID:
- * timestamp - 60-bit: time_low, time_mid, time_hi_and_version
- * version - 4 bit (bit 4 through 7 of the time_hi_and_version)
- * clock seq - 14 bit: clock_seq_hi_and_reserved, clock_seq_low
- * variant: - bit 6 and 7 of clock_seq_hi_and_reserved
- * node - 48 bit
- *
- * source: https://www.ietf.org/rfc/rfc4122.txt
- *
- * UUID binary format (16 bytes):
- *
- * 4B-2B-2B-2B-6B (big endian - network byte order)
- *
- * UUID string is 36 length of characters (36 bytes):
- *
- * 0 9 14 19 24
- * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
- * be be be be be
- *
- * where x is a hexadecimal character. Fields are separated by '-'s.
- * When converting to a binary UUID, le means the field should be converted
- * to little endian and be means it should be converted to big endian.
- *
- * UUID is also used as GUID (Globally Unique Identifier) with the same binary
- * format but it differs in string format like below.
- *
- * GUID:
- * 0 9 14 19 24
- * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
- * le le le be be
- *
- * GUID is used e.g. in GPT (GUID Partition Table) as a partiions unique id.
- */
int uuid_str_valid(const char *uuid)
{
int i, valid;
@@ -105,6 +63,10 @@
{"swap", PARTITION_LINUX_SWAP_GUID},
{"lvm", PARTITION_LINUX_LVM_GUID},
{"u-boot-env", PARTITION_U_BOOT_ENVIRONMENT},
+ {"cros-kern", PARTITION_CROS_KERNEL},
+ {"cros-root", PARTITION_CROS_ROOT},
+ {"cros-fw", PARTITION_CROS_FIRMWARE},
+ {"cros-rsrv", PARTITION_CROS_RESERVED},
#endif
#if defined(CONFIG_CMD_EFIDEBUG) || defined(CONFIG_EFI)
{
@@ -269,12 +231,6 @@
#endif
};
-/*
- * uuid_guid_get_bin() - this function get GUID bin for string
- *
- * @param guid_str - pointer to partition type string
- * @param guid_bin - pointer to allocated array for big endian output [16B]
- */
int uuid_guid_get_bin(const char *guid_str, unsigned char *guid_bin)
{
int i;
@@ -288,13 +244,6 @@
return -ENODEV;
}
-/*
- * uuid_guid_get_str() - this function get string for GUID.
- *
- * @param guid_bin - pointer to string with partition type guid [16B]
- *
- * Returns NULL if the type GUID is not known.
- */
const char *uuid_guid_get_str(const unsigned char *guid_bin)
{
int i;
@@ -307,13 +256,6 @@
return NULL;
}
-/*
- * uuid_str_to_bin() - convert string UUID or GUID to big endian binary data.
- *
- * @param uuid_str - pointer to UUID or GUID string [37B] or GUID shorcut
- * @param uuid_bin - pointer to allocated array for big endian output [16B]
- * @str_format - UUID string format: 0 - UUID; 1 - GUID
- */
int uuid_str_to_bin(const char *uuid_str, unsigned char *uuid_bin,
int str_format)
{
@@ -322,6 +264,7 @@
uint64_t tmp64;
if (!uuid_str_valid(uuid_str)) {
+ log_debug("not valid\n");
#ifdef CONFIG_PARTITION_TYPE_GUID
if (!uuid_guid_get_bin(uuid_str, uuid_bin))
return 0;
@@ -358,23 +301,6 @@
return 0;
}
-/**
- * uuid_str_to_le_bin() - Convert string UUID to little endian binary data.
- * @uuid_str: pointer to UUID string
- * @uuid_bin: pointer to allocated array for little endian output [16B]
- *
- * UUID string is 36 characters (36 bytes):
- *
- * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
- *
- * where x is a hexadecimal character. Fields are separated by '-'s.
- * When converting to a little endian binary UUID, the string fields are reversed.
- *
- * Return:
- *
- * uuid_bin filled with little endian UUID data
- * On success 0 is returned. Otherwise, failure code.
- */
int uuid_str_to_le_bin(const char *uuid_str, unsigned char *uuid_bin)
{
u16 tmp16;
@@ -402,14 +328,6 @@
return 0;
}
-/*
- * uuid_bin_to_str() - convert big endian binary data to string UUID or GUID.
- *
- * @param uuid_bin: pointer to binary data of UUID (big endian) [16B]
- * @param uuid_str: pointer to allocated array for output string [37B]
- * @str_format: bit 0: 0 - UUID; 1 - GUID
- * bit 1: 0 - lower case; 2 - upper case
- */
void uuid_bin_to_str(const unsigned char *uuid_bin, char *uuid_str,
int str_format)
{
@@ -449,13 +367,6 @@
}
}
-/*
- * gen_rand_uuid() - this function generates a random binary UUID version 4.
- * In this version all fields beside 4 bits of version and
- * 2 bits of variant are randomly generated.
- *
- * @param uuid_bin - pointer to allocated array [16B]. Output is in big endian.
-*/
#if defined(CONFIG_RANDOM_UUID) || defined(CONFIG_CMD_UUID)
void gen_rand_uuid(unsigned char *uuid_bin)
{
@@ -493,13 +404,6 @@
memcpy(uuid_bin, uuid, 16);
}
-/*
- * gen_rand_uuid_str() - this function generates UUID v4 (random) in two string
- * formats UUID or GUID.
- *
- * @param uuid_str - pointer to allocated array [37B].
- * @param - uuid output type: UUID - 0, GUID - 1
- */
void gen_rand_uuid_str(char *uuid_str, int str_format)
{
unsigned char uuid_bin[UUID_BIN_LEN];
diff --git a/net/Kconfig b/net/Kconfig
index 4215889..92a22ac 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -57,7 +57,7 @@
bool "NetConsole support"
help
Support the 'nc' input/output device for networked console.
- See README.NetConsole for details.
+ See doc/usage/netconsole.rst for details.
config IP_DEFRAG
bool "Support IP datagram reassembly"
diff --git a/net/Makefile b/net/Makefile
index 002b0f6..bba9fae 100644
--- a/net/Makefile
+++ b/net/Makefile
@@ -27,8 +27,8 @@
obj-$(CONFIG_CMD_RARP) += rarp.o
obj-$(CONFIG_CMD_SNTP) += sntp.o
obj-$(CONFIG_CMD_TFTPBOOT) += tftp.o
-obj-$(CONFIG_UDP_FUNCTION_FASTBOOT) += fastboot_udp.o
-obj-$(CONFIG_TCP_FUNCTION_FASTBOOT) += fastboot_tcp.o
+obj-$(CONFIG_$(SPL_TPL_)UDP_FUNCTION_FASTBOOT) += fastboot_udp.o
+obj-$(CONFIG_$(SPL_TPL_)TCP_FUNCTION_FASTBOOT) += fastboot_tcp.o
obj-$(CONFIG_CMD_WOL) += wol.o
obj-$(CONFIG_PROT_UDP) += udp.o
obj-$(CONFIG_PROT_TCP) += tcp.o
diff --git a/net/bootp.c b/net/bootp.c
index 8b1a4ae..6800290 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -26,6 +26,7 @@
#ifdef CONFIG_BOOTP_RANDOM_DELAY
#include "net_rand.h"
#endif
+#include <malloc.h>
#define BOOTP_VENDOR_MAGIC 0x63825363 /* RFC1048 Magic Cookie */
@@ -41,9 +42,6 @@
*/
#define TIMEOUT_MS ((3 + (CONFIG_NET_RETRY_COUNT * 5)) * 1000)
-#define PORT_BOOTPS 67 /* BOOTP server UDP port */
-#define PORT_BOOTPC 68 /* BOOTP client UDP port */
-
#ifndef CFG_DHCP_MIN_EXT_LEN /* minimal length of extension list */
#define CFG_DHCP_MIN_EXT_LEN 64
#endif
@@ -604,6 +602,10 @@
*e++ = 42;
*cnt += 1;
#endif
+ if (IS_ENABLED(CONFIG_BOOTP_PXE_DHCP_OPTION)) {
+ *e++ = 209; /* PXELINUX Config File */
+ *cnt += 1;
+ }
/* no options, so back up to avoid sending an empty request list */
if (*cnt == 0)
e -= 2;
@@ -912,6 +914,22 @@
net_boot_file_name[size] = 0;
}
break;
+ case 209: /* PXELINUX Config File */
+ if (IS_ENABLED(CONFIG_BOOTP_PXE_DHCP_OPTION)) {
+ /* In case it has already been allocated when get DHCP Offer packet,
+ * free first to avoid memory leak.
+ */
+ if (pxelinux_configfile)
+ free(pxelinux_configfile);
+
+ pxelinux_configfile = (char *)malloc((oplen + 1) * sizeof(char));
+
+ if (pxelinux_configfile)
+ strlcpy(pxelinux_configfile, popt + 2, oplen + 1);
+ else
+ printf("Error: Failed to allocate pxelinux_configfile\n");
+ }
+ break;
default:
#if defined(CONFIG_BOOTP_VENDOREX)
if (dhcp_vendorex_proc(popt))
@@ -1076,6 +1094,11 @@
CONFIG_SYS_BOOTFILE_PREFIX,
strlen(CONFIG_SYS_BOOTFILE_PREFIX)) == 0) {
#endif /* CONFIG_SYS_BOOTFILE_PREFIX */
+ if (CONFIG_IS_ENABLED(UNIT_TEST) &&
+ dhcp_message_type((u8 *)bp->bp_vend) == -1) {
+ debug("got BOOTP response; transitioning to BOUND\n");
+ goto dhcp_got_bootp;
+ }
dhcp_packet_process_options(bp);
if (CONFIG_IS_ENABLED(EFI_LOADER) &&
IS_ENABLED(CONFIG_NETDEVICES))
@@ -1102,6 +1125,7 @@
debug("DHCP State: REQUESTING\n");
if (dhcp_message_type((u8 *)bp->bp_vend) == DHCP_ACK) {
+dhcp_got_bootp:
dhcp_packet_process_options(bp);
/* Store net params from reply */
store_net_params(bp);
diff --git a/net/bootp.h b/net/bootp.h
index 567340e..4e32b19 100644
--- a/net/bootp.h
+++ b/net/bootp.h
@@ -15,6 +15,9 @@
/**********************************************************************/
+#define PORT_BOOTPS 67 /* BOOTP server UDP port */
+#define PORT_BOOTPC 68 /* BOOTP client UDP port */
+
/*
* BOOTP header.
*/
diff --git a/net/dhcpv6.c b/net/dhcpv6.c
index 73a1067..4aea779 100644
--- a/net/dhcpv6.c
+++ b/net/dhcpv6.c
@@ -304,7 +304,7 @@
static void dhcp6_parse_options(uchar *rx_pkt, unsigned int len)
{
uchar *option_ptr;
- int sol_max_rt_sec, option_len;
+ int sol_max_rt_sec, option_len, param_len_1;
char *s, *e;
struct dhcp6_option_hdr *option_hdr;
@@ -390,14 +390,23 @@
case DHCP6_OPTION_OPT_BOOTFILE_PARAM:
if (IS_ENABLED(CONFIG_DHCP6_PXE_DHCP_OPTION)) {
debug("DHCP6_OPTION_OPT_BOOTFILE_PARAM FOUND\n");
+ /* if CONFIG_DHCP6_PXE_DHCP_OPTION is set the PXE config file path
+ * is contained in the first OPT_BOOTFILE_PARAM argument
+ */
+ param_len_1 = ntohs(*((u16 *)option_ptr));
+ option_ptr += sizeof(u16);
+ if (param_len_1 + sizeof(u16) > option_len) {
+ debug("Invalid BOOTFILE_PARAM param_len_1. Skipping\n");
+ break;
+ }
if (pxelinux_configfile)
free(pxelinux_configfile);
- pxelinux_configfile = (char *)malloc((option_len + 1) *
+ pxelinux_configfile = (char *)malloc((param_len_1 + 1) *
sizeof(char));
if (pxelinux_configfile)
- strlcpy(pxelinux_configfile, option_ptr, option_len + 1);
+ strlcpy(pxelinux_configfile, option_ptr, param_len_1 + 1);
else
printf("Error: Failed to allocate pxelinux_configfile\n");
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index c393600..3d0ec91 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -556,42 +556,20 @@
unsigned char env_enetaddr[ARP_HLEN];
char *source = "DT";
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- struct eth_ops *ops = eth_get_ops(dev);
- static int reloc_done;
-
- if (!reloc_done) {
- if (ops->start)
- ops->start += gd->reloc_off;
- if (ops->send)
- ops->send += gd->reloc_off;
- if (ops->recv)
- ops->recv += gd->reloc_off;
- if (ops->free_pkt)
- ops->free_pkt += gd->reloc_off;
- if (ops->stop)
- ops->stop += gd->reloc_off;
- if (ops->mcast)
- ops->mcast += gd->reloc_off;
- if (ops->write_hwaddr)
- ops->write_hwaddr += gd->reloc_off;
- if (ops->read_rom_hwaddr)
- ops->read_rom_hwaddr += gd->reloc_off;
-
- reloc_done++;
- }
-#endif
-
priv->state = ETH_STATE_INIT;
priv->running = false;
/* Check if the device has a valid MAC address in device tree */
if (!eth_dev_get_mac_address(dev, pdata->enetaddr) ||
!is_valid_ethaddr(pdata->enetaddr)) {
- source = "ROM";
/* Check if the device has a MAC address in ROM */
- if (eth_get_ops(dev)->read_rom_hwaddr)
- eth_get_ops(dev)->read_rom_hwaddr(dev);
+ if (eth_get_ops(dev)->read_rom_hwaddr) {
+ int ret;
+
+ ret = eth_get_ops(dev)->read_rom_hwaddr(dev);
+ if (!ret)
+ source = "ROM";
+ }
}
eth_env_get_enetaddr_by_index("eth", dev_seq(dev), env_enetaddr);
@@ -620,7 +598,7 @@
eth_env_set_enetaddr_by_index("eth", dev_seq(dev),
pdata->enetaddr);
#else
- printf("\nError: %s address not set.\n",
+ printf("\nError: %s No valid MAC address found.\n",
dev->name);
return -EINVAL;
#endif
diff --git a/net/eth_common.c b/net/eth_common.c
index c94a7ba..14d4c07 100644
--- a/net/eth_common.c
+++ b/net/eth_common.c
@@ -36,10 +36,6 @@
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
miiphy_init();
#endif
-
-#if defined(CONFIG_NEEDS_MANUAL_RELOC) && defined(CONFIG_PHYLIB)
- phy_init();
-#endif
#endif
}
diff --git a/net/fastboot_udp.c b/net/fastboot_udp.c
index d706928..d690787 100644
--- a/net/fastboot_udp.c
+++ b/net/fastboot_udp.c
@@ -8,6 +8,7 @@
#include <fastboot.h>
#include <net.h>
#include <net/fastboot_udp.h>
+#include <linux/printk.h>
enum {
FASTBOOT_ERROR = 0,
diff --git a/net/net.c b/net/net.c
index b483ec2..1a5bdaf 100644
--- a/net/net.c
+++ b/net/net.c
@@ -515,12 +515,12 @@
tftp_start_server();
break;
#endif
-#if defined(CONFIG_UDP_FUNCTION_FASTBOOT)
+#if CONFIG_IS_ENABLED(UDP_FUNCTION_FASTBOOT)
case FASTBOOT_UDP:
fastboot_udp_start_server();
break;
#endif
-#if defined(CONFIG_TCP_FUNCTION_FASTBOOT)
+#if CONFIG_IS_ENABLED(TCP_FUNCTION_FASTBOOT)
case FASTBOOT_TCP:
fastboot_tcp_start_server();
break;
@@ -720,7 +720,7 @@
case NETLOOP_SUCCESS:
net_cleanup_loop();
if (net_boot_file_size > 0) {
- printf("Bytes transferred = %d (%x hex)\n",
+ printf("Bytes transferred = %u (%x hex)\n",
net_boot_file_size, net_boot_file_size);
env_set_hex("filesize", net_boot_file_size);
env_set_hex("fileaddr", image_load_addr);
@@ -1213,6 +1213,9 @@
ushort cti = 0, vlanid = VLAN_NONE, myvlanid, mynvlanid;
debug_cond(DEBUG_NET_PKT, "packet received\n");
+ if (DEBUG_NET_PKT_TRACE)
+ print_hex_dump_bytes("rx: ", DUMP_PREFIX_OFFSET, in_packet,
+ len);
#if defined(CONFIG_CMD_PCAP)
pcap_post(in_packet, len, false);
diff --git a/net/wget.c b/net/wget.c
index 8bb4d72..e1e580c 100644
--- a/net/wget.c
+++ b/net/wget.c
@@ -14,6 +14,9 @@
#include <net/tcp.h>
#include <net/wget.h>
+/* The default, change with environment variable 'httpdstp' */
+#define SERVER_PORT 80
+
static const char bootfile1[] = "GET ";
static const char bootfile3[] = " HTTP/1.0\r\n\r\n";
static const char http_eom[] = "\r\n\r\n";
@@ -91,19 +94,22 @@
int len = retry_len;
unsigned int tcp_ack_num = retry_tcp_seq_num + (len == 0 ? 1 : len);
unsigned int tcp_seq_num = retry_tcp_ack_num;
+ unsigned int server_port;
uchar *ptr, *offset;
+ server_port = env_get_ulong("httpdstp", 10, SERVER_PORT) & 0xffff;
+
switch (current_wget_state) {
case WGET_CLOSED:
debug_cond(DEBUG_WGET, "wget: send SYN\n");
current_wget_state = WGET_CONNECTING;
- net_send_tcp_packet(0, SERVER_PORT, our_port, action,
+ net_send_tcp_packet(0, server_port, our_port, action,
tcp_seq_num, tcp_ack_num);
packets = 0;
break;
case WGET_CONNECTING:
pkt_q_idx = 0;
- net_send_tcp_packet(0, SERVER_PORT, our_port, action,
+ net_send_tcp_packet(0, server_port, our_port, action,
tcp_seq_num, tcp_ack_num);
ptr = net_tx_packet + net_eth_hdr_size() +
@@ -118,14 +124,14 @@
memcpy(offset, &bootfile3, strlen(bootfile3));
offset += strlen(bootfile3);
- net_send_tcp_packet((offset - ptr), SERVER_PORT, our_port,
+ net_send_tcp_packet((offset - ptr), server_port, our_port,
TCP_PUSH, tcp_seq_num, tcp_ack_num);
current_wget_state = WGET_CONNECTED;
break;
case WGET_CONNECTED:
case WGET_TRANSFERRING:
case WGET_TRANSFERRED:
- net_send_tcp_packet(0, SERVER_PORT, our_port, action,
+ net_send_tcp_packet(0, server_port, our_port, action,
tcp_seq_num, tcp_ack_num);
break;
}
diff --git a/post/post.c b/post/post.c
index 4db862c..946d909 100644
--- a/post/post.c
+++ b/post/post.c
@@ -416,54 +416,6 @@
return 0;
}
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
-void post_reloc(void)
-{
- unsigned int i;
-
- /*
- * We have to relocate the test table manually
- */
- for (i = 0; i < post_list_size; i++) {
- ulong addr;
- struct post_test *test = post_list + i;
-
- if (test->name) {
- addr = (ulong)(test->name) + gd->reloc_off;
- test->name = (char *)addr;
- }
-
- if (test->cmd) {
- addr = (ulong)(test->cmd) + gd->reloc_off;
- test->cmd = (char *)addr;
- }
-
- if (test->desc) {
- addr = (ulong)(test->desc) + gd->reloc_off;
- test->desc = (char *)addr;
- }
-
- if (test->test) {
- addr = (ulong)(test->test) + gd->reloc_off;
- test->test = (int (*)(int flags)) addr;
- }
-
- if (test->init_f) {
- addr = (ulong)(test->init_f) + gd->reloc_off;
- test->init_f = (int (*)(void)) addr;
- }
-
- if (test->reloc) {
- addr = (ulong)(test->reloc) + gd->reloc_off;
- test->reloc = (void (*)(void)) addr;
-
- test->reloc();
- }
- }
-}
-#endif
-
-
/*
* Some tests (e.g. SYSMON) need the time when post_init_f started,
* but we cannot use get_timer() at this point.
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 2ffb043..9220426 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -179,10 +179,13 @@
u_boot_dtsi_options_debug = $(warning $(u_boot_dtsi_options_raw))
endif
-# We use the first match
-u_boot_dtsi = $(strip $(u_boot_dtsi_options_debug) \
+# We use the first match to be included
+dtsi_include_list = $(strip $(u_boot_dtsi_options_debug) \
$(notdir $(firstword $(u_boot_dtsi_options))))
+# The CONFIG_DEVICE_TREE_INCLUDES also need to be included
+dtsi_include_list += $(CONFIG_DEVICE_TREE_INCLUDES)
+
# Modified for U-Boot
dtc_cpp_flags = -Wp,-MD,$(depfile).pre.tmp -nostdinc \
$(UBOOTINCLUDE) \
@@ -320,8 +323,8 @@
# Bring in any U-Boot-specific include at the end of the file
# And finally any custom .dtsi fragments specified with CONFIG_DEVICE_TREE_INCLUDES
cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \
- (cat $<; $(if $(u_boot_dtsi),echo '$(pound)include "$(u_boot_dtsi)"')) > $(pre-tmp); \
- $(foreach f,$(subst $(quote),,$(CONFIG_DEVICE_TREE_INCLUDES)), \
+ (cat $< > $(pre-tmp)); \
+ $(foreach f,$(subst $(quote),,$(dtsi_include_list)), \
echo '$(pound)include "$(f)"' >> $(pre-tmp);) \
$(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $(pre-tmp) ; \
$(DTC) -O dtb -o $@ -b 0 \
@@ -331,7 +334,29 @@
; \
sed "s:$(pre-tmp):$(<):" $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
-$(obj)/%.dtb: $(src)/%.dts $(DTC) FORCE
+quiet_cmd_capsule_esl_gen = CAPSULE_ESL_GEN $@
+cmd_capsule_esl_gen = \
+ $(shell sed "s:ESL_BIN_FILE:$(capsule_esl_path):" $(capsule_esl_input_file) > $@)
+
+$(obj)/.capsule_esl.dtsi: FORCE
+ifeq ($(CONFIG_EFI_CAPSULE_ESL_FILE),"")
+ $(error "CONFIG_EFI_CAPSULE_ESL_FILE is empty, EFI capsule authentication \
+ public key must be specified when CONFIG_EFI_CAPSULE_AUTHENTICATE is enabled")
+else
+ $(call cmd_capsule_esl_gen)
+endif
+
+capsule_esl_input_file=$(srctree)/lib/efi_loader/capsule_esl.dtsi.in
+capsule_esl_dtsi = .capsule_esl.dtsi
+capsule_esl_path=$(abspath $(srctree)/$(subst $(quote),,$(CONFIG_EFI_CAPSULE_ESL_FILE)))
+
+ifdef CONFIG_EFI_CAPSULE_AUTHENTICATE
+dtsi_include_list += $(capsule_esl_dtsi)
+endif
+
+dtsi_include_list_deps = $(addprefix $(obj)/,$(subst $(quote),,$(dtsi_include_list)))
+
+$(obj)/%.dtb: $(src)/%.dts $(DTC) $(dtsi_include_list_deps) FORCE
$(call if_changed_dep,dtc)
pre-tmp = $(subst $(comma),_,$(dot-target).pre.tmp)
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 15ac872..e450ffd 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -7,7 +7,7 @@
# Daniel Schwierzeck, daniel.schwierzeck@googlemail.com.
#
# (C) Copyright 2011
-# Texas Instruments Incorporated - http://www.ti.com/
+# Texas Instruments Incorporated - https://www.ti.com/
# Aneesh V <aneesh@ti.com>
# Based on top-level Makefile.
#
@@ -96,7 +96,7 @@
HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makefile),y,n)
-libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/)
+libs-y += $(if $(wildcard $(srctree)/board/$(BOARDDIR)/Makefile),board/$(BOARDDIR)/)
libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
ifeq ($(CONFIG_TPL_BUILD),y)
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 62b764f..b8eb57f 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -2606,8 +2606,8 @@
"Possible new uclass - make sure to add a sandbox driver, plus a test in test/dm/<name>.c\n" . $herecurr);
}
- # try to get people to use the livetree API
- if ($line =~ /^\+.*fdtdec_/) {
+ # try to get people to use the livetree API, except when changing tooling
+ if ($line =~ /^\+.*fdtdec_/ && $realfile !~ /^tools\//) {
WARN("LIVETREE",
"Use the livetree API (dev_read_...)\n" . $herecurr);
}
@@ -2636,12 +2636,18 @@
"All CONFIG symbols are managed by Kconfig\n" . $herecurr);
}
- # Don't put common.h and dm.h in header files
- if ($realfile =~ /\.h$/ && $rawline =~ /^\+#include\s*<(common|dm)\.h>*/) {
+ # Don't put dm.h in header files
+ if ($realfile =~ /\.h$/ && $rawline =~ /^\+#include\s*<dm\.h>*/) {
ERROR("BARRED_INCLUDE_IN_HDR",
"Avoid including common.h and dm.h in header files\n" . $herecurr);
}
+ # Don't add common.h to files
+ if ($rawline =~ /^\+#include\s*<common\.h>*/) {
+ ERROR("BARRED_INCLUDE_COMMON_H",
+ "Do not add common.h to files\n" . $herecurr);
+ }
+
# Do not disable fdt / initrd relocation
if ($rawline =~ /^\+.*(fdt|initrd)_high=0xffffffff/) {
ERROR("DISABLE_FDT_OR_INITRD_RELOC",
diff --git a/scripts/dtc/Makefile b/scripts/dtc/Makefile
index 8a2ef18..a01528c 100644
--- a/scripts/dtc/Makefile
+++ b/scripts/dtc/Makefile
@@ -22,4 +22,6 @@
$(obj)/dtc-lexer.lex.o: $(obj)/dtc-parser.tab.h
# Added for U-Boot
+ifeq ($(PYTHON_ENABLE),y)
subdir-$(CONFIG_PYLIBFDT) += pylibfdt
+endif
diff --git a/scripts/event_dump.py b/scripts/event_dump.py
index 0117457..24dfe2b 100755
--- a/scripts/event_dump.py
+++ b/scripts/event_dump.py
@@ -19,8 +19,10 @@
# A typical symbol looks like this:
# _u_boot_list_2_evspy_info_2_EVT_MISC_INIT_F_3_sandbox_misc_init_f
-PREFIX = '_u_boot_list_2_evspy_info_2_'
-RE_EVTYPE = re.compile('%s(.*)_3_.*' % PREFIX)
+PREFIX_FULL = '_u_boot_list_2_evspy_info_2_'
+PREFIX_SIMPLE = '_u_boot_list_2_evspy_info_simple_2_'
+RE_EVTYPE_FULL = re.compile('%s(.*)_3_.*' % PREFIX_FULL)
+RE_EVTYPE_SIMPLE = re.compile('%s(.*)_3_.*' % PREFIX_SIMPLE)
def show_sym(fname, data, endian, evtype, sym):
"""Show information about an evspy entry
@@ -88,12 +90,14 @@
fname (str): Filename of ELF file
endian (str): Endianness to use ('little', 'big', 'auto')
"""
- syms = elf.GetSymbolFileOffset(fname, [PREFIX])
+ syms = elf.GetSymbolFileOffset(fname, [PREFIX_FULL, PREFIX_SIMPLE])
data = tools.read_file(fname)
print('%-20s %-30s %s' % ('Event type', 'Id', 'Source location'))
print('%-20s %-30s %s' % ('-' * 20, '-' * 30, '-' * 30))
for name, sym in syms.items():
- m_evtype = RE_EVTYPE.search(name)
+ m_evtype = RE_EVTYPE_FULL.search(name)
+ if not m_evtype:
+ m_evtype = RE_EVTYPE_SIMPLE.search(name)
evtype = m_evtype .group(1)
show_sym(fname, data, endian, evtype, sym)
diff --git a/scripts/gen_compile_commands.py b/scripts/gen_compile_commands.py
new file mode 100755
index 0000000..cdca85e
--- /dev/null
+++ b/scripts/gen_compile_commands.py
@@ -0,0 +1,230 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) Google LLC, 2018
+#
+# Author: Tom Roeder <tmroeder@google.com>
+# Ported and modified for U-Boot by Joao Marcos Costa <jmcosta944@gmail.com>
+# Briefly documented at doc/build/gen_compile_commands.rst
+#
+"""A tool for generating compile_commands.json in U-Boot."""
+
+import argparse
+import json
+import logging
+import os
+import re
+import subprocess
+import sys
+
+_DEFAULT_OUTPUT = 'compile_commands.json'
+_DEFAULT_LOG_LEVEL = 'WARNING'
+
+_FILENAME_PATTERN = r'^\..*\.cmd$'
+_LINE_PATTERN = r'^cmd_[^ ]*\.o := (.* )([^ ]*\.c) *(;|$)'
+_VALID_LOG_LEVELS = ['DEBUG', 'INFO', 'WARNING', 'ERROR', 'CRITICAL']
+# The tools/ directory adopts a different build system, and produces .cmd
+# files in a different format. Do not support it.
+_EXCLUDE_DIRS = ['.git', 'Documentation', 'include', 'tools']
+
+def parse_arguments():
+ """Sets up and parses command-line arguments.
+
+ Returns:
+ log_level: A logging level to filter log output.
+ directory: The work directory where the objects were built.
+ ar: Command used for parsing .a archives.
+ output: Where to write the compile-commands JSON file.
+ paths: The list of files/directories to handle to find .cmd files.
+ """
+ usage = 'Creates a compile_commands.json database from U-Boot .cmd files'
+ parser = argparse.ArgumentParser(description=usage)
+
+ directory_help = ('specify the output directory used for the U-Boot build '
+ '(defaults to the working directory)')
+ parser.add_argument('-d', '--directory', type=str, default='.',
+ help=directory_help)
+
+ output_help = ('path to the output command database (defaults to ' +
+ _DEFAULT_OUTPUT + ')')
+ parser.add_argument('-o', '--output', type=str, default=_DEFAULT_OUTPUT,
+ help=output_help)
+
+ log_level_help = ('the level of log messages to produce (defaults to ' +
+ _DEFAULT_LOG_LEVEL + ')')
+ parser.add_argument('--log_level', choices=_VALID_LOG_LEVELS,
+ default=_DEFAULT_LOG_LEVEL, help=log_level_help)
+
+ ar_help = 'command used for parsing .a archives'
+ parser.add_argument('-a', '--ar', type=str, default='llvm-ar', help=ar_help)
+
+ paths_help = ('directories to search or files to parse '
+ '(files should be *.o, *.a, or modules.order). '
+ 'If nothing is specified, the current directory is searched')
+ parser.add_argument('paths', type=str, nargs='*', help=paths_help)
+
+ args = parser.parse_args()
+
+ return (args.log_level,
+ os.path.abspath(args.directory),
+ args.output,
+ args.ar,
+ args.paths if len(args.paths) > 0 else [args.directory])
+
+
+def cmdfiles_in_dir(directory):
+ """Generate the iterator of .cmd files found under the directory.
+
+ Walk under the given directory, and yield every .cmd file found.
+
+ Args:
+ directory: The directory to search for .cmd files.
+
+ Yields:
+ The path to a .cmd file.
+ """
+
+ filename_matcher = re.compile(_FILENAME_PATTERN)
+ exclude_dirs = [ os.path.join(directory, d) for d in _EXCLUDE_DIRS ]
+
+ for dirpath, dirnames, filenames in os.walk(directory, topdown=True):
+ # Prune unwanted directories.
+ if dirpath in exclude_dirs:
+ dirnames[:] = []
+ continue
+
+ for filename in filenames:
+ if filename_matcher.match(filename):
+ yield os.path.join(dirpath, filename)
+
+
+def to_cmdfile(path):
+ """Return the path of .cmd file used for the given build artifact
+
+ Args:
+ Path: file path
+
+ Returns:
+ The path to .cmd file
+ """
+ dir, base = os.path.split(path)
+ return os.path.join(dir, '.' + base + '.cmd')
+
+
+def cmdfiles_for_a(archive, ar):
+ """Generate the iterator of .cmd files associated with the archive.
+
+ Parse the given archive, and yield every .cmd file used to build it.
+
+ Args:
+ archive: The archive to parse
+
+ Yields:
+ The path to every .cmd file found
+ """
+ for obj in subprocess.check_output([ar, '-t', archive]).decode().split():
+ yield to_cmdfile(obj)
+
+
+def cmdfiles_for_modorder(modorder):
+ """Generate the iterator of .cmd files associated with the modules.order.
+
+ Parse the given modules.order, and yield every .cmd file used to build the
+ contained modules.
+
+ Args:
+ modorder: The modules.order file to parse
+
+ Yields:
+ The path to every .cmd file found
+ """
+ with open(modorder) as f:
+ for line in f:
+ obj = line.rstrip()
+ base, ext = os.path.splitext(obj)
+ if ext != '.o':
+ sys.exit('{}: module path must end with .o'.format(obj))
+ mod = base + '.mod'
+ # Read from *.mod, to get a list of objects that compose the module.
+ with open(mod) as m:
+ for mod_line in m:
+ yield to_cmdfile(mod_line.rstrip())
+
+
+def process_line(root_directory, command_prefix, file_path):
+ """Extracts information from a .cmd line and creates an entry from it.
+
+ Args:
+ root_directory: The directory that was searched for .cmd files. Usually
+ used directly in the "directory" entry in compile_commands.json.
+ command_prefix: The extracted command line, up to the last element.
+ file_path: The .c file from the end of the extracted command.
+ Usually relative to root_directory, but sometimes absolute.
+
+ Returns:
+ An entry to append to compile_commands.
+
+ Raises:
+ ValueError: Could not find the extracted file based on file_path and
+ root_directory or file_directory.
+ """
+ # The .cmd files are intended to be included directly by Make, so they
+ # escape the pound sign '#', either as '\#' or '$(pound)' (depending on the
+ # kernel version). The compile_commands.json file is not interepreted
+ # by Make, so this code replaces the escaped version with '#'.
+ prefix = command_prefix.replace('\#', '#').replace('$(pound)', '#')
+
+ # Use os.path.abspath() to normalize the path resolving '.' and '..' .
+ abs_path = os.path.abspath(os.path.join(root_directory, file_path))
+ if not os.path.exists(abs_path):
+ raise ValueError('File %s not found' % abs_path)
+ return {
+ 'directory': root_directory,
+ 'file': abs_path,
+ 'command': prefix + file_path,
+ }
+
+
+def main():
+ """Walks through the directory and finds and parses .cmd files."""
+ log_level, directory, output, ar, paths = parse_arguments()
+
+ level = getattr(logging, log_level)
+ logging.basicConfig(format='%(levelname)s: %(message)s', level=level)
+
+ line_matcher = re.compile(_LINE_PATTERN)
+
+ compile_commands = []
+
+ for path in paths:
+ # If 'path' is a directory, handle all .cmd files under it.
+ # Otherwise, handle .cmd files associated with the file.
+ # built-in objects are linked via vmlinux.a
+ # Modules are listed in modules.order.
+ if os.path.isdir(path):
+ cmdfiles = cmdfiles_in_dir(path)
+ elif path.endswith('.a'):
+ cmdfiles = cmdfiles_for_a(path, ar)
+ elif path.endswith('modules.order'):
+ cmdfiles = cmdfiles_for_modorder(path)
+ else:
+ sys.exit('{}: unknown file type'.format(path))
+
+ for cmdfile in cmdfiles:
+ with open(cmdfile, 'rt') as f:
+ result = line_matcher.match(f.readline())
+ if result:
+ try:
+ entry = process_line(directory, result.group(1),
+ result.group(2))
+ compile_commands.append(entry)
+ except ValueError as err:
+ logging.info('Could not add line from %s: %s',
+ cmdfile, err)
+
+ with open(output, 'wt') as f:
+ json.dump(compile_commands, f, indent=2, sort_keys=True)
+
+
+if __name__ == '__main__':
+ main()
diff --git a/scripts/get_maintainer.pl b/scripts/get_maintainer.pl
index 81116e2..6c58578 100755
--- a/scripts/get_maintainer.pl
+++ b/scripts/get_maintainer.pl
@@ -981,6 +981,7 @@
}
foreach my $email (@file_emails) {
+ $email = mailmap_email($email);
my ($name, $address) = parse_email($email);
my $tmp_email = format_email($name, $address, $email_usename);
@@ -1718,7 +1719,7 @@
%VCS_cmds = %VCS_cmds_hg;
return 2 if eval $VCS_cmds{"available"};
%VCS_cmds = ();
- if (!$printed_novcs) {
+ if (!$printed_novcs && $email_git) {
warn("$P: No supported VCS found. Add --nogit to options?\n");
warn("Using a git repository produces better results.\n");
warn("Try Linus Torvalds' latest git repository using:\n");
diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile
index 12e525e..2d97aab 100644
--- a/scripts/kconfig/Makefile
+++ b/scripts/kconfig/Makefile
@@ -99,7 +99,9 @@
%_config: %_defconfig
@:
-configfiles=$(wildcard $(srctree)/kernel/configs/$@ $(srctree)/arch/$(SRCARCH)/configs/$@)
+configfiles=$(wildcard $(srctree)/kernel/configs/$@ \
+ $(srctree)/arch/$(SRCARCH)/configs/$@ \
+ $(shell find $(srctree)/board -name "$@"))
%.config: $(obj)/conf
$(if $(call configfiles),, $(error No configuration exists for this target on this architecture))
diff --git a/test/Kconfig b/test/Kconfig
index 6e859fb..ca648d2 100644
--- a/test/Kconfig
+++ b/test/Kconfig
@@ -1,9 +1,4 @@
-config POST
- bool "Power On Self Test support"
- help
- See doc/README.POST for more details
-
-menu "Unit tests"
+menu "Testing"
config UNIT_TEST
bool "Unit tests"
@@ -106,8 +101,14 @@
source "test/dm/Kconfig"
source "test/env/Kconfig"
+source "test/image/Kconfig"
source "test/lib/Kconfig"
source "test/optee/Kconfig"
source "test/overlay/Kconfig"
+config POST
+ bool "Power On Self Test support"
+ help
+ See doc/README.POST for more details
+
endmenu
diff --git a/test/Makefile b/test/Makefile
index 1787736..8e1fed2 100644
--- a/test/Makefile
+++ b/test/Makefile
@@ -3,9 +3,6 @@
# (C) Copyright 2012 The Chromium Authors
obj-y += test-main.o
-ifdef CONFIG_SPL_LOAD_FIT
-obj-$(CONFIG_SANDBOX) += image/
-endif
ifneq ($(CONFIG_$(SPL_)BLOBLIST),)
obj-$(CONFIG_$(SPL_)CMDLINE) += bloblist.o
@@ -30,4 +27,6 @@
obj-$(CONFIG_UNIT_TEST) += common/
obj-y += log/
obj-$(CONFIG_$(SPL_)UT_UNICODE) += unicode_ut.o
+else
+obj-$(CONFIG_SPL_UT_LOAD) += image/
endif
diff --git a/test/boot/Makefile b/test/boot/Makefile
index 22ed61c..068522c 100644
--- a/test/boot/Makefile
+++ b/test/boot/Makefile
@@ -4,8 +4,10 @@
obj-$(CONFIG_BOOTSTD) += bootdev.o bootstd_common.o bootflow.o bootmeth.o
obj-$(CONFIG_FIT) += image.o
+obj-$(CONFIG_MEASURED_BOOT) += measurement.o
obj-$(CONFIG_EXPO) += expo.o
+obj-$(CONFIG_CEDIT) += cedit.o
ifdef CONFIG_OF_LIVE
obj-$(CONFIG_BOOTMETH_VBE_SIMPLE) += vbe_simple.o
diff --git a/test/boot/bootdev.c b/test/boot/bootdev.c
index 6b29213..0702fcc 100644
--- a/test/boot/bootdev.c
+++ b/test/boot/bootdev.c
@@ -190,12 +190,21 @@
BOOTSTD_TEST(bootdev_test_any, UT_TESTF_DM | UT_TESTF_SCAN_FDT |
UT_TESTF_ETH_BOOTDEV);
-/* Check bootdev ordering with the bootdev-order property */
+/*
+ * Check bootdev ordering with the bootdev-order property and boot_targets
+ * environment variable
+ */
static int bootdev_test_order(struct unit_test_state *uts)
{
struct bootflow_iter iter;
struct bootflow bflow;
+ test_set_skip_delays(true);
+
+ /* Start up USB which gives us three additional bootdevs */
+ usb_started = false;
+ ut_assertok(run_command("usb start", 0));
+
/*
* First try the order set by the bootdev-order property
* Like all sandbox unit tests this relies on the devicetree setting up
@@ -213,12 +222,55 @@
bootflow_iter_uninit(&iter);
/* Use the environment variable to override it */
- ut_assertok(env_set("boot_targets", "mmc1 mmc2"));
+ ut_assertok(env_set("boot_targets", "mmc1 mmc2 usb"));
ut_assertok(bootflow_scan_first(NULL, NULL, &iter, 0, &bflow));
ut_asserteq(-ENODEV, bootflow_scan_next(&iter, &bflow));
- ut_asserteq(2, iter.num_devs);
+ ut_asserteq(5, iter.num_devs);
ut_asserteq_str("mmc1.bootdev", iter.dev_used[0]->name);
ut_asserteq_str("mmc2.bootdev", iter.dev_used[1]->name);
+ ut_asserteq_str("usb_mass_storage.lun0.bootdev",
+ iter.dev_used[2]->name);
+ bootflow_iter_uninit(&iter);
+
+ /* Try a single uclass */
+ ut_assertok(env_set("boot_targets", NULL));
+ ut_assertok(bootflow_scan_first(NULL, "mmc", &iter, 0, &bflow));
+ ut_asserteq(2, iter.num_devs);
+
+ /* Now scan past mmc1 and make sure that only mmc0 shows up */
+ ut_asserteq(-ENODEV, bootflow_scan_next(&iter, &bflow));
+ ut_asserteq(3, iter.num_devs);
+ ut_asserteq_str("mmc2.bootdev", iter.dev_used[0]->name);
+ ut_asserteq_str("mmc1.bootdev", iter.dev_used[1]->name);
+ ut_asserteq_str("mmc0.bootdev", iter.dev_used[2]->name);
+ bootflow_iter_uninit(&iter);
+
+ /* Try a single uclass with boot_targets */
+ ut_assertok(env_set("boot_targets", "mmc"));
+ ut_assertok(bootflow_scan_first(NULL, NULL, &iter, 0, &bflow));
+ ut_asserteq(2, iter.num_devs);
+
+ /* Now scan past mmc1 and make sure that only mmc0 shows up */
+ ut_asserteq(-ENODEV, bootflow_scan_next(&iter, &bflow));
+ ut_asserteq(3, iter.num_devs);
+ ut_asserteq_str("mmc2.bootdev", iter.dev_used[0]->name);
+ ut_asserteq_str("mmc1.bootdev", iter.dev_used[1]->name);
+ ut_asserteq_str("mmc0.bootdev", iter.dev_used[2]->name);
+ bootflow_iter_uninit(&iter);
+
+ /* Try a single uclass with boot_targets */
+ ut_assertok(env_set("boot_targets", "mmc usb"));
+ ut_assertok(bootflow_scan_first(NULL, NULL, &iter, 0, &bflow));
+ ut_asserteq(2, iter.num_devs);
+
+ /* Now scan past mmc1 and make sure that the 3 USB devices show up */
+ ut_asserteq(-ENODEV, bootflow_scan_next(&iter, &bflow));
+ ut_asserteq(6, iter.num_devs);
+ ut_asserteq_str("mmc2.bootdev", iter.dev_used[0]->name);
+ ut_asserteq_str("mmc1.bootdev", iter.dev_used[1]->name);
+ ut_asserteq_str("mmc0.bootdev", iter.dev_used[2]->name);
+ ut_asserteq_str("usb_mass_storage.lun0.bootdev",
+ iter.dev_used[3]->name);
bootflow_iter_uninit(&iter);
return 0;
diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c
index 1c91a94..b97c566 100644
--- a/test/boot/bootflow.c
+++ b/test/boot/bootflow.c
@@ -27,6 +27,7 @@
DECLARE_GLOBAL_DATA_PTR;
+extern U_BOOT_DRIVER(bootmeth_cros);
extern U_BOOT_DRIVER(bootmeth_2script);
static int inject_response(struct unit_test_state *uts)
@@ -167,21 +168,22 @@
ut_assert_nextline("Seq Method State Uclass Part Name Filename");
ut_assert_nextlinen("---");
ut_assert_nextline("Scanning bootdev 'mmc2.bootdev':");
- ut_assert_nextline(" 0 extlinux media mmc 0 mmc2.bootdev.whole <NULL>");
+ ut_assert_nextline(" 0 extlinux media mmc 0 mmc2.bootdev.whole ");
ut_assert_nextline(" ** No partition found, err=-93: Protocol not supported");
- ut_assert_nextline(" 1 efi media mmc 0 mmc2.bootdev.whole <NULL>");
+ ut_assert_nextline(" 1 efi media mmc 0 mmc2.bootdev.whole ");
ut_assert_nextline(" ** No partition found, err=-93: Protocol not supported");
ut_assert_nextline("Scanning bootdev 'mmc1.bootdev':");
- ut_assert_nextline(" 2 extlinux media mmc 0 mmc1.bootdev.whole <NULL>");
+ ut_assert_nextline(" 2 extlinux media mmc 0 mmc1.bootdev.whole ");
ut_assert_nextline(" ** No partition found, err=-2: No such file or directory");
- ut_assert_nextline(" 3 efi media mmc 0 mmc1.bootdev.whole <NULL>");
+ ut_assert_nextline(" 3 efi media mmc 0 mmc1.bootdev.whole ");
ut_assert_nextline(" ** No partition found, err=-2: No such file or directory");
ut_assert_nextline(" 4 extlinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf");
ut_assert_nextline(" 5 efi fs mmc 1 mmc1.bootdev.part_1 efi/boot/bootsbox.efi");
ut_assert_skip_to_line("Scanning bootdev 'mmc0.bootdev':");
- ut_assert_skip_to_line(" 3f efi media mmc 0 mmc0.bootdev.whole <NULL>");
+ ut_assert_skip_to_line(
+ " 3f efi media mmc 0 mmc0.bootdev.whole ");
ut_assert_nextline(" ** No partition found, err=-93: Protocol not supported");
ut_assert_nextline("No more bootdevs");
ut_assert_nextlinen("---");
@@ -192,10 +194,11 @@
ut_assert_nextline("Showing all bootflows");
ut_assert_nextline("Seq Method State Uclass Part Name Filename");
ut_assert_nextlinen("---");
- ut_assert_nextline(" 0 extlinux media mmc 0 mmc2.bootdev.whole <NULL>");
- ut_assert_nextline(" 1 efi media mmc 0 mmc2.bootdev.whole <NULL>");
- ut_assert_skip_to_line(" 4 extlinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf");
- ut_assert_skip_to_line(" 3f efi media mmc 0 mmc0.bootdev.whole <NULL>");
+ ut_assert_nextline(" 0 extlinux media mmc 0 mmc2.bootdev.whole ");
+ ut_assert_nextline(" 1 efi media mmc 0 mmc2.bootdev.whole ");
+ ut_assert_skip_to_line(
+ " 4 extlinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf");
+ ut_assert_skip_to_line(" 3f efi media mmc 0 mmc0.bootdev.whole ");
ut_assert_nextlinen("---");
ut_assert_nextline("(64 bootflows, 1 valid)");
ut_assert_console_end();
@@ -384,7 +387,7 @@
console_record_reset_enable();
ut_assertok(run_command("bootflow scan -lH", 0));
ut_assert_skip_to_line(
- " 0 efi_mgr ready (none) 0 <NULL> <NULL>");
+ " 0 efi_mgr ready (none) 0 <NULL> ");
ut_assert_skip_to_line("No more bootdevs");
ut_assert_skip_to_line("(2 bootflows, 2 valid)");
ut_assert_console_end();
@@ -506,21 +509,33 @@
BOOTSTD_TEST(bootflow_cmd_boot, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
/**
- * prep_mmc4_bootdev() - Set up the mmc4 bootdev so we can access a fake Armbian
+ * prep_mmc_bootdev() - Set up an mmc bootdev so we can access other distros
+ *
+ * After calling this function, set std->bootdev_order to *@old_orderp to
+ * restore normal operation of bootstd (i.e. with the original bootdev order)
*
* @uts: Unit test state
+ * @mmc_dev: MMC device to use, e.g. "mmc4". Note that this must remain valid
+ * in the caller until
+ * @bind_cros: true to bind the ChromiumOS bootmeth
+ * @old_orderp: Returns the original bootdev order, which must be restored
* Returns 0 on success, -ve on failure
*/
-static int prep_mmc4_bootdev(struct unit_test_state *uts)
+static int prep_mmc_bootdev(struct unit_test_state *uts, const char *mmc_dev,
+ bool bind_cros, const char ***old_orderp)
{
- static const char *order[] = {"mmc2", "mmc1", "mmc4", NULL};
+ static const char *order[] = {"mmc2", "mmc1", NULL, NULL};
struct udevice *dev, *bootstd;
struct bootstd_priv *std;
const char **old_order;
- ofnode node;
+ ofnode root, node;
+
+ order[2] = mmc_dev;
/* Enable the mmc4 node since we need a second bootflow */
- node = ofnode_path("/mmc4");
+ root = oftree_root(oftree_default());
+ node = ofnode_find_subnode(root, mmc_dev);
+ ut_assert(ofnode_valid(node));
ut_assertok(lists_bind_fdt(gd->dm_root, node, &dev, NULL, false));
/* Enable the script bootmeth too */
@@ -528,27 +543,74 @@
ut_assertok(device_bind(bootstd, DM_DRIVER_REF(bootmeth_2script),
"bootmeth_script", 0, ofnode_null(), &dev));
- /* Change the order to include mmc4 */
+ /* Enable the cros bootmeth if needed */
+ if (bind_cros) {
+ ut_assertok(uclass_first_device_err(UCLASS_BOOTSTD, &bootstd));
+ ut_assertok(device_bind(bootstd, DM_DRIVER_REF(bootmeth_cros),
+ "cros", 0, ofnode_null(), &dev));
+ }
+
+ /* Change the order to include the device */
std = dev_get_priv(bootstd);
old_order = std->bootdev_order;
std->bootdev_order = order;
+ *old_orderp = old_order;
+
+ return 0;
+}
+
+/**
+ * scan_mmc_bootdev() - Set up an mmc bootdev so we can access other distros
+ *
+ * @uts: Unit test state
+ * @mmc_dev: MMC device to use, e.g. "mmc4"
+ * @bind_cros: true to bind the ChromiumOS bootmeth
+ * Returns 0 on success, -ve on failure
+ */
+static int scan_mmc_bootdev(struct unit_test_state *uts, const char *mmc_dev,
+ bool bind_cros)
+{
+ struct bootstd_priv *std;
+ struct udevice *bootstd;
+ const char **old_order;
+
+ ut_assertok(prep_mmc_bootdev(uts, mmc_dev, bind_cros, &old_order));
console_record_reset_enable();
ut_assertok(run_command("bootflow scan", 0));
ut_assert_console_end();
/* Restore the order used by the device tree */
+ ut_assertok(uclass_first_device_err(UCLASS_BOOTSTD, &bootstd));
+ std = dev_get_priv(bootstd);
std->bootdev_order = old_order;
return 0;
}
+/**
+ * scan_mmc4_bootdev() - Set up the mmc4 bootdev so we can access a fake Armbian
+ *
+ * @uts: Unit test state
+ * Returns 0 on success, -ve on failure
+ */
+static int scan_mmc4_bootdev(struct unit_test_state *uts)
+{
+ ut_assertok(scan_mmc_bootdev(uts, "mmc4", false));
+
+ return 0;
+}
+
/* Check 'bootflow menu' to select a bootflow */
static int bootflow_cmd_menu(struct unit_test_state *uts)
{
+ struct bootstd_priv *std;
char prev[3];
- ut_assertok(prep_mmc4_bootdev(uts));
+ /* get access to the current bootflow */
+ ut_assertok(bootstd_get_priv(&std));
+
+ ut_assertok(scan_mmc4_bootdev(uts));
/* Add keypresses to move to and select the second one in the list */
prev[0] = CTL_CH('n');
@@ -558,6 +620,17 @@
ut_assertok(run_command("bootflow menu", 0));
ut_assert_nextline("Selected: Armbian");
+ ut_assertnonnull(std->cur_bootflow);
+ ut_assert_console_end();
+
+ /* Check not selecting anything */
+ prev[0] = '\e';
+ prev[1] = '\0';
+ ut_asserteq(1, console_in_puts(prev));
+
+ ut_asserteq(1, run_command("bootflow menu", 0));
+ ut_assertnull(std->cur_bootflow);
+ ut_assert_nextline("Nothing chosen");
ut_assert_console_end();
return 0;
@@ -654,7 +727,7 @@
ofnode node;
int i;
- ut_assertok(prep_mmc4_bootdev(uts));
+ ut_assertok(scan_mmc4_bootdev(uts));
ut_assertok(bootflow_menu_new(&exp));
node = ofnode_path("/bootstd/theme");
@@ -945,3 +1018,44 @@
return 0;
}
BOOTSTD_TEST(bootflow_cmdline, 0);
+
+/* test a few special changes to a long command line */
+static int bootflow_cmdline_special(struct unit_test_state *uts)
+{
+ char buf[500];
+ int pos;
+
+ /*
+ * check handling of an argument which has an embedded '=', as well as
+ * handling of a argument which partially matches ("ro" and "root")
+ */
+ ut_asserteq(32, cmdline_set_arg(
+ buf, sizeof(buf),
+ "loglevel=7 root=PARTUUID=d68352e3 rootwait ro noinitrd",
+ "root", NULL, &pos));
+ ut_asserteq_str("loglevel=7 rootwait ro noinitrd", buf);
+
+ return 0;
+}
+BOOTSTD_TEST(bootflow_cmdline_special, 0);
+
+/* Test ChromiumOS bootmeth */
+static int bootflow_cros(struct unit_test_state *uts)
+{
+ ut_assertok(scan_mmc_bootdev(uts, "mmc5", true));
+ ut_assertok(run_command("bootflow list", 0));
+
+ ut_assert_nextlinen("Showing all");
+ ut_assert_nextlinen("Seq");
+ ut_assert_nextlinen("---");
+ ut_assert_nextlinen(" 0 extlinux");
+ ut_assert_nextlinen(" 1 cros ready mmc 2 mmc5.bootdev.part_2 ");
+ ut_assert_nextlinen(" 2 cros ready mmc 4 mmc5.bootdev.part_4 ");
+ ut_assert_nextlinen("---");
+ ut_assert_skip_to_line("(3 bootflows, 3 valid)");
+
+ ut_assert_console_end();
+
+ return 0;
+}
+BOOTSTD_TEST(bootflow_cros, 0);
diff --git a/test/boot/cedit.c b/test/boot/cedit.c
new file mode 100644
index 0000000..aa41719
--- /dev/null
+++ b/test/boot/cedit.c
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <cedit.h>
+#include <env.h>
+#include <expo.h>
+#include <mapmem.h>
+#include <dm/ofnode.h>
+#include <test/ut.h>
+#include "bootstd_common.h"
+#include <test/cedit-test.h>
+#include "../../boot/scene_internal.h"
+
+/* Check the cedit command */
+static int cedit_base(struct unit_test_state *uts)
+{
+ extern struct expo *cur_exp;
+ struct scene_obj_menu *menu;
+ struct scene_obj_txt *txt;
+ struct expo *exp;
+ struct scene *scn;
+
+ ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0));
+
+ console_record_reset_enable();
+
+ /*
+ * ^N Move down to second menu
+ * ^M Open menu
+ * ^N Move down to second item
+ * ^M Select item
+ * \e Quit
+ */
+ console_in_puts("\x0e\x0d\x0e\x0d\e");
+ ut_assertok(run_command("cedit run", 0));
+
+ exp = cur_exp;
+ scn = expo_lookup_scene_id(exp, exp->scene_id);
+ ut_assertnonnull(scn);
+
+ menu = scene_obj_find(scn, scn->highlight_id, SCENEOBJT_NONE);
+ ut_assertnonnull(menu);
+
+ txt = scene_obj_find(scn, menu->title_id, SCENEOBJT_NONE);
+ ut_assertnonnull(txt);
+ ut_asserteq_str("AC Power", expo_get_str(exp, txt->str_id));
+
+ ut_asserteq(ID_AC_ON, menu->cur_item_id);
+
+ return 0;
+}
+BOOTSTD_TEST(cedit_base, 0);
+
+/* Check the cedit write_fdt and read_fdt commands */
+static int cedit_fdt(struct unit_test_state *uts)
+{
+ struct scene_obj_textline *tline;
+ struct video_priv *vid_priv;
+ extern struct expo *cur_exp;
+ struct scene_obj_menu *menu;
+ ulong addr = 0x1000;
+ struct ofprop prop;
+ struct scene *scn;
+ oftree tree;
+ ofnode node;
+ char *str;
+ void *fdt;
+ int i;
+
+ console_record_reset_enable();
+ ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0));
+
+ ut_asserteq(ID_SCENE1, cedit_prepare(cur_exp, &vid_priv, &scn));
+
+ /* get a menu to fiddle with */
+ menu = scene_obj_find(scn, ID_CPU_SPEED, SCENEOBJT_MENU);
+ ut_assertnonnull(menu);
+ menu->cur_item_id = ID_CPU_SPEED_2;
+
+ /* get a textline to fiddle with too */
+ tline = scene_obj_find(scn, ID_MACHINE_NAME, SCENEOBJT_TEXTLINE);
+ ut_assertnonnull(tline);
+ str = abuf_data(&tline->buf);
+ strcpy(str, "my-machine");
+
+ ut_assertok(run_command("cedit write_fdt hostfs - settings.dtb", 0));
+ ut_assertok(run_commandf("load hostfs - %lx settings.dtb", addr));
+ ut_assert_nextlinen("1024 bytes read");
+
+ fdt = map_sysmem(addr, 1024);
+ tree = oftree_from_fdt(fdt);
+ node = ofnode_find_subnode(oftree_root(tree), CEDIT_NODE_NAME);
+ ut_assert(ofnode_valid(node));
+
+ ut_asserteq(ID_CPU_SPEED_2,
+ ofnode_read_u32_default(node, "cpu-speed", 0));
+ ut_asserteq_str("2.5 GHz", ofnode_read_string(node, "cpu-speed-str"));
+ ut_asserteq_str("my-machine", ofnode_read_string(node, "machine-name"));
+
+ /* There should only be 5 properties */
+ for (i = 0, ofnode_first_property(node, &prop); ofprop_valid(&prop);
+ i++, ofnode_next_property(&prop))
+ ;
+ ut_asserteq(5, i);
+
+ ut_assert_console_end();
+
+ /* reset the expo */
+ menu->cur_item_id = ID_CPU_SPEED_1;
+ *str = '\0';
+
+ /* load in the settings and make sure they update */
+ ut_assertok(run_command("cedit read_fdt hostfs - settings.dtb", 0));
+ ut_asserteq(ID_CPU_SPEED_2, menu->cur_item_id);
+ ut_asserteq_str("my-machine", ofnode_read_string(node, "machine-name"));
+
+ ut_assertnonnull(menu);
+ ut_assert_console_end();
+
+ return 0;
+}
+BOOTSTD_TEST(cedit_fdt, 0);
+
+/* Check the cedit write_env and read_env commands */
+static int cedit_env(struct unit_test_state *uts)
+{
+ struct scene_obj_textline *tline;
+ struct video_priv *vid_priv;
+ extern struct expo *cur_exp;
+ struct scene_obj_menu *menu;
+ struct scene *scn;
+ char *str;
+
+ console_record_reset_enable();
+ ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0));
+
+ ut_asserteq(ID_SCENE1, cedit_prepare(cur_exp, &vid_priv, &scn));
+
+ /* get a menu to fiddle with */
+ menu = scene_obj_find(scn, ID_CPU_SPEED, SCENEOBJT_MENU);
+ ut_assertnonnull(menu);
+ menu->cur_item_id = ID_CPU_SPEED_2;
+
+ /* get a textline to fiddle with too */
+ tline = scene_obj_find(scn, ID_MACHINE_NAME, SCENEOBJT_TEXTLINE);
+ ut_assertnonnull(tline);
+ str = abuf_data(&tline->buf);
+ strcpy(str, "my-machine");
+
+ ut_assertok(run_command("cedit write_env -v", 0));
+ ut_assert_nextlinen("c.cpu-speed=7");
+ ut_assert_nextlinen("c.cpu-speed-str=2.5 GHz");
+ ut_assert_nextlinen("c.power-loss=10");
+ ut_assert_nextlinen("c.power-loss-str=Always Off");
+ ut_assert_nextlinen("c.machine-name=my-machine");
+ ut_assert_console_end();
+
+ ut_asserteq(7, env_get_ulong("c.cpu-speed", 10, 0));
+ ut_asserteq_str("2.5 GHz", env_get("c.cpu-speed-str"));
+ ut_asserteq_str("my-machine", env_get("c.machine-name"));
+
+ /* reset the expo */
+ menu->cur_item_id = ID_CPU_SPEED_1;
+ *str = '\0';
+
+ ut_assertok(run_command("cedit read_env -v", 0));
+ ut_assert_nextlinen("c.cpu-speed=7");
+ ut_assert_nextlinen("c.power-loss=10");
+ ut_assert_nextlinen("c.machine-name=my-machine");
+ ut_assert_console_end();
+
+ ut_asserteq(ID_CPU_SPEED_2, menu->cur_item_id);
+ ut_asserteq_str("my-machine", env_get("c.machine-name"));
+
+ return 0;
+}
+BOOTSTD_TEST(cedit_env, 0);
+
+/* Check the cedit write_cmos and read_cmos commands */
+static int cedit_cmos(struct unit_test_state *uts)
+{
+ struct scene_obj_menu *menu, *menu2;
+ struct video_priv *vid_priv;
+ extern struct expo *cur_exp;
+ struct scene *scn;
+
+ console_record_reset_enable();
+ ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0));
+
+ ut_asserteq(ID_SCENE1, cedit_prepare(cur_exp, &vid_priv, &scn));
+
+ /* get the menus to fiddle with */
+ menu = scene_obj_find(scn, ID_CPU_SPEED, SCENEOBJT_MENU);
+ ut_assertnonnull(menu);
+ menu->cur_item_id = ID_CPU_SPEED_2;
+
+ menu2 = scene_obj_find(scn, ID_POWER_LOSS, SCENEOBJT_MENU);
+ ut_assertnonnull(menu2);
+ menu2->cur_item_id = ID_AC_MEMORY;
+
+ ut_assertok(run_command("cedit write_cmos -v", 0));
+ ut_assert_nextlinen("Write 2 bytes from offset 80 to 84");
+ ut_assert_console_end();
+
+ /* reset the expo */
+ menu->cur_item_id = ID_CPU_SPEED_1;
+ menu2->cur_item_id = ID_AC_OFF;
+
+ ut_assertok(run_command("cedit read_cmos -v", 0));
+ ut_assert_nextlinen("Read 2 bytes from offset 80 to 84");
+ ut_assert_console_end();
+
+ ut_asserteq(ID_CPU_SPEED_2, menu->cur_item_id);
+ ut_asserteq(ID_AC_MEMORY, menu2->cur_item_id);
+
+ return 0;
+}
+BOOTSTD_TEST(cedit_cmos, 0);
diff --git a/test/boot/expo.c b/test/boot/expo.c
index 3898f85..714fdfa 100644
--- a/test/boot/expo.c
+++ b/test/boot/expo.c
@@ -289,6 +289,33 @@
}
BOOTSTD_TEST(expo_object_attr, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+/**
+ * struct test_iter_priv - private data for expo-iterator test
+ *
+ * @count: number of scene objects
+ * @menu_count: number of menus
+ * @fail_at: item ID at which to return an error
+ */
+struct test_iter_priv {
+ int count;
+ int menu_count;
+ int fail_at;
+};
+
+int h_test_iter(struct scene_obj *obj, void *vpriv)
+{
+ struct test_iter_priv *priv = vpriv;
+
+ if (priv->fail_at == obj->id)
+ return -EINVAL;
+
+ priv->count++;
+ if (obj->type == SCENEOBJT_MENU)
+ priv->menu_count++;
+
+ return 0;
+}
+
/* Check creating a scene with a menu */
static int expo_object_menu(struct unit_test_state *uts)
{
@@ -296,6 +323,7 @@
struct scene_menitem *item;
int id, label_id, desc_id, key_id, pointer_id, preview_id;
struct scene_obj_txt *ptr, *name1, *desc1, *key1, *tit, *prev1;
+ struct test_iter_priv priv;
struct scene *scn;
struct expo *exp;
ulong start_mem;
@@ -382,6 +410,23 @@
ut_asserteq(menu->obj.dim.y + 32, prev1->obj.dim.y);
ut_asserteq(true, prev1->obj.flags & SCENEOF_HIDE);
+ /* check iterating through scene items */
+ memset(&priv, '\0', sizeof(priv));
+ ut_assertok(expo_iter_scene_objs(exp, h_test_iter, &priv));
+ ut_asserteq(7, priv.count);
+ ut_asserteq(1, priv.menu_count);
+
+ /* check the iterator failing part way through iteration */
+ memset(&priv, '\0', sizeof(priv));
+ priv.fail_at = key_id;
+ ut_asserteq(-EINVAL, expo_iter_scene_objs(exp, h_test_iter, &priv));
+
+ /* 2 items (preview_id and the menuitem) are after key_id, 7 - 2 = 5 */
+ ut_asserteq(5, priv.count);
+
+ /* menu is first, so is still processed */
+ ut_asserteq(1, priv.menu_count);
+
expo_destroy(exp);
ut_assertok(ut_check_delta(start_mem));
@@ -609,7 +654,7 @@
ut_asserteq_str("name", exp->name);
ut_asserteq(0, exp->scene_id);
- ut_asserteq(ID_DYNAMIC_START + 20, exp->next_id);
+ ut_asserteq(ID_DYNAMIC_START + 24, exp->next_id);
ut_asserteq(false, exp->popup);
/* check the scene */
@@ -669,46 +714,3 @@
return 0;
}
BOOTSTD_TEST(expo_test_build, UT_TESTF_DM);
-
-/* Check the cedit command */
-static int expo_cedit(struct unit_test_state *uts)
-{
- extern struct expo *cur_exp;
- struct scene_obj_menu *menu;
- struct scene_obj_txt *txt;
- struct expo *exp;
- struct scene *scn;
-
- if (!IS_ENABLED(CONFIG_CMD_CEDIT))
- return -EAGAIN;
-
- ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0));
-
- console_record_reset_enable();
-
- /*
- * ^N Move down to second menu
- * ^M Open menu
- * ^N Move down to second item
- * ^M Select item
- * \e Quit
- */
- console_in_puts("\x0e\x0d\x0e\x0d\e");
- ut_assertok(run_command("cedit run", 0));
-
- exp = cur_exp;
- scn = expo_lookup_scene_id(exp, exp->scene_id);
- ut_assertnonnull(scn);
-
- menu = scene_obj_find(scn, scn->highlight_id, SCENEOBJT_NONE);
- ut_assertnonnull(menu);
-
- txt = scene_obj_find(scn, menu->title_id, SCENEOBJT_NONE);
- ut_assertnonnull(txt);
- ut_asserteq_str("AC Power", expo_get_str(exp, txt->str_id));
-
- ut_asserteq(ID_AC_ON, menu->cur_item_id);
-
- return 0;
-}
-BOOTSTD_TEST(expo_cedit, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
diff --git a/test/boot/files/expo_ids.h b/test/boot/files/expo_ids.h
new file mode 100644
index 0000000..a86e0d0
--- /dev/null
+++ b/test/boot/files/expo_ids.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Sample expo screen layout (ID numbers)
+ */
+
+enum {
+ ZERO,
+ ID_PROMPT,
+
+ ID_SCENE1,
+ ID_SCENE1_TITLE,
+
+ ID_CPU_SPEED,
+ ID_CPU_SPEED_TITLE,
+ ID_CPU_SPEED_1,
+ ID_CPU_SPEED_2,
+ ID_CPU_SPEED_3,
+
+ ID_POWER_LOSS,
+ ID_AC_OFF,
+ ID_AC_ON,
+ ID_AC_MEMORY,
+
+ ID_MACHINE_NAME,
+ ID_MACHINE_NAME_EDIT,
+
+ ID_DYNAMIC_START,
+};
diff --git a/test/boot/files/expo_layout.dts b/test/boot/files/expo_layout.dts
index 55d5c91..bed5522 100644
--- a/test/boot/files/expo_layout.dts
+++ b/test/boot/files/expo_layout.dts
@@ -5,28 +5,7 @@
/dts-v1/;
-/*
-enum {
- ZERO,
- ID_PROMPT,
-
- ID_SCENE1,
- ID_SCENE1_TITLE,
-
- ID_CPU_SPEED,
- ID_CPU_SPEED_TITLE,
- ID_CPU_SPEED_1,
- ID_CPU_SPEED_2,
- ID_CPU_SPEED_3,
-
- ID_POWER_LOSS,
- ID_AC_OFF,
- ID_AC_ON,
- ID_AC_MEMORY,
-
- ID_DYNAMIC_START,
-};
-*/
+/* see expo_ids.h for the IDs */
/ {
dynamic-start = <ID_DYNAMIC_START>;
@@ -59,6 +38,9 @@
/* IDs for the menu items */
item-id = <ID_CPU_SPEED_1 ID_CPU_SPEED_2
ID_CPU_SPEED_3>;
+
+ start-bit = <0x400>;
+ bit-length = <2>;
};
power-loss {
@@ -70,6 +52,16 @@
"Memory";
item-id = <ID_AC_OFF ID_AC_ON ID_AC_MEMORY>;
+ start-bit = <0x422>;
+ bit-length = <2>;
+ };
+
+ machine-name {
+ id = <ID_MACHINE_NAME>;
+ type = "textline";
+ max-chars = <20>;
+ title = "Machine name";
+ edit-id = <ID_MACHINE_NAME_EDIT>;
};
};
};
diff --git a/test/boot/measurement.c b/test/boot/measurement.c
new file mode 100644
index 0000000..9db2ed3
--- /dev/null
+++ b/test/boot/measurement.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Test for measured boot functions
+ *
+ * Copyright 2023 IBM Corp.
+ * Written by Eddie James <eajames@linux.ibm.com>
+ */
+
+#include <common.h>
+#include <bootm.h>
+#include <malloc.h>
+#include <test/suites.h>
+#include <test/test.h>
+#include <test/ut.h>
+#include <asm/io.h>
+
+#define MEASUREMENT_TEST(_name, _flags) \
+ UNIT_TEST(_name, _flags, measurement_test)
+
+static int measure(struct unit_test_state *uts)
+{
+ struct bootm_headers images;
+ const size_t size = 1024;
+ u8 *kernel;
+ u8 *initrd;
+ size_t i;
+
+ kernel = malloc(size);
+ initrd = malloc(size);
+
+ images.os.image_start = map_to_sysmem(kernel);
+ images.os.image_len = size;
+
+ images.rd_start = map_to_sysmem(initrd);
+ images.rd_end = images.rd_start + size;
+
+ images.ft_addr = malloc(size);
+ images.ft_len = size;
+
+ env_set("bootargs", "measurement testing");
+
+ for (i = 0; i < size; ++i) {
+ kernel[i] = 0xf0 | (i & 0xf);
+ initrd[i] = (i & 0xf0) | 0xf;
+ images.ft_addr[i] = i & 0xff;
+ }
+
+ ut_assertok(bootm_measure(&images));
+
+ free(images.ft_addr);
+ free(initrd);
+ free(kernel);
+
+ return 0;
+}
+MEASUREMENT_TEST(measure, 0);
+
+int do_ut_measurement(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct unit_test *tests = UNIT_TEST_SUITE_START(measurement_test);
+ const int n_ents = UNIT_TEST_SUITE_COUNT(measurement_test);
+
+ return cmd_ut_category("measurement", "measurement_test_", tests,
+ n_ents, argc, argv);
+}
diff --git a/test/cmd/Makefile b/test/cmd/Makefile
index 6e3d7e9..e296ba1 100644
--- a/test/cmd/Makefile
+++ b/test/cmd/Makefile
@@ -14,6 +14,7 @@
obj-$(CONFIG_CMD_BDI) += bdinfo.o
obj-$(CONFIG_CMD_FDT) += fdt.o
obj-$(CONFIG_CONSOLE_TRUETYPE) += font.o
+obj-$(CONFIG_CMD_HISTORY) += history.o
obj-$(CONFIG_CMD_LOADM) += loadm.o
obj-$(CONFIG_CMD_MEM_SEARCH) += mem_search.o
ifdef CONFIG_CMD_PCI
@@ -23,6 +24,7 @@
obj-$(CONFIG_CMD_PWM) += pwm.o
obj-$(CONFIG_CMD_SEAMA) += seama.o
ifdef CONFIG_SANDBOX
+obj-$(CONFIG_CMD_MBR) += mbr.o
obj-$(CONFIG_CMD_READ) += rw.o
obj-$(CONFIG_CMD_SETEXPR) += setexpr.o
obj-$(CONFIG_ARM_FFA_TRANSPORT) += armffa.o
diff --git a/test/cmd/history.c b/test/cmd/history.c
new file mode 100644
index 0000000..06517fc
--- /dev/null
+++ b/test/cmd/history.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Tests for history command
+ *
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <cli.h>
+#include <command.h>
+#include <test/lib.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+static int lib_test_history(struct unit_test_state *uts)
+{
+ static const char cmd1[] = "setenv fred hello";
+ static const char cmd2[] = "print fred";
+
+ /* running commands directly does not add to history */
+ ut_assertok(run_command(cmd1, 0));
+ ut_assert_console_end();
+ ut_assertok(run_command("history", 0));
+ ut_assert_console_end();
+
+ /* enter commands via the console */
+ console_in_puts(cmd1);
+ console_in_puts("\n");
+ ut_asserteq(strlen(cmd1), cli_readline(""));
+ ut_assert_nextline(cmd1);
+
+ console_in_puts(cmd2);
+ console_in_puts("\n");
+ ut_asserteq(strlen(cmd2), cli_readline(""));
+ ut_assert_nextline(cmd2);
+
+ ut_assertok(run_command("print fred", 0));
+ ut_assert_nextline("fred=hello");
+ ut_assert_console_end();
+
+ ut_assertok(run_command("history", 0));
+ ut_assert_nextline(cmd1);
+ ut_assert_nextline(cmd2);
+ ut_assert_console_end();
+
+ return 0;
+}
+LIB_TEST(lib_test_history, UT_TESTF_CONSOLE_REC);
diff --git a/test/cmd/mbr.c b/test/cmd/mbr.c
new file mode 100644
index 0000000..46b78e7
--- /dev/null
+++ b/test/cmd/mbr.c
@@ -0,0 +1,479 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Tests for mbr command
+ *
+ * Copyright 2023 Matrox Video
+ * Written by Alex Gendin <agendin@matrox.com>
+ */
+
+#include <dm.h>
+#include <console.h>
+#include <dm/test.h>
+#include <mapmem.h>
+#include <part.h>
+#include <asm/global_data.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <test/suites.h>
+#include <test/ut.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Requirements for running test manually:
+ * mmc6.img - File size needs to be at least 12 MiB
+ *
+ * Command to create mmc6.img:
+ * $ dd if=/dev/zero of=mmc6.img bs=12M count=1
+ *
+ * To run this test manually, place mmc6.img into the same directory as u-boot,
+ * then run:
+ * $ ./u-boot -Tc 'ut mbr'
+ *
+ * To run this test as part of U-Boot test:
+ * $ ./test/py/test.py --bd sandbox --build -k ut_dm -v
+ * Note: mmc6.img will be created by the test suit.
+ */
+
+static char * mbr_parts_header = "setenv mbr_parts '";
+static char * mbr_parts_p1 = "uuid_disk=0x12345678;name=p1,start=8M,bootable,size=1M,id=0x0e";
+static char * mbr_parts_p2 = ";name=p2,size=1M,id=0x0e";
+static char * mbr_parts_p3 = ";name=p3,size=1M,id=0x0e";
+static char * mbr_parts_p4 = ";name=p4,size=1M,id=0x0e";
+static char * mbr_parts_p5 = ";name=[ext],size=2M,id=0x05;name=p5,size=1M,id=0x0e";
+static char * mbr_parts_tail = "'";
+
+/*
+ * One MBR partition
+000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....|
+000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 00 |...%$..@........|
+000001d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
+000001e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
+000001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 aa |..............U.|
+*/
+static unsigned mbr_cmp_start = 0x1B8;
+static unsigned mbr_cmp_size = 0x48;
+static unsigned char mbr_parts_ref_p1[] = {
+ 0x78, 0x56, 0x34, 0x12, 0x00, 0x00, 0x80, 0x05,
+0x05, 0x01, 0x0e, 0x25, 0x24, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0xaa
+};
+
+/*
+ * Two MBR partitions
+000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....|
+000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%|
+000001d0 25 01 0e 46 05 01 00 48 00 00 00 08 00 00 00 00 |%..F...H........|
+000001e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
+000001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 aa |..............U.|
+*/
+static unsigned char mbr_parts_ref_p2[] = {
+ 0x78, 0x56, 0x34, 0x12, 0x00, 0x00, 0x80, 0x05,
+0x05, 0x01, 0x0e, 0x25, 0x24, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x25,
+0x25, 0x01, 0x0e, 0x46, 0x05, 0x01, 0x00, 0x48, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0xaa
+};
+
+/*
+ * Three MBR partitions
+000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....|
+000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%|
+000001d0 25 01 0e 46 05 01 00 48 00 00 00 08 00 00 00 46 |%..F...H.......F|
+000001e0 06 01 0e 66 25 01 00 50 00 00 00 08 00 00 00 00 |...f%..P........|
+000001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 aa |..............U.|
+*/
+static unsigned char mbr_parts_ref_p3[] = {
+ 0x78, 0x56, 0x34, 0x12, 0x00, 0x00, 0x80, 0x05,
+0x05, 0x01, 0x0e, 0x25, 0x24, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x25,
+0x25, 0x01, 0x0e, 0x46, 0x05, 0x01, 0x00, 0x48, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x46,
+0x06, 0x01, 0x0e, 0x66, 0x25, 0x01, 0x00, 0x50, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0xaa
+};
+
+/*
+ * Four MBR partitions
+000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....|
+000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%|
+000001d0 25 01 0e 46 05 01 00 48 00 00 00 08 00 00 00 46 |%..F...H.......F|
+000001e0 06 01 0e 66 25 01 00 50 00 00 00 08 00 00 00 66 |...f%..P.......f|
+000001f0 26 01 0e 87 06 01 00 58 00 00 00 08 00 00 55 aa |&......X......U.|
+*/
+static unsigned char mbr_parts_ref_p4[] = {
+ 0x78, 0x56, 0x34, 0x12, 0x00, 0x00, 0x80, 0x05,
+0x05, 0x01, 0x0e, 0x25, 0x24, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x25,
+0x25, 0x01, 0x0e, 0x46, 0x05, 0x01, 0x00, 0x48, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x46,
+0x06, 0x01, 0x0e, 0x66, 0x25, 0x01, 0x00, 0x50, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x66,
+0x26, 0x01, 0x0e, 0x87, 0x06, 0x01, 0x00, 0x58, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x55, 0xaa
+};
+
+/*
+ * Five MBR partitions
+000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....|
+000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%|
+000001d0 25 01 0e 46 05 01 00 48 00 00 00 08 00 00 00 46 |%..F...H.......F|
+000001e0 06 01 0e 66 25 01 00 50 00 00 00 08 00 00 00 66 |...f%..P.......f|
+000001f0 26 01 05 a7 26 01 00 58 00 00 00 10 00 00 55 aa |&...&..X......U.|
+*/
+static unsigned char mbr_parts_ref_p5[] = {
+ 0x78, 0x56, 0x34, 0x12, 0x00, 0x00, 0x80, 0x05,
+0x05, 0x01, 0x0e, 0x25, 0x24, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x25,
+0x25, 0x01, 0x0e, 0x46, 0x05, 0x01, 0x00, 0x48, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x46,
+0x06, 0x01, 0x0e, 0x66, 0x25, 0x01, 0x00, 0x50, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x66,
+0x26, 0x01, 0x05, 0xa7, 0x26, 0x01, 0x00, 0x58, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x55, 0xaa
+};
+static unsigned ebr_cmp_start = 0x1B8;
+static unsigned ebr_cmp_size = 0x48;
+/*
+ * EBR
+00b001b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 87 |................|
+00b001c0 07 01 0e a7 26 01 00 08 00 00 00 08 00 00 00 00 |....&...........|
+00b001d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
+00b001e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
+00b001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 aa |..............U.|
+*/
+static unsigned char ebr_parts_ref_p5[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x87,
+0x07, 0x01, 0x0e, 0xa7, 0x26, 0x01, 0x00, 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0xaa
+};
+
+/* Fill write buffers with pseudo-random data */
+static void init_write_buffers(char *mbr_wb, size_t mbr_wb_size,
+ char *ebr_wb, size_t ebr_wb_size, unsigned seed)
+{
+ while (mbr_wb_size--) {
+ *mbr_wb++ = seed;
+ seed *= 43;
+ seed += 17 + mbr_wb_size/4;
+ }
+ while (ebr_wb_size--) {
+ *ebr_wb++ = seed;
+ seed *= 43;
+ seed += 17 + ebr_wb_size/4;
+ }
+}
+
+/* Build string with MBR partition(s) layout */
+static unsigned build_mbr_parts(char *buf, size_t buf_size, unsigned num_parts)
+{
+ size_t bytes_remaining, cur_str_size;
+ char * cur_buf;
+
+ if (!num_parts || num_parts > 5 || !buf)
+ return 1;
+
+ cur_buf = buf;
+ *cur_buf = '\0';
+ bytes_remaining = buf_size;
+
+ cur_str_size = sizeof(mbr_parts_header);
+ if (cur_str_size + 1 > bytes_remaining)
+ return 1;
+ strcat(cur_buf, mbr_parts_header);
+ bytes_remaining -= cur_str_size;
+
+ if (num_parts >= 1) {
+ cur_str_size = sizeof(mbr_parts_p1);
+ if (cur_str_size + 1 > bytes_remaining)
+ return 1;
+ strcat(cur_buf, mbr_parts_p1);
+ bytes_remaining -= cur_str_size;
+
+ if (num_parts >= 2) {
+ cur_str_size = sizeof(mbr_parts_p2);
+ if (cur_str_size + 1 > bytes_remaining)
+ return 1;
+ strcat(cur_buf, mbr_parts_p2);
+ bytes_remaining -= cur_str_size;
+
+ if (num_parts >= 3) {
+ cur_str_size = sizeof(mbr_parts_p3);
+ if (cur_str_size + 1 > bytes_remaining)
+ return 1;
+ strcat(cur_buf, mbr_parts_p3);
+ bytes_remaining -= cur_str_size;
+
+ if (num_parts == 4) {
+ cur_str_size = sizeof(mbr_parts_p4);
+ if (cur_str_size + 1 > bytes_remaining)
+ return 1;
+ strcat(cur_buf, mbr_parts_p4);
+ bytes_remaining -= cur_str_size;
+
+ }
+ else if (num_parts == 5) {
+ cur_str_size = sizeof(mbr_parts_p5);
+ if (cur_str_size + 1 > bytes_remaining)
+ return 1;
+ strcat(cur_buf, mbr_parts_p5);
+ bytes_remaining -= cur_str_size;
+
+ }
+ }
+ }
+ }
+
+ cur_str_size = sizeof(mbr_parts_tail);
+ if (cur_str_size + 1 > bytes_remaining)
+ return 1;
+ strcat(cur_buf, mbr_parts_tail);
+
+ return 0;
+}
+
+static int mbr_test_run(struct unit_test_state *uts)
+{
+ struct blk_desc *mmc_dev_desc;
+ unsigned char mbr_wbuf[512], ebr_wbuf[512], rbuf[512];
+ char mbr_parts_buf[256];
+ ulong mbr_wa, ebr_wa, ra, ebr_blk, mbr_parts_max;
+ struct udevice *dev;
+ ofnode root, node;
+
+ /* Enable the mmc6 node for this test */
+ root = oftree_root(oftree_default());
+ node = ofnode_find_subnode(root, "mmc6");
+ ut_assert(ofnode_valid(node));
+ ut_assertok(lists_bind_fdt(gd->dm_root, node, &dev, NULL, false));
+
+ mbr_parts_max = sizeof('\0') + 2 +
+ strlen(mbr_parts_header) +
+ strlen(mbr_parts_p1) +
+ strlen(mbr_parts_p2) +
+ strlen(mbr_parts_p3) +
+ max(strlen(mbr_parts_p4), strlen(mbr_parts_p5)) +
+ strlen(mbr_parts_tail);
+ ut_assertf(sizeof(mbr_parts_buf) >= mbr_parts_max, "Buffer avail: %ld; buffer req: %ld\n",
+ sizeof(mbr_parts_buf), mbr_parts_max);
+
+ mbr_wa = map_to_sysmem(mbr_wbuf);
+ ebr_wa = map_to_sysmem(ebr_wbuf);
+ ra = map_to_sysmem(rbuf);
+ ebr_blk = (ulong)0xB00000 / 0x200;
+
+ /* Make sure mmc6 exists */
+ ut_asserteq(6, blk_get_device_by_str("mmc", "6", &mmc_dev_desc));
+ ut_assertok(console_record_reset_enable());
+ ut_assertok(run_commandf("mmc dev 6"));
+ ut_assert_nextline("switch to partitions #0, OK");
+ ut_assert_nextline("mmc6 is current device");
+ ut_assertok(ut_check_console_end(uts));
+
+ /* Make sure mmc6 is 12+ MiB in size */
+ ut_assertok(run_commandf("mmc read 0x%lx 0x%lx 1", ra, (ulong)0xBFFE00 / 0x200));
+
+ /* Test one MBR partition */
+ init_write_buffers(mbr_wbuf, sizeof(mbr_wbuf), ebr_wbuf, sizeof(ebr_wbuf), __LINE__);
+ ut_assertok(build_mbr_parts(mbr_parts_buf, sizeof(mbr_parts_buf), 1));
+ ut_assertok(run_commandf("write mmc 6:0 0x%lx 0 1", mbr_wa));
+ memset(rbuf, 0, sizeof(rbuf));
+ ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra));
+ ut_assertok(memcmp(mbr_wbuf, rbuf, 512));
+ ut_assertok(run_commandf("write mmc 6:0 0x%lx 0x%lx 1", ebr_wa, ebr_blk));
+ memset(rbuf, 0, sizeof(rbuf));
+ ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
+ ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
+ ut_assertok(console_record_reset_enable());
+ ut_assertf(0 == run_commandf(mbr_parts_buf), "Invalid partitions string: %s\n", mbr_parts_buf);
+ ut_assertok(run_commandf("mbr write mmc 6"));
+ ut_assert_nextline("MBR: write success!");
+ ut_assertok(run_commandf("mbr verify mmc 6"));
+ ut_assert_nextline("MBR: verify success!");
+ memset(rbuf, 0, sizeof(rbuf));
+ ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
+ ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
+ ut_assertok(ut_check_console_end(uts));
+ /*
+ 000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....|
+ 000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 00 |...%$..@........|
+ 000001d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
+ 000001e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
+ 000001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 aa |..............U.|
+ */
+ memset(rbuf, 0, sizeof(rbuf));
+ ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra));
+ for (unsigned i = 0; i < mbr_cmp_size; i++) {
+ ut_assertf(rbuf[mbr_cmp_start + i] == mbr_parts_ref_p1[i],
+ "1P MBR+0x%04X: expected 0x%02X, actual: 0x%02X\n",
+ mbr_cmp_start + i, mbr_parts_ref_p1[i], rbuf[mbr_cmp_start + i]);
+ }
+
+ /* Test two MBR partitions */
+ init_write_buffers(mbr_wbuf, sizeof(mbr_wbuf), ebr_wbuf, sizeof(ebr_wbuf), __LINE__);
+ ut_assertok(build_mbr_parts(mbr_parts_buf, sizeof(mbr_parts_buf), 2));
+ ut_assertok(run_commandf("write mmc 6:0 0x%lx 0 1", mbr_wa));
+ memset(rbuf, 0, sizeof(rbuf));
+ ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra));
+ ut_assertok(memcmp(mbr_wbuf, rbuf, 512));
+ ut_assertok(run_commandf("write mmc 6:0 0x%lx 0x%lx 1", ebr_wa, ebr_blk));
+ memset(rbuf, 0, sizeof(rbuf));
+ ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
+ ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
+ ut_assertok(console_record_reset_enable());
+ ut_assertf(0 == run_commandf(mbr_parts_buf), "Invalid partitions string: %s\n", mbr_parts_buf);
+ ut_assertok(run_commandf("mbr write mmc 6"));
+ ut_assert_nextline("MBR: write success!");
+ ut_assertok(run_commandf("mbr verify mmc 6"));
+ ut_assert_nextline("MBR: verify success!");
+ memset(rbuf, 0, sizeof(rbuf));
+ ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
+ ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
+ ut_assertok(ut_check_console_end(uts));
+ /*
+ 000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....|
+ 000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%|
+ 000001d0 25 01 0e 46 05 01 00 48 00 00 00 08 00 00 00 00 |%..F...H........|
+ 000001e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
+ 000001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 aa |..............U.|
+ */
+ memset(rbuf, 0, sizeof(rbuf));
+ ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra));
+ for (unsigned i = 0; i < mbr_cmp_size; i++) {
+ ut_assertf(rbuf[mbr_cmp_start + i] == mbr_parts_ref_p2[i],
+ "2P MBR+0x%04X: expected 0x%02X, actual: 0x%02X\n",
+ mbr_cmp_start + i, mbr_parts_ref_p2[i], rbuf[mbr_cmp_start + i]);
+ }
+
+ /* Test three MBR partitions */
+ init_write_buffers(mbr_wbuf, sizeof(mbr_wbuf), ebr_wbuf, sizeof(ebr_wbuf), __LINE__);
+ ut_assertok(build_mbr_parts(mbr_parts_buf, sizeof(mbr_parts_buf), 3));
+ ut_assertok(run_commandf("write mmc 6:0 0x%lx 0 1", mbr_wa));
+ memset(rbuf, 0, sizeof(rbuf));
+ ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra));
+ ut_assertok(memcmp(mbr_wbuf, rbuf, 512));
+ ut_assertok(run_commandf("write mmc 6:0 0x%lx 0x%lx 1", ebr_wa, ebr_blk));
+ memset(rbuf, 0, sizeof(rbuf));
+ ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
+ ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
+ ut_assertok(console_record_reset_enable());
+ ut_assertf(0 == run_commandf(mbr_parts_buf), "Invalid partitions string: %s\n", mbr_parts_buf);
+ ut_assertok(run_commandf("mbr write mmc 6"));
+ ut_assert_nextline("MBR: write success!");
+ ut_assertok(run_commandf("mbr verify mmc 6"));
+ ut_assert_nextline("MBR: verify success!");
+ memset(rbuf, 0, sizeof(rbuf));
+ ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
+ ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
+ ut_assertok(ut_check_console_end(uts));
+ /*
+ 000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....|
+ 000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%|
+ 000001d0 25 01 0e 46 05 01 00 48 00 00 00 08 00 00 00 46 |%..F...H.......F|
+ 000001e0 06 01 0e 66 25 01 00 50 00 00 00 08 00 00 00 00 |...f%..P........|
+ 000001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 aa |..............U.|
+ */
+ memset(rbuf, 0, sizeof(rbuf));
+ ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra));
+ for (unsigned i = 0; i < mbr_cmp_size; i++) {
+ ut_assertf(rbuf[mbr_cmp_start + i] == mbr_parts_ref_p3[i],
+ "3P MBR+0x%04X: expected 0x%02X, actual: 0x%02X\n",
+ mbr_cmp_start + i, mbr_parts_ref_p3[i], rbuf[mbr_cmp_start + i]);
+ }
+
+ /* Test four MBR partitions */
+ init_write_buffers(mbr_wbuf, sizeof(mbr_wbuf), ebr_wbuf, sizeof(ebr_wbuf), __LINE__);
+ ut_assertok(build_mbr_parts(mbr_parts_buf, sizeof(mbr_parts_buf), 4));
+ ut_assertok(run_commandf("write mmc 6:0 0x%lx 0 1", mbr_wa));
+ memset(rbuf, 0, sizeof(rbuf));
+ ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra));
+ ut_assertok(memcmp(mbr_wbuf, rbuf, 512));
+ ut_assertok(run_commandf("write mmc 6:0 0x%lx 0x%lx 1", ebr_wa, ebr_blk));
+ memset(rbuf, 0, sizeof(rbuf));
+ ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
+ ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
+ ut_assertok(console_record_reset_enable());
+ ut_assertf(0 == run_commandf(mbr_parts_buf), "Invalid partitions string: %s\n", mbr_parts_buf);
+ ut_assertok(run_commandf("mbr write mmc 6"));
+ ut_assert_nextline("MBR: write success!");
+ ut_assertok(run_commandf("mbr verify mmc 6"));
+ ut_assert_nextline("MBR: verify success!");
+ memset(rbuf, 0, sizeof(rbuf));
+ ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
+ ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
+ ut_assertok(ut_check_console_end(uts));
+ /*
+ 000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....|
+ 000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%|
+ 000001d0 25 01 0e 46 05 01 00 48 00 00 00 08 00 00 00 46 |%..F...H.......F|
+ 000001e0 06 01 0e 66 25 01 00 50 00 00 00 08 00 00 00 66 |...f%..P.......f|
+ 000001f0 26 01 0e 87 06 01 00 58 00 00 00 08 00 00 55 aa |&......X......U.|
+ */
+ memset(rbuf, 0, sizeof(rbuf));
+ ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra));
+ for (unsigned i = 0; i < mbr_cmp_size; i++) {
+ ut_assertf(rbuf[mbr_cmp_start + i] == mbr_parts_ref_p4[i],
+ "4P MBR+0x%04X: expected 0x%02X, actual: 0x%02X\n",
+ mbr_cmp_start + i, mbr_parts_ref_p4[i], rbuf[mbr_cmp_start + i]);
+ }
+
+ /* Test five MBR partitions */
+ init_write_buffers(mbr_wbuf, sizeof(mbr_wbuf), ebr_wbuf, sizeof(ebr_wbuf), __LINE__);
+ ut_assertok(build_mbr_parts(mbr_parts_buf, sizeof(mbr_parts_buf), 5));
+ ut_assertok(run_commandf("write mmc 6:0 0x%lx 0 1", mbr_wa));
+ memset(rbuf, 0, sizeof(rbuf));
+ ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra));
+ ut_assertok(memcmp(mbr_wbuf, rbuf, 512));
+ ut_assertok(run_commandf("write mmc 6:0 0x%lx 0x%lx 1", ebr_wa, ebr_blk));
+ memset(rbuf, 0, sizeof(rbuf));
+ ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
+ ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
+ ut_assertok(console_record_reset_enable());
+ ut_assertf(0 == run_commandf(mbr_parts_buf), "Invalid partitions string: %s\n", mbr_parts_buf);
+ ut_assertf(0 == run_commandf("mbr write mmc 6"), "Invalid partitions string: %s\n", mbr_parts_buf);
+ ut_assert_nextline("MBR: write success!");
+ ut_assertok(run_commandf("mbr verify mmc 6"));
+ ut_assert_nextline("MBR: verify success!");
+ ut_assertok(ut_check_console_end(uts));
+ /*
+ 000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....|
+ 000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%|
+ 000001d0 25 01 0e 46 05 01 00 48 00 00 00 08 00 00 00 46 |%..F...H.......F|
+ 000001e0 06 01 0e 66 25 01 00 50 00 00 00 08 00 00 00 66 |...f%..P.......f|
+ 000001f0 26 01 05 a7 26 01 00 58 00 00 00 10 00 00 55 aa |&...&..X......U.|
+ */
+ memset(rbuf, 0, sizeof(rbuf));
+ ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra));
+ for (unsigned i = 0; i < mbr_cmp_size; i++) {
+ ut_assertf(rbuf[mbr_cmp_start + i] == mbr_parts_ref_p5[i],
+ "5P MBR+0x%04X: expected 0x%02X, actual: 0x%02X\n",
+ mbr_cmp_start + i, mbr_parts_ref_p5[i], rbuf[mbr_cmp_start + i]);
+ }
+ /*
+ 00b001b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 87 |................|
+ 00b001c0 07 01 0e a7 26 01 00 08 00 00 00 08 00 00 00 00 |....&...........|
+ 00b001d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
+ 00b001e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
+ 00b001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 aa |..............U.|
+ */
+ memset(rbuf, 0, sizeof(rbuf));
+ ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
+ for (unsigned i = 0; i < ebr_cmp_size; i++) {
+ ut_assertf(rbuf[ebr_cmp_start + i] == ebr_parts_ref_p5[i],
+ "5P EBR+0x%04X: expected 0x%02X, actual: 0x%02X\n",
+ ebr_cmp_start + i, ebr_parts_ref_p5[i], rbuf[ebr_cmp_start + i]);
+ }
+
+ return 0;
+}
+
+/* Declare mbr test */
+UNIT_TEST(mbr_test_run, UT_TESTF_CONSOLE_REC, mbr_test);
+
+int do_ut_mbr(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ struct unit_test *tests = UNIT_TEST_SUITE_START(mbr_test);
+ const int n_ents = UNIT_TEST_SUITE_COUNT(mbr_test);
+
+ return cmd_ut_category("mbr", "mbr_test_", tests, n_ents, argc, argv);
+}
+
+static int dm_test_cmd_mbr(struct unit_test_state *uts)
+{
+ return mbr_test_run(uts);
+}
+
+DM_TEST(dm_test_cmd_mbr, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
diff --git a/test/cmd_ut.c b/test/cmd_ut.c
index 0cb5144..2d5b80f 100644
--- a/test/cmd_ut.c
+++ b/test/cmd_ut.c
@@ -87,6 +87,10 @@
#ifdef CONFIG_UT_LOG
U_BOOT_CMD_MKENT(log, CONFIG_SYS_MAXARGS, 1, do_ut_log, "", ""),
#endif
+#if defined(CONFIG_SANDBOX) && defined(CONFIG_CMD_MBR) && defined(CONFIG_CMD_MMC) \
+ && defined(CONFIG_MMC_SANDBOX) && defined(CONFIG_MMC_WRITE)
+ U_BOOT_CMD_MKENT(mbr, CONFIG_SYS_MAXARGS, 1, do_ut_mbr, "", ""),
+#endif
U_BOOT_CMD_MKENT(mem, CONFIG_SYS_MAXARGS, 1, do_ut_mem, "", ""),
#if defined(CONFIG_SANDBOX) && defined(CONFIG_CMD_SETEXPR)
U_BOOT_CMD_MKENT(setexpr, CONFIG_SYS_MAXARGS, 1, do_ut_setexpr, "",
@@ -99,6 +103,10 @@
#if CONFIG_IS_ENABLED(UT_UNICODE) && !defined(API_BUILD)
U_BOOT_CMD_MKENT(unicode, CONFIG_SYS_MAXARGS, 1, do_ut_unicode, "", ""),
#endif
+#ifdef CONFIG_MEASURED_BOOT
+ U_BOOT_CMD_MKENT(measurement, CONFIG_SYS_MAXARGS, 1, do_ut_measurement,
+ "", ""),
+#endif
#ifdef CONFIG_SANDBOX
U_BOOT_CMD_MKENT(compression, CONFIG_SYS_MAXARGS, 1, do_ut_compression,
"", ""),
@@ -166,8 +174,7 @@
return CMD_RET_USAGE;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char ut_help_text[] =
+U_BOOT_LONGHELP(ut,
"[-r] [-f] [<suite>] - run unit tests\n"
" -r<runs> Number of times to run each test\n"
" -f Force 'manual' tests to run as well\n"
@@ -201,7 +208,7 @@
"\nfdt - fdt command"
#endif
#ifdef CONFIG_CONSOLE_TRUETYPE
- "\nut font - font command"
+ "\nfont - font command"
#endif
#ifdef CONFIG_CMD_LOADM
"\nloadm - loadm command parameters and loading memory blob"
@@ -237,8 +244,7 @@
!defined(CONFIG_SPL_BUILD) && !defined(API_BUILD)
"\nunicode - Unicode functions"
#endif
- ;
-#endif /* CONFIG_SYS_LONGHELP */
+ );
U_BOOT_CMD(
ut, CONFIG_SYS_MAXARGS, 1, do_ut,
diff --git a/test/common/cread.c b/test/common/cread.c
index 2fdd29a..4edc773 100644
--- a/test/common/cread.c
+++ b/test/common/cread.c
@@ -43,6 +43,12 @@
ut_asserteq('a', cli_ch_process(cch, 'a'));
ut_asserteq(0, cli_ch_process(cch, 0));
+ /* unexpected 'Esc' */
+ ut_asserteq('a', cli_ch_process(cch, 'a'));
+ ut_asserteq(0, cli_ch_process(cch, '\e'));
+ ut_asserteq('b', cli_ch_process(cch, 'b'));
+ ut_asserteq(0, cli_ch_process(cch, 0));
+
return 0;
}
COMMON_TEST(cli_ch_test, 0);
@@ -80,6 +86,12 @@
ut_asserteq(7, cli_readline_into_buffer("-> ", buf, 1));
ut_asserteq_str("abc\e[Xx", buf);
+ /* unexpected 'Esc' */
+ *buf = '\0';
+ ut_asserteq(7, console_in_puts("abc\eXx\n"));
+ ut_asserteq(5, cli_readline_into_buffer("-> ", buf, 1));
+ ut_asserteq_str("abcXx", buf);
+
/* check timeout, should be between 1000 and 1050ms */
start = get_timer(0);
*buf = '\0';
diff --git a/test/common/event.c b/test/common/event.c
index 6037ae2..c0912a3 100644
--- a/test/common/event.c
+++ b/test/common/event.c
@@ -18,6 +18,8 @@
int val;
};
+static bool called;
+
static int h_adder(void *ctx, struct event *event)
{
struct event_data_test *data = &event->data.test;
@@ -28,6 +30,14 @@
return 0;
}
+static int h_adder_simple(void)
+{
+ called = true;
+
+ return 0;
+}
+EVENT_SPY_SIMPLE(EVT_TEST, h_adder_simple);
+
static int test_event_base(struct unit_test_state *uts)
{
struct test_state state;
@@ -46,6 +56,18 @@
}
COMMON_TEST(test_event_base, 0);
+static int test_event_simple(struct unit_test_state *uts)
+{
+ called = false;
+
+ /* Check that the handler is called */
+ ut_assertok(event_notify_null(EVT_TEST));
+ ut_assert(called);
+
+ return 0;
+}
+COMMON_TEST(test_event_simple, 0);
+
static int h_probe(void *ctx, struct event *event)
{
struct test_state *test_state = ctx;
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 7ed0073..cb82d83 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -100,6 +100,7 @@
obj-$(CONFIG_DM_RESET) += reset.o
obj-$(CONFIG_SYSRESET) += sysreset.o
obj-$(CONFIG_DM_REGULATOR) += regulator.o
+obj-$(CONFIG_CMD_RKMTD) += rkmtd.o
obj-$(CONFIG_DM_RNG) += rng.o
obj-$(CONFIG_DM_RTC) += rtc.o
obj-$(CONFIG_SCMI_FIRMWARE) += scmi.o
@@ -115,6 +116,7 @@
obj-$(CONFIG_SPMI) += spmi.o
obj-y += syscon.o
obj-$(CONFIG_RESET_SYSCON) += syscon-reset.o
+obj-$(CONFIG_SM) += sm.o
obj-$(CONFIG_SYSINFO) += sysinfo.o
obj-$(CONFIG_SYSINFO_GPIO) += sysinfo-gpio.o
obj-$(CONFIG_UT_DM) += tag.o
diff --git a/test/dm/acpi.c b/test/dm/acpi.c
index 77eb524..5997bda 100644
--- a/test/dm/acpi.c
+++ b/test/dm/acpi.c
@@ -221,7 +221,8 @@
ut_assertnonnull(cpu);
ut_assertok(acpi_create_dmar(&dmar, DMAR_INTR_REMAP));
ut_asserteq(DMAR_INTR_REMAP, dmar.flags);
- ut_asserteq(32 - 1, dmar.host_address_width);
+ ut_asserteq((IS_ENABLED(CONFIG_PHYS_64BIT) ? 64 : 32) - 1,
+ dmar.host_address_width);
return 0;
}
@@ -277,13 +278,16 @@
*/
ut_asserteq_ptr(dmar + 3, ctx.current);
ut_asserteq(DMAR_INTR_REMAP, dmar->flags);
- ut_asserteq(32 - 1, dmar->host_address_width);
+ ut_asserteq((IS_ENABLED(CONFIG_PHYS_64BIT) ? 64 : 32) - 1,
+ dmar->host_address_width);
ut_asserteq(DMAR_INTR_REMAP, dmar[1].flags);
- ut_asserteq(32 - 1, dmar[1].host_address_width);
+ ut_asserteq((IS_ENABLED(CONFIG_PHYS_64BIT) ? 64 : 32) - 1,
+ dmar[1].host_address_width);
ut_asserteq(DMAR_INTR_REMAP, dmar[2].flags);
- ut_asserteq(32 - 1, dmar[2].host_address_width);
+ ut_asserteq((IS_ENABLED(CONFIG_PHYS_64BIT) ? 64 : 32) - 1,
+ dmar[2].host_address_width);
/* Check that the pointers were added correctly */
for (i = 0; i < 3; i++) {
diff --git a/test/dm/blk.c b/test/dm/blk.c
index 446c442..799f1e4 100644
--- a/test/dm/blk.c
+++ b/test/dm/blk.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <blk.h>
#include <dm.h>
#include <part.h>
#include <sandbox_host.h>
@@ -22,8 +23,8 @@
struct udevice *blk0, *blk1, *dev0, *dev1, *dev, *chk0, *chk1;
/* Create two, one the parent of the other */
- ut_assertok(host_create_device("test0", false, &dev0));
- ut_assertok(host_create_device("test1", false, &dev1));
+ ut_assertok(host_create_device("test0", false, DEFAULT_BLKSZ, &dev0));
+ ut_assertok(host_create_device("test1", false, DEFAULT_BLKSZ, &dev1));
/* Check we can find them */
ut_assertok(blk_get_device(UCLASS_HOST, 0, &blk0));
@@ -99,7 +100,7 @@
{
struct udevice *blk, *chk, *dev;
- ut_assertok(host_create_device("test0", false, &dev));
+ ut_assertok(host_create_device("test0", false, DEFAULT_BLKSZ, &dev));
ut_assertok(blk_find_device(UCLASS_HOST, 0, &chk));
ut_assertok(device_find_first_child_by_uclass(dev, UCLASS_BLK, &blk));
diff --git a/test/dm/clk.c b/test/dm/clk.c
index f48de05..01417fb 100644
--- a/test/dm/clk.c
+++ b/test/dm/clk.c
@@ -36,6 +36,15 @@
ut_asserteq(clk_is_match(&clk_method1, &clk_method2), true);
ut_asserteq(clk_method1.id, clk_method2.id);
+ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test2", &dev));
+ ut_assertok(clk_set_defaults(dev, CLK_DEFAULTS_PRE));
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test3", &dev));
+ ut_assertok(clk_set_defaults(dev, CLK_DEFAULTS_PRE));
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test4", &dev));
+ ut_assertok(clk_set_defaults(dev, CLK_DEFAULTS_PRE));
+
return 0;
}
diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c
index e4ebb93..61dad8d 100644
--- a/test/dm/clk_ccf.c
+++ b/test/dm/clk_ccf.c
@@ -19,16 +19,18 @@
static int dm_test_clk_ccf(struct unit_test_state *uts)
{
struct clk *clk, *pclk;
- struct udevice *dev;
+ struct udevice *dev, *test_dev;
long long rate;
int ret;
#if CONFIG_IS_ENABLED(CLK_CCF)
+ struct clk clk_ccf;
const char *clkname;
int clkid, i;
#endif
/* Get the device using the clk device */
ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-ccf", &dev));
+ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test", &test_dev));
/* Test for clk_get_by_id() */
ret = clk_get_by_id(SANDBOX_CLK_ECSPI_ROOT, &clk);
@@ -63,6 +65,9 @@
rate = clk_get_parent_rate(clk);
ut_asserteq(rate, 60000000);
+ rate = clk_set_rate(clk, 60000000);
+ ut_asserteq(rate, -ENOSYS);
+
rate = clk_get_rate(clk);
ut_asserteq(rate, 60000000);
@@ -87,6 +92,9 @@
ut_asserteq_str("pll3_80m", pclk->dev->name);
ut_asserteq(CLK_SET_RATE_PARENT, pclk->flags);
+ rate = clk_set_rate(clk, 80000000);
+ ut_asserteq(rate, -ENOSYS);
+
rate = clk_get_rate(clk);
ut_asserteq(rate, 80000000);
@@ -108,13 +116,23 @@
rate = clk_get_rate(clk);
ut_asserteq(rate, 60000000);
+ rate = clk_set_rate(clk, 60000000);
+ ut_asserteq(rate, 60000000);
+
#if CONFIG_IS_ENABLED(CLK_CCF)
/* Test clk tree enable/disable */
+
+ ret = clk_get_by_index(test_dev, SANDBOX_CLK_TEST_ID_I2C_ROOT, &clk_ccf);
+ ut_assertok(ret);
+ ut_asserteq_str("clk-ccf", clk_ccf.dev->name);
+ ut_asserteq(clk_ccf.id, SANDBOX_CLK_I2C_ROOT);
+
ret = clk_get_by_id(SANDBOX_CLK_I2C_ROOT, &clk);
ut_assertok(ret);
ut_asserteq_str("i2c_root", clk->dev->name);
+ ut_asserteq(clk->id, SANDBOX_CLK_I2C_ROOT);
- ret = clk_enable(clk);
+ ret = clk_enable(&clk_ccf);
ut_assertok(ret);
ret = sandbox_clk_enable_count(clk);
diff --git a/test/dm/fwu_mdata.c b/test/dm/fwu_mdata.c
index 8b5c83e..52018f6 100644
--- a/test/dm/fwu_mdata.c
+++ b/test/dm/fwu_mdata.c
@@ -93,6 +93,12 @@
struct udevice *dev;
struct fwu_mdata mdata = { 0 };
+ /*
+ * Trigger lib/fwu_updates/fwu.c fwu_boottime_checks()
+ * to populate g_dev global pointer in that library.
+ */
+ event_notify_null(EVT_MAIN_LOOP);
+
ut_assertok(uclass_first_device_err(UCLASS_FWU_MDATA, &dev));
ut_assertok(setup_blk_device(uts));
ut_assertok(populate_mmc_disk_image(uts));
@@ -112,6 +118,12 @@
struct udevice *dev;
struct fwu_mdata mdata = { 0 };
+ /*
+ * Trigger lib/fwu_updates/fwu.c fwu_boottime_checks()
+ * to populate g_dev global pointer in that library.
+ */
+ event_notify_null(EVT_MAIN_LOOP);
+
ut_assertok(setup_blk_device(uts));
ut_assertok(populate_mmc_disk_image(uts));
ut_assertok(write_mmc_blk_device(uts));
diff --git a/test/dm/host.c b/test/dm/host.c
index 355ba77..ca05a36 100644
--- a/test/dm/host.c
+++ b/test/dm/host.c
@@ -8,6 +8,7 @@
#include <blk.h>
#include <dm.h>
#include <fs.h>
+#include <os.h>
#include <sandbox_host.h>
#include <asm/test.h>
#include <dm/device-internal.h>
@@ -15,9 +16,6 @@
#include <test/test.h>
#include <test/ut.h>
-static const char filename[] = "2MB.ext2.img";
-static const char filename2[] = "1MB.fat32.img";
-
/* Basic test of host interface */
static int dm_test_host(struct unit_test_state *uts)
{
@@ -25,6 +23,7 @@
struct udevice *dev, *part, *chk, *blk;
struct host_sb_plat *plat;
struct blk_desc *desc;
+ char fname[256];
ulong mem_start;
loff_t actwrite;
@@ -32,7 +31,7 @@
ut_asserteq(-ENODEV, uclass_first_device_err(UCLASS_PARTITION, &part));
mem_start = ut_check_delta(0);
- ut_assertok(host_create_device(label, true, &dev));
+ ut_assertok(host_create_device(label, true, DEFAULT_BLKSZ, &dev));
/* Check that the plat data has been allocated */
plat = dev_get_plat(dev);
@@ -40,13 +39,15 @@
ut_assert(label != plat->label);
ut_asserteq(0, plat->fd);
- /* Attach a file created in test_host.py */
- ut_assertok(host_attach_file(dev, filename));
+ /* Attach a file created in test_ut_dm_init */
+ ut_assertok(os_persistent_file(fname, sizeof(fname), "2MB.ext2.img"));
+
+ ut_assertok(host_attach_file(dev, fname));
ut_assertok(uclass_first_device_err(UCLASS_HOST, &chk));
ut_asserteq_ptr(chk, dev);
- ut_asserteq_str(filename, plat->filename);
- ut_assert(filename != plat->filename);
+ ut_asserteq_str(fname, plat->filename);
+ ut_assert(fname != plat->filename);
ut_assert(plat->fd != 0);
/* Get the block device */
@@ -79,21 +80,25 @@
{
static char label[] = "test";
struct udevice *dev, *chk;
+ char fname[256];
ut_asserteq(0, uclass_id_count(UCLASS_HOST));
- ut_assertok(host_create_device(label, true, &dev));
+ ut_assertok(host_create_device(label, true, DEFAULT_BLKSZ, &dev));
- /* Attach a file created in test_host.py */
- ut_assertok(host_attach_file(dev, filename));
+ /* Attach a file created in test_ut_dm_init */
+ ut_assertok(os_persistent_file(fname, sizeof(fname), "2MB.ext2.img"));
+ ut_assertok(host_attach_file(dev, fname));
ut_assertok(uclass_first_device_err(UCLASS_HOST, &chk));
ut_asserteq_ptr(chk, dev);
ut_asserteq(1, uclass_id_count(UCLASS_HOST));
/* Create another device with the same label (should remove old one) */
- ut_assertok(host_create_device(label, true, &dev));
+ ut_assertok(host_create_device(label, true, DEFAULT_BLKSZ, &dev));
- /* Attach a different file created in test_host.py */
- ut_assertok(host_attach_file(dev, filename2));
+ /* Attach a different file created in test_ut_dm_init */
+ ut_assertok(os_persistent_file(fname, sizeof(fname), "1MB.fat32.img"));
+ ut_assertok(host_attach_file(dev, fname));
+
ut_assertok(uclass_first_device_err(UCLASS_HOST, &chk));
ut_asserteq_ptr(chk, dev);
@@ -109,15 +114,17 @@
{
struct udevice *dev, *blk;
struct blk_desc *desc;
+ char fname[256];
console_record_reset();
/* first check 'host info' with binding */
ut_assertok(run_command("host info", 0));
- ut_assert_nextline("dev blocks label path");
+ ut_assert_nextline("dev blocks blksz label path");
ut_assert_console_end();
- ut_assertok(run_commandf("host bind -r test2 %s", filename));
+ ut_assertok(os_persistent_file(fname, sizeof(fname), "2MB.ext2.img"));
+ ut_assertok(run_commandf("host bind -r test2 %s", fname));
/* Check the -r flag worked */
ut_assertok(uclass_first_device_err(UCLASS_HOST, &dev));
@@ -126,11 +133,12 @@
ut_asserteq(true, desc->removable);
ut_assertok(run_command("host info", 0));
- ut_assert_nextline("dev blocks label path");
- ut_assert_nextline(" 0 4096 test2 2MB.ext2.img");
+ ut_assert_nextline("dev blocks blksz label path");
+ ut_assert_nextlinen(" 0 4096 512 test2");
ut_assert_console_end();
- ut_assertok(run_commandf("host bind fat %s", filename2));
+ ut_assertok(os_persistent_file(fname, sizeof(fname), "1MB.fat32.img"));
+ ut_assertok(run_commandf("host bind fat %s", fname));
/* Check it is not removable (no '-r') */
ut_assertok(uclass_next_device_err(&dev));
@@ -139,9 +147,9 @@
ut_asserteq(false, desc->removable);
ut_assertok(run_command("host info", 0));
- ut_assert_nextline("dev blocks label path");
- ut_assert_nextline(" 0 4096 test2 2MB.ext2.img");
- ut_assert_nextline(" 1 2048 fat 1MB.fat32.img");
+ ut_assert_nextline("dev blocks blksz label path");
+ ut_assert_nextlinen(" 0 4096 512 test2");
+ ut_assert_nextlinen(" 1 2048 512 fat");
ut_assert_console_end();
ut_asserteq(1, run_command("host info test", 0));
@@ -149,8 +157,8 @@
ut_assert_console_end();
ut_assertok(run_command("host info fat", 0));
- ut_assert_nextline("dev blocks label path");
- ut_assert_nextline(" 1 2048 fat 1MB.fat32.img");
+ ut_assert_nextline("dev blocks blksz label path");
+ ut_assert_nextlinen(" 1 2048 512 fat");
ut_assert_console_end();
/* check 'host dev' */
@@ -186,8 +194,8 @@
ut_assert_console_end();
ut_assertok(run_command("host info", 0));
- ut_assert_nextline("dev blocks label path");
- ut_assert_nextline(" 1 2048 fat 1MB.fat32.img");
+ ut_assert_nextline("dev blocks blksz label path");
+ ut_assert_nextlinen(" 1 2048 512 fat");
ut_assert_console_end();
return 0;
diff --git a/test/dm/mux-emul.c b/test/dm/mux-emul.c
index 58233ed..c6aeeb7 100644
--- a/test/dm/mux-emul.c
+++ b/test/dm/mux-emul.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
* Pratyush Yadav <p.yadav@ti.com>
*/
#include <common.h>
diff --git a/test/dm/mux-mmio.c b/test/dm/mux-mmio.c
index fd353d8..27c881d 100644
--- a/test/dm/mux-mmio.c
+++ b/test/dm/mux-mmio.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/test/dm/nop.c b/test/dm/nop.c
index 75b9e7b..f7d9a0f 100644
--- a/test/dm/nop.c
+++ b/test/dm/nop.c
@@ -2,7 +2,7 @@
/*
* Test for the NOP uclass
*
- * (C) Copyright 2019 - Texas Instruments Incorporated - http://www.ti.com/
+ * (C) Copyright 2019 - Texas Instruments Incorporated - https://www.ti.com/
* Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/test/dm/nvmxip.c b/test/dm/nvmxip.c
index 89bf481..f0ad47d 100644
--- a/test/dm/nvmxip.c
+++ b/test/dm/nvmxip.c
@@ -103,6 +103,8 @@
void *buffer = NULL;
unsigned long flashsz;
+ sandbox_set_enable_memio(true);
+
/* set the flash content first for both devices */
dm_nvmxip_flash_sanity(uts, 0, NULL);
dm_nvmxip_flash_sanity(uts, 1, NULL);
diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c
index 6fbebc7..a5bc43a 100644
--- a/test/dm/ofnode.c
+++ b/test/dm/ofnode.c
@@ -17,6 +17,7 @@
*/
#include <common.h>
+#include <abuf.h>
#include <dm.h>
#include <log.h>
#include <of_live.h>
@@ -26,6 +27,7 @@
#include <dm/root.h>
#include <dm/test.h>
#include <dm/uclass-internal.h>
+#include <linux/sizes.h>
#include <test/test.h>
#include <test/ut.h>
@@ -91,6 +93,7 @@
free(tree.np);
}
+/* test ofnode_device_is_compatible() */
static int dm_test_ofnode_compatible(struct unit_test_state *uts)
{
ofnode root_node = ofnode_path("/");
@@ -114,7 +117,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_compatible_ot, UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_compatible_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
static int dm_test_ofnode_get_by_phandle(struct unit_test_state *uts)
{
@@ -134,6 +137,7 @@
}
DM_TEST(dm_test_ofnode_get_by_phandle, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+/* test oftree_get_by_phandle() with a the 'other' oftree */
static int dm_test_ofnode_get_by_phandle_ot(struct unit_test_state *uts)
{
oftree otree = get_other_oftree(uts);
@@ -146,7 +150,8 @@
return 0;
}
-DM_TEST(dm_test_ofnode_get_by_phandle_ot, UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_get_by_phandle_ot,
+ UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
static int check_prop_values(struct unit_test_state *uts, ofnode start,
const char *propname, const char *propval,
@@ -187,6 +192,7 @@
}
DM_TEST(dm_test_ofnode_by_prop_value, UT_TESTF_SCAN_FDT);
+/* test ofnode_by_prop_value() with a the 'other' oftree */
static int dm_test_ofnode_by_prop_value_ot(struct unit_test_state *uts)
{
oftree otree = get_other_oftree(uts);
@@ -196,8 +202,10 @@
return 0;
}
-DM_TEST(dm_test_ofnode_by_prop_value_ot, UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_by_prop_value_ot,
+ UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+/* test ofnode_read_fmap_entry() */
static int dm_test_ofnode_fmap(struct unit_test_state *uts)
{
struct fmap_entry entry;
@@ -213,12 +221,16 @@
}
DM_TEST(dm_test_ofnode_fmap, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+/* test ofnode_read_prop() */
static int dm_test_ofnode_read(struct unit_test_state *uts)
{
const u32 *val;
ofnode node;
int size;
+ node = oftree_path(oftree_default(), "/");
+ ut_assert(ofnode_valid(node));
+
node = ofnode_path("/a-test");
ut_assert(ofnode_valid(node));
@@ -237,8 +249,9 @@
return 0;
}
-DM_TEST(dm_test_ofnode_read, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_read, UT_TESTF_SCAN_FDT);
+/* test ofnode_read_prop() with the 'other' tree */
static int dm_test_ofnode_read_ot(struct unit_test_state *uts)
{
oftree otree = get_other_oftree(uts);
@@ -246,6 +259,9 @@
ofnode node;
int size;
+ node = oftree_path(otree, "/");
+ ut_assert(ofnode_valid(node));
+
node = oftree_path(otree, "/node/subnode");
ut_assert(ofnode_valid(node));
@@ -256,8 +272,9 @@
return 0;
}
-DM_TEST(dm_test_ofnode_read_ot, UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_read_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+/* test ofnode_count_/parse_phandle_with_args() */
static int dm_test_ofnode_phandle(struct unit_test_state *uts)
{
struct ofnode_phandle_args args;
@@ -333,6 +350,7 @@
}
DM_TEST(dm_test_ofnode_phandle, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+/* test ofnode_count_/parse_phandle_with_args() with 'other' tree */
static int dm_test_ofnode_phandle_ot(struct unit_test_state *uts)
{
oftree otree = get_other_oftree(uts);
@@ -361,6 +379,7 @@
}
DM_TEST(dm_test_ofnode_phandle_ot, UT_TESTF_OTHER_FDT);
+/* test ofnode_read_chosen_string/node/prop() */
static int dm_test_ofnode_read_chosen(struct unit_test_state *uts)
{
const char *str;
@@ -390,6 +409,7 @@
}
DM_TEST(dm_test_ofnode_read_chosen, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+/* test ofnode_get_aliases_node/prop() */
static int dm_test_ofnode_read_aliases(struct unit_test_state *uts)
{
const void *val;
@@ -433,6 +453,7 @@
DM_TEST(dm_test_ofnode_get_child_count,
UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+/* test ofnode_get_child_count() with 'other' tree */
static int dm_test_ofnode_get_child_count_ot(struct unit_test_state *uts)
{
oftree otree = get_other_oftree(uts);
@@ -452,7 +473,8 @@
return 0;
}
-DM_TEST(dm_test_ofnode_get_child_count_ot, UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_get_child_count_ot,
+ UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
static int dm_test_ofnode_is_enabled(struct unit_test_state *uts)
{
@@ -466,6 +488,7 @@
}
DM_TEST(dm_test_ofnode_is_enabled, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+/* test ofnode_is_enabled() with 'other' tree */
static int dm_test_ofnode_is_enabled_ot(struct unit_test_state *uts)
{
oftree otree = get_other_oftree(uts);
@@ -479,6 +502,7 @@
}
DM_TEST(dm_test_ofnode_is_enabled_ot, UT_TESTF_OTHER_FDT);
+/* test ofnode_get_addr/size() */
static int dm_test_ofnode_get_reg(struct unit_test_state *uts)
{
ofnode node;
@@ -515,6 +539,7 @@
}
DM_TEST(dm_test_ofnode_get_reg, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+/* test ofnode_get_addr() with 'other' tree */
static int dm_test_ofnode_get_reg_ot(struct unit_test_state *uts)
{
oftree otree = get_other_oftree(uts);
@@ -526,7 +551,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_get_reg_ot, UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_get_reg_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
static int dm_test_ofnode_get_path(struct unit_test_state *uts)
{
@@ -549,6 +574,7 @@
}
DM_TEST(dm_test_ofnode_get_path, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+/* test ofnode_get_path() with 'other' tree */
static int dm_test_ofnode_get_path_ot(struct unit_test_state *uts)
{
oftree otree = get_other_oftree(uts);
@@ -566,8 +592,9 @@
return 0;
}
-DM_TEST(dm_test_ofnode_get_path_ot, UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_get_path_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+/* test ofnode_conf_read_bool/int/str() */
static int dm_test_ofnode_conf(struct unit_test_state *uts)
{
ut_assert(!ofnode_conf_read_bool("missing"));
@@ -581,7 +608,26 @@
return 0;
}
-DM_TEST(dm_test_ofnode_conf, 0);
+DM_TEST(dm_test_ofnode_conf, UT_TESTF_SCAN_FDT);
+
+static int dm_test_ofnode_options(struct unit_test_state *uts)
+{
+ u64 bootscr_address, bootscr_offset;
+ u64 bootscr_flash_offset, bootscr_flash_size;
+
+ ut_assertok(ofnode_read_bootscript_address(&bootscr_address,
+ &bootscr_offset));
+ ut_asserteq_64(0, bootscr_address);
+ ut_asserteq_64(0x12345678, bootscr_offset);
+
+ ut_assertok(ofnode_read_bootscript_flash(&bootscr_flash_offset,
+ &bootscr_flash_size));
+ ut_asserteq_64(0, bootscr_flash_offset);
+ ut_asserteq_64(0x2000, bootscr_flash_size);
+
+ return 0;
+}
+DM_TEST(dm_test_ofnode_options, 0);
static int dm_test_ofnode_for_each_compatible_node(struct unit_test_state *uts)
{
@@ -601,6 +647,7 @@
}
DM_TEST(dm_test_ofnode_for_each_compatible_node, UT_TESTF_SCAN_FDT);
+/* test dm_test_ofnode_string_count/index/list() */
static int dm_test_ofnode_string(struct unit_test_state *uts)
{
const char **val;
@@ -646,8 +693,9 @@
return 0;
}
-DM_TEST(dm_test_ofnode_string, 0);
+DM_TEST(dm_test_ofnode_string, UT_TESTF_SCAN_FDT);
+/* test error returns from ofnode_read_string_count/index/list() */
static int dm_test_ofnode_string_err(struct unit_test_state *uts)
{
const char **val;
@@ -697,7 +745,7 @@
}
DM_TEST(dm_test_ofnode_string_err, UT_TESTF_LIVE_TREE);
-static int dm_test_ofnode_get_phy(struct unit_test_state *uts)
+static int dm_test_ofnode_read_phy_mode(struct unit_test_state *uts)
{
ofnode eth_node, phy_node;
phy_interface_t mode;
@@ -717,7 +765,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_get_phy, 0);
+DM_TEST(dm_test_ofnode_read_phy_mode, UT_TESTF_SCAN_FDT);
/**
* make_ofnode_fdt() - Create an FDT for testing with ofnode
@@ -751,11 +799,11 @@
return 0;
}
-static int dm_test_ofnode_root(struct unit_test_state *uts)
+/* Check that aliases work on the control FDT */
+static int dm_test_ofnode_aliases(struct unit_test_state *uts)
{
ofnode node;
- /* Check that aliases work on the control FDT */
node = ofnode_get_aliases_node("ethernet3");
ut_assert(ofnode_valid(node));
ut_asserteq_str("sbe5", ofnode_get_name(node));
@@ -764,8 +812,15 @@
return 0;
}
-DM_TEST(dm_test_ofnode_root, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_aliases, UT_TESTF_SCAN_FDT);
+/**
+ * dm_test_ofnode_root_mult() - Check aliaes on control and 'other' tree
+ *
+ * Check that aliases work only with the control FDT, not with 'other' tree.
+ * This is not actually the desired behaviour. If aliases are implemented for
+ * any tree, then this test should be changed.
+ */
static int dm_test_ofnode_root_mult(struct unit_test_state *uts)
{
char fdt[256];
@@ -798,6 +853,7 @@
}
DM_TEST(dm_test_ofnode_root_mult, UT_TESTF_SCAN_FDT);
+/* test ofnode_set_enabled(), ofnode_write_prop() on a livetree */
static int dm_test_ofnode_livetree_writing(struct unit_test_state *uts)
{
struct udevice *dev;
@@ -887,6 +943,7 @@
}
DM_TEST(dm_test_ofnode_write_copy, UT_TESTF_SCAN_FDT);
+/* test writing a property to the 'other' tree */
static int dm_test_ofnode_write_copy_ot(struct unit_test_state *uts)
{
oftree otree = get_other_oftree(uts);
@@ -901,8 +958,9 @@
return 0;
}
-DM_TEST(dm_test_ofnode_write_copy_ot, UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_write_copy_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+/* test ofnode_read_u32_index/default() */
static int dm_test_ofnode_u32(struct unit_test_state *uts)
{
ofnode node;
@@ -930,6 +988,7 @@
}
DM_TEST(dm_test_ofnode_u32, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+/* test ofnode_read_u32_array() */
static int dm_test_ofnode_u32_array(struct unit_test_state *uts)
{
ofnode node;
@@ -956,6 +1015,7 @@
}
DM_TEST(dm_test_ofnode_u32_array, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+/* test ofnode_read_u64() and ofnode_write_u64() */
static int dm_test_ofnode_u64(struct unit_test_state *uts)
{
ofnode node;
@@ -965,8 +1025,26 @@
ut_assert(ofnode_valid(node));
ut_assertok(ofnode_read_u64(node, "int64-value", &val));
ut_asserteq_64(0x1111222233334444, val);
+ ut_assertok(ofnode_write_u64(node, "new-int64-value", 0x9876543210));
+ ut_assertok(ofnode_read_u64(node, "new-int64-value", &val));
+ ut_asserteq_64(0x9876543210, val);
+
ut_asserteq(-EINVAL, ofnode_read_u64(node, "missing", &val));
+ ut_assertok(ofnode_read_u64_index(node, "int64-array", 0, &val));
+ ut_asserteq_64(0x1111222233334444, val);
+ ut_assertok(ofnode_read_u64_index(node, "int64-array", 1, &val));
+ ut_asserteq_64(0x4444333322221111, val);
+ ut_asserteq(-EOVERFLOW,
+ ofnode_read_u64_index(node, "int64-array", 2, &val));
+ ut_asserteq(-EINVAL, ofnode_read_u64_index(node, "missing", 0, &val));
+
+ ut_assertok(ofnode_write_u64(node, "int64-array", 0x9876543210));
+ ut_assertok(ofnode_read_u64_index(node, "int64-array", 0, &val));
+ ut_asserteq_64(0x9876543210, val);
+ ut_asserteq(-EOVERFLOW,
+ ofnode_read_u64_index(node, "int64-array", 1, &val));
+
return 0;
}
DM_TEST(dm_test_ofnode_u64, UT_TESTF_SCAN_FDT);
@@ -1080,6 +1158,7 @@
}
DM_TEST(dm_test_ofnode_by_compatible, UT_TESTF_SCAN_FDT);
+/* check ofnode_by_compatible() on the 'other' tree */
static int dm_test_ofnode_by_compatible_ot(struct unit_test_state *uts)
{
const char *compat = "sandbox-other2";
@@ -1095,7 +1174,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_by_compatible_ot, UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_by_compatible_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
static int dm_test_ofnode_find_subnode(struct unit_test_state *uts)
{
@@ -1114,6 +1193,7 @@
}
DM_TEST(dm_test_ofnode_find_subnode, UT_TESTF_SCAN_FDT);
+/* test ofnode_find_subnode() on the 'other' tree */
static int dm_test_ofnode_find_subnode_ot(struct unit_test_state *uts)
{
oftree otree = get_other_oftree(uts);
@@ -1182,12 +1262,11 @@
}
DM_TEST(dm_test_ofnode_too_many, UT_TESTF_SCAN_FDT);
-static int check_copy_props(struct unit_test_state *uts, ofnode src,
- ofnode dst)
+static int check_copy_props(struct unit_test_state *uts, ofnode dst, ofnode src)
{
u32 reg[2], val;
- ut_assertok(ofnode_copy_props(src, dst));
+ ut_assertok(ofnode_copy_props(dst, src));
ut_assertok(ofnode_read_u32(dst, "ping-expect", &val));
ut_asserteq(3, val);
@@ -1219,7 +1298,7 @@
src = ofnode_path("/b-test");
dst = ofnode_path("/some-bus");
- ut_assertok(check_copy_props(uts, src, dst));
+ ut_assertok(check_copy_props(uts, dst, src));
/* check a property that is in the destination already */
ut_asserteq_str("mux0", ofnode_read_string(dst, "mux-control-names"));
@@ -1228,6 +1307,7 @@
}
DM_TEST(dm_test_ofnode_copy_props, UT_TESTF_SCAN_FDT);
+/* test ofnode_copy_props() with the 'other' tree */
static int dm_test_ofnode_copy_props_ot(struct unit_test_state *uts)
{
ofnode src, dst;
@@ -1235,7 +1315,7 @@
src = ofnode_path("/b-test");
dst = oftree_path(otree, "/node/subnode2");
- ut_assertok(check_copy_props(uts, src, dst));
+ ut_assertok(check_copy_props(uts, dst, src));
return 0;
}
@@ -1265,7 +1345,7 @@
return 0;
}
-DM_TEST(dm_test_livetree_align, UT_TESTF_LIVE_TREE);
+DM_TEST(dm_test_livetree_align, UT_TESTF_SCAN_FDT | UT_TESTF_LIVE_TREE);
/* check that it is possible to load an arbitrary livetree */
static int dm_test_livetree_ensure(struct unit_test_state *uts)
@@ -1284,4 +1364,161 @@
return 0;
}
-DM_TEST(dm_test_livetree_ensure, 0);
+DM_TEST(dm_test_livetree_ensure, UT_TESTF_SCAN_FDT);
+
+static int dm_test_oftree_new(struct unit_test_state *uts)
+{
+ ofnode node, subnode, check;
+ oftree tree;
+
+ ut_assertok(oftree_new(&tree));
+ node = oftree_root(tree);
+ ut_assert(ofnode_valid(node));
+ ut_assertok(ofnode_add_subnode(node, "edmund", &subnode));
+ check = ofnode_find_subnode(node, "edmund");
+ ut_asserteq(check.of_offset, subnode.of_offset);
+
+ return 0;
+}
+DM_TEST(dm_test_oftree_new, UT_TESTF_SCAN_FDT);
+
+static int check_copy_node(struct unit_test_state *uts, ofnode dst, ofnode src,
+ ofnode *nodep)
+{
+ u32 reg[2], val;
+ ofnode node;
+
+ ut_assertok(ofnode_copy_node(dst, "copy-test", src, &node));
+
+ ut_assertok(ofnode_read_u32(node, "ping-expect", &val));
+ ut_asserteq(3, val);
+
+ ut_asserteq_str("denx,u-boot-fdt-test",
+ ofnode_read_string(node, "compatible"));
+
+ /* check that a property with the same name is overwritten */
+ ut_assertok(ofnode_read_u32_array(node, "reg", reg, ARRAY_SIZE(reg)));
+ ut_asserteq(3, reg[0]);
+ ut_asserteq(1, reg[1]);
+
+ /* reset the compatible so the live tree does not change */
+ ut_assertok(ofnode_write_string(node, "compatible", "nothing"));
+ *nodep = node;
+
+ return 0;
+}
+
+static int dm_test_ofnode_copy_node(struct unit_test_state *uts)
+{
+ ofnode src, dst, node, try;
+
+ /*
+ * These nodes are chosen so that the src node is before the destination
+ * node in the tree. This doesn't matter with livetree, but with
+ * flattree any attempt to insert a property earlier in the tree will
+ * mess up the offsets after it.
+ */
+ src = ofnode_path("/b-test");
+ dst = ofnode_path("/some-bus");
+
+ ut_assertok(check_copy_node(uts, dst, src, &node));
+
+ /* check trying to copy over an existing node */
+ ut_asserteq(-EEXIST, ofnode_copy_node(dst, "copy-test", src, &try));
+ ut_asserteq(try.of_offset, node.of_offset);
+
+ return 0;
+}
+DM_TEST(dm_test_ofnode_copy_node, UT_TESTF_SCAN_FDT);
+
+/* test ofnode_copy_node() with the 'other' tree */
+static int dm_test_ofnode_copy_node_ot(struct unit_test_state *uts)
+{
+ oftree otree = get_other_oftree(uts);
+ ofnode src, dst, node;
+
+ src = ofnode_path("/b-test");
+ dst = oftree_path(otree, "/node/subnode2");
+ ut_assertok(check_copy_node(uts, dst, src, &node));
+
+ return 0;
+}
+DM_TEST(dm_test_ofnode_copy_node_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+
+static int dm_test_ofnode_delete(struct unit_test_state *uts)
+{
+ ofnode node;
+
+ /*
+ * At present the livetree is not restored after changes made in tests.
+ * See test_pre_run() for how this is done with the other FDT and
+ * dm_test_pre_run() where it sets up the root-tree pointer. So use
+ * nodes which don't matter to other tests.
+ *
+ * We could fix this by detecting livetree changes and regenerating it
+ * before the next test if needed.
+ */
+ node = ofnode_path("/leds/iracibble");
+ ut_assert(ofnode_valid(node));
+ ut_assertok(ofnode_delete(&node));
+ ut_assert(!ofnode_valid(node));
+ ut_assert(!ofnode_valid(ofnode_path("/leds/iracibble")));
+
+ node = ofnode_path("/leds/default_on");
+ ut_assert(ofnode_valid(node));
+ ut_assertok(ofnode_delete(&node));
+ ut_assert(!ofnode_valid(node));
+ ut_assert(!ofnode_valid(ofnode_path("/leds/default_on")));
+
+ ut_asserteq(2, ofnode_get_child_count(ofnode_path("/leds")));
+
+ return 0;
+}
+DM_TEST(dm_test_ofnode_delete, UT_TESTF_SCAN_FDT);
+
+static int dm_test_oftree_to_fdt(struct unit_test_state *uts)
+{
+ oftree tree, check;
+ struct abuf buf, buf2;
+
+ tree = oftree_default();
+ ut_assertok(oftree_to_fdt(tree, &buf));
+ ut_assert(abuf_size(&buf) > SZ_16K);
+
+ /* convert it back to a tree and see if it looks OK */
+ check = oftree_from_fdt(abuf_data(&buf));
+ ut_assert(oftree_valid(check));
+
+ ut_assertok(oftree_to_fdt(check, &buf2));
+ ut_assert(abuf_size(&buf2) > SZ_16K);
+ ut_asserteq(abuf_size(&buf), abuf_size(&buf2));
+ ut_asserteq_mem(abuf_data(&buf), abuf_data(&buf2), abuf_size(&buf));
+
+ return 0;
+}
+DM_TEST(dm_test_oftree_to_fdt, UT_TESTF_SCAN_FDT);
+
+/* test ofnode_read_bool() and ofnode_write_bool() */
+static int dm_test_bool(struct unit_test_state *uts)
+{
+ const char *propname = "missing-bool-value";
+ ofnode node;
+
+ node = ofnode_path("/a-test");
+ ut_assert(ofnode_read_bool(node, "bool-value"));
+ ut_assert(!ofnode_read_bool(node, propname));
+ ut_assert(!ofnode_has_property(node, propname));
+
+ ut_assertok(ofnode_write_bool(node, propname, true));
+ ut_assert(ofnode_read_bool(node, propname));
+ ut_assert(ofnode_has_property(node, propname));
+ ut_assert(ofnode_read_bool(node, "bool-value"));
+
+ ut_assertok(ofnode_write_bool(node, propname, false));
+ ut_assert(!ofnode_read_bool(node, propname));
+ ut_assert(!ofnode_has_property(node, propname));
+ ut_assert(ofnode_read_bool(node, "bool-value"));
+
+ return 0;
+}
+DM_TEST(dm_test_bool, UT_TESTF_SCAN_FDT);
diff --git a/test/dm/pci.c b/test/dm/pci.c
index 70a736c..8c5e7da 100644
--- a/test/dm/pci.c
+++ b/test/dm/pci.c
@@ -301,10 +301,12 @@
{
struct udevice *swap1f, *swap1;
ulong io_addr, mem_addr;
+ fdt_addr_t size;
ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap1f));
io_addr = dm_pci_read_bar32(swap1f, 0);
- ut_asserteq(io_addr, dev_read_addr_pci(swap1f));
+ ut_asserteq(io_addr, dev_read_addr_pci(swap1f, &size));
+ ut_asserteq(0, size);
/*
* This device has both I/O and MEM spaces but the MEM space appears
@@ -312,7 +314,8 @@
*/
ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1, 0), &swap1));
mem_addr = dm_pci_read_bar32(swap1, 1);
- ut_asserteq(mem_addr, dev_read_addr_pci(swap1));
+ ut_asserteq(mem_addr, dev_read_addr_pci(swap1, &size));
+ ut_asserteq(0, size);
return 0;
}
@@ -329,12 +332,15 @@
static int dm_test_pci_addr_live(struct unit_test_state *uts)
{
struct udevice *swap1f, *swap1;
+ fdt_size_t size;
ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap1f));
- ut_asserteq_64(FDT_ADDR_T_NONE, dev_read_addr_pci(swap1f));
+ ut_asserteq_64(FDT_ADDR_T_NONE, dev_read_addr_pci(swap1f, &size));
+ ut_asserteq(0, size);
ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1, 0), &swap1));
- ut_asserteq_64(FDT_ADDR_T_NONE, dev_read_addr_pci(swap1));
+ ut_asserteq_64(FDT_ADDR_T_NONE, dev_read_addr_pci(swap1, &size));
+ ut_asserteq(0, size);
return 0;
}
diff --git a/test/dm/phy.c b/test/dm/phy.c
index 4d4a083..0cf3689 100644
--- a/test/dm/phy.c
+++ b/test/dm/phy.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
* Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
@@ -29,7 +29,9 @@
* Get the same phy port in 2 different ways and compare.
*/
ut_assertok(generic_phy_get_by_name(parent, "phy1", &phy1_method1));
+ ut_assert(generic_phy_valid(&phy1_method1));
ut_assertok(generic_phy_get_by_index(parent, 0, &phy1_method2));
+ ut_assert(generic_phy_valid(&phy1_method2));
ut_asserteq(phy1_method1.id, phy1_method2.id);
/*
@@ -47,9 +49,23 @@
ut_assert(phy2.dev != phy3.dev);
/* Try to get a non-existing phy */
- ut_asserteq(-ENODEV, uclass_get_device(UCLASS_PHY, 4, &dev));
+ ut_asserteq(-ENODEV, uclass_get_device(UCLASS_PHY, 5, &dev));
ut_asserteq(-ENODATA, generic_phy_get_by_name(parent,
"phy_not_existing", &phy1_method1));
+ ut_assert(!generic_phy_valid(&phy1_method1));
+ ut_asserteq(-ENOENT, generic_phy_get_by_index(parent, 3,
+ &phy1_method2));
+ ut_assert(!generic_phy_valid(&phy1_method2));
+
+ /* Try to get a phy where of_xlate fail */
+ ut_assertok(uclass_get_device_by_name(UCLASS_SIMPLE_BUS,
+ "gen_phy_user2", &parent));
+ ut_asserteq(-EINVAL, generic_phy_get_by_name(parent, "phy1",
+ &phy1_method1));
+ ut_assert(!generic_phy_valid(&phy1_method1));
+ ut_asserteq(-EINVAL, generic_phy_get_by_index(parent, 0,
+ &phy1_method2));
+ ut_assert(!generic_phy_valid(&phy1_method2));
return 0;
}
@@ -218,3 +234,32 @@
return 0;
}
DM_TEST(dm_test_phy_multi_exit, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+static int dm_test_phy_setup(struct unit_test_state *uts)
+{
+ struct phy phy;
+ struct udevice *parent;
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_SIMPLE_BUS,
+ "gen_phy_user", &parent));
+
+ /* normal */
+ ut_assertok(generic_setup_phy(parent, &phy, 0));
+ ut_assertok(generic_shutdown_phy(&phy));
+
+ /* power_off fail with -EIO */
+ ut_assertok(generic_setup_phy(parent, &phy, 1));
+ ut_asserteq(-EIO, generic_shutdown_phy(&phy));
+
+ /* power_on fail with -EIO */
+ ut_asserteq(-EIO, generic_setup_phy(parent, &phy, 2));
+ ut_assertok(generic_shutdown_phy(&phy));
+
+ /* generic_phy_get_by_index fail with -ENOENT */
+ ut_asserteq(-ENOENT, generic_phy_get_by_index(parent, 3, &phy));
+ ut_assertok(generic_setup_phy(parent, &phy, 3));
+ ut_assertok(generic_shutdown_phy(&phy));
+
+ return 0;
+}
+DM_TEST(dm_test_phy_setup, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
diff --git a/test/dm/remoteproc.c b/test/dm/remoteproc.c
index 7a8ff47..f6f9e50 100644
--- a/test/dm/remoteproc.c
+++ b/test/dm/remoteproc.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2015
- * Texas Instruments Incorporated - http://www.ti.com/
+ * Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
#include <dm.h>
diff --git a/test/dm/rkmtd.c b/test/dm/rkmtd.c
new file mode 100644
index 0000000..3c3e8ef
--- /dev/null
+++ b/test/dm/rkmtd.c
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Test derived from:
+ * /test/dm/host.c
+ * Copyright 2022 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * Copyright (C) 2023 Johan Jonker <jbx6244@gmail.com>
+ */
+
+#include <common.h>
+#include <blk.h>
+#include <dm.h>
+#include <fs.h>
+#include <rkmtd.h>
+#include <asm/test.h>
+#include <dm/device-internal.h>
+#include <dm/test.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+#define RW_BUF_SIZE 12 * 512
+
+/* Basic test of the RKMTD interface */
+static int dm_test_rkmtd(struct unit_test_state *uts)
+{
+ struct udevice *dev, *part, *chk, *blk;
+ char write[RW_BUF_SIZE], read[RW_BUF_SIZE];
+ static const char label[] = "test";
+ struct rkmtd_dev *plat;
+ struct blk_desc *desc;
+ struct sector0 *sec0;
+ int i;
+
+ ut_asserteq(-ENODEV, uclass_first_device_err(UCLASS_RKMTD, &dev));
+ ut_asserteq(-ENODEV, uclass_first_device_err(UCLASS_PARTITION, &part));
+
+ ut_assertok(rkmtd_create_device(label, &dev));
+
+ /* Check that the plat data has been allocated */
+ plat = dev_get_plat(dev);
+ ut_asserteq_str("test", plat->label);
+ ut_assert(label != plat->label);
+
+ /* Attach RKMTD driver */
+ ut_assertok(rkmtd_attach(dev));
+ ut_assertok(uclass_first_device_err(UCLASS_RKMTD, &chk));
+ ut_asserteq_ptr(chk, dev);
+
+ /* Get RKMTD block device */
+ ut_assertok(blk_get_from_parent(dev, &blk));
+ ut_assertok(device_probe(blk));
+
+ /* There should be a GPT partition table in this device */
+ ut_asserteq(0, uclass_first_device_err(UCLASS_PARTITION, &part));
+
+ /* Write a boot block and verify that we get the same data back */
+ desc = dev_get_uclass_plat(blk);
+ ut_asserteq(true, desc->removable);
+ ut_asserteq(LBA, desc->lba);
+
+ memset(write, '\0', BLK_SIZE);
+
+ for (i = BLK_SIZE; i < sizeof(write); i++)
+ write[i] = i;
+
+ sec0 = (struct sector0 *)write;
+ sec0->magic = 0x0FF0AA55;
+ sec0->rc4_flag = 0;
+ sec0->boot_code1_offset = 4;
+ sec0->boot_code2_offset = 4;
+ sec0->flash_data_size = 4;
+ sec0->flash_boot_size = 8;
+
+ rkmtd_rc4(write, 512);
+ ut_asserteq(RK_TAG, sec0->magic);
+
+ ut_asserteq(12, blk_dwrite(desc, 64, 12, write));
+ ut_asserteq(12, blk_dread(desc, 64, 12, read));
+ ut_asserteq_mem(write, read, RW_BUF_SIZE);
+
+ ut_assertok(rkmtd_detach(dev));
+
+ ut_asserteq(-ENODEV, blk_get_from_parent(dev, &blk));
+ ut_assertok(device_unbind(dev));
+
+ return 0;
+}
+DM_TEST(dm_test_rkmtd, UT_TESTF_SCAN_FDT);
+
+/* Reusing the same label should work */
+static int dm_test_rkmtd_dup(struct unit_test_state *uts)
+{
+ static const char label[] = "test";
+ struct udevice *dev, *chk;
+
+ /* Create a RKMTD device with label "test" */
+ ut_asserteq(0, uclass_id_count(UCLASS_RKMTD));
+ ut_assertok(rkmtd_create_device(label, &dev));
+ ut_assertok(rkmtd_attach(dev));
+ ut_assertok(uclass_first_device_err(UCLASS_RKMTD, &chk));
+ ut_asserteq_ptr(chk, dev);
+ ut_asserteq(1, uclass_id_count(UCLASS_RKMTD));
+
+ /* Create another device with the same label (should remove old one) */
+ ut_assertok(rkmtd_create_device(label, &dev));
+ ut_assertok(rkmtd_attach(dev));
+ ut_assertok(uclass_first_device_err(UCLASS_RKMTD, &chk));
+ ut_asserteq_ptr(chk, dev);
+
+ /* Make sure there is still only one device */
+ ut_asserteq(1, uclass_id_count(UCLASS_RKMTD));
+
+ return 0;
+}
+DM_TEST(dm_test_rkmtd_dup, UT_TESTF_SCAN_FDT);
+
+/* Basic test of the 'rkmtd' command */
+static int dm_test_rkmtd_cmd(struct unit_test_state *uts)
+{
+ struct udevice *dev, *blk;
+ struct blk_desc *desc;
+
+ /* First check 'rkmtd info' with binding */
+ ut_assertok(run_command("rkmtd info", 0));
+ ut_assert_nextline("dev blocks label ");
+ ut_assert_console_end();
+
+ /* Bind device 1 */
+ ut_assertok(run_commandf("rkmtd bind test1"));
+ ut_assertok(uclass_first_device_err(UCLASS_RKMTD, &dev));
+ ut_assertok(blk_get_from_parent(dev, &blk));
+ desc = dev_get_uclass_plat(blk);
+
+ ut_assertok(run_command("rkmtd info", 0));
+ ut_assert_nextline("dev blocks label ");
+ ut_assert_nextline(" 0 609 test1 ");
+ ut_assert_console_end();
+
+ /* Bind device 2 */
+ ut_assertok(run_commandf("rkmtd bind test2"));
+ ut_assertok(uclass_next_device_err(&dev));
+ ut_assertok(blk_get_from_parent(dev, &blk));
+ desc = dev_get_uclass_plat(blk);
+
+ ut_assertok(run_command("rkmtd info", 0));
+ ut_assert_nextline("dev blocks label ");
+ ut_assert_nextline(" 0 609 test1 ");
+ ut_assert_nextline(" 1 609 test2 ");
+ ut_assert_console_end();
+
+ ut_asserteq(1, run_command("rkmtd info test", 0));
+ ut_assert_nextline("No such device 'test'");
+ ut_assert_console_end();
+
+ ut_assertok(run_command("rkmtd info test2", 0));
+ ut_assert_nextline("dev blocks label ");
+ ut_assert_nextline(" 1 609 test2 ");
+ ut_assert_console_end();
+
+ /* Check 'rkmtd dev' */
+ ut_asserteq(1, run_command("rkmtd dev", 0));
+ ut_assert_nextline("No current rkmtd device");
+ ut_assert_console_end();
+
+ ut_asserteq(1, run_command("rkmtd dev missing", 0));
+ ut_assert_nextline("No such device 'missing'");
+ ut_assert_console_end();
+
+ ut_assertok(run_command("rkmtd dev test2", 0));
+ ut_assert_console_end();
+
+ ut_assertok(run_command("rkmtd dev", 0));
+ ut_assert_nextline("Current rkmtd device: 1: test2");
+ ut_assert_console_end();
+
+ /* Try a numerical label */
+ ut_assertok(run_command("rkmtd dev 0", 0));
+ ut_assert_console_end();
+
+ ut_assertok(run_command("rkmtd dev", 0));
+ ut_assert_nextline("Current rkmtd device: 0: test1");
+ ut_assert_console_end();
+
+ /* Remove one of the bindings */
+ ut_assertok(run_commandf("rkmtd unbind test1"));
+
+ /* There should now be no current device */
+ ut_asserteq(1, run_command("rkmtd dev", 0));
+ ut_assert_nextline("No current rkmtd device");
+ ut_assert_console_end();
+
+ ut_assertok(run_command("rkmtd info", 0));
+ ut_assert_nextline("dev blocks label ");
+ ut_assert_nextline(" 1 609 test2 ");
+ ut_assert_console_end();
+
+ return 0;
+}
+DM_TEST(dm_test_rkmtd_cmd, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
diff --git a/test/dm/scmi.c b/test/dm/scmi.c
index d87e273..da45314 100644
--- a/test/dm/scmi.c
+++ b/test/dm/scmi.c
@@ -16,6 +16,9 @@
#include <clk.h>
#include <dm.h>
#include <reset.h>
+#include <scmi_agent.h>
+#include <scmi_agent-uclass.h>
+#include <scmi_protocols.h>
#include <asm/scmi_test.h>
#include <dm/device-internal.h>
#include <dm/test.h>
@@ -23,22 +26,11 @@
#include <power/regulator.h>
#include <test/ut.h>
-static int ut_assert_scmi_state_preprobe(struct unit_test_state *uts)
-{
- struct sandbox_scmi_service *scmi_ctx = sandbox_scmi_service_ctx();
-
- ut_assertnonnull(scmi_ctx);
- ut_assertnull(scmi_ctx->agent);
-
- return 0;
-}
-
static int ut_assert_scmi_state_postprobe(struct unit_test_state *uts,
+ struct sandbox_scmi_agent *agent,
struct udevice *dev)
{
struct sandbox_scmi_devices *scmi_devices;
- struct sandbox_scmi_service *scmi_ctx;
- struct sandbox_scmi_agent *agent;
/* Device references to check context against test sequence */
scmi_devices = sandbox_scmi_devices_ctx(dev);
@@ -48,10 +40,6 @@
ut_asserteq(2, scmi_devices->regul_count);
/* State of the simulated SCMI server exposed */
- scmi_ctx = sandbox_scmi_service_ctx();
- ut_assertnonnull(scmi_ctx);
- agent = scmi_ctx->agent;
- ut_assertnonnull(agent);
ut_asserteq(3, agent->clk_count);
ut_assertnonnull(agent->clk);
ut_asserteq(1, agent->reset_count);
@@ -63,27 +51,32 @@
}
static int load_sandbox_scmi_test_devices(struct unit_test_state *uts,
+ struct sandbox_scmi_agent **ctx,
struct udevice **dev)
{
- int ret;
+ struct udevice *agent_dev;
- ret = ut_assert_scmi_state_preprobe(uts);
- if (ret)
- return ret;
+ ut_assertok(uclass_get_device_by_name(UCLASS_SCMI_AGENT, "scmi",
+ &agent_dev));
+ ut_assertnonnull(agent_dev);
+ *ctx = sandbox_scmi_agent_ctx(agent_dev);
+ ut_assertnonnull(*ctx);
+
+ /* probe */
ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "sandbox_scmi",
dev));
ut_assertnonnull(*dev);
- return ut_assert_scmi_state_postprobe(uts, *dev);
+ return ut_assert_scmi_state_postprobe(uts, *ctx, *dev);
}
static int release_sandbox_scmi_test_devices(struct unit_test_state *uts,
struct udevice *dev)
{
+ /* un-probe */
ut_assertok(device_remove(dev, DM_REMOVE_NORMAL));
- /* Not sure test devices are fully removed, agent may not be visible */
return 0;
}
@@ -93,10 +86,11 @@
*/
static int dm_test_scmi_sandbox_agent(struct unit_test_state *uts)
{
+ struct sandbox_scmi_agent *ctx;
struct udevice *dev = NULL;
int ret;
- ret = load_sandbox_scmi_test_devices(uts, &dev);
+ ret = load_sandbox_scmi_test_devices(uts, &ctx, &dev);
if (!ret)
ret = release_sandbox_scmi_test_devices(uts, dev);
@@ -104,25 +98,239 @@
}
DM_TEST(dm_test_scmi_sandbox_agent, UT_TESTF_SCAN_FDT);
+static int dm_test_scmi_base(struct unit_test_state *uts)
+{
+ struct udevice *agent_dev, *base;
+ struct scmi_agent_priv *priv;
+ u32 version, num_agents, num_protocols, impl_version;
+ u32 attributes, agent_id;
+ u8 *vendor, *agent_name, *protocols;
+ int ret;
+
+ /* preparation */
+ ut_assertok(uclass_get_device_by_name(UCLASS_SCMI_AGENT, "scmi",
+ &agent_dev));
+ ut_assertnonnull(agent_dev);
+ ut_assertnonnull(priv = dev_get_uclass_plat(agent_dev));
+ ut_assertnonnull(base = scmi_get_protocol(agent_dev,
+ SCMI_PROTOCOL_ID_BASE));
+
+ /* version */
+ ret = scmi_base_protocol_version(base, &version);
+ ut_assertok(ret);
+ ut_asserteq(priv->version, version);
+
+ /* protocol attributes */
+ ret = scmi_base_protocol_attrs(base, &num_agents, &num_protocols);
+ ut_assertok(ret);
+ ut_asserteq(priv->num_agents, num_agents);
+ ut_asserteq(priv->num_protocols, num_protocols);
+
+ /* discover vendor */
+ ret = scmi_base_discover_vendor(base, &vendor);
+ ut_assertok(ret);
+ ut_asserteq_str(priv->vendor, vendor);
+ free(vendor);
+
+ /* message attributes */
+ ret = scmi_base_protocol_message_attrs(base,
+ SCMI_BASE_DISCOVER_SUB_VENDOR,
+ &attributes);
+ ut_assertok(ret);
+ ut_assertok(attributes);
+
+ /* discover sub vendor */
+ ret = scmi_base_discover_sub_vendor(base, &vendor);
+ ut_assertok(ret);
+ ut_asserteq_str(priv->sub_vendor, vendor);
+ free(vendor);
+
+ /* impl version */
+ ret = scmi_base_discover_impl_version(base, &impl_version);
+ ut_assertok(ret);
+ ut_asserteq(priv->impl_version, impl_version);
+
+ /* discover agent (my self) */
+ ret = scmi_base_discover_agent(base, 0xffffffff, &agent_id,
+ &agent_name);
+ ut_assertok(ret);
+ ut_asserteq(priv->agent_id, agent_id);
+ ut_asserteq_str(priv->agent_name, agent_name);
+ free(agent_name);
+
+ /* discover protocols */
+ ret = scmi_base_discover_list_protocols(base, &protocols);
+ ut_asserteq(num_protocols, ret);
+ ut_asserteq_mem(priv->protocols, protocols, sizeof(u8) * num_protocols);
+ free(protocols);
+
+ /*
+ * NOTE: Sandbox SCMI driver handles device-0 only. It supports setting
+ * access and protocol permissions, but doesn't allow unsetting them nor
+ * resetting the configurations.
+ */
+ /* set device permissions */
+ ret = scmi_base_set_device_permissions(base, agent_id, 0,
+ SCMI_BASE_SET_DEVICE_PERMISSIONS_ACCESS);
+ ut_assertok(ret); /* SCMI_SUCCESS */
+ ret = scmi_base_set_device_permissions(base, agent_id, 1,
+ SCMI_BASE_SET_DEVICE_PERMISSIONS_ACCESS);
+ ut_asserteq(-ENOENT, ret); /* SCMI_NOT_FOUND */
+ ret = scmi_base_set_device_permissions(base, agent_id, 0, 0);
+ ut_asserteq(-EACCES, ret); /* SCMI_DENIED */
+
+ /* set protocol permissions */
+ ret = scmi_base_set_protocol_permissions(base, agent_id, 0,
+ SCMI_PROTOCOL_ID_CLOCK,
+ SCMI_BASE_SET_PROTOCOL_PERMISSIONS_ACCESS);
+ ut_assertok(ret); /* SCMI_SUCCESS */
+ ret = scmi_base_set_protocol_permissions(base, agent_id, 1,
+ SCMI_PROTOCOL_ID_CLOCK,
+ SCMI_BASE_SET_PROTOCOL_PERMISSIONS_ACCESS);
+ ut_asserteq(-ENOENT, ret); /* SCMI_NOT_FOUND */
+ ret = scmi_base_set_protocol_permissions(base, agent_id, 0,
+ SCMI_PROTOCOL_ID_CLOCK, 0);
+ ut_asserteq(-EACCES, ret); /* SCMI_DENIED */
+
+ /* reset agent configuration */
+ ret = scmi_base_reset_agent_configuration(base, agent_id, 0);
+ ut_asserteq(-EACCES, ret); /* SCMI_DENIED */
+ ret = scmi_base_reset_agent_configuration(base, agent_id,
+ SCMI_BASE_RESET_ALL_ACCESS_PERMISSIONS);
+ ut_asserteq(-EACCES, ret); /* SCMI_DENIED */
+ ret = scmi_base_reset_agent_configuration(base, agent_id, 0);
+ ut_asserteq(-EACCES, ret); /* SCMI_DENIED */
+
+ return 0;
+}
+
+DM_TEST(dm_test_scmi_base, UT_TESTF_SCAN_FDT);
+
+static int dm_test_scmi_power_domains(struct unit_test_state *uts)
+{
+ struct sandbox_scmi_agent *agent;
+ struct sandbox_scmi_devices *scmi_devices;
+ struct udevice *agent_dev, *pwd, *dev;
+ u32 version, count, attributes, pstate;
+ u64 stats_addr;
+ size_t stats_len;
+ u8 *name;
+ int ret;
+
+ /* preparation */
+ ut_assertok(load_sandbox_scmi_test_devices(uts, &agent, &dev));
+ ut_assertnonnull(agent);
+ scmi_devices = sandbox_scmi_devices_ctx(dev);
+ ut_assertnonnull(scmi_devices);
+ ut_asserteq(2, scmi_devices->pwdom->id); /* in test.dts */
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_SCMI_AGENT, "scmi",
+ &agent_dev));
+ ut_assertnonnull(agent_dev);
+ pwd = scmi_get_protocol(agent_dev, SCMI_PROTOCOL_ID_POWER_DOMAIN);
+ ut_assertnonnull(pwd);
+
+ /*
+ * SCMI Power domain management protocol interfaces
+ */
+ /* version */
+ ret = scmi_generic_protocol_version(pwd, SCMI_PROTOCOL_ID_POWER_DOMAIN,
+ &version);
+ ut_assertok(ret);
+ ut_asserteq(agent->pwdom_version, version);
+
+ /* protocol attributes */
+ ret = scmi_pwd_protocol_attrs(pwd, &count, &stats_addr, &stats_len);
+ ut_assertok(ret);
+ ut_asserteq(agent->pwdom_count, count);
+ ut_asserteq(0, stats_len);
+
+ /* protocol message attributes */
+ ret = scmi_pwd_protocol_message_attrs(pwd, SCMI_PWD_STATE_SET,
+ &attributes);
+ ut_assertok(ret);
+ ret = scmi_pwd_protocol_message_attrs(pwd, SCMI_PWD_STATE_NOTIFY,
+ &attributes);
+ ut_asserteq(-ENOENT, ret); /* the protocol not supported */
+
+ /* power domain attributes */
+ ret = scmi_pwd_attrs(pwd, 0, &attributes, &name);
+ ut_assertok(ret);
+ ut_asserteq_str("power-domain--0", name);
+ free(name);
+
+ ret = scmi_pwd_attrs(pwd, 10, &attributes, &name);
+ ut_asserteq(-ENOENT, ret); /* domain-10 doesn't exist */
+
+ /* power domain state set/get */
+ ret = scmi_pwd_state_set(pwd, 0, 0, 0);
+ ut_assertok(ret);
+ ret = scmi_pwd_state_get(pwd, 0, &pstate);
+ ut_assertok(ret);
+ ut_asserteq(0, pstate); /* ON */
+
+ ret = scmi_pwd_state_set(pwd, 0, 0, SCMI_PWD_PSTATE_TYPE_LOST);
+ ut_assertok(ret);
+ ret = scmi_pwd_state_get(pwd, 0, &pstate);
+ ut_assertok(ret);
+ ut_asserteq(SCMI_PWD_PSTATE_TYPE_LOST, pstate); /* OFF */
+
+ ret = scmi_pwd_state_set(pwd, 0, 10, 0);
+ ut_asserteq(-ENOENT, ret);
+
+ /* power domain name get */
+ ret = scmi_pwd_name_get(pwd, 0, &name);
+ ut_assertok(ret);
+ ut_asserteq_str("power-domain--0-extended", name);
+ free(name);
+
+ ret = scmi_pwd_name_get(pwd, 10, &name);
+ ut_asserteq(-ENOENT, ret); /* domain-10 doesn't exist */
+
+ /*
+ * U-Boot driver model interfaces
+ */
+ /* power_domain_on */
+ ret = power_domain_on(scmi_devices->pwdom);
+ ut_assertok(ret);
+ ret = scmi_pwd_state_get(pwd, scmi_devices->pwdom->id, &pstate);
+ ut_assertok(ret);
+ ut_asserteq(0, pstate); /* ON */
+
+ /* power_domain_off */
+ ret = power_domain_off(scmi_devices->pwdom);
+ ut_assertok(ret);
+ ret = scmi_pwd_state_get(pwd, scmi_devices->pwdom->id, &pstate);
+ ut_assertok(ret);
+ ut_asserteq(SCMI_PWD_PSTATE_TYPE_LOST, pstate); /* OFF */
+
+ return release_sandbox_scmi_test_devices(uts, dev);
+}
+
+DM_TEST(dm_test_scmi_power_domains, UT_TESTF_SCAN_FDT);
+
static int dm_test_scmi_clocks(struct unit_test_state *uts)
{
- struct sandbox_scmi_devices *scmi_devices;
- struct sandbox_scmi_service *scmi_ctx;
struct sandbox_scmi_agent *agent;
- struct udevice *dev;
+ struct sandbox_scmi_devices *scmi_devices;
+ struct udevice *agent_dev, *clock_dev, *dev;
int ret_dev;
int ret;
- ret = load_sandbox_scmi_test_devices(uts, &dev);
+ ret = load_sandbox_scmi_test_devices(uts, &agent, &dev);
if (ret)
return ret;
scmi_devices = sandbox_scmi_devices_ctx(dev);
ut_assertnonnull(scmi_devices);
- scmi_ctx = sandbox_scmi_service_ctx();
- ut_assertnonnull(scmi_ctx);
- agent = scmi_ctx->agent;
- ut_assertnonnull(agent);
+
+ /* Sandbox SCMI clock protocol has its own channel */
+ ut_assertok(uclass_get_device_by_name(UCLASS_SCMI_AGENT, "scmi",
+ &agent_dev));
+ ut_assertnonnull(agent_dev);
+ clock_dev = scmi_get_protocol(agent_dev, SCMI_PROTOCOL_ID_CLOCK);
+ ut_assertnonnull(clock_dev);
+ ut_asserteq(0x14, sandbox_scmi_channel_id(clock_dev));
/* Test SCMI clocks rate manipulation */
ut_asserteq(333, agent->clk[0].rate);
@@ -169,22 +377,25 @@
static int dm_test_scmi_resets(struct unit_test_state *uts)
{
- struct sandbox_scmi_devices *scmi_devices;
- struct sandbox_scmi_service *scmi_ctx;
struct sandbox_scmi_agent *agent;
- struct udevice *dev = NULL;
+ struct sandbox_scmi_devices *scmi_devices;
+ struct udevice *agent_dev, *reset_dev, *dev = NULL;
int ret;
- ret = load_sandbox_scmi_test_devices(uts, &dev);
+ ret = load_sandbox_scmi_test_devices(uts, &agent, &dev);
if (ret)
return ret;
scmi_devices = sandbox_scmi_devices_ctx(dev);
ut_assertnonnull(scmi_devices);
- scmi_ctx = sandbox_scmi_service_ctx();
- ut_assertnonnull(scmi_ctx);
- agent = scmi_ctx->agent;
- ut_assertnonnull(agent);
+
+ /* Sandbox SCMI reset protocol doesn't have its own channel */
+ ut_assertok(uclass_get_device_by_name(UCLASS_SCMI_AGENT, "scmi",
+ &agent_dev));
+ ut_assertnonnull(agent_dev);
+ reset_dev = scmi_get_protocol(agent_dev, SCMI_PROTOCOL_ID_RESET_DOMAIN);
+ ut_assertnonnull(reset_dev);
+ ut_asserteq(0x0, sandbox_scmi_channel_id(reset_dev));
/* Test SCMI resect controller manipulation */
ut_assert(!agent->reset[0].asserted);
@@ -201,21 +412,16 @@
static int dm_test_scmi_voltage_domains(struct unit_test_state *uts)
{
- struct sandbox_scmi_devices *scmi_devices;
- struct sandbox_scmi_service *scmi_ctx;
struct sandbox_scmi_agent *agent;
+ struct sandbox_scmi_devices *scmi_devices;
struct dm_regulator_uclass_plat *uc_pdata;
struct udevice *dev;
struct udevice *regul0_dev;
- ut_assertok(load_sandbox_scmi_test_devices(uts, &dev));
+ ut_assertok(load_sandbox_scmi_test_devices(uts, &agent, &dev));
scmi_devices = sandbox_scmi_devices_ctx(dev);
ut_assertnonnull(scmi_devices);
- scmi_ctx = sandbox_scmi_service_ctx();
- ut_assertnonnull(scmi_ctx);
- agent = scmi_ctx->agent;
- ut_assertnonnull(agent);
/* Set/Get an SCMI voltage domain level */
regul0_dev = scmi_devices->regul[0];
diff --git a/test/dm/serial.c b/test/dm/serial.c
index 37d17a6..34b783e 100644
--- a/test/dm/serial.c
+++ b/test/dm/serial.c
@@ -29,6 +29,7 @@
&dev_serial));
ut_assertok(serial_tstc());
+ ut_asserteq(115200, fetch_baud_from_dtb());
/*
* test with default config which is the only one supported by
* sandbox_serial driver
diff --git a/test/dm/sm.c b/test/dm/sm.c
new file mode 100644
index 0000000..7ebb0c9
--- /dev/null
+++ b/test/dm/sm.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 SberDevices, Inc.
+ *
+ * Author: Alexey Romanov <avromanov@salutedevices.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <sm.h>
+#include <sandbox-sm.h>
+#include <asm/ptrace.h>
+#include <dm/device-internal.h>
+#include <dm/test.h>
+#include <test/ut.h>
+#include <linux/sizes.h>
+
+static int dm_test_sm(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ struct pt_regs regs;
+ char buffer[128] = { 0 };
+ char test_string[] = "secure-monitor";
+ int ret, val;
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_SM,
+ "secure-monitor", &dev));
+
+ ret = sm_call(dev, SANDBOX_SMC_CMD_COUNT, NULL, ®s);
+ ut_asserteq(ret, -EINVAL);
+
+ ret = sm_call(dev, SANDBOX_SMC_CMD_COMMON, &val, ®s);
+ ut_asserteq(ret, 0);
+ ut_asserteq(val, 0);
+
+ ret = sm_call_write(dev, buffer, sizeof(buffer),
+ SANDBOX_SMC_CMD_COUNT, ®s);
+ ut_asserteq(ret, -EINVAL);
+
+ ret = sm_call_write(dev, buffer, SZ_4K + 1,
+ SANDBOX_SMC_CMD_WRITE_MEM, ®s);
+ ut_asserteq(ret, -EINVAL);
+
+ ret = sm_call_write(dev, buffer, sizeof(buffer),
+ SANDBOX_SMC_CMD_COUNT, ®s);
+ ut_asserteq(ret, -EINVAL);
+
+ ret = sm_call_write(dev, buffer, SZ_4K + 1,
+ SANDBOX_SMC_CMD_READ_MEM, ®s);
+ ut_asserteq(ret, -EINVAL);
+
+ ret = sm_call_write(dev, test_string, sizeof(test_string),
+ SANDBOX_SMC_CMD_WRITE_MEM, ®s);
+ ut_asserteq(ret, sizeof(test_string));
+
+ ret = sm_call_read(dev, buffer, sizeof(buffer),
+ SANDBOX_SMC_CMD_READ_MEM, ®s);
+ ut_asserteq(ret, sizeof(buffer));
+
+ ut_asserteq_str(buffer, test_string);
+
+ return 0;
+}
+
+DM_TEST(dm_test_sm, UT_TESTF_SCAN_FDT);
diff --git a/test/dm/soc.c b/test/dm/soc.c
index 17e1b5b..8f6c97f 100644
--- a/test/dm/soc.c
+++ b/test/dm/soc.c
@@ -2,7 +2,7 @@
/*
* Test for the SOC uclass
*
- * (C) Copyright 2020 - Texas Instruments Incorporated - http://www.ti.com/
+ * (C) Copyright 2020 - Texas Instruments Incorporated - https://www.ti.com/
* Dave Gerlach <d-gerlach@ti.com>
*/
diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c
index eeecd1d..72d0eb5 100644
--- a/test/dm/test-fdt.c
+++ b/test/dm/test-fdt.c
@@ -135,8 +135,8 @@
* want to test the code that sets that up
* (testfdt_drv_probe()).
*/
- base = fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev),
- "ping-expect");
+ base = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "ping-expect", -1);
debug("dev=%d, base=%d: %s\n", i, base,
fdt_get_name(gd->fdt_blob, dev_of_offset(dev), NULL));
diff --git a/test/dm/tpm.c b/test/dm/tpm.c
index 3defb3c..cde933a 100644
--- a/test/dm/tpm.c
+++ b/test/dm/tpm.c
@@ -98,10 +98,11 @@
if (reinit)
ut_assertok(tpm_init(dev));
- /*
- * tpm_auto_start will rerun tpm_init() if reinit, but handles the
- * -EBUSY return code internally.
- */
+
+ /*
+ * tpm_auto_start will rerun tpm_init() if reinit, but handles the
+ * -EBUSY return code internally.
+ */
ut_assertok(tpm_auto_start(dev));
return 0;
diff --git a/test/dm/wdt.c b/test/dm/wdt.c
index 653d7b1..2bbebcd 100644
--- a/test/dm/wdt.c
+++ b/test/dm/wdt.c
@@ -54,7 +54,7 @@
*/
struct udevice *wdt, *gpio;
const u64 timeout = 42;
- const int offset = 7;
+ const int offset = 8;
int val;
ut_assertok(uclass_get_device_by_name(UCLASS_WDT,
@@ -115,7 +115,7 @@
struct udevice *gpio_wdt, *sandbox_wdt;
struct udevice *gpio;
const u64 timeout = 42;
- const int offset = 7;
+ const int offset = 8;
uint reset_count;
int val;
diff --git a/test/fuzz/cmd_fuzz.c b/test/fuzz/cmd_fuzz.c
index e2f44f3..d0bc7b8 100644
--- a/test/fuzz/cmd_fuzz.c
+++ b/test/fuzz/cmd_fuzz.c
@@ -70,11 +70,8 @@
return 1;
}
-#ifdef CONFIG_SYS_LONGHELP
-static char fuzz_help_text[] =
- "[fuzz-test-name] - execute the named fuzz test\n"
- ;
-#endif /* CONFIG_SYS_LONGHELP */
+U_BOOT_LONGHELP(fuzz,
+ "[fuzz-test-name] - execute the named fuzz test\n");
U_BOOT_CMD(
fuzz, CONFIG_SYS_MAXARGS, 1, do_fuzz,
diff --git a/test/image/Kconfig b/test/image/Kconfig
new file mode 100644
index 0000000..8f9e6ae
--- /dev/null
+++ b/test/image/Kconfig
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2023 Sean Anderson <seanga2@gmail.com>
+
+config SPL_UT_LOAD
+ bool "Unit tests for SPL load methods"
+ depends on SPL_UNIT_TEST
+ default y if SANDBOX
+ help
+ Test various SPL load methods.
+
+if SPL_UT_LOAD
+
+config SPL_UT_LOAD_FS
+ bool "Unit tests for filesystems"
+ depends on SANDBOX && SPL_OF_REAL
+ depends on FS_LOADER
+ depends on SPL_BLK_FS
+ depends on SPL_FS_FAT
+ depends on SPL_FS_EXT4
+ depends on SPL_MMC_WRITE
+ depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+ default y
+ help
+ Test filesystems and the various load methods which use them.
+
+config SPL_UT_LOAD_NET
+ bool "Test loading over TFTP"
+ depends on SANDBOX && SPL_OF_REAL
+ depends on SPL_ETH
+ depends on USE_BOOTFILE
+ default y
+ help
+ Test loading images over TFTP using the NET image load method.
+
+config SPL_UT_LOAD_SPI
+ bool "Test loading from SPI Flash"
+ depends on SANDBOX && SPL_OF_REAL
+ depends on SPL_SPI_LOAD
+ default y
+ help
+ Test the SPI flash image load metod.
+
+config SPL_UT_LOAD_OS
+ bool "Test loading from the host OS"
+ depends on SANDBOX && SPL_LOAD_FIT
+ default y
+ help
+ Smoke test to ensure that loading U-boot works in sandbox.
+
+endif
diff --git a/test/image/Makefile b/test/image/Makefile
index c4039df..b302101 100644
--- a/test/image/Makefile
+++ b/test/image/Makefile
@@ -2,4 +2,9 @@
#
# Copyright 2021 Google LLC
-obj-$(CONFIG_SPL_BUILD) += spl_load.o
+obj-y += spl_load.o
+obj-$(CONFIG_SPL_UT_LOAD_FS) += spl_load_fs.o
+obj-$(CONFIG_SPL_UT_LOAD_NET) += spl_load_net.o
+obj-$(CONFIG_SPL_NOR_SUPPORT) += spl_load_nor.o
+obj-$(CONFIG_SPL_UT_LOAD_OS) += spl_load_os.o
+obj-$(CONFIG_SPL_UT_LOAD_SPI) += spl_load_spi.o
diff --git a/test/image/spl_load.c b/test/image/spl_load.c
index 4e27ff4..ab4c14d 100644
--- a/test/image/spl_load.c
+++ b/test/image/spl_load.c
@@ -1,48 +1,19 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2021 Google LLC
- * Written by Simon Glass <sjg@chromium.org>
+ * Copyright (C) 2023 Sean Anderson <seanga2@gmail.com>
*/
#include <common.h>
#include <image.h>
+#include <imx_container.h>
#include <mapmem.h>
-#include <os.h>
+#include <memalign.h>
+#include <rand.h>
+#include <spi_flash.h>
#include <spl.h>
+#include <test/spl.h>
#include <test/ut.h>
-
-/* Declare a new SPL test */
-#define SPL_TEST(_name, _flags) UNIT_TEST(_name, _flags, spl_test)
-
-/* Context used for this test */
-struct text_ctx {
- int fd;
-};
-
-static ulong read_fit_image(struct spl_load_info *load, ulong sector,
- ulong count, void *buf)
-{
- struct text_ctx *text_ctx = load->priv;
- off_t offset, ret;
- ssize_t res;
-
- offset = sector * load->bl_len;
- ret = os_lseek(text_ctx->fd, offset, OS_SEEK_SET);
- if (ret != offset) {
- printf("Failed to seek to %zx, got %zx (errno=%d)\n", offset,
- ret, errno);
- return 0;
- }
-
- res = os_read(text_ctx->fd, buf, count * load->bl_len);
- if (res == -1) {
- printf("Failed to read %lx bytes, got %ld (errno=%d)\n",
- count * load->bl_len, res, errno);
- return 0;
- }
-
- return count;
-}
+#include <u-boot/crc.h>
int board_fit_config_name_match(const char *name)
{
@@ -54,38 +25,637 @@
return map_sysmem(0x100000, 0);
}
-static int spl_test_load(struct unit_test_state *uts)
+/* Try to reuse the load buffer to conserve memory */
+void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
{
- struct spl_image_info image;
- struct legacy_img_hdr *header;
- struct text_ctx text_ctx;
- struct spl_load_info load;
- char fname[256];
- int ret;
- int fd;
+ static void *buf;
+ static size_t size;
- memset(&load, '\0', sizeof(load));
- load.bl_len = 512;
- load.read = read_fit_image;
-
- ret = sandbox_find_next_phase(fname, sizeof(fname), true);
- if (ret) {
- printf("(%s not found, error %d)\n", fname, ret);
- return ret;
+ if (size < sectors * bl_len) {
+ free(buf);
+ size = sectors * bl_len;
+ buf = malloc_cache_aligned(size);
}
- load.filename = fname;
+ return buf;
+}
- header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
+/* Local flags for spl_image; start from the "top" to avoid conflicts */
+#define SPL_IMX_CONTAINER 0x80000000
+#define SPL_COMP_LZMA 0x40000000
- fd = os_open(fname, OS_O_RDONLY);
- ut_assert(fd >= 0);
- ut_asserteq(512, os_read(fd, header, 512));
- text_ctx.fd = fd;
+void generate_data(char *data, size_t size, const char *test_name)
+{
+ int i;
+ unsigned int seed = 1;
- load.priv = &text_ctx;
+ while (*test_name) {
+ seed += *test_name++;
+ rand_r(&seed);
+ }
- ut_assertok(spl_load_simple_fit(&image, &load, 0, header));
+ for (i = 0; i < size; i++)
+ data[i] = (i & 0xf) << 4 | (rand_r(&seed) & 0xf);
+}
+
+static size_t create_legacy(void *dst, struct spl_image_info *spl_image,
+ size_t *data_offset)
+{
+ struct legacy_img_hdr *hdr = dst;
+ void *data = dst + sizeof(*hdr);
+
+ if (data_offset)
+ *data_offset = data - dst;
+
+ if (!dst)
+ goto out;
+
+ image_set_magic(hdr, IH_MAGIC);
+ image_set_time(hdr, 0);
+ image_set_size(hdr, spl_image->size);
+ image_set_load(hdr, spl_image->load_addr);
+ image_set_ep(hdr, spl_image->entry_point);
+ image_set_dcrc(hdr, crc32(0, data, spl_image->size));
+ image_set_os(hdr, spl_image->os);
+ image_set_arch(hdr, IH_ARCH_DEFAULT);
+ image_set_type(hdr, IH_TYPE_FIRMWARE);
+ image_set_comp(hdr, spl_image->flags & SPL_COMP_LZMA ? IH_COMP_LZMA :
+ IH_COMP_NONE);
+ image_set_name(hdr, spl_image->name);
+ image_set_hcrc(hdr, crc32(0, (void *)hdr, sizeof(*hdr)));
+
+out:
+ return sizeof(*hdr) + spl_image->size;
+}
+
+static size_t create_imx8(void *dst, struct spl_image_info *spl_image,
+ size_t *data_offset)
+{
+ struct container_hdr *hdr = dst;
+ struct boot_img_t *img = dst + sizeof(*hdr);
+ size_t length = sizeof(*hdr) + sizeof(*img);
+ /* Align to MMC block size for now */
+ void *data = dst + 512;
+
+ if (data_offset)
+ *data_offset = data - dst;
+
+ if (!dst)
+ goto out;
+
+ hdr->version = CONTAINER_HDR_VERSION;
+ hdr->length_lsb = length & 0xff;
+ hdr->length_msb = length >> 8;
+ hdr->tag = CONTAINER_HDR_TAG;
+ hdr->num_images = 1;
+
+ /* spl_load_imx_container doesn't handle endianness; whoops! */
+ img->offset = data - dst;
+ img->size = spl_image->size;
+ img->dst = spl_image->load_addr;
+ img->entry = spl_image->entry_point;
+
+out:
+ return data - dst + spl_image->size;
+}
+
+#define ADDRESS_CELLS (sizeof(uintptr_t) / sizeof(u32))
+
+static inline int fdt_property_addr(void *fdt, const char *name, uintptr_t val)
+{
+ if (sizeof(uintptr_t) == sizeof(u32))
+ return fdt_property_u32(fdt, name, val);
+ return fdt_property_u64(fdt, name, val);
+}
+
+static size_t start_fit(void *dst, size_t fit_size, size_t data_size,
+ bool external)
+{
+ void *data;
+
+ if (fdt_create(dst, fit_size))
+ return 0;
+ if (fdt_finish_reservemap(dst))
+ return 0;
+ if (fdt_begin_node(dst, ""))
+ return 0;
+ if (fdt_property_u32(dst, FIT_TIMESTAMP_PROP, 0))
+ return 0;
+ if (fdt_property_u32(dst, "#address-cells", ADDRESS_CELLS))
+ return 0;
+ if (fdt_property_string(dst, FIT_DESC_PROP, ""))
+ return 0;
+
+ if (fdt_begin_node(dst, "images"))
+ return 0;
+ if (fdt_begin_node(dst, "u-boot"))
+ return 0;
+
+ if (external) {
+ if (fdt_property_u32(dst, FIT_DATA_OFFSET_PROP, 0))
+ return 0;
+ return fit_size;
+ }
+
+ if (fdt_property_placeholder(dst, FIT_DATA_PROP, data_size, &data))
+ return 0;
+ return data - dst;
+}
+
+static size_t create_fit(void *dst, struct spl_image_info *spl_image,
+ size_t *data_offset, bool external)
+{
+ size_t prop_size = 596, total_size = prop_size + spl_image->size;
+ size_t off, size;
+
+ if (external) {
+ size = prop_size;
+ off = size;
+ } else {
+ char tmp[256];
+
+ size = total_size;
+ off = start_fit(tmp, sizeof(tmp), 0, false);
+ if (!off)
+ return 0;
+ }
+
+ if (data_offset)
+ *data_offset = off;
+
+ if (!dst)
+ goto out;
+
+ if (start_fit(dst, size, spl_image->size, external) != off)
+ return 0;
+
+ if (fdt_property_string(dst, FIT_DESC_PROP, spl_image->name))
+ return 0;
+ if (fdt_property_string(dst, FIT_TYPE_PROP, "firmware"))
+ return 0;
+ if (fdt_property_string(dst, FIT_COMP_PROP, "none"))
+ return 0;
+ if (fdt_property_u32(dst, FIT_DATA_SIZE_PROP, spl_image->size))
+ return 0;
+ if (fdt_property_string(dst, FIT_OS_PROP,
+ genimg_get_os_short_name(spl_image->os)))
+ return 0;
+ if (fdt_property_string(dst, FIT_ARCH_PROP,
+ genimg_get_arch_short_name(IH_ARCH_DEFAULT)))
+ return 0;
+ if (fdt_property_addr(dst, FIT_ENTRY_PROP, spl_image->entry_point))
+ return 0;
+ if (fdt_property_addr(dst, FIT_LOAD_PROP, spl_image->load_addr))
+ return 0;
+ if (fdt_end_node(dst)) /* u-boot */
+ return 0;
+ if (fdt_end_node(dst)) /* images */
+ return 0;
+
+ if (fdt_begin_node(dst, "configurations"))
+ return 0;
+ if (fdt_property_string(dst, FIT_DEFAULT_PROP, "config-1"))
+ return 0;
+ if (fdt_begin_node(dst, "config-1"))
+ return 0;
+ if (fdt_property_string(dst, FIT_DESC_PROP, spl_image->name))
+ return 0;
+ if (fdt_property_string(dst, FIT_FIRMWARE_PROP, "u-boot"))
+ return 0;
+ if (fdt_end_node(dst)) /* configurations */
+ return 0;
+ if (fdt_end_node(dst)) /* config-1 */
+ return 0;
+
+ if (fdt_end_node(dst)) /* root */
+ return 0;
+ if (fdt_finish(dst))
+ return 0;
+
+ if (external) {
+ if (fdt_totalsize(dst) > size)
+ return 0;
+ fdt_set_totalsize(dst, size);
+ }
+
+out:
+ return total_size;
+}
+
+size_t create_image(void *dst, enum spl_test_image type,
+ struct spl_image_info *info, size_t *data_offset)
+{
+ bool external = false;
+
+ info->os = IH_OS_U_BOOT;
+ info->load_addr = CONFIG_TEXT_BASE;
+ info->entry_point = CONFIG_TEXT_BASE + 0x100;
+ info->flags = 0;
+
+ switch (type) {
+ case LEGACY_LZMA:
+ info->flags = SPL_COMP_LZMA;
+ case LEGACY:
+ return create_legacy(dst, info, data_offset);
+ case IMX8:
+ info->flags = SPL_IMX_CONTAINER;
+ return create_imx8(dst, info, data_offset);
+ case FIT_EXTERNAL:
+ /*
+ * spl_fit_append_fdt will clobber external images with U-Boot's
+ * FDT if the image doesn't have one. Just set the OS to
+ * something which doesn't take a devicetree.
+ */
+ if (!IS_ENABLED(CONFIG_LOAD_FIT_FULL))
+ info->os = IH_OS_TEE;
+ external = true;
+ case FIT_INTERNAL:
+ info->flags = SPL_FIT_FOUND;
+ return create_fit(dst, info, data_offset, external);
+ }
return 0;
}
-SPL_TEST(spl_test_load, 0);
+
+int check_image_info(struct unit_test_state *uts, struct spl_image_info *info1,
+ struct spl_image_info *info2)
+{
+ if (info2->name) {
+ if (info1->flags & SPL_FIT_FOUND)
+ ut_asserteq_str(genimg_get_os_name(info1->os),
+ info2->name);
+ else
+ ut_asserteq_str(info1->name, info2->name);
+ }
+
+ if (info1->flags & SPL_IMX_CONTAINER)
+ ut_asserteq(IH_OS_INVALID, info2->os);
+ else
+ ut_asserteq(info1->os, info2->os);
+
+ ut_asserteq(info1->entry_point, info2->entry_point);
+ if (info1->flags & (SPL_FIT_FOUND | SPL_IMX_CONTAINER) ||
+ info2->flags & SPL_COPY_PAYLOAD_ONLY) {
+ ut_asserteq(info1->load_addr, info2->load_addr);
+ if (info1->flags & SPL_IMX_CONTAINER)
+ ut_asserteq(0, info2->size);
+ else if (!(info1->flags & SPL_COMP_LZMA))
+ ut_asserteq(info1->size, info2->size);
+ } else {
+ ut_asserteq(info1->load_addr - sizeof(struct legacy_img_hdr),
+ info2->load_addr);
+ ut_asserteq(info1->size + sizeof(struct legacy_img_hdr),
+ info2->size);
+ }
+
+ return 0;
+}
+
+static ulong spl_test_read(struct spl_load_info *load, ulong sector,
+ ulong count, void *buf)
+{
+ memcpy(buf, load->priv + sector, count);
+ return count;
+}
+
+static int spl_test_image(struct unit_test_state *uts, const char *test_name,
+ enum spl_test_image type)
+{
+ size_t img_size, img_data, data_size = SPL_TEST_DATA_SIZE;
+ struct spl_image_info info_write = {
+ .name = test_name,
+ .size = data_size,
+ }, info_read = { };
+ char *data;
+ void *img;
+
+ img_size = create_image(NULL, type, &info_write, &img_data);
+ ut_assert(img_size);
+ img = calloc(img_size, 1);
+ ut_assertnonnull(img);
+
+ data = img + img_data;
+ generate_data(data, data_size, test_name);
+ ut_asserteq(img_size, create_image(img, type, &info_write, NULL));
+
+ if (type == LEGACY) {
+ ut_assertok(spl_parse_image_header(&info_read, NULL, img));
+ if (check_image_info(uts, &info_write, &info_read))
+ return CMD_RET_FAILURE;
+ } else {
+ struct spl_load_info load = {
+ .bl_len = 1,
+ .priv = img,
+ .read = spl_test_read,
+ };
+
+ if (type == IMX8)
+ ut_assertok(spl_load_imx_container(&info_read, &load,
+ 0));
+ else if (IS_ENABLED(CONFIG_SPL_FIT_FULL))
+ ut_assertok(spl_parse_image_header(&info_read, NULL,
+ img));
+ else
+ ut_assertok(spl_load_simple_fit(&info_read, &load, 0,
+ img));
+ if (check_image_info(uts, &info_write, &info_read))
+ return CMD_RET_FAILURE;
+ ut_asserteq_mem(data, phys_to_virt(info_write.load_addr),
+ data_size);
+ }
+
+ free(img);
+ return 0;
+}
+SPL_IMG_TEST(spl_test_image, LEGACY, 0);
+SPL_IMG_TEST(spl_test_image, IMX8, 0);
+SPL_IMG_TEST(spl_test_image, FIT_INTERNAL, 0);
+SPL_IMG_TEST(spl_test_image, FIT_EXTERNAL, 0);
+
+/*
+ * LZMA is too complex to generate on the fly, so let's use some data I put in
+ * the oven^H^H^H^H compressed earlier
+ */
+static const char lzma_compressed[] = {
+ 0x5d, 0x00, 0x00, 0x80, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0x00, 0x02, 0x05, 0x55, 0x4e, 0x82, 0xbc, 0xc2, 0x42, 0xf6, 0x88,
+ 0x6c, 0x99, 0xd6, 0x82, 0x48, 0xa6, 0x06, 0x67, 0xf8, 0x46, 0x7c, 0xe9,
+ 0x41, 0x79, 0xfe, 0x90, 0x0b, 0x31, 0x7b, 0x79, 0x91, 0xb8, 0x5f, 0x33,
+ 0x11, 0x04, 0xc3, 0x4f, 0xf5, 0x71, 0xd1, 0xfb, 0x94, 0x6b, 0x5f, 0x78,
+ 0xe2, 0xfa, 0x6a, 0x21, 0xb6, 0x1d, 0x11, 0x0e, 0x5b, 0x56, 0x6a, 0x5b,
+ 0xe9, 0x56, 0x5f, 0x8b, 0x87, 0x61, 0x96, 0x6d, 0xce, 0x66, 0xbb, 0xb6,
+ 0xe7, 0x13, 0x5a, 0xd8, 0x84, 0x29, 0x60, 0xa0, 0x80, 0x43, 0xdd, 0x0f,
+ 0x4b, 0x85, 0xb0, 0x04, 0x9d, 0x9f, 0x28, 0x97, 0x0a, 0x1e, 0x16, 0xb0,
+ 0x45, 0x33, 0x5e, 0x79, 0x4f, 0xaa, 0xee, 0x79, 0x6e, 0xc3, 0x4e, 0x3d,
+ 0xe8, 0x67, 0x7c, 0xe0, 0xd0, 0xcc, 0x05, 0x40, 0xae, 0x6b, 0x97, 0x82,
+ 0x97, 0x02, 0x01, 0xe2, 0xe3, 0xbc, 0xe4, 0x9b, 0xb3, 0x28, 0xed, 0x5e,
+ 0x0d, 0x68, 0x6e, 0xe5, 0x17, 0x0a, 0x86, 0x5a, 0xcd, 0x8d, 0x46, 0x2d,
+ 0x06, 0x10, 0xa6, 0x90, 0x44, 0xa1, 0xfc, 0x66, 0x6d, 0x7c, 0x57, 0x57,
+ 0x07, 0xbc, 0x95, 0xb2, 0x8d, 0xf0, 0x9f, 0x4d, 0x90, 0x04, 0xaf, 0x0c,
+ 0x23, 0x51, 0x1b, 0x34, 0xd5, 0x5c, 0x5d, 0x87, 0x5e, 0x10, 0x2b, 0x71,
+ 0xc2, 0xcf, 0xc5, 0x9d, 0x4b, 0x89, 0x01, 0xc4, 0x97, 0xf2, 0xea, 0x83,
+ 0x97, 0xfa, 0xe0, 0x51, 0x96, 0x78, 0x4f, 0x44, 0xb8, 0xa8, 0x9d, 0x03,
+ 0x1c, 0x6e, 0xb7, 0xc6, 0xd7, 0xc5, 0x3e, 0x32, 0x65, 0xa7, 0x06, 0xab,
+ 0x86, 0xfb, 0xd2, 0x9b, 0xd7, 0x86, 0xa8, 0xfe, 0x46, 0x41, 0x2e, 0xc2,
+ 0x4e, 0xed, 0xa2, 0x9b, 0x79, 0x36, 0x37, 0x49, 0x90, 0xfc, 0xa6, 0x14,
+ 0x93, 0x17, 0x82, 0x62, 0x3f, 0x79, 0x6b, 0x86, 0xc2, 0xeb, 0x82, 0xfe,
+ 0x87, 0x49, 0xa5, 0x7e, 0x41, 0xe3, 0x59, 0x60, 0x15, 0x61, 0x4e, 0x3b,
+ 0x16, 0xcf, 0xdb, 0x49, 0x2c, 0x84, 0x92, 0x26, 0x40, 0x04, 0x78, 0xd3,
+ 0xd6, 0xa6, 0xed, 0x6e, 0x63, 0x49, 0xcb, 0xea, 0xfe, 0x43, 0x85, 0x21,
+ 0x1a, 0x28, 0x36, 0x0a, 0x3e, 0x2a, 0xad, 0xba, 0xfc, 0x8a, 0x37, 0x18,
+ 0xb4, 0x80, 0xbe, 0x6a, 0x36, 0x14, 0x03, 0xdd, 0xa3, 0x37, 0xbd, 0xc1,
+ 0x8a, 0xbb, 0x2d, 0xd4, 0x08, 0xd7, 0x4b, 0xc4, 0xe9, 0xb8, 0xb4, 0x65,
+ 0xdd, 0xf6, 0xe8, 0x17, 0x2c, 0x2c, 0x9b, 0x1e, 0x92, 0x0b, 0xcb, 0x22,
+ 0x7c, 0x1b, 0x74, 0x8d, 0x65, 0x11, 0x5f, 0xfe, 0xf5, 0x2a, 0xc2, 0xbe,
+ 0xea, 0xa2, 0xf1, 0x7b, 0xe8, 0xaf, 0x32, 0x5a, 0x0a, 0x5b, 0xd2, 0x5a,
+ 0x11, 0x22, 0x79, 0xfa, 0xae, 0x2d, 0xe8, 0xc6, 0x17, 0xba, 0x17, 0x81,
+ 0x6a, 0x63, 0xb5, 0x26, 0xd7, 0x8d, 0xd0, 0x66, 0x0c, 0x4a, 0x0c, 0x22,
+ 0x1b, 0x20, 0x9f, 0x3d, 0x0b, 0x1b, 0x59, 0x53, 0x89, 0x9b, 0x5e, 0xbd,
+ 0x3d, 0xd1, 0xdd, 0xff, 0xca, 0xb2, 0xb7, 0x12, 0x8d, 0x03, 0xaa, 0xc3,
+ 0x1d, 0x56, 0x76, 0x14, 0xf8, 0xee, 0xb3, 0xeb, 0x80, 0x38, 0xc1, 0xc1,
+ 0x1a, 0xef, 0x4a, 0xd5, 0x16, 0x1f, 0x5e, 0x21, 0x5d, 0x46, 0x01, 0xb3,
+ 0xa4, 0xf7, 0x99, 0x94, 0x05, 0xc6, 0xc8, 0x06, 0xd8, 0x1c, 0xac, 0x47,
+ 0x13, 0x54, 0x13, 0x1b, 0x1f, 0xb6, 0x23, 0x9c, 0x73, 0x2b, 0x57, 0x32,
+ 0x94, 0x92, 0xf1, 0x71, 0x44, 0x40, 0x02, 0xc3, 0x21, 0x4a, 0x2f, 0x36,
+ 0x5e, 0x8a, 0xd0, 0x4b, 0x02, 0xc7, 0x6e, 0xcf, 0xed, 0xa2, 0xdb, 0xce,
+ 0x0a, 0x0f, 0x66, 0x4f, 0xb2, 0x3d, 0xb6, 0xcc, 0x75, 0x45, 0x80, 0x0a,
+ 0x49, 0x4a, 0xe7, 0xe7, 0x24, 0x62, 0x65, 0xc7, 0x02, 0x22, 0x13, 0xbe,
+ 0x6c, 0xa9, 0x9a, 0x8b, 0xa9, 0x1b, 0x2b, 0x3a, 0xde, 0x5e, 0x37, 0xbd,
+ 0x7f, 0x85, 0xd1, 0x32, 0x1d, 0xbf, 0x03, 0x8a, 0x3b, 0xe5, 0xb3, 0xfd,
+ 0x01, 0xca, 0xde, 0x0d, 0x7a, 0x5b, 0x01, 0x05, 0x1d, 0x3c, 0x23, 0x00,
+ 0x60, 0xb7, 0x50, 0xfd, 0x0d, 0xd7, 0x63, 0x92, 0xd6, 0xb0, 0x48, 0x3a,
+ 0x2d, 0xa3, 0xf8, 0xf6, 0x44, 0xe1, 0xda, 0x3b, 0xf4, 0x39, 0x47, 0xc4,
+ 0x4d, 0x8f, 0x54, 0x78, 0xec, 0x27, 0x7b, 0xc6, 0xe4, 0x81, 0x3a, 0x3f,
+ 0xa5, 0x61, 0x9d, 0xcb, 0x71, 0x0b, 0x0d, 0x55, 0xea, 0x5b, 0xeb, 0x58,
+ 0xa5, 0x49, 0xb5, 0x44, 0x1b, 0xb0, 0x0d, 0x1f, 0x58, 0xfb, 0x7a, 0xd4,
+ 0x09, 0x1e, 0x9a, 0x7e, 0x21, 0xba, 0xb3, 0x36, 0xa6, 0x04, 0x74, 0xe1,
+ 0xd0, 0xca, 0x02, 0x11, 0x84, 0x93, 0x8f, 0x86, 0x3d, 0x79, 0xbf, 0xa8,
+ 0xec, 0x0a, 0x23, 0x5e, 0xde, 0xc4, 0xc6, 0xda, 0x45, 0xbd, 0x95, 0x74,
+ 0x7b, 0xbf, 0xc1, 0x80, 0x48, 0x3f, 0x10, 0xb6, 0xb9, 0x5c, 0x31, 0x52,
+ 0x06, 0x5a, 0xac, 0xec, 0x94, 0x21, 0x80, 0x51, 0xba, 0x64, 0xed, 0x9d,
+ 0x27, 0x72, 0x8d, 0x17, 0x43, 0x5f, 0xf1, 0x60, 0xfa, 0xb5, 0x65, 0xd4,
+ 0xb9, 0xf8, 0xfc, 0x48, 0x7b, 0xe3, 0xfe, 0xae, 0xe4, 0x71, 0x4a, 0x3d,
+ 0x8c, 0xf5, 0x72, 0x8b, 0xbf, 0x60, 0xd8, 0x6a, 0x8f, 0x51, 0x82, 0xae,
+ 0x98, 0xd0, 0x56, 0xf9, 0xa8, 0x3a, 0xad, 0x86, 0x26, 0xa8, 0x5a, 0xf8,
+ 0x63, 0x87, 0x2c, 0x74, 0xbf, 0xf9, 0x7d, 0x00, 0xa0, 0x2f, 0x17, 0x23,
+ 0xb7, 0x62, 0x94, 0x19, 0x47, 0x57, 0xf9, 0xa8, 0xe7, 0x4b, 0xe9, 0x2b,
+ 0xe8, 0xb4, 0x03, 0xbf, 0x23, 0x75, 0xfe, 0xc3, 0x94, 0xc0, 0xa9, 0x5b,
+ 0x07, 0xb5, 0x75, 0x87, 0xcc, 0xa5, 0xb5, 0x9b, 0x35, 0x29, 0xe4, 0xb1,
+ 0xaa, 0x04, 0x57, 0xe9, 0xa3, 0xd0, 0xa3, 0xe4, 0x11, 0xe1, 0xaa, 0x3b,
+ 0x67, 0x09, 0x60, 0x83, 0x23, 0x72, 0xa6, 0x7b, 0x73, 0x22, 0x5b, 0x4a,
+ 0xe0, 0xf0, 0xa3, 0xeb, 0x9c, 0x91, 0xda, 0xba, 0x8b, 0xc1, 0x32, 0xa9,
+ 0x24, 0x13, 0x51, 0xe4, 0x67, 0x49, 0x4a, 0xd9, 0x3d, 0xae, 0x80, 0xfd,
+ 0x0a, 0x0d, 0x56, 0x98, 0x66, 0xa2, 0x6d, 0x92, 0x54, 0x7f, 0x82, 0xe5,
+ 0x17, 0x39, 0xd3, 0xaa, 0xc4, 0x4e, 0x6f, 0xe1, 0x2e, 0xfe, 0x03, 0x44,
+ 0x8a, 0xdd, 0xeb, 0xc0, 0x74, 0x79, 0x63, 0x33, 0x2b, 0x4b, 0xb5, 0x62,
+ 0xdd, 0x47, 0xba, 0x6e, 0xfc, 0x91, 0x08, 0xa9, 0x17, 0x8c, 0x47, 0x61,
+ 0xd9, 0x32, 0xe9, 0xa0, 0xb3, 0xa2, 0x82, 0xc9, 0xa6, 0x32, 0xa1, 0xca,
+ 0x7c, 0x41, 0xa6, 0x5a, 0xe2, 0x46, 0xb6, 0x45, 0x53, 0x72, 0x55, 0x9e,
+ 0xdf, 0xac, 0x96, 0x68, 0xe5, 0xdc, 0x4e, 0x2d, 0xa8, 0x1e, 0x7a, 0x8e,
+ 0xff, 0x54, 0xe4, 0x0a, 0x33, 0x5d, 0x97, 0xdf, 0x4e, 0x36, 0x96, 0xba,
+ 0x52, 0xd9, 0xa9, 0xec, 0x52, 0xe5, 0x1d, 0x94, 0xfe, 0x1c, 0x46, 0x54,
+ 0xa6, 0x8e, 0x85, 0x47, 0xba, 0xeb, 0x4b, 0x8d, 0x57, 0xe4, 0x34, 0x24,
+ 0x9e, 0x80, 0xb5, 0xc9, 0xa9, 0x94, 0x1d, 0xe4, 0x18, 0xb6, 0x07, 0x1e,
+ 0xfa, 0xe0, 0x1c, 0x88, 0x06, 0x84, 0xaa, 0xcb, 0x5e, 0xfa, 0x15, 0x5a,
+ 0xdd, 0x10, 0x43, 0x81, 0xf2, 0x50, 0x3e, 0x93, 0x26, 0x77, 0x1c, 0x77,
+ 0xe9, 0x0c, 0xfc, 0x5f, 0xdd, 0x67, 0x31, 0x02, 0xc6, 0xdd, 0xf4, 0x30,
+ 0x76, 0x51, 0xce, 0x56, 0xba, 0x7f, 0x44, 0xbd, 0x42, 0x9f, 0x10, 0x8c,
+ 0x56, 0x49, 0x48, 0xa2, 0xcb, 0xc4, 0xdd, 0x29, 0xae, 0xf0, 0x33, 0x35,
+ 0x46, 0x69, 0x1d, 0xae, 0xde, 0xde, 0x98, 0x82, 0x79, 0xa6, 0x50, 0x28,
+ 0xb3, 0x5f, 0x10, 0x24, 0x63, 0xee, 0x9a, 0x22, 0xbe, 0xf8, 0x3a, 0xf4,
+ 0xab, 0x98, 0xfe, 0xdf, 0x30, 0x03, 0xe8, 0x45, 0x8c, 0xf4, 0x85, 0xc6,
+ 0x98, 0x7b, 0x35, 0xb8, 0x30, 0x9c, 0x15, 0xa6, 0x45, 0xbd, 0x39, 0x84,
+ 0xe7, 0x43, 0x4b, 0x05, 0xa4, 0x8f, 0x52, 0x8e, 0x4a, 0xe4, 0x87, 0xc1,
+ 0xdc, 0xdf, 0x25, 0x9c, 0x5c, 0x37, 0xd0, 0x66, 0x12, 0x41, 0x66, 0x8c,
+ 0x28, 0xd0, 0x3f, 0x5c, 0x7f, 0x15, 0x9b, 0xcf, 0xa0, 0xae, 0x29, 0x33,
+ 0xb0, 0xe4, 0xb7, 0x36, 0x2a, 0x45, 0x83, 0xff, 0x86, 0x75, 0xcf, 0xa7,
+ 0x4d, 0x5c, 0xa8, 0xcf, 0x3f, 0xf2, 0xc8, 0xde, 0xdd, 0xad, 0x42, 0x8f,
+ 0x0e, 0xd0, 0x11, 0x24, 0x42, 0x86, 0x51, 0x52, 0x76, 0x21, 0x68, 0xf1,
+ 0xa7, 0x8f, 0xdb, 0x5b, 0x78, 0xfa, 0x44, 0x5f, 0xee, 0x31, 0xda, 0x62,
+ 0x5f, 0xfe, 0x69, 0xae, 0x97, 0xc9, 0xb5, 0x04, 0x76, 0x79, 0x2e, 0xb9,
+ 0xd9, 0x1b, 0xdd, 0xb7, 0xc4, 0x12, 0x78, 0xb2, 0x4d, 0xab, 0xd2, 0x29,
+ 0x25, 0x8c, 0xd5, 0x52, 0x4a, 0xd7, 0x2e, 0x18, 0x9d, 0xa2, 0xee, 0x7b,
+ 0xa5, 0xe5, 0x35, 0x3c, 0xb5, 0x54, 0x1c, 0x7f, 0x87, 0x4b, 0xc0, 0xbb,
+ 0x1a, 0x85, 0x19, 0xc0, 0xa9, 0x2b, 0x4d, 0xed, 0x71, 0xc0, 0x15, 0xb3,
+ 0x49, 0x2c, 0x46, 0xfc, 0x37, 0x40, 0xc0, 0x60, 0xd0, 0x00, 0x96, 0xfa,
+ 0x7f, 0xbb, 0x30, 0x94, 0x6b, 0x81, 0x61, 0xc5, 0x13, 0x93, 0x95, 0xaa,
+ 0xf3, 0x8d, 0x1d, 0xac, 0xdb, 0xbd, 0xc3, 0x90, 0xf3, 0xd2, 0x5f, 0x3a,
+ 0x08, 0xb1, 0xc9, 0x3a, 0xe8, 0x25, 0x4d, 0x20, 0x2a, 0xe9, 0x4c, 0xaf,
+ 0x9b, 0x54, 0x7b, 0xaf, 0x89, 0x44, 0x3a, 0x60, 0x23, 0xd3, 0x02, 0xb1,
+ 0xb3, 0x9a, 0x3a, 0xb0, 0xa0, 0xdb, 0x61, 0x0b, 0xac, 0x55, 0xa1, 0x36,
+ 0x55, 0x5b, 0xc4, 0xc5, 0xbd, 0x2a, 0x16, 0xe9, 0xe7, 0x86, 0x7f, 0xdb,
+ 0xee, 0x90, 0xfa, 0xfd, 0x08, 0x7f, 0x1a, 0x43, 0xe0, 0xb8, 0x21, 0xb3,
+ 0xe3, 0xdf, 0x27, 0x56, 0x61, 0xc4, 0xe8, 0xd5, 0x60, 0xe9, 0x6d, 0x49,
+ 0xd9, 0xa8, 0xf5, 0xd9, 0xfc, 0x66, 0x82, 0xe9, 0x80, 0x5b, 0x85, 0x16,
+ 0x55, 0x2b, 0xef, 0x50, 0x90, 0x6c, 0x5d, 0x81, 0x00, 0x00, 0x88, 0x9b,
+ 0xb4, 0x62, 0x49, 0x46, 0x2e, 0x5d, 0x71, 0x95, 0xff, 0x63, 0xfb, 0x93,
+ 0x23, 0xf8, 0x9f, 0xa2, 0x55, 0x56, 0xd4, 0xd5, 0xf7, 0xae, 0xaf, 0xd3,
+ 0xf6, 0x82, 0xc8, 0xdd, 0x89, 0x0f, 0x7e, 0x89, 0x0d, 0x0d, 0x7f, 0x4f,
+ 0x84, 0xa7, 0x16, 0xe8, 0xaf, 0xf2, 0x95, 0xd7, 0xc3, 0x66, 0xd6, 0x85,
+ 0x5b, 0xa1, 0xbb, 0xea, 0x31, 0x02, 0xac, 0xa2, 0x7b, 0x50, 0xf4, 0x78,
+ 0x29, 0x49, 0x59, 0xf6, 0x41, 0x42, 0x52, 0xa8, 0x19, 0xfb, 0x3d, 0xda,
+ 0xa9, 0x8d, 0xac, 0xe1, 0x25, 0xd4, 0x12, 0x1e, 0x2b, 0x48, 0x44, 0xb0,
+ 0xf6, 0x29, 0xd0, 0x55, 0x22, 0xb4, 0xe7, 0xbc, 0x22, 0x97, 0x1f, 0xe2,
+ 0xe1, 0x73, 0x16, 0x13, 0x7a, 0x00, 0x62, 0x14, 0xcb, 0x25, 0x9b, 0x21,
+ 0x98, 0x9d, 0xb8, 0xd8, 0xf4, 0x65, 0xf6, 0x8f, 0x39, 0xe4, 0x76, 0xf7,
+ 0x30, 0xaf, 0xbc, 0x3a, 0xfe, 0x0e, 0xf1, 0x81, 0xa7, 0xff, 0x4d, 0xa7,
+ 0xff, 0xbf, 0x15, 0x60, 0x0b, 0xcd, 0x69, 0xd5, 0x77, 0xba, 0xcb, 0x7b,
+ 0x5a, 0xfb, 0x34, 0xc7, 0x5d, 0x13, 0x33, 0xd7, 0x86, 0x02, 0x43, 0x57,
+ 0x52, 0x2c, 0x74, 0x61, 0x21, 0xa3, 0x34, 0xf5, 0x89, 0x51, 0x44, 0x89,
+ 0xfc, 0xbb, 0x57, 0x5c, 0x6d, 0xb0, 0x2e, 0x8c, 0xff, 0x73, 0xe5, 0x09,
+ 0x13, 0x3b, 0x45, 0x5b, 0x27, 0x88, 0xee, 0x9b, 0xab, 0x57, 0x7c, 0x9b,
+ 0xb9, 0x78, 0x73, 0xd2, 0x2d, 0x98, 0x6f, 0xd2, 0x78, 0xb3, 0xeb, 0xaa,
+ 0x18, 0x44, 0x87, 0x6d, 0x51, 0x1e, 0x9b, 0x73, 0xaa, 0x91, 0x1a, 0x4f,
+ 0x69, 0x78, 0xef, 0x3f, 0xb1, 0x2d, 0x39, 0x3e, 0xda, 0x31, 0xfc, 0x99,
+ 0xf6, 0xa2, 0x8c, 0xe5, 0xfd, 0x97, 0x95, 0x77, 0x37, 0xef, 0xf5, 0xd1,
+ 0xc8, 0x74, 0x2c, 0x9a, 0x1f, 0x23, 0x8f, 0x72, 0x96, 0x3d, 0xb5, 0xad,
+ 0x28, 0xa0, 0x6c, 0x66, 0xe8, 0xee, 0xaa, 0x9d, 0xc2, 0x8a, 0x56, 0x54,
+ 0x89, 0x74, 0x56, 0xdc, 0x57, 0x49, 0xc3, 0x8e, 0xb9, 0x3a, 0x91, 0x34,
+ 0xc4, 0x5e, 0x0b, 0x13, 0x63, 0x5e, 0xeb, 0xc5, 0xef, 0xc7, 0xe9, 0x7f,
+ 0x27, 0xe8, 0xe7, 0xe5, 0x0d, 0x83, 0x95, 0x5f, 0x8a, 0xf2, 0xb2, 0x22,
+ 0x03, 0x8d, 0x71, 0x4f, 0x62, 0xb7, 0xf1, 0x87, 0xf5, 0x3f, 0xc4, 0x23,
+ 0x21, 0x40, 0x35, 0xcf, 0x79, 0x7a, 0x5b, 0x9d, 0x76, 0xb2, 0xdc, 0x6a,
+ 0xb5, 0x1d, 0x8b, 0xb6, 0x9a, 0x19, 0xe4, 0x87, 0xf5, 0xce, 0x38, 0xf3,
+ 0x70, 0xbf, 0x9e, 0x86, 0xa6, 0x07, 0x53, 0xdd, 0x5d, 0xc7, 0x72, 0x84,
+ 0x47, 0x38, 0xd0, 0xe2, 0xeb, 0x64, 0x4c, 0x3a, 0x1e, 0xf6, 0x56, 0x79,
+ 0x75, 0x75, 0x14, 0x5d, 0xe4, 0x1d, 0x9d, 0xbb, 0xe1, 0x35, 0x03, 0x5e,
+ 0x4f, 0x8f, 0xea, 0x95, 0xde, 0x19, 0x57, 0x98, 0xe9, 0x2c, 0x42, 0x22,
+ 0xcb, 0x0f, 0x15, 0x7a, 0x6b, 0x53, 0xc3, 0xec, 0xdc, 0xa0, 0x66, 0x26,
+ 0x91, 0x04, 0x83, 0x75, 0x09, 0x0c, 0x22, 0x05, 0xec, 0x3a, 0x2d, 0x39,
+ 0xea, 0x19, 0xf2, 0x1d, 0xdb, 0xba, 0x5c, 0x46, 0x47, 0xd4, 0x94, 0x6d,
+ 0x51, 0xdb, 0x68, 0xde, 0x0c, 0xa0, 0x36, 0x8f, 0xbc, 0xfd, 0x9b, 0x8f,
+ 0xfe, 0x04, 0x1f, 0xde, 0x1e, 0x77, 0xb5, 0x80, 0xb9, 0x9c, 0x1b, 0x24,
+ 0x61, 0xfc, 0x2b, 0xc0, 0x42, 0x2b, 0xc5, 0x90, 0x58, 0xa2, 0xb1, 0x38,
+ 0x58, 0xf2, 0x8b, 0x65, 0xbf, 0xe8, 0xe6, 0x79, 0xcf, 0x65, 0x35, 0xa5,
+ 0xe1, 0xb7, 0x8b, 0x95, 0x54, 0xd7, 0x1d, 0xf0, 0x91, 0x18, 0xc0, 0x5d,
+ 0x2c, 0xb5, 0xca, 0x1a, 0x7f, 0x8d, 0xfb, 0x9e, 0x57, 0x1c, 0x5c, 0xf0,
+ 0x94, 0x36, 0x51, 0x95, 0x27, 0x62, 0xca, 0x92, 0x96, 0xe5, 0x00, 0x2e,
+ 0xa4, 0x41, 0x97, 0xbf, 0x28, 0x3c, 0x6d, 0xc1, 0xb7, 0xe9, 0x1c, 0x2e,
+ 0x3e, 0xe0, 0x5e, 0x89, 0x0c, 0x78, 0x88, 0x80, 0xb8, 0x30, 0xd2, 0x22,
+ 0xf9, 0x71, 0xb4, 0xc8, 0xee, 0xe6, 0x80, 0x04, 0x04, 0x9a, 0xfb, 0x0c,
+ 0x36, 0xcb, 0xea, 0x66, 0xf9, 0x52, 0x8c, 0x66, 0xbf, 0x4c, 0x0f, 0xf4,
+ 0xf8, 0x1e, 0x7e, 0x39, 0x80, 0xe8, 0x82, 0x4b, 0x0e, 0x66, 0x1d, 0x51,
+ 0x16, 0xa9, 0x8d, 0xd6, 0xea, 0x33, 0xb0, 0x2c, 0x36, 0x25, 0xf5, 0x01,
+ 0x30, 0x7e, 0x03, 0x7f, 0xae, 0x8e, 0xd6, 0x25, 0x62, 0x6d, 0x99, 0x8c,
+ 0x1f, 0xc1, 0x22, 0xf0, 0x94, 0x80, 0xbf, 0x82, 0x51, 0xea, 0xc2, 0x5a,
+ 0x3c, 0x85, 0x2a, 0x5d, 0xbe, 0xae, 0xe1, 0xe3, 0x07, 0x92, 0xd2, 0x40,
+ 0x47, 0xe8, 0x0f, 0x1a, 0xa5, 0x73, 0x64, 0x26, 0xc4, 0xac, 0xca, 0xc2,
+ 0x83, 0x5a, 0x56, 0xbc, 0x81, 0x21, 0xcb, 0x72, 0xf3, 0xe7, 0x82, 0x1e,
+ 0xc8, 0x54, 0x18, 0x42, 0xfe, 0xd6, 0xfc, 0x96, 0x0e, 0x03, 0x29, 0x98,
+ 0x4f, 0xd1, 0xd2, 0x98, 0x7c, 0x9e, 0x4e, 0x1a, 0x0f, 0xd6, 0x4e, 0xa4,
+ 0x52, 0x1b, 0xd1, 0xd8, 0x36, 0xf7, 0x47, 0x5f, 0xce, 0xcb, 0x87, 0x36,
+ 0xc8, 0x9b, 0x44, 0xc6, 0x7a, 0xf3, 0x45, 0x28, 0xae, 0x96, 0x5a, 0x85,
+ 0x62, 0x8b, 0x10, 0xc2, 0x7b, 0x39, 0x51, 0xdf, 0xf4, 0x21, 0xc2, 0x6b,
+ 0x6f, 0x93, 0x27, 0xed, 0xf6, 0xea, 0xff, 0x2a, 0x21, 0x70, 0x84, 0x4e,
+ 0x21, 0xac, 0xbc, 0x06, 0x41, 0xd3, 0x59, 0xa0, 0xa1, 0x50, 0xa6, 0x87,
+ 0xa2, 0x48, 0xad, 0x94, 0x44, 0x8d, 0x2f, 0xa8, 0xc6, 0x10, 0xb5, 0xeb,
+ 0x66, 0x82, 0x94, 0x5f, 0xae, 0x6a, 0x56, 0xb4, 0x8d, 0xf4, 0x62, 0x80,
+ 0xe4, 0x42, 0xc4, 0xbc, 0xe7, 0xee, 0xa6, 0x96, 0x3b, 0xfd, 0xc0, 0x92,
+ 0x7d, 0xcd, 0xe7, 0x0c, 0x99, 0x9a, 0xb6, 0x83, 0xcf, 0x45, 0xe5, 0x74,
+ 0xb3, 0xbc, 0xc0, 0x40, 0xad, 0x4d, 0xfc, 0xa7, 0x92, 0x35, 0x13, 0x81,
+ 0x5c, 0x9c, 0x21, 0x00, 0xa4, 0x37, 0x07, 0x1d, 0x19, 0xfc, 0x88, 0x4d,
+ 0x71, 0x43, 0x7d, 0x94, 0xf7, 0x32, 0xb8, 0x4b, 0x8a, 0x54, 0xd6, 0xe4,
+ 0x37, 0x4f, 0x27, 0x1f, 0xfd, 0x45, 0x83, 0xb9, 0x14, 0x5a, 0xf7, 0x36,
+ 0xdc, 0x98, 0xad, 0x99, 0xb9, 0x38, 0x69, 0xac, 0x18, 0x7e, 0x47, 0xd0,
+ 0x63, 0x27, 0xba, 0xe7, 0xd5, 0x1d, 0x7b, 0x6e, 0xde, 0x28, 0x7b, 0xf1,
+ 0x84, 0x4d, 0x2d, 0x7c, 0x16, 0x38, 0x4b, 0x16, 0xa9, 0x10, 0x83, 0xfb,
+ 0xe0, 0xe0, 0x6f, 0xdd, 0x03, 0x0a, 0xb8, 0x81, 0xf5, 0x8c, 0x98, 0xc3,
+ 0xf4, 0xc8, 0x31, 0x3a, 0xed, 0x14, 0x83, 0x89, 0xc3, 0x0e, 0xf7, 0xba,
+ 0x84, 0xb0, 0x49, 0xdf, 0xc6, 0x6b, 0xed, 0xbe, 0xd4, 0xa3, 0x83, 0x3a,
+ 0xe6, 0x6d, 0xa3, 0x83, 0x17, 0x43, 0x5e, 0x3a, 0x83, 0xda, 0x81, 0xe3,
+ 0x26, 0x95, 0x6b, 0xe5, 0x30, 0x28, 0x6d, 0xec, 0xd7, 0xd7, 0x35, 0xfa,
+ 0x1a, 0xad, 0x86, 0x04, 0x05, 0x2c, 0x76, 0x3f, 0xb2, 0x83, 0x92, 0x4e,
+ 0xef, 0x05, 0xde, 0x13, 0x26, 0x68, 0x80, 0x57, 0xee, 0x92, 0x80, 0xa3,
+ 0x99, 0xb4, 0xac, 0x98, 0x31, 0xd4, 0xf3, 0xe2, 0x60, 0xd9, 0xb9, 0x8d,
+ 0x20, 0xf7, 0x97, 0x70, 0x10, 0xd6, 0xba, 0x86, 0xb8, 0x9c, 0xb8, 0xf8,
+ 0x49, 0x71, 0x28, 0x9d, 0x05, 0x38, 0x1f, 0x63, 0xba, 0xf7, 0x15, 0x60,
+ 0x96, 0x61, 0x84, 0x68, 0xeb, 0x5d, 0x28, 0x51, 0xe3, 0x51, 0xdd, 0x69,
+ 0x8a, 0xdd, 0xba, 0xec, 0xbd, 0xd3, 0xa1, 0x42, 0x83, 0x59, 0x77, 0x11,
+ 0x12, 0x86, 0x5b, 0x8d, 0x30, 0xcf, 0xdf, 0x6f, 0xea, 0x9d, 0x31, 0xa2,
+ 0x65, 0xa5, 0x61, 0xc0, 0xde, 0x52, 0x6c, 0x72, 0x71, 0x0b, 0x4c, 0x7a,
+ 0x4c, 0x9f, 0x75, 0x74, 0x38, 0xc8, 0xdd, 0x12, 0xba, 0x21, 0x57, 0x1b,
+ 0x45, 0xb3, 0x02, 0x1d, 0x67, 0x22, 0x66, 0x53, 0x18, 0x48, 0xed, 0x60,
+ 0x40, 0x55, 0xd1, 0x25, 0x3b, 0xbc, 0x08, 0x7b, 0x19, 0x8a, 0x30, 0x5b,
+ 0x02, 0x4f, 0x65, 0x42, 0xff, 0xce, 0x87, 0xe8, 0x97, 0x2b, 0xbb, 0xfe,
+ 0x52, 0x52, 0x72, 0xe8, 0xb5, 0x77, 0xb7, 0x8e, 0x94, 0x34, 0xbc, 0x46,
+ 0xf1, 0xe1, 0x94, 0x98, 0x19, 0xbe, 0x7c, 0x3f, 0xf6, 0x0e, 0xe4, 0xbb,
+ 0x88, 0x32, 0x07, 0x83, 0x64, 0xad, 0xd7, 0xd1, 0xe8, 0x35, 0x8d, 0x5d,
+ 0x70, 0x16, 0xc8, 0x11, 0x94, 0x39, 0xc9, 0xac, 0xd6, 0xed, 0x6b, 0xdf,
+ 0xc8, 0xf3, 0x1d, 0x5e, 0x37, 0xd8, 0xb5, 0x86, 0x9b, 0xc2, 0xdc, 0x3c,
+ 0x5c, 0x04, 0x52, 0x5c, 0x11, 0x88, 0x0a, 0x2b, 0x78, 0x48, 0x9e, 0x5e,
+ 0x98, 0x57, 0x5a, 0xd1, 0x77, 0x1c, 0x7d, 0x5f, 0x60, 0xbb, 0x61, 0x7e,
+ 0x7e, 0x2a, 0xaf, 0x44, 0x14, 0x88, 0xfc, 0xa5, 0x31, 0xb7, 0xd4, 0x44,
+ 0x48, 0xda, 0xb5, 0x71, 0xa8, 0xd8, 0x4f, 0x79, 0xcd, 0xe4, 0xbe, 0xb6,
+ 0x1a, 0x61, 0x74, 0x4b, 0xd8, 0xec, 0xd7, 0xbf, 0xad, 0x57, 0x00, 0x42,
+ 0x04, 0xe8, 0xb3, 0xec, 0x47, 0x1d, 0x2a, 0x0a, 0xde, 0x7c, 0x6e, 0x5e,
+ 0xf8, 0xaa, 0x44, 0x05, 0x10, 0xab, 0xe9, 0x4e, 0xd7, 0x44, 0x0b, 0x97,
+ 0x6f, 0x1a, 0xc1, 0x59, 0x2b, 0xe4, 0xe1, 0x8a, 0x13, 0x82, 0x65, 0xd8,
+ 0xae, 0x5f, 0x2b, 0xbc, 0xa6, 0x14, 0x39, 0xaf, 0x38, 0x41, 0x26, 0x74,
+ 0xdb, 0x55, 0x6b, 0xe2, 0x21, 0x80, 0x5d, 0x20, 0xc3, 0xf5, 0x82, 0xee,
+ 0xcc, 0x3c, 0xc9, 0xb4, 0xeb, 0x52, 0xe9, 0x13, 0x8a, 0xea, 0xc6, 0x19,
+ 0x70, 0x37, 0x1b, 0xb8, 0x2e, 0x86, 0xa2, 0xe9, 0x9d, 0xb6, 0xd5, 0xd6,
+ 0xf3, 0xa8, 0x31, 0xf3, 0x02, 0xaa, 0x10, 0x33, 0x3f, 0xba, 0xf8, 0xf9,
+ 0x46, 0x5b, 0xe1, 0xd7, 0x34, 0x9f, 0x94, 0xcb, 0xfb, 0xb1, 0x3d, 0x60,
+ 0x77, 0x85, 0x14, 0xd4, 0xcf, 0x55, 0x60, 0x5d, 0x47, 0x6c, 0x07, 0xb4,
+ 0xc7, 0x73, 0xbd, 0x49, 0xbd, 0xa5, 0x31, 0xa1, 0xfa, 0x34, 0x3a, 0x8b,
+ 0x77, 0x1b, 0xaa, 0xaf, 0xa5, 0x87, 0x12, 0x4e, 0x36, 0x06, 0x14, 0xe7,
+ 0xb3, 0xb8, 0x87, 0x6c, 0x4b, 0x50, 0xc9, 0x52, 0x1b, 0x19, 0x48, 0x69,
+ 0x5b, 0x7f, 0xd8, 0xc9, 0x14, 0xb8, 0x11, 0xa0, 0x51, 0x09, 0xbd, 0x42,
+ 0x5a, 0x50, 0x32, 0x57, 0x69, 0x39, 0x30, 0xdb, 0xbf, 0x8b, 0x93, 0x54,
+ 0x43, 0x80, 0x4e, 0xd0, 0xc6, 0xf2, 0x81, 0x15, 0x6d, 0xef, 0x5a, 0xb6,
+ 0x4d, 0x70, 0x93, 0x88, 0x8d, 0xce, 0x0d, 0xb8, 0xe9, 0xac, 0xa2, 0xcd,
+ 0xc7, 0x18, 0xa5, 0x95, 0xb7, 0xf6, 0x0c, 0x6f, 0xe1, 0x10, 0x7b, 0x22,
+ 0xf8, 0x81, 0x18, 0x42, 0x6a, 0x09, 0x75, 0x20, 0xb4, 0x2f, 0x67, 0x7a,
+ 0xda, 0x55, 0x28, 0xc3, 0x81, 0xf7, 0xc1, 0xf0, 0xe6, 0x1b, 0x29, 0x9c,
+ 0x72, 0x87, 0xe5, 0x4c, 0xa9, 0x5b, 0x5b, 0x62, 0xb5, 0xb7, 0x1e, 0x82,
+ 0xc3, 0x7b, 0xaf, 0xe9, 0x6f, 0x37, 0x31, 0x9f, 0x79, 0xe7, 0x4f, 0x06,
+ 0x1e, 0xff, 0xff, 0x80, 0x8e, 0x00, 0x00
+};
+
+int do_spl_test_load(struct unit_test_state *uts, const char *test_name,
+ enum spl_test_image type, struct spl_image_loader *loader,
+ int (*write_image)(struct unit_test_state *, void *, size_t))
+{
+ size_t img_size, img_data, plain_size = SPL_TEST_DATA_SIZE;
+ struct spl_image_info info_write = {
+ .name = test_name,
+ .size = type == LEGACY_LZMA ? sizeof(lzma_compressed) :
+ plain_size,
+ }, info_read = { };
+ struct spl_boot_device bootdev = {
+ .boot_device = loader->boot_device,
+ };
+ char *data, *plain;
+ void *img;
+
+ img_size = create_image(NULL, type, &info_write, &img_data);
+ ut_assert(img_size);
+ img = calloc(img_size, 1);
+ ut_assertnonnull(img);
+
+ data = img + img_data;
+ if (type == LEGACY_LZMA) {
+ plain = malloc(plain_size);
+ ut_assertnonnull(plain);
+ generate_data(plain, plain_size, "lzma");
+ memcpy(data, lzma_compressed, sizeof(lzma_compressed));
+ } else {
+ plain = data;
+ generate_data(plain, plain_size, test_name);
+ }
+ ut_asserteq(img_size, create_image(img, type, &info_write, NULL));
+
+ if (write_image(uts, img, img_size))
+ return CMD_RET_FAILURE;
+
+ ut_assertok(loader->load_image(&info_read, &bootdev));
+ if (check_image_info(uts, &info_write, &info_read))
+ return CMD_RET_FAILURE;
+ if (type == LEGACY_LZMA)
+ ut_asserteq(plain_size, info_read.size);
+ ut_asserteq_mem(plain, phys_to_virt(info_write.load_addr), plain_size);
+
+ if (type == LEGACY_LZMA)
+ free(plain);
+ free(img);
+ return 0;
+}
diff --git a/test/image/spl_load_fs.c b/test/image/spl_load_fs.c
new file mode 100644
index 0000000..297ab08
--- /dev/null
+++ b/test/image/spl_load_fs.c
@@ -0,0 +1,428 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <common.h>
+#include <blk.h>
+#include <ext_common.h>
+#include <ext4fs.h>
+#include <fat.h>
+#include <fs.h>
+#include <memalign.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <linux/stat.h>
+#include <test/spl.h>
+#include <test/ut.h>
+
+/**
+ * create_ext2() - Create an "ext2" filesystem with a single file
+ * @dst: The location of the new filesystem; MUST be zeroed
+ * @size: The size of the file
+ * @filename: The name of the file
+ * @data_offset: Filled with the offset of the file data from @dst
+ *
+ * Budget mke2fs. We use 1k blocks (to reduce overhead) with a single block
+ * group, which limits us to 8M of data. Almost every feature which increases
+ * complexity (checksums, hash tree directories, etc.) is disabled. We do cheat
+ * a little and use extents from ext4 to save having to deal with indirects, but
+ * U-Boot doesn't care.
+ *
+ * If @dst is %NULL, nothing is copied.
+ *
+ * Return: The size of the filesystem in bytes
+ */
+static size_t create_ext2(void *dst, size_t size, const char *filename,
+ size_t *data_offset)
+{
+ u32 super_block = 1;
+ u32 group_block = 2;
+ u32 block_bitmap_block = 3;
+ u32 inode_bitmap_block = 4;
+ u32 inode_table_block = 5;
+ u32 root_block = 6;
+ u32 file_block = 7;
+
+ u32 root_ino = EXT2_ROOT_INO;
+ u32 file_ino = EXT2_BOOT_LOADER_INO;
+
+ u32 block_size = EXT2_MIN_BLOCK_SIZE;
+ u32 inode_size = sizeof(struct ext2_inode);
+
+ u32 file_blocks = (size + block_size - 1) / block_size;
+ u32 blocks = file_block + file_blocks;
+ u32 inodes = block_size / inode_size;
+ u32 filename_len = strlen(filename);
+ u32 dirent_len = ALIGN(filename_len, sizeof(struct ext2_dirent)) +
+ sizeof(struct ext2_dirent);
+
+ struct ext2_sblock *sblock = dst + super_block * block_size;
+ struct ext2_block_group *bg = dst + group_block * block_size;
+ struct ext2_inode *inode_table = dst + inode_table_block * block_size;
+ struct ext2_inode *root_inode = &inode_table[root_ino - 1];
+ struct ext2_inode *file_inode = &inode_table[file_ino - 1];
+ struct ext4_extent_header *ext_block = (void *)&file_inode->b;
+ struct ext4_extent *extent = (void *)(ext_block + 1);
+ struct ext2_dirent *dot = dst + root_block * block_size;
+ struct ext2_dirent *dotdot = dot + 2;
+ struct ext2_dirent *dirent = dotdot + 2;
+ struct ext2_dirent *last = ((void *)dirent) + dirent_len;
+
+ /* Make sure we fit in one block group */
+ if (blocks > block_size * 8)
+ return 0;
+
+ if (filename_len > EXT2_NAME_LEN)
+ return 0;
+
+ if (data_offset)
+ *data_offset = file_block * block_size;
+
+ if (!dst)
+ goto out;
+
+ sblock->total_inodes = cpu_to_le32(inodes);
+ sblock->total_blocks = cpu_to_le32(blocks);
+ sblock->first_data_block = cpu_to_le32(super_block);
+ sblock->blocks_per_group = cpu_to_le32(blocks);
+ sblock->fragments_per_group = cpu_to_le32(blocks);
+ sblock->inodes_per_group = cpu_to_le32(inodes);
+ sblock->magic = cpu_to_le16(EXT2_MAGIC);
+ /* Done mostly so we can pretend to be (in)compatible */
+ sblock->revision_level = cpu_to_le32(EXT2_DYNAMIC_REV);
+ /* Not really accurate but it doesn't matter */
+ sblock->first_inode = cpu_to_le32(EXT2_GOOD_OLD_FIRST_INO);
+ sblock->inode_size = cpu_to_le32(inode_size);
+ sblock->feature_incompat = cpu_to_le32(EXT4_FEATURE_INCOMPAT_EXTENTS);
+
+ bg->block_id = cpu_to_le32(block_bitmap_block);
+ bg->inode_id = cpu_to_le32(inode_bitmap_block);
+ bg->inode_table_id = cpu_to_le32(inode_table_block);
+
+ /*
+ * All blocks/inodes are in-use. I don't want to have to deal with
+ * endianness, so just fill everything in.
+ */
+ memset(dst + block_bitmap_block * block_size, 0xff, block_size * 2);
+
+ root_inode->mode = cpu_to_le16(S_IFDIR | 0755);
+ root_inode->size = cpu_to_le32(block_size);
+ root_inode->nlinks = cpu_to_le16(3);
+ root_inode->blockcnt = cpu_to_le32(1);
+ root_inode->flags = cpu_to_le32(EXT4_TOPDIR_FL);
+ root_inode->b.blocks.dir_blocks[0] = root_block;
+
+ file_inode->mode = cpu_to_le16(S_IFREG | 0644);
+ file_inode->size = cpu_to_le32(size);
+ file_inode->nlinks = cpu_to_le16(1);
+ file_inode->blockcnt = cpu_to_le32(file_blocks);
+ file_inode->flags = cpu_to_le32(EXT4_EXTENTS_FL);
+ ext_block->eh_magic = cpu_to_le16(EXT4_EXT_MAGIC);
+ ext_block->eh_entries = cpu_to_le16(1);
+ ext_block->eh_max = cpu_to_le16(sizeof(file_inode->b) /
+ sizeof(*ext_block) - 1);
+ extent->ee_len = cpu_to_le16(file_blocks);
+ extent->ee_start_lo = cpu_to_le16(file_block);
+
+ /* I'm not sure we need these, but it can't hurt */
+ dot->inode = cpu_to_le32(root_ino);
+ dot->direntlen = cpu_to_le16(2 * sizeof(*dot));
+ dot->namelen = 1;
+ dot->filetype = FILETYPE_DIRECTORY;
+ memcpy(dot + 1, ".", dot->namelen);
+
+ dotdot->inode = cpu_to_le32(root_ino);
+ dotdot->direntlen = cpu_to_le16(2 * sizeof(*dotdot));
+ dotdot->namelen = 2;
+ dotdot->filetype = FILETYPE_DIRECTORY;
+ memcpy(dotdot + 1, "..", dotdot->namelen);
+
+ dirent->inode = cpu_to_le32(file_ino);
+ dirent->direntlen = cpu_to_le16(dirent_len);
+ dirent->namelen = filename_len;
+ dirent->filetype = FILETYPE_REG;
+ memcpy(dirent + 1, filename, filename_len);
+
+ last->direntlen = block_size - dirent_len;
+
+out:
+ return (size_t)blocks * block_size;
+}
+
+/**
+ * create_fat() - Create a FAT32 filesystem with a single file
+ * @dst: The location of the new filesystem; MUST be zeroed
+ * @size: The size of the file
+ * @filename: The name of the file
+ * @data_offset: Filled with the offset of the file data from @dst
+ *
+ * Budget mkfs.fat. We use FAT32 (so I don't have to deal with FAT12) with no
+ * info sector, and a single one-sector FAT. This limits us to 64k of data
+ * (enough for anyone). The filename must fit in 8.3.
+ *
+ * If @dst is %NULL, nothing is copied.
+ *
+ * Return: The size of the filesystem in bytes
+ */
+static size_t create_fat(void *dst, size_t size, const char *filename,
+ size_t *data_offset)
+{
+ u16 boot_sector = 0;
+ u16 fat_sector = 1;
+ u32 root_sector = 2;
+ u32 file_sector = 3;
+
+ u16 sector_size = 512;
+ u32 file_sectors = (size + sector_size - 1) / sector_size;
+ u32 sectors = file_sector + file_sectors;
+
+ char *ext;
+ size_t filename_len, ext_len;
+ int i;
+
+ struct boot_sector *bs = dst + boot_sector * sector_size;
+ struct volume_info *vi = (void *)(bs + 1);
+ __le32 *fat = dst + fat_sector * sector_size;
+ struct dir_entry *dirent = dst + root_sector * sector_size;
+
+ /* Make sure we fit in the FAT */
+ if (sectors > sector_size / sizeof(u32))
+ return 0;
+
+ ext = strchr(filename, '.');
+ if (ext) {
+ filename_len = ext - filename;
+ ext++;
+ ext_len = strlen(ext);
+ } else {
+ filename_len = strlen(filename);
+ ext_len = 0;
+ }
+
+ if (filename_len > 8 || ext_len > 3)
+ return 0;
+
+ if (data_offset)
+ *data_offset = file_sector * sector_size;
+
+ if (!dst)
+ goto out;
+
+ bs->sector_size[0] = sector_size & 0xff;
+ bs->sector_size[1] = sector_size >> 8;
+ bs->cluster_size = 1;
+ bs->reserved = cpu_to_le16(fat_sector);
+ bs->fats = 1;
+ bs->media = 0xf8;
+ bs->total_sect = cpu_to_le32(sectors);
+ bs->fat32_length = cpu_to_le32(1);
+ bs->root_cluster = cpu_to_le32(root_sector);
+
+ vi->ext_boot_sign = 0x29;
+ memcpy(vi->fs_type, FAT32_SIGN, sizeof(vi->fs_type));
+
+ memcpy(dst + 0x1fe, "\x55\xAA", 2);
+
+ fat[0] = cpu_to_le32(0x0ffffff8);
+ fat[1] = cpu_to_le32(0x0fffffff);
+ fat[2] = cpu_to_le32(0x0ffffff8);
+ for (i = file_sector; file_sectors > 1; file_sectors--, i++)
+ fat[i] = cpu_to_le32(i + 1);
+ fat[i] = cpu_to_le32(0x0ffffff8);
+
+ for (i = 0; i < sizeof(dirent->nameext.name); i++) {
+ if (i < filename_len)
+ dirent->nameext.name[i] = toupper(filename[i]);
+ else
+ dirent->nameext.name[i] = ' ';
+ }
+
+ for (i = 0; i < sizeof(dirent->nameext.ext); i++) {
+ if (i < ext_len)
+ dirent->nameext.ext[i] = toupper(ext[i]);
+ else
+ dirent->nameext.ext[i] = ' ';
+ }
+
+ dirent->start = cpu_to_le16(file_sector);
+ dirent->size = cpu_to_le32(size);
+
+out:
+ return sectors * sector_size;
+}
+
+typedef size_t (*create_fs_t)(void *, size_t, const char *, size_t *);
+
+static int spl_test_fs(struct unit_test_state *uts, const char *test_name,
+ create_fs_t create)
+{
+ const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME;
+ struct blk_desc *dev_desc;
+ char *data_write, *data_read;
+ void *fs;
+ size_t fs_size, fs_data, fs_blocks, data_size = SPL_TEST_DATA_SIZE;
+ loff_t actread;
+
+ fs_size = create(NULL, data_size, filename, &fs_data);
+ ut_assert(fs_size);
+ fs = calloc(fs_size, 1);
+ ut_assertnonnull(fs);
+
+ data_write = fs + fs_data;
+ generate_data(data_write, data_size, test_name);
+ ut_asserteq(fs_size, create(fs, data_size, filename, NULL));
+
+ dev_desc = blk_get_devnum_by_uclass_id(UCLASS_MMC, 0);
+ ut_assertnonnull(dev_desc);
+ ut_asserteq(512, dev_desc->blksz);
+ fs_blocks = fs_size / dev_desc->blksz;
+ ut_asserteq(fs_blocks, blk_dwrite(dev_desc, 0, fs_blocks, fs));
+
+ /* We have to use malloc so we can call virt_to_phys */
+ data_read = malloc_cache_aligned(data_size);
+ ut_assertnonnull(data_read);
+ ut_assertok(fs_set_blk_dev_with_part(dev_desc, 0));
+ ut_assertok(fs_read("/" CONFIG_SPL_FS_LOAD_PAYLOAD_NAME,
+ virt_to_phys(data_read), 0, data_size, &actread));
+ ut_asserteq(data_size, actread);
+ ut_asserteq_mem(data_write, data_read, data_size);
+
+ free(data_read);
+ free(fs);
+ return 0;
+}
+
+static int spl_test_ext(struct unit_test_state *uts)
+{
+ return spl_test_fs(uts, __func__, create_ext2);
+}
+SPL_TEST(spl_test_ext, DM_FLAGS);
+
+static int spl_test_fat(struct unit_test_state *uts)
+{
+ spl_fat_force_reregister();
+ return spl_test_fs(uts, __func__, create_fat);
+}
+SPL_TEST(spl_test_fat, DM_FLAGS);
+
+static bool spl_mmc_raw;
+
+u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
+{
+ return spl_mmc_raw ? MMCSD_MODE_RAW : MMCSD_MODE_FS;
+}
+
+static int spl_test_mmc_fs(struct unit_test_state *uts, const char *test_name,
+ enum spl_test_image type, create_fs_t create_fs,
+ bool blk_mode)
+{
+ const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME;
+ struct blk_desc *dev_desc;
+ size_t fs_size, fs_data, img_size, img_data,
+ data_size = SPL_TEST_DATA_SIZE;
+ struct spl_image_info info_write = {
+ .name = test_name,
+ .size = data_size,
+ }, info_read = { };
+ struct disk_partition part = {
+ .start = 1,
+ .sys_ind = 0x83,
+ };
+ struct spl_image_loader *loader =
+ SPL_LOAD_IMAGE_GET(0, BOOT_DEVICE_MMC1, spl_mmc_load_image);
+ struct spl_boot_device bootdev = {
+ .boot_device = loader->boot_device,
+ };
+ void *fs;
+ char *data;
+
+ img_size = create_image(NULL, type, &info_write, &img_data);
+ ut_assert(img_size);
+ fs_size = create_fs(NULL, img_size, filename, &fs_data);
+ ut_assert(fs_size);
+ fs = calloc(fs_size, 1);
+ ut_assertnonnull(fs);
+
+ data = fs + fs_data + img_data;
+ generate_data(data, data_size, test_name);
+ ut_asserteq(img_size, create_image(fs + fs_data, type, &info_write,
+ NULL));
+ ut_asserteq(fs_size, create_fs(fs, img_size, filename, NULL));
+
+ dev_desc = blk_get_devnum_by_uclass_id(UCLASS_MMC, 0);
+ ut_assertnonnull(dev_desc);
+
+ ut_asserteq(512, dev_desc->blksz);
+ part.size = fs_size / dev_desc->blksz;
+ ut_assertok(write_mbr_partitions(dev_desc, &part, 1, 0));
+ ut_asserteq(part.size, blk_dwrite(dev_desc, part.start, part.size, fs));
+
+ spl_mmc_raw = false;
+ if (blk_mode)
+ ut_assertok(spl_blk_load_image(&info_read, &bootdev, UCLASS_MMC,
+ 0, 1));
+ else
+ ut_assertok(loader->load_image(&info_read, &bootdev));
+ if (check_image_info(uts, &info_write, &info_read))
+ return CMD_RET_FAILURE;
+ ut_asserteq_mem(data, phys_to_virt(info_write.load_addr), data_size);
+
+ free(fs);
+ return 0;
+}
+
+static int spl_test_blk(struct unit_test_state *uts, const char *test_name,
+ enum spl_test_image type)
+{
+ spl_fat_force_reregister();
+ if (spl_test_mmc_fs(uts, test_name, type, create_fat, true))
+ return CMD_RET_FAILURE;
+
+ return spl_test_mmc_fs(uts, test_name, type, create_ext2, true);
+}
+SPL_IMG_TEST(spl_test_blk, LEGACY, DM_FLAGS);
+SPL_IMG_TEST(spl_test_blk, FIT_EXTERNAL, DM_FLAGS);
+SPL_IMG_TEST(spl_test_blk, FIT_INTERNAL, DM_FLAGS);
+
+static int spl_test_mmc_write_image(struct unit_test_state *uts, void *img,
+ size_t img_size)
+{
+ struct blk_desc *dev_desc;
+ size_t img_blocks;
+
+ dev_desc = blk_get_devnum_by_uclass_id(UCLASS_MMC, 0);
+ ut_assertnonnull(dev_desc);
+
+ img_blocks = DIV_ROUND_UP(img_size, dev_desc->blksz);
+ ut_asserteq(img_blocks, blk_dwrite(dev_desc,
+ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
+ img_blocks, img));
+
+ spl_mmc_raw = true;
+ return 0;
+}
+
+static int spl_test_mmc(struct unit_test_state *uts, const char *test_name,
+ enum spl_test_image type)
+{
+ spl_mmc_clear_cache();
+ spl_fat_force_reregister();
+
+ if (type == LEGACY &&
+ spl_test_mmc_fs(uts, test_name, type, create_ext2, false))
+ return CMD_RET_FAILURE;
+
+ if (type != IMX8 &&
+ spl_test_mmc_fs(uts, test_name, type, create_fat, false))
+ return CMD_RET_FAILURE;
+
+ return do_spl_test_load(uts, test_name, type,
+ SPL_LOAD_IMAGE_GET(0, BOOT_DEVICE_MMC1,
+ spl_mmc_load_image),
+ spl_test_mmc_write_image);
+}
+SPL_IMG_TEST(spl_test_mmc, LEGACY, DM_FLAGS);
+SPL_IMG_TEST(spl_test_mmc, IMX8, DM_FLAGS);
+SPL_IMG_TEST(spl_test_mmc, FIT_EXTERNAL, DM_FLAGS);
+SPL_IMG_TEST(spl_test_mmc, FIT_INTERNAL, DM_FLAGS);
diff --git a/test/image/spl_load_net.c b/test/image/spl_load_net.c
new file mode 100644
index 0000000..f570cef
--- /dev/null
+++ b/test/image/spl_load_net.c
@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spl.h>
+#include <test/spl.h>
+#include <asm/eth.h>
+#include <test/ut.h>
+#include "../../net/bootp.h"
+
+/*
+ * sandbox_eth_bootp_req_to_reply()
+ *
+ * Check if a BOOTP request was sent. If so, inject a reply
+ *
+ * returns 0 if injected, -EAGAIN if not
+ */
+static int sandbox_eth_bootp_req_to_reply(struct udevice *dev, void *packet,
+ unsigned int len)
+{
+ struct eth_sandbox_priv *priv = dev_get_priv(dev);
+ struct ethernet_hdr *eth = packet;
+ struct ip_udp_hdr *ip;
+ struct bootp_hdr *bp;
+ struct ethernet_hdr *eth_recv;
+ struct ip_udp_hdr *ipr;
+ struct bootp_hdr *bpr;
+
+ if (ntohs(eth->et_protlen) != PROT_IP)
+ return -EAGAIN;
+
+ ip = packet + ETHER_HDR_SIZE;
+ if (ip->ip_p != IPPROTO_UDP)
+ return -EAGAIN;
+
+ if (ntohs(ip->udp_dst) != PORT_BOOTPS)
+ return -EAGAIN;
+
+ bp = (void *)ip + IP_UDP_HDR_SIZE;
+ if (bp->bp_op != OP_BOOTREQUEST)
+ return -EAGAIN;
+
+ /* Don't allow the buffer to overrun */
+ if (priv->recv_packets >= PKTBUFSRX)
+ return 0;
+
+ /* reply to the request */
+ eth_recv = (void *)priv->recv_packet_buffer[priv->recv_packets];
+ memcpy(eth_recv, packet, len);
+ ipr = (void *)eth_recv + ETHER_HDR_SIZE;
+ bpr = (void *)ipr + IP_UDP_HDR_SIZE;
+ memcpy(eth_recv->et_dest, eth->et_src, ARP_HLEN);
+ memcpy(eth_recv->et_src, priv->fake_host_hwaddr, ARP_HLEN);
+ ipr->ip_sum = 0;
+ ipr->ip_off = 0;
+ net_write_ip(&ipr->ip_dst, net_ip);
+ net_write_ip(&ipr->ip_src, priv->fake_host_ipaddr);
+ ipr->ip_sum = compute_ip_checksum(ipr, IP_HDR_SIZE);
+ ipr->udp_src = ip->udp_dst;
+ ipr->udp_dst = ip->udp_src;
+
+ bpr->bp_op = OP_BOOTREPLY;
+ net_write_ip(&bpr->bp_yiaddr, net_ip);
+ net_write_ip(&bpr->bp_siaddr, priv->fake_host_ipaddr);
+ copy_filename(bpr->bp_file, CONFIG_BOOTFILE, sizeof(CONFIG_BOOTFILE));
+ memset(&bpr->bp_vend, 0, sizeof(bpr->bp_vend));
+
+ priv->recv_packet_length[priv->recv_packets] = len;
+ ++priv->recv_packets;
+
+ return 0;
+}
+
+struct spl_test_net_priv {
+ struct unit_test_state *uts;
+ void *img;
+ size_t img_size;
+ u16 port;
+};
+
+/* Well known TFTP port # */
+#define TFTP_PORT 69
+/* Transaction ID, chosen at random */
+#define TFTP_TID 21313
+
+/*
+ * TFTP operations.
+ */
+#define TFTP_RRQ 1
+#define TFTP_DATA 3
+#define TFTP_ACK 4
+
+/* default TFTP block size */
+#define TFTP_BLOCK_SIZE 512
+
+struct tftp_hdr {
+ u16 opcode;
+ u16 block;
+};
+
+#define TFTP_HDR_SIZE sizeof(struct tftp_hdr)
+
+/*
+ * sandbox_eth_tftp_req_to_reply()
+ *
+ * Check if a TFTP request was sent. If so, inject a reply. We don't support
+ * options, and we don't check for rollover, so we are limited files of less
+ * than 32M.
+ *
+ * returns 0 if injected, -EAGAIN if not
+ */
+static int sandbox_eth_tftp_req_to_reply(struct udevice *dev, void *packet,
+ unsigned int len)
+{
+ struct eth_sandbox_priv *priv = dev_get_priv(dev);
+ struct spl_test_net_priv *test_priv = priv->priv;
+ struct ethernet_hdr *eth = packet;
+ struct ip_udp_hdr *ip;
+ struct tftp_hdr *tftp;
+ struct ethernet_hdr *eth_recv;
+ struct ip_udp_hdr *ipr;
+ struct tftp_hdr *tftpr;
+ size_t size;
+ u16 block;
+
+ if (ntohs(eth->et_protlen) != PROT_IP)
+ return -EAGAIN;
+
+ ip = packet + ETHER_HDR_SIZE;
+ if (ip->ip_p != IPPROTO_UDP)
+ return -EAGAIN;
+
+ if (ntohs(ip->udp_dst) == TFTP_PORT) {
+ tftp = (void *)ip + IP_UDP_HDR_SIZE;
+ if (htons(tftp->opcode) != TFTP_RRQ)
+ return -EAGAIN;
+
+ block = 0;
+ } else if (ntohs(ip->udp_dst) == TFTP_TID) {
+ tftp = (void *)ip + IP_UDP_HDR_SIZE;
+ if (htons(tftp->opcode) != TFTP_ACK)
+ return -EAGAIN;
+
+ block = htons(tftp->block);
+ } else {
+ return -EAGAIN;
+ }
+
+ if (block * TFTP_BLOCK_SIZE > test_priv->img_size)
+ return 0;
+
+ size = min(test_priv->img_size - block * TFTP_BLOCK_SIZE,
+ (size_t)TFTP_BLOCK_SIZE);
+
+ /* Don't allow the buffer to overrun */
+ if (priv->recv_packets >= PKTBUFSRX)
+ return 0;
+
+ /* reply to the request */
+ eth_recv = (void *)priv->recv_packet_buffer[priv->recv_packets];
+ memcpy(eth_recv->et_dest, eth->et_src, ARP_HLEN);
+ memcpy(eth_recv->et_src, priv->fake_host_hwaddr, ARP_HLEN);
+ eth_recv->et_protlen = htons(PROT_IP);
+
+ ipr = (void *)eth_recv + ETHER_HDR_SIZE;
+ ipr->ip_hl_v = 0x45;
+ ipr->ip_len = htons(IP_UDP_HDR_SIZE + TFTP_HDR_SIZE + size);
+ ipr->ip_off = htons(IP_FLAGS_DFRAG);
+ ipr->ip_ttl = 255;
+ ipr->ip_p = IPPROTO_UDP;
+ ipr->ip_sum = 0;
+ net_copy_ip(&ipr->ip_dst, &ip->ip_src);
+ net_copy_ip(&ipr->ip_src, &ip->ip_dst);
+ ipr->ip_sum = compute_ip_checksum(ipr, IP_HDR_SIZE);
+
+ ipr->udp_src = htons(TFTP_TID);
+ ipr->udp_dst = ip->udp_src;
+ ipr->udp_len = htons(UDP_HDR_SIZE + TFTP_HDR_SIZE + size);
+ ipr->udp_xsum = 0;
+
+ tftpr = (void *)ipr + IP_UDP_HDR_SIZE;
+ tftpr->opcode = htons(TFTP_DATA);
+ tftpr->block = htons(block + 1);
+ memcpy((void *)tftpr + TFTP_HDR_SIZE,
+ test_priv->img + block * TFTP_BLOCK_SIZE, size);
+
+ priv->recv_packet_length[priv->recv_packets] =
+ ETHER_HDR_SIZE + IP_UDP_HDR_SIZE + TFTP_HDR_SIZE + size;
+ ++priv->recv_packets;
+
+ return 0;
+}
+
+static int spl_net_handler(struct udevice *dev, void *packet,
+ unsigned int len)
+{
+ struct eth_sandbox_priv *priv = dev_get_priv(dev);
+ int old_packets = priv->recv_packets;
+
+ priv->fake_host_ipaddr = string_to_ip("1.1.2.4");
+ net_ip = string_to_ip("1.1.2.2");
+
+ sandbox_eth_arp_req_to_reply(dev, packet, len);
+ sandbox_eth_bootp_req_to_reply(dev, packet, len);
+ sandbox_eth_tftp_req_to_reply(dev, packet, len);
+
+ if (old_packets == priv->recv_packets)
+ return 0;
+
+ return 0;
+}
+
+static int spl_test_net_write_image(struct unit_test_state *uts, void *img,
+ size_t img_size)
+{
+ struct spl_test_net_priv *test_priv = malloc(sizeof(*test_priv));
+
+ ut_assertnonnull(test_priv);
+ test_priv->uts = uts;
+ test_priv->img = img;
+ test_priv->img_size = img_size;
+
+ sandbox_eth_set_tx_handler(0, spl_net_handler);
+ sandbox_eth_set_priv(0, test_priv);
+ return 0;
+}
+
+static int spl_test_net(struct unit_test_state *uts, const char *test_name,
+ enum spl_test_image type)
+{
+ struct eth_sandbox_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ net_server_ip = string_to_ip("1.1.2.4");
+ ret = do_spl_test_load(uts, test_name, type,
+ SPL_LOAD_IMAGE_GET(0, BOOT_DEVICE_CPGMAC,
+ spl_net_load_image_cpgmac),
+ spl_test_net_write_image);
+
+ sandbox_eth_set_tx_handler(0, NULL);
+ ut_assertok(uclass_get_device(UCLASS_ETH, 0, &dev));
+ priv = dev_get_priv(dev);
+ free(priv->priv);
+ return ret;
+}
+SPL_IMG_TEST(spl_test_net, LEGACY, DM_FLAGS);
+SPL_IMG_TEST(spl_test_net, FIT_INTERNAL, DM_FLAGS);
+SPL_IMG_TEST(spl_test_net, FIT_EXTERNAL, DM_FLAGS);
diff --git a/test/image/spl_load_nor.c b/test/image/spl_load_nor.c
new file mode 100644
index 0000000..a62bb60
--- /dev/null
+++ b/test/image/spl_load_nor.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <test/spl.h>
+#include <test/ut.h>
+
+static void *spl_test_nor_base;
+
+unsigned long spl_nor_get_uboot_base(void)
+{
+ return virt_to_phys(spl_test_nor_base);
+}
+
+static int spl_test_nor_write_image(struct unit_test_state *uts, void *img,
+ size_t img_size)
+{
+ spl_test_nor_base = img;
+ return 0;
+}
+
+static int spl_test_nor(struct unit_test_state *uts, const char *test_name,
+ enum spl_test_image type)
+{
+ return do_spl_test_load(uts, test_name, type,
+ SPL_LOAD_IMAGE_GET(0, BOOT_DEVICE_NOR,
+ spl_nor_load_image),
+ spl_test_nor_write_image);
+}
+SPL_IMG_TEST(spl_test_nor, LEGACY, 0);
+SPL_IMG_TEST(spl_test_nor, LEGACY_LZMA, 0);
+SPL_IMG_TEST(spl_test_nor, IMX8, 0);
+SPL_IMG_TEST(spl_test_nor, FIT_INTERNAL, 0);
+SPL_IMG_TEST(spl_test_nor, FIT_EXTERNAL, 0);
diff --git a/test/image/spl_load_os.c b/test/image/spl_load_os.c
new file mode 100644
index 0000000..49edf15
--- /dev/null
+++ b/test/image/spl_load_os.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <image.h>
+#include <os.h>
+#include <spl.h>
+#include <test/spl.h>
+#include <test/ut.h>
+
+/* Context used for this test */
+struct text_ctx {
+ int fd;
+};
+
+static ulong read_fit_image(struct spl_load_info *load, ulong sector,
+ ulong count, void *buf)
+{
+ struct text_ctx *text_ctx = load->priv;
+ off_t offset, ret;
+ ssize_t res;
+
+ offset = sector * load->bl_len;
+ ret = os_lseek(text_ctx->fd, offset, OS_SEEK_SET);
+ if (ret != offset) {
+ printf("Failed to seek to %zx, got %zx (errno=%d)\n", offset,
+ ret, errno);
+ return 0;
+ }
+
+ res = os_read(text_ctx->fd, buf, count * load->bl_len);
+ if (res == -1) {
+ printf("Failed to read %lx bytes, got %ld (errno=%d)\n",
+ count * load->bl_len, res, errno);
+ return 0;
+ }
+
+ return count;
+}
+
+static int spl_test_load(struct unit_test_state *uts)
+{
+ struct spl_image_info image;
+ struct legacy_img_hdr *header;
+ struct text_ctx text_ctx;
+ struct spl_load_info load;
+ char fname[256];
+ int ret;
+ int fd;
+
+ memset(&load, '\0', sizeof(load));
+ load.bl_len = 512;
+ load.read = read_fit_image;
+
+ ret = sandbox_find_next_phase(fname, sizeof(fname), true);
+ if (ret)
+ ut_assertf(0, "%s not found, error %d\n", fname, ret);
+ load.filename = fname;
+
+ header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
+
+ fd = os_open(fname, OS_O_RDONLY);
+ ut_assert(fd >= 0);
+ ut_asserteq(512, os_read(fd, header, 512));
+ text_ctx.fd = fd;
+
+ load.priv = &text_ctx;
+
+ ut_assertok(spl_load_simple_fit(&image, &load, 0, header));
+
+ return 0;
+}
+SPL_TEST(spl_test_load, 0);
diff --git a/test/image/spl_load_spi.c b/test/image/spl_load_spi.c
new file mode 100644
index 0000000..8f9b6e0
--- /dev/null
+++ b/test/image/spl_load_spi.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spi_flash.h>
+#include <spl.h>
+#include <test/spl.h>
+#include <test/ut.h>
+
+static int spl_test_spi_write_image(struct unit_test_state *uts, void *img,
+ size_t img_size)
+{
+ struct spi_flash *flash;
+
+ flash = spi_flash_probe(spl_spi_boot_bus(), spl_spi_boot_cs(),
+ CONFIG_SF_DEFAULT_SPEED,
+ CONFIG_SF_DEFAULT_MODE);
+ ut_assertnonnull(flash);
+ ut_assertok(spi_flash_write(flash, spl_spi_get_uboot_offs(flash),
+ img_size, img));
+
+ return 0;
+}
+
+static int spl_test_spi(struct unit_test_state *uts, const char *test_name,
+ enum spl_test_image type)
+{
+ return do_spl_test_load(uts, test_name, type,
+ SPL_LOAD_IMAGE_GET(1, BOOT_DEVICE_SPI,
+ spl_spi_load_image),
+ spl_test_spi_write_image);
+}
+SPL_IMG_TEST(spl_test_spi, LEGACY, DM_FLAGS);
+SPL_IMG_TEST(spl_test_spi, IMX8, DM_FLAGS);
+SPL_IMG_TEST(spl_test_spi, FIT_INTERNAL, DM_FLAGS);
+#if !IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)
+SPL_IMG_TEST(spl_test_spi, FIT_EXTERNAL, DM_FLAGS);
+#endif
diff --git a/test/lib/abuf.c b/test/lib/abuf.c
index 42ee4c1..42803b2 100644
--- a/test/lib/abuf.c
+++ b/test/lib/abuf.c
@@ -155,6 +155,31 @@
}
LIB_TEST(lib_test_abuf_realloc_size, 0);
+/* Test abuf_realloc_inc() */
+static int lib_test_abuf_realloc_inc(struct unit_test_state *uts)
+{
+ struct abuf buf;
+ ulong start;
+
+ start = ut_check_free();
+
+ abuf_init(&buf);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ abuf_realloc_inc(&buf, 20);
+ ut_asserteq(20, buf.size);
+ ut_asserteq(true, buf.alloced);
+
+ abuf_uninit(&buf);
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_realloc_inc, 0);
+
/* Test handling of buffers that are too large */
static int lib_test_abuf_large(struct unit_test_state *uts)
{
diff --git a/test/lib/asn1.c b/test/lib/asn1.c
index 8661fdd..a66cdd7 100644
--- a/test/lib/asn1.c
+++ b/test/lib/asn1.c
@@ -120,7 +120,7 @@
cert = x509_cert_parse(cert_data, cert_data_len);
- ut_assertf(cert != NULL, "decoding failed\n");
+ ut_assertf(!IS_ERR(cert), "decoding failed\n");
ut_assertf(!strcmp(cert->subject, "Linaro: Tester"),
"subject doesn't match\n");
ut_assertf(!strcmp(cert->issuer, "Linaro: Tester"),
@@ -313,7 +313,7 @@
pkcs7 = pkcs7_parse_message(image_pk7, image_pk7_len);
- ut_assertf(pkcs7 != NULL, "decoding failed\n");
+ ut_assertf(!IS_ERR(pkcs7), "decoding failed\n");
ut_assertf(pkcs7->data_len == 104, "signature size doesn't match\n");
ut_assertf(pkcs7->signed_infos != NULL, "sign-info doesn't exist\n");
ut_assertf(pkcs7->signed_infos->msgdigest_len == 32,
diff --git a/test/lib/kconfig.c b/test/lib/kconfig.c
index 76225ba..3914f69 100644
--- a/test/lib/kconfig.c
+++ b/test/lib/kconfig.c
@@ -22,9 +22,9 @@
ut_asserteq(0, CONFIG_IS_ENABLED(OF_PLATDATA));
ut_asserteq(0, CONFIG_IS_ENABLED(_UNDEFINED));
- ut_asserteq(0xc000,
+ ut_asserteq(0xb000,
IF_ENABLED_INT(CONFIG_BLOBLIST_FIXED, CONFIG_BLOBLIST_ADDR));
- ut_asserteq(0xc000,
+ ut_asserteq(0xb000,
CONFIG_IF_ENABLED_INT(BLOBLIST_FIXED, BLOBLIST_ADDR));
/*
diff --git a/test/lib/lmb.c b/test/lib/lmb.c
index 1628875..15c68ce 100644
--- a/test/lib/lmb.c
+++ b/test/lib/lmb.c
@@ -451,12 +451,23 @@
ut_asserteq(ret, 0);
ASSERT_LMB(&lmb, ram, ram_size, 2, 0x40010000, 0x10000,
0x40030000, 0x10000, 0, 0);
- /* allocate 2nd region */
+ /* allocate 2nd region , This should coalesced all region into one */
ret = lmb_reserve(&lmb, 0x40020000, 0x10000);
ut_assert(ret >= 0);
ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x30000,
0, 0, 0, 0);
+ /* allocate 2nd region, which should be added as first region */
+ ret = lmb_reserve(&lmb, 0x40000000, 0x8000);
+ ut_assert(ret >= 0);
+ ASSERT_LMB(&lmb, ram, ram_size, 2, 0x40000000, 0x8000,
+ 0x40010000, 0x30000, 0, 0);
+
+ /* allocate 3rd region, coalesce with first and overlap with second */
+ ret = lmb_reserve(&lmb, 0x40008000, 0x10000);
+ ut_assert(ret >= 0);
+ ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40000000, 0x40000,
+ 0, 0, 0, 0);
return 0;
}
diff --git a/test/lib/strlcat.c b/test/lib/strlcat.c
index a0ec037..d8453fe 100644
--- a/test/lib/strlcat.c
+++ b/test/lib/strlcat.c
@@ -43,11 +43,11 @@
s2[i] = 32 + 23 * i % (127 - 32);
s2[len2 - 1] = '\0';
- expected = len2 < n ? min(len1 + len2 - 1, n) : n;
+ expected = min(strlen(s2), n) + strlen(s1);
actual = strlcat(s2, s1, n);
if (expected != actual) {
ut_failf(uts, __FILE__, line, __func__,
- "strlcat(s2, s1, 2) == len2 < n ? min(len1 + len2, n) : n",
+ "strlcat(s2, s1, n) == min(len2, n) + len1",
"Expected %#zx (%zd), got %#zx (%zd)",
expected, expected, actual, actual);
return CMD_RET_FAILURE;
diff --git a/test/print_ut.c b/test/print_ut.c
index 47a6ce5..b26f628 100644
--- a/test/print_ut.c
+++ b/test/print_ut.c
@@ -283,16 +283,21 @@
/* bytes */
console_record_reset();
print_hex_dump_bytes("", DUMP_PREFIX_ADDRESS, buf, 0x12);
- ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........");
- ut_assert_nextline("00000010: 10 00 ..");
+ ut_assert_nextline("%0*lx: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........",
+ IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x0UL);
+ ut_assert_nextline("%0*lx: 10 00 ..",
+ IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x10UL);
ut_assert_console_end();
/* line length */
console_record_reset();
print_hex_dump("", DUMP_PREFIX_ADDRESS, 8, 1, buf, 0x12, true);
- ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 ..\"3DUfw");
- ut_assert_nextline("00000008: 88 99 aa bb cc dd ee ff ........");
- ut_assert_nextline("00000010: 10 00 ..");
+ ut_assert_nextline("%0*lx: 00 11 22 33 44 55 66 77 ..\"3DUfw",
+ IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x0UL);
+ ut_assert_nextline("%0*lx: 88 99 aa bb cc dd ee ff ........",
+ IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x8UL);
+ ut_assert_nextline("%0*lx: 10 00 ..",
+ IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x10UL);
ut_assert_console_end();
unmap_sysmem(buf);
@@ -300,31 +305,39 @@
console_record_reset();
buf[0x41] = 0x41;
print_hex_dump("", DUMP_PREFIX_ADDRESS, 0x40, 1, buf, 0x42, true);
- ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ..\"3DUfw........................................................");
- ut_assert_nextline("00000040: 00 41 .A");
+ ut_assert_nextline("%0*lx: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ..\"3DUfw........................................................",
+ IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x0UL);
+ ut_assert_nextline("%0*lx: 00 41 .A",
+ IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x40UL);
ut_assert_console_end();
/* 16-bit */
console_record_reset();
print_hex_dump("", DUMP_PREFIX_ADDRESS, 0, 2, buf, 0x12, true);
- ut_assert_nextline("00000000: 1100 3322 5544 7766 9988 bbaa ddcc ffee ..\"3DUfw........");
- ut_assert_nextline("00000010: 0010 ..");
+ ut_assert_nextline("%0*lx: 1100 3322 5544 7766 9988 bbaa ddcc ffee ..\"3DUfw........",
+ IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x0UL);
+ ut_assert_nextline("%0*lx: 0010 ..",
+ IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x10UL);
ut_assert_console_end();
unmap_sysmem(buf);
/* 32-bit */
console_record_reset();
print_hex_dump("", DUMP_PREFIX_ADDRESS, 0, 4, buf, 0x14, true);
- ut_assert_nextline("00000000: 33221100 77665544 bbaa9988 ffeeddcc ..\"3DUfw........");
- ut_assert_nextline("00000010: 00000010 ....");
+ ut_assert_nextline("%0*lx: 33221100 77665544 bbaa9988 ffeeddcc ..\"3DUfw........",
+ IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x0UL);
+ ut_assert_nextline("%0*lx: 00000010 ....",
+ IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x10UL);
ut_assert_console_end();
unmap_sysmem(buf);
/* 64-bit */
console_record_reset();
print_hex_dump("", DUMP_PREFIX_ADDRESS, 16, 8, buf, 0x18, true);
- ut_assert_nextline("00000000: 7766554433221100 ffeeddccbbaa9988 ..\"3DUfw........");
- ut_assert_nextline("00000010: 0000000000000010 ........");
+ ut_assert_nextline("%0*lx: 7766554433221100 ffeeddccbbaa9988 ..\"3DUfw........",
+ IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x0UL);
+ ut_assert_nextline("%0*lx: 0000000000000010 ........",
+ IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x10UL);
ut_assert_console_end();
unmap_sysmem(buf);
@@ -337,7 +350,8 @@
buf[4 + i] = 126 + i;
buf[8] = 255;
print_hex_dump("", DUMP_PREFIX_ADDRESS, 0, 1, buf, 10, true);
- ut_assert_nextline("00000000: 00 1f 20 21 7e 7f 80 81 ff 99 .. !~.....");
+ ut_assert_nextline("%0*lx: 00 1f 20 21 7e 7f 80 81 ff 99 .. !~.....",
+ IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x0UL);
ut_assert_console_end();
unmap_sysmem(buf);
diff --git a/test/py/tests/fs_helper.py b/test/py/tests/fs_helper.py
index 17151bc..9882ddb 100644
--- a/test/py/tests/fs_helper.py
+++ b/test/py/tests/fs_helper.py
@@ -9,7 +9,7 @@
import os
from subprocess import call, check_call, check_output, CalledProcessError
-def mk_fs(config, fs_type, size, prefix, use_src_dir=False):
+def mk_fs(config, fs_type, size, prefix):
"""Create a file system volume
Args:
@@ -17,14 +17,12 @@
fs_type (str): File system type, e.g. 'ext4'
size (int): Size of file system in bytes
prefix (str): Prefix string of volume's file name
- use_src_dir (bool): true to put the file in the source directory
Raises:
CalledProcessError: if any error occurs when creating the filesystem
"""
fs_img = f'{prefix}.{fs_type}.img'
- fs_img = os.path.join(config.source_dir if use_src_dir
- else config.persistent_data_dir, fs_img)
+ fs_img = os.path.join(config.persistent_data_dir, fs_img)
if fs_type == 'fat16':
mkfs_opt = '-F 16'
diff --git a/test/py/tests/test_efi_capsule/capsule_gen_binman.dts b/test/py/tests/test_efi_capsule/capsule_gen_binman.dts
new file mode 100644
index 0000000..e8a1858
--- /dev/null
+++ b/test/py/tests/test_efi_capsule/capsule_gen_binman.dts
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Devicetree for capsule generation through binman
+ */
+
+/dts-v1/;
+
+#include <sandbox_efi_capsule.h>
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+&binman {
+ itb {
+ filename = UBOOT_FIT_IMAGE;
+
+ fit {
+ description = "Automatic U-Boot environment update";
+ #address-cells = <2>;
+
+ images {
+ u-boot-bin {
+ description = "U-Boot binary on SPI Flash";
+ compression = "none";
+ type = "firmware";
+ arch = "sandbox";
+ load = <0>;
+ text {
+ text = "u-boot:New";
+ };
+
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+ u-boot-env {
+ description = "U-Boot environment on SPI Flash";
+ compression = "none";
+ type = "firmware";
+ arch = "sandbox";
+ load = <0>;
+ text {
+ text = "u-boot-env:New";
+ };
+
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+ };
+ };
+ };
+
+ capsule1 {
+ filename = "Test01";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule2 {
+ filename = "Test02";
+ efi-capsule {
+ image-index = <0x2>;
+ image-guid = SANDBOX_UBOOT_ENV_IMAGE_GUID;
+
+ text {
+ text = "u-boot-env:New";
+ };
+ };
+ };
+
+ capsule3 {
+ filename = "Test03";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = SANDBOX_INCORRECT_GUID;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule4 {
+ filename = "Test04";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = SANDBOX_FIT_IMAGE_GUID;
+
+ blob {
+ filename = UBOOT_FIT_IMAGE;
+ };
+ };
+ };
+
+ capsule5 {
+ filename = "Test05";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = SANDBOX_INCORRECT_GUID;
+
+ blob {
+ filename = UBOOT_FIT_IMAGE;
+ };
+ };
+ };
+
+ capsule6 {
+ filename = "Test101";
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x5>;
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule7 {
+ filename = "Test102";
+ efi-capsule {
+ image-index = <0x2>;
+ fw-version = <0xa>;
+ image-guid = SANDBOX_UBOOT_ENV_IMAGE_GUID;
+
+ text {
+ text = "u-boot-env:New";
+ };
+ };
+ };
+
+ capsule8 {
+ filename = "Test103";
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x2>;
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule9 {
+ filename = "Test104";
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x5>;
+ image-guid = SANDBOX_FIT_IMAGE_GUID;
+
+ blob {
+ filename = UBOOT_FIT_IMAGE;
+ };
+ };
+ };
+
+ capsule10 {
+ filename = "Test105";
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x2>;
+ image-guid = SANDBOX_FIT_IMAGE_GUID;
+
+ blob {
+ filename = UBOOT_FIT_IMAGE;
+ };
+ };
+ };
+
+ capsule11 {
+ filename = "Test11";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+ private-key = CAPSULE_PRIV_KEY;
+ public-key-cert = CAPSULE_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule12 {
+ filename = "Test12";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+ private-key = CAPSULE_INVAL_KEY;
+ public-key-cert = CAPSULE_INVAL_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule13 {
+ filename = "Test13";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = SANDBOX_FIT_IMAGE_GUID;
+ private-key = CAPSULE_PRIV_KEY;
+ public-key-cert = CAPSULE_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = UBOOT_FIT_IMAGE;
+ };
+ };
+ };
+
+ capsule14 {
+ filename = "Test14";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = SANDBOX_FIT_IMAGE_GUID;
+ private-key = CAPSULE_INVAL_KEY;
+ public-key-cert = CAPSULE_INVAL_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = UBOOT_FIT_IMAGE;
+ };
+ };
+ };
+
+ capsule15 {
+ filename = "Test111";
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x5>;
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+ private-key = CAPSULE_PRIV_KEY;
+ public-key-cert = CAPSULE_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule16 {
+ filename = "Test112";
+ efi-capsule {
+ image-index = <0x2>;
+ fw-version = <0xa>;
+ image-guid = SANDBOX_UBOOT_ENV_IMAGE_GUID;
+ private-key = CAPSULE_PRIV_KEY;
+ public-key-cert = CAPSULE_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ text {
+ text = "u-boot-env:New";
+ };
+ };
+ };
+
+ capsule17 {
+ filename = "Test113";
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x2>;
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+ private-key = CAPSULE_PRIV_KEY;
+ public-key-cert = CAPSULE_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule18 {
+ filename = "Test114";
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x5>;
+ image-guid = SANDBOX_FIT_IMAGE_GUID;
+ private-key = CAPSULE_PRIV_KEY;
+ public-key-cert = CAPSULE_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = UBOOT_FIT_IMAGE;
+ };
+ };
+ };
+
+ capsule19 {
+ filename = "Test115";
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x2>;
+ image-guid = SANDBOX_FIT_IMAGE_GUID;
+ private-key = CAPSULE_PRIV_KEY;
+ public-key-cert = CAPSULE_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = UBOOT_FIT_IMAGE;
+ };
+ };
+ };
+};
diff --git a/test/py/tests/test_efi_capsule/conftest.py b/test/py/tests/test_efi_capsule/conftest.py
index 054be1e..dd41da9 100644
--- a/test/py/tests/test_efi_capsule/conftest.py
+++ b/test/py/tests/test_efi_capsule/conftest.py
@@ -4,6 +4,8 @@
"""Fixture for UEFI capsule test."""
+import os
+
from subprocess import call, check_call, CalledProcessError
import pytest
from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR, EFITOOLS_PATH
@@ -34,40 +36,31 @@
capsule_auth_enabled = u_boot_config.buildconfig.get(
'config_efi_capsule_authenticate')
+ key_dir = u_boot_config.source_dir + '/board/sandbox'
if capsule_auth_enabled:
- # Create private key (SIGNER.key) and certificate (SIGNER.crt)
- check_call('cd %s; '
- 'openssl req -x509 -sha256 -newkey rsa:2048 '
- '-subj /CN=TEST_SIGNER/ -keyout SIGNER.key '
- '-out SIGNER.crt -nodes -days 365'
- % data_dir, shell=True)
- check_call('cd %s; %scert-to-efi-sig-list SIGNER.crt SIGNER.esl'
- % (data_dir, EFITOOLS_PATH), shell=True)
+ # Get the keys from the board directory
+ check_call('cp %s/capsule_priv_key_good.key %s/SIGNER.key'
+ % (key_dir, data_dir), shell=True)
+ check_call('cp %s/capsule_pub_key_good.crt %s/SIGNER.crt'
+ % (key_dir, data_dir), shell=True)
+ check_call('cp %s/capsule_pub_esl_good.esl %s/SIGNER.esl'
+ % (key_dir, data_dir), shell=True)
- # Update dtb adding capsule certificate
- check_call('cd %s; '
- 'cp %s/test/py/tests/test_efi_capsule/signature.dts .'
- % (data_dir, u_boot_config.source_dir), shell=True)
- check_call('cd %s; '
- 'dtc -@ -I dts -O dtb -o signature.dtbo signature.dts; '
- 'fdtoverlay -i %s/arch/sandbox/dts/test.dtb '
- '-o test_sig.dtb signature.dtbo'
- % (data_dir, u_boot_config.build_dir), shell=True)
-
- # Create *malicious* private key (SIGNER2.key) and certificate
- # (SIGNER2.crt)
- check_call('cd %s; '
- 'openssl req -x509 -sha256 -newkey rsa:2048 '
- '-subj /CN=TEST_SIGNER/ -keyout SIGNER2.key '
- '-out SIGNER2.crt -nodes -days 365'
- % data_dir, shell=True)
+ check_call('cp %s/capsule_priv_key_bad.key %s/SIGNER2.key'
+ % (key_dir, data_dir), shell=True)
+ check_call('cp %s/capsule_pub_key_bad.crt %s/SIGNER2.crt'
+ % (key_dir, data_dir), shell=True)
# Update dtb to add the version information
check_call('cd %s; '
'cp %s/test/py/tests/test_efi_capsule/version.dts .'
% (data_dir, u_boot_config.source_dir), shell=True)
+
if capsule_auth_enabled:
check_call('cd %s; '
+ 'cp %s/arch/sandbox/dts/test.dtb test_sig.dtb'
+ % (data_dir, u_boot_config.build_dir), shell=True)
+ check_call('cd %s; '
'dtc -@ -I dts -O dtb -o version.dtbo version.dts; '
'fdtoverlay -i test_sig.dtb '
'-o test_ver.dtb version.dtbo'
@@ -79,132 +72,20 @@
'-o test_ver.dtb version.dtbo'
% (data_dir, u_boot_config.build_dir), shell=True)
- # Create capsule files
# two regions: one for u-boot.bin and the other for u-boot.env
check_call('cd %s; echo -n u-boot:Old > u-boot.bin.old; echo -n u-boot:New > u-boot.bin.new; echo -n u-boot-env:Old > u-boot.env.old; echo -n u-boot-env:New > u-boot.env.new' % data_dir,
shell=True)
- check_call('sed -e \"s?BINFILE1?u-boot.bin.new?\" -e \"s?BINFILE2?u-boot.env.new?\" %s/test/py/tests/test_efi_capsule/uboot_bin_env.its > %s/uboot_bin_env.its' %
- (u_boot_config.source_dir, data_dir),
- shell=True)
- check_call('cd %s; %s/tools/mkimage -f uboot_bin_env.its uboot_bin_env.itb' %
- (data_dir, u_boot_config.build_dir),
- shell=True)
- check_call('cd %s; %s/tools/mkeficapsule --index 1 --guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 u-boot.bin.new Test01' %
- (data_dir, u_boot_config.build_dir),
- shell=True)
- check_call('cd %s; %s/tools/mkeficapsule --index 2 --guid 5A7021F5-FEF2-48B4-AABA-832E777418C0 u-boot.env.new Test02' %
- (data_dir, u_boot_config.build_dir),
- shell=True)
- check_call('cd %s; %s/tools/mkeficapsule --index 1 --guid 058B7D83-50D5-4C47-A195-60D86AD341C4 u-boot.bin.new Test03' %
- (data_dir, u_boot_config.build_dir),
- shell=True)
- check_call('cd %s; %s/tools/mkeficapsule --index 1 --guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 uboot_bin_env.itb Test04' %
- (data_dir, u_boot_config.build_dir),
- shell=True)
- check_call('cd %s; %s/tools/mkeficapsule --index 1 --guid 058B7D83-50D5-4C47-A195-60D86AD341C4 uboot_bin_env.itb Test05' %
- (data_dir, u_boot_config.build_dir),
- shell=True)
- check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 5 '
- '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 u-boot.bin.new Test101' %
- (data_dir, u_boot_config.build_dir),
- shell=True)
- check_call('cd %s; %s/tools/mkeficapsule --index 2 --fw-version 10 '
- '--guid 5A7021F5-FEF2-48B4-AABA-832E777418C0 u-boot.env.new Test102' %
- (data_dir, u_boot_config.build_dir),
- shell=True)
- check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 2 '
- '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 u-boot.bin.new Test103' %
- (data_dir, u_boot_config.build_dir),
- shell=True)
- check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 5 '
- '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 uboot_bin_env.itb Test104' %
- (data_dir, u_boot_config.build_dir),
- shell=True)
- check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 2 '
- '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 uboot_bin_env.itb Test105' %
- (data_dir, u_boot_config.build_dir),
- shell=True)
- if capsule_auth_enabled:
- # raw firmware signed with proper key
- check_call('cd %s; '
- '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
- '--private-key SIGNER.key --certificate SIGNER.crt '
- '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 '
- 'u-boot.bin.new Test11'
- % (data_dir, u_boot_config.build_dir),
- shell=True)
- # raw firmware signed with *mal* key
- check_call('cd %s; '
- '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
- '--private-key SIGNER2.key '
- '--certificate SIGNER2.crt '
- '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 '
- 'u-boot.bin.new Test12'
- % (data_dir, u_boot_config.build_dir),
- shell=True)
- # FIT firmware signed with proper key
- check_call('cd %s; '
- '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
- '--private-key SIGNER.key --certificate SIGNER.crt '
- '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 '
- 'uboot_bin_env.itb Test13'
- % (data_dir, u_boot_config.build_dir),
- shell=True)
- # FIT firmware signed with *mal* key
- check_call('cd %s; '
- '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
- '--private-key SIGNER2.key '
- '--certificate SIGNER2.crt '
- '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 '
- 'uboot_bin_env.itb Test14'
- % (data_dir, u_boot_config.build_dir),
- shell=True)
- # raw firmware signed with proper key with version information
- check_call('cd %s; '
- '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
- '--fw-version 5 '
- '--private-key SIGNER.key --certificate SIGNER.crt '
- '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 '
- 'u-boot.bin.new Test111'
- % (data_dir, u_boot_config.build_dir),
- shell=True)
- # raw firmware signed with proper key with version information
- check_call('cd %s; '
- '%s/tools/mkeficapsule --index 2 --monotonic-count 1 '
- '--fw-version 10 '
- '--private-key SIGNER.key --certificate SIGNER.crt '
- '--guid 5A7021F5-FEF2-48B4-AABA-832E777418C0 '
- 'u-boot.env.new Test112'
- % (data_dir, u_boot_config.build_dir),
- shell=True)
- # raw firmware signed with proper key with lower version information
- check_call('cd %s; '
- '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
- '--fw-version 2 '
- '--private-key SIGNER.key --certificate SIGNER.crt '
- '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 '
- 'u-boot.bin.new Test113'
- % (data_dir, u_boot_config.build_dir),
- shell=True)
- # FIT firmware signed with proper key with version information
- check_call('cd %s; '
- '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
- '--fw-version 5 '
- '--private-key SIGNER.key --certificate SIGNER.crt '
- '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 '
- 'uboot_bin_env.itb Test114'
- % (data_dir, u_boot_config.build_dir),
- shell=True)
- # FIT firmware signed with proper key with lower version information
- check_call('cd %s; '
- '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
- '--fw-version 2 '
- '--private-key SIGNER.key --certificate SIGNER.crt '
- '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 '
- 'uboot_bin_env.itb Test115'
- % (data_dir, u_boot_config.build_dir),
- shell=True)
+ pythonpath = os.environ.get('PYTHONPATH', '')
+ os.environ['PYTHONPATH'] = pythonpath + ':' + '%s/scripts/dtc/pylibfdt' % u_boot_config.build_dir
+ check_call('cd %s; '
+ 'cc -E -I %s/include -x assembler-with-cpp -o capsule_gen_tmp.dts %s/test/py/tests/test_efi_capsule/capsule_gen_binman.dts; '
+ 'dtc -I dts -O dtb capsule_gen_tmp.dts -o capsule_binman.dtb;'
+ % (data_dir, u_boot_config.source_dir, u_boot_config.source_dir), shell=True)
+ check_call('cd %s; '
+ './tools/binman/binman --toolpath %s/tools build -u -d %s/capsule_binman.dtb -O %s -m --allow-missing -I %s -I ./board/sandbox -I ./arch/sandbox/dts'
+ % (u_boot_config.source_dir, u_boot_config.build_dir, data_dir, data_dir, data_dir), shell=True)
+ os.environ['PYTHONPATH'] = pythonpath
# Create a disk image with EFI system partition
check_call('virt-make-fs --partition=gpt --size=+1M --type=vfat %s %s' %
diff --git a/test/py/tests/test_efi_capsule/signature.dts b/test/py/tests/test_efi_capsule/signature.dts
deleted file mode 100644
index 078cfc7..0000000
--- a/test/py/tests/test_efi_capsule/signature.dts
+++ /dev/null
@@ -1,10 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-/dts-v1/;
-/plugin/;
-
-&{/} {
- signature {
- capsule-key = /incbin/("SIGNER.esl");
- };
-};
diff --git a/test/py/tests/test_efi_capsule/uboot_bin_env.its b/test/py/tests/test_efi_capsule/uboot_bin_env.its
deleted file mode 100644
index fc65907..0000000
--- a/test/py/tests/test_efi_capsule/uboot_bin_env.its
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Automatic software update for U-Boot
- * Make sure the flashing addresses ('load' prop) is correct for your board!
- */
-
-/dts-v1/;
-
-/ {
- description = "Automatic U-Boot environment update";
- #address-cells = <2>;
-
- images {
- u-boot-bin {
- description = "U-Boot binary on SPI Flash";
- data = /incbin/("BINFILE1");
- compression = "none";
- type = "firmware";
- arch = "sandbox";
- load = <0>;
- hash-1 {
- algo = "sha1";
- };
- };
- u-boot-env {
- description = "U-Boot environment on SPI Flash";
- data = /incbin/("BINFILE2");
- compression = "none";
- type = "firmware";
- arch = "sandbox";
- load = <0>;
- hash-1 {
- algo = "sha1";
- };
- };
- };
-};
diff --git a/test/py/tests/test_event_dump.py b/test/py/tests/test_event_dump.py
index da196df..e282c67 100644
--- a/test/py/tests/test_event_dump.py
+++ b/test/py/tests/test_event_dump.py
@@ -18,5 +18,7 @@
-------------------- ------------------------------ ------------------------------
EVT_FT_FIXUP bootmeth_vbe_ft_fixup .*boot/vbe_request.c:.*
EVT_FT_FIXUP bootmeth_vbe_simple_ft_fixup .*boot/vbe_simple_os.c:.*
-EVT_MISC_INIT_F sandbox_misc_init_f .*arch/sandbox/cpu/start.c:'''
+EVT_LAST_STAGE_INIT install_smbios_table .*lib/efi_loader/efi_smbios.c:.*
+EVT_MISC_INIT_F sandbox_early_getopt_check .*arch/sandbox/cpu/start.c:.*
+EVT_TEST h_adder_simple .*test/common/event.c:'''
assert re.match(expect, out, re.MULTILINE) is not None
diff --git a/test/py/tests/test_fs/conftest.py b/test/py/tests/test_fs/conftest.py
index 0d87d18..7c76425 100644
--- a/test/py/tests/test_fs/conftest.py
+++ b/test/py/tests/test_fs/conftest.py
@@ -9,6 +9,7 @@
from subprocess import call, check_call, check_output, CalledProcessError
from fstest_defs import *
import u_boot_utils as util
+# pylint: disable=E0611
from tests import fs_helper
supported_fs_basic = ['fat16', 'fat32', 'ext4']
diff --git a/test/py/tests/test_gpt.py b/test/py/tests/test_gpt.py
index 73bfbf7..6e135b6 100644
--- a/test/py/tests/test_gpt.py
+++ b/test/py/tests/test_gpt.py
@@ -16,6 +16,35 @@
# Mark all tests here as slow
pytestmark = pytest.mark.slow
+def parse_gpt_parts(disk_str):
+ """Parser a partition string into a list of partitions.
+
+ Args:
+ disk_str: The disk description string, as returned by `gpt read`
+
+ Returns:
+ A list of parsed partitions. Each partition is a dictionary with the
+ string value from each specified key in the partition description, or a
+ key with with the value True for a boolean flag
+ """
+ parts = []
+ for part_str in disk_str.split(';'):
+ part = {}
+ for option in part_str.split(","):
+ if not option:
+ continue
+
+ if "=" in option:
+ key, value = option.split("=")
+ part[key] = value
+ else:
+ part[option] = True
+
+ if part:
+ parts.append(part)
+
+ return parts
+
class GptTestDiskImage(object):
"""Disk Image used by the GPT tests."""
@@ -49,10 +78,13 @@
u_boot_utils.run_and_log(u_boot_console, cmd)
# part1 offset 1MB size 1MB
cmd = ('sgdisk', '--new=1:2048:4095', '--change-name=1:part1',
+ '--partition-guid=1:33194895-67f6-4561-8457-6fdeed4f50a3',
+ '-A 1:set:2',
persistent)
# part2 offset 2MB size 1.5MB
u_boot_utils.run_and_log(u_boot_console, cmd)
cmd = ('sgdisk', '--new=2:4096:7167', '--change-name=2:part2',
+ '--partition-guid=2:cc9c6e4a-6551-4cb5-87be-3210f96c86fb',
persistent)
u_boot_utils.run_and_log(u_boot_console, cmd)
cmd = ('sgdisk', '--load-backup=' + persistent)
@@ -61,18 +93,14 @@
cmd = ('cp', persistent, self.path)
u_boot_utils.run_and_log(u_boot_console, cmd)
-gtdi = None
@pytest.fixture(scope='function')
def state_disk_image(u_boot_console):
"""pytest fixture to provide a GptTestDiskImage object to tests.
This is function-scoped because it uses u_boot_console, which is also
- function-scoped. However, we don't need to actually do any function-scope
- work, so this simply returns the same object over and over each time."""
+ function-scoped. A new disk is returned each time to prevent tests from
+ interfering with each other."""
- global gtdi
- if not gtdi:
- gtdi = GptTestDiskImage(u_boot_console)
- return gtdi
+ return GptTestDiskImage(u_boot_console)
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpt')
@@ -93,6 +121,41 @@
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpt')
+@pytest.mark.buildconfigspec('partition_type_guid')
+@pytest.mark.requiredtool('sgdisk')
+def test_gpt_read_var(state_disk_image, u_boot_console):
+ """Test the gpt read command."""
+
+ u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
+ output = u_boot_console.run_command('gpt read host 0 gpt_parts')
+ assert 'success!' in output
+
+ output = u_boot_console.run_command('echo ${gpt_parts}')
+ parts = parse_gpt_parts(output.rstrip())
+
+ assert parts == [
+ {
+ "uuid_disk": "375a56f7-d6c9-4e81-b5f0-09d41ca89efe",
+ },
+ {
+ "name": "part1",
+ "start": "0x100000",
+ "size": "0x100000",
+ "type": "0fc63daf-8483-4772-8e79-3d69d8477de4",
+ "uuid": "33194895-67f6-4561-8457-6fdeed4f50a3",
+ "bootable": True,
+ },
+ {
+ "name": "part2",
+ "start": "0x200000",
+ "size": "0x180000",
+ "type": "0fc63daf-8483-4772-8e79-3d69d8477de4",
+ "uuid": "cc9c6e4a-6551-4cb5-87be-3210f96c86fb",
+ },
+ ]
+
+@pytest.mark.boardspec('sandbox')
+@pytest.mark.buildconfigspec('cmd_gpt')
@pytest.mark.requiredtool('sgdisk')
def test_gpt_verify(state_disk_image, u_boot_console):
"""Test the gpt verify command."""
@@ -124,6 +187,38 @@
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpt')
@pytest.mark.requiredtool('sgdisk')
+def test_gpt_setenv(state_disk_image, u_boot_console):
+ """Test the gpt setenv command."""
+ u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
+ output = u_boot_console.run_command('gpt setenv host 0 part1')
+ assert 'success!' in output
+ output = u_boot_console.run_command('echo ${gpt_partition_addr}')
+ assert output.rstrip() == '800'
+ output = u_boot_console.run_command('echo ${gpt_partition_size}')
+ assert output.rstrip() == '800'
+ output = u_boot_console.run_command('echo ${gpt_partition_name}')
+ assert output.rstrip() == 'part1'
+ output = u_boot_console.run_command('echo ${gpt_partition_entry}')
+ assert output.rstrip() == '1'
+ output = u_boot_console.run_command('echo ${gpt_partition_bootable}')
+ assert output.rstrip() == '1'
+
+ output = u_boot_console.run_command('gpt setenv host 0 part2')
+ assert 'success!' in output
+ output = u_boot_console.run_command('echo ${gpt_partition_addr}')
+ assert output.rstrip() == '1000'
+ output = u_boot_console.run_command('echo ${gpt_partition_size}')
+ assert output.rstrip() == 'c00'
+ output = u_boot_console.run_command('echo ${gpt_partition_name}')
+ assert output.rstrip() == 'part2'
+ output = u_boot_console.run_command('echo ${gpt_partition_entry}')
+ assert output.rstrip() == '2'
+ output = u_boot_console.run_command('echo ${gpt_partition_bootable}')
+ assert output.rstrip() == '0'
+
+@pytest.mark.boardspec('sandbox')
+@pytest.mark.buildconfigspec('cmd_gpt')
+@pytest.mark.requiredtool('sgdisk')
def test_gpt_save_guid(state_disk_image, u_boot_console):
"""Test the gpt guid command to save GUID into a string."""
@@ -186,12 +281,34 @@
u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
output = u_boot_console.run_command('part list host 0')
- assert '0x00000800 0x00000fff "first"' in output
- assert '0x00001000 0x00001bff "second"' in output
- u_boot_console.run_command('gpt swap host 0 first second')
+ assert '0x00000800 0x00000fff "part1"' in output
+ assert '0x00001000 0x00001bff "part2"' in output
+ u_boot_console.run_command('gpt swap host 0 part1 part2')
output = u_boot_console.run_command('part list host 0')
- assert '0x00000800 0x00000fff "second"' in output
- assert '0x00001000 0x00001bff "first"' in output
+ assert '0x00000800 0x00000fff "part2"' in output
+ assert '0x00001000 0x00001bff "part1"' in output
+
+@pytest.mark.buildconfigspec('cmd_gpt')
+@pytest.mark.buildconfigspec('cmd_gpt_rename')
+@pytest.mark.buildconfigspec('cmd_part')
+@pytest.mark.requiredtool('sgdisk')
+def test_gpt_set_bootable(state_disk_image, u_boot_console):
+ """Test the gpt set-bootable command."""
+
+ u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
+ parts = ('part2', 'part1')
+ for bootable in parts:
+ output = u_boot_console.run_command(f'gpt set-bootable host 0 {bootable}')
+ assert 'success!' in output
+
+ for p in parts:
+ output = u_boot_console.run_command(f'gpt setenv host 0 {p}')
+ assert 'success!' in output
+ output = u_boot_console.run_command('echo ${gpt_partition_bootable}')
+ if p == bootable:
+ assert output.rstrip() == '1'
+ else:
+ assert output.rstrip() == '0'
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpt')
@@ -212,3 +329,22 @@
assert '0x00001000 0x00001bff "second"' in output
output = u_boot_console.run_command('gpt guid host 0')
assert '375a56f7-d6c9-4e81-b5f0-09d41ca89efe' in output
+
+@pytest.mark.buildconfigspec('cmd_gpt')
+@pytest.mark.buildconfigspec('cmd_gpt_rename')
+@pytest.mark.buildconfigspec('cmd_part')
+@pytest.mark.requiredtool('sgdisk')
+def test_gpt_transpose(state_disk_image, u_boot_console):
+ """Test the gpt transpose command."""
+
+ u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
+ output = u_boot_console.run_command('part list host 0')
+ assert '1\t0x00000800\t0x00000fff\t"part1"' in output
+ assert '2\t0x00001000\t0x00001bff\t"part2"' in output
+
+ output = u_boot_console.run_command('gpt transpose host 0 1 2')
+ assert 'success!' in output
+
+ output = u_boot_console.run_command('part list host 0')
+ assert '2\t0x00000800\t0x00000fff\t"part1"' in output
+ assert '1\t0x00001000\t0x00001bff\t"part2"' in output
diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py
index cd4b4dc..b2241ae 100644
--- a/test/py/tests/test_net.py
+++ b/test/py/tests/test_net.py
@@ -6,6 +6,7 @@
import pytest
import u_boot_utils
+import uuid
"""
Note: This test relies on boardenv_* containing configuration values to define
@@ -61,6 +62,16 @@
'crc32': 'c2244b26',
}
+# Details regarding a file that may be read from a TFTP server. This variable
+# may be omitted or set to None if PXE testing is not possible or desired.
+env__net_pxe_readable_file = {
+ 'fn': 'default',
+ 'addr': 0x2000000,
+ 'size': 74,
+ 'timeout': 50000,
+ 'pattern': 'Linux',
+}
+
# True if a router advertisement service is connected to the network, and should
# be tested. If router advertisement testing is not possible or desired, this
variable may be omitted or set to False.
@@ -260,3 +271,58 @@
output = u_boot_console.run_command('crc32 %x $filesize' % addr)
assert expected_crc in output
+
+@pytest.mark.buildconfigspec("cmd_net")
+@pytest.mark.buildconfigspec("cmd_pxe")
+def test_net_pxe_get(u_boot_console):
+ """Test the pxe get command.
+
+ A pxe configuration file is downloaded from the TFTP server and interpreted
+ to boot the images mentioned in pxe configuration file.
+
+ The details of the file to download are provided by the boardenv_* file;
+ see the comment at the beginning of this file.
+ """
+
+ if not net_set_up:
+ pytest.skip("Network not initialized")
+
+ test_net_setup_static(u_boot_console)
+
+ f = u_boot_console.config.env.get("env__net_pxe_readable_file", None)
+ if not f:
+ pytest.skip("No PXE readable file to read")
+
+ addr = f.get("addr", None)
+ timeout = f.get("timeout", u_boot_console.p.timeout)
+
+ pxeuuid = uuid.uuid1()
+ u_boot_console.run_command(f"setenv pxeuuid {pxeuuid}")
+ expected_text_uuid = f"Retrieving file: pxelinux.cfg/{pxeuuid}"
+
+ ethaddr = u_boot_console.run_command("echo $ethaddr")
+ ethaddr = ethaddr.replace(':', '-')
+ expected_text_ethaddr = f"Retrieving file: pxelinux.cfg/01-{ethaddr}"
+
+ ip = u_boot_console.run_command("echo $ipaddr")
+ ip = ip.split('.')
+ ipaddr_file = "".join(['%02x' % int(x) for x in ip]).upper()
+ expected_text_ipaddr = f"Retrieving file: pxelinux.cfg/{ipaddr_file}"
+ expected_text_default = f"Retrieving file: pxelinux.cfg/default"
+
+ with u_boot_console.temporary_timeout(timeout):
+ output = u_boot_console.run_command("pxe get")
+
+ assert "TIMEOUT" not in output
+ assert expected_text_uuid in output
+ assert expected_text_ethaddr in output
+ assert expected_text_ipaddr in output
+
+ i = 1
+ for i in range(0, len(ipaddr_file) - 1):
+ expected_text_ip = f"Retrieving file: pxelinux.cfg/{ipaddr_file[:-i]}"
+ assert expected_text_ip in output
+ i += 1
+
+ assert expected_text_default in output
+ assert "Config file 'default.boot' found" in output
diff --git a/test/py/tests/test_semihosting/conftest.py b/test/py/tests/test_semihosting/conftest.py
new file mode 100644
index 0000000..b00d8f4
--- /dev/null
+++ b/test/py/tests/test_semihosting/conftest.py
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+"""Fixture for semihosting command test
+"""
+
+import os
+import pytest
+
+@pytest.fixture(scope='session')
+def semihosting_data(u_boot_config):
+ """Set up a file system to be used in semihosting tests
+
+ Args:
+ u_boot_config -- U-Boot configuration.
+ """
+ image_path = u_boot_config.persistent_data_dir + '/semihosting.txt'
+
+ with open(image_path, 'w', encoding = 'utf-8') as file:
+ file.write('Das U-Boot\n')
+
+ yield image_path
+
+ os.remove(image_path)
diff --git a/test/py/tests/test_semihosting/test_hostfs.py b/test/py/tests/test_semihosting/test_hostfs.py
new file mode 100644
index 0000000..51f6fa7
--- /dev/null
+++ b/test/py/tests/test_semihosting/test_hostfs.py
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+""" Unit test for semihosting
+"""
+
+import pytest
+
+@pytest.mark.buildconfigspec('semihosting')
+def test_semihosting_hostfs(u_boot_console, semihosting_data):
+ """ Unit test for semihosting
+
+ Args:
+ u_boot_console -- U-Boot console
+ semihosting_data -- Path to the disk image used for testing.
+ """
+ response = u_boot_console.run_command(
+ f'load hostfs - $loadaddr {semihosting_data}')
+ assert '11 bytes read' in response
+
+ response = u_boot_console.run_command(
+ 'crc32 $loadaddr $filesize')
+ assert '==> 60cfccfc' in response
+
+ u_boot_console.run_command(
+ f'save hostfs - $loadaddr {semihosting_data} 11 11')
+
+ response = u_boot_console.run_command(
+ f'load hostfs - $loadaddr {semihosting_data} 4 13')
+ assert '4 bytes read' in response
+
+ response = u_boot_console.run_command(
+ 'crc32 $loadaddr $filesize')
+ assert '==> e29063ea' in response
diff --git a/test/py/tests/test_sleep.py b/test/py/tests/test_sleep.py
index 392af29..66a5743 100644
--- a/test/py/tests/test_sleep.py
+++ b/test/py/tests/test_sleep.py
@@ -41,3 +41,21 @@
if not u_boot_console.config.gdbserver:
# margin is hopefully enough to account for any system overhead.
assert elapsed < (sleep_time + sleep_margin)
+
+@pytest.mark.buildconfigspec("cmd_misc")
+def test_time(u_boot_console):
+ """Test the time command, and validate that it gives approximately the
+ correct amount of command execution time."""
+
+ sleep_skip = u_boot_console.config.env.get("env__sleep_accurate", True)
+ if not sleep_skip:
+ pytest.skip("sleep is not accurate")
+
+ sleep_time = u_boot_console.config.env.get("env__sleep_time", 10)
+ sleep_margin = u_boot_console.config.env.get("env__sleep_margin", 0.25)
+ output = u_boot_console.run_command("time sleep %d" % sleep_time)
+ execute_time = float(output.split()[1])
+ assert sleep_time >= (execute_time - 0.01)
+ if not u_boot_console.config.gdbserver:
+ # margin is hopefully enough to account for any system overhead.
+ assert sleep_time < (execute_time + sleep_margin)
diff --git a/test/py/tests/test_spl.py b/test/py/tests/test_spl.py
index bd273da..42e4c43 100644
--- a/test/py/tests/test_spl.py
+++ b/test/py/tests/test_spl.py
@@ -5,6 +5,16 @@
import os.path
import pytest
+@pytest.mark.buildconfigspec('spl_unit_test')
+def test_ut_spl_init(u_boot_console):
+ """Initialize data for ut spl tests."""
+
+ fn = u_boot_console.config.source_dir + '/spi.bin'
+ if not os.path.exists(fn):
+ data = b'\x00' * (2 * 1024 * 1024)
+ with open(fn, 'wb') as fh:
+ fh.write(data)
+
def test_spl(u_boot_console, ut_spl_subtest):
"""Execute a "ut" subtest.
diff --git a/test/py/tests/test_tpm2.py b/test/py/tests/test_tpm2.py
index fce689c..1d654cd 100644
--- a/test/py/tests/test_tpm2.py
+++ b/test/py/tests/test_tpm2.py
@@ -61,7 +61,7 @@
skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
if skip_test:
pytest.skip('skip TPM device test')
- u_boot_console.run_command('tpm2 init')
+ u_boot_console.run_command('tpm2 autostart')
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
@@ -71,6 +71,9 @@
Initiate the TPM internal state machine.
"""
+ skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
+ if skip_test:
+ pytest.skip('skip TPM device test')
u_boot_console.run_command('tpm2 startup TPM2_SU_CLEAR')
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
@@ -97,7 +100,7 @@
"""
if is_sandbox(u_boot_console):
u_boot_console.restart_uboot()
- u_boot_console.run_command('tpm2 init')
+ u_boot_console.run_command('tpm2 autostart')
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
@@ -236,7 +239,7 @@
def test_tpm2_pcr_read(u_boot_console):
"""Execute a TPM2_PCR_Read command.
- Perform a PCR read of the 0th PCR. Must be zero.
+ Perform a PCR read of the 10th PCR. Must be zero.
"""
if is_sandbox(u_boot_console):
tpm2_sandbox_init(u_boot_console)
@@ -244,7 +247,7 @@
force_init(u_boot_console)
ram = u_boot_utils.find_ram_base(u_boot_console)
- read_pcr = u_boot_console.run_command('tpm2 pcr_read 0 0x%x' % ram)
+ read_pcr = u_boot_console.run_command('tpm2 pcr_read 10 0x%x' % ram)
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
@@ -254,7 +257,7 @@
updates = int(re.findall(r'\d+', str)[0])
# Check the output value
- assert 'PCR #0 content' in read_pcr
+ assert 'PCR #10 content' in read_pcr
assert '00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00' in read_pcr
@pytest.mark.buildconfigspec('cmd_tpm_v2')
@@ -272,19 +275,19 @@
force_init(u_boot_console)
ram = u_boot_utils.find_ram_base(u_boot_console)
- read_pcr = u_boot_console.run_command('tpm2 pcr_read 0 0x%x' % (ram + 0x20))
+ read_pcr = u_boot_console.run_command('tpm2 pcr_read 10 0x%x' % (ram + 0x20))
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
str = re.findall(r'\d+ known updates', read_pcr)[0]
updates = int(re.findall(r'\d+', str)[0])
- u_boot_console.run_command('tpm2 pcr_extend 0 0x%x' % ram)
+ u_boot_console.run_command('tpm2 pcr_extend 10 0x%x' % ram)
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
# Read the value back into a different place so we can still use 'ram' as
# our zero bytes
- read_pcr = u_boot_console.run_command('tpm2 pcr_read 0 0x%x' % (ram + 0x20))
+ read_pcr = u_boot_console.run_command('tpm2 pcr_read 10 0x%x' % (ram + 0x20))
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
assert 'f5 a5 fd 42 d1 6a 20 30 27 98 ef 6e d3 09 97 9b' in read_pcr
@@ -294,11 +297,11 @@
new_updates = int(re.findall(r'\d+', str)[0])
assert (updates + 1) == new_updates
- u_boot_console.run_command('tpm2 pcr_extend 0 0x%x' % ram)
+ u_boot_console.run_command('tpm2 pcr_extend 10 0x%x' % ram)
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
- read_pcr = u_boot_console.run_command('tpm2 pcr_read 0 0x%x' % (ram + 0x20))
+ read_pcr = u_boot_console.run_command('tpm2 pcr_read 10 0x%x' % (ram + 0x20))
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
assert '7a 05 01 f5 95 7b df 9c b3 a8 ff 49 66 f0 22 65' in read_pcr
diff --git a/test/py/tests/test_trace.py b/test/py/tests/test_trace.py
index ac3e959..28a6e72 100644
--- a/test/py/tests/test_trace.py
+++ b/test/py/tests/test_trace.py
@@ -61,7 +61,7 @@
# Read out the trace data
addr = 0x02000000
- size = 0x01000000
+ size = 0x02000000
out = cons.run_command(f'trace calls {addr:x} {size:x}')
print(out)
fname = os.path.join(TMPDIR, 'trace')
@@ -175,7 +175,7 @@
# Then look for this:
# u-boot-1 [000] 282.101375: funcgraph_exit: 0.006 us | }
# Then check for this:
- # u-boot-1 [000] 282.101375: funcgraph_entry: 0.000 us | event_init();
+ # u-boot-1 [000] 282.101375: funcgraph_entry: 0.000 us | initcall_is_event();
expected_indent = None
found_start = False
@@ -197,8 +197,9 @@
elif found_start and indent == expected_indent and brace == '}':
found_end = True
- # The next function after initf_bootstage() exits should be event_init()
- assert upto == 'event_init()'
+ # The next function after initf_bootstage() exits should be
+ # initcall_is_event()
+ assert upto == 'initcall_is_event()'
# Now look for initf_dm() and dm_timer_init() so we can check the bootstage
# time
@@ -247,7 +248,7 @@
# We expect dm_timer_init() to be called twice: once before relocation and
# once after
look1 = 'initf_dm;dm_timer_init 1'
- look2 = 'board_init_r;initr_dm_devices;dm_timer_init 1'
+ look2 = 'board_init_r;initcall_run_list;initr_dm_devices;dm_timer_init 1'
found = 0
with open(trace_fg, 'r') as fd:
for line in fd:
@@ -272,7 +273,7 @@
total += count
return total
-
+check_flamegraph
@pytest.mark.slow
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('trace')
diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py
index aa1d477..0e3a48e 100644
--- a/test/py/tests/test_ut.py
+++ b/test/py/tests/test_ut.py
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
# Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+import collections
import getpass
import gzip
import os
@@ -8,6 +9,7 @@
import pytest
import u_boot_utils
+# pylint: disable=E0611
from tests import fs_helper
def mkdir_cond(dirname):
@@ -282,14 +284,155 @@
copy_prepared_image(cons, mmc_dev, fname)
+def setup_cros_image(cons):
+ """Create a 20MB disk image with ChromiumOS partitions"""
+ Partition = collections.namedtuple('part', 'start,size,name')
+ parts = {}
+ disk_data = None
+
+ def pack_kernel(cons, arch, kern, dummy):
+ """Pack a kernel containing some fake data
+
+ Args:
+ cons (ConsoleBase): Console to use
+ arch (str): Architecture to use ('x86' or 'arm')
+ kern (str): Filename containing kernel
+ dummy (str): Dummy filename to use for config and bootloader
+
+ Return:
+ bytes: Packed-kernel data
+ """
+ kern_part = os.path.join(cons.config.result_dir, 'kern-part-{arch}.bin')
+ u_boot_utils.run_and_log(
+ cons,
+ f'futility vbutil_kernel --pack {kern_part} '
+ '--keyblock doc/chromium/files/devkeys/kernel.keyblock '
+ '--signprivate doc/chromium/files/devkeys/kernel_data_key.vbprivk '
+ f'--version 1 --config {dummy} --bootloader {dummy} '
+ f'--vmlinuz {kern}')
+
+ with open(kern_part, 'rb') as inf:
+ kern_part_data = inf.read()
+ return kern_part_data
+
+ def set_part_data(partnum, data):
+ """Set the contents of a disk partition
+
+ This updates disk_data by putting data in the right place
+
+ Args:
+ partnum (int): Partition number to set
+ data (bytes): Data for that partition
+ """
+ nonlocal disk_data
+
+ start = parts[partnum].start * sect_size
+ disk_data = disk_data[:start] + data + disk_data[start + len(data):]
+
+ mmc_dev = 5
+ fname = os.path.join(cons.config.source_dir, f'mmc{mmc_dev}.img')
+ u_boot_utils.run_and_log(cons, 'qemu-img create %s 20M' % fname)
+ #mnt = os.path.join(cons.config.persistent_data_dir, 'mnt')
+ #mkdir_cond(mnt)
+ u_boot_utils.run_and_log(cons, f'cgpt create {fname}')
+
+ uuid_state = 'ebd0a0a2-b9e5-4433-87c0-68b6b72699c7'
+ uuid_kern = 'fe3a2a5d-4f32-41a7-b725-accc3285a309'
+ uuid_root = '3cb8e202-3b7e-47dd-8a3c-7ff2a13cfcec'
+ uuid_rwfw = 'cab6e88e-abf3-4102-a07a-d4bb9be3c1d3'
+ uuid_reserved = '2e0a753d-9e48-43b0-8337-b15192cb1b5e'
+ uuid_efi = 'c12a7328-f81f-11d2-ba4b-00a0c93ec93b'
+
+ ptr = 40
+
+ # Number of sectors in 1MB
+ sect_size = 512
+ sect_1mb = (1 << 20) // sect_size
+
+ required_parts = [
+ {'num': 0xb, 'label':'RWFW', 'type': uuid_rwfw, 'size': '1'},
+ {'num': 6, 'label':'KERN_C', 'type': uuid_kern, 'size': '1'},
+ {'num': 7, 'label':'ROOT_C', 'type': uuid_root, 'size': '1'},
+ {'num': 9, 'label':'reserved', 'type': uuid_reserved, 'size': '1'},
+ {'num': 0xa, 'label':'reserved', 'type': uuid_reserved, 'size': '1'},
+
+ {'num': 2, 'label':'KERN_A', 'type': uuid_kern, 'size': '1M'},
+ {'num': 4, 'label':'KERN_B', 'type': uuid_kern, 'size': '1M'},
+
+ {'num': 8, 'label':'OEM', 'type': uuid_state, 'size': '1M'},
+ {'num': 0xc, 'label':'EFI-SYSTEM', 'type': uuid_efi, 'size': '1M'},
+
+ {'num': 5, 'label':'ROOT_B', 'type': uuid_root, 'size': '1'},
+ {'num': 3, 'label':'ROOT_A', 'type': uuid_root, 'size': '1'},
+ {'num': 1, 'label':'STATE', 'type': uuid_state, 'size': '1M'},
+ ]
+
+ for part in required_parts:
+ size_str = part['size']
+ if 'M' in size_str:
+ size = int(size_str[:-1]) * sect_1mb
+ else:
+ size = int(size_str)
+ u_boot_utils.run_and_log(
+ cons,
+ f"cgpt add -i {part['num']} -b {ptr} -s {size} -t {part['type']} {fname}")
+ ptr += size
+
+ u_boot_utils.run_and_log(cons, f'cgpt boot -p {fname}')
+ out = u_boot_utils.run_and_log(cons, f'cgpt show -q {fname}')
+ '''We expect something like this:
+ 8239 2048 1 Basic data
+ 45 2048 2 ChromeOS kernel
+ 8238 1 3 ChromeOS rootfs
+ 2093 2048 4 ChromeOS kernel
+ 8237 1 5 ChromeOS rootfs
+ 41 1 6 ChromeOS kernel
+ 42 1 7 ChromeOS rootfs
+ 4141 2048 8 Basic data
+ 43 1 9 ChromeOS reserved
+ 44 1 10 ChromeOS reserved
+ 40 1 11 ChromeOS firmware
+ 6189 2048 12 EFI System Partition
+ '''
+
+ # Create a dict (indexed by partition number) containing the above info
+ for line in out.splitlines():
+ start, size, num, name = line.split(maxsplit=3)
+ parts[int(num)] = Partition(int(start), int(size), name)
+
+ dummy = os.path.join(cons.config.result_dir, 'dummy.txt')
+ with open(dummy, 'wb') as outf:
+ outf.write(b'dummy\n')
+
+ # For now we just use dummy kernels. This limits testing to just detecting
+ # a signed kernel. We could add support for the x86 data structures so that
+ # testing could cover getting the cmdline, setup.bin and other pieces.
+ kern = os.path.join(cons.config.result_dir, 'kern.bin')
+ with open(kern, 'wb') as outf:
+ outf.write(b'kernel\n')
+
+ with open(fname, 'rb') as inf:
+ disk_data = inf.read()
+
+ # put x86 kernel in partition 2 and arm one in partition 4
+ set_part_data(2, pack_kernel(cons, 'x86', kern, dummy))
+ set_part_data(4, pack_kernel(cons, 'arm', kern, dummy))
+
+ with open(fname, 'wb') as outf:
+ outf.write(disk_data)
+
+ return fname
+
+
def setup_cedit_file(cons):
infname = os.path.join(cons.config.source_dir,
'test/boot/files/expo_layout.dts')
+ inhname = os.path.join(cons.config.source_dir,
+ 'test/boot/files/expo_ids.h')
expo_tool = os.path.join(cons.config.source_dir, 'tools/expo.py')
outfname = 'cedit.dtb'
u_boot_utils.run_and_log(
- cons, f'{expo_tool} -e {infname} -l {infname} -o {outfname}')
-
+ cons, f'{expo_tool} -e {inhname} -l {infname} -o {outfname}')
@pytest.mark.buildconfigspec('ut_dm')
def test_ut_dm_init(u_boot_console):
@@ -317,10 +460,14 @@
u_boot_utils.run_and_log(
u_boot_console, f'sfdisk {fn}', stdin=b'type=83')
- fs_helper.mk_fs(u_boot_console.config, 'ext2', 0x200000, '2MB',
- use_src_dir=True)
- fs_helper.mk_fs(u_boot_console.config, 'fat32', 0x100000, '1MB',
- use_src_dir=True)
+ fs_helper.mk_fs(u_boot_console.config, 'ext2', 0x200000, '2MB')
+ fs_helper.mk_fs(u_boot_console.config, 'fat32', 0x100000, '1MB')
+
+ mmc_dev = 6
+ fn = os.path.join(u_boot_console.config.source_dir, f'mmc{mmc_dev}.img')
+ data = b'\x00' * (12 * 1024 * 1024)
+ with open(fn, 'wb') as fh:
+ fh.write(data)
@pytest.mark.buildconfigspec('cmd_bootflow')
def test_ut_dm_init_bootstd(u_boot_console):
@@ -329,6 +476,7 @@
setup_bootflow_image(u_boot_console)
setup_bootmenu_image(u_boot_console)
setup_cedit_file(u_boot_console)
+ setup_cros_image(u_boot_console)
# Restart so that the new mmc1.img is picked up
u_boot_console.restart_uboot()
diff --git a/test/test-main.c b/test/test-main.c
index 778bf0a..b7015d9 100644
--- a/test/test-main.c
+++ b/test/test-main.c
@@ -303,7 +303,7 @@
if (test->flags & UT_TESTF_PROBE_TEST)
ut_assertok(do_autoprobe(uts));
- if (!CONFIG_IS_ENABLED(OF_PLATDATA) &&
+ if (CONFIG_IS_ENABLED(OF_REAL) &&
(test->flags & UT_TESTF_SCAN_FDT)) {
/*
* only set this if we know the ethernet uclass will be created
@@ -476,7 +476,8 @@
* (for sandbox we handle this by copying the tree, but not for other
* boards)
*/
- if ((test->flags & UT_TESTF_SCAN_FDT) &&
+ if ((!CONFIG_IS_ENABLED(OF_LIVE) ||
+ (test->flags & UT_TESTF_SCAN_FDT)) &&
!(test->flags & UT_TESTF_LIVE_TREE) &&
(CONFIG_IS_ENABLED(OFNODE_MULTI_TREE) ||
!(test->flags & UT_TESTF_OTHER_FDT)) &&
diff --git a/test/unicode_ut.c b/test/unicode_ut.c
index b27d711..1d0d90c 100644
--- a/test/unicode_ut.c
+++ b/test/unicode_ut.c
@@ -807,28 +807,28 @@
/* dest and src are empty string */
memset(buf, 0, sizeof(buf));
- ret = u16_strlcat(buf, &null_src, sizeof(buf));
- ut_asserteq(1, ret);
+ ret = u16_strlcat(buf, &null_src, ARRAY_SIZE(buf));
+ ut_asserteq(0, ret);
/* dest is empty string */
memset(buf, 0, sizeof(buf));
- ret = u16_strlcat(buf, src, sizeof(buf));
- ut_asserteq(5, ret);
+ ret = u16_strlcat(buf, src, ARRAY_SIZE(buf));
+ ut_asserteq(4, ret);
ut_assert(!unicode_test_u16_strcmp(buf, src, 40));
/* src is empty string */
memset(buf, 0xCD, (sizeof(buf) - sizeof(u16)));
buf[39] = 0;
memcpy(buf, dest, sizeof(dest));
- ret = u16_strlcat(buf, &null_src, sizeof(buf));
- ut_asserteq(6, ret);
+ ret = u16_strlcat(buf, &null_src, ARRAY_SIZE(buf));
+ ut_asserteq(5, ret);
ut_assert(!unicode_test_u16_strcmp(buf, dest, 40));
for (i = 0; i <= 40; i++) {
memset(buf, 0xCD, (sizeof(buf) - sizeof(u16)));
buf[39] = 0;
memcpy(buf, dest, sizeof(dest));
- expected = 10;
+ expected = min(5, i) + 4;
ret = u16_strlcat(buf, src, i);
ut_asserteq(expected, ret);
if (i <= 6) {
diff --git a/tools/.gitignore b/tools/.gitignore
index 941d38d..0108c56 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -34,7 +34,7 @@
/relocate-rela
/spl_size_limit
/sunxi-spl-image-builder
-/tools/generated/**/*.c
+/generated/**/*.c
/update_octeon_header
/version.h
/xway-swap-bytes
diff --git a/tools/Makefile b/tools/Makefile
index 5d0eba8..a628b30 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -121,6 +121,7 @@
pblimage.o \
pbl_crc32.o \
renesas_spkgimage.o \
+ sfspl.o \
vybridimage.o \
stm32image.o \
$(ROCKCHIP_OBS) \
diff --git a/tools/binman/bintool.py b/tools/binman/bintool.py
index 0b0f56d..3c4ad1a 100644
--- a/tools/binman/bintool.py
+++ b/tools/binman/bintool.py
@@ -328,7 +328,7 @@
return result.stdout
@classmethod
- def build_from_git(cls, git_repo, make_target, bintool_path, flags=None):
+ def build_from_git(cls, git_repo, make_targets, bintool_path, flags=None):
"""Build a bintool from a git repo
This clones the repo in a temporary directory, builds it with 'make',
@@ -336,7 +336,8 @@
Args:
git_repo (str): URL of git repo
- make_target (str): Target to pass to 'make' to build the tool
+ make_targets (list of str): List of targets to pass to 'make' to build
+ the tool
bintool_path (str): Relative path of the tool in the repo, after
build is complete
flags (list of str): Flags or variables to pass to make, or None
@@ -350,12 +351,14 @@
tmpdir = tempfile.mkdtemp(prefix='binmanf.')
print(f"- clone git repo '{git_repo}' to '{tmpdir}'")
tools.run('git', 'clone', '--depth', '1', git_repo, tmpdir)
- print(f"- build target '{make_target}'")
- cmd = ['make', '-C', tmpdir, '-j', f'{multiprocessing.cpu_count()}',
- make_target]
- if flags:
- cmd += flags
- tools.run(*cmd)
+ for target in make_targets:
+ print(f"- build target '{target}'")
+ cmd = ['make', '-C', tmpdir, '-j', f'{multiprocessing.cpu_count()}',
+ target]
+ if flags:
+ cmd += flags
+ tools.run(*cmd)
+
fname = os.path.join(tmpdir, bintool_path)
if not os.path.exists(fname):
print(f"- File '{fname}' was not produced")
diff --git a/tools/binman/btool/bootgen.py b/tools/binman/btool/bootgen.py
index f2ca552..1bc9f0a 100644
--- a/tools/binman/btool/bootgen.py
+++ b/tools/binman/btool/bootgen.py
@@ -132,6 +132,6 @@
result = self.build_from_git(
'https://github.com/Xilinx/bootgen',
- 'all',
+ ['all'],
'bootgen')
return result
diff --git a/tools/binman/btool/fiptool.py b/tools/binman/btool/fiptool.py
index c80f827..34002f5 100644
--- a/tools/binman/btool/fiptool.py
+++ b/tools/binman/btool/fiptool.py
@@ -109,6 +109,6 @@
return None
result = self.build_from_git(
'https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git',
- 'fiptool',
+ ['fiptool'],
'tools/fiptool/fiptool')
return result
diff --git a/tools/binman/btool/futility.py b/tools/binman/btool/futility.py
index 04c9aef..0d3980d 100644
--- a/tools/binman/btool/futility.py
+++ b/tools/binman/btool/futility.py
@@ -170,7 +170,7 @@
# .gitcookies file. So use a mirror instead.
result = self.build_from_git(
'https://github.com/sjg20/vboot_reference.git',
- 'all',
+ ['all'],
'build/futility/futility',
flags=['USE_FLASHROM=0'])
return result
diff --git a/tools/binman/btool/mkeficapsule.py b/tools/binman/btool/mkeficapsule.py
new file mode 100644
index 0000000..ef1da63
--- /dev/null
+++ b/tools/binman/btool/mkeficapsule.py
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2023 Linaro Limited
+#
+"""Bintool implementation for mkeficapsule tool
+
+mkeficapsule is a tool used for generating EFI capsules.
+
+The following are the commandline options to be provided
+to the tool
+Usage: mkeficapsule [options] <image blob> <output file>
+Options:
+ -g, --guid <guid string> guid for image blob type
+ -i, --index <index> update image index
+ -I, --instance <instance> update hardware instance
+ -v, --fw-version <version> firmware version
+ -p, --private-key <privkey file> private key file
+ -c, --certificate <cert file> signer's certificate file
+ -m, --monotonic-count <count> monotonic count
+ -d, --dump_sig dump signature (*.p7)
+ -A, --fw-accept firmware accept capsule, requires GUID, no image blob
+ -R, --fw-revert firmware revert capsule, takes no GUID, no image blob
+ -o, --capoemflag Capsule OEM Flag, an integer between 0x0000 and 0xffff
+ -h, --help print a help message
+"""
+
+from binman import bintool
+
+class Bintoolmkeficapsule(bintool.Bintool):
+ """Handles the 'mkeficapsule' tool
+
+ This bintool is used for generating the EFI capsules. The
+ capsule generation parameters can either be specified through
+ commandline, or through a config file.
+ """
+ def __init__(self, name):
+ super().__init__(name, 'mkeficapsule tool for generating capsules')
+
+ def generate_capsule(self, image_index, image_guid, hardware_instance,
+ payload, output_fname, priv_key, pub_key,
+ monotonic_count=0, version=0, oemflags=0):
+ """Generate a capsule through commandline-provided parameters
+
+ Args:
+ image_index (int): Unique number for identifying payload image
+ image_guid (str): GUID used for identifying the image
+ hardware_instance (int): Optional unique hardware instance of
+ a device in the system. 0 if not being used
+ payload (str): Path to the input payload image
+ output_fname (str): Path to the output capsule file
+ priv_key (str): Path to the private key
+ pub_key(str): Path to the public key
+ monotonic_count (int): Count used when signing an image
+ version (int): Image version (Optional)
+ oemflags (int): Optional 16 bit OEM flags
+
+ Returns:
+ str: Tool output
+ """
+ args = [
+ f'--index={image_index}',
+ f'--guid={image_guid}',
+ f'--instance={hardware_instance}'
+ ]
+
+ if version:
+ args += [f'--fw-version={version}']
+ if oemflags:
+ args += [f'--capoemflag={oemflags}']
+ if priv_key and pub_key:
+ args += [
+ f'--monotonic-count={monotonic_count}',
+ f'--private-key={priv_key}',
+ f'--certificate={pub_key}'
+ ]
+
+ args += [
+ payload,
+ output_fname
+ ]
+
+ return self.run_cmd(*args)
+
+ def generate_empty_capsule(self, image_guid, output_fname,
+ accept=True):
+ """Generate empty capsules for FWU A/B updates
+
+ Args:
+ image_guid (str): GUID used for identifying the image
+ in case of an accept capsule
+ output_fname (str): Path to the output capsule file
+ accept (bool): Generate an accept capsule,
+ else a revert capsule
+
+ Returns:
+ str: Tool output
+ """
+ if accept:
+ args = [
+ f'--guid={image_guid}',
+ '--fw-accept'
+ ]
+ else:
+ args = [ '--fw-revert' ]
+
+ args += [ output_fname ]
+
+ return self.run_cmd(*args)
+
+ def fetch(self, method):
+ """Fetch handler for mkeficapsule
+
+ This builds the tool from source
+
+ Returns:
+ tuple:
+ str: Filename of fetched file to copy to a suitable directory
+ str: Name of temp directory to remove, or None
+ """
+ if method != bintool.FETCH_BUILD:
+ return None
+
+ cmd = ['tools-only_defconfig', 'tools']
+ result = self.build_from_git(
+ 'https://source.denx.de/u-boot/u-boot.git',
+ cmd,
+ 'tools/mkeficapsule')
+ return result
diff --git a/tools/binman/btool/openssl.py b/tools/binman/btool/openssl.py
index aad3b61..7ee2683 100644
--- a/tools/binman/btool/openssl.py
+++ b/tools/binman/btool/openssl.py
@@ -155,6 +155,7 @@
C, ST, L, O, OU, CN and emailAddress
cert_type (int): Certification type
bootcore (int): Booting core
+ bootcore_opts(int): Booting core option, lockstep (0) or split (2) mode
load_addr (int): Load address of image
sha (int): Hash function
@@ -225,7 +226,7 @@
imagesize_sbl, hashval_sbl, load_addr_sysfw, imagesize_sysfw,
hashval_sysfw, load_addr_sysfw_data, imagesize_sysfw_data,
hashval_sysfw_data, sysfw_inner_cert_ext_boot_block,
- dm_data_ext_boot_block):
+ dm_data_ext_boot_block, bootcore_opts):
"""Create a certificate
Args:
@@ -241,6 +242,7 @@
bootcore (int): Booting core
load_addr (int): Load address of image
sha (int): Hash function
+ bootcore_opts (int): Booting core option, lockstep (0) or split (2) mode
Returns:
str: Tool output
@@ -285,7 +287,7 @@
[sbl]
compType = INTEGER:1
bootCore = INTEGER:16
-compOpts = INTEGER:0
+compOpts = INTEGER:{bootcore_opts}
destAddr = FORMAT:HEX,OCT:{load_addr:08x}
compSize = INTEGER:{imagesize_sbl}
shaType = OID:{sha_type}
diff --git a/tools/binman/cbfs_util.py b/tools/binman/cbfs_util.py
index fc56b40..671cafa 100644
--- a/tools/binman/cbfs_util.py
+++ b/tools/binman/cbfs_util.py
@@ -42,27 +42,24 @@
FILE_HEADER_FORMAT = b'>8sIIII'
FILE_HEADER_LEN = 0x18
FILE_MAGIC = b'LARCHIVE'
-FILENAME_ALIGN = 16 # Filename lengths are aligned to this
+ATTRIBUTE_ALIGN = 4 # All attribute sizes must be divisible by this
-# A stage header containing information about 'stage' files
+# A stage-header attribute containing information about 'stage' files
# Yes this is correct: this header is in litte-endian format
-STAGE_FORMAT = '<IQQII'
-STAGE_LEN = 0x1c
+ATTR_STAGE_FORMAT = '>IIQII'
+ATTR_STAGE_LEN = 0x18
# An attribute describring the compression used in a file
ATTR_COMPRESSION_FORMAT = '>IIII'
ATTR_COMPRESSION_LEN = 0x10
# Attribute tags
-# Depending on how the header was initialised, it may be backed with 0x00 or
-# 0xff. Support both.
-FILE_ATTR_TAG_UNUSED = 0
-FILE_ATTR_TAG_UNUSED2 = 0xffffffff
FILE_ATTR_TAG_COMPRESSION = 0x42435a4c
FILE_ATTR_TAG_HASH = 0x68736148
FILE_ATTR_TAG_POSITION = 0x42435350 # PSCB
FILE_ATTR_TAG_ALIGNMENT = 0x42434c41 # ALCB
FILE_ATTR_TAG_PADDING = 0x47444150 # PDNG
+FILE_ATTR_TAG_STAGEHEADER = 0x53746748 # StgH
# This is 'the size of bootblock reserved in firmware image (cbfs.txt)'
# Not much more info is available, but we set it to 4, due to this comment in
@@ -100,7 +97,8 @@
# File types. Only supported ones are included here
TYPE_CBFSHEADER = 0x02 # Master header, HEADER_FORMAT
-TYPE_STAGE = 0x10 # Stage, holding an executable, see STAGE_FORMAT
+TYPE_LEGACY_STAGE = 0x10 # Stage, holding an executable
+TYPE_STAGE = 0x11 # New-type stage with ATTR_STAGE_FORMAT
TYPE_RAW = 0x50 # Raw file, possibly compressed
TYPE_EMPTY = 0xffffffff # Empty data
@@ -190,7 +188,7 @@
String with required padding (at least one 0x00 byte) at the end
"""
val = tools.to_bytes(instr)
- pad_len = align_int(len(val) + 1, FILENAME_ALIGN)
+ pad_len = align_int(len(val) + 1, ATTRIBUTE_ALIGN)
return val + tools.get_bytes(0, pad_len - len(val))
@@ -304,7 +302,7 @@
CbfsFile object containing the file information
"""
cfile = CbfsFile('', TYPE_EMPTY, b'', None)
- cfile.size = space_to_use - FILE_HEADER_LEN - FILENAME_ALIGN
+ cfile.size = space_to_use - FILE_HEADER_LEN - ATTRIBUTE_ALIGN
cfile.erase_byte = erase_byte
return cfile
@@ -331,9 +329,10 @@
name = _pack_string(self.name)
hdr_len = len(name) + FILE_HEADER_LEN
if self.ftype == TYPE_STAGE:
- pass
+ hdr_len += ATTR_STAGE_LEN
elif self.ftype == TYPE_RAW:
- hdr_len += ATTR_COMPRESSION_LEN
+ if self.compress:
+ hdr_len += ATTR_COMPRESSION_LEN
elif self.ftype == TYPE_EMPTY:
pass
else:
@@ -359,9 +358,9 @@
data = self.data
if self.ftype == TYPE_STAGE:
elf_data = elf.DecodeElf(data, self.base_address)
- content = struct.pack(STAGE_FORMAT, self.compress,
- elf_data.entry, elf_data.load,
- len(elf_data.data), elf_data.memsize)
+ attr = struct.pack(ATTR_STAGE_FORMAT, FILE_ATTR_TAG_STAGEHEADER,
+ ATTR_STAGE_LEN, elf_data.load,
+ elf_data.entry - elf_data.load, elf_data.memsize)
data = elf_data.data
elif self.ftype == TYPE_RAW:
orig_data = data
@@ -369,9 +368,11 @@
data = self.comp_bintool.compress(orig_data)
self.memlen = len(orig_data)
self.data_len = len(data)
- attr = struct.pack(ATTR_COMPRESSION_FORMAT,
- FILE_ATTR_TAG_COMPRESSION, ATTR_COMPRESSION_LEN,
- self.compress, self.memlen)
+ if self.compress:
+ attr = struct.pack(ATTR_COMPRESSION_FORMAT,
+ FILE_ATTR_TAG_COMPRESSION,
+ ATTR_COMPRESSION_LEN, self.compress,
+ self.memlen)
elif self.ftype == TYPE_EMPTY:
data = tools.get_bytes(self.erase_byte, self.size)
else:
@@ -391,6 +392,8 @@
raise ValueError("Internal error: CBFS file '%s': Requested offset %#x but current output position is %#x" %
(self.name, self.cbfs_offset, offset))
pad = tools.get_bytes(pad_byte, pad_len)
+ if attr_pos:
+ attr_pos += pad_len
hdr_len += pad_len
# This is the offset of the start of the file's data,
@@ -405,9 +408,9 @@
if expected_len != actual_len: # pragma: no cover
# Test coverage of this is not available since this should never
# happen. It probably indicates that get_header_len() is broken.
- raise ValueError("Internal error: CBFS file '%s': Expected headers of %#x bytes, got %#d" %
+ raise ValueError("Internal error: CBFS file '%s': Expected headers of %#x bytes, got %#x" %
(self.name, expected_len, actual_len))
- return hdr + name + attr + pad + content + data, hdr_len
+ return hdr + name + pad + attr + content + data, hdr_len
class CbfsWriter(object):
@@ -453,6 +456,9 @@
self._arch = arch
self._bootblock_size = 0
self._erase_byte = 0xff
+
+ # Small padding to align a file uses 0
+ self._small_pad_byte = 0
self._align = ENTRY_ALIGN
self._add_fileheader = False
if self._arch == ARCHITECTURE_X86:
@@ -474,7 +480,7 @@
self._bootblock_size, self._align)
self._hdr_at_start = True
- def _skip_to(self, fd, offset):
+ def _skip_to(self, fd, offset, pad_byte):
"""Write out pad bytes until a given offset
Args:
@@ -484,16 +490,16 @@
if fd.tell() > offset:
raise ValueError('No space for data before offset %#x (current offset %#x)' %
(offset, fd.tell()))
- fd.write(tools.get_bytes(self._erase_byte, offset - fd.tell()))
+ fd.write(tools.get_bytes(pad_byte, offset - fd.tell()))
- def _pad_to(self, fd, offset):
+ def _pad_to(self, fd, offset, pad_byte):
"""Write out pad bytes and/or an empty file until a given offset
Args:
fd: File objext to write to
offset: Offset to write to
"""
- self._align_to(fd, self._align)
+ self._align_to(fd, self._align, pad_byte)
upto = fd.tell()
if upto > offset:
raise ValueError('No space for data before pad offset %#x (current offset %#x)' %
@@ -502,9 +508,9 @@
if todo:
cbf = CbfsFile.empty(todo, self._erase_byte)
fd.write(cbf.get_data_and_offset()[0])
- self._skip_to(fd, offset)
+ self._skip_to(fd, offset, pad_byte)
- def _align_to(self, fd, align):
+ def _align_to(self, fd, align, pad_byte):
"""Write out pad bytes until a given alignment is reached
This only aligns if the resulting output would not reach the end of the
@@ -518,7 +524,7 @@
"""
offset = align_int(fd.tell(), align)
if offset < self._size:
- self._skip_to(fd, offset)
+ self._skip_to(fd, offset, pad_byte)
def add_file_stage(self, name, data, cbfs_offset=None):
"""Add a new stage file to the CBFS
@@ -568,7 +574,7 @@
raise ValueError('No space for header at offset %#x (current offset %#x)' %
(self._header_offset, fd.tell()))
if not add_fileheader:
- self._pad_to(fd, self._header_offset)
+ self._pad_to(fd, self._header_offset, self._erase_byte)
hdr = struct.pack(HEADER_FORMAT, HEADER_MAGIC, HEADER_VERSION2,
self._size, self._bootblock_size, self._align,
self._contents_offset, self._arch, 0xffffffff)
@@ -580,7 +586,7 @@
fd.write(name)
self._header_offset = fd.tell()
fd.write(hdr)
- self._align_to(fd, self._align)
+ self._align_to(fd, self._align, self._erase_byte)
else:
fd.write(hdr)
@@ -597,24 +603,26 @@
# THe header can go at the start in some cases
if self._hdr_at_start:
self._write_header(fd, add_fileheader=self._add_fileheader)
- self._skip_to(fd, self._contents_offset)
+ self._skip_to(fd, self._contents_offset, self._erase_byte)
# Write out each file
for cbf in self._files.values():
# Place the file at its requested place, if any
offset = cbf.calc_start_offset()
if offset is not None:
- self._pad_to(fd, align_int_down(offset, self._align))
+ self._pad_to(fd, align_int_down(offset, self._align),
+ self._erase_byte)
pos = fd.tell()
- data, data_offset = cbf.get_data_and_offset(pos, self._erase_byte)
+ data, data_offset = cbf.get_data_and_offset(pos,
+ self._small_pad_byte)
fd.write(data)
- self._align_to(fd, self._align)
+ self._align_to(fd, self._align, self._erase_byte)
cbf.calced_cbfs_offset = pos + data_offset
if not self._hdr_at_start:
self._write_header(fd, add_fileheader=self._add_fileheader)
# Pad to the end and write a pointer to the CBFS master header
- self._pad_to(fd, self._base_address or self._size - 4)
+ self._pad_to(fd, self._base_address or self._size - 4, self._erase_byte)
rel_offset = self._header_offset - self._size
fd.write(struct.pack('<I', rel_offset & 0xffffffff))
@@ -734,26 +742,28 @@
print('name', name)
# If there are attribute headers present, read those
- compress = self._read_attr(fd, file_pos, attr, offset)
- if compress is None:
+ attrs = self._read_attr(fd, file_pos, attr, offset)
+ if attrs is None:
return False
# Create the correct CbfsFile object depending on the type
cfile = None
cbfs_offset = file_pos + offset
fd.seek(cbfs_offset, io.SEEK_SET)
+ if DEBUG:
+ print(f'ftype {ftype:x}')
if ftype == TYPE_CBFSHEADER:
self._read_header(fd)
elif ftype == TYPE_STAGE:
- data = fd.read(STAGE_LEN)
cfile = CbfsFile.stage(self.stage_base_address, name, b'',
cbfs_offset)
- (cfile.compress, cfile.entry, cfile.load, cfile.data_len,
- cfile.memlen) = struct.unpack(STAGE_FORMAT, data)
- cfile.data = fd.read(cfile.data_len)
+ cfile.load, entry_offset, cfile.memlen = attrs
+ cfile.entry = cfile.load + entry_offset
+ cfile.data = fd.read(cfile.memlen)
+ cfile.data_len = cfile.memlen
elif ftype == TYPE_RAW:
data = fd.read(size)
- cfile = CbfsFile.raw(name, data, cbfs_offset, compress)
+ cfile = CbfsFile.raw(name, data, cbfs_offset, attrs)
cfile.decompress()
if DEBUG:
print('data', data)
@@ -777,8 +787,8 @@
"""Read attributes from the file
CBFS files can have attributes which are things that cannot fit into the
- header. The only attributes currently supported are compression and the
- unused tag.
+ header. The only attributes currently supported are compression, stage
+ header and the unused tag
Args:
fd: File to read from
@@ -788,11 +798,16 @@
attributes)
Returns:
- Compression to use for the file (COMPRESS_...)
+ Either:
+ Compression to use for the file (COMPRESS_...)
+ tuple containing stage info:
+ load address
+ entry offset
+ memory size
"""
- compress = COMPRESS_NONE
+ attrs = None
if not attr:
- return compress
+ return COMPRESS_NONE
attr_size = offset - attr
fd.seek(file_pos + attr, io.SEEK_SET)
while attr_size:
@@ -807,12 +822,15 @@
# We don't currently use this information
atag, alen, compress, _decomp_size = struct.unpack(
ATTR_COMPRESSION_FORMAT, data)
- elif atag == FILE_ATTR_TAG_UNUSED2:
- break
+ attrs = compress
+ elif atag == FILE_ATTR_TAG_STAGEHEADER:
+ atag, alen, load, entry_offset, memsize = struct.unpack(
+ ATTR_STAGE_FORMAT, data)
+ attrs = (load, entry_offset, memsize)
else:
print('Unknown attribute tag %x' % atag)
attr_size -= len(data)
- return compress
+ return attrs
def _read_header(self, fd):
"""Read the master header
@@ -843,7 +861,8 @@
def _read_string(cls, fd):
"""Read a string from a file
- This reads a string and aligns the data to the next alignment boundary
+ This reads a string and aligns the data to the next alignment boundary.
+ The string must be nul-terminated
Args:
fd: File to read from
@@ -854,8 +873,8 @@
"""
val = b''
while True:
- data = fd.read(FILENAME_ALIGN)
- if len(data) < FILENAME_ALIGN:
+ data = fd.read(ATTRIBUTE_ALIGN)
+ if len(data) < ATTRIBUTE_ALIGN:
return None
pos = data.find(b'\0')
if pos == -1:
diff --git a/tools/binman/cbfs_util_test.py b/tools/binman/cbfs_util_test.py
index ee951d1..4c415b7 100755
--- a/tools/binman/cbfs_util_test.py
+++ b/tools/binman/cbfs_util_test.py
@@ -96,7 +96,7 @@
self.assertEqual(arch, cbfs.arch)
return cbfs
- def _check_uboot(self, cbfs, ftype=cbfs_util.TYPE_RAW, offset=0x38,
+ def _check_uboot(self, cbfs, ftype=cbfs_util.TYPE_RAW, offset=0x20,
data=U_BOOT_DATA, cbfs_offset=None):
"""Check that the U-Boot file is as expected
@@ -122,7 +122,7 @@
self.assertEqual(len(data), cfile.memlen)
return cfile
- def _check_dtb(self, cbfs, offset=0x38, data=U_BOOT_DTB_DATA,
+ def _check_dtb(self, cbfs, offset=0x24, data=U_BOOT_DTB_DATA,
cbfs_offset=None):
"""Check that the U-Boot dtb file is as expected
@@ -391,7 +391,7 @@
cbfs_util.DEBUG = True
with test_util.capture_sys_output() as (stdout, _stderr):
cbfs_util.CbfsReader(data)
- self.assertEqual('name u-boot\ndata %s\n' % U_BOOT_DATA,
+ self.assertEqual('name u-boot\nftype 50\ndata %s\n' % U_BOOT_DATA,
stdout.getvalue())
finally:
cbfs_util.DEBUG = False
@@ -437,8 +437,9 @@
pos = fd.tell()
# Create a new CBFS with only the first 4 bytes of the compression tag,
- # then try to read the file
- tag_pos = pos + cbfs_util.FILE_HEADER_LEN + cbfs_util.FILENAME_ALIGN
+ # then try to read the file. Note that the tag gets pushed out 4 bytes
+ tag_pos = (4 + pos + cbfs_util.FILE_HEADER_LEN +
+ cbfs_util.ATTRIBUTE_ALIGN)
newdata = data[:tag_pos + 4]
with test_util.capture_sys_output() as (stdout, _stderr):
with io.BytesIO(newdata) as fd:
@@ -474,7 +475,7 @@
self._compare_expected_cbfs(data, cbfs_fname)
def test_cbfs_stage(self):
- """Tests handling of a Coreboot Filesystem (CBFS)"""
+ """Tests handling of a CBFS stage"""
if not elf.ELF_TOOLS:
self.skipTest('Python elftools not available')
elf_fname = os.path.join(self._indir, 'cbfs-stage.elf')
@@ -489,7 +490,7 @@
load = 0xfef20000
entry = load + 2
- cfile = self._check_uboot(cbfs, cbfs_util.TYPE_STAGE, offset=0x28,
+ cfile = self._check_uboot(cbfs, cbfs_util.TYPE_STAGE, offset=0x38,
data=U_BOOT_DATA + U_BOOT_DTB_DATA)
self.assertEqual(entry, cfile.entry)
@@ -520,7 +521,7 @@
self.assertIn('u-boot', cbfs.files)
cfile = cbfs.files['u-boot']
self.assertEqual(cfile.name, 'u-boot')
- self.assertEqual(cfile.offset, 56)
+ self.assertEqual(cfile.offset, 0x30)
self.assertEqual(cfile.data, COMPRESS_DATA)
self.assertEqual(cfile.ftype, cbfs_util.TYPE_RAW)
self.assertEqual(cfile.compress, cbfs_util.COMPRESS_LZ4)
@@ -529,7 +530,7 @@
self.assertIn('u-boot-dtb', cbfs.files)
cfile = cbfs.files['u-boot-dtb']
self.assertEqual(cfile.name, 'u-boot-dtb')
- self.assertEqual(cfile.offset, 56)
+ self.assertEqual(cfile.offset, 0x34)
self.assertEqual(cfile.data, COMPRESS_DATA)
self.assertEqual(cfile.ftype, cbfs_util.TYPE_RAW)
self.assertEqual(cfile.compress, cbfs_util.COMPRESS_LZMA)
@@ -598,8 +599,8 @@
data = cbw.get_data()
cbfs = cbfs_util.CbfsReader(data)
- self.assertEqual(0x38, cbfs.files['u-boot'].cbfs_offset)
- self.assertEqual(0x78, cbfs.files['u-boot-dtb'].cbfs_offset)
+ self.assertEqual(0x20, cbfs.files['u-boot'].cbfs_offset)
+ self.assertEqual(0x64, cbfs.files['u-boot-dtb'].cbfs_offset)
if __name__ == '__main__':
diff --git a/tools/binman/control.py b/tools/binman/control.py
index c6d3205..2f00279 100644
--- a/tools/binman/control.py
+++ b/tools/binman/control.py
@@ -858,6 +858,8 @@
data = state.GetFdtForEtype('u-boot-dtb').GetContents()
elf.UpdateFile(*elf_params, data)
+ bintool.Bintool.set_missing_list(None)
+
# This can only be True if -M is provided, since otherwise binman
# would have raised an error already
if invalid:
diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst
index e7dfe6b..61de7f1 100644
--- a/tools/binman/entries.rst
+++ b/tools/binman/entries.rst
@@ -1,5 +1,5 @@
Binman Entry Documentation
-===========================
+==========================
This file describes the entry types supported by binman. These entry types can
be placed in an image one by one to build up a final firmware image. It is
@@ -468,6 +468,114 @@
+.. _etype_efi_capsule:
+
+Entry: capsule: Entry for generating EFI Capsule files
+------------------------------------------------------
+
+The parameters needed for generation of the capsules can be provided
+as properties in the entry.
+
+Properties / Entry arguments:
+ - image-index: Unique number for identifying corresponding
+ payload image. Number between 1 and descriptor count, i.e.
+ the total number of firmware images that can be updated. Mandatory
+ property.
+ - image-guid: Image GUID which will be used for identifying the
+ updatable image on the board. Mandatory property.
+ - hardware-instance: Optional number for identifying unique
+ hardware instance of a device in the system. Default value of 0
+ for images where value is not to be used.
+ - fw-version: Value of image version that can be put on the capsule
+ through the Firmware Management Protocol(FMP) header.
+ - monotonic-count: Count used when signing an image.
+ - private-key: Path to PEM formatted .key private key file. Mandatory
+ property for generating signed capsules.
+ - public-key-cert: Path to PEM formatted .crt public key certificate
+ file. Mandatory property for generating signed capsules.
+ - oem-flags - OEM flags to be passed through capsule header.
+
+ Since this is a subclass of Entry_section, all properties of the parent
+ class also apply here. Except for the properties stated as mandatory, the
+ rest of the properties are optional.
+
+For more details on the description of the capsule format, and the capsule
+update functionality, refer Section 8.5 and Chapter 23 in the `UEFI
+specification`_.
+
+The capsule parameters like image index and image GUID are passed as
+properties in the entry. The payload to be used in the capsule is to be
+provided as a subnode of the capsule entry.
+
+A typical capsule entry node would then look something like this::
+
+ capsule {
+ type = "efi-capsule";
+ image-index = <0x1>;
+ /* Image GUID for testing capsule update */
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+ hardware-instance = <0x0>;
+ private-key = "path/to/the/private/key";
+ public-key-cert = "path/to/the/public-key-cert";
+ oem-flags = <0x8000>;
+
+ u-boot {
+ };
+ };
+
+In the above example, the capsule payload is the U-Boot image. The
+capsule entry would read the contents of the payload and put them
+into the capsule. Any external file can also be specified as the
+payload using the blob-ext subnode.
+
+.. _`UEFI specification`: https://uefi.org/sites/default/files/resources/UEFI_Spec_2_10_Aug29.pdf
+
+
+
+.. _etype_efi_empty_capsule:
+
+Entry: efi-empty-capsule: Entry for generating EFI Empty Capsule files
+----------------------------------------------------------------------
+
+The parameters needed for generation of the empty capsules can
+be provided as properties in the entry.
+
+Properties / Entry arguments:
+ - image-guid: Image GUID which will be used for identifying the
+ updatable image on the board. Mandatory for accept capsule.
+ - capsule-type - String to indicate type of capsule to generate. Valid
+ values are 'accept' and 'revert'.
+
+For more details on the description of the capsule format, and the capsule
+update functionality, refer Section 8.5 and Chapter 23 in the `UEFI
+specification`_. For more information on the empty capsule, refer the
+sections 2.3.2 and 2.3.3 in the `Dependable Boot specification`_.
+
+A typical accept empty capsule entry node would then look something
+like this::
+
+ empty-capsule {
+ type = "efi-empty-capsule";
+ /* GUID of the image being accepted */
+ image-type-id = SANDBOX_UBOOT_IMAGE_GUID;
+ capsule-type = "accept";
+ };
+
+A typical revert empty capsule entry node would then look something
+like this::
+
+ empty-capsule {
+ type = "efi-empty-capsule";
+ capsule-type = "revert";
+ };
+
+The empty capsules do not have any input payload image.
+
+.. _`UEFI specification`: https://uefi.org/sites/default/files/resources/UEFI_Spec_2_10_Aug29.pdf
+.. _`Dependable Boot specification`: https://git.codelinaro.org/linaro/dependable-boot/mbfw/uploads/6f7ddfe3be24e18d4319e108a758d02e/mbfw.pdf
+
+
+
.. _etype_encrypted:
Entry: encrypted: Externally built encrypted binary blob
@@ -1836,6 +1944,7 @@
- core: core on which bootloader runs, valid cores are 'secure' and 'public'
- content: phandle of SPL in case of legacy bootflow or phandles of component binaries
in case of combined bootflow
+ - core-opts (optional): lockstep (0) or split (2) mode set to 0 by default
The following properties are only for generating a combined bootflow binary:
- sysfw-inner-cert: boolean if binary contains sysfw inner certificate
diff --git a/tools/binman/etype/efi_capsule.py b/tools/binman/etype/efi_capsule.py
new file mode 100644
index 0000000..e320371
--- /dev/null
+++ b/tools/binman/etype/efi_capsule.py
@@ -0,0 +1,155 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2023 Linaro Limited
+#
+# Entry-type module for producing a EFI capsule
+#
+
+import os
+
+from binman.entry import Entry
+from binman.etype.section import Entry_section
+from dtoc import fdt_util
+from u_boot_pylib import tools
+
+def get_binman_test_guid(type_str):
+ """Get the test image GUID for binman
+
+ Based on the string passed to the function, return
+ the corresponding GUID.
+
+ Args:
+ type_str: Key value of the type of GUID to look for
+
+ Returns:
+ The actual GUID value (str)
+ """
+ TYPE_TO_GUID = {
+ 'binman-test' : '09d7cf52-0720-4710-91d1-08469b7fe9c8'
+ }
+
+ return TYPE_TO_GUID[type_str]
+
+class Entry_efi_capsule(Entry_section):
+ """Generate EFI capsules
+
+ The parameters needed for generation of the capsules can
+ be provided as properties in the entry.
+
+ Properties / Entry arguments:
+ - image-index: Unique number for identifying corresponding
+ payload image. Number between 1 and descriptor count, i.e.
+ the total number of firmware images that can be updated. Mandatory
+ property.
+ - image-guid: Image GUID which will be used for identifying the
+ updatable image on the board. Mandatory property.
+ - hardware-instance: Optional number for identifying unique
+ hardware instance of a device in the system. Default value of 0
+ for images where value is not to be used.
+ - fw-version: Value of image version that can be put on the capsule
+ through the Firmware Management Protocol(FMP) header.
+ - monotonic-count: Count used when signing an image.
+ - private-key: Path to PEM formatted .key private key file. Mandatory
+ property for generating signed capsules.
+ - public-key-cert: Path to PEM formatted .crt public key certificate
+ file. Mandatory property for generating signed capsules.
+ - oem-flags - OEM flags to be passed through capsule header.
+
+ Since this is a subclass of Entry_section, all properties of the parent
+ class also apply here. Except for the properties stated as mandatory, the
+ rest of the properties are optional.
+
+ For more details on the description of the capsule format, and the capsule
+ update functionality, refer Section 8.5 and Chapter 23 in the `UEFI
+ specification`_.
+
+ The capsule parameters like image index and image GUID are passed as
+ properties in the entry. The payload to be used in the capsule is to be
+ provided as a subnode of the capsule entry.
+
+ A typical capsule entry node would then look something like this
+
+ capsule {
+ type = "efi-capsule";
+ image-index = <0x1>;
+ /* Image GUID for testing capsule update */
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+ hardware-instance = <0x0>;
+ private-key = "path/to/the/private/key";
+ public-key-cert = "path/to/the/public-key-cert";
+ oem-flags = <0x8000>;
+
+ u-boot {
+ };
+ };
+
+ In the above example, the capsule payload is the U-Boot image. The
+ capsule entry would read the contents of the payload and put them
+ into the capsule. Any external file can also be specified as the
+ payload using the blob-ext subnode.
+
+ .. _`UEFI specification`: https://uefi.org/sites/default/files/resources/UEFI_Spec_2_10_Aug29.pdf
+ """
+ def __init__(self, section, etype, node):
+ super().__init__(section, etype, node)
+ self.required_props = ['image-index', 'image-guid']
+ self.image_index = 0
+ self.image_guid = ''
+ self.hardware_instance = 0
+ self.monotonic_count = 0
+ self.fw_version = 0
+ self.oem_flags = 0
+ self.private_key = ''
+ self.public_key_cert = ''
+ self.auth = 0
+
+ def ReadNode(self):
+ super().ReadNode()
+
+ self.image_index = fdt_util.GetInt(self._node, 'image-index')
+ self.image_guid = fdt_util.GetString(self._node, 'image-guid')
+ self.fw_version = fdt_util.GetInt(self._node, 'fw-version')
+ self.hardware_instance = fdt_util.GetInt(self._node, 'hardware-instance')
+ self.monotonic_count = fdt_util.GetInt(self._node, 'monotonic-count')
+ self.oem_flags = fdt_util.GetInt(self._node, 'oem-flags')
+
+ self.private_key = fdt_util.GetString(self._node, 'private-key')
+ self.public_key_cert = fdt_util.GetString(self._node, 'public-key-cert')
+ if ((self.private_key and not self.public_key_cert) or (self.public_key_cert and not self.private_key)):
+ self.Raise('Both private key and public key certificate need to be provided')
+ elif not (self.private_key and self.public_key_cert):
+ self.auth = 0
+ else:
+ self.auth = 1
+
+ def BuildSectionData(self, required):
+ private_key = ''
+ public_key_cert = ''
+ if self.auth:
+ if not os.path.isabs(self.private_key):
+ private_key = tools.get_input_filename(self.private_key)
+ if not os.path.isabs(self.public_key_cert):
+ public_key_cert = tools.get_input_filename(self.public_key_cert)
+ data, payload, uniq = self.collect_contents_to_file(
+ self._entries.values(), 'capsule_in')
+ outfile = self._filename if self._filename else 'capsule.%s' % uniq
+ capsule_fname = tools.get_output_filename(outfile)
+ guid = self.image_guid
+ if self.image_guid == "binman-test":
+ guid = get_binman_test_guid('binman-test')
+
+ ret = self.mkeficapsule.generate_capsule(self.image_index,
+ guid,
+ self.hardware_instance,
+ payload,
+ capsule_fname,
+ private_key,
+ public_key_cert,
+ self.monotonic_count,
+ self.fw_version,
+ self.oem_flags)
+ if ret is not None:
+ os.remove(payload)
+ return tools.read_file(capsule_fname)
+
+ def AddBintools(self, btools):
+ self.mkeficapsule = self.AddBintool(btools, 'mkeficapsule')
diff --git a/tools/binman/etype/efi_empty_capsule.py b/tools/binman/etype/efi_empty_capsule.py
new file mode 100644
index 0000000..064bf9a
--- /dev/null
+++ b/tools/binman/etype/efi_empty_capsule.py
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2023 Linaro Limited
+#
+# Entry-type module for producing an empty EFI capsule
+#
+
+import os
+
+from binman.entry import Entry
+from binman.etype.efi_capsule import get_binman_test_guid
+from binman.etype.section import Entry_section
+from dtoc import fdt_util
+from u_boot_pylib import tools
+
+class Entry_efi_empty_capsule(Entry_section):
+ """Generate EFI empty capsules
+
+ The parameters needed for generation of the empty capsules can
+ be provided as properties in the entry.
+
+ Properties / Entry arguments:
+ - image-guid: Image GUID which will be used for identifying the
+ updatable image on the board. Mandatory for accept capsule.
+ - capsule-type - String to indicate type of capsule to generate. Valid
+ values are 'accept' and 'revert'.
+
+ For more details on the description of the capsule format, and the capsule
+ update functionality, refer Section 8.5 and Chapter 23 in the `UEFI
+ specification`_. For more information on the empty capsule, refer the
+ sections 2.3.2 and 2.3.3 in the `Dependable Boot specification`_.
+
+ A typical accept empty capsule entry node would then look something like this
+
+ empty-capsule {
+ type = "efi-empty-capsule";
+ /* GUID of image being accepted */
+ image-type-id = SANDBOX_UBOOT_IMAGE_GUID;
+ capsule-type = "accept";
+ };
+
+ A typical revert empty capsule entry node would then look something like this
+
+ empty-capsule {
+ type = "efi-empty-capsule";
+ capsule-type = "revert";
+ };
+
+ The empty capsules do not have any input payload image.
+
+ .. _`UEFI specification`: https://uefi.org/sites/default/files/resources/UEFI_Spec_2_10_Aug29.pdf
+ .. _`Dependable Boot specification`: https://git.codelinaro.org/linaro/dependable-boot/mbfw/uploads/6f7ddfe3be24e18d4319e108a758d02e/mbfw.pdf
+ """
+ def __init__(self, section, etype, node):
+ super().__init__(section, etype, node)
+ self.required_props = ['capsule-type']
+ self.accept = 0
+ self.revert = 0
+
+ def ReadNode(self):
+ super().ReadNode()
+
+ self.image_guid = fdt_util.GetString(self._node, 'image-guid')
+ self.capsule_type = fdt_util.GetString(self._node, 'capsule-type')
+
+ if self.capsule_type != 'accept' and self.capsule_type != 'revert':
+ self.Raise('capsule-type should be either \'accept\' or \'revert\'')
+
+ if self.capsule_type == 'accept' and not self.image_guid:
+ self.Raise('Image GUID needed for generating accept capsule')
+
+ def BuildSectionData(self, required):
+ uniq = self.GetUniqueName()
+ outfile = self._filename if self._filename else 'capsule.%s' % uniq
+ capsule_fname = tools.get_output_filename(outfile)
+ accept = True if self.capsule_type == 'accept' else False
+ guid = self.image_guid
+ if self.image_guid == "binman-test":
+ guid = get_binman_test_guid('binman-test')
+
+ ret = self.mkeficapsule.generate_empty_capsule(guid, capsule_fname,
+ accept)
+ if ret is not None:
+ return tools.read_file(capsule_fname)
+
+ def AddBintools(self, btools):
+ self.mkeficapsule = self.AddBintool(btools, 'mkeficapsule')
diff --git a/tools/binman/etype/ti_secure_rom.py b/tools/binman/etype/ti_secure_rom.py
index 9a7ac9e..f6fc3f9 100644
--- a/tools/binman/etype/ti_secure_rom.py
+++ b/tools/binman/etype/ti_secure_rom.py
@@ -32,6 +32,7 @@
- core: core on which bootloader runs, valid cores are 'secure' and 'public'
- content: phandle of SPL in case of legacy bootflow or phandles of component binaries
in case of combined bootflow
+ - core-opts (optional): lockstep (0) or split (2) mode set to 0 by default
The following properties are only for generating a combined bootflow binary:
- sysfw-inner-cert: boolean if binary contains sysfw inner certificate
@@ -69,6 +70,7 @@
self.sw_rev = fdt_util.GetInt(self._node, 'sw-rev', 1)
self.sha = fdt_util.GetInt(self._node, 'sha', 512)
self.core = fdt_util.GetString(self._node, 'core', 'secure')
+ self.bootcore_opts = fdt_util.GetInt(self._node, 'core-opts')
self.key_fname = self.GetEntryArgsOrProps([
EntryArg('keyfile', str)], required=True)[0]
if self.combined:
@@ -97,17 +99,19 @@
bytes content of the entry, which is the certificate binary for the
provided data
"""
+ if self.bootcore_opts is None:
+ self.bootcore_opts = 0
+
if self.core == 'secure':
if self.countersign:
self.cert_type = 3
else:
self.cert_type = 2
self.bootcore = 0
- self.bootcore_opts = 32
else:
self.cert_type = 1
self.bootcore = 16
- self.bootcore_opts = 0
+
return super().GetCertificate(required=required, type='rom')
def CombinedGetCertificate(self, required):
@@ -126,6 +130,9 @@
self.num_comps = 3
self.sha_type = SHA_OIDS[self.sha]
+ if self.bootcore_opts is None:
+ self.bootcore_opts = 0
+
# sbl
self.content = fdt_util.GetPhandleList(self._node, 'content-sbl')
input_data_sbl = self.GetContents(required)
diff --git a/tools/binman/etype/x509_cert.py b/tools/binman/etype/x509_cert.py
index d028cfe..fc0bb12 100644
--- a/tools/binman/etype/x509_cert.py
+++ b/tools/binman/etype/x509_cert.py
@@ -136,7 +136,8 @@
imagesize_sysfw_data=self.imagesize_sysfw_data,
hashval_sysfw_data=self.hashval_sysfw_data,
sysfw_inner_cert_ext_boot_block=self.sysfw_inner_cert_ext_boot_block,
- dm_data_ext_boot_block=self.dm_data_ext_boot_block
+ dm_data_ext_boot_block=self.dm_data_ext_boot_block,
+ bootcore_opts=self.bootcore_opts
)
if stdout is not None:
data = tools.read_file(output_fname)
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index 1293e9d..5ace2a8 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -48,6 +48,7 @@
BLOB_DATA = b'89'
ME_DATA = b'0abcd'
VGA_DATA = b'vga'
+EFI_CAPSULE_DATA = b'efi'
U_BOOT_DTB_DATA = b'udtb'
U_BOOT_SPL_DTB_DATA = b'spldtb'
U_BOOT_TPL_DTB_DATA = b'tpldtb'
@@ -119,6 +120,16 @@
TEE_ADDR = 0x5678
+# Firmware Management Protocol(FMP) GUID
+FW_MGMT_GUID = '6dcbd5ed-e82d-4c44-bda1-7194199ad92a'
+# Image GUID specified in the DTS
+CAPSULE_IMAGE_GUID = '09d7cf52-0720-4710-91d1-08469b7fe9c8'
+# Windows cert GUID
+WIN_CERT_TYPE_EFI_GUID = '4aafd29d-68df-49ee-8aa9-347d375665a7'
+# Empty capsule GUIDs
+EMPTY_CAPSULE_ACCEPT_GUID = '0c996046-bcc0-4d04-85ec-e1fcedf1c6f8'
+EMPTY_CAPSULE_REVERT_GUID = 'acd58b4b-c0e8-475f-99b5-6b3f7e07aaf0'
+
class TestFunctional(unittest.TestCase):
"""Functional tests for binman
@@ -215,6 +226,7 @@
TestFunctional._MakeInputFile('scp.bin', SCP_DATA)
TestFunctional._MakeInputFile('rockchip-tpl.bin', ROCKCHIP_TPL_DATA)
TestFunctional._MakeInputFile('ti_unsecure.bin', TI_UNSECURE_DATA)
+ TestFunctional._MakeInputFile('capsule_input.bin', EFI_CAPSULE_DATA)
# Add a few .dtb files for testing
TestFunctional._MakeInputFile('%s/test-fdt1.dtb' % TEST_FDT_SUBDIR,
@@ -2655,12 +2667,12 @@
'cbfs:offset': 0,
'cbfs:size': len(data),
'cbfs:image-pos': 0,
- 'cbfs/u-boot:offset': 0x38,
+ 'cbfs/u-boot:offset': 0x30,
'cbfs/u-boot:uncomp-size': len(U_BOOT_DATA),
- 'cbfs/u-boot:image-pos': 0x38,
- 'cbfs/u-boot-dtb:offset': 0xb8,
+ 'cbfs/u-boot:image-pos': 0x30,
+ 'cbfs/u-boot-dtb:offset': 0xa4,
'cbfs/u-boot-dtb:size': len(U_BOOT_DATA),
- 'cbfs/u-boot-dtb:image-pos': 0xb8,
+ 'cbfs/u-boot-dtb:image-pos': 0xa4,
}, props)
def testCbfsBadType(self):
@@ -2842,7 +2854,7 @@
' u-boot 0 4 u-boot 0',
' section 100 %x section 100' % section_size,
' cbfs 100 400 cbfs 0',
-' u-boot 138 4 u-boot 38',
+' u-boot 120 4 u-boot 20',
' u-boot-dtb 180 105 u-boot-dtb 80 3c9',
' u-boot-dtb 500 %x u-boot-dtb 400 3c9' % fdt_size,
' fdtmap %x 3bd fdtmap %x' %
@@ -7216,5 +7228,191 @@
self.assertRegex(err,
"Image 'image'.*missing bintools.*: bootgen")
+ def _GetCapsuleHeaders(self, data):
+ """Get the capsule header contents
+
+ Args:
+ data: Capsule file contents
+
+ Returns:
+ Dict:
+ key: Capsule Header name (str)
+ value: Header field value (str)
+ """
+ capsule_file = os.path.join(self._indir, 'test.capsule')
+ tools.write_file(capsule_file, data)
+
+ out = tools.run('mkeficapsule', '--dump-capsule', capsule_file)
+ lines = out.splitlines()
+
+ re_line = re.compile(r'^([^:\-\t]*)(?:\t*\s*:\s*(.*))?$')
+ vals = {}
+ for line in lines:
+ mat = re_line.match(line)
+ if mat:
+ vals[mat.group(1)] = mat.group(2)
+
+ return vals
+
+ def _CheckCapsule(self, data, signed_capsule=False, version_check=False,
+ capoemflags=False):
+ fmp_signature = "3153534D" # 'M', 'S', 'S', '1'
+ fmp_size = "00000010"
+ fmp_fw_version = "00000002"
+ capsule_image_index = "00000001"
+ oemflag = "00018000"
+ auth_hdr_revision = "00000200"
+ auth_hdr_cert_type = "00000EF1"
+
+ payload_data_len = len(EFI_CAPSULE_DATA)
+
+ hdr = self._GetCapsuleHeaders(data)
+
+ self.assertEqual(FW_MGMT_GUID.upper(), hdr['EFI_CAPSULE_HDR.CAPSULE_GUID'])
+
+ self.assertEqual(CAPSULE_IMAGE_GUID.upper(),
+ hdr['FMP_CAPSULE_IMAGE_HDR.UPDATE_IMAGE_TYPE_ID'])
+ self.assertEqual(capsule_image_index,
+ hdr['FMP_CAPSULE_IMAGE_HDR.UPDATE_IMAGE_INDEX'])
+
+ if capoemflags:
+ self.assertEqual(oemflag, hdr['EFI_CAPSULE_HDR.FLAGS'])
+
+ if signed_capsule:
+ self.assertEqual(auth_hdr_revision,
+ hdr['EFI_FIRMWARE_IMAGE_AUTH.AUTH_INFO.HDR.wREVISION'])
+ self.assertEqual(auth_hdr_cert_type,
+ hdr['EFI_FIRMWARE_IMAGE_AUTH.AUTH_INFO.HDR.wCERTTYPE'])
+ self.assertEqual(WIN_CERT_TYPE_EFI_GUID.upper(),
+ hdr['EFI_FIRMWARE_IMAGE_AUTH.AUTH_INFO.CERT_TYPE'])
+
+ if version_check:
+ self.assertEqual(fmp_signature,
+ hdr['FMP_PAYLOAD_HDR.SIGNATURE'])
+ self.assertEqual(fmp_size,
+ hdr['FMP_PAYLOAD_HDR.HEADER_SIZE'])
+ self.assertEqual(fmp_fw_version,
+ hdr['FMP_PAYLOAD_HDR.FW_VERSION'])
+
+ self.assertEqual(payload_data_len, int(hdr['Payload Image Size']))
+
+ def _CheckEmptyCapsule(self, data, accept_capsule=False):
+ if accept_capsule:
+ capsule_hdr_guid = EMPTY_CAPSULE_ACCEPT_GUID
+ else:
+ capsule_hdr_guid = EMPTY_CAPSULE_REVERT_GUID
+
+ hdr = self._GetCapsuleHeaders(data)
+
+ self.assertEqual(capsule_hdr_guid.upper(),
+ hdr['EFI_CAPSULE_HDR.CAPSULE_GUID'])
+
+ if accept_capsule:
+ capsule_size = "0000002C"
+ else:
+ capsule_size = "0000001C"
+ self.assertEqual(capsule_size,
+ hdr['EFI_CAPSULE_HDR.CAPSULE_IMAGE_SIZE'])
+
+ if accept_capsule:
+ self.assertEqual(CAPSULE_IMAGE_GUID.upper(), hdr['ACCEPT_IMAGE_GUID'])
+
+ def testCapsuleGen(self):
+ """Test generation of EFI capsule"""
+ data = self._DoReadFile('311_capsule.dts')
+
+ self._CheckCapsule(data)
+
+ def testSignedCapsuleGen(self):
+ """Test generation of EFI capsule"""
+ data = tools.read_file(self.TestFile("key.key"))
+ self._MakeInputFile("key.key", data)
+ data = tools.read_file(self.TestFile("key.pem"))
+ self._MakeInputFile("key.crt", data)
+
+ data = self._DoReadFile('312_capsule_signed.dts')
+
+ self._CheckCapsule(data, signed_capsule=True)
+
+ def testCapsuleGenVersionSupport(self):
+ """Test generation of EFI capsule with version support"""
+ data = self._DoReadFile('313_capsule_version.dts')
+
+ self._CheckCapsule(data, version_check=True)
+
+ def testCapsuleGenSignedVer(self):
+ """Test generation of signed EFI capsule with version information"""
+ data = tools.read_file(self.TestFile("key.key"))
+ self._MakeInputFile("key.key", data)
+ data = tools.read_file(self.TestFile("key.pem"))
+ self._MakeInputFile("key.crt", data)
+
+ data = self._DoReadFile('314_capsule_signed_ver.dts')
+
+ self._CheckCapsule(data, signed_capsule=True, version_check=True)
+
+ def testCapsuleGenCapOemFlags(self):
+ """Test generation of EFI capsule with OEM Flags set"""
+ data = self._DoReadFile('315_capsule_oemflags.dts')
+
+ self._CheckCapsule(data, capoemflags=True)
+
+ def testCapsuleGenKeyMissing(self):
+ """Test that binman errors out on missing key"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('316_capsule_missing_key.dts')
+
+ self.assertIn("Both private key and public key certificate need to be provided",
+ str(e.exception))
+
+ def testCapsuleGenIndexMissing(self):
+ """Test that binman errors out on missing image index"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('317_capsule_missing_index.dts')
+
+ self.assertIn("entry is missing properties: image-index",
+ str(e.exception))
+
+ def testCapsuleGenGuidMissing(self):
+ """Test that binman errors out on missing image GUID"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('318_capsule_missing_guid.dts')
+
+ self.assertIn("entry is missing properties: image-guid",
+ str(e.exception))
+
+ def testCapsuleGenAcceptCapsule(self):
+ """Test generationg of accept EFI capsule"""
+ data = self._DoReadFile('319_capsule_accept.dts')
+
+ self._CheckEmptyCapsule(data, accept_capsule=True)
+
+ def testCapsuleGenRevertCapsule(self):
+ """Test generationg of revert EFI capsule"""
+ data = self._DoReadFile('320_capsule_revert.dts')
+
+ self._CheckEmptyCapsule(data)
+
+ def testCapsuleGenAcceptGuidMissing(self):
+ """Test that binman errors out on missing image GUID for accept capsule"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('321_capsule_accept_missing_guid.dts')
+
+ self.assertIn("Image GUID needed for generating accept capsule",
+ str(e.exception))
+
+ def testCapsuleGenEmptyCapsuleTypeMissing(self):
+ """Test that capsule-type is specified"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('322_empty_capsule_type_missing.dts')
+
+ self.assertIn("entry is missing properties: capsule-type",
+ str(e.exception))
+
+ def testCapsuleGenAcceptOrRevertMissing(self):
+ """Test that both accept and revert capsule are not specified"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('323_capsule_accept_revert_missing.dts')
+
if __name__ == "__main__":
unittest.main()
diff --git a/tools/binman/test/297_ti_secure_rom.dts b/tools/binman/test/297_ti_secure_rom.dts
index d131376..1a3eca9 100644
--- a/tools/binman/test/297_ti_secure_rom.dts
+++ b/tools/binman/test/297_ti_secure_rom.dts
@@ -9,6 +9,7 @@
binman {
ti-secure-rom {
content = <&unsecure_binary>;
+ core-opts = <2>;
};
unsecure_binary: blob-ext {
filename = "ti_unsecure.bin";
diff --git a/tools/binman/test/311_capsule.dts b/tools/binman/test/311_capsule.dts
new file mode 100644
index 0000000..0a62ef8
--- /dev/null
+++ b/tools/binman/test/311_capsule.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ binman {
+ efi-capsule {
+ image-index = <0x1>;
+ /* Image GUID for testing capsule update */
+ image-guid = "binman-test";
+ hardware-instance = <0x0>;
+
+ blob {
+ filename = "capsule_input.bin";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/312_capsule_signed.dts b/tools/binman/test/312_capsule_signed.dts
new file mode 100644
index 0000000..4ab838e
--- /dev/null
+++ b/tools/binman/test/312_capsule_signed.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ binman {
+ efi-capsule {
+ image-index = <0x1>;
+ /* Image GUID for testing capsule update */
+ image-guid = "binman-test";
+ hardware-instance = <0x0>;
+ private-key = "key.key";
+ public-key-cert = "key.crt";
+
+ blob {
+ filename = "capsule_input.bin";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/313_capsule_version.dts b/tools/binman/test/313_capsule_version.dts
new file mode 100644
index 0000000..19e7e83
--- /dev/null
+++ b/tools/binman/test/313_capsule_version.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ binman {
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x2>;
+ /* Image GUID for testing capsule update */
+ image-guid = "binman-test";
+ hardware-instance = <0x0>;
+
+ blob {
+ filename = "capsule_input.bin";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/314_capsule_signed_ver.dts b/tools/binman/test/314_capsule_signed_ver.dts
new file mode 100644
index 0000000..649b8cc
--- /dev/null
+++ b/tools/binman/test/314_capsule_signed_ver.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ binman {
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x2>;
+ /* Image GUID for testing capsule update */
+ image-guid = "binman-test";
+ hardware-instance = <0x0>;
+ private-key = "key.key";
+ public-key-cert = "key.crt";
+
+ blob {
+ filename = "capsule_input.bin";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/315_capsule_oemflags.dts b/tools/binman/test/315_capsule_oemflags.dts
new file mode 100644
index 0000000..45853f6
--- /dev/null
+++ b/tools/binman/test/315_capsule_oemflags.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ binman {
+ efi-capsule {
+ image-index = <0x1>;
+ /* Image GUID for testing capsule update */
+ image-guid = "binman-test";
+ hardware-instance = <0x0>;
+ oem-flags = <0x8000>;
+
+ blob {
+ filename = "capsule_input.bin";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/316_capsule_missing_key.dts b/tools/binman/test/316_capsule_missing_key.dts
new file mode 100644
index 0000000..a14a74e
--- /dev/null
+++ b/tools/binman/test/316_capsule_missing_key.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ binman {
+ efi-capsule {
+ image-index = <0x1>;
+ /* Image GUID for testing capsule update */
+ image-guid = "binman-test";
+ hardware-instance = <0x0>;
+ private-key = "tools/binman/test/key.key";
+
+ blob {
+ filename = "capsule_input.bin";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/317_capsule_missing_index.dts b/tools/binman/test/317_capsule_missing_index.dts
new file mode 100644
index 0000000..99a54d5
--- /dev/null
+++ b/tools/binman/test/317_capsule_missing_index.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ binman {
+ efi-capsule {
+ /* Image GUID for testing capsule update */
+ image-guid = "binman-test";
+ hardware-instance = <0x0>;
+
+ blob {
+ filename = "capsule_input.bin";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/318_capsule_missing_guid.dts b/tools/binman/test/318_capsule_missing_guid.dts
new file mode 100644
index 0000000..85d3317
--- /dev/null
+++ b/tools/binman/test/318_capsule_missing_guid.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ binman {
+ efi-capsule {
+ image-index = <0x1>;
+ hardware-instance = <0x0>;
+
+ blob {
+ filename = "capsule_input.bin";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/319_capsule_accept.dts b/tools/binman/test/319_capsule_accept.dts
new file mode 100644
index 0000000..d48e59f
--- /dev/null
+++ b/tools/binman/test/319_capsule_accept.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ binman {
+ efi-empty-capsule {
+ /* Image GUID for testing capsule update */
+ image-guid = "binman-test";
+ capsule-type = "accept";
+ };
+ };
+};
diff --git a/tools/binman/test/320_capsule_revert.dts b/tools/binman/test/320_capsule_revert.dts
new file mode 100644
index 0000000..bd141ef
--- /dev/null
+++ b/tools/binman/test/320_capsule_revert.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ binman {
+ efi-empty-capsule {
+ capsule-type = "revert";
+ };
+ };
+};
diff --git a/tools/binman/test/321_capsule_accept_missing_guid.dts b/tools/binman/test/321_capsule_accept_missing_guid.dts
new file mode 100644
index 0000000..a0088b1
--- /dev/null
+++ b/tools/binman/test/321_capsule_accept_missing_guid.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ binman {
+ efi-empty-capsule {
+ capsule-type = "accept";
+ };
+ };
+};
diff --git a/tools/binman/test/322_empty_capsule_type_missing.dts b/tools/binman/test/322_empty_capsule_type_missing.dts
new file mode 100644
index 0000000..d356168
--- /dev/null
+++ b/tools/binman/test/322_empty_capsule_type_missing.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ binman {
+ efi-empty-capsule {
+ /* Image GUID for testing capsule update */
+ image-guid = "binman-test";
+ };
+ };
+};
diff --git a/tools/binman/test/323_capsule_accept_revert_missing.dts b/tools/binman/test/323_capsule_accept_revert_missing.dts
new file mode 100644
index 0000000..31268b2
--- /dev/null
+++ b/tools/binman/test/323_capsule_accept_revert_missing.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ binman {
+ efi-empty-capsule {
+ /* Image GUID for testing capsule update */
+ image-guid = "binman-test";
+ capsule-type = "foo";
+ };
+ };
+};
diff --git a/tools/buildman/boards.py b/tools/buildman/boards.py
index eef3f19..341a505 100644
--- a/tools/buildman/boards.py
+++ b/tools/buildman/boards.py
@@ -19,6 +19,7 @@
from buildman import board
from buildman import kconfiglib
+from u_boot_pylib.terminal import print_clear, tprint
### constant variables ###
OUTPUT_FILE = 'boards.cfg'
@@ -863,11 +864,19 @@
Returns:
bool: True if all is well, False if there were warnings
"""
- if not force and output_is_new(output, CONFIG_DIR, '.'):
+ if not force:
if not quiet:
- print(f'{output} is up to date. Nothing to do.')
- return True
+ tprint('\rChecking for Kconfig changes...', newline=False)
+ is_new = output_is_new(output, CONFIG_DIR, '.')
+ print_clear()
+ if is_new:
+ if not quiet:
+ print(f'{output} is up to date. Nothing to do.')
+ return True
+ if not quiet:
+ tprint('\rGenerating board list...', newline=False)
params_list, warnings = self.build_board_list(CONFIG_DIR, '.', jobs)
+ print_clear()
for warn in warnings:
print(warn, file=sys.stderr)
self.format_and_output(params_list, output)
diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index ecbd368..3e42c98 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py
@@ -35,6 +35,10 @@
# which indicates that BREAK_ME has an empty default
RE_NO_DEFAULT = re.compile(b'\((\w+)\) \[] \(NEW\)')
+# Symbol types which appear in the bloat feature (-B). Others are silently
+# dropped when reading in the 'nm' output
+NM_SYMBOL_TYPES = 'tTdDbBr'
+
"""
Theory of Operation
@@ -328,7 +332,7 @@
self._build_period_us = None
self._complete_delay = None
self._next_delay_update = datetime.now()
- self._start_time = datetime.now()
+ self._start_time = None
self._step = step
self._error_lines = 0
self.no_subdirs = no_subdirs
@@ -693,7 +697,7 @@
parts = line.split()
if line and len(parts) == 3:
size, type, name = line.split()
- if type in 'tTdDbB':
+ if type in NM_SYMBOL_TYPES:
# function names begin with '.' on 64-bit powerpc
if '.' in name[1:]:
name = 'static.' + name.split('.')[0]
@@ -1778,6 +1782,7 @@
self._prepare_output_space()
if not self._ide:
tprint('\rStarting build...', newline=False)
+ self._start_time = datetime.now()
self.setup_build(board_selected, commits)
self.process_result(None)
self.thread_exceptions = []
diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py
index 25f460c..6a61f64 100644
--- a/tools/buildman/builderthread.py
+++ b/tools/buildman/builderthread.py
@@ -23,6 +23,9 @@
RETURN_CODE_RETRY = -1
BASE_ELF_FILENAMES = ['u-boot', 'spl/u-boot-spl', 'tpl/u-boot-tpl']
+# Common extensions for images
+COMMON_EXTS = ['.bin', '.rom', '.itb', '.img']
+
def mkdir(dirname, parents=False):
"""Make a directory if it doesn't already exist.
@@ -636,10 +639,11 @@
# Now write the actual build output
if keep_outputs:
- copy_files(
- result.out_dir, build_dir, '',
- ['u-boot*', '*.bin', '*.map', '*.img', 'MLO', 'SPL',
- 'include/autoconf.mk', 'spl/u-boot-spl*'])
+ to_copy = ['u-boot*', '*.map', 'MLO', 'SPL',
+ 'include/autoconf.mk', 'spl/u-boot-spl*',
+ 'tpl/u-boot-tpl*', 'vpl/u-boot-vpl*']
+ to_copy += [f'*{ext}' for ext in COMMON_EXTS]
+ copy_files(result.out_dir, build_dir, '', to_copy)
def _send_result(self, result):
"""Send a result to the builder for processing
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index f2ffb7f..8f6850c 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -621,7 +621,8 @@
if not brds:
brds = get_boards_obj(output_dir, args.regen_board_list,
args.maintainer_check, args.full_check,
- args.threads, args.verbose)
+ args.threads, args.verbose and
+ not args.print_arch and not args.print_prefix)
if isinstance(brds, int):
return brds
diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py
index b050011..79c7c11 100644
--- a/tools/buildman/toolchain.py
+++ b/tools/buildman/toolchain.py
@@ -499,7 +499,7 @@
if arch == 'aarch64':
arch = 'arm64'
base = 'https://www.kernel.org/pub/tools/crosstool/files/bin'
- versions = ['13.1.0', '12.2.0']
+ versions = ['13.2.0', '12.2.0']
links = []
for version in versions:
url = '%s/%s/%s/' % (base, arch, version)
diff --git a/tools/default_image.c b/tools/default_image.c
index 0e49ab3..04bc85b 100644
--- a/tools/default_image.c
+++ b/tools/default_image.c
@@ -15,7 +15,6 @@
#include "imagetool.h"
#include "mkimage.h"
-#include <u-boot/crc.h>
#include <image.h>
#include <tee/optee.h>
diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile
index ff16829..c4a2596 100644
--- a/tools/docker/Dockerfile
+++ b/tools/docker/Dockerfile
@@ -2,7 +2,7 @@
# This Dockerfile is used to build an image containing basic stuff to be used
# to build U-Boot and run our test suites.
-FROM ubuntu:jammy-20230624
+FROM ubuntu:jammy-20230804
MAINTAINER Tom Rini <trini@konsulko.com>
LABEL Description=" This image is for building U-Boot inside a container"
@@ -14,19 +14,19 @@
RUN wget -O - https://apt.llvm.org/llvm-snapshot.gpg.key | apt-key add -
RUN echo deb http://apt.llvm.org/jammy/ llvm-toolchain-jammy-16 main | tee /etc/apt/sources.list.d/llvm.list
-# Manually install the kernel.org "Crosstool" based toolchains for gcc-13.1.0
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-aarch64-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-arc-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-arm-linux-gnueabi.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-i386-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-m68k-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-mips-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-microblaze-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-nios2-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-powerpc-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-riscv64-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-riscv32-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-sh2-linux.tar.xz | tar -C /opt -xJ
+# Manually install the kernel.org "Crosstool" based toolchains for gcc-13.2.0
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-aarch64-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-arc-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-arm-linux-gnueabi.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-i386-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-m68k-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-mips-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-microblaze-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-nios2-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-powerpc-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-riscv64-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-riscv32-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-sh2-linux.tar.xz | tar -C /opt -xJ
# Manually install other toolchains
RUN wget -O - https://github.com/foss-xtensa/toolchain/releases/download/2020.07/x86_64-2020.07-xtensa-dc233c-elf.tar.gz | tar -C /opt -xz
@@ -39,10 +39,10 @@
binutils-dev \
bison \
build-essential \
+ cgpt \
clang-16 \
coreutils \
cpio \
- cppcheck \
curl \
device-tree-compiler \
dosfstools \
@@ -104,7 +104,6 @@
python3-virtualenv \
rpm2cpio \
sbsigntool \
- sloccount \
socat \
softhsm2 \
sparse \
@@ -115,6 +114,8 @@
util-linux \
uuid-dev \
virtualenv \
+ vboot-kernel-utils \
+ vboot-utils \
xxd \
zip \
&& rm -rf /var/lib/apt/lists/*
@@ -134,11 +135,11 @@
mkdir -p /opt/grub && \
./configure --target=aarch64 --with-platform=efi \
CC=gcc \
- TARGET_CC=/opt/gcc-13.1.0-nolibc/aarch64-linux/bin/aarch64-linux-gcc \
- TARGET_OBJCOPY=/opt/gcc-13.1.0-nolibc/aarch64-linux/bin/aarch64-linux-objcopy \
- TARGET_STRIP=/opt/gcc-13.1.0-nolibc/aarch64-linux/bin/aarch64-linux-strip \
- TARGET_NM=/opt/gcc-13.1.0-nolibc/aarch64-linux/bin/aarch64-linux-nm \
- TARGET_RANLIB=/opt/gcc-13.1.0-nolibc/aarch64-linux/bin/aarch64-linux-ranlib && \
+ TARGET_CC=/opt/gcc-13.2.0-nolibc/aarch64-linux/bin/aarch64-linux-gcc \
+ TARGET_OBJCOPY=/opt/gcc-13.2.0-nolibc/aarch64-linux/bin/aarch64-linux-objcopy \
+ TARGET_STRIP=/opt/gcc-13.2.0-nolibc/aarch64-linux/bin/aarch64-linux-strip \
+ TARGET_NM=/opt/gcc-13.2.0-nolibc/aarch64-linux/bin/aarch64-linux-nm \
+ TARGET_RANLIB=/opt/gcc-13.2.0-nolibc/aarch64-linux/bin/aarch64-linux-ranlib && \
make && \
./grub-mkimage -O arm64-efi -o /opt/grub/grubaa64.efi --prefix= -d \
grub-core cat chain configfile echo efinet ext2 fat halt help linux \
@@ -148,11 +149,11 @@
make clean && \
./configure --target=arm --with-platform=efi \
CC=gcc \
- TARGET_CC=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc \
- TARGET_OBJCOPY=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-objcopy \
- TARGET_STRIP=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-strip \
- TARGET_NM=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-nm \
- TARGET_RANLIB=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ranlib && \
+ TARGET_CC=/opt/gcc-13.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc \
+ TARGET_OBJCOPY=/opt/gcc-13.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-objcopy \
+ TARGET_STRIP=/opt/gcc-13.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-strip \
+ TARGET_NM=/opt/gcc-13.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-nm \
+ TARGET_RANLIB=/opt/gcc-13.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ranlib && \
make && \
./grub-mkimage -O arm-efi -o /opt/grub/grubarm.efi --prefix= -d \
grub-core cat chain configfile echo efinet ext2 fat halt help linux \
@@ -162,11 +163,11 @@
make clean && \
./configure --target=riscv64 --with-platform=efi \
CC=gcc \
- TARGET_CC=/opt/gcc-13.1.0-nolibc/riscv64-linux/bin/riscv64-linux-gcc \
- TARGET_OBJCOPY=/opt/gcc-13.1.0-nolibc/riscv64-linux/bin/riscv64-linux-objcopy \
- TARGET_STRIP=/opt/gcc-13.1.0-nolibc/riscv64-linux/bin/riscv64-linux-strip \
- TARGET_NM=/opt/gcc-13.1.0-nolibc/riscv64-linux/bin/riscv64-linux-nm \
- TARGET_RANLIB=/opt/gcc-13.1.0-nolibc/riscv64-linux/bin/riscv64-linux-ranlib && \
+ TARGET_CC=/opt/gcc-13.2.0-nolibc/riscv64-linux/bin/riscv64-linux-gcc \
+ TARGET_OBJCOPY=/opt/gcc-13.2.0-nolibc/riscv64-linux/bin/riscv64-linux-objcopy \
+ TARGET_STRIP=/opt/gcc-13.2.0-nolibc/riscv64-linux/bin/riscv64-linux-strip \
+ TARGET_NM=/opt/gcc-13.2.0-nolibc/riscv64-linux/bin/riscv64-linux-nm \
+ TARGET_RANLIB=/opt/gcc-13.2.0-nolibc/riscv64-linux/bin/riscv64-linux-ranlib && \
make && \
./grub-mkimage -O riscv64-efi -o /opt/grub/grubriscv64.efi --prefix= -d \
grub-core cat chain configfile echo efinet ext2 fat halt help linux \
@@ -246,7 +247,7 @@
# Create the buildman config file
RUN /bin/echo -e "[toolchain]\nroot = /usr" > ~/.buildman
-RUN /bin/echo -e "kernelorg = /opt/gcc-13.1.0-nolibc/*" >> ~/.buildman
+RUN /bin/echo -e "kernelorg = /opt/gcc-13.2.0-nolibc/*" >> ~/.buildman
RUN /bin/echo -e "\n[toolchain-prefix]\nxtensa = /opt/2020.07/xtensa-dc233c-elf/bin/xtensa-dc233c-elf-" >> ~/.buildman;
RUN /bin/echo -e "\n[toolchain-alias]\nsh = sh2" >> ~/.buildman
RUN /bin/echo -e "\nsandbox = x86_64" >> ~/.buildman
diff --git a/tools/eficapsule.h b/tools/eficapsule.h
index 2099a2e..6efd07d 100644
--- a/tools/eficapsule.h
+++ b/tools/eficapsule.h
@@ -22,6 +22,8 @@
#define __aligned(x) __attribute__((__aligned__(x)))
#endif
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
typedef struct {
uint8_t b[16];
} efi_guid_t __aligned(8);
diff --git a/tools/expo.py b/tools/expo.py
index c6eb87a..ea80c70 100755
--- a/tools/expo.py
+++ b/tools/expo.py
@@ -69,7 +69,10 @@
def run_expo(args):
"""Run the expo program"""
- ids = calc_ids(args.enum_fname)
+ fname = args.enum_fname or args.layout
+ ids = calc_ids(fname)
+ if not ids:
+ print(f"Warning: No enum ID values found in file '{fname}'")
indata = tools.read_file(args.layout)
@@ -88,10 +91,10 @@
with open('/tmp/asc', 'wb') as outf:
outf.write(data)
- proc = subprocess.run('dtc', input=data, capture_output=True, check=True)
+ proc = subprocess.run('dtc', input=data, capture_output=True)
edtb = proc.stdout
if proc.stderr:
- print(proc.stderr)
+ print(f"Devicetree compiler error:\n{proc.stderr.decode('utf-8')}")
return 1
tools.write_file(args.outfile, edtb)
return 0
@@ -109,11 +112,13 @@
args is a list of string arguments
"""
parser = argparse.ArgumentParser()
+ parser.add_argument('-D', '--debug', action='store_true',
+ help='Enable full debug traceback')
parser.add_argument('-e', '--enum-fname', type=str,
- help='C file containing enum declaration for expo items')
- parser.add_argument('-l', '--layout', type=str,
- help='Devicetree file source .dts for expo layout')
- parser.add_argument('-o', '--outfile', type=str,
+ help='.dts or C file containing enum declaration for expo items')
+ parser.add_argument('-l', '--layout', type=str, required=True,
+ help='Devicetree file source .dts for expo layout (and perhaps enums)')
+ parser.add_argument('-o', '--outfile', type=str, required=True,
help='Filename to write expo layout dtb')
return parser.parse_args(argv)
@@ -122,6 +127,9 @@
"""Start the expo program"""
args = parse_args(sys.argv[1:])
+ if not args.debug:
+ sys.tracebacklimit = 0
+
ret_code = run_expo(args)
sys.exit(ret_code)
diff --git a/tools/fit_image.c b/tools/fit_image.c
index ecc282a..cd17149 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -494,7 +494,7 @@
{
void *buf = NULL;
int buf_ptr;
- int fit_size, new_size;
+ int fit_size, unpadded_size, new_size, pad_boundary;
int fd;
struct stat sbuf;
void *fdt;
@@ -561,9 +561,13 @@
/* Pack the FDT and place the data after it */
fdt_pack(fdt);
- new_size = fdt_totalsize(fdt);
- new_size = ALIGN(new_size, align_size);
+ unpadded_size = fdt_totalsize(fdt);
+ new_size = ALIGN(unpadded_size, align_size);
fdt_set_totalsize(fdt, new_size);
+ if (unpadded_size < fit_size) {
+ pad_boundary = new_size < fit_size ? new_size : fit_size;
+ memset(fdt + unpadded_size, 0, pad_boundary - unpadded_size);
+ }
debug("Size reduced from %x to %x\n", fit_size, fdt_totalsize(fdt));
debug("External data size %x\n", buf_ptr);
munmap(fdt, sbuf.st_size);
@@ -613,6 +617,8 @@
static int fit_import_data(struct image_tool_params *params, const char *fname)
{
void *fdt, *old_fdt;
+ void *data = NULL;
+ const char *ext_data_prop = NULL;
int fit_size, new_size, size, data_base;
int fd;
struct stat sbuf;
@@ -656,14 +662,28 @@
int buf_ptr;
int len;
- buf_ptr = fdtdec_get_int(fdt, node, "data-offset", -1);
- len = fdtdec_get_int(fdt, node, "data-size", -1);
- if (buf_ptr == -1 || len == -1)
+ /*
+ * FIT_DATA_OFFSET_PROP and FIT_DATA_POSITION_PROP are never both present,
+ * but if they are, prefer FIT_DATA_OFFSET_PROP as it was there first
+ */
+ buf_ptr = fdtdec_get_int(fdt, node, FIT_DATA_POSITION_PROP, -1);
+ if (buf_ptr != -1) {
+ ext_data_prop = FIT_DATA_POSITION_PROP;
+ data = old_fdt + buf_ptr;
+ }
+ buf_ptr = fdtdec_get_int(fdt, node, FIT_DATA_OFFSET_PROP, -1);
+ if (buf_ptr != -1) {
+ ext_data_prop = FIT_DATA_OFFSET_PROP;
+ data = old_fdt + data_base + buf_ptr;
+ }
+ len = fdtdec_get_int(fdt, node, FIT_DATA_SIZE_PROP, -1);
+ if (!data || len == -1)
continue;
debug("Importing data size %x\n", len);
- ret = fdt_setprop(fdt, node, "data",
- old_fdt + data_base + buf_ptr, len);
+ ret = fdt_setprop(fdt, node, FIT_DATA_PROP, data, len);
+ ret = fdt_delprop(fdt, node, ext_data_prop);
+
if (ret) {
debug("%s: Failed to write property: %s\n", __func__,
fdt_strerror(ret));
diff --git a/tools/image-host.c b/tools/image-host.c
index f3c61ad..8048476 100644
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -40,9 +40,9 @@
ret = fdt_setprop(fit, noffset, FIT_VALUE_PROP, value, value_len);
if (ret) {
- printf("Can't set hash '%s' property for '%s' node(%s)\n",
- FIT_VALUE_PROP, fit_get_name(fit, noffset, NULL),
- fdt_strerror(ret));
+ fprintf(stderr, "Can't set hash '%s' property for '%s' node(%s)\n",
+ FIT_VALUE_PROP, fit_get_name(fit, noffset, NULL),
+ fdt_strerror(ret));
return ret == -FDT_ERR_NOSPACE ? -ENOSPC : -EIO;
}
@@ -74,21 +74,23 @@
node_name = fit_get_name(fit, noffset, NULL);
if (fit_image_hash_get_algo(fit, noffset, &algo)) {
- printf("Can't get hash algo property for '%s' hash node in '%s' image node\n",
- node_name, image_name);
+ fprintf(stderr,
+ "Can't get hash algo property for '%s' hash node in '%s' image node\n",
+ node_name, image_name);
return -ENOENT;
}
if (calculate_hash(data, size, algo, value, &value_len)) {
- printf("Unsupported hash algorithm (%s) for '%s' hash node in '%s' image node\n",
- algo, node_name, image_name);
+ fprintf(stderr,
+ "Unsupported hash algorithm (%s) for '%s' hash node in '%s' image node\n",
+ algo, node_name, image_name);
return -EPROTONOSUPPORT;
}
ret = fit_set_hash_value(fit, noffset, value, value_len);
if (ret) {
- printf("Can't set hash value for '%s' hash node in '%s' image node\n",
- node_name, image_name);
+ fprintf(stderr, "Can't set hash value for '%s' hash node in '%s' image node\n",
+ node_name, image_name);
return ret;
}
@@ -172,8 +174,9 @@
node_name = fit_get_name(fit, noffset, NULL);
if (!algo_name) {
if (fit_image_hash_get_algo(fit, noffset, &algo_name)) {
- printf("Can't get algo property for '%s' signature node in '%s' image node\n",
- node_name, image_name);
+ fprintf(stderr,
+ "Can't get algo property for '%s' signature node in '%s' image node\n",
+ node_name, image_name);
return -1;
}
}
@@ -193,8 +196,9 @@
info->require_keys = require_keys;
info->engine_id = engine_id;
if (!info->checksum || !info->crypto) {
- printf("Unsupported signature algorithm (%s) for '%s' signature node in '%s' image node\n",
- algo_name, node_name, image_name);
+ fprintf(stderr,
+ "Unsupported signature algorithm (%s) for '%s' signature node in '%s' image node\n",
+ algo_name, node_name, image_name);
return -1;
}
@@ -243,8 +247,8 @@
region.size = size;
ret = info.crypto->sign(&info, ®ion, 1, &value, &value_len);
if (ret) {
- printf("Failed to sign '%s' signature node in '%s' image node: %d\n",
- node_name, image_name, ret);
+ fprintf(stderr, "Failed to sign '%s' signature node in '%s' image node: %d\n",
+ node_name, image_name, ret);
/* We allow keys to be missing */
if (ret == -ENOENT)
@@ -257,8 +261,9 @@
if (ret) {
if (ret == -FDT_ERR_NOSPACE)
return -ENOSPC;
- printf("Can't write signature for '%s' signature node in '%s' conf node: %s\n",
- node_name, image_name, fdt_strerror(ret));
+ fprintf(stderr,
+ "Can't write signature for '%s' signature node in '%s' conf node: %s\n",
+ node_name, image_name, fdt_strerror(ret));
return -1;
}
free(value);
@@ -274,8 +279,9 @@
if (keydest) {
ret = info.crypto->add_verify_data(&info, keydest);
if (ret < 0) {
- printf("Failed to add verification data for '%s' signature node in '%s' image node\n",
- node_name, image_name);
+ fprintf(stderr,
+ "Failed to add verification data for '%s' signature node in '%s' image node\n",
+ node_name, image_name);
return ret;
}
/* Return the node that was written to */
@@ -295,37 +301,37 @@
/* Open file */
fd = open(filename, O_RDONLY | O_BINARY);
if (fd < 0) {
- printf("Can't open file %s (err=%d => %s)\n",
- filename, errno, strerror(errno));
+ fprintf(stderr, "Can't open file %s (err=%d => %s)\n",
+ filename, errno, strerror(errno));
return -1;
}
/* Compute file size */
if (fstat(fd, &sbuf) < 0) {
- printf("Can't fstat file %s (err=%d => %s)\n",
- filename, errno, strerror(errno));
+ fprintf(stderr, "Can't fstat file %s (err=%d => %s)\n",
+ filename, errno, strerror(errno));
goto err;
}
/* Check file size */
if (sbuf.st_size != expected_size) {
- printf("File %s don't have the expected size (size=%lld, expected=%d)\n",
- filename, (long long)sbuf.st_size, expected_size);
+ fprintf(stderr, "File %s don't have the expected size (size=%lld, expected=%d)\n",
+ filename, (long long)sbuf.st_size, expected_size);
goto err;
}
/* Read data */
n = read(fd, data, sbuf.st_size);
if (n < 0) {
- printf("Can't read file %s (err=%d => %s)\n",
- filename, errno, strerror(errno));
+ fprintf(stderr, "Can't read file %s (err=%d => %s)\n",
+ filename, errno, strerror(errno));
goto err;
}
/* Check that we have read all the file */
if (n != sbuf.st_size) {
- printf("Can't read all file %s (read %zd bytes, expected %lld)\n",
- filename, n, (long long)sbuf.st_size);
+ fprintf(stderr, "Can't read all file %s (read %zd bytes, expected %lld)\n",
+ filename, n, (long long)sbuf.st_size);
goto err;
}
@@ -343,15 +349,15 @@
int i, ret;
if (!tmp) {
- printf("%s: pointer data is NULL\n", __func__);
+ fprintf(stderr, "%s: pointer data is NULL\n", __func__);
ret = -1;
goto out;
}
ret = clock_gettime(CLOCK_MONOTONIC, &date);
if (ret) {
- printf("%s: clock_gettime has failed (%s)\n", __func__,
- strerror(errno));
+ fprintf(stderr, "%s: clock_gettime has failed (%s)\n", __func__,
+ strerror(errno));
goto out;
}
@@ -376,8 +382,8 @@
int ret = -1;
if (fit_image_cipher_get_algo(fit, noffset, &algo_name)) {
- printf("Can't get algo name for cipher in image '%s'\n",
- image_name);
+ fprintf(stderr, "Can't get algo name for cipher in image '%s'\n",
+ image_name);
goto out;
}
@@ -386,8 +392,8 @@
/* Read the key name */
info->keyname = fdt_getprop(fit, noffset, FIT_KEY_HINT, NULL);
if (!info->keyname) {
- printf("Can't get key name for cipher in image '%s'\n",
- image_name);
+ fprintf(stderr, "Can't get key name for cipher in image '%s'\n",
+ image_name);
goto out;
}
@@ -405,7 +411,7 @@
info->cipher = image_get_cipher_algo(algo_name);
if (!info->cipher) {
- printf("Can't get algo for cipher '%s'\n", image_name);
+ fprintf(stderr, "Can't get algo for cipher '%s'\n", image_name);
goto out;
}
@@ -414,7 +420,7 @@
info->keydir, info->keyname, ".bin");
info->key = malloc(info->cipher->key_len);
if (!info->key) {
- printf("Can't allocate memory for key\n");
+ fprintf(stderr, "Can't allocate memory for key\n");
ret = -1;
goto out;
}
@@ -425,7 +431,7 @@
info->iv = malloc(info->cipher->iv_len);
if (!info->iv) {
- printf("Can't allocate memory for iv\n");
+ fprintf(stderr, "Can't allocate memory for iv\n");
ret = -1;
goto out;
}
@@ -459,7 +465,7 @@
goto out;
}
if (ret) {
- printf("Can't replace data with ciphered data (err = %d)\n", ret);
+ fprintf(stderr, "Can't replace data with ciphered data (err = %d)\n", ret);
goto out;
}
@@ -470,7 +476,7 @@
goto out;
}
if (ret) {
- printf("Can't add unciphered data size (err = %d)\n", ret);
+ fprintf(stderr, "Can't add unciphered data size (err = %d)\n", ret);
goto out;
}
@@ -510,8 +516,9 @@
if (keydest) {
ret = info.cipher->add_cipher_data(&info, keydest, fit, node_noffset);
if (ret) {
- printf("Failed to add verification data for cipher '%s' in image '%s'\n",
- info.keyname, image_name);
+ fprintf(stderr,
+ "Failed to add verification data for cipher '%s' in image '%s'\n",
+ info.keyname, image_name);
goto out;
}
}
@@ -540,13 +547,13 @@
/* Get image name */
image_name = fit_get_name(fit, image_noffset, NULL);
if (!image_name) {
- printf("Can't get image name\n");
+ fprintf(stderr, "Can't get image name\n");
return -1;
}
/* Get image data and data length */
if (fit_image_get_data(fit, image_noffset, &data, &size)) {
- printf("Can't get image data/size\n");
+ fprintf(stderr, "Can't get image data/size\n");
return -1;
}
@@ -560,7 +567,7 @@
if (fdt_getprop(fit, image_noffset, "data-size-unciphered", &len))
return 0;
if (len != -FDT_ERR_NOTFOUND) {
- printf("Failure testing for data-size-unciphered\n");
+ fprintf(stderr, "Failure testing for data-size-unciphered\n");
return -1;
}
@@ -570,7 +577,7 @@
if (cipher_node_offset == -FDT_ERR_NOTFOUND)
return 0;
if (cipher_node_offset < 0) {
- printf("Failure getting cipher node\n");
+ fprintf(stderr, "Failure getting cipher node\n");
return -1;
}
if (!IMAGE_ENABLE_ENCRYPT || !keydir)
@@ -626,7 +633,7 @@
/* Get image data and data length */
if (fit_image_get_data(fit, image_noffset, &data, &size)) {
- printf("Can't get image data/size\n");
+ fprintf(stderr, "Can't get image data/size\n");
return -1;
}
@@ -767,8 +774,9 @@
}
if (!hash_count) {
- printf("Failed to find any hash nodes in configuration '%s/%s' image '%s' - without these it is not possible to verify this image\n",
- conf_name, sig_name, iname);
+ fprintf(stderr,
+ "Failed to find any hash nodes in configuration '%s/%s' image '%s' - without these it is not possible to verify this image\n",
+ conf_name, sig_name, iname);
return -ENOMSG;
}
@@ -777,9 +785,10 @@
FIT_CIPHER_NODENAME);
if (noffset != -FDT_ERR_NOTFOUND) {
if (noffset < 0) {
- printf("Failed to get cipher node in configuration '%s/%s' image '%s': %s\n",
- conf_name, sig_name, iname,
- fdt_strerror(noffset));
+ fprintf(stderr,
+ "Failed to get cipher node in configuration '%s/%s' image '%s': %s\n",
+ conf_name, sig_name, iname,
+ fdt_strerror(noffset));
return -EIO;
}
ret = fdt_get_path(fit, noffset, path, sizeof(path));
@@ -792,13 +801,13 @@
return 0;
err_mem:
- printf("Out of memory processing configuration '%s/%s'\n", conf_name,
- sig_name);
+ fprintf(stderr, "Out of memory processing configuration '%s/%s'\n", conf_name,
+ sig_name);
return -ENOMEM;
err_path:
- printf("Failed to get path for image '%s' in configuration '%s/%s': %s\n",
- iname, conf_name, sig_name, fdt_strerror(ret));
+ fprintf(stderr, "Failed to get path for image '%s' in configuration '%s/%s': %s\n",
+ iname, conf_name, sig_name, fdt_strerror(ret));
return -ENOENT;
}
@@ -859,8 +868,9 @@
iname, index);
if (image_noffset < 0) {
- printf("Failed to find image '%s' in configuration '%s/%s'\n",
- iname, conf_name, sig_name);
+ fprintf(stderr,
+ "Failed to find image '%s' in configuration '%s/%s'\n",
+ iname, conf_name, sig_name);
if (allow_missing)
continue;
@@ -877,16 +887,16 @@
}
if (!image_count) {
- printf("Failed to find any images for configuration '%s/%s'\n",
- conf_name, sig_name);
+ fprintf(stderr, "Failed to find any images for configuration '%s/%s'\n",
+ conf_name, sig_name);
return -ENOMSG;
}
return 0;
err_mem:
- printf("Out of memory processing configuration '%s/%s'\n", conf_name,
- sig_name);
+ fprintf(stderr, "Out of memory processing configuration '%s/%s'\n", conf_name,
+ sig_name);
return -ENOMEM;
}
@@ -948,21 +958,21 @@
fdt_regions, ARRAY_SIZE(fdt_regions),
path, sizeof(path), 1);
if (count < 0) {
- printf("Failed to hash configuration '%s/%s': %s\n", conf_name,
- sig_name, fdt_strerror(ret));
+ fprintf(stderr, "Failed to hash configuration '%s/%s': %s\n", conf_name,
+ sig_name, fdt_strerror(ret));
return -EIO;
}
if (count == 0) {
- printf("No data to hash for configuration '%s/%s': %s\n",
- conf_name, sig_name, fdt_strerror(ret));
+ fprintf(stderr, "No data to hash for configuration '%s/%s': %s\n",
+ conf_name, sig_name, fdt_strerror(ret));
return -EINVAL;
}
/* Build our list of data blocks */
region = fit_region_make_list(fit, fdt_regions, count, NULL);
if (!region) {
- printf("Out of memory hashing configuration '%s/%s'\n",
- conf_name, sig_name);
+ fprintf(stderr, "Out of memory hashing configuration '%s/%s'\n",
+ conf_name, sig_name);
return -ENOMEM;
}
@@ -974,8 +984,8 @@
}
region_prop = malloc(len);
if (!region_prop) {
- printf("Out of memory setting up regions for configuration '%s/%s'\n",
- conf_name, sig_name);
+ fprintf(stderr, "Out of memory setting up regions for configuration '%s/%s'\n",
+ conf_name, sig_name);
return -ENOMEM;
}
for (i = len = 0; i < node_inc.count;
@@ -1040,8 +1050,8 @@
&value_len);
free(region);
if (ret) {
- printf("Failed to sign '%s' signature node in '%s' conf node\n",
- node_name, conf_name);
+ fprintf(stderr, "Failed to sign '%s' signature node in '%s' conf node\n",
+ node_name, conf_name);
/* We allow keys to be missing */
if (ret == -ENOENT)
@@ -1055,8 +1065,9 @@
if (ret) {
if (ret == -FDT_ERR_NOSPACE)
return -ENOSPC;
- printf("Can't write signature for '%s' signature node in '%s' conf node: %s\n",
- node_name, conf_name, fdt_strerror(ret));
+ fprintf(stderr,
+ "Can't write signature for '%s' signature node in '%s' conf node: %s\n",
+ node_name, conf_name, fdt_strerror(ret));
return -1;
}
free(value);
@@ -1069,8 +1080,9 @@
if (keydest) {
ret = info.crypto->add_verify_data(&info, keydest);
if (ret < 0) {
- printf("Failed to add verification data for '%s' signature node in '%s' configuration node\n",
- node_name, conf_name);
+ fprintf(stderr,
+ "Failed to add verification data for '%s' signature node in '%s' configuration node\n",
+ node_name, conf_name);
}
return ret;
}
@@ -1132,8 +1144,8 @@
/* Find images parent node offset */
images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
if (images_noffset < 0) {
- printf("Can't find images parent node '%s' (%s)\n",
- FIT_IMAGES_PATH, fdt_strerror(images_noffset));
+ fprintf(stderr, "Can't find images parent node '%s' (%s)\n",
+ FIT_IMAGES_PATH, fdt_strerror(images_noffset));
return images_noffset;
}
@@ -1169,8 +1181,8 @@
/* Find images parent node offset */
images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
if (images_noffset < 0) {
- printf("Can't find images parent node '%s' (%s)\n",
- FIT_IMAGES_PATH, fdt_strerror(images_noffset));
+ fprintf(stderr, "Can't find images parent node '%s' (%s)\n",
+ FIT_IMAGES_PATH, fdt_strerror(images_noffset));
return images_noffset;
}
@@ -1186,9 +1198,9 @@
fit, noffset, comment, require_keys, engine_id,
cmdname, algo_name);
if (ret) {
- printf("Can't add verification data for node '%s' (%s)\n",
- fdt_get_name(fit, noffset, NULL),
- fdt_strerror(ret));
+ fprintf(stderr, "Can't add verification data for node '%s' (%s)\n",
+ fdt_get_name(fit, noffset, NULL),
+ fdt_strerror(ret));
return ret;
}
}
@@ -1200,8 +1212,8 @@
/* Find configurations parent node offset */
confs_noffset = fdt_path_offset(fit, FIT_CONFS_PATH);
if (confs_noffset < 0) {
- printf("Can't find images parent node '%s' (%s)\n",
- FIT_CONFS_PATH, fdt_strerror(confs_noffset));
+ fprintf(stderr, "Can't find images parent node '%s' (%s)\n",
+ FIT_CONFS_PATH, fdt_strerror(confs_noffset));
return -ENOENT;
}
diff --git a/tools/iot2050-sign-fw.sh b/tools/iot2050-sign-fw.sh
index 6b426c8..75ffd56 100755
--- a/tools/iot2050-sign-fw.sh
+++ b/tools/iot2050-sign-fw.sh
@@ -5,6 +5,8 @@
exit 1
fi
+TOOLS_DIR=$(dirname $0)
+
TEMP_X509=$(mktemp XXXXXXXX.temp)
REVISION=${2:-0}
@@ -39,10 +41,10 @@
openssl req -new -x509 -key $1 -nodes -outform DER -out $CERT_X509 -config $TEMP_X509 -sha512
cat $CERT_X509 tispl.bin > tispl.bin_signed
-source/tools/binman/binman replace -i flash-pg1.bin -f tispl.bin_signed fit@180000
-source/tools/binman/binman replace -i flash-pg2.bin -f tispl.bin_signed fit@180000
+$TOOLS_DIR/binman/binman replace -i flash-pg1.bin -f tispl.bin_signed fit@180000
+$TOOLS_DIR/binman/binman replace -i flash-pg2.bin -f tispl.bin_signed fit@180000
rm $TEMP_X509 $CERT_X509
-source/tools/binman/binman sign -i flash-pg1.bin -k $1 -a sha256,rsa4096 fit@380000
-source/tools/binman/binman sign -i flash-pg2.bin -k $1 -a sha256,rsa4096 fit@380000
+$TOOLS_DIR/binman/binman sign -i flash-pg1.bin -k $1 -a sha256,rsa4096 fit@380000
+$TOOLS_DIR/binman/binman sign -i flash-pg2.bin -k $1 -a sha256,rsa4096 fit@380000
diff --git a/tools/logos/stm32f746-disco.bmp b/tools/logos/stm32f746-disco.bmp
new file mode 100644
index 0000000..c1ef4fb
--- /dev/null
+++ b/tools/logos/stm32f746-disco.bmp
Binary files differ
diff --git a/tools/logos/ti.bmp b/tools/logos/ti_logo_414x97_32bpp.bmp
similarity index 100%
rename from tools/logos/ti.bmp
rename to tools/logos/ti_logo_414x97_32bpp.bmp
Binary files differ
diff --git a/tools/logos/ti.gz b/tools/logos/ti_logo_414x97_32bpp.bmp.gz
similarity index 100%
rename from tools/logos/ti.gz
rename to tools/logos/ti_logo_414x97_32bpp.bmp.gz
Binary files differ
diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c
index 52be1f1..b8fc606 100644
--- a/tools/mkeficapsule.c
+++ b/tools/mkeficapsule.c
@@ -29,7 +29,7 @@
efi_guid_t efi_guid_fm_capsule = EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID;
efi_guid_t efi_guid_cert_type_pkcs7 = EFI_CERT_TYPE_PKCS7_GUID;
-static const char *opts_short = "g:i:I:v:p:c:m:o:dhAR";
+static const char *opts_short = "g:i:I:v:p:c:m:o:dhARD";
enum {
CAPSULE_NORMAL_BLOB = 0,
@@ -49,6 +49,7 @@
{"fw-accept", no_argument, NULL, 'A'},
{"fw-revert", no_argument, NULL, 'R'},
{"capoemflag", required_argument, NULL, 'o'},
+ {"dump-capsule", no_argument, NULL, 'D'},
{"help", no_argument, NULL, 'h'},
{NULL, 0, NULL, 0},
};
@@ -69,6 +70,7 @@
"\t-A, --fw-accept firmware accept capsule, requires GUID, no image blob\n"
"\t-R, --fw-revert firmware revert capsule, takes no GUID, no image blob\n"
"\t-o, --capoemflag Capsule OEM Flag, an integer between 0x0000 and 0xffff\n"
+ "\t-D, --dump-capsule dump the contents of the capsule headers\n"
"\t-h, --help print a help message\n",
tool_name);
}
@@ -647,6 +649,215 @@
return ret;
}
+static void print_guid(void *ptr)
+{
+ int i;
+ efi_guid_t *guid = ptr;
+ const uint8_t seq[] = {
+ 3, 2, 1, 0, '-', 5, 4, '-', 7, 6,
+ '-', 8, 9, '-', 10, 11, 12, 13, 14, 15 };
+
+ for (i = 0; i < ARRAY_SIZE(seq); i++) {
+ if (seq[i] == '-')
+ putchar(seq[i]);
+ else
+ printf("%02X", guid->b[seq[i]]);
+ }
+
+ printf("\n");
+}
+
+static uint32_t dump_fmp_payload_header(
+ struct fmp_payload_header *fmp_payload_hdr)
+{
+ if (fmp_payload_hdr->signature == FMP_PAYLOAD_HDR_SIGNATURE) {
+ printf("--------\n");
+ printf("FMP_PAYLOAD_HDR.SIGNATURE\t\t\t: %08X\n",
+ FMP_PAYLOAD_HDR_SIGNATURE);
+ printf("FMP_PAYLOAD_HDR.HEADER_SIZE\t\t\t: %08X\n",
+ fmp_payload_hdr->header_size);
+ printf("FMP_PAYLOAD_HDR.FW_VERSION\t\t\t: %08X\n",
+ fmp_payload_hdr->fw_version);
+ printf("FMP_PAYLOAD_HDR.LOWEST_SUPPORTED_VERSION\t: %08X\n",
+ fmp_payload_hdr->lowest_supported_version);
+ return fmp_payload_hdr->header_size;
+ }
+
+ return 0;
+}
+
+static void dump_capsule_auth_header(
+ struct efi_firmware_image_authentication *capsule_auth_hdr)
+{
+ printf("EFI_FIRMWARE_IMAGE_AUTH.MONOTONIC_COUNT\t\t: %08lX\n",
+ capsule_auth_hdr->monotonic_count);
+ printf("EFI_FIRMWARE_IMAGE_AUTH.AUTH_INFO.HDR.dwLENGTH\t: %08X\n",
+ capsule_auth_hdr->auth_info.hdr.dwLength);
+ printf("EFI_FIRMWARE_IMAGE_AUTH.AUTH_INFO.HDR.wREVISION\t: %08X\n",
+ capsule_auth_hdr->auth_info.hdr.wRevision);
+ printf("EFI_FIRMWARE_IMAGE_AUTH.AUTH_INFO.HDR.wCERTTYPE\t: %08X\n",
+ capsule_auth_hdr->auth_info.hdr.wCertificateType);
+ printf("EFI_FIRMWARE_IMAGE_AUTH.AUTH_INFO.CERT_TYPE\t: ");
+ print_guid(&capsule_auth_hdr->auth_info.cert_type);
+}
+
+static void dump_fmp_capsule_image_header(
+ struct efi_firmware_management_capsule_image_header *image_hdr)
+{
+ void *capsule_auth_hdr;
+ void *fmp_payload_hdr;
+ uint64_t signature_size = 0;
+ uint32_t payload_size = 0;
+ uint32_t fmp_payload_hdr_size = 0;
+ struct efi_firmware_image_authentication *auth_hdr;
+
+ printf("--------\n");
+ printf("FMP_CAPSULE_IMAGE_HDR.VERSION\t\t\t: %08X\n",
+ image_hdr->version);
+ printf("FMP_CAPSULE_IMAGE_HDR.UPDATE_IMAGE_TYPE_ID\t: ");
+ print_guid(&image_hdr->update_image_type_id);
+ printf("FMP_CAPSULE_IMAGE_HDR.UPDATE_IMAGE_INDEX\t: %08X\n",
+ image_hdr->update_image_index);
+ printf("FMP_CAPSULE_IMAGE_HDR.UPDATE_IMAGE_SIZE\t\t: %08X\n",
+ image_hdr->update_image_size);
+ printf("FMP_CAPSULE_IMAGE_HDR.UPDATE_VENDOR_CODE_SIZE\t: %08X\n",
+ image_hdr->update_vendor_code_size);
+ printf("FMP_CAPSULE_IMAGE_HDR.UPDATE_HARDWARE_INSTANCE\t: %08lX\n",
+ image_hdr->update_hardware_instance);
+ printf("FMP_CAPSULE_IMAGE_HDR.IMAGE_CAPSULE_SUPPORT\t: %08lX\n",
+ image_hdr->image_capsule_support);
+
+ printf("--------\n");
+ if (image_hdr->image_capsule_support & CAPSULE_SUPPORT_AUTHENTICATION) {
+ capsule_auth_hdr = (char *)image_hdr + sizeof(*image_hdr);
+ dump_capsule_auth_header(capsule_auth_hdr);
+
+ auth_hdr = capsule_auth_hdr;
+ signature_size = sizeof(auth_hdr->monotonic_count) +
+ auth_hdr->auth_info.hdr.dwLength;
+ fmp_payload_hdr = (char *)capsule_auth_hdr + signature_size;
+ } else {
+ printf("Capsule Authentication Not Enabled\n");
+ fmp_payload_hdr = (char *)image_hdr + sizeof(*image_hdr);
+ }
+
+ fmp_payload_hdr_size = dump_fmp_payload_header(fmp_payload_hdr);
+
+ payload_size = image_hdr->update_image_size - signature_size -
+ fmp_payload_hdr_size;
+ printf("--------\n");
+ printf("Payload Image Size\t\t\t\t: %08X\n", payload_size);
+}
+
+static void dump_fmp_header(
+ struct efi_firmware_management_capsule_header *fmp_hdr)
+{
+ int i;
+ void *capsule_image_hdr;
+
+ printf("EFI_FMP_HDR.VERSION\t\t\t\t: %08X\n", fmp_hdr->version);
+ printf("EFI_FMP_HDR.EMBEDDED_DRIVER_COUNT\t\t: %08X\n",
+ fmp_hdr->embedded_driver_count);
+ printf("EFI_FMP_HDR.PAYLOAD_ITEM_COUNT\t\t\t: %08X\n",
+ fmp_hdr->payload_item_count);
+
+ /*
+ * We currently don't support Embedded Drivers.
+ * Only worry about the payload items.
+ */
+ for (i = 0; i < fmp_hdr->payload_item_count; i++) {
+ capsule_image_hdr = (char *)fmp_hdr +
+ fmp_hdr->item_offset_list[i];
+ dump_fmp_capsule_image_header(capsule_image_hdr);
+ }
+}
+
+static void dump_capsule_header(struct efi_capsule_header *capsule_hdr)
+{
+ printf("EFI_CAPSULE_HDR.CAPSULE_GUID\t\t\t: ");
+ print_guid((void *)&capsule_hdr->capsule_guid);
+ printf("EFI_CAPSULE_HDR.HEADER_SIZE\t\t\t: %08X\n",
+ capsule_hdr->header_size);
+ printf("EFI_CAPSULE_HDR.FLAGS\t\t\t\t: %08X\n", capsule_hdr->flags);
+ printf("EFI_CAPSULE_HDR.CAPSULE_IMAGE_SIZE\t\t: %08X\n",
+ capsule_hdr->capsule_image_size);
+}
+
+static void normal_capsule_dump(void *capsule_buf)
+{
+ void *fmp_hdr;
+ struct efi_capsule_header *hdr = capsule_buf;
+
+ dump_capsule_header(hdr);
+ printf("--------\n");
+
+ fmp_hdr = (char *)capsule_buf + sizeof(*hdr);
+ dump_fmp_header(fmp_hdr);
+}
+
+static void empty_capsule_dump(void *capsule_buf)
+{
+ efi_guid_t *accept_image_guid;
+ struct efi_capsule_header *hdr = capsule_buf;
+ efi_guid_t efi_empty_accept_capsule = FW_ACCEPT_OS_GUID;
+
+ dump_capsule_header(hdr);
+
+ if (!memcmp(&efi_empty_accept_capsule, &hdr->capsule_guid,
+ sizeof(efi_guid_t))) {
+ accept_image_guid = (void *)(char *)capsule_buf +
+ sizeof(struct efi_capsule_header);
+ printf("--------\n");
+ printf("ACCEPT_IMAGE_GUID\t\t\t\t: ");
+ print_guid(accept_image_guid);
+ }
+}
+
+static void dump_capsule_contents(char *capsule_file)
+{
+ int fd;
+ char *ptr;
+ efi_guid_t efi_fmp_guid = EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID;
+ efi_guid_t efi_empty_accept_capsule = FW_ACCEPT_OS_GUID;
+ efi_guid_t efi_empty_revert_capsule = FW_REVERT_OS_GUID;
+ struct stat sbuf;
+
+ if (!capsule_file) {
+ fprintf(stderr, "No capsule file provided\n");
+ exit(EXIT_FAILURE);
+ }
+
+ if ((fd = open(capsule_file, O_RDONLY)) < 0) {
+ fprintf(stderr, "Error opening capsule file: %s\n",
+ capsule_file);
+ exit(EXIT_FAILURE);
+ }
+
+ if (fstat(fd, &sbuf) < 0) {
+ fprintf(stderr, "Can't stat capsule file: %s\n", capsule_file);
+ exit(EXIT_FAILURE);
+ }
+
+ if ((ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, fd, 0))
+ == MAP_FAILED) {
+ fprintf(stderr, "Can't mmap capsule file: %s\n", capsule_file);
+ exit(EXIT_FAILURE);
+ }
+
+ if (!memcmp(&efi_fmp_guid, ptr, sizeof(efi_guid_t))) {
+ normal_capsule_dump(ptr);
+ } else if (!memcmp(&efi_empty_accept_capsule, ptr,
+ sizeof(efi_guid_t)) ||
+ !memcmp(&efi_empty_revert_capsule, ptr,
+ sizeof(efi_guid_t))) {
+ empty_capsule_dump(ptr);
+ } else {
+ fprintf(stderr, "Unable to decode the capsule file: %s\n",
+ capsule_file);
+ exit(EXIT_FAILURE);
+ }
+}
+
/**
* main - main entry function of mkeficapsule
* @argc: Number of arguments
@@ -666,6 +877,7 @@
unsigned long index, instance;
uint64_t mcount;
unsigned long oemflags;
+ bool capsule_dump;
char *privkey_file, *cert_file;
int c, idx;
struct fmp_payload_header_params fmp_ph_params = { 0 };
@@ -676,6 +888,7 @@
mcount = 0;
privkey_file = NULL;
cert_file = NULL;
+ capsule_dump = false;
dump_sig = 0;
capsule_type = CAPSULE_NORMAL_BLOB;
oemflags = 0;
@@ -754,12 +967,24 @@
exit(1);
}
break;
+ case 'D':
+ capsule_dump = true;
+ break;
default:
print_usage();
exit(EXIT_SUCCESS);
}
}
+ if (capsule_dump) {
+ if (argc != optind + 1) {
+ fprintf(stderr, "Must provide the capsule file to parse\n");
+ exit(EXIT_FAILURE);
+ }
+ dump_capsule_contents(argv[argc - 1]);
+ exit(EXIT_SUCCESS);
+ }
+
/* check necessary parameters */
if ((capsule_type == CAPSULE_NORMAL_BLOB &&
((argc != optind + 2) || !guid ||
diff --git a/tools/patman/__main__.py b/tools/patman/__main__.py
index 8eba5d3..f645b38 100755
--- a/tools/patman/__main__.py
+++ b/tools/patman/__main__.py
@@ -6,195 +6,93 @@
"""See README for more information"""
-from argparse import ArgumentParser
try:
- import importlib.resources
+ from importlib import resources
except ImportError:
# for Python 3.6
- import importlib_resources
+ import importlib_resources as resources
import os
import re
import sys
import traceback
-if __name__ == "__main__":
- # Allow 'from patman import xxx to work'
- our_path = os.path.dirname(os.path.realpath(__file__))
- sys.path.append(os.path.join(our_path, '..'))
+# Allow 'from patman import xxx to work'
+# pylint: disable=C0413
+our_path = os.path.dirname(os.path.realpath(__file__))
+sys.path.append(os.path.join(our_path, '..'))
# Our modules
+from patman import cmdline
from patman import control
-from patman import func_test
-from patman import gitutil
-from patman import project
-from patman import settings
from u_boot_pylib import terminal
from u_boot_pylib import test_util
from u_boot_pylib import tools
-epilog = '''Create patches from commits in a branch, check them and email them
-as specified by tags you place in the commits. Use -n to do a dry run first.'''
-parser = ArgumentParser(epilog=epilog)
-parser.add_argument('-b', '--branch', type=str,
- help="Branch to process (by default, the current branch)")
-parser.add_argument('-c', '--count', dest='count', type=int,
- default=-1, help='Automatically create patches from top n commits')
-parser.add_argument('-e', '--end', type=int, default=0,
- help='Commits to skip at end of patch list')
-parser.add_argument('-D', '--debug', action='store_true',
- help='Enabling debugging (provides a full traceback on error)')
-parser.add_argument('-p', '--project', default=project.detect_project(),
- help="Project name; affects default option values and "
- "aliases [default: %(default)s]")
-parser.add_argument('-P', '--patchwork-url',
- default='https://patchwork.ozlabs.org',
- help='URL of patchwork server [default: %(default)s]')
-parser.add_argument('-s', '--start', dest='start', type=int,
- default=0, help='Commit to start creating patches from (0 = HEAD)')
-parser.add_argument('-v', '--verbose', action='store_true', dest='verbose',
- default=False, help='Verbose output of errors and warnings')
-parser.add_argument('-H', '--full-help', action='store_true', dest='full_help',
- default=False, help='Display the README file')
+def run_patman():
+ """Run patamn
-subparsers = parser.add_subparsers(dest='cmd')
-send = subparsers.add_parser(
- 'send', help='Format, check and email patches (default command)')
-send.add_argument('-i', '--ignore-errors', action='store_true',
- dest='ignore_errors', default=False,
- help='Send patches email even if patch errors are found')
-send.add_argument('-l', '--limit-cc', dest='limit', type=int, default=None,
- help='Limit the cc list to LIMIT entries [default: %(default)s]')
-send.add_argument('-m', '--no-maintainers', action='store_false',
- dest='add_maintainers', default=True,
- help="Don't cc the file maintainers automatically")
-send.add_argument(
- '--get-maintainer-script', dest='get_maintainer_script', type=str,
- action='store',
- default=os.path.join(gitutil.get_top_level(), 'scripts',
- 'get_maintainer.pl') + ' --norolestats',
- help='File name of the get_maintainer.pl (or compatible) script.')
-send.add_argument('-n', '--dry-run', action='store_true', dest='dry_run',
- default=False, help="Do a dry run (create but don't email patches)")
-send.add_argument('-r', '--in-reply-to', type=str, action='store',
- help="Message ID that this series is in reply to")
-send.add_argument('-t', '--ignore-bad-tags', action='store_true',
- default=False,
- help='Ignore bad tags / aliases (default=warn)')
-send.add_argument('-T', '--thread', action='store_true', dest='thread',
- default=False, help='Create patches as a single thread')
-send.add_argument('--cc-cmd', dest='cc_cmd', type=str, action='store',
- default=None, help='Output cc list for patch file (used by git)')
-send.add_argument('--no-binary', action='store_true', dest='ignore_binary',
- default=False,
- help="Do not output contents of changes in binary files")
-send.add_argument('--no-check', action='store_false', dest='check_patch',
- default=True,
- help="Don't check for patch compliance")
-send.add_argument('--tree', dest='check_patch_use_tree', default=False,
- action='store_true',
- help=("Set `tree` to True. If `tree` is False then we'll "
- "pass '--no-tree' to checkpatch (default: tree=%(default)s)"))
-send.add_argument('--no-tree', dest='check_patch_use_tree',
- action='store_false', help="Set `tree` to False")
-send.add_argument('--no-tags', action='store_false', dest='process_tags',
- default=True, help="Don't process subject tags as aliases")
-send.add_argument('--no-signoff', action='store_false', dest='add_signoff',
- default=True, help="Don't add Signed-off-by to patches")
-send.add_argument('--smtp-server', type=str,
- help="Specify the SMTP server to 'git send-email'")
+ This is the main program. It collects arguments and runs either the tests or
+ the control module.
+ """
+ args = cmdline.parse_args()
-send.add_argument('patchfiles', nargs='*')
+ if not args.debug:
+ sys.tracebacklimit = 0
-# Only add the 'test' action if the test data files are available.
-if os.path.exists(func_test.TEST_DATA_DIR):
- test_parser = subparsers.add_parser('test', help='Run tests')
- test_parser.add_argument('testname', type=str, default=None, nargs='?',
- help="Specify the test to run")
+ # Run our meagre tests
+ if args.cmd == 'test':
+ # pylint: disable=C0415
+ from patman import func_test
+ from patman import test_checkpatch
-status = subparsers.add_parser('status',
- help='Check status of patches in patchwork')
-status.add_argument('-C', '--show-comments', action='store_true',
- help='Show comments from each patch')
-status.add_argument('-d', '--dest-branch', type=str,
- help='Name of branch to create with collected responses')
-status.add_argument('-f', '--force', action='store_true',
- help='Force overwriting an existing branch')
+ result = test_util.run_test_suites(
+ 'patman', False, False, False, None, None, None,
+ [test_checkpatch.TestPatch, func_test.TestFunctional,
+ 'gitutil', 'settings'])
-# Parse options twice: first to get the project and second to handle
-# defaults properly (which depends on project)
-# Use parse_known_args() in case 'cmd' is omitted
-argv = sys.argv[1:]
-args, rest = parser.parse_known_args(argv)
-if hasattr(args, 'project'):
- settings.Setup(parser, args.project)
- args, rest = parser.parse_known_args(argv)
+ sys.exit(0 if result.wasSuccessful() else 1)
-# If we have a command, it is safe to parse all arguments
-if args.cmd:
- args = parser.parse_args(argv)
-else:
- # No command, so insert it after the known arguments and before the ones
- # that presumably relate to the 'send' subcommand
- nargs = len(rest)
- argv = argv[:-nargs] + ['send'] + rest
- args = parser.parse_args(argv)
+ # Process commits, produce patches files, check them, email them
+ elif args.cmd == 'send':
+ # Called from git with a patch filename as argument
+ # Printout a list of additional CC recipients for this patch
+ if args.cc_cmd:
+ re_line = re.compile(r'(\S*) (.*)')
+ with open(args.cc_cmd, 'r', encoding='utf-8') as inf:
+ for line in inf.readlines():
+ match = re_line.match(line)
+ if match and match.group(1) == args.patchfiles[0]:
+ for cca in match.group(2).split('\0'):
+ cca = cca.strip()
+ if cca:
+ print(cca)
-if __name__ != "__main__":
- pass
+ elif args.full_help:
+ with resources.path('patman', 'README.rst') as readme:
+ tools.print_full_help(str(readme))
+ else:
+ # If we are not processing tags, no need to warning about bad ones
+ if not args.process_tags:
+ args.ignore_bad_tags = True
+ control.send(args)
-if not args.debug:
- sys.tracebacklimit = 0
+ # Check status of patches in patchwork
+ elif args.cmd == 'status':
+ ret_code = 0
+ try:
+ control.patchwork_status(args.branch, args.count, args.start, args.end,
+ args.dest_branch, args.force,
+ args.show_comments, args.patchwork_url)
+ except Exception as exc:
+ terminal.tprint(f'patman: {type(exc).__name__}: {exc}',
+ colour=terminal.Color.RED)
+ if args.debug:
+ print()
+ traceback.print_exc()
+ ret_code = 1
+ sys.exit(ret_code)
-# Run our meagre tests
-if args.cmd == 'test':
- from patman import func_test
- from patman import test_checkpatch
- result = test_util.run_test_suites(
- 'patman', False, False, False, None, None, None,
- [test_checkpatch.TestPatch, func_test.TestFunctional,
- 'gitutil', 'settings'])
-
- sys.exit(0 if result.wasSuccessful() else 1)
-
-# Process commits, produce patches files, check them, email them
-elif args.cmd == 'send':
- # Called from git with a patch filename as argument
- # Printout a list of additional CC recipients for this patch
- if args.cc_cmd:
- fd = open(args.cc_cmd, 'r')
- re_line = re.compile('(\S*) (.*)')
- for line in fd.readlines():
- match = re_line.match(line)
- if match and match.group(1) == args.patchfiles[0]:
- for cc in match.group(2).split('\0'):
- cc = cc.strip()
- if cc:
- print(cc)
- fd.close()
-
- elif args.full_help:
- with importlib.resources.path('patman', 'README.rst') as readme:
- tools.print_full_help(str(readme))
- else:
- # If we are not processing tags, no need to warning about bad ones
- if not args.process_tags:
- args.ignore_bad_tags = True
- control.send(args)
-
-# Check status of patches in patchwork
-elif args.cmd == 'status':
- ret_code = 0
- try:
- control.patchwork_status(args.branch, args.count, args.start, args.end,
- args.dest_branch, args.force,
- args.show_comments, args.patchwork_url)
- except Exception as e:
- terminal.tprint('patman: %s: %s' % (type(e).__name__, e),
- colour=terminal.Color.RED)
- if args.debug:
- print()
- traceback.print_exc()
- ret_code = 1
- sys.exit(ret_code)
+if __name__ == "__main__":
+ sys.exit(run_patman())
diff --git a/tools/patman/cmdline.py b/tools/patman/cmdline.py
new file mode 100644
index 0000000..d6496c0
--- /dev/null
+++ b/tools/patman/cmdline.py
@@ -0,0 +1,147 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2023 Google LLC
+#
+
+"""Handles parsing of buildman arguments
+
+This creates the argument parser and uses it to parse the arguments passed in
+"""
+
+import argparse
+import os
+import pathlib
+import sys
+
+from patman import gitutil
+from patman import project
+from patman import settings
+
+PATMAN_DIR = pathlib.Path(__file__).parent
+HAS_TESTS = os.path.exists(PATMAN_DIR / "func_test.py")
+
+def parse_args():
+ """Parse command line arguments from sys.argv[]
+
+ Returns:
+ tuple containing:
+ options: command line options
+ args: command lin arguments
+ """
+ epilog = '''Create patches from commits in a branch, check them and email
+ them as specified by tags you place in the commits. Use -n to do a dry
+ run first.'''
+
+ parser = argparse.ArgumentParser(epilog=epilog)
+ parser.add_argument('-b', '--branch', type=str,
+ help="Branch to process (by default, the current branch)")
+ parser.add_argument('-c', '--count', dest='count', type=int,
+ default=-1, help='Automatically create patches from top n commits')
+ parser.add_argument('-e', '--end', type=int, default=0,
+ help='Commits to skip at end of patch list')
+ parser.add_argument('-D', '--debug', action='store_true',
+ help='Enabling debugging (provides a full traceback on error)')
+ parser.add_argument('-p', '--project', default=project.detect_project(),
+ help="Project name; affects default option values and "
+ "aliases [default: %(default)s]")
+ parser.add_argument('-P', '--patchwork-url',
+ default='https://patchwork.ozlabs.org',
+ help='URL of patchwork server [default: %(default)s]')
+ parser.add_argument('-s', '--start', dest='start', type=int,
+ default=0, help='Commit to start creating patches from (0 = HEAD)')
+ parser.add_argument(
+ '-v', '--verbose', action='store_true', dest='verbose', default=False,
+ help='Verbose output of errors and warnings')
+ parser.add_argument(
+ '-H', '--full-help', action='store_true', dest='full_help',
+ default=False, help='Display the README file')
+
+ subparsers = parser.add_subparsers(dest='cmd')
+ send = subparsers.add_parser(
+ 'send', help='Format, check and email patches (default command)')
+ send.add_argument('-i', '--ignore-errors', action='store_true',
+ dest='ignore_errors', default=False,
+ help='Send patches email even if patch errors are found')
+ send.add_argument('-l', '--limit-cc', dest='limit', type=int, default=None,
+ help='Limit the cc list to LIMIT entries [default: %(default)s]')
+ send.add_argument('-m', '--no-maintainers', action='store_false',
+ dest='add_maintainers', default=True,
+ help="Don't cc the file maintainers automatically")
+ send.add_argument(
+ '--get-maintainer-script', dest='get_maintainer_script', type=str,
+ action='store',
+ default=os.path.join(gitutil.get_top_level(), 'scripts',
+ 'get_maintainer.pl') + ' --norolestats',
+ help='File name of the get_maintainer.pl (or compatible) script.')
+ send.add_argument('-n', '--dry-run', action='store_true', dest='dry_run',
+ default=False, help="Do a dry run (create but don't email patches)")
+ send.add_argument('-r', '--in-reply-to', type=str, action='store',
+ help="Message ID that this series is in reply to")
+ send.add_argument('-t', '--ignore-bad-tags', action='store_true',
+ default=False,
+ help='Ignore bad tags / aliases (default=warn)')
+ send.add_argument('-T', '--thread', action='store_true', dest='thread',
+ default=False, help='Create patches as a single thread')
+ send.add_argument('--cc-cmd', dest='cc_cmd', type=str, action='store',
+ default=None, help='Output cc list for patch file (used by git)')
+ send.add_argument('--no-binary', action='store_true', dest='ignore_binary',
+ default=False,
+ help="Do not output contents of changes in binary files")
+ send.add_argument('--no-check', action='store_false', dest='check_patch',
+ default=True,
+ help="Don't check for patch compliance")
+ send.add_argument(
+ '--tree', dest='check_patch_use_tree', default=False,
+ action='store_true',
+ help=("Set `tree` to True. If `tree` is False then we'll pass "
+ "'--no-tree' to checkpatch (default: tree=%(default)s)"))
+ send.add_argument('--no-tree', dest='check_patch_use_tree',
+ action='store_false', help="Set `tree` to False")
+ send.add_argument(
+ '--no-tags', action='store_false', dest='process_tags', default=True,
+ help="Don't process subject tags as aliases")
+ send.add_argument('--no-signoff', action='store_false', dest='add_signoff',
+ default=True, help="Don't add Signed-off-by to patches")
+ send.add_argument('--smtp-server', type=str,
+ help="Specify the SMTP server to 'git send-email'")
+ send.add_argument('--keep-change-id', action='store_true',
+ help='Preserve Change-Id tags in patches to send.')
+
+ send.add_argument('patchfiles', nargs='*')
+
+ # Only add the 'test' action if the test data files are available.
+ if HAS_TESTS:
+ test_parser = subparsers.add_parser('test', help='Run tests')
+ test_parser.add_argument('testname', type=str, default=None, nargs='?',
+ help="Specify the test to run")
+
+ status = subparsers.add_parser('status',
+ help='Check status of patches in patchwork')
+ status.add_argument('-C', '--show-comments', action='store_true',
+ help='Show comments from each patch')
+ status.add_argument(
+ '-d', '--dest-branch', type=str,
+ help='Name of branch to create with collected responses')
+ status.add_argument('-f', '--force', action='store_true',
+ help='Force overwriting an existing branch')
+
+ # Parse options twice: first to get the project and second to handle
+ # defaults properly (which depends on project)
+ # Use parse_known_args() in case 'cmd' is omitted
+ argv = sys.argv[1:]
+ args, rest = parser.parse_known_args(argv)
+ if hasattr(args, 'project'):
+ settings.Setup(parser, args.project)
+ args, rest = parser.parse_known_args(argv)
+
+ # If we have a command, it is safe to parse all arguments
+ if args.cmd:
+ args = parser.parse_args(argv)
+ else:
+ # No command, so insert it after the known arguments and before the ones
+ # that presumably relate to the 'send' subcommand
+ nargs = len(rest)
+ argv = argv[:-nargs] + ['send'] + rest
+ args = parser.parse_args(argv)
+
+ return args
diff --git a/tools/patman/control.py b/tools/patman/control.py
index 916ddf8..b292da9 100644
--- a/tools/patman/control.py
+++ b/tools/patman/control.py
@@ -16,11 +16,14 @@
from patman import patchstream
from u_boot_pylib import terminal
+
def setup():
"""Do required setup before doing anything"""
gitutil.setup()
-def prepare_patches(col, branch, count, start, end, ignore_binary, signoff):
+
+def prepare_patches(col, branch, count, start, end, ignore_binary, signoff,
+ keep_change_id=False):
"""Figure out what patches to generate, then generate them
The patch files are written to the current directory, e.g. 0001_xxx.patch
@@ -35,6 +38,7 @@
end (int): End patch to use (0=last one in series, 1=one before that,
etc.)
ignore_binary (bool): Don't generate patches for binary files
+ keep_change_id (bool): Preserve the Change-Id tag.
Returns:
Tuple:
@@ -59,11 +63,12 @@
branch, start, to_do, ignore_binary, series, signoff)
# Fix up the patch files to our liking, and insert the cover letter
- patchstream.fix_patches(series, patch_files)
+ patchstream.fix_patches(series, patch_files, keep_change_id)
if cover_fname and series.get('cover'):
patchstream.insert_cover_letter(cover_fname, series, to_do)
return series, cover_fname, patch_files
+
def check_patches(series, patch_files, run_checkpatch, verbose, use_tree):
"""Run some checks on a set of patches
@@ -166,7 +171,8 @@
col = terminal.Color()
series, cover_fname, patch_files = prepare_patches(
col, args.branch, args.count, args.start, args.end,
- args.ignore_binary, args.add_signoff)
+ args.ignore_binary, args.add_signoff,
+ keep_change_id=args.keep_change_id)
ok = check_patches(series, patch_files, args.check_patch,
args.verbose, args.check_patch_use_tree)
diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py
index b0a12f2..10ea5ff 100644
--- a/tools/patman/gitutil.py
+++ b/tools/patman/gitutil.py
@@ -147,8 +147,9 @@
if remote == '.':
return merge, None
elif remote and merge:
- leaf = merge.split('/')[-1]
- return '%s/%s' % (remote, leaf), None
+ # Drop the initial refs/heads from merge
+ leaf = merge.split('/', maxsplit=2)[2:]
+ return '%s/%s' % (remote, '/'.join(leaf)), None
else:
raise ValueError("Cannot determine upstream branch for branch "
"'%s' remote='%s', merge='%s'"
diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index f91669a..e2e2a83 100644
--- a/tools/patman/patchstream.py
+++ b/tools/patman/patchstream.py
@@ -68,6 +68,7 @@
STATE_PATCH_HEADER = 2 # In patch header (after the subject)
STATE_DIFFS = 3 # In the diff part (past --- line)
+
class PatchStream:
"""Class for detecting/injecting tags in a patch or series of patches
@@ -76,7 +77,7 @@
unwanted tags or inject additional ones. These correspond to the two
phases of processing.
"""
- def __init__(self, series, is_log=False):
+ def __init__(self, series, is_log=False, keep_change_id=False):
self.skip_blank = False # True to skip a single blank line
self.found_test = False # Found a TEST= line
self.lines_after_test = 0 # Number of lines found after TEST=
@@ -86,6 +87,7 @@
self.section = [] # The current section...END section
self.series = series # Info about the patch series
self.is_log = is_log # True if indent like git log
+ self.keep_change_id = keep_change_id # True to keep Change-Id tags
self.in_change = None # Name of the change list we are in
self.change_version = 0 # Non-zero if we are in a change list
self.change_lines = [] # Lines of the current change
@@ -452,6 +454,8 @@
# Detect Change-Id tags
elif change_id_match:
+ if self.keep_change_id:
+ out = [line]
value = change_id_match.group(1)
if self.is_log:
if self.commit.change_id:
@@ -763,7 +767,7 @@
pst.finalise()
return series
-def fix_patch(backup_dir, fname, series, cmt):
+def fix_patch(backup_dir, fname, series, cmt, keep_change_id=False):
"""Fix up a patch file, by adding/removing as required.
We remove our tags from the patch file, insert changes lists, etc.
@@ -776,6 +780,7 @@
fname (str): Filename to patch file to process
series (Series): Series information about this patch set
cmt (Commit): Commit object for this patch file
+ keep_change_id (bool): Keep the Change-Id tag.
Return:
list: A list of errors, each str, or [] if all ok.
@@ -783,7 +788,7 @@
handle, tmpname = tempfile.mkstemp()
outfd = os.fdopen(handle, 'w', encoding='utf-8')
infd = open(fname, 'r', encoding='utf-8')
- pst = PatchStream(series)
+ pst = PatchStream(series, keep_change_id=keep_change_id)
pst.commit = cmt
pst.process_stream(infd, outfd)
infd.close()
@@ -795,7 +800,7 @@
shutil.move(tmpname, fname)
return cmt.warn
-def fix_patches(series, fnames):
+def fix_patches(series, fnames, keep_change_id=False):
"""Fix up a list of patches identified by filenames
The patch files are processed in place, and overwritten.
@@ -803,6 +808,7 @@
Args:
series (Series): The Series object
fnames (:type: list of str): List of patch files to process
+ keep_change_id (bool): Keep the Change-Id tag.
"""
# Current workflow creates patches, so we shouldn't need a backup
backup_dir = None #tempfile.mkdtemp('clean-patch')
@@ -811,7 +817,8 @@
cmt = series.commits[count]
cmt.patch = fname
cmt.count = count
- result = fix_patch(backup_dir, fname, series, cmt)
+ result = fix_patch(backup_dir, fname, series, cmt,
+ keep_change_id=keep_change_id)
if result:
print('%d warning%s for %s:' %
(len(result), 's' if len(result) > 1 else '', fname))
diff --git a/tools/patman/patman.rst b/tools/patman/patman.rst
index 038b651..a8b317e 100644
--- a/tools/patman/patman.rst
+++ b/tools/patman/patman.rst
@@ -371,11 +371,12 @@
Separate each tag with a comma.
Change-Id:
- This tag is stripped out but is used to generate the Message-Id
- of the emails that will be sent. When you keep the Change-Id the
- same you are asserting that this is a slightly different version
- (but logically the same patch) as other patches that have been
- sent out with the same Change-Id.
+ This tag is used to generate the Message-Id of the emails that
+ will be sent. When you keep the Change-Id the same you are
+ asserting that this is a slightly different version (but logically
+ the same patch) as other patches that have been sent out with the
+ same Change-Id. The Change-Id tag line is removed from outgoing
+ patches, unless the `keep_change_id` settings is set to `True`.
Various other tags are silently removed, like these Chrome OS and
Gerrit tags::
diff --git a/tools/patman/test_checkpatch.py b/tools/patman/test_checkpatch.py
index a8bb364..db7860f 100644
--- a/tools/patman/test_checkpatch.py
+++ b/tools/patman/test_checkpatch.py
@@ -18,19 +18,47 @@
class Line:
+ """Single changed line in one file in a patch
+
+ Args:
+ fname (str): Filename containing the added line
+ text (str): Text of the added line
+ """
def __init__(self, fname, text):
self.fname = fname
self.text = text
class PatchMaker:
+ """Makes a patch for checking with checkpatch.pl
+
+ The idea here is to create a patch which adds one line in one file,
+ intended to provoke a checkpatch error or warning. The base patch is empty
+ (i.e. invalid), so you should call add_line() to add at least one line.
+ """
def __init__(self):
+ """Set up the PatchMaker object
+
+ Properties:
+ lines (list of Line): List of lines to add to the patch. Note that
+ each line has both a file and some text associated with it,
+ since for simplicity we just add a single line for each file
+ """
self.lines = []
def add_line(self, fname, text):
+ """Add to the list of filename/line pairs"""
self.lines.append(Line(fname, text))
def get_patch_text(self):
+ """Build the patch text
+
+ Takes a base patch and adds a diffstat and patch for each filename/line
+ pair in the list.
+
+ Returns:
+ str: Patch text ready for submission to checkpatch
+ """
base = '''From 125b77450f4c66b8fd9654319520bbe795c9ef31 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 14 Jun 2020 09:45:14 -0600
@@ -75,6 +103,11 @@
return '\n'.join(lines)
def get_patch(self):
+ """Get the patch text and write it into a temporary file
+
+ Returns:
+ str: Filename containing the patch
+ """
inhandle, inname = tempfile.mkstemp()
infd = os.fdopen(inhandle, 'w')
infd.write(self.get_patch_text())
@@ -82,6 +115,22 @@
return inname
def run_checkpatch(self):
+ """Run checkpatch on the patch file
+
+ Returns:
+ namedtuple containing:
+ ok: False=failure, True=ok
+ problems: List of problems, each a dict:
+ 'type'; error or warning
+ 'msg': text message
+ 'file' : filename
+ 'line': line number
+ errors: Number of errors
+ warnings: Number of warnings
+ checks: Number of checks
+ lines: Number of lines
+ stdout: Full output of checkpatch
+ """
return checkpatch.check_patch(self.get_patch(), show_types=True)
@@ -160,6 +209,22 @@
rc = os.system('diff -u %s %s' % (inname, expname))
self.assertEqual(rc, 0)
+ os.remove(inname)
+
+ # Test whether the keep_change_id settings works.
+ inhandle, inname = tempfile.mkstemp()
+ infd = os.fdopen(inhandle, 'w', encoding='utf-8')
+ infd.write(data)
+ infd.close()
+
+ patchstream.fix_patch(None, inname, series.Series(), com,
+ keep_change_id=True)
+
+ with open(inname, 'r') as f:
+ content = f.read()
+ self.assertIn(
+ 'Change-Id: I80fe1d0c0b7dd10aa58ce5bb1d9290b6664d5413',
+ content)
os.remove(inname)
os.remove(expname)
@@ -238,7 +303,7 @@
+ * passed to kernel in the ATAGs
+ */
+
-+#include <common.h>
++#include <config.h>
+
+struct bootstage_record {
+ u32 time_us;
@@ -401,10 +466,15 @@
def test_barred_include_in_hdr(self):
"""Test for using a barred include in a header file"""
pm = PatchMaker()
- #pm.add_line('include/myfile.h', '#include <common.h>')
pm.add_line('include/myfile.h', '#include <dm.h>')
self.check_single_message(pm, 'BARRED_INCLUDE_IN_HDR', 'error')
+ def test_barred_include_common_h(self):
+ """Test for adding common.h to a file"""
+ pm = PatchMaker()
+ pm.add_line('include/myfile.h', '#include <common.h>')
+ self.check_single_message(pm, 'BARRED_INCLUDE_COMMON_H', 'error')
+
def test_config_is_enabled_config(self):
"""Test for accidental CONFIG_IS_ENABLED(CONFIG_*) calls"""
pm = PatchMaker()
diff --git a/tools/moveconfig.py b/tools/qconfig.py
similarity index 66%
rename from tools/moveconfig.py
rename to tools/qconfig.py
index 6cbecc3..04118d9 100755
--- a/tools/moveconfig.py
+++ b/tools/qconfig.py
@@ -5,17 +5,14 @@
#
"""
-Move config options from headers to defconfig files.
+Build and query a Kconfig database for boards.
See doc/develop/moveconfig.rst for documentation.
"""
from argparse import ArgumentParser
-import asteval
import collections
from contextlib import ExitStack
-import copy
-import difflib
import doctest
import filecmp
import fnmatch
@@ -32,9 +29,11 @@
import time
import unittest
+import asteval
from buildman import bsettings
from buildman import kconfiglib
from buildman import toolchain
+from u_boot_pylib import terminal
SHOW_GNU_MAKE = 'scripts/show-gnu-make'
SLEEP_TIME=0.03
@@ -44,30 +43,9 @@
STATE_AUTOCONF = 2
STATE_SAVEDEFCONFIG = 3
-ACTION_MOVE = 0
-ACTION_NO_ENTRY = 1
-ACTION_NO_ENTRY_WARN = 2
-ACTION_NO_CHANGE = 3
-
-COLOR_BLACK = '0;30'
-COLOR_RED = '0;31'
-COLOR_GREEN = '0;32'
-COLOR_BROWN = '0;33'
-COLOR_BLUE = '0;34'
-COLOR_PURPLE = '0;35'
-COLOR_CYAN = '0;36'
-COLOR_LIGHT_GRAY = '0;37'
-COLOR_DARK_GRAY = '1;30'
-COLOR_LIGHT_RED = '1;31'
-COLOR_LIGHT_GREEN = '1;32'
-COLOR_YELLOW = '1;33'
-COLOR_LIGHT_BLUE = '1;34'
-COLOR_LIGHT_PURPLE = '1;35'
-COLOR_LIGHT_CYAN = '1;36'
-COLOR_WHITE = '1;37'
-
AUTO_CONF_PATH = 'include/config/auto.conf'
-CONFIG_DATABASE = 'moveconfig.db'
+CONFIG_DATABASE = 'qconfig.db'
+FAILED_LIST = 'qconfig.failed'
CONFIG_LEN = len('CONFIG_')
@@ -196,111 +174,6 @@
return defconfigs
-def color_text(color_enabled, color, string):
- """Return colored string."""
- if color_enabled:
- # LF should not be surrounded by the escape sequence.
- # Otherwise, additional whitespace or line-feed might be printed.
- return '\n'.join([ '\033[' + color + 'm' + s + '\033[0m' if s else ''
- for s in string.split('\n') ])
- return string
-
-def show_diff(alines, blines, file_path, color_enabled):
- """Show unidified diff.
-
- Args:
- alines (list of str): A list of lines (before)
- blines (list of str): A list of lines (after)
- file_path (str): Path to the file
- color_enabled (bool): Display the diff in color
- """
- diff = difflib.unified_diff(alines, blines,
- fromfile=os.path.join('a', file_path),
- tofile=os.path.join('b', file_path))
-
- for line in diff:
- if line.startswith('-') and not line.startswith('--'):
- print(color_text(color_enabled, COLOR_RED, line))
- elif line.startswith('+') and not line.startswith('++'):
- print(color_text(color_enabled, COLOR_GREEN, line))
- else:
- print(line)
-
-def extend_matched_lines(lines, matched, pre_patterns, post_patterns,
- extend_pre, extend_post):
- """Extend matched lines if desired patterns are found before/after already
- matched lines.
-
- Args:
- lines (list of str): list of lines handled.
- matched (list of int): list of line numbers that have been already
- matched (will be updated by this function)
- pre_patterns (list of re.Pattern): list of regular expression that should
- be matched as preamble
- post_patterns (list of re.Pattern): list of regular expression that should
- be matched as postamble
- extend_pre (bool): Add the line number of matched preamble to the matched
- list
- extend_post (bool): Add the line number of matched postamble to the
- matched list
- """
- extended_matched = []
-
- j = matched[0]
-
- for i in matched:
- if i == 0 or i < j:
- continue
- j = i
- while j in matched:
- j += 1
- if j >= len(lines):
- break
-
- for pat in pre_patterns:
- if pat.search(lines[i - 1]):
- break
- else:
- # not matched
- continue
-
- for pat in post_patterns:
- if pat.search(lines[j]):
- break
- else:
- # not matched
- continue
-
- if extend_pre:
- extended_matched.append(i - 1)
- if extend_post:
- extended_matched.append(j)
-
- matched += extended_matched
- matched.sort()
-
-def confirm(args, prompt):
- """Ask the user to confirm something
-
- Args:
- args (Namespace ): program arguments
-
- Returns:
- bool: True to confirm, False to cancel/stop
- """
- if not args.yes:
- while True:
- choice = input(f'{prompt} [y/n]: ')
- choice = choice.lower()
- print(choice)
- if choice in ('y', 'n'):
- break
-
- if choice == 'n':
- return False
-
- return True
-
def write_file(fname, data):
"""Write data to a file
@@ -321,7 +194,7 @@
Args:
fname (str): Filename to read from
- as_lines: Return file contents as a list of lines
+ as_lines (bool): Return file contents as a list of lines
skip_unicode (bool): True to report unicode errors and continue
Returns:
@@ -336,163 +209,13 @@
try:
if as_lines:
return [line.rstrip('\n') for line in inf.readlines()]
- else:
- return inf.read()
- except UnicodeDecodeError as e:
+ return inf.read()
+ except UnicodeDecodeError as exc:
if not skip_unicode:
raise
- print("Failed on file %s': %s" % (fname, e))
+ print(f"Failed on file '{fname}: {exc}")
return None
-def cleanup_empty_blocks(header_path, args):
- """Clean up empty conditional blocks
-
- Args:
- header_path (str): path to the cleaned file.
- args (Namespace): program arguments
- """
- pattern = re.compile(r'^\s*#\s*if.*$\n^\s*#\s*endif.*$\n*', flags=re.M)
- data = read_file(header_path, as_lines=False, skip_unicode=True)
- if data is None:
- return
-
- new_data = pattern.sub('\n', data)
-
- show_diff(data.splitlines(True), new_data.splitlines(True), header_path,
- args.color)
-
- if args.dry_run:
- return
-
- if new_data != data:
- write_file(header_path, new_data)
-
-def cleanup_one_header(header_path, patterns, args):
- """Clean regex-matched lines away from a file.
-
- Args:
- header_path: path to the cleaned file.
- patterns: list of regex patterns. Any lines matching to these
- patterns are deleted.
- args (Namespace): program arguments
- """
- lines = read_file(header_path, skip_unicode=True)
- if lines is None:
- return
-
- matched = []
- for i, line in enumerate(lines):
- if i - 1 in matched and lines[i - 1].endswith('\\'):
- matched.append(i)
- continue
- for pattern in patterns:
- if pattern.search(line):
- matched.append(i)
- break
-
- if not matched:
- return
-
- # remove empty #ifdef ... #endif, successive blank lines
- pattern_if = re.compile(r'#\s*if(def|ndef)?\b') # #if, #ifdef, #ifndef
- pattern_elif = re.compile(r'#\s*el(if|se)\b') # #elif, #else
- pattern_endif = re.compile(r'#\s*endif\b') # #endif
- pattern_blank = re.compile(r'^\s*$') # empty line
-
- while True:
- old_matched = copy.copy(matched)
- extend_matched_lines(lines, matched, [pattern_if],
- [pattern_endif], True, True)
- extend_matched_lines(lines, matched, [pattern_elif],
- [pattern_elif, pattern_endif], True, False)
- extend_matched_lines(lines, matched, [pattern_if, pattern_elif],
- [pattern_blank], False, True)
- extend_matched_lines(lines, matched, [pattern_blank],
- [pattern_elif, pattern_endif], True, False)
- extend_matched_lines(lines, matched, [pattern_blank],
- [pattern_blank], True, False)
- if matched == old_matched:
- break
-
- tolines = copy.copy(lines)
-
- for i in reversed(matched):
- tolines.pop(i)
-
- show_diff(lines, tolines, header_path, args.color)
-
- if args.dry_run:
- return
-
- write_file(header_path, tolines)
-
-def cleanup_headers(configs, args):
- """Delete config defines from board headers.
-
- Args:
- configs: A list of CONFIGs to remove.
- args (Namespace): program arguments
- """
- if not confirm(args, 'Clean up headers?'):
- return
-
- patterns = []
- for config in configs:
- patterns.append(re.compile(r'#\s*define\s+%s\b' % config))
- patterns.append(re.compile(r'#\s*undef\s+%s\b' % config))
-
- for dir in 'include', 'arch', 'board':
- for (dirpath, dirnames, filenames) in os.walk(dir):
- if dirpath == os.path.join('include', 'generated'):
- continue
- for filename in filenames:
- if not filename.endswith(('~', '.dts', '.dtsi', '.bin',
- '.elf','.aml','.dat')):
- header_path = os.path.join(dirpath, filename)
- # This file contains UTF-16 data and no CONFIG symbols
- if header_path == 'include/video_font_data.h':
- continue
- cleanup_one_header(header_path, patterns, args)
- cleanup_empty_blocks(header_path, args)
-
-def find_matching(patterns, line):
- for pat in patterns:
- if pat.search(line):
- return True
- return False
-
-def cleanup_readme(configs, args):
- """Delete config description in README
-
- Args:
- configs: A list of CONFIGs to remove.
- args (Namespace): program arguments
- """
- if not confirm(args, 'Clean up README?'):
- return
-
- patterns = []
- for config in configs:
- patterns.append(re.compile(r'^\s+%s' % config))
-
- lines = read_file('README')
-
- found = False
- newlines = []
- for line in lines:
- if not found:
- found = find_matching(patterns, line)
- if found:
- continue
-
- if found and re.search(r'^\s+CONFIG', line):
- found = False
-
- if not found:
- newlines.append(line)
-
- write_file('README', newlines)
-
def try_expand(line):
"""If value looks like an expression, try expanding it
Otherwise just return the existing value
@@ -506,10 +229,10 @@
val= val.strip('\"')
if re.search(r'[*+-/]|<<|SZ_+|\(([^\)]+)\)', val):
newval = hex(aeval(val))
- print('\tExpanded expression %s to %s' % (val, newval))
+ print(f'\tExpanded expression {val} to {newval}')
return cfg+'='+newval
except:
- print('\tFailed to expand expression in %s' % line)
+ print(f'\tFailed to expand expression in {line}')
return line
@@ -519,23 +242,36 @@
"""Progress Indicator"""
- def __init__(self, total):
+ def __init__(self, col, total):
"""Create a new progress indicator.
Args:
- total: A number of defconfig files to process.
+ color_enabled (bool): True for colour output
+ total (int): A number of defconfig files to process.
"""
+ self.col = col
self.current = 0
+ self.good = 0
self.total = total
- def inc(self):
- """Increment the number of processed defconfig files."""
+ def inc(self, success):
+ """Increment the number of processed defconfig files.
+ Args:
+ success (bool): True if processing succeeded
+ """
+ self.good += success
self.current += 1
def show(self):
"""Display the progress."""
- print(' %d defconfigs out of %d\r' % (self.current, self.total), end=' ')
+ if self.current != self.total:
+ line = self.col.build(self.col.GREEN, f'{self.good:5d}')
+ line += self.col.build(self.col.RED,
+ f'{self.current - self.good:5d}')
+ line += self.col.build(self.col.MAGENTA,
+ f'/{self.total - self.current}')
+ print(f'{line} \r', end='')
sys.stdout.flush()
@@ -559,15 +295,13 @@
re_arch = re.compile(r'CONFIG_SYS_ARCH="(.*)"')
re_cpu = re.compile(r'CONFIG_SYS_CPU="(.*)"')
- def __init__(self, configs, args, build_dir):
+ def __init__(self, args, build_dir):
"""Create a new parser.
Args:
- configs: A list of CONFIGs to move.
args (Namespace): program arguments
build_dir: Build directory.
"""
- self.configs = configs
self.args = args
self.dotconfig = os.path.join(build_dir, '.config')
self.autoconf = os.path.join(build_dir, 'include', 'autoconf.mk')
@@ -585,13 +319,13 @@
arch = ''
cpu = ''
for line in read_file(self.dotconfig):
- m = self.re_arch.match(line)
- if m:
- arch = m.group(1)
+ m_arch = self.re_arch.match(line)
+ if m_arch:
+ arch = m_arch.group(1)
continue
- m = self.re_cpu.match(line)
- if m:
- cpu = m.group(1)
+ m_cpu = self.re_cpu.match(line)
+ if m_cpu:
+ cpu = m_cpu.group(1)
if not arch:
return None
@@ -602,155 +336,6 @@
return arch
- def parse_one_config(self, config, dotconfig_lines, autoconf_lines):
- """Parse .config, defconfig, include/autoconf.mk for one config.
-
- This function looks for the config options in the lines from
- defconfig, .config, and include/autoconf.mk in order to decide
- which action should be taken for this defconfig.
-
- Args:
- config: CONFIG name to parse.
- dotconfig_lines: lines from the .config file.
- autoconf_lines: lines from the include/autoconf.mk file.
-
- Returns:
- A tupple of the action for this defconfig and the line
- matched for the config.
- """
- not_set = '# %s is not set' % config
-
- for line in autoconf_lines:
- line = line.rstrip()
- if line.startswith(config + '='):
- new_val = line
- break
- else:
- new_val = not_set
-
- new_val = try_expand(new_val)
-
- for line in dotconfig_lines:
- line = line.rstrip()
- if line.startswith(config + '=') or line == not_set:
- old_val = line
- break
- else:
- if new_val == not_set:
- return (ACTION_NO_ENTRY, config)
- else:
- return (ACTION_NO_ENTRY_WARN, config)
-
- # If this CONFIG is neither bool nor trisate
- if old_val[-2:] != '=y' and old_val[-2:] != '=m' and old_val != not_set:
- # tools/scripts/define2mk.sed changes '1' to 'y'.
- # This is a problem if the CONFIG is int type.
- # Check the type in Kconfig and handle it correctly.
- if new_val[-2:] == '=y':
- new_val = new_val[:-1] + '1'
-
- return (ACTION_NO_CHANGE if old_val == new_val else ACTION_MOVE,
- new_val)
-
- def update_dotconfig(self):
- """Parse files for the config options and update the .config.
-
- This function parses the generated .config and include/autoconf.mk
- searching the target options.
- Move the config option(s) to the .config as needed.
-
- Args:
- defconfig: defconfig name.
-
- Returns:
- Return a tuple of (updated flag, log string).
- The "updated flag" is True if the .config was updated, False
- otherwise. The "log string" shows what happend to the .config.
- """
-
- results = []
- updated = False
- suspicious = False
- rm_files = [self.config_autoconf, self.autoconf]
-
- if self.args.spl:
- if os.path.exists(self.spl_autoconf):
- autoconf_path = self.spl_autoconf
- rm_files.append(self.spl_autoconf)
- else:
- for f in rm_files:
- os.remove(f)
- return (updated, suspicious,
- color_text(self.args.color, COLOR_BROWN,
- "SPL is not enabled. Skipped.") + '\n')
- else:
- autoconf_path = self.autoconf
-
- dotconfig_lines = read_file(self.dotconfig)
-
- autoconf_lines = read_file(autoconf_path)
-
- for config in self.configs:
- result = self.parse_one_config(config, dotconfig_lines,
- autoconf_lines)
- results.append(result)
-
- log = ''
-
- for (action, value) in results:
- if action == ACTION_MOVE:
- actlog = "Move '%s'" % value
- log_color = COLOR_LIGHT_GREEN
- elif action == ACTION_NO_ENTRY:
- actlog = '%s is not defined in Kconfig. Do nothing.' % value
- log_color = COLOR_LIGHT_BLUE
- elif action == ACTION_NO_ENTRY_WARN:
- actlog = '%s is not defined in Kconfig (suspicious). Do nothing.' % value
- log_color = COLOR_YELLOW
- suspicious = True
- elif action == ACTION_NO_CHANGE:
- actlog = "'%s' is the same as the define in Kconfig. Do nothing." \
- % value
- log_color = COLOR_LIGHT_PURPLE
- else:
- sys.exit('Internal Error. This should not happen.')
-
- log += color_text(self.args.color, log_color, actlog) + '\n'
-
- with open(self.dotconfig, 'a', encoding='utf-8') as out:
- for (action, value) in results:
- if action == ACTION_MOVE:
- out.write(value + '\n')
- updated = True
-
- self.results = results
- for f in rm_files:
- os.remove(f)
-
- return (updated, suspicious, log)
-
- def check_defconfig(self):
- """Check the defconfig after savedefconfig
-
- Returns:
- Return additional log if moved CONFIGs were removed again by
- 'make savedefconfig'.
- """
-
- log = ''
-
- defconfig_lines = read_file(self.defconfig)
-
- for (action, value) in self.results:
- if action != ACTION_MOVE:
- continue
- if not value in defconfig_lines:
- log += color_text(self.args.color, COLOR_YELLOW,
- "'%s' was removed by savedefconfig.\n" %
- value)
-
- return log
-
class DatabaseThread(threading.Thread):
"""This thread processes results from Slot threads.
@@ -788,13 +373,12 @@
for faster processing.
"""
- def __init__(self, toolchains, configs, args, progress, devnull,
- make_cmd, reference_src_dir, db_queue):
+ def __init__(self, toolchains, args, progress, devnull, make_cmd,
+ reference_src_dir, db_queue, col):
"""Create a new process slot.
Args:
toolchains: Toolchains object containing toolchains.
- configs: A list of CONFIGs to move.
args: Program arguments
progress: A progress indicator.
devnull: A file object of '/dev/null'.
@@ -802,6 +386,7 @@
reference_src_dir: Determine the true starting config state from this
source tree.
db_queue: output queue to write config info for the database
+ col (terminal.Color): Colour object
"""
self.toolchains = toolchains
self.args = args
@@ -811,10 +396,14 @@
self.make_cmd = (make_cmd, 'O=' + self.build_dir)
self.reference_src_dir = reference_src_dir
self.db_queue = db_queue
- self.parser = KconfigParser(configs, args, self.build_dir)
+ self.col = col
+ self.parser = KconfigParser(args, self.build_dir)
self.state = STATE_IDLE
self.failed_boards = set()
- self.suspicious_boards = set()
+ self.defconfig = None
+ self.log = []
+ self.current_src_dir = None
+ self.proc = None
def __del__(self):
"""Delete the working directory
@@ -827,7 +416,7 @@
If the subprocess is still running, wait until it finishes.
"""
if self.state != STATE_IDLE:
- while self.ps.poll() == None:
+ while self.proc.poll() is None:
pass
shutil.rmtree(self.build_dir)
@@ -839,7 +428,7 @@
the slot is occupied (i.e. the current subprocess is still running).
Args:
- defconfig: defconfig name.
+ defconfig (str): defconfig name.
Returns:
Return True on success or False on failure
@@ -848,7 +437,7 @@
return False
self.defconfig = defconfig
- self.log = ''
+ self.log = []
self.current_src_dir = self.reference_src_dir
self.do_defconfig()
return True
@@ -872,10 +461,10 @@
if self.state == STATE_IDLE:
return True
- if self.ps.poll() == None:
+ if self.proc.poll() is None:
return False
- if self.ps.poll() != 0:
+ if self.proc.poll() != 0:
self.handle_error()
elif self.state == STATE_DEFCONFIG:
if self.reference_src_dir and not self.current_src_dir:
@@ -895,16 +484,16 @@
else:
sys.exit('Internal Error. This should not happen.')
- return True if self.state == STATE_IDLE else False
+ return self.state == STATE_IDLE
def handle_error(self):
"""Handle error cases."""
- self.log += color_text(self.args.color, COLOR_LIGHT_RED,
- 'Failed to process.\n')
+ self.log.append(self.col.build(self.col.RED, 'Failed to process',
+ bright=True))
if self.args.verbose:
- self.log += color_text(self.args.color, COLOR_LIGHT_CYAN,
- self.ps.stderr.read().decode())
+ for line in self.proc.stderr.read().decode().splitlines():
+ self.log.append(self.col.build(self.col.CYAN, line, True))
self.finish(False)
def do_defconfig(self):
@@ -912,9 +501,9 @@
cmd = list(self.make_cmd)
cmd.append(self.defconfig)
- self.ps = subprocess.Popen(cmd, stdout=self.devnull,
- stderr=subprocess.PIPE,
- cwd=self.current_src_dir)
+ self.proc = subprocess.Popen(cmd, stdout=self.devnull,
+ stderr=subprocess.PIPE,
+ cwd=self.current_src_dir)
self.state = STATE_DEFCONFIG
def do_autoconf(self):
@@ -922,20 +511,21 @@
arch = self.parser.get_arch()
try:
- toolchain = self.toolchains.Select(arch)
+ tchain = self.toolchains.Select(arch)
except ValueError:
- self.log += color_text(self.args.color, COLOR_YELLOW,
- "Tool chain for '%s' is missing. Do nothing.\n" % arch)
+ self.log.append(self.col.build(
+ self.col.YELLOW,
+ f"Tool chain for '{arch}' is missing: do nothing"))
self.finish(False)
return
- env = toolchain.MakeEnvironment(False)
+ env = tchain.MakeEnvironment(False)
cmd = list(self.make_cmd)
cmd.append('KCONFIG_IGNORE_DUPLICATES=1')
cmd.append(AUTO_CONF_PATH)
- self.ps = subprocess.Popen(cmd, stdout=self.devnull, env=env,
- stderr=subprocess.PIPE,
- cwd=self.current_src_dir)
+ self.proc = subprocess.Popen(cmd, stdout=self.devnull, env=env,
+ stderr=subprocess.PIPE,
+ cwd=self.current_src_dir)
self.state = STATE_AUTOCONF
def do_build_db(self):
@@ -950,41 +540,25 @@
def do_savedefconfig(self):
"""Update the .config and run 'make savedefconfig'."""
-
- (updated, suspicious, log) = self.parser.update_dotconfig()
- if suspicious:
- self.suspicious_boards.add(self.defconfig)
- self.log += log
-
- if not self.args.force_sync and not updated:
+ if not self.args.force_sync:
self.finish(True)
return
- if updated:
- self.log += color_text(self.args.color, COLOR_LIGHT_GREEN,
- 'Syncing by savedefconfig...\n')
- else:
- self.log += 'Syncing by savedefconfig (forced by option)...\n'
cmd = list(self.make_cmd)
cmd.append('savedefconfig')
- self.ps = subprocess.Popen(cmd, stdout=self.devnull,
- stderr=subprocess.PIPE)
+ self.proc = subprocess.Popen(cmd, stdout=self.devnull,
+ stderr=subprocess.PIPE)
self.state = STATE_SAVEDEFCONFIG
def update_defconfig(self):
"""Update the input defconfig and go back to the idle state."""
-
- log = self.parser.check_defconfig()
- if log:
- self.suspicious_boards.add(self.defconfig)
- self.log += log
orig_defconfig = os.path.join('configs', self.defconfig)
new_defconfig = os.path.join(self.build_dir, 'defconfig')
updated = not filecmp.cmp(orig_defconfig, new_defconfig)
if updated:
- self.log += color_text(self.args.color, COLOR_LIGHT_BLUE,
- 'defconfig was updated.\n')
+ self.log.append(
+ self.col.build(self.col.BLUE, 'defconfig updated', bright=True))
if not self.args.dry_run and updated:
shutil.move(new_defconfig, orig_defconfig)
@@ -994,25 +568,30 @@
"""Display log along with progress and go to the idle state.
Args:
- success: Should be True when the defconfig was processed
+ success (bool): Should be True when the defconfig was processed
successfully, or False when it fails.
"""
# output at least 30 characters to hide the "* defconfigs out of *".
- log = self.defconfig.ljust(30) + '\n'
+ name = self.defconfig[:-len('_defconfig')]
+ if self.log:
- log += '\n'.join([ ' ' + s for s in self.log.split('\n') ])
- # Some threads are running in parallel.
- # Print log atomically to not mix up logs from different threads.
- print(log, file=(sys.stdout if success else sys.stderr))
+ # Put the first log line on the first line
+ log = name.ljust(20) + ' ' + self.log[0]
+
+ if len(self.log) > 1:
+ log += '\n' + '\n'.join([' ' + s for s in self.log[1:]])
+ # Some threads are running in parallel.
+ # Print log atomically to not mix up logs from different threads.
+ print(log, file=(sys.stdout if success else sys.stderr))
if not success:
if self.args.exit_on_error:
sys.exit('Exit on error.')
# If --exit-on-error flag is not set, skip this board and continue.
# Record the failed board.
- self.failed_boards.add(self.defconfig)
+ self.failed_boards.add(name)
- self.progress.inc()
+ self.progress.inc(success)
self.progress.show()
self.state = STATE_IDLE
@@ -1021,42 +600,38 @@
"""
return self.failed_boards
- def get_suspicious_boards(self):
- """Returns a set of boards (defconfigs) with possible misconversion.
- """
- return self.suspicious_boards - self.failed_boards
-
class Slots:
"""Controller of the array of subprocess slots."""
- def __init__(self, toolchains, configs, args, progress,
- reference_src_dir, db_queue):
+ def __init__(self, toolchains, args, progress, reference_src_dir, db_queue,
+ col):
"""Create a new slots controller.
Args:
- toolchains: Toolchains object containing toolchains.
- configs: A list of CONFIGs to move.
- args: Program arguments
- progress: A progress indicator.
- reference_src_dir: Determine the true starting config state from this
- source tree.
- db_queue: output queue to write config info for the database
+ toolchains (Toolchains): Toolchains object containing toolchains
+ args (Namespace): Program arguments
+ progress (Progress): A progress indicator.
+ reference_src_dir (str): Determine the true starting config state
+ from this source tree (None for none)
+ db_queue (Queue): output queue to write config info for the database
+ col (terminal.Color): Colour object
"""
self.args = args
self.slots = []
+ self.progress = progress
+ self.col = col
devnull = subprocess.DEVNULL
make_cmd = get_make_cmd()
- for i in range(args.jobs):
- self.slots.append(Slot(toolchains, configs, args, progress,
- devnull, make_cmd, reference_src_dir,
- db_queue))
+ for _ in range(args.jobs):
+ self.slots.append(Slot(toolchains, args, progress, devnull,
+ make_cmd, reference_src_dir, db_queue, col))
def add(self, defconfig):
"""Add a new subprocess if a vacant slot is found.
Args:
- defconfig: defconfig name to be put into.
+ defconfig (str): defconfig name to be put into.
Returns:
Return True on success or False on failure
@@ -1089,42 +664,17 @@
ret = False
return ret
- def show_failed_boards(self):
- """Display all of the failed boards (defconfigs)."""
+ def write_failed_boards(self):
+ """Show the results of processing"""
boards = set()
- output_file = 'moveconfig.failed'
for slot in self.slots:
boards |= slot.get_failed_boards()
if boards:
- boards = '\n'.join(boards) + '\n'
- msg = 'The following boards were not processed due to error:\n'
- msg += boards
- msg += '(the list has been saved in %s)\n' % output_file
- print(color_text(self.args.color, COLOR_LIGHT_RED,
- msg), file=sys.stderr)
+ boards = '\n'.join(sorted(boards)) + '\n'
+ write_file(FAILED_LIST, boards)
- write_file(output_file, boards)
-
- def show_suspicious_boards(self):
- """Display all boards (defconfigs) with possible misconversion."""
- boards = set()
- output_file = 'moveconfig.suspicious'
-
- for slot in self.slots:
- boards |= slot.get_suspicious_boards()
-
- if boards:
- boards = '\n'.join(boards) + '\n'
- msg = 'The following boards might have been converted incorrectly.\n'
- msg += 'It is highly recommended to check them manually:\n'
- msg += boards
- msg += '(the list has been saved in %s)\n' % output_file
- print(color_text(self.args.color, COLOR_YELLOW,
- msg), file=sys.stderr)
-
- write_file(output_file, boards)
class ReferenceSource:
@@ -1140,8 +690,9 @@
print('Cloning git repo to a separate work directory...')
subprocess.check_output(['git', 'clone', os.getcwd(), '.'],
cwd=self.src_dir)
- print("Checkout '%s' to build the original autoconf.mk." % \
- subprocess.check_output(['git', 'rev-parse', '--short', commit]).strip())
+ rev = subprocess.check_output(['git', 'rev-parse', '--short',
+ commit]).strip()
+ print(f"Checkout '{rev}' to build the original autoconf.mk.")
subprocess.check_output(['git', 'checkout', commit],
stderr=subprocess.STDOUT, cwd=self.src_dir)
@@ -1160,24 +711,18 @@
return self.src_dir
-def move_config(toolchains, configs, args, db_queue):
- """Move config options to defconfig files.
+def move_config(toolchains, args, db_queue, col):
+ """Build database or sync config options to defconfig files.
Args:
- configs: A list of CONFIGs to move.
- args: Program arguments
- """
- if len(configs) == 0:
- if args.force_sync:
- print('No CONFIG is specified. You are probably syncing defconfigs.', end=' ')
- elif args.build_db:
- print('Building %s database' % CONFIG_DATABASE)
- else:
- print('Neither CONFIG nor --force-sync is specified. Nothing will happen.', end=' ')
- else:
- print('Move ' + ', '.join(configs), end=' ')
- print('(jobs: %d)\n' % args.jobs)
+ toolchains (Toolchains): Toolchains to use
+ args (Namespace): Program arguments
+ db_queue (Queue): Queue for database updates
+ col (terminal.Color): Colour object
+ Returns:
+ Progress: Progress indicator
+ """
if args.git_ref:
reference_src = ReferenceSource(args.git_ref)
reference_src_dir = reference_src.get_dir()
@@ -1189,9 +734,8 @@
else:
defconfigs = get_all_defconfigs()
- progress = Progress(len(defconfigs))
- slots = Slots(toolchains, configs, args, progress, reference_src_dir,
- db_queue)
+ progress = Progress(col, len(defconfigs))
+ slots = Slots(toolchains, args, progress, reference_src_dir, db_queue, col)
# Main loop to process defconfig files:
# Add a new subprocess into a vacant slot.
@@ -1206,25 +750,24 @@
while not slots.empty():
time.sleep(SLEEP_TIME)
- print('')
- slots.show_failed_boards()
- slots.show_suspicious_boards()
+ slots.write_failed_boards()
+ return progress
def find_kconfig_rules(kconf, config, imply_config):
"""Check whether a config has a 'select' or 'imply' keyword
Args:
- kconf: Kconfiglib.Kconfig object
- config: Name of config to check (without CONFIG_ prefix)
- imply_config: Implying config (without CONFIG_ prefix) which may or
- may not have an 'imply' for 'config')
+ kconf (Kconfiglib.Kconfig): Kconfig object
+ config (str): Name of config to check (without CONFIG_ prefix)
+ imply_config (str): Implying config (without CONFIG_ prefix) which may
+ or may not have an 'imply' for 'config')
Returns:
Symbol object for 'config' if found, else None
"""
sym = kconf.syms.get(imply_config)
if sym:
- for sel, cond in (sym.selects + sym.implies):
+ for sel, _ in (sym.selects + sym.implies):
if sel.name == config:
return sym
return None
@@ -1236,54 +779,55 @@
to add an 'imply' for 'config' to that part of the Kconfig.
Args:
- kconf: Kconfiglib.Kconfig object
- config: Name of config to check (without CONFIG_ prefix)
- imply_config: Implying config (without CONFIG_ prefix) which may or
- may not have an 'imply' for 'config')
+ kconf (Kconfiglib.Kconfig): Kconfig object
+ config (str): Name of config to check (without CONFIG_ prefix)
+ imply_config (str): Implying config (without CONFIG_ prefix) which may
+ or may not have an 'imply' for 'config')
Returns:
tuple:
- filename of Kconfig file containing imply_config, or None if none
- line number within the Kconfig file, or 0 if none
- message indicating the result
+ str: filename of Kconfig file containing imply_config, or None if
+ none
+ int: line number within the Kconfig file, or 0 if none
+ str: message indicating the result
"""
sym = kconf.syms.get(imply_config)
if not sym:
return 'cannot find sym'
nodes = sym.nodes
if len(nodes) != 1:
- return '%d locations' % len(nodes)
+ return f'{len(nodes)} locations'
node = nodes[0]
fname, linenum = node.filename, node.linenr
cwd = os.getcwd()
if cwd and fname.startswith(cwd):
fname = fname[len(cwd) + 1:]
- file_line = ' at %s:%d' % (fname, linenum)
+ file_line = f' at {fname}:{linenum}'
data = read_file(fname)
- if data[linenum - 1] != 'config %s' % imply_config:
- return None, 0, 'bad sym format %s%s' % (data[linenum], file_line)
- return fname, linenum, 'adding%s' % file_line
+ if data[linenum - 1] != f'config {imply_config}':
+ return None, 0, f'bad sym format {data[linenum]}{file_line})'
+ return fname, linenum, f'adding{file_line}'
def add_imply_rule(config, fname, linenum):
"""Add a new 'imply' option to a Kconfig
Args:
- config: config option to add an imply for (without CONFIG_ prefix)
- fname: Kconfig filename to update
- linenum: Line number to place the 'imply' before
+ config (str): config option to add an imply for (without CONFIG_ prefix)
+ fname (str): Kconfig filename to update
+ linenum (int): Line number to place the 'imply' before
Returns:
Message indicating the result
"""
- file_line = ' at %s:%d' % (fname, linenum)
+ file_line = f' at {fname}:{linenum}'
data = read_file(fname)
linenum -= 1
for offset, line in enumerate(data[linenum:]):
if line.strip().startswith('help') or not line:
- data.insert(linenum + offset, '\timply %s' % config)
+ data.insert(linenum + offset, f'\timply {config}')
write_file(fname, data)
- return 'added%s' % file_line
+ return f'added{file_line}'
return 'could not insert%s'
@@ -1356,7 +900,7 @@
all x86 boards will have that option, avoiding adding CONFIG_CMD_IRQ to
each of the x86 defconfig files.
- This function uses the moveconfig database to find such options. It
+ This function uses the qconfig database to find such options. It
displays a list of things that could possibly imply those in the list.
The algorithm ignores any that start with CONFIG_TARGET since these
typically refer to only a few defconfigs (often one). It also does not
@@ -1392,21 +936,20 @@
if add_imply and add_imply != 'all':
add_imply = add_imply.split(',')
- all_configs, all_defconfigs, config_db, defconfig_db = read_database()
+ all_configs, all_defconfigs, _, defconfig_db = read_database()
# Work through each target config option in turn, independently
for config in config_list:
defconfigs = defconfig_db.get(config)
if not defconfigs:
- print('%s not found in any defconfig' % config)
+ print(f'{config} not found in any defconfig')
continue
# Get the set of defconfigs without this one (since a config cannot
# imply itself)
non_defconfigs = all_defconfigs - defconfigs
num_defconfigs = len(defconfigs)
- print('%s found in %d/%d defconfigs' % (config, num_defconfigs,
- len(all_configs)))
+ print(f'{config} found in {num_defconfigs}/{len(all_configs)} defconfigs')
# This will hold the results: key=config, value=defconfigs containing it
imply_configs = {}
@@ -1452,7 +995,7 @@
# skip imply_config because prev is a superset
skip = True
break
- elif count > prev_count:
+ if count > prev_count:
# delete prev because imply_config is a superset
del imply_configs[prev]
if not skip:
@@ -1487,7 +1030,7 @@
fname, linenum = nodes[0].filename, nodes[0].linenr
if cwd and fname.startswith(cwd):
fname = fname[len(cwd) + 1:]
- kconfig_info = '%s:%d' % (fname, linenum)
+ kconfig_info = f'{fname}:{linenum}'
if skip_added:
show = False
else:
@@ -1513,8 +1056,8 @@
add_list[fname].append(linenum)
if show and kconfig_info != 'skip':
- print('%5d : %-30s%-25s %s' % (num_common, iconfig.ljust(30),
- kconfig_info, missing_str))
+ print(f'{num_common:5d} : '
+ f'{iconfig.ljust(30):-30s}{kconfig_info:-25s} {missing_str}')
# Having collected a list of things to add, now we add them. We process
# each file from the largest line number to the smallest so that
@@ -1553,7 +1096,7 @@
is preceded by a tilde (~) then it must be false, otherwise it must
be true)
"""
- all_configs, all_defconfigs, config_db, defconfig_db = read_database()
+ _, all_defconfigs, config_db, _ = read_database()
# Start with all defconfigs
out = all_defconfigs
@@ -1597,19 +1140,19 @@
>>> prefix_config('A123')
'CONFIG_A123'
"""
- op = ''
+ oper = ''
if cfg[0] == '~':
- op = cfg[0]
+ oper = cfg[0]
cfg = cfg[1:]
if not cfg.startswith('CONFIG_'):
cfg = 'CONFIG_' + cfg
- return op + cfg
+ return oper + cfg
-RE_MK_CONFIGS = re.compile('CONFIG_(\$\(SPL_(?:TPL_)?\))?([A-Za-z0-9_]*)')
-RE_IFDEF = re.compile('(ifdef|ifndef)')
-RE_C_CONFIGS = re.compile('CONFIG_([A-Za-z0-9_]*)')
-RE_CONFIG_IS = re.compile('CONFIG_IS_ENABLED\(([A-Za-z0-9_]*)\)')
+RE_MK_CONFIGS = re.compile(r'CONFIG_(\$\(SPL_(?:TPL_)?\))?([A-Za-z0-9_]*)')
+RE_IFDEF = re.compile(r'(ifdef|ifndef)')
+RE_C_CONFIGS = re.compile(r'CONFIG_([A-Za-z0-9_]*)')
+RE_CONFIG_IS = re.compile(r'CONFIG_IS_ENABLED\(([A-Za-z0-9_]*)\)')
class ConfigUse:
def __init__(self, cfg, is_spl, fname, rest):
@@ -1651,14 +1194,12 @@
fname_uses = {}
for fname, rest in fnames:
m_iter = RE_MK_CONFIGS.finditer(rest)
- found = False
- for m in m_iter:
- found = True
- real_opt = m.group(2)
+ for mat in m_iter:
+ real_opt = mat.group(2)
if real_opt == '':
continue
is_spl = False
- if m.group(1):
+ if mat.group(1):
is_spl = True
use = ConfigUse(real_opt, is_spl, fname, rest)
if fname not in fname_uses:
@@ -1694,10 +1235,12 @@
>>> RE_CONFIG_IS.search('#if CONFIG_IS_ENABLED(OF_PLATDATA)').groups()
('OF_PLATDATA',)
"""
+ fname = None
+ rest = None
+
def add_uses(m_iter, is_spl):
- for m in m_iter:
- found = True
- real_opt = m.group(1)
+ for mat in m_iter:
+ real_opt = mat.group(1)
if real_opt == '':
continue
use = ConfigUse(real_opt, is_spl, fname, rest)
@@ -1754,7 +1297,7 @@
"""
# Make sure we know about all the options
not_found = collections.defaultdict(list)
- for use, rest in all_uses.items():
+ for use, _ in all_uses.items():
name = use.cfg
if name in IGNORE_SYMS:
continue
@@ -1766,7 +1309,6 @@
# If it is an SPL symbol, try prepending all SPL_ prefixes to
# find at least one SPL symbol
if use.is_spl:
- add_to_dict = False
for prefix in SPL_PREFIXES:
try_name = prefix + name
sym = kconf.syms.get(try_name)
@@ -1784,7 +1326,6 @@
elif not use.is_spl:
check = False
else: # MODE_NORMAL
- debug = False
sym = kconf.syms.get(name)
if not sym:
proper_name = is_not_proper(name)
@@ -1825,7 +1366,7 @@
print(f'Scanning source in {path}')
args = ['git', 'grep', '-E', r'IS_ENABLED|\bCONFIG']
with subprocess.Popen(args, stdout=subprocess.PIPE) as proc:
- out, err = proc.communicate()
+ out, _ = proc.communicate()
lines = out.splitlines()
re_fname = re.compile('^([^:]*):(.*)')
src_list = []
@@ -1859,7 +1400,7 @@
print(f'Not sure how to handle file {fname}')
# Scan the Makefiles
- all_uses, fname_uses = scan_makefiles(mk_list)
+ all_uses, _ = scan_makefiles(mk_list)
spl_not_found = set()
proper_not_found = set()
@@ -1872,15 +1413,15 @@
print('\nCONFIG options present in Makefiles but not Kconfig (SPL):')
not_found = check_not_found(all_uses, MODE_SPL)
show_uses(not_found)
- spl_not_found |= set([is_not_proper(key) or key for key in not_found.keys()])
+ spl_not_found |= {is_not_proper(key) or key for key in not_found.keys()}
print('\nCONFIG options used as Proper in Makefiles but without a non-SPL_ variant:')
not_found = check_not_found(all_uses, MODE_PROPER)
show_uses(not_found)
- proper_not_found |= set([key for key in not_found.keys()])
+ proper_not_found |= {not_found.keys()}
# Scan the source code
- all_uses, fname_uses = scan_src_files(src_list)
+ all_uses, _ = scan_src_files(src_list)
# Make sure we know about all the options
print('\nCONFIG options present in source but not Kconfig:')
@@ -1890,12 +1431,12 @@
print('\nCONFIG options present in source but not Kconfig (SPL):')
not_found = check_not_found(all_uses, MODE_SPL)
show_uses(not_found)
- spl_not_found |= set([is_not_proper(key) or key for key in not_found.keys()])
+ spl_not_found |= {is_not_proper(key) or key for key in not_found.keys()}
print('\nCONFIG options used as Proper in source but without a non-SPL_ variant:')
not_found = check_not_found(all_uses, MODE_PROPER)
show_uses(not_found)
- proper_not_found |= set([key for key in not_found.keys()])
+ proper_not_found |= {not_found.keys()}
print('\nCONFIG options used as SPL but without an SPL_ variant:')
for item in sorted(spl_not_found):
@@ -1907,12 +1448,14 @@
# Write out the updated information
if do_update:
- with open(os.path.join(path, 'scripts', 'conf_nospl'), 'w') as out:
+ with open(os.path.join(path, 'scripts', 'conf_nospl'), 'w',
+ encoding='utf-8') as out:
print('# These options should not be enabled in SPL builds\n',
file=out)
for item in sorted(spl_not_found):
print(item, file=out)
- with open(os.path.join(path, 'scripts', 'conf_noproper'), 'w') as out:
+ with open(os.path.join(path, 'scripts', 'conf_noproper'), 'w',
+ encoding='utf-8') as out:
print('# These options should not be enabled in Proper builds\n',
file=out)
for item in sorted(proper_not_found):
@@ -1938,10 +1481,10 @@
'implying others')
parser.add_argument('-b', '--build-db', action='store_true', default=False,
help='build a CONFIG database')
- parser.add_argument('-c', '--color', action='store_true', default=False,
- help='display the log in color')
parser.add_argument('-C', '--commit', action='store_true', default=False,
help='Create a git commit for the operation')
+ parser.add_argument('--nocolour', action='store_true', default=False,
+ help="don't display the log in colour")
parser.add_argument('-d', '--defconfigs', type=str,
help='a file containing a list of defconfigs to move, '
"one per line (for example 'snow_defconfig') "
@@ -1951,9 +1494,6 @@
help='exit immediately on any error')
parser.add_argument('-f', '--find', action='store_true', default=False,
help='Find boards with a given config combination')
- parser.add_argument('-H', '--headers-only', dest='cleanup_headers_only',
- action='store_true', default=False,
- help='only cleanup the headers')
parser.add_argument('-i', '--imply', action='store_true', default=False,
help='find options which imply others')
parser.add_argument('-I', '--imply-flags', type=str, default='',
@@ -1981,26 +1521,27 @@
parser.add_argument('configs', nargs='*')
args = parser.parse_args()
- configs = args.configs
if args.test:
sys.argv = [sys.argv[0]]
- fail, count = doctest.testmod()
+ fail, _ = doctest.testmod()
if fail:
return 1
unittest.main()
+ col = terminal.Color(terminal.COLOR_NEVER if args.nocolour
+ else terminal.COLOR_IF_TERMINAL)
+
if args.scan_source:
do_scan_source(os.getcwd(), args.update)
- return
+ return 0
- if not any((len(configs), args.force_sync, args.build_db, args.imply,
- args.find)):
+ if not any((args.force_sync, args.build_db, args.imply, args.find)):
parser.print_usage()
sys.exit(1)
# prefix the option name with CONFIG_ if missing
- configs = [prefix_config(cfg) for cfg in configs]
+ configs = [prefix_config(cfg) for cfg in args.configs]
check_top_directory()
@@ -2013,40 +1554,36 @@
for flag in args.imply_flags.split(','):
bad = flag not in IMPLY_FLAGS
if bad:
- print("Invalid flag '%s'" % flag)
+ print(f"Invalid flag '{flag}'")
if flag == 'help' or bad:
print("Imply flags: (separate with ',')")
for name, info in IMPLY_FLAGS.items():
- print(' %-15s: %s' % (name, info[1]))
+ print(f' {name:-15s}: {info[1]}')
parser.print_usage()
sys.exit(1)
imply_flags |= IMPLY_FLAGS[flag][0]
do_imply_config(configs, args.add_imply, imply_flags, args.skip_added)
- return
+ return 0
if args.find:
do_find_config(configs)
- return
+ return 0
+ # We are either building the database or forcing a sync of defconfigs
config_db = {}
db_queue = queue.Queue()
- t = DatabaseThread(config_db, db_queue)
- t.setDaemon(True)
- t.start()
+ dbt = DatabaseThread(config_db, db_queue)
+ dbt.daemon = True
+ dbt.start()
- if not args.cleanup_headers_only:
- check_clean_directory()
- bsettings.setup('')
- toolchains = toolchain.Toolchains()
- toolchains.GetSettings()
- toolchains.Scan(verbose=False)
- move_config(toolchains, configs, args, db_queue)
- db_queue.join()
-
- if configs:
- cleanup_headers(configs, args)
- cleanup_readme(configs, args)
+ check_clean_directory()
+ bsettings.setup('')
+ toolchains = toolchain.Toolchains()
+ toolchains.GetSettings()
+ toolchains.Scan(verbose=False)
+ progress = move_config(toolchains, args, db_queue, col)
+ db_queue.join()
if args.commit:
subprocess.call(['git', 'add', '-u'])
@@ -2060,13 +1597,28 @@
msg += '\n\nRsync all defconfig files using moveconfig.py'
subprocess.call(['git', 'commit', '-s', '-m', msg])
+ failed = progress.total - progress.good
+ failure = f'{failed} failed, ' if failed else ''
if args.build_db:
- with open(CONFIG_DATABASE, 'w', encoding='utf-8') as fd:
+ with open(CONFIG_DATABASE, 'w', encoding='utf-8') as outf:
for defconfig, configs in config_db.items():
- fd.write('%s\n' % defconfig)
+ outf.write(f'{defconfig}\n')
for config in sorted(configs.keys()):
- fd.write(' %s=%s\n' % (config, configs[config]))
- fd.write('\n')
+ outf.write(f' {config}={configs[config]}\n')
+ outf.write('\n')
+ print(col.build(
+ col.RED if failed else col.GREEN,
+ f'{failure}{len(config_db)} boards written to {CONFIG_DATABASE}'))
+ else:
+ if failed:
+ print(col.build(col.RED, f'{failure}see {FAILED_LIST}', True))
+ else:
+ # Add enough spaces to overwrite the progress indicator
+ print(col.build(
+ col.GREEN, f'{progress.total} processed ', bright=True))
+
+ return 0
+
if __name__ == '__main__':
sys.exit(main())
diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c
index f230ec5..613abd2 100644
--- a/tools/relocate-rela.c
+++ b/tools/relocate-rela.c
@@ -24,6 +24,30 @@
#define R_AARCH64_RELATIVE 1027
#endif
+#ifndef EM_M68K
+#define EM_M68K 4
+#endif
+
+#ifndef R_68K_NONE
+#define R_68K_NONE 0
+#endif
+
+#ifndef R_68K_32
+#define R_68K_32 1
+#endif
+
+#ifndef R_68K_GLOB_DAT
+#define R_68K_GLOB_DAT 20
+#endif
+
+#ifndef R_68K_JMP_SLOT
+#define R_68K_JMP_SLOT 21
+#endif
+
+#ifndef R_68K_RELATIVE
+#define R_68K_RELATIVE 22
+#endif
+
#ifndef EM_MICROBLAZE
#define EM_MICROBLAZE 189
#endif
@@ -46,6 +70,7 @@
static int ei_class;
static int ei_data;
+static int machine;
static uint64_t rela_start, rela_end, text_base, dyn_start;
@@ -78,6 +103,14 @@
return be32_to_cpu(data);
}
+static uint32_t cpu_to_elf32(uint32_t data)
+{
+ if (ei_data == ELFDATA2LSB)
+ return cpu_to_le32(data);
+
+ return cpu_to_be32(data);
+}
+
static bool supported_rela(Elf64_Rela *rela)
{
uint64_t mask = 0xffffffffULL; /* would be different on 32-bit */
@@ -103,7 +136,7 @@
uint64_t sh_addr, sh_offset, sh_size;
Elf64_Half sh_index, sh_num;
Elf64_Shdr *sh_table; /* Elf symbol table */
- int ret, i, machine;
+ int ret, i;
char *sh_str;
debug("64bit version\n");
@@ -237,7 +270,7 @@
uint32_t sh_addr, sh_offset, sh_size;
Elf32_Half sh_index, sh_num;
Elf32_Shdr *sh_table; /* Elf symbol table */
- int ret, i, machine;
+ int ret, i;
char *sh_str;
debug("32bit version\n");
@@ -254,12 +287,20 @@
machine = elf16_to_cpu(header.e_machine);
debug("Machine %d\n", machine);
- if (machine != EM_MICROBLAZE) {
+ if (machine != EM_MICROBLAZE && machine != EM_M68K) {
fprintf(stderr, "%s: Not supported machine type\n", argv[0]);
return 30;
}
text_base = elf32_to_cpu(header.e_entry);
+ /*
+ * M68K ELF entry point is MONITOR_BASE, not TEXT_BASE.
+ * TEXT_BASE is always MONITOR_BASE &~ 0x7ff, so clear
+ * those bits here.
+ */
+ if (machine == EM_M68K)
+ text_base &= ~0x7ff;
+
section_header_base = elf32_to_cpu(header.e_shoff);
section_header_size = elf16_to_cpu(header.e_shentsize) *
elf16_to_cpu(header.e_shnum);
@@ -480,25 +521,44 @@
debug("Type:\t");
- switch (*type) {
- case R_MICROBLAZE_32:
- debug("R_MICROBLAZE_32\n");
- return true;
- case R_MICROBLAZE_GLOB_DAT:
- debug("R_MICROBLAZE_GLOB_DAT\n");
- return true;
- case R_MICROBLAZE_NONE:
- debug("R_MICROBLAZE_NONE - ignoring - do nothing\n");
- return false;
- case R_MICROBLAZE_REL:
- debug("R_MICROBLAZE_REL\n");
- return true;
- default:
- fprintf(stderr, "warning: unsupported relocation type %"
- PRIu32 " at %" PRIx32 "\n", *type, rela->r_offset);
-
- return false;
+ if (machine == EM_M68K) {
+ switch (*type) {
+ case R_68K_32:
+ debug("R_68K_32\n");
+ return true;
+ case R_68K_GLOB_DAT:
+ debug("R_68K_GLOB_DAT\n");
+ return true;
+ case R_68K_JMP_SLOT:
+ debug("R_68K_JMP_SLOT\n");
+ return true;
+ case R_68K_NONE:
+ debug("R_68K_NONE - ignoring - do nothing\n");
+ return false;
+ case R_68K_RELATIVE:
+ debug("R_68K_RELATIVE\n");
+ return true;
+ }
+ } else {
+ switch (*type) {
+ case R_MICROBLAZE_32:
+ debug("R_MICROBLAZE_32\n");
+ return true;
+ case R_MICROBLAZE_GLOB_DAT:
+ debug("R_MICROBLAZE_GLOB_DAT\n");
+ return true;
+ case R_MICROBLAZE_NONE:
+ debug("R_MICROBLAZE_NONE - ignoring - do nothing\n");
+ return false;
+ case R_MICROBLAZE_REL:
+ debug("R_MICROBLAZE_REL\n");
+ return true;
+ }
}
+ fprintf(stderr, "warning: unsupported relocation type %"
+ PRIu32 " at %" PRIx32 "\n", *type, rela->r_offset);
+
+ return false;
}
static int rela_elf32(char **argv, FILE *f)
@@ -561,8 +621,8 @@
debug("Addr:\t0x%" PRIx32 "\n", addr);
- switch (type) {
- case R_MICROBLAZE_REL:
+ if ((machine == EM_M68K && type == R_68K_RELATIVE) ||
+ (machine == EM_MICROBLAZE && type == R_MICROBLAZE_REL)) {
if (fseek(f, addr, SEEK_SET) < 0) {
fprintf(stderr, "%s: %s: seek to %"
PRIx32 " failed: %s\n",
@@ -577,9 +637,12 @@
argv[0], argv[1], addr);
return 4;
}
- break;
- case R_MICROBLAZE_32:
- case R_MICROBLAZE_GLOB_DAT:
+ } else if ((machine == EM_M68K &&
+ (type == R_68K_32 || type == R_68K_GLOB_DAT ||
+ type == R_68K_JMP_SLOT)) ||
+ (machine == EM_MICROBLAZE &&
+ (type == R_MICROBLAZE_32 ||
+ type == R_MICROBLAZE_GLOB_DAT))) {
/* global symbols read it and add reloc offset */
index = swrela.r_info >> 8;
pos_dyn = dyn_start + sizeof(Elf32_Sym) * index;
@@ -602,14 +665,16 @@
}
debug("Symbol description:\n");
- debug(" st_name:\t0x%x\n", symbols.st_name);
- debug(" st_value:\t0x%x\n", symbols.st_value);
- debug(" st_size:\t0x%x\n", symbols.st_size);
+ debug(" st_name:\t0x%x\n", elf32_to_cpu(symbols.st_name));
+ debug(" st_value:\t0x%x\n", elf32_to_cpu(symbols.st_value));
+ debug(" st_size:\t0x%x\n", elf32_to_cpu(symbols.st_size));
- value = swrela.r_addend + symbols.st_value;
+ value = swrela.r_addend + elf32_to_cpu(symbols.st_value);
debug("Value:\t0x%x\n", value);
+ value = cpu_to_elf32(value);
+
if (fseek(f, addr, SEEK_SET) < 0) {
fprintf(stderr, "%s: %s: seek to %"
PRIx32 " failed: %s\n",
@@ -622,12 +687,11 @@
argv[0], argv[1], addr);
return 4;
}
-
- break;
- case R_MICROBLAZE_NONE:
+ } else if (machine == EM_M68K && type == R_68K_NONE) {
+ debug("R_68K_NONE - skip\n");
+ } else if (machine == EM_MICROBLAZE && type == R_MICROBLAZE_NONE) {
debug("R_MICROBLAZE_NONE - skip\n");
- break;
- default:
+ } else {
fprintf(stderr, "warning: unsupported relocation type %"
PRIu32 " at %" PRIx32 "\n",
type, rela.r_offset);
diff --git a/tools/renesas_spkgimage.c b/tools/renesas_spkgimage.c
index 5cd81dd..ce3b2b2 100644
--- a/tools/renesas_spkgimage.c
+++ b/tools/renesas_spkgimage.c
@@ -147,7 +147,8 @@
/* Check the marker bytes */
if (memcmp(header->marker, marker, 4)) {
- fprintf(stderr, "Error: invalid marker bytes\n");
+ if (param->type == IH_TYPE_RENESAS_SPKG)
+ fprintf(stderr, "Error: invalid marker bytes\n");
return -EINVAL;
}
diff --git a/tools/sfspl.c b/tools/sfspl.c
new file mode 100644
index 0000000..c76420c
--- /dev/null
+++ b/tools/sfspl.c
@@ -0,0 +1,174 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
+ *
+ * The StarFive JH7110 requires to prepend a header to u-boot-spl.bin describing
+ * the payload length and CRC32.
+ *
+ * This module implements support in mkimage and dumpimage for this file format.
+ *
+ * StarFive's spl_tool available under GPL-2.0-and-later at
+ * https://github.com/starfive-tech/Tools implements writing the same file
+ * format and served as a reference.
+ */
+
+#include <compiler.h>
+#include <fcntl.h>
+#include <u-boot/crc.h>
+#include <unistd.h>
+#include "imagetool.h"
+
+#define DEFAULT_VERSION 0x01010101
+#define DEFAULT_BACKUP 0x200000U
+#define DEFAULT_OFFSET 0x240
+
+/**
+ * struct spl_hdr - header for SPL on JH7110
+ *
+ * All fields are low-endian.
+ */
+struct spl_hdr {
+ /** @offset: offset to SPL header (0x240) */
+ unsigned int offset;
+ /** @bkp_offs: address of backup SPL, defaults to DEFAULT_BACKUP */
+ unsigned int bkp_offs;
+ /** @zero1: set to zero */
+ unsigned int zero1[159];
+ /** @version: header version, defaults to DEFAULT_VERSION */
+ unsigned int version;
+ /** @file_size: file size */
+ unsigned int file_size;
+ /** @hdr_size: size of the file header (0x400) */
+ unsigned int hdr_size;
+ /** @crc32: CRC32 */
+ unsigned int crc32;
+ /** @zero2: set to zero */
+ unsigned int zero2[91];
+};
+
+static int sfspl_check_params(struct image_tool_params *params)
+{
+ /* Only the RISC-V architecture is supported */
+ if (params->Aflag && params->arch != IH_ARCH_RISCV)
+ return EXIT_FAILURE;
+
+ return EXIT_SUCCESS;
+}
+
+static int sfspl_verify_header(unsigned char *buf, int size,
+ struct image_tool_params *params)
+{
+ struct spl_hdr *hdr = (void *)buf;
+ unsigned int hdr_size = le32_to_cpu(hdr->hdr_size);
+ unsigned int file_size = le32_to_cpu(hdr->file_size);
+ unsigned int crc = le32_to_cpu(hdr->crc32);
+ unsigned int crc_check;
+
+ if (size < 0 ||
+ (size_t)size < sizeof(struct spl_hdr) ||
+ (size_t)size < hdr_size + file_size) {
+ printf("Truncated file\n");
+ return EXIT_FAILURE;
+ }
+ if (hdr->version != DEFAULT_VERSION) {
+ printf("Unknown file format version\n");
+ return EXIT_FAILURE;
+ }
+ crc_check = crc32(0, &buf[hdr_size], size - hdr_size);
+ if (crc_check != crc) {
+ printf("Incorrect CRC32\n");
+ return EXIT_FAILURE;
+ }
+
+ return EXIT_SUCCESS;
+}
+
+static void sfspl_print_header(const void *buf,
+ struct image_tool_params *params)
+{
+ struct spl_hdr *hdr = (void *)buf;
+ unsigned int hdr_size = le32_to_cpu(hdr->hdr_size);
+ unsigned int file_size = le32_to_cpu(hdr->file_size);
+
+ printf("Header size: %u\n", hdr_size);
+ printf("Payload size: %u\n", file_size);
+}
+
+static int sfspl_image_extract_subimage(void *ptr,
+ struct image_tool_params *params)
+{
+ struct spl_hdr *hdr = (void *)ptr;
+ unsigned char *buf = ptr;
+ int fd, ret = EXIT_SUCCESS;
+ unsigned int hdr_size = le32_to_cpu(hdr->hdr_size);
+ unsigned int file_size = le32_to_cpu(hdr->file_size);
+
+ if (params->pflag) {
+ printf("Invalid image index %d\n", params->pflag);
+ return EXIT_FAILURE;
+ }
+
+ fd = open(params->outfile, O_WRONLY | O_CREAT | O_TRUNC, 0644);
+ if (fd == -1) {
+ perror("Cannot open file");
+ return EXIT_FAILURE;
+ }
+ if (write(fd, &buf[hdr_size], file_size) != file_size) {
+ perror("Cannot write file");
+ ret = EXIT_FAILURE;
+ }
+ close(fd);
+
+ return ret;
+}
+
+static int sfspl_check_image_type(uint8_t type)
+{
+ if (type == IH_TYPE_STARFIVE_SPL)
+ return EXIT_SUCCESS;
+
+ return EXIT_FAILURE;
+}
+
+static void sfspl_set_header(void *buf, struct stat *sbuf, int infd,
+ struct image_tool_params *params)
+{
+ struct spl_hdr *hdr = buf;
+ unsigned int file_size;
+ unsigned int crc;
+
+ file_size = params->file_size - sizeof(struct spl_hdr);
+ crc = crc32(0, &((unsigned char *)buf)[sizeof(struct spl_hdr)],
+ file_size);
+
+ hdr->offset = cpu_to_le32(DEFAULT_OFFSET);
+ hdr->bkp_offs = cpu_to_le32(DEFAULT_BACKUP);
+ hdr->version = cpu_to_le32(DEFAULT_VERSION);
+ hdr->file_size = cpu_to_le32(file_size);
+ hdr->hdr_size = cpu_to_le32(sizeof(struct spl_hdr));
+ hdr->crc32 = cpu_to_le32(crc);
+}
+
+static int sfspl_vrec_header(struct image_tool_params *params,
+ struct image_type_params *tparams)
+{
+ tparams->hdr = calloc(sizeof(struct spl_hdr), 1);
+
+ /* No padding */
+ return 0;
+}
+
+U_BOOT_IMAGE_TYPE(
+ sfspl, /* id */
+ "StarFive SPL Image", /* name */
+ sizeof(struct spl_hdr), /* header_size */
+ NULL, /* header */
+ sfspl_check_params, /* check_params */
+ sfspl_verify_header, /* verify header */
+ sfspl_print_header, /* print header */
+ sfspl_set_header, /* set header */
+ sfspl_image_extract_subimage, /* extract_subimage */
+ sfspl_check_image_type, /* check_image_type */
+ NULL, /* fflag_handle */
+ sfspl_vrec_header /* vrec_header */
+);
diff --git a/tools/u_boot_pylib/command.py b/tools/u_boot_pylib/command.py
index 9bbfc5b..bbe95d8 100644
--- a/tools/u_boot_pylib/command.py
+++ b/tools/u_boot_pylib/command.py
@@ -105,9 +105,7 @@
last_pipe.communicate_filter(output_func))
if result.stdout and oneline:
result.output = result.stdout.rstrip(b'\r\n')
- result.return_code = last_pipe.wait()
- else:
- result.return_code = os.waitpid(last_pipe.pid, 0)[1]
+ result.return_code = last_pipe.wait()
if raise_on_error and result.return_code:
raise Exception("Error running '%s'" % user_pipestr)
return result.to_output(binary)
