| 10 registers, 56 instructions: |
| 0 r0 = splat 3F000000 (0.5) |
| 1 r1 = uniform32 ptr0 4 |
| 2 r2 = uniform32 ptr0 8 |
| 3 r3 = uniform32 ptr0 C |
| 4 r4 = splat 0 (0) |
| 5 r5 = splat 3F800000 (1) |
| 6 r6 = splat 40000000 (2) |
| 7 r6 = mul_f32 r3 r6 |
| 8 r6 = sub_f32 r6 r5 |
| 9 r7 = splat 7FFFFFFF (nan) |
| 10 r6 = bit_and r6 r7 |
| 11 r6 = sub_f32 r5 r6 |
| 12 r6 = mul_f32 r2 r6 |
| 13 r2 = splat 3F2AAAAB (0.66666669) |
| 14 r8 = splat 3EAAAAAB (0.33333334) |
| 15 r2 = add_f32 r1 r2 |
| 16 r8 = add_f32 r1 r8 |
| 17 r9 = floor r1 |
| 18 r9 = sub_f32 r1 r9 |
| 19 r1 = floor r2 |
| 20 r1 = sub_f32 r2 r1 |
| 21 r2 = floor r8 |
| 22 r2 = sub_f32 r8 r2 |
| 23 r8 = splat 40C00000 (6) |
| 24 r9 = mul_f32 r9 r8 |
| 25 r1 = mul_f32 r1 r8 |
| 26 r8 = mul_f32 r2 r8 |
| 27 r2 = splat 40400000 (3) |
| 28 r9 = sub_f32 r9 r2 |
| 29 r1 = sub_f32 r1 r2 |
| 30 r2 = sub_f32 r8 r2 |
| 31 r9 = bit_and r9 r7 |
| 32 r1 = bit_and r1 r7 |
| 33 r7 = bit_and r2 r7 |
| 34 r9 = sub_f32 r9 r5 |
| 35 r1 = sub_f32 r1 r5 |
| 36 r7 = sub_f32 r7 r5 |
| 37 r9 = min_f32 r9 r5 |
| 38 r9 = max_f32 r4 r9 |
| 39 r1 = min_f32 r1 r5 |
| 40 r1 = max_f32 r4 r1 |
| 41 r7 = min_f32 r7 r5 |
| 42 r7 = max_f32 r4 r7 |
| 43 r9 = sub_f32 r9 r0 |
| 44 r1 = sub_f32 r1 r0 |
| 45 r0 = sub_f32 r7 r0 |
| 46 r9 = mul_f32 r6 r9 |
| 47 r1 = mul_f32 r6 r1 |
| 48 r0 = mul_f32 r6 r0 |
| 49 r9 = add_f32 r3 r9 |
| 50 r1 = add_f32 r3 r1 |
| 51 r0 = add_f32 r3 r0 |
| loop: |
| 52 store32 ptr1 r9 |
| 53 store32 ptr2 r1 |
| 54 store32 ptr3 r0 |
| 55 store32 ptr4 r5 |
