Merge changes Ice960cbe,Icc0d8ee4

* changes:
  bochs/bios: Fix the mask value used when writing to MTRR_PHYSMASK MSR
  bochs/bios: Fix build
diff --git a/bochs/bios/rombios32.c b/bochs/bios/rombios32.c
index f8de96d..c0e85a0 100644
--- a/bochs/bios/rombios32.c
+++ b/bochs/bios/rombios32.c
@@ -83,6 +83,12 @@
 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
 
+#define MTRR_MEMTYPE_UC 0
+#define MTRR_MEMTYPE_WC 1
+#define MTRR_MEMTYPE_WT 4
+#define MTRR_MEMTYPE_WP 5
+#define MTRR_MEMTYPE_WB 6
+
 static inline void outl(int addr, int val)
 {
     asm volatile ("outl %1, %w0" : : "d" (addr), "a" (val));
@@ -604,9 +610,10 @@
     wrmsr_smp(MSR_MTRRfix4K_F0000, 0);
     wrmsr_smp(MSR_MTRRfix4K_F8000, 0);
     /* Mark 3.5-4GB as UC, anything not specified defaults to WB */
-    wrmsr_smp(MTRRphysBase_MSR(0), 0xe0000000ull | 0);
-    wrmsr_smp(MTRRphysMask_MSR(0), ~(0x20000000ull - 1) | 0x800);
-    wrmsr_smp(MSR_MTRRdefType, 0xc06);
+    wrmsr_smp(MTRRphysBase_MSR(0), 0xe0000000 | MTRR_MEMTYPE_UC);
+    /* Make sure no reserved bit set to '1 in MTRRphysMask_MSR */
+    wrmsr_smp(MTRRphysMask_MSR(0), (uint32_t)(~(0x20000000 - 1)) | 0x800);
+    wrmsr_smp(MSR_MTRRdefType, 0xc00 | MTRR_MEMTYPE_WB);
 }
 
 void ram_probe(void)
diff --git a/bochs/bios/rombios32.ld b/bochs/bios/rombios32.ld
index ff765c8..fe0414a 100644
--- a/bochs/bios/rombios32.ld
+++ b/bochs/bios/rombios32.ld
@@ -12,6 +12,7 @@
         /DISCARD/ : { *(.stab)
                      *(.stabstr)
                      *(.comment)
+                     *(.eh_frame)
                      *(.note)
                   }
 }