commit | 5e29087a9444d323bbab1ed7c7120ea7ef3739f2 | [log] [tgz] |
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author | Miodrag Dinic <miodrag.dinic@imgtec.com> | Thu Jun 11 16:21:18 2015 +0200 |
committer | Miodrag Dinic <miodrag.dinic@imgtec.com> | Tue Jun 16 12:08:43 2015 +0200 |
tree | 32d8a485a824551215176a39af4ec8fbecb9e421 | |
parent | 5f25a532cb29ca9090343b1fda8815f46be9b213 [diff] |
target-mips: fix updating BadVAddr for misaligned accesses Update BadVAddr correctly for the case of misaligned block accesses. The address reported by BadVAddr on page permission or TLB miss exceptions must be a byte address in the misaligned access for a page on which the exception is reported, but may be any such byte address. It is not required to be the lowest. Cherry-picked from PRPL QEMU : https://github.com/yongbok/prpl-qemu/commit/3e5e2b5f6affab2c367e8e774105877bc0f505f3 3e5e2b5f target-mips: fix updating BadVAddr for misaligned accesses Change-Id: I489effe5b4c0c693dca7a41a01157c3477cea47c