commit | b211ef108da1d434d434b04ffc3a5f60a14328f3 | [log] [tgz] |
---|---|---|
author | Leon Alrae <leon.alrae@imgtec.com> | Mon Jan 19 11:35:11 2015 +0100 |
committer | Miodrag Dinic <miodrag.dinic@imgtec.com> | Thu Feb 05 11:21:14 2015 +0100 |
tree | 4c22ceae88a850d08f360cc0af9d451b5ceb7a9a | |
parent | f521bd2470294784df3bfed9704661583ce40573 [diff] |
target-mips: add ERETNC instruction ERETNC is identical to ERET except that an ERETNC will not clear the LLbit that is set by execution of an LL instruction, and thus when placed between an LL and SC sequence, will never cause the SC to fail. Software can detect the presence of ERETNC by reading Config5.LLB Change-Id: Ifbd263b8cbd974d97c9f9f29488618117a16b460