commit 6c6413f3f973862c7275e7baecdd4bb6bcf430c9
author pvanhout <pierre.vanhoutryve@amd.com> Tue May 13 14:21:52 2025 +0200
committer pvanhout <pierre.vanhoutryve@amd.com> Tue May 13 14:22:07 2025 +0200
tree 1804b83a103eaf4b7d175c26338108f690070f33
parent e99ca74dc187a86671dd5b13c89fe2755465078a

[TableGen] Fixup #139715

The increment must be after the assert, not before, otherwise the assert fails everytime.

llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp

diff --git a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
index d11812b..f095982 100644
--- a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
@@ -2611,8 +2611,8 @@
     // (GICXXPred_Invalid + 1).
     unsigned ExpectedID = 0;
     for (const auto &ID : keys(AllCombineRules)) {
-      ++ExpectedID;
       assert(ExpectedID == ID && "combine rules are not ordered!");
+      ++ExpectedID;
       OS << "  " << getIsEnabledPredicateEnumName(ID) << EnumeratorSeparator;
       EnumeratorSeparator = ",\n";
     }