| commit | 343e3c6bb827fb2c969f7399bef448bd58e1e43f | [log] [tgz] |
|---|---|---|
| author | Paul Walker <paul.walker@arm.com> | Thu Jul 10 11:54:19 2025 +0100 |
| committer | GitHub <noreply@github.com> | Thu Jul 10 11:54:19 2025 +0100 |
| tree | c6388d72d6a5a908c0296ad915f7bac399f68862 | |
| parent | 628c7350108dbf207e22489ab2cd0324277afb2b [diff] |
[LLVM][CodeGen][SVE] Make bf16 fabs/fneg isel consistent with fp16. (#147543) Whilst at first glance there appears to be no native bfloat instructions to modify the sign bit, this is only the case when FEAT_AFP is implemented. Without this feature vector FABS/FNEG does not care about the floating point format beyond needing to know the position of the sign bit. From what I can see LLVM has no support for FEAT_AFP in terms of feature detection or ACLE builtins and so I believe the compiler can work under the assumption the feature is not enabled. In fact, if FEAT_AFP is enabled then I believe the current isel is likely broken for half, float and double anyway.
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