| commit | 1fec092fd74abc6fa7399da5bcf165d6249883f5 | [log] [tgz] |
|---|---|---|
| author | David Green <david.green@arm.com> | Sat Jun 21 07:01:35 2025 +0100 |
| committer | GitHub <noreply@github.com> | Sat Jun 21 07:01:35 2025 +0100 |
| tree | 35e80e63f85a577316ac493a94c4265d342a7454 | |
| parent | cb4f329004b8fc346bbd44ae8f9b94ff2e41998b [diff] |
[AArch64][GlobalISel] Allow selecting FPR index loads. (#143835) We can, through legalization of certain operations, end up generating G_INDEXED_LOAD into FPR registers that require entensions. SExt and ZExt will always opt for GPR, but anyext/noext can curently be set to FPR registers in regbankselect. As writing a subregister will set higher bits in the same register to 0, we can successfully handle zext and anyext on FPR registers, which is what this patch attempts to add.
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