commit 115f768b68d290995b3d9129f44e33cd7c8a11a6
author Philip Reames <preames@rivosinc.com> Tue Jul 22 09:29:20 2025 -0700
committer GitHub <noreply@github.com> Tue Jul 22 09:29:20 2025 -0700
tree c3f0e0e950f81953427a347b34979ff5b8b1b574
parent 75ec7250aaede77ba540ddde61a222f39b30008a

[RISCV] Correct alignment of one-active (de)interleave cases (#150052)

Noticed this while going to rewrite the load case as a DAG combine. I
don't have a test case which demonstrates this leading to a miscompile,
but it seems like it could be possible.

llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp

diff --git a/llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp b/llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
index 25817b6..878401e 100644
--- a/llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
@@ -232,6 +232,7 @@
         Builder.CreateIntrinsic(Intrinsic::experimental_vp_strided_load,
                                 {VTy, BasePtr->getType(), Stride->getType()},
                                 {BasePtr, Stride, Mask, VL});
+    Alignment = commonAlignment(Alignment, Indices[0] * ScalarSizeInBytes);
     CI->addParamAttr(0,
                      Attribute::getWithAlignment(CI->getContext(), Alignment));
     Shuffles[0]->replaceAllUsesWith(CI);
@@ -303,8 +304,9 @@
         Intrinsic::experimental_vp_strided_store,
         {Data->getType(), BasePtr->getType(), Stride->getType()},
         {Data, BasePtr, Stride, Mask, VL});
+    Align Alignment = commonAlignment(SI->getAlign(), Index * ScalarSizeInBytes);
     CI->addParamAttr(
-        1, Attribute::getWithAlignment(CI->getContext(), SI->getAlign()));
+        1, Attribute::getWithAlignment(CI->getContext(), Alignment));
 
     return true;
   }