radv: Expose helper for base pa_su_sc_mode_cntl.
So that we can feed it to the DGC shader for front face overrides.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17269>
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index edddfd4..8e5691f 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1576,11 +1576,11 @@
S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl));
}
-static void
-radv_emit_culling(struct radv_cmd_buffer *cmd_buffer, uint64_t states)
+uint32_t
+radv_get_pa_su_sc_mode_cntl(const struct radv_cmd_buffer *cmd_buffer)
{
unsigned pa_su_sc_mode_cntl = cmd_buffer->state.graphics_pipeline->pa_su_sc_mode_cntl;
- struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
+ const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
pa_su_sc_mode_cntl &= C_028814_CULL_FRONT &
C_028814_CULL_BACK &
@@ -1595,6 +1595,13 @@
S_028814_POLY_OFFSET_FRONT_ENABLE(d->depth_bias_enable) |
S_028814_POLY_OFFSET_BACK_ENABLE(d->depth_bias_enable) |
S_028814_POLY_OFFSET_PARA_ENABLE(d->depth_bias_enable);
+ return pa_su_sc_mode_cntl;
+}
+
+static void
+radv_emit_culling(struct radv_cmd_buffer *cmd_buffer, uint64_t states)
+{
+ unsigned pa_su_sc_mode_cntl = radv_get_pa_su_sc_mode_cntl(cmd_buffer);
radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL, pa_su_sc_mode_cntl);
}
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index a72f306..51ac906 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1680,6 +1680,7 @@
void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer, bool enable_occlusion_queries);
+uint32_t radv_get_pa_su_sc_mode_cntl(const struct radv_cmd_buffer *cmd_buffer);
unsigned radv_instance_rate_prolog_index(unsigned num_attributes, uint32_t instance_rate_inputs);
uint32_t radv_hash_vs_prolog(const void *key_);