radv: clear image implementation for compute queue

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
index 5994a7c..55f3a4b 100644
--- a/src/amd/vulkan/radv_meta.h
+++ b/src/amd/vulkan/radv_meta.h
@@ -163,6 +163,10 @@
 			  struct radv_meta_saved_compute_state *save);
 void radv_meta_end_itoi(struct radv_cmd_buffer *cmd_buffer,
 			struct radv_meta_saved_compute_state *save);
+void radv_meta_begin_cleari(struct radv_cmd_buffer *cmd_buffer,
+			    struct radv_meta_saved_compute_state *save);
+void radv_meta_end_cleari(struct radv_cmd_buffer *cmd_buffer,
+			  struct radv_meta_saved_compute_state *save);
 void radv_meta_image_to_buffer(struct radv_cmd_buffer *cmd_buffer,
 			       struct radv_meta_blit2d_surf *src,
 			       struct radv_meta_blit2d_buffer *dst,
@@ -179,6 +183,9 @@
 				 struct radv_meta_blit2d_surf *dst,
 				 unsigned num_rects,
 				 struct radv_meta_blit2d_rect *rects);
+void radv_meta_clear_image_cs(struct radv_cmd_buffer *cmd_buffer,
+			      struct radv_meta_blit2d_surf *dst,
+			      const VkClearColorValue *clear_color);
 
 void radv_decompress_depth_image_inplace(struct radv_cmd_buffer *cmd_buffer,
 					 struct radv_image *image,
diff --git a/src/amd/vulkan/radv_meta_bufimage.c b/src/amd/vulkan/radv_meta_bufimage.c
index 638208f..984b347 100644
--- a/src/amd/vulkan/radv_meta_bufimage.c
+++ b/src/amd/vulkan/radv_meta_bufimage.c
@@ -609,12 +609,159 @@
 	}
 }
 
+static nir_shader *
+build_nir_cleari_compute_shader(struct radv_device *dev)
+{
+	nir_builder b;
+	const struct glsl_type *img_type = glsl_sampler_type(GLSL_SAMPLER_DIM_2D,
+							     false,
+							     false,
+							     GLSL_TYPE_FLOAT);
+	nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
+	b.shader->info->name = ralloc_strdup(b.shader, "meta_cleari_cs");
+	b.shader->info->cs.local_size[0] = 16;
+	b.shader->info->cs.local_size[1] = 16;
+	b.shader->info->cs.local_size[2] = 1;
+
+	nir_variable *output_img = nir_variable_create(b.shader, nir_var_uniform,
+						       img_type, "out_img");
+	output_img->data.descriptor_set = 0;
+	output_img->data.binding = 0;
+
+	nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
+	nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
+	nir_ssa_def *block_size = nir_imm_ivec4(&b,
+						b.shader->info->cs.local_size[0],
+						b.shader->info->cs.local_size[1],
+						b.shader->info->cs.local_size[2], 0);
+
+	nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
+
+	nir_intrinsic_instr *clear_val = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
+	clear_val->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
+	clear_val->num_components = 4;
+	nir_ssa_dest_init(&clear_val->instr, &clear_val->dest, 4, 32, "clear_value");
+	nir_builder_instr_insert(&b, &clear_val->instr);
+
+	nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_store);
+	store->src[0] = nir_src_for_ssa(global_id);
+	store->src[1] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
+	store->src[2] = nir_src_for_ssa(&clear_val->dest.ssa);
+	store->variables[0] = nir_deref_var_create(store, output_img);
+
+	nir_builder_instr_insert(&b, &store->instr);
+	return b.shader;
+}
+
+static VkResult
+radv_device_init_meta_cleari_state(struct radv_device *device)
+{
+	VkResult result;
+	struct radv_shader_module cs = { .nir = NULL };
+
+	zero(device->meta_state.cleari);
+
+	cs.nir = build_nir_cleari_compute_shader(device);
+
+	/*
+	 * two descriptors one for the image being sampled
+	 * one for the buffer being written.
+	 */
+	VkDescriptorSetLayoutCreateInfo ds_create_info = {
+		.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
+		.bindingCount = 1,
+		.pBindings = (VkDescriptorSetLayoutBinding[]) {
+			{
+				.binding = 0,
+				.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
+				.descriptorCount = 1,
+				.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
+				.pImmutableSamplers = NULL
+			},
+		}
+	};
+
+	result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
+						&ds_create_info,
+						&device->meta_state.alloc,
+						&device->meta_state.cleari.img_ds_layout);
+	if (result != VK_SUCCESS)
+		goto fail;
+
+
+	VkPipelineLayoutCreateInfo pl_create_info = {
+		.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
+		.setLayoutCount = 1,
+		.pSetLayouts = &device->meta_state.cleari.img_ds_layout,
+		.pushConstantRangeCount = 1,
+		.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
+	};
+
+	result = radv_CreatePipelineLayout(radv_device_to_handle(device),
+					  &pl_create_info,
+					  &device->meta_state.alloc,
+					  &device->meta_state.cleari.img_p_layout);
+	if (result != VK_SUCCESS)
+		goto fail;
+
+	/* compute shader */
+
+	VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
+		.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
+		.stage = VK_SHADER_STAGE_COMPUTE_BIT,
+		.module = radv_shader_module_to_handle(&cs),
+		.pName = "main",
+		.pSpecializationInfo = NULL,
+	};
+
+	VkComputePipelineCreateInfo vk_pipeline_info = {
+		.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
+		.stage = pipeline_shader_stage,
+		.flags = 0,
+		.layout = device->meta_state.cleari.img_p_layout,
+	};
+
+	result = radv_CreateComputePipelines(radv_device_to_handle(device),
+					     radv_pipeline_cache_to_handle(&device->meta_state.cache),
+					     1, &vk_pipeline_info, NULL,
+					     &device->meta_state.cleari.pipeline);
+	if (result != VK_SUCCESS)
+		goto fail;
+
+	ralloc_free(cs.nir);
+	return VK_SUCCESS;
+fail:
+	ralloc_free(cs.nir);
+	return result;
+}
+
+static void
+radv_device_finish_meta_cleari_state(struct radv_device *device)
+{
+	if (device->meta_state.cleari.img_p_layout) {
+		radv_DestroyPipelineLayout(radv_device_to_handle(device),
+					   device->meta_state.cleari.img_p_layout,
+					   &device->meta_state.alloc);
+	}
+	if (device->meta_state.cleari.img_ds_layout) {
+		radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
+						device->meta_state.cleari.img_ds_layout,
+						&device->meta_state.alloc);
+	}
+	if (device->meta_state.cleari.pipeline) {
+		radv_DestroyPipeline(radv_device_to_handle(device),
+				     device->meta_state.cleari.pipeline,
+				     &device->meta_state.alloc);
+	}
+}
+
 void
 radv_device_finish_meta_bufimage_state(struct radv_device *device)
 {
 	radv_device_finish_meta_itob_state(device);
 	radv_device_finish_meta_btoi_state(device);
 	radv_device_finish_meta_itoi_state(device);
+	radv_device_finish_meta_cleari_state(device);
 }
 
 VkResult
@@ -627,18 +774,25 @@
 		return result;
 
 	result = radv_device_init_meta_btoi_state(device);
-	if (result != VK_SUCCESS) {
-		radv_device_finish_meta_itob_state(device);
-		return result;
-	}
+	if (result != VK_SUCCESS)
+		goto fail_itob;
 
 	result = radv_device_init_meta_itoi_state(device);
-	if (result != VK_SUCCESS) {
-		radv_device_finish_meta_itob_state(device);
-		radv_device_finish_meta_btoi_state(device);
-		return result;
-	}
+	if (result != VK_SUCCESS)
+		goto fail_btoi;
+
+	result = radv_device_init_meta_cleari_state(device);
+	if (result != VK_SUCCESS)
+		goto fail_itoi;
+
 	return VK_SUCCESS;
+fail_itoi:
+	radv_device_finish_meta_itoi_state(device);
+fail_btoi:
+	radv_device_finish_meta_btoi_state(device);
+fail_itob:
+	radv_device_finish_meta_itob_state(device);
+	return result;
 }
 
 void
@@ -669,6 +823,20 @@
 	radv_meta_restore_compute(save, cmd_buffer, 12);
 }
 
+void
+radv_meta_begin_cleari(struct radv_cmd_buffer *cmd_buffer,
+		       struct radv_meta_saved_compute_state *save)
+{
+	radv_meta_save_compute(save, cmd_buffer, 16);
+}
+
+void
+radv_meta_end_cleari(struct radv_cmd_buffer *cmd_buffer,
+		     struct radv_meta_saved_compute_state *save)
+{
+	radv_meta_restore_compute(save, cmd_buffer, 16);
+}
+
 static void
 create_iview(struct radv_cmd_buffer *cmd_buffer,
              struct radv_meta_blit2d_surf *surf,
@@ -1006,3 +1174,86 @@
 	}
 	radv_temp_descriptor_set_destroy(cmd_buffer->device, temps.set);
 }
+
+struct cleari_temps {
+	struct radv_image_view dst_iview;
+	VkDescriptorSet set;
+};
+
+static void
+cleari_bind_descriptors(struct radv_cmd_buffer *cmd_buffer,
+			struct cleari_temps *tmp)
+{
+	struct radv_device *device = cmd_buffer->device;
+	VkDevice vk_device = radv_device_to_handle(cmd_buffer->device);
+
+	radv_temp_descriptor_set_create(device, cmd_buffer,
+					device->meta_state.cleari.img_ds_layout,
+					&tmp->set);
+
+	radv_UpdateDescriptorSets(vk_device,
+				  1, /* writeCount */
+				  (VkWriteDescriptorSet[]) {
+					  {
+						  .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
+						  .dstSet = tmp->set,
+						  .dstBinding = 0,
+						  .dstArrayElement = 0,
+						  .descriptorCount = 1,
+						  .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
+						  .pImageInfo = (VkDescriptorImageInfo[]) {
+							  {
+								  .sampler = NULL,
+								  .imageView = radv_image_view_to_handle(&tmp->dst_iview),
+								  .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
+							  },
+						  }
+					  },
+				  }, 0, NULL);
+
+	radv_CmdBindDescriptorSets(radv_cmd_buffer_to_handle(cmd_buffer),
+				   VK_PIPELINE_BIND_POINT_COMPUTE,
+				   device->meta_state.cleari.img_p_layout, 0, 1,
+				   &tmp->set, 0, NULL);
+}
+
+static void
+cleari_bind_pipeline(struct radv_cmd_buffer *cmd_buffer)
+{
+	VkPipeline pipeline =
+		cmd_buffer->device->meta_state.cleari.pipeline;
+
+	if (cmd_buffer->state.compute_pipeline != radv_pipeline_from_handle(pipeline)) {
+		radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
+				     VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
+	}
+}
+
+void
+radv_meta_clear_image_cs(struct radv_cmd_buffer *cmd_buffer,
+			 struct radv_meta_blit2d_surf *dst,
+			 const VkClearColorValue *clear_color)
+{
+	struct radv_device *device = cmd_buffer->device;
+	struct cleari_temps temps;
+
+	create_iview(cmd_buffer, dst, VK_IMAGE_USAGE_STORAGE_BIT, &temps.dst_iview);
+	cleari_bind_descriptors(cmd_buffer, &temps);
+
+	cleari_bind_pipeline(cmd_buffer);
+
+	unsigned push_constants[4] = {
+		clear_color->uint32[0],
+		clear_color->uint32[1],
+		clear_color->uint32[2],
+		clear_color->uint32[3],
+	};
+
+	radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
+			      device->meta_state.cleari.img_p_layout,
+			      VK_SHADER_STAGE_COMPUTE_BIT, 0, 16,
+			      push_constants);
+
+	radv_unaligned_dispatch(cmd_buffer, dst->image->extent.width, dst->image->extent.height, 1);
+	radv_temp_descriptor_set_destroy(cmd_buffer->device, temps.set);
+}
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index e9f0132..849c540 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -402,6 +402,11 @@
 		VkDescriptorSetLayout                     img_ds_layout;
 		VkPipeline pipeline;
 	} itoi;
+	struct {
+		VkPipelineLayout                          img_p_layout;
+		VkDescriptorSetLayout                     img_ds_layout;
+		VkPipeline pipeline;
+	} cleari;
 
 	struct {
 		VkPipeline                                pipeline;