| commit | b50ae770144ef6622591c7cc23aa96e45933cf37 | [log] [tgz] |
|---|---|---|
| author | Rhys Perry <pendingchaos02@gmail.com> | Thu Aug 06 14:39:04 2020 +0100 |
| committer | Marge Bot <eric+marge@anholt.net> | Thu Aug 20 10:52:19 2020 +0000 |
| tree | 8122104d25ab644d9539241ad00ded57040fae5b | |
| parent | 4f08af6766c23295922a08a95d0183820f7bc702 [diff] |
radv: align pipeline cache entry and header sizes Fixes UBSan error: ../src/amd/vulkan/radv_pipeline_cache.c:603:42: runtime error: member access within misaligned address 0x00000152ebcc for type 'struct cache_entry', which requires 8 byte alignment Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6206>