nir: Add load_sbt_amd intrinsic.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9767>
diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c
index a67d7e2..8d4d6ab 100644
--- a/src/compiler/nir/nir_divergence_analysis.c
+++ b/src/compiler/nir/nir_divergence_analysis.c
@@ -319,6 +319,7 @@
case nir_intrinsic_masked_swizzle_amd:
case nir_intrinsic_is_sparse_texels_resident:
case nir_intrinsic_sparse_residency_code_and:
+ case nir_intrinsic_load_sbt_amd:
case nir_intrinsic_get_ubo_size:
case nir_intrinsic_load_ssbo_address: {
unsigned num_srcs = nir_intrinsic_infos[instr->intrinsic].num_srcs;
diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py
index 5305091..30b5397 100644
--- a/src/compiler/nir/nir_intrinsics.py
+++ b/src/compiler/nir/nir_intrinsics.py
@@ -1149,6 +1149,10 @@
# Allocates export space for vertices and primitives. src[] = {num_vertices, num_primitives}.
intrinsic("alloc_vertices_and_primitives_amd", src_comp=[1, 1], indices=[])
+# src = [index] BINDING = which table BASE = offset within handle
+intrinsic("load_sbt_amd", src_comp=[-1], dest_comp=0, indices=[BINDING, BASE],
+ flags=[CAN_ELIMINATE, CAN_REORDER])
+
# V3D-specific instrinc for tile buffer color reads.
#
# The hardware requires that we read the samples and components of a pixel
