commit 7868c8698f47c465004db9a5b612166633cb10ca
author Mark Janes <markjanes@swizzler.org> Thu Jun 01 09:18:28 2023 -0700
committer Marge Bot <emma+marge@anholt.net> Wed Jun 07 22:30:34 2023 +0000
tree 4015725c0184bcc9c11d3b7e319427a91793f283
parent 5b2d71ab8851259cc06ccd324ddef32bb8b999ec

iris: convert Wa_14010455700 to use workaround mechanism

The original lineage for 14010455700 is 1808121037.  Use this defect
number to apply the workaround to relevant platforms with the new
workaround mechanism.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23380>

src/gallium/drivers/iris/iris_state.c

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index cf1abf8..53b5ad2 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -1360,7 +1360,7 @@
                     GENX(3DSTATE_CLEAR_PARAMS_length)];
 };
 
-#if GFX_VERx10 == 120
+#if INTEL_NEEDS_WA_1808121037
 enum iris_depth_reg_mode {
    IRIS_DEPTH_REG_MODE_HW_DEFAULT = 0,
    IRIS_DEPTH_REG_MODE_D16_1X_MSAA,
@@ -1389,7 +1389,7 @@
    /* Is object level preemption enabled? */
    bool object_preemption;
 
-#if GFX_VERx10 == 120
+#if INTEL_NEEDS_WA_1808121037
    enum iris_depth_reg_mode depth_reg_mode;
 #endif
 
@@ -6069,7 +6069,7 @@
                                    struct iris_batch *batch,
                                    const struct isl_surf *surf)
 {
-#if GFX_VERx10 == 120
+#if INTEL_NEEDS_WA_1808121037
    const bool is_d16_1x_msaa = surf->format == ISL_FORMAT_R16_UNORM &&
                                surf->samples == 1;
 
@@ -6091,11 +6091,11 @@
     * settings while we change the registers.
     */
    iris_emit_end_of_pipe_sync(batch,
-                              "Workaround: Stop pipeline for 14010455700",
+                              "Workaround: Stop pipeline for Wa_1808121037",
                               PIPE_CONTROL_DEPTH_STALL |
                               PIPE_CONTROL_DEPTH_CACHE_FLUSH);
 
-   /* Wa_14010455700
+   /* Wa_1808121037
     *
     * To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer
     * Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA”.
@@ -8813,7 +8813,7 @@
 {
    struct iris_genx_state *genx = ice->state.genx;
 
-#if GFX_VERx10 == 120
+#if INTEL_NEEDS_WA_1808121037
    genx->depth_reg_mode = IRIS_DEPTH_REG_MODE_UNKNOWN;
 #endif