commit 72dc06e07e3f8b9ed5bb46e3927b8f87dd24e42b
author Jason Ekstrand <jason@jlekstrand.net> Fri Aug 07 11:19:45 2020 -0500
committer Marge Bot <eric+marge@anholt.net> Sat Aug 29 16:41:05 2020 +0000
tree e4a46098fbb48f31b126a98c8fad413692425afa
parent 373e25e6b53338c6fa6c5757a878e10398241c47

intel/nir: Pass the nir_builder by reference in lower_alpha_to_coverage

I'm honestly not sure how passing a builder by-value ever worked.  I
guess the struct is mostly copyable.  In any case, that's the wrong way
to use it and it's causing issues.

Fixes: 7ecfbd4f6d4 "nir: Add alpha_to_coverage lowering pass"
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6233>

src/intel/compiler/brw_nir_lower_alpha_to_coverage.c

diff --git a/src/intel/compiler/brw_nir_lower_alpha_to_coverage.c b/src/intel/compiler/brw_nir_lower_alpha_to_coverage.c
index 113c226..c804bde 100644
--- a/src/intel/compiler/brw_nir_lower_alpha_to_coverage.c
+++ b/src/intel/compiler/brw_nir_lower_alpha_to_coverage.c
@@ -56,30 +56,30 @@
  *  1.0000 1111111111111111
  */
 static nir_ssa_def *
-build_dither_mask(nir_builder b, nir_intrinsic_instr *store_instr)
+build_dither_mask(nir_builder *b, nir_intrinsic_instr *store_instr)
 {
    nir_ssa_def *alpha =
-      nir_channel(&b, nir_ssa_for_src(&b, store_instr->src[0], 4), 3);
+      nir_channel(b, nir_ssa_for_src(b, store_instr->src[0], 4), 3);
 
    nir_ssa_def *m =
-      nir_f2i32(&b, nir_fmul_imm(&b, nir_fsat(&b, alpha), 16.0));
+      nir_f2i32(b, nir_fmul_imm(b, nir_fsat(b, alpha), 16.0));
 
    nir_ssa_def *part_a =
-      nir_iand(&b,
-               nir_imm_int(&b, 0xf),
-               nir_ushr(&b,
-                        nir_imm_int(&b, 0xfea80),
-                        nir_iand(&b, m, nir_imm_int(&b, ~3))));
+      nir_iand(b,
+               nir_imm_int(b, 0xf),
+               nir_ushr(b,
+                        nir_imm_int(b, 0xfea80),
+                        nir_iand(b, m, nir_imm_int(b, ~3))));
 
-   nir_ssa_def *part_b = nir_iand(&b, m, nir_imm_int(&b, 2));
+   nir_ssa_def *part_b = nir_iand(b, m, nir_imm_int(b, 2));
 
-   nir_ssa_def *part_c = nir_iand(&b, m, nir_imm_int(&b, 1));
+   nir_ssa_def *part_c = nir_iand(b, m, nir_imm_int(b, 1));
 
-   return nir_ior(&b,
-                  nir_imul_imm(&b, part_a, 0x1111),
-                  nir_ior(&b,
-                          nir_imul_imm(&b, part_b, 0x0808),
-                          nir_imul_imm(&b, part_c, 0x0100)));
+   return nir_ior(b,
+                  nir_imul_imm(b, part_a, 0x1111),
+                  nir_ior(b,
+                          nir_imul_imm(b, part_b, 0x0808),
+                          nir_imul_imm(b, part_c, 0x0100)));
 }
 
 void
@@ -136,7 +136,7 @@
 
          if (sample_mask_instr && store_instr) {
             b.cursor = nir_before_instr(&store_instr->instr);
-            nir_ssa_def *dither_mask = build_dither_mask(b, store_instr);
+            nir_ssa_def *dither_mask = build_dither_mask(&b, store_instr);
 
             /* Combine dither_mask and reorder gl_SampleMask store instruction
              * after render target 0 store instruction.