tree ce0784dc3552f7fef3d4b4d59953f1658c6c127d
parent adb6d7fe9add275a73b593a6e5f7445a952c7305
author Emma Anholt <emma@anholt.net> 1648491686 -0700
committer Marge Bot <emma+marge@anholt.net> 1650491913 +0000

nouveau/nir: Disable bitfield ops pre-nvc0.

There's no hardware instructions for them until then.  These chips don't
expose the extension provinding the GLSL builtins for operations like
bfrev, but NIR can recognize the construct and optimize it to
bitfield_reverse, which pre-nvc0 would then fail to codegen.  Prevents a
regression when moving to nir-to-tgsi.  Other lower_bitfield flags are set
as well for when someone comes along and adds optimizations for them too.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16063>