diff --git a/src/compiler/glsl/glsl_to_nir.cpp b/src/compiler/glsl/glsl_to_nir.cpp
index fdcdc07..efc4c67 100644
--- a/src/compiler/glsl/glsl_to_nir.cpp
+++ b/src/compiler/glsl/glsl_to_nir.cpp
@@ -2302,7 +2302,7 @@
       result = nir_channel(&b, srcs[0], 0);
       for (unsigned i = 1; i < ir->operands[0]->type->vector_elements; i++) {
          nir_ssa_def *swizzled = nir_channel(&b, srcs[0], i);
-         result = nir_bcsel(&b, nir_ieq(&b, srcs[1], nir_imm_int(&b, i)),
+         result = nir_bcsel(&b, nir_ieq_imm(&b, srcs[1], i),
                             swizzled, result);
       }
       break;
diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h
index 1b43892..c92b405 100644
--- a/src/compiler/nir/nir_builder.h
+++ b/src/compiler/nir/nir_builder.h
@@ -770,6 +770,13 @@
    }
 }
 
+
+static inline nir_ssa_def *
+nir_ieq_imm(nir_builder *build, nir_ssa_def *x, uint64_t y)
+{
+   return nir_ieq(build, x, nir_imm_intN_t(build, y, x->bit_size));
+}
+
 static inline nir_ssa_def *
 _nir_mul_imm(nir_builder *build, nir_ssa_def *x, uint64_t y, bool amul)
 {
diff --git a/src/compiler/nir/nir_builtin_builder.h b/src/compiler/nir/nir_builtin_builder.h
index 50f48d5..0ddfcd1 100644
--- a/src/compiler/nir/nir_builtin_builder.h
+++ b/src/compiler/nir/nir_builtin_builder.h
@@ -244,7 +244,7 @@
       uint64_t mask = 1ull << (s->bit_size - 1);
       s = nir_iand(b, s, nir_imm_intN_t(b, mask, s->bit_size));
    }
-   return nir_bcsel(b, nir_ieq(b, s, nir_imm_intN_t(b, 0, s->bit_size)), x, y);
+   return nir_bcsel(b, nir_ieq_imm(b, s, 0), x, y);
 }
 
 static inline nir_ssa_def *
diff --git a/src/compiler/nir/nir_lower_idiv.c b/src/compiler/nir/nir_lower_idiv.c
index b139108..06f6b5a 100644
--- a/src/compiler/nir/nir_lower_idiv.c
+++ b/src/compiler/nir/nir_lower_idiv.c
@@ -120,7 +120,7 @@
             q = nir_imul(bld, q, denom);
             q = nir_isub(bld, numer, q);
             if (op == nir_op_imod) {
-               q = nir_bcsel(bld, nir_ieq(bld, q, nir_imm_int(bld, 0)),
+               q = nir_bcsel(bld, nir_ieq_imm(bld, q, 0),
                              nir_imm_int(bld, 0),
                              nir_bcsel(bld, r, nir_iadd(bld, q, denom), q));
             }
@@ -195,7 +195,7 @@
       res = nir_ixor(bld, res, lh_sign);
       res = nir_isub(bld, res, lh_sign);
       if (op == nir_op_imod) {
-         nir_ssa_def *cond = nir_ieq(bld, res, nir_imm_int(bld, 0));
+         nir_ssa_def *cond = nir_ieq_imm(bld, res, 0);
          cond = nir_ior(bld, nir_ieq(bld, lh_sign, rh_sign), cond);
          res = nir_bcsel(bld, cond, res, nir_iadd(bld, res, denom));
       }
diff --git a/src/compiler/nir/nir_lower_int64.c b/src/compiler/nir/nir_lower_int64.c
index 07b307e..ff2c1d9 100644
--- a/src/compiler/nir/nir_lower_int64.c
+++ b/src/compiler/nir/nir_lower_int64.c
@@ -200,8 +200,7 @@
       nir_pack_64_2x32_split(b, nir_imm_int(b, 0),
                                 nir_ishl(b, x_lo, reverse_count));
 
-   return nir_bcsel(b,
-                    nir_ieq(b, y, nir_imm_int(b, 0)), x,
+   return nir_bcsel(b, nir_ieq_imm(b, y, 0), x,
                     nir_bcsel(b, nir_uge(b, y, nir_imm_int(b, 32)),
                                  res_if_ge_32, res_if_lt_32));
 }
@@ -245,8 +244,7 @@
       nir_pack_64_2x32_split(b, nir_ishr(b, x_hi, reverse_count),
                                 nir_ishr(b, x_hi, nir_imm_int(b, 31)));
 
-   return nir_bcsel(b,
-                    nir_ieq(b, y, nir_imm_int(b, 0)), x,
+   return nir_bcsel(b, nir_ieq_imm(b, y, 0), x,
                     nir_bcsel(b, nir_uge(b, y, nir_imm_int(b, 32)),
                                  res_if_ge_32, res_if_lt_32));
 }
@@ -289,8 +287,7 @@
       nir_pack_64_2x32_split(b, nir_ushr(b, x_hi, reverse_count),
                                 nir_imm_int(b, 0));
 
-   return nir_bcsel(b,
-                    nir_ieq(b, y, nir_imm_int(b, 0)), x,
+   return nir_bcsel(b, nir_ieq_imm(b, y, 0), x,
                     nir_bcsel(b, nir_uge(b, y, nir_imm_int(b, 32)),
                                  res_if_ge_32, res_if_lt_32));
 }
@@ -522,7 +519,7 @@
     * denom == 0.
     */
    nir_ssa_def *need_high_div =
-      nir_iand(b, nir_ieq(b, d_hi, nir_imm_int(b, 0)), nir_uge(b, n_hi, d_lo));
+      nir_iand(b, nir_ieq_imm(b, d_hi, 0), nir_uge(b, n_hi, d_lo));
    nir_push_if(b, nir_bany(b, need_high_div));
    {
       /* If we only have one component, then the bany above goes away and
@@ -630,7 +627,7 @@
 
    nir_ssa_def *rem = nir_bcsel(b, n_is_neg, nir_ineg(b, r), r);
 
-   return nir_bcsel(b, nir_ieq(b, r, nir_imm_int64(b, 0)), nir_imm_int64(b, 0),
+   return nir_bcsel(b, nir_ieq_imm(b, r, 0), nir_imm_int64(b, 0),
           nir_bcsel(b, nir_ieq(b, n_is_neg, d_is_neg), rem,
                        nir_iadd(b, rem, d)));
 }
diff --git a/src/compiler/spirv/vtn_cfg.c b/src/compiler/spirv/vtn_cfg.c
index 5f0505a..4162275 100644
--- a/src/compiler/spirv/vtn_cfg.c
+++ b/src/compiler/spirv/vtn_cfg.c
@@ -984,10 +984,8 @@
       return nir_inot(&b->nb, any);
    } else {
       nir_ssa_def *cond = nir_imm_false(&b->nb);
-      util_dynarray_foreach(&cse->values, uint64_t, val) {
-         nir_ssa_def *imm = nir_imm_intN_t(&b->nb, *val, sel->bit_size);
-         cond = nir_ior(&b->nb, cond, nir_ieq(&b->nb, sel, imm));
-      }
+      util_dynarray_foreach(&cse->values, uint64_t, val)
+         cond = nir_ior(&b->nb, cond, nir_ieq_imm(&b->nb, sel, *val));
       return cond;
    }
 }
@@ -1303,10 +1301,8 @@
             }
 
             nir_ssa_def *cond = nir_imm_false(&b->nb);
-            util_dynarray_foreach(&cse->values, uint64_t, val) {
-               nir_ssa_def *imm = nir_imm_intN_t(&b->nb, *val, sel->bit_size);
-               cond = nir_ior(&b->nb, cond, nir_ieq(&b->nb, sel, imm));
-            }
+            util_dynarray_foreach(&cse->values, uint64_t, val)
+               cond = nir_ior(&b->nb, cond, nir_ieq_imm(&b->nb, sel, *val));
 
             /* block for the next check */
             nir_block *e = vtn_new_unstructured_block(b, func);
diff --git a/src/freedreno/ir3/ir3_nir_lower_tess.c b/src/freedreno/ir3/ir3_nir_lower_tess.c
index 6b3f95c..87b49c9 100644
--- a/src/freedreno/ir3/ir3_nir_lower_tess.c
+++ b/src/freedreno/ir3/ir3_nir_lower_tess.c
@@ -704,7 +704,7 @@
 	b.cursor = nir_after_cf_list(&nif->then_list);
 
 	/* Insert conditional exit for threads invocation id != 0 */
-	nir_ssa_def *iid0_cond = nir_ieq(&b, iid, nir_imm_int(&b, 0));
+	nir_ssa_def *iid0_cond = nir_ieq_imm(&b, iid, 0);
 	nir_intrinsic_instr *cond_end =
 		nir_intrinsic_instr_create(shader, nir_intrinsic_cond_end_ir3);
 	cond_end->src[0] = nir_src_for_ssa(iid0_cond);
@@ -974,7 +974,7 @@
 		nir_intrinsic_instr *discard_if =
 			nir_intrinsic_instr_create(b.shader, nir_intrinsic_discard_if);
 
-		nir_ssa_def *cond = nir_ieq(&b, nir_load_var(&b, state.emitted_vertex_var), nir_imm_int(&b, 0));
+		nir_ssa_def *cond = nir_ieq_imm(&b, nir_load_var(&b, state.emitted_vertex_var), 0);
 
 		discard_if->src[0] = nir_src_for_ssa(cond);
 
diff --git a/src/freedreno/vulkan/tu_shader.c b/src/freedreno/vulkan/tu_shader.c
index 509b254..1b99e24 100644
--- a/src/freedreno/vulkan/tu_shader.c
+++ b/src/freedreno/vulkan/tu_shader.c
@@ -277,7 +277,7 @@
 
    for (unsigned i = 0; i < MAX_SETS + 1; i++) {
       /* if (base_idx == i) { ... */
-      nir_if *nif = nir_push_if(b, nir_ieq(b, base_idx, nir_imm_int(b, i)));
+      nir_if *nif = nir_push_if(b, nir_ieq_imm(b, base_idx, i));
 
       nir_intrinsic_instr *bindless =
          nir_intrinsic_instr_create(b->shader,
diff --git a/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp b/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp
index 43254a0..7781361 100644
--- a/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp
+++ b/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp
@@ -381,7 +381,7 @@
                      1, 32, NULL);
    nir_builder_instr_insert(b, &invocation_id->instr);
 
-   nir_push_if(b, nir_ieq(b, &invocation_id->dest.ssa, nir_imm_int(b, 0)));
+   nir_push_if(b, nir_ieq_imm(b, &invocation_id->dest.ssa, 0));
    auto base = emit_load_param_base(b, nir_intrinsic_load_tcs_out_param_base_r600);
    auto rel_patch_id = r600_load_rel_patch_id(b);
 
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index f14f005..18d4ad7 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -671,11 +671,10 @@
           * clear color and we can skip the remaining fetches just like we do
           * when MCS == 0.
           */
-         nir_ssa_def *mcs_zero =
-            nir_ieq(b, nir_channel(b, mcs, 0), nir_imm_int(b, 0));
+         nir_ssa_def *mcs_zero = nir_ieq_imm(b, nir_channel(b, mcs, 0), 0);
          if (tex_samples == 16) {
             mcs_zero = nir_iand(b, mcs_zero,
-               nir_ieq(b, nir_channel(b, mcs, 1), nir_imm_int(b, 0)));
+               nir_ieq_imm(b, nir_channel(b, mcs, 1), 0));
          }
          nir_ssa_def *mcs_clear =
             blorp_nir_mcs_is_clear_color(b, mcs, tex_samples);
@@ -1442,9 +1441,9 @@
       assert(dst_pos->num_components == 2);
 
       nir_ssa_def *color_component =
-         nir_bcsel(&b, nir_ieq(&b, comp, nir_imm_int(&b, 0)),
+         nir_bcsel(&b, nir_ieq_imm(&b, comp, 0),
                        nir_channel(&b, color, 0),
-                       nir_bcsel(&b, nir_ieq(&b, comp, nir_imm_int(&b, 1)),
+                       nir_bcsel(&b, nir_ieq_imm(&b, comp, 1),
                                      nir_channel(&b, color, 1),
                                      nir_channel(&b, color, 2)));
 
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index b232678..26f7d85 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -76,9 +76,9 @@
       nir_ssa_def *comp = nir_umod(&b, nir_channel(&b, pos, 0),
                                        nir_imm_int(&b, 3));
       nir_ssa_def *color_component =
-         nir_bcsel(&b, nir_ieq(&b, comp, nir_imm_int(&b, 0)),
+         nir_bcsel(&b, nir_ieq_imm(&b, comp, 0),
                        nir_channel(&b, color, 0),
-                       nir_bcsel(&b, nir_ieq(&b, comp, nir_imm_int(&b, 1)),
+                       nir_bcsel(&b, nir_ieq_imm(&b, comp, 1),
                                      nir_channel(&b, color, 1),
                                      nir_channel(&b, color, 2)));
 
diff --git a/src/intel/blorp/blorp_nir_builder.h b/src/intel/blorp/blorp_nir_builder.h
index 0ba855f..328f471 100644
--- a/src/intel/blorp/blorp_nir_builder.h
+++ b/src/intel/blorp/blorp_nir_builder.h
@@ -79,22 +79,20 @@
       /* Empirical evidence suggests that the value returned from the
        * sampler is not always 0x3 for clear color so we need to mask it.
        */
-      return nir_ieq(b, nir_iand(b, nir_channel(b, mcs, 0),
-                                    nir_imm_int(b, 0x3)),
-                    nir_imm_int(b, 0x3));
+      return nir_ieq_imm(b, nir_iand(b, nir_channel(b, mcs, 0),
+                                        nir_imm_int(b, 0x3)),
+                            0x3);
 
    case 4:
-      return nir_ieq(b, nir_channel(b, mcs, 0), nir_imm_int(b, 0xff));
+      return nir_ieq_imm(b, nir_channel(b, mcs, 0), 0xff);
 
    case 8:
-      return nir_ieq(b, nir_channel(b, mcs, 0), nir_imm_int(b, ~0));
+      return nir_ieq_imm(b, nir_channel(b, mcs, 0), ~0);
 
    case 16:
       /* For 16x MSAA, the MCS is actually an ivec2 */
-      return nir_iand(b, nir_ieq(b, nir_channel(b, mcs, 0),
-                                    nir_imm_int(b, ~0)),
-                         nir_ieq(b, nir_channel(b, mcs, 1),
-                                    nir_imm_int(b, ~0)));
+      return nir_iand(b, nir_ieq_imm(b, nir_channel(b, mcs, 0), ~0),
+                         nir_ieq_imm(b, nir_channel(b, mcs, 1), ~0));
 
    default:
       unreachable("Invalid sample count");
diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
index f4aafe6..b453fc7 100644
--- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
+++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
@@ -637,7 +637,7 @@
          nir_builder_instr_insert(b, &dyn_load->instr);
 
          nir_ssa_def *dynamic_offset =
-            nir_bcsel(b, nir_ieq(b, dyn_offset_base, nir_imm_int(b, 0xff)),
+            nir_bcsel(b, nir_ieq_imm(b, dyn_offset_base, 0xff),
                          nir_imm_int(b, 0), &dyn_load->dest.ssa);
 
          switch (state->ssbo_addr_format) {