diff --git a/lib/Target/ARM64/ARM64InstrInfo.td b/lib/Target/ARM64/ARM64InstrInfo.td
index 76f99ba..455cdf3 100644
--- a/lib/Target/ARM64/ARM64InstrInfo.td
+++ b/lib/Target/ARM64/ARM64InstrInfo.td
@@ -544,19 +544,19 @@
 }
 
 // Variable shift
-defm ASRV : Shift<0b10, "asrv", sra>;
-defm LSLV : Shift<0b00, "lslv", shl>;
-defm LSRV : Shift<0b01, "lsrv", srl>;
-defm RORV : Shift<0b11, "rorv", rotr>;
+defm ASRV : Shift<0b10, "asr", sra>;
+defm LSLV : Shift<0b00, "lsl", shl>;
+defm LSRV : Shift<0b01, "lsr", srl>;
+defm RORV : Shift<0b11, "ror", rotr>;
 
-def : ShiftAlias<"asr", ASRVWr, GPR32>;
-def : ShiftAlias<"asr", ASRVXr, GPR64>;
-def : ShiftAlias<"lsl", LSLVWr, GPR32>;
-def : ShiftAlias<"lsl", LSLVXr, GPR64>;
-def : ShiftAlias<"lsr", LSRVWr, GPR32>;
-def : ShiftAlias<"lsr", LSRVXr, GPR64>;
-def : ShiftAlias<"ror", RORVWr, GPR32>;
-def : ShiftAlias<"ror", RORVXr, GPR64>;
+def : ShiftAlias<"asrv", ASRVWr, GPR32>;
+def : ShiftAlias<"asrv", ASRVXr, GPR64>;
+def : ShiftAlias<"lslv", LSLVWr, GPR32>;
+def : ShiftAlias<"lslv", LSLVXr, GPR64>;
+def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
+def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
+def : ShiftAlias<"rorv", RORVWr, GPR32>;
+def : ShiftAlias<"rorv", RORVXr, GPR64>;
 
 // Multiply-add
 let AddedComplexity = 7 in {
diff --git a/test/CodeGen/ARM64/arith.ll b/test/CodeGen/ARM64/arith.ll
index db528f7..803af6c 100644
--- a/test/CodeGen/ARM64/arith.ll
+++ b/test/CodeGen/ARM64/arith.ll
@@ -48,7 +48,7 @@
 define i32 @t6(i32 %a, i32 %b) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: t6:
-; CHECK: lslv w0, w0, w1
+; CHECK: lsl w0, w0, w1
 ; CHECK: ret
   %shl = shl i32 %a, %b
   ret i32 %shl
@@ -57,7 +57,7 @@
 define i64 @t7(i64 %a, i64 %b) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: t7:
-; CHECK: lslv x0, x0, x1
+; CHECK: lsl x0, x0, x1
 ; CHECK: ret
   %shl = shl i64 %a, %b
   ret i64 %shl
@@ -66,7 +66,7 @@
 define i32 @t8(i32 %a, i32 %b) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: t8:
-; CHECK: lsrv w0, w0, w1
+; CHECK: lsr w0, w0, w1
 ; CHECK: ret
   %lshr = lshr i32 %a, %b
   ret i32 %lshr
@@ -75,7 +75,7 @@
 define i64 @t9(i64 %a, i64 %b) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: t9:
-; CHECK: lsrv x0, x0, x1
+; CHECK: lsr x0, x0, x1
 ; CHECK: ret
   %lshr = lshr i64 %a, %b
   ret i64 %lshr
@@ -84,7 +84,7 @@
 define i32 @t10(i32 %a, i32 %b) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: t10:
-; CHECK: asrv w0, w0, w1
+; CHECK: asr w0, w0, w1
 ; CHECK: ret
   %ashr = ashr i32 %a, %b
   ret i32 %ashr
@@ -93,7 +93,7 @@
 define i64 @t11(i64 %a, i64 %b) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: t11:
-; CHECK: asrv x0, x0, x1
+; CHECK: asr x0, x0, x1
 ; CHECK: ret
   %ashr = ashr i64 %a, %b
   ret i64 %ashr
diff --git a/test/CodeGen/ARM64/long-shift.ll b/test/CodeGen/ARM64/long-shift.ll
index caa486a..d5baf16 100644
--- a/test/CodeGen/ARM64/long-shift.ll
+++ b/test/CodeGen/ARM64/long-shift.ll
@@ -2,16 +2,16 @@
 
 define i128 @shl(i128 %r, i128 %s) nounwind readnone {
 ; CHECK-LABEL: shl:
-; CHECK: lslv  [[XREG_0:x[0-9]+]], x1, x2
+; CHECK: lsl  [[XREG_0:x[0-9]+]], x1, x2
 ; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
 ; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], x[[XREG_1]], x2
-; CHECK-NEXT: lsrv  [[XREG_3:x[0-9]+]], x0, [[XREG_2]]
+; CHECK-NEXT: lsr  [[XREG_3:x[0-9]+]], x0, [[XREG_2]]
 ; CHECK-NEXT: orr [[XREG_6:x[0-9]+]], [[XREG_3]], [[XREG_0]]
 ; CHECK-NEXT: sub [[XREG_4:x[0-9]+]], x2, #64
-; CHECK-NEXT: lslv  [[XREG_5:x[0-9]+]], x0, [[XREG_4]]
+; CHECK-NEXT: lsl  [[XREG_5:x[0-9]+]], x0, [[XREG_4]]
 ; CHECK-NEXT: cmp   [[XREG_4]], #0
 ; CHECK-NEXT: csel  x1, [[XREG_5]], [[XREG_6]], ge
-; CHECK-NEXT: lslv  [[SMALLSHIFT_LO:x[0-9]+]], x0, x2
+; CHECK-NEXT: lsl  [[SMALLSHIFT_LO:x[0-9]+]], x0, x2
 ; CHECK-NEXT: csel  x0, xzr, [[SMALLSHIFT_LO]], ge
 ; CHECK-NEXT: ret
 
@@ -21,16 +21,16 @@
 
 define i128 @ashr(i128 %r, i128 %s) nounwind readnone {
 ; CHECK-LABEL: ashr:
-; CHECK: lsrv  [[XREG_0:x[0-9]+]], x0, x2
+; CHECK: lsr  [[XREG_0:x[0-9]+]], x0, x2
 ; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
 ; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], x[[XREG_1]], x2
-; CHECK-NEXT: lslv  [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
+; CHECK-NEXT: lsl  [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
 ; CHECK-NEXT: orr [[XREG_4:x[0-9]+]], [[XREG_0]], [[XREG_3]]
 ; CHECK-NEXT: sub [[XREG_5:x[0-9]+]], x2, #64
-; CHECK-NEXT: asrv  [[XREG_6:x[0-9]+]], x1, [[XREG_5]]
+; CHECK-NEXT: asr  [[XREG_6:x[0-9]+]], x1, [[XREG_5]]
 ; CHECK-NEXT: cmp   [[XREG_5]], #0
 ; CHECK-NEXT: csel  x0, [[XREG_6]], [[XREG_4]], ge
-; CHECK-NEXT: asrv  [[SMALLSHIFT_HI:x[0-9]+]], x1, x2
+; CHECK-NEXT: asr  [[SMALLSHIFT_HI:x[0-9]+]], x1, x2
 ; CHECK-NEXT: asr [[BIGSHIFT_HI:x[0-9]+]], x1, #63
 ; CHECK-NEXT: csel x1, [[BIGSHIFT_HI]], [[SMALLSHIFT_HI]], ge
 ; CHECK-NEXT: ret
@@ -41,16 +41,16 @@
 
 define i128 @lshr(i128 %r, i128 %s) nounwind readnone {
 ; CHECK-LABEL: lshr:
-; CHECK: lsrv  [[XREG_0:x[0-9]+]], x0, x2
+; CHECK: lsr  [[XREG_0:x[0-9]+]], x0, x2
 ; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
 ; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], x[[XREG_1]], x2
-; CHECK-NEXT: lslv  [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
+; CHECK-NEXT: lsl  [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
 ; CHECK-NEXT: orr [[XREG_4:x[0-9]+]], [[XREG_0]], [[XREG_3]]
 ; CHECK-NEXT: sub [[XREG_5:x[0-9]+]], x2, #64
-; CHECK-NEXT: lsrv  [[XREG_6:x[0-9]+]], x1, [[XREG_5]]
+; CHECK-NEXT: lsr  [[XREG_6:x[0-9]+]], x1, [[XREG_5]]
 ; CHECK-NEXT: cmp   [[XREG_5]], #0
 ; CHECK-NEXT: csel  x0, [[XREG_6]], [[XREG_4]], ge
-; CHECK-NEXT: lsrv  [[SMALLSHIFT_HI:x[0-9]+]], x1, x2
+; CHECK-NEXT: lsr  [[SMALLSHIFT_HI:x[0-9]+]], x1, x2
 ; CHECK-NEXT: csel x1, xzr, [[SMALLSHIFT_HI]], ge
 ; CHECK-NEXT: ret
 
diff --git a/test/MC/Disassembler/ARM64/arithmetic.txt b/test/MC/Disassembler/ARM64/arithmetic.txt
index 7e18fc6..ffd9770 100644
--- a/test/MC/Disassembler/ARM64/arithmetic.txt
+++ b/test/MC/Disassembler/ARM64/arithmetic.txt
@@ -368,21 +368,21 @@
 #==---------------------------------------------------------------------------==
 
   0x41 0x28 0xc3 0x1a
-# CHECK: asrv w1, w2, w3
+# CHECK: asr w1, w2, w3
   0x41 0x28 0xc3 0x9a
-# CHECK: asrv x1, x2, x3
+# CHECK: asr x1, x2, x3
   0x41 0x20 0xc3 0x1a
-# CHECK: lslv w1, w2, w3
+# CHECK: lsl w1, w2, w3
   0x41 0x20 0xc3 0x9a
-# CHECK: lslv x1, x2, x3
+# CHECK: lsl x1, x2, x3
   0x41 0x24 0xc3 0x1a
-# CHECK: lsrv w1, w2, w3
+# CHECK: lsr w1, w2, w3
   0x41 0x24 0xc3 0x9a
-# CHECK: lsrv x1, x2, x3
+# CHECK: lsr x1, x2, x3
   0x41 0x2c 0xc3 0x1a
-# CHECK: rorv w1, w2, w3
+# CHECK: ror w1, w2, w3
   0x41 0x2c 0xc3 0x9a
-# CHECK: rorv x1, x2, x3
+# CHECK: ror x1, x2, x3
 
 #==---------------------------------------------------------------------------==
 # One operand instructions