commit 6e4e64859fe019c949f3d2c89abdfc2fe27f3af5
author Akira Hatanaka <ahatanaka@mips.com> Wed Oct 05 02:21:58 2011 +0000
committer Akira Hatanaka <ahatanaka@mips.com> Wed Oct 05 02:21:58 2011 +0000
tree 698fa9dcab73368dfafe1016b7e5cf1f29c002fd
parent 0c419a7c4bec0a4931dd1dbd9f1adb43ec9b15c2

Do not examine variadic or implicit operands if instruction is a return (jr).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141157 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Mips/MipsDelaySlotFiller.cpp

diff --git a/lib/Target/Mips/MipsDelaySlotFiller.cpp b/lib/Target/Mips/MipsDelaySlotFiller.cpp
index 91a80a7..bbcdb1e 100644
--- a/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -222,8 +222,9 @@
   //       no instruction that can possibly be put in a delay slot can read or
   //       write it.
 
-  unsigned e = MI->getDesc().isCall() ? MI->getDesc().getNumOperands() :
-                                        MI->getNumOperands();
+  MCInstrDesc MCID = MI->getDesc();
+  unsigned e = MCID.isCall() || MCID.isReturn() ? MCID.getNumOperands() :
+                                                  MI->getNumOperands();
 
   for (unsigned i = 0; i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);