Tweak Thumb1 ADD encoding selection a bit.
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138862 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index ab0ff87..67176ad 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -3473,8 +3473,11 @@
}
break;
case ARM::tADDi8:
- // If the immediate is in the range 0-7, we really wanted tADDi3.
- if (Inst.getOperand(3).getImm() < 8)
+ // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
+ // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
+ // to encoding T2 if <Rd> is specified and encoding T2 is preferred
+ // to encoding T1 if <Rd> is omitted."
+ if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
Inst.setOpcode(ARM::tADDi3);
break;
case ARM::tBcc:
diff --git a/test/MC/ARM/basic-thumb-instructions.s b/test/MC/ARM/basic-thumb-instructions.s
index 54d353e..94ba839 100644
--- a/test/MC/ARM/basic-thumb-instructions.s
+++ b/test/MC/ARM/basic-thumb-instructions.s
@@ -26,11 +26,13 @@
@ ADD (immediate)
@------------------------------------------------------------------------------
adds r1, r2, #3
+@ When Rd is not explicitly specified, encoding T2 is preferred even though
+@ the literal is in the range [0,7] which would allow encoding T1.
adds r2, #3
adds r2, #8
@ CHECK: adds r1, r2, #3 @ encoding: [0xd1,0x1c]
-@ CHECK: adds r2, r2, #3 @ encoding: [0xd2,0x1c]
+@ CHECK: adds r2, #3 @ encoding: [0x03,0x32]
@ CHECK: adds r2, #8 @ encoding: [0x08,0x32]
