tree 243951ca06d2b99d69ae5621ad34ed20b3bcc15c
parent 5c5d3ac2064ae2466c81d40186bcc09b2d5b7892
author Qiuxu Zhuo <qiuxu.zhuo@intel.com> 1561529798 +0800
committer Tony Luck <tony.luck@intel.com> 1561568769 -0700

EDAC, i10nm: Check ECC enabling status per channel

The i10nm_edac only checks the ECC enabling status for the first
channel of the memory controller. If there aren't memory DIMMs
populated on the first channel, but at least one DIMM populated
on the second channel, it will wrongly report that the ECC for
the memory controller is disabled that fails to load the i10nm_edac
driver. Fix it by checking ECC enabling status per channel.

[Tony: Also report which channel has ECC disabled]

Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>