tree 87dfbff40a3856fe54aef986bee5439fe76a3e56
parent f05c07b05d67c578d2f11c04482d983dba7ebc9c
author Marek Behún <marek.behun@nic.cz> 1545413577 +0100
committer Linus Walleij <linus.walleij@linaro.org> 1547196827 +0100

pinctrl: armada-37xx: Correct mpp definitions

This is a cleanup and fix of the patch by Ken Ma <make@marvell.com>.

Fix the mpp definitions according to newest revision of the
specification:
  - northbridge:
    fix pmic1 gpio number to 7
    fix pmic0 gpio number to 6
  - southbridge
    split pcie1 group bit mask to BIT(5) and  BIT(9)
    fix ptp group bit mask to BIT(11) | BIT(12) | BIT(13)
    add smi group with bit mask BIT(4)

[gregory: split the pcie group in 2, as at hardware level they can be
configured separately]
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Tested-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>