tree cc562edccdbd0d0eaa042e3f9a14fdfd6508b61b
parent 74054c413ae8c36a5529e7891c2450a747667753
author Paul Cercueil <paul@crapouillou.net> 1556832302 +0200
committer Stephen Boyd <sboyd@kernel.org> 1559933341 -0700

clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly

The code was setting the bit 21 of the CPCCR register to use a divider
of 2 for the "pll half" clock, and clearing the bit to use a divider
of 1.

This is the opposite of how this register field works: a cleared bit
means that the /2 divider is used, and a set bit means that the divider
is 1.

Restore the correct behaviour using the newly introduced .div_table
field.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>