| commit | 27405a217f75f663a814454068bd81fcf30e9cf6 | [log] [tgz] |
|---|---|---|
| author | Harish Mahendrakar <harish.mahendrakar@ittiam.com> | Wed Jan 20 13:24:52 2016 +0530 |
| committer | Rachad <rachad@google.com> | Wed Aug 24 18:11:14 2016 -0700 |
| tree | 8a98d9fac5a29bc39ea9d6bd0feea5845a622f2d | |
| parent | c07d2b24adc12b6f424397a4dc06f939ed196c83 [diff] |
Added memory barrier calls On some A72 based devices, data shared between cores was found to be inconsistent which was resulting in an infinite loop. Adding memory barriers before marking a CTB as parsed/processed, all the pending memory operations are guaranteed to be completed. Change-Id: I6e3bb11123a3c12ba7e69c4bfcd38960616f9fb5 (cherry picked from commit 031b91dde5dd07c15d6401601e47e7c937e79051)