blob: a7a0b62d18dac1de695cfe38441df7b0bdd1c93c [file] [log] [blame]
/******************************************************************************
*
* Copyright (C) 2012 Ittiam Systems Pvt Ltd, Bangalore
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
/**
*******************************************************************************
* @file
* ihevcd_api.c
*
* @brief
* Contains api functions definitions for HEVC decoder
*
* @author
* Harish
*
* @par List of Functions:
* - api_check_struct_sanity()
* - ihevcd_get_version()
* - ihevcd_set_default_params()
* - ihevcd_init()
* - ihevcd_get_num_rec()
* - ihevcd_fill_num_mem_rec()
* - ihevcd_init_mem_rec()
* - ihevcd_retrieve_memrec()
* - ihevcd_set_display_frame()
* - ihevcd_set_flush_mode()
* - ihevcd_get_status()
* - ihevcd_get_buf_info()
* - ihevcd_set_params()
* - ihevcd_reset()
* - ihevcd_rel_display_frame()
* - ihevcd_disable_deblk()
* - ihevcd_get_frame_dimensions()
* - ihevcd_set_num_cores()
* - ihevcd_ctl()
* - ihevcd_cxa_api_function()
*
* @remarks
* None
*
*******************************************************************************
*/
/*****************************************************************************/
/* File Includes */
/*****************************************************************************/
#include <stdio.h>
#include <stddef.h>
#include <stdlib.h>
#include <string.h>
#include "ihevc_typedefs.h"
#include "iv.h"
#include "ivd.h"
#include "ihevcd_cxa.h"
#include "ithread.h"
#include "ihevc_defs.h"
#include "ihevc_debug.h"
#include "ihevc_structs.h"
#include "ihevc_macros.h"
#include "ihevc_platform_macros.h"
#include "ihevc_buf_mgr.h"
#include "ihevc_dpb_mgr.h"
#include "ihevc_disp_mgr.h"
#include "ihevc_common_tables.h"
#include "ihevc_cabac_tables.h"
#include "ihevc_error.h"
#include "ihevcd_defs.h"
#include "ihevcd_trace.h"
#include "ihevcd_function_selector.h"
#include "ihevcd_structs.h"
#include "ihevcd_error.h"
#include "ihevcd_utils.h"
#include "ihevcd_decode.h"
#include "ihevcd_job_queue.h"
#include "ihevcd_statistics.h"
/*****************************************************************************/
/* Function Prototypes */
/*****************************************************************************/
IV_API_CALL_STATUS_T ihevcd_get_version(CHAR *pc_version_string,
UWORD32 u4_version_buffer_size);
/**
*******************************************************************************
*
* @brief
* Used to test arguments for corresponding API call
*
* @par Description:
* For each command the arguments are validated
*
* @param[in] ps_handle
* Codec handle at API level
*
* @param[in] pv_api_ip
* Pointer to input structure
*
* @param[out] pv_api_op
* Pointer to output structure
*
* @returns Status of error checking
*
* @remarks
*
*
*******************************************************************************
*/
static IV_API_CALL_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle,
void *pv_api_ip,
void *pv_api_op)
{
IVD_API_COMMAND_TYPE_T e_cmd;
UWORD32 *pu4_api_ip;
UWORD32 *pu4_api_op;
WORD32 i, j;
if(NULL == pv_api_op)
return (IV_FAIL);
if(NULL == pv_api_ip)
return (IV_FAIL);
pu4_api_ip = (UWORD32 *)pv_api_ip;
pu4_api_op = (UWORD32 *)pv_api_op;
e_cmd = (IVD_API_COMMAND_TYPE_T)*(pu4_api_ip + 1);
*(pu4_api_op + 1) = 0;
/* error checks on handle */
switch((WORD32)e_cmd)
{
case IV_CMD_GET_NUM_MEM_REC:
case IV_CMD_FILL_NUM_MEM_REC:
break;
case IV_CMD_INIT:
if(ps_handle == NULL)
{
*(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
*(pu4_api_op + 1) |= IVD_HANDLE_NULL;
return IV_FAIL;
}
if(ps_handle->u4_size != sizeof(iv_obj_t))
{
*(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
*(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
DEBUG("Sizes do not match. Expected: %d, Got: %d",
sizeof(iv_obj_t), ps_handle->u4_size);
return IV_FAIL;
}
break;
case IVD_CMD_REL_DISPLAY_FRAME:
case IVD_CMD_SET_DISPLAY_FRAME:
case IVD_CMD_GET_DISPLAY_FRAME:
case IVD_CMD_VIDEO_DECODE:
case IV_CMD_RETRIEVE_MEMREC:
case IVD_CMD_VIDEO_CTL:
if(ps_handle == NULL)
{
*(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
*(pu4_api_op + 1) |= IVD_HANDLE_NULL;
return IV_FAIL;
}
if(ps_handle->u4_size != sizeof(iv_obj_t))
{
*(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
*(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
if(ps_handle->pv_codec_handle == NULL)
{
*(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
*(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
return IV_FAIL;
}
break;
default:
*(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
*(pu4_api_op + 1) |= IVD_INVALID_API_CMD;
return IV_FAIL;
}
switch((WORD32)e_cmd)
{
case IV_CMD_GET_NUM_MEM_REC:
{
ihevcd_cxa_num_mem_rec_ip_t *ps_ip =
(ihevcd_cxa_num_mem_rec_ip_t *)pv_api_ip;
ihevcd_cxa_num_mem_rec_op_t *ps_op =
(ihevcd_cxa_num_mem_rec_op_t *)pv_api_op;
ps_op->s_ivd_num_mem_rec_op_t.u4_error_code = 0;
if(ps_ip->s_ivd_num_mem_rec_ip_t.u4_size
!= sizeof(ihevcd_cxa_num_mem_rec_ip_t))
{
ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |=
IVD_IP_API_STRUCT_SIZE_INCORRECT;
return (IV_FAIL);
}
if(ps_op->s_ivd_num_mem_rec_op_t.u4_size
!= sizeof(ihevcd_cxa_num_mem_rec_op_t))
{
ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |=
IVD_OP_API_STRUCT_SIZE_INCORRECT;
return (IV_FAIL);
}
}
break;
case IV_CMD_FILL_NUM_MEM_REC:
{
ihevcd_cxa_fill_mem_rec_ip_t *ps_ip =
(ihevcd_cxa_fill_mem_rec_ip_t *)pv_api_ip;
ihevcd_cxa_fill_mem_rec_op_t *ps_op =
(ihevcd_cxa_fill_mem_rec_op_t *)pv_api_op;
iv_mem_rec_t *ps_mem_rec;
WORD32 max_wd = ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd;
WORD32 max_ht = ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht;
max_wd = ALIGN64(max_wd);
max_ht = ALIGN64(max_ht);
ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0;
if((ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size
> sizeof(ihevcd_cxa_fill_mem_rec_ip_t))
|| (ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size
< sizeof(iv_fill_mem_rec_ip_t)))
{
ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
IVD_IP_API_STRUCT_SIZE_INCORRECT;
return (IV_FAIL);
}
if((ps_op->s_ivd_fill_mem_rec_op_t.u4_size
!= sizeof(ihevcd_cxa_fill_mem_rec_op_t))
&& (ps_op->s_ivd_fill_mem_rec_op_t.u4_size
!= sizeof(iv_fill_mem_rec_op_t)))
{
ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
IVD_OP_API_STRUCT_SIZE_INCORRECT;
return (IV_FAIL);
}
if(max_wd < MIN_WD)
{
ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
return (IV_FAIL);
}
if(max_wd > MAX_WD)
{
ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
return (IV_FAIL);
}
if(max_ht < MIN_HT)
{
ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
return (IV_FAIL);
}
if((max_ht * max_wd) > (MAX_HT * MAX_WD))
{
ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
return (IV_FAIL);
}
if(NULL == ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location)
{
ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
IVD_NUM_REC_NOT_SUFFICIENT;
return (IV_FAIL);
}
/* check memrecords sizes are correct */
ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
for(i = 0; i < MEM_REC_CNT; i++)
{
if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
{
ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
}
}
break;
case IV_CMD_INIT:
{
ihevcd_cxa_init_ip_t *ps_ip = (ihevcd_cxa_init_ip_t *)pv_api_ip;
ihevcd_cxa_init_op_t *ps_op = (ihevcd_cxa_init_op_t *)pv_api_op;
iv_mem_rec_t *ps_mem_rec;
WORD32 max_wd = ps_ip->s_ivd_init_ip_t.u4_frm_max_wd;
WORD32 max_ht = ps_ip->s_ivd_init_ip_t.u4_frm_max_ht;
max_wd = ALIGN64(max_wd);
max_ht = ALIGN64(max_ht);
ps_op->s_ivd_init_op_t.u4_error_code = 0;
if((ps_ip->s_ivd_init_ip_t.u4_size > sizeof(ihevcd_cxa_init_ip_t))
|| (ps_ip->s_ivd_init_ip_t.u4_size
< sizeof(ivd_init_ip_t)))
{
ps_op->s_ivd_init_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_init_op_t.u4_error_code |=
IVD_IP_API_STRUCT_SIZE_INCORRECT;
DEBUG("\n");
return (IV_FAIL);
}
if((ps_op->s_ivd_init_op_t.u4_size != sizeof(ihevcd_cxa_init_op_t))
&& (ps_op->s_ivd_init_op_t.u4_size
!= sizeof(ivd_init_op_t)))
{
ps_op->s_ivd_init_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_init_op_t.u4_error_code |=
IVD_OP_API_STRUCT_SIZE_INCORRECT;
DEBUG("\n");
return (IV_FAIL);
}
if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec != MEM_REC_CNT)
{
ps_op->s_ivd_init_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_init_op_t.u4_error_code |=
IVD_INIT_DEC_NOT_SUFFICIENT;
DEBUG("\n");
return (IV_FAIL);
}
if(max_wd < MIN_WD)
{
ps_op->s_ivd_init_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_init_op_t.u4_error_code |=
IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
DEBUG("\n");
return (IV_FAIL);
}
if(max_wd > MAX_WD)
{
ps_op->s_ivd_init_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_init_op_t.u4_error_code |=
IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
DEBUG("\n");
return (IV_FAIL);
}
if(max_ht < MIN_HT)
{
ps_op->s_ivd_init_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_init_op_t.u4_error_code |=
IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
DEBUG("\n");
return (IV_FAIL);
}
if((max_ht * max_wd) > (MAX_HT * MAX_WD))
{
ps_op->s_ivd_init_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_init_op_t.u4_error_code |=
IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
DEBUG("\n");
return (IV_FAIL);
}
if(NULL == ps_ip->s_ivd_init_ip_t.pv_mem_rec_location)
{
ps_op->s_ivd_init_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_init_op_t.u4_error_code |=
IVD_NUM_REC_NOT_SUFFICIENT;
DEBUG("\n");
return (IV_FAIL);
}
if((ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P)
&& (ps_ip->s_ivd_init_ip_t.e_output_format
!= IV_YUV_422ILE)
&& (ps_ip->s_ivd_init_ip_t.e_output_format
!= IV_RGB_565)
&& (ps_ip->s_ivd_init_ip_t.e_output_format
!= IV_RGBA_8888)
&& (ps_ip->s_ivd_init_ip_t.e_output_format
!= IV_YUV_420SP_UV)
&& (ps_ip->s_ivd_init_ip_t.e_output_format
!= IV_YUV_420SP_VU))
{
ps_op->s_ivd_init_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_init_op_t.u4_error_code |=
IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
DEBUG("\n");
return (IV_FAIL);
}
/* verify number of mem records */
if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec < MEM_REC_CNT)
{
ps_op->s_ivd_init_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_init_op_t.u4_error_code |=
IVD_INIT_DEC_MEM_REC_NOT_SUFFICIENT;
DEBUG("\n");
return IV_FAIL;
}
ps_mem_rec = ps_ip->s_ivd_init_ip_t.pv_mem_rec_location;
/* check memrecords sizes are correct */
for(i = 0; i < (WORD32)ps_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++)
{
if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
{
ps_op->s_ivd_init_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_init_op_t.u4_error_code |=
IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
DEBUG("i: %d\n", i);
return IV_FAIL;
}
/* check memrecords pointers are not NULL */
if(ps_mem_rec[i].pv_base == NULL)
{
ps_op->s_ivd_init_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_init_op_t.u4_error_code |=
IVD_INIT_DEC_MEM_REC_BASE_NULL;
DEBUG("i: %d\n", i);
return IV_FAIL;
}
}
/* verify memtabs for overlapping regions */
{
void *start[MEM_REC_CNT];
void *end[MEM_REC_CNT];
start[0] = (ps_mem_rec[0].pv_base);
end[0] = (UWORD8 *)(ps_mem_rec[0].pv_base)
+ ps_mem_rec[0].u4_mem_size - 1;
for(i = 1; i < MEM_REC_CNT; i++)
{
/* This array is populated to check memtab overlapp */
start[i] = (ps_mem_rec[i].pv_base);
end[i] = (UWORD8 *)(ps_mem_rec[i].pv_base)
+ ps_mem_rec[i].u4_mem_size - 1;
for(j = 0; j < i; j++)
{
if((start[i] >= start[j]) && (start[i] <= end[j]))
{
ps_op->s_ivd_init_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_init_op_t.u4_error_code |=
IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
DEBUG("i: %d, j: %d\n", i, j);
return IV_FAIL;
}
if((end[i] >= start[j]) && (end[i] <= end[j]))
{
ps_op->s_ivd_init_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_init_op_t.u4_error_code |=
IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
DEBUG("i: %d, j: %d\n", i, j);
return IV_FAIL;
}
if((start[i] < start[j]) && (end[i] > end[j]))
{
ps_op->s_ivd_init_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_init_op_t.u4_error_code |=
IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
DEBUG("i: %d, j: %d\n", i, j);
return IV_FAIL;
}
}
}
}
{
iv_mem_rec_t mem_rec_ittiam_api[MEM_REC_CNT];
ihevcd_cxa_fill_mem_rec_ip_t s_fill_mem_rec_ip;
ihevcd_cxa_fill_mem_rec_op_t s_fill_mem_rec_op;
IV_API_CALL_STATUS_T e_status;
WORD32 i;
s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.e_cmd =
IV_CMD_FILL_NUM_MEM_REC;
s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location =
mem_rec_ittiam_api;
s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd =
max_wd;
s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht =
max_ht;
if(ps_ip->s_ivd_init_ip_t.u4_size
> offsetof(ihevcd_cxa_init_ip_t, i4_level))
{
s_fill_mem_rec_ip.i4_level = ps_ip->i4_level;
}
else
{
s_fill_mem_rec_ip.i4_level = IHEVC_LEVEL_31;
}
if(ps_ip->s_ivd_init_ip_t.u4_size
> offsetof(ihevcd_cxa_init_ip_t,
u4_num_ref_frames))
{
s_fill_mem_rec_ip.u4_num_ref_frames =
ps_ip->u4_num_ref_frames;
}
else
{
s_fill_mem_rec_ip.u4_num_ref_frames = (MAX_REF_CNT + 1);
}
if(ps_ip->s_ivd_init_ip_t.u4_size
> offsetof(ihevcd_cxa_init_ip_t,
u4_num_reorder_frames))
{
s_fill_mem_rec_ip.u4_num_reorder_frames =
ps_ip->u4_num_reorder_frames;
}
else
{
s_fill_mem_rec_ip.u4_num_reorder_frames = (MAX_REF_CNT + 1);
}
if(ps_ip->s_ivd_init_ip_t.u4_size
> offsetof(ihevcd_cxa_init_ip_t,
u4_num_extra_disp_buf))
{
s_fill_mem_rec_ip.u4_num_extra_disp_buf =
ps_ip->u4_num_extra_disp_buf;
}
else
{
s_fill_mem_rec_ip.u4_num_extra_disp_buf = 0;
}
if(ps_ip->s_ivd_init_ip_t.u4_size
> offsetof(ihevcd_cxa_init_ip_t,
u4_share_disp_buf))
{
#ifndef LOGO_EN
s_fill_mem_rec_ip.u4_share_disp_buf =
ps_ip->u4_share_disp_buf;
#else
s_fill_mem_rec_ip.u4_share_disp_buf = 0;
#endif
}
else
{
s_fill_mem_rec_ip.u4_share_disp_buf = 0;
}
s_fill_mem_rec_ip.e_output_format =
ps_ip->s_ivd_init_ip_t.e_output_format;
if((s_fill_mem_rec_ip.e_output_format != IV_YUV_420P)
&& (s_fill_mem_rec_ip.e_output_format
!= IV_YUV_420SP_UV)
&& (s_fill_mem_rec_ip.e_output_format
!= IV_YUV_420SP_VU))
{
s_fill_mem_rec_ip.u4_share_disp_buf = 0;
}
s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_size =
sizeof(ihevcd_cxa_fill_mem_rec_ip_t);
s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_size =
sizeof(ihevcd_cxa_fill_mem_rec_op_t);
for(i = 0; i < MEM_REC_CNT; i++)
mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t);
e_status = ihevcd_cxa_api_function(NULL,
(void *)&s_fill_mem_rec_ip,
(void *)&s_fill_mem_rec_op);
if(IV_FAIL == e_status)
{
ps_op->s_ivd_init_op_t.u4_error_code =
s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_error_code;
DEBUG("Fail\n");
return (IV_FAIL);
}
for(i = 0; i < MEM_REC_CNT; i++)
{
#ifdef ARMRVDS
if((UWORD32)(ps_mem_rec[i].pv_base) & (mem_rec_ittiam_api[i].u4_mem_alignment - 1))
{
ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR;
DEBUG("Fail\n");
return IV_FAIL;
}
#endif
if(ps_mem_rec[i].u4_mem_size
< mem_rec_ittiam_api[i].u4_mem_size)
{
ps_op->s_ivd_init_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_init_op_t.u4_error_code |=
IVD_INIT_DEC_MEM_REC_INSUFFICIENT_SIZE;
DEBUG("i: %d \n", i);
return IV_FAIL;
}
if(ps_mem_rec[i].u4_mem_alignment
!= mem_rec_ittiam_api[i].u4_mem_alignment)
{
ps_op->s_ivd_init_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_init_op_t.u4_error_code |=
IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR;
DEBUG("i: %d \n", i);
return IV_FAIL;
}
if(ps_mem_rec[i].e_mem_type
!= mem_rec_ittiam_api[i].e_mem_type)
{
UWORD32 check = IV_SUCCESS;
UWORD32 diff = mem_rec_ittiam_api[i].e_mem_type
- ps_mem_rec[i].e_mem_type;
if((ps_mem_rec[i].e_mem_type
<= IV_EXTERNAL_CACHEABLE_SCRATCH_MEM)
&& (mem_rec_ittiam_api[i].e_mem_type
>= IV_INTERNAL_NONCACHEABLE_PERSISTENT_MEM))
{
check = IV_FAIL;
}
if(3 != (mem_rec_ittiam_api[i].e_mem_type % 4))
{
/*
* It is not IV_EXTERNAL_NONCACHEABLE_PERSISTENT_MEM or IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM
*/
if((diff < 1) || (diff > 3))
{
// Difference between 1 and 3 is okay for all cases other than the two filtered
// with the MOD condition above
check = IV_FAIL;
}
}
else
{
if(diff == 1)
{
/*
* This particular case is when codec asked for External Persistent, but got
* Internal Scratch.
*/
check = IV_FAIL;
}
if((diff != 2) && (diff != 3))
{
check = IV_FAIL;
}
}
if(check == IV_FAIL)
{
ps_op->s_ivd_init_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_init_op_t.u4_error_code |=
IVD_INIT_DEC_MEM_REC_INCORRECT_TYPE;
DEBUG("i: %d \n", i);
return IV_FAIL;
}
}
}
}
}
break;
case IVD_CMD_GET_DISPLAY_FRAME:
{
ihevcd_cxa_get_display_frame_ip_t *ps_ip =
(ihevcd_cxa_get_display_frame_ip_t *)pv_api_ip;
ihevcd_cxa_get_display_frame_op_t *ps_op =
(ihevcd_cxa_get_display_frame_op_t *)pv_api_op;
ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0;
if((ps_ip->s_ivd_get_display_frame_ip_t.u4_size
!= sizeof(ihevcd_cxa_get_display_frame_ip_t))
&& (ps_ip->s_ivd_get_display_frame_ip_t.u4_size
!= sizeof(ivd_get_display_frame_ip_t)))
{
ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_get_display_frame_op_t.u4_error_code |=
IVD_IP_API_STRUCT_SIZE_INCORRECT;
return (IV_FAIL);
}
if((ps_op->s_ivd_get_display_frame_op_t.u4_size
!= sizeof(ihevcd_cxa_get_display_frame_op_t))
&& (ps_op->s_ivd_get_display_frame_op_t.u4_size
!= sizeof(ivd_get_display_frame_op_t)))
{
ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_get_display_frame_op_t.u4_error_code |=
IVD_OP_API_STRUCT_SIZE_INCORRECT;
return (IV_FAIL);
}
}
break;
case IVD_CMD_REL_DISPLAY_FRAME:
{
ihevcd_cxa_rel_display_frame_ip_t *ps_ip =
(ihevcd_cxa_rel_display_frame_ip_t *)pv_api_ip;
ihevcd_cxa_rel_display_frame_op_t *ps_op =
(ihevcd_cxa_rel_display_frame_op_t *)pv_api_op;
ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0;
if((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size
!= sizeof(ihevcd_cxa_rel_display_frame_ip_t))
&& (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size
!= sizeof(ivd_rel_display_frame_ip_t)))
{
ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |=
IVD_IP_API_STRUCT_SIZE_INCORRECT;
return (IV_FAIL);
}
if((ps_op->s_ivd_rel_display_frame_op_t.u4_size
!= sizeof(ihevcd_cxa_rel_display_frame_op_t))
&& (ps_op->s_ivd_rel_display_frame_op_t.u4_size
!= sizeof(ivd_rel_display_frame_op_t)))
{
ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |=
IVD_OP_API_STRUCT_SIZE_INCORRECT;
return (IV_FAIL);
}
}
break;
case IVD_CMD_SET_DISPLAY_FRAME:
{
ihevcd_cxa_set_display_frame_ip_t *ps_ip =
(ihevcd_cxa_set_display_frame_ip_t *)pv_api_ip;
ihevcd_cxa_set_display_frame_op_t *ps_op =
(ihevcd_cxa_set_display_frame_op_t *)pv_api_op;
UWORD32 j;
ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0;
if((ps_ip->s_ivd_set_display_frame_ip_t.u4_size
!= sizeof(ihevcd_cxa_set_display_frame_ip_t))
&& (ps_ip->s_ivd_set_display_frame_ip_t.u4_size
!= sizeof(ivd_set_display_frame_ip_t)))
{
ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
IVD_IP_API_STRUCT_SIZE_INCORRECT;
return (IV_FAIL);
}
if((ps_op->s_ivd_set_display_frame_op_t.u4_size
!= sizeof(ihevcd_cxa_set_display_frame_op_t))
&& (ps_op->s_ivd_set_display_frame_op_t.u4_size
!= sizeof(ivd_set_display_frame_op_t)))
{
ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
IVD_OP_API_STRUCT_SIZE_INCORRECT;
return (IV_FAIL);
}
if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0)
{
ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
IVD_DISP_FRM_ZERO_OP_BUFS;
return IV_FAIL;
}
for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs;
j++)
{
if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs
== 0)
{
ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
IVD_DISP_FRM_ZERO_OP_BUFS;
return IV_FAIL;
}
for(i = 0;
i
< (WORD32)ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs;
i++)
{
if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i]
== NULL)
{
ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
IVD_DISP_FRM_OP_BUF_NULL;
return IV_FAIL;
}
if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i]
== 0)
{
ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
return IV_FAIL;
}
}
}
}
break;
case IVD_CMD_VIDEO_DECODE:
{
ihevcd_cxa_video_decode_ip_t *ps_ip =
(ihevcd_cxa_video_decode_ip_t *)pv_api_ip;
ihevcd_cxa_video_decode_op_t *ps_op =
(ihevcd_cxa_video_decode_op_t *)pv_api_op;
DEBUG("The input bytes is: %d",
ps_ip->s_ivd_video_decode_ip_t.u4_num_Bytes);
ps_op->s_ivd_video_decode_op_t.u4_error_code = 0;
if(ps_ip->s_ivd_video_decode_ip_t.u4_size
!= sizeof(ihevcd_cxa_video_decode_ip_t)
&& ps_ip->s_ivd_video_decode_ip_t.u4_size
!= offsetof(ivd_video_decode_ip_t,
s_out_buffer))
{
ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_video_decode_op_t.u4_error_code |=
IVD_IP_API_STRUCT_SIZE_INCORRECT;
return (IV_FAIL);
}
if(ps_op->s_ivd_video_decode_op_t.u4_size
!= sizeof(ihevcd_cxa_video_decode_op_t)
&& ps_op->s_ivd_video_decode_op_t.u4_size
!= offsetof(ivd_video_decode_op_t,
u4_output_present))
{
ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_video_decode_op_t.u4_error_code |=
IVD_OP_API_STRUCT_SIZE_INCORRECT;
return (IV_FAIL);
}
}
break;
case IV_CMD_RETRIEVE_MEMREC:
{
ihevcd_cxa_retrieve_mem_rec_ip_t *ps_ip =
(ihevcd_cxa_retrieve_mem_rec_ip_t *)pv_api_ip;
ihevcd_cxa_retrieve_mem_rec_op_t *ps_op =
(ihevcd_cxa_retrieve_mem_rec_op_t *)pv_api_op;
iv_mem_rec_t *ps_mem_rec;
ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = 0;
if(ps_ip->s_ivd_retrieve_mem_rec_ip_t.u4_size
!= sizeof(ihevcd_cxa_retrieve_mem_rec_ip_t))
{
ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |=
IVD_IP_API_STRUCT_SIZE_INCORRECT;
return (IV_FAIL);
}
if(ps_op->s_ivd_retrieve_mem_rec_op_t.u4_size
!= sizeof(ihevcd_cxa_retrieve_mem_rec_op_t))
{
ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |=
IVD_OP_API_STRUCT_SIZE_INCORRECT;
return (IV_FAIL);
}
ps_mem_rec = ps_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location;
/* check memrecords sizes are correct */
for(i = 0; i < MEM_REC_CNT; i++)
{
if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
{
ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |=
IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
}
}
break;
case IVD_CMD_VIDEO_CTL:
{
UWORD32 *pu4_ptr_cmd;
UWORD32 sub_command;
pu4_ptr_cmd = (UWORD32 *)pv_api_ip;
pu4_ptr_cmd += 2;
sub_command = *pu4_ptr_cmd;
switch(sub_command)
{
case IVD_CMD_CTL_SETPARAMS:
{
ihevcd_cxa_ctl_set_config_ip_t *ps_ip;
ihevcd_cxa_ctl_set_config_op_t *ps_op;
ps_ip = (ihevcd_cxa_ctl_set_config_ip_t *)pv_api_ip;
ps_op = (ihevcd_cxa_ctl_set_config_op_t *)pv_api_op;
if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size
!= sizeof(ihevcd_cxa_ctl_set_config_ip_t))
{
ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |=
IVD_IP_API_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
}
//no break; is needed here
case IVD_CMD_CTL_SETDEFAULT:
{
ihevcd_cxa_ctl_set_config_op_t *ps_op;
ps_op = (ihevcd_cxa_ctl_set_config_op_t *)pv_api_op;
if(ps_op->s_ivd_ctl_set_config_op_t.u4_size
!= sizeof(ihevcd_cxa_ctl_set_config_op_t))
{
ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |=
IVD_OP_API_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
}
break;
case IVD_CMD_CTL_GETPARAMS:
{
ihevcd_cxa_ctl_getstatus_ip_t *ps_ip;
ihevcd_cxa_ctl_getstatus_op_t *ps_op;
ps_ip = (ihevcd_cxa_ctl_getstatus_ip_t *)pv_api_ip;
ps_op = (ihevcd_cxa_ctl_getstatus_op_t *)pv_api_op;
if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size
!= sizeof(ihevcd_cxa_ctl_getstatus_ip_t))
{
ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |=
IVD_IP_API_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
if((ps_op->s_ivd_ctl_getstatus_op_t.u4_size
!= sizeof(ihevcd_cxa_ctl_getstatus_op_t)) &&
(ps_op->s_ivd_ctl_getstatus_op_t.u4_size
!= sizeof(ivd_ctl_getstatus_op_t)))
{
ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |=
IVD_OP_API_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
}
break;
case IVD_CMD_CTL_GETBUFINFO:
{
ihevcd_cxa_ctl_getbufinfo_ip_t *ps_ip;
ihevcd_cxa_ctl_getbufinfo_op_t *ps_op;
ps_ip = (ihevcd_cxa_ctl_getbufinfo_ip_t *)pv_api_ip;
ps_op = (ihevcd_cxa_ctl_getbufinfo_op_t *)pv_api_op;
if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size
!= sizeof(ihevcd_cxa_ctl_getbufinfo_ip_t))
{
ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |=
IVD_IP_API_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size
!= sizeof(ihevcd_cxa_ctl_getbufinfo_op_t))
{
ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |=
IVD_OP_API_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
}
break;
case IVD_CMD_CTL_GETVERSION:
{
ihevcd_cxa_ctl_getversioninfo_ip_t *ps_ip;
ihevcd_cxa_ctl_getversioninfo_op_t *ps_op;
ps_ip = (ihevcd_cxa_ctl_getversioninfo_ip_t *)pv_api_ip;
ps_op = (ihevcd_cxa_ctl_getversioninfo_op_t *)pv_api_op;
if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size
!= sizeof(ihevcd_cxa_ctl_getversioninfo_ip_t))
{
ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |=
IVD_IP_API_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size
!= sizeof(ihevcd_cxa_ctl_getversioninfo_op_t))
{
ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |=
IVD_OP_API_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
}
break;
case IVD_CMD_CTL_FLUSH:
{
ihevcd_cxa_ctl_flush_ip_t *ps_ip;
ihevcd_cxa_ctl_flush_op_t *ps_op;
ps_ip = (ihevcd_cxa_ctl_flush_ip_t *)pv_api_ip;
ps_op = (ihevcd_cxa_ctl_flush_op_t *)pv_api_op;
if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size
!= sizeof(ihevcd_cxa_ctl_flush_ip_t))
{
ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_ctl_flush_op_t.u4_error_code |=
IVD_IP_API_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
if(ps_op->s_ivd_ctl_flush_op_t.u4_size
!= sizeof(ihevcd_cxa_ctl_flush_op_t))
{
ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_ctl_flush_op_t.u4_error_code |=
IVD_OP_API_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
}
break;
case IVD_CMD_CTL_RESET:
{
ihevcd_cxa_ctl_reset_ip_t *ps_ip;
ihevcd_cxa_ctl_reset_op_t *ps_op;
ps_ip = (ihevcd_cxa_ctl_reset_ip_t *)pv_api_ip;
ps_op = (ihevcd_cxa_ctl_reset_op_t *)pv_api_op;
if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size
!= sizeof(ihevcd_cxa_ctl_reset_ip_t))
{
ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_ctl_reset_op_t.u4_error_code |=
IVD_IP_API_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
if(ps_op->s_ivd_ctl_reset_op_t.u4_size
!= sizeof(ihevcd_cxa_ctl_reset_op_t))
{
ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1
<< IVD_UNSUPPORTEDPARAM;
ps_op->s_ivd_ctl_reset_op_t.u4_error_code |=
IVD_OP_API_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
}
break;
case IHEVCD_CXA_CMD_CTL_DEGRADE:
{
ihevcd_cxa_ctl_degrade_ip_t *ps_ip;
ihevcd_cxa_ctl_degrade_op_t *ps_op;
ps_ip = (ihevcd_cxa_ctl_degrade_ip_t *)pv_api_ip;
ps_op = (ihevcd_cxa_ctl_degrade_op_t *)pv_api_op;
if(ps_ip->u4_size
!= sizeof(ihevcd_cxa_ctl_degrade_ip_t))
{
ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
ps_op->u4_error_code |=
IVD_IP_API_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
if(ps_op->u4_size
!= sizeof(ihevcd_cxa_ctl_degrade_op_t))
{
ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
ps_op->u4_error_code |=
IVD_OP_API_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
if((ps_ip->i4_degrade_pics < 0) ||
(ps_ip->i4_degrade_pics > 4) ||
(ps_ip->i4_nondegrade_interval < 0) ||
(ps_ip->i4_degrade_type < 0) ||
(ps_ip->i4_degrade_type > 15))
{
ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
return IV_FAIL;
}
break;
}
case IHEVCD_CXA_CMD_CTL_GET_BUFFER_DIMENSIONS:
{
ihevcd_cxa_ctl_get_frame_dimensions_ip_t *ps_ip;
ihevcd_cxa_ctl_get_frame_dimensions_op_t *ps_op;
ps_ip =
(ihevcd_cxa_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
ps_op =
(ihevcd_cxa_ctl_get_frame_dimensions_op_t *)pv_api_op;
if(ps_ip->u4_size
!= sizeof(ihevcd_cxa_ctl_get_frame_dimensions_ip_t))
{
ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
ps_op->u4_error_code |=
IVD_IP_API_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
if(ps_op->u4_size
!= sizeof(ihevcd_cxa_ctl_get_frame_dimensions_op_t))
{
ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
ps_op->u4_error_code |=
IVD_OP_API_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
break;
}
case IHEVCD_CXA_CMD_CTL_GET_VUI_PARAMS:
{
ihevcd_cxa_ctl_get_vui_params_ip_t *ps_ip;
ihevcd_cxa_ctl_get_vui_params_op_t *ps_op;
ps_ip =
(ihevcd_cxa_ctl_get_vui_params_ip_t *)pv_api_ip;
ps_op =
(ihevcd_cxa_ctl_get_vui_params_op_t *)pv_api_op;
if(ps_ip->u4_size
!= sizeof(ihevcd_cxa_ctl_get_vui_params_ip_t))
{
ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
ps_op->u4_error_code |=
IVD_IP_API_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
if(ps_op->u4_size
!= sizeof(ihevcd_cxa_ctl_get_vui_params_op_t))
{
ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
ps_op->u4_error_code |=
IVD_OP_API_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
break;
}
case IHEVCD_CXA_CMD_CTL_SET_NUM_CORES:
{
ihevcd_cxa_ctl_set_num_cores_ip_t *ps_ip;
ihevcd_cxa_ctl_set_num_cores_op_t *ps_op;
ps_ip = (ihevcd_cxa_ctl_set_num_cores_ip_t *)pv_api_ip;
ps_op = (ihevcd_cxa_ctl_set_num_cores_op_t *)pv_api_op;
if(ps_ip->u4_size
!= sizeof(ihevcd_cxa_ctl_set_num_cores_ip_t))
{
ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
ps_op->u4_error_code |=
IVD_IP_API_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
if(ps_op->u4_size
!= sizeof(ihevcd_cxa_ctl_set_num_cores_op_t))
{
ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
ps_op->u4_error_code |=
IVD_OP_API_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
#ifdef MULTICORE
if((ps_ip->u4_num_cores < 1) || (ps_ip->u4_num_cores > MAX_NUM_CORES))
#else
if(ps_ip->u4_num_cores != 1)
#endif
{
ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
return IV_FAIL;
}
break;
}
case IHEVCD_CXA_CMD_CTL_SET_PROCESSOR:
{
ihevcd_cxa_ctl_set_processor_ip_t *ps_ip;
ihevcd_cxa_ctl_set_processor_op_t *ps_op;
ps_ip = (ihevcd_cxa_ctl_set_processor_ip_t *)pv_api_ip;
ps_op = (ihevcd_cxa_ctl_set_processor_op_t *)pv_api_op;
if(ps_ip->u4_size
!= sizeof(ihevcd_cxa_ctl_set_processor_ip_t))
{
ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
ps_op->u4_error_code |=
IVD_IP_API_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
if(ps_op->u4_size
!= sizeof(ihevcd_cxa_ctl_set_processor_op_t))
{
ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
ps_op->u4_error_code |=
IVD_OP_API_STRUCT_SIZE_INCORRECT;
return IV_FAIL;
}
break;
}
default:
*(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
*(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD;
return IV_FAIL;
}
}
break;
default:
*(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
*(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD;
return IV_FAIL;
}
return IV_SUCCESS;
}
/**
*******************************************************************************
*
* @brief
* Sets default dynamic parameters
*
* @par Description:
* Sets default dynamic parameters. Will be called in ihevcd_init() to ensure
* that even if set_params is not called, codec continues to work
*
* @param[in] ps_codec_obj
* Pointer to codec object at API level
*
* @param[in] pv_api_ip
* Pointer to input argument structure
*
* @param[out] pv_api_op
* Pointer to output argument structure
*
* @returns Status
*
* @remarks
*
*
*******************************************************************************
*/
WORD32 ihevcd_set_default_params(codec_t *ps_codec)
{
WORD32 ret = IV_SUCCESS;
ps_codec->e_pic_skip_mode = IVD_SKIP_NONE;
ps_codec->i4_strd = 0;
ps_codec->i4_disp_strd = 0;
ps_codec->i4_header_mode = 0;
ps_codec->e_pic_out_order = IVD_DISPLAY_FRAME_OUT;
return ret;
}
void ihevcd_update_function_ptr(codec_t *ps_codec)
{
/* Init inter pred function array */
ps_codec->apf_inter_pred[0] = NULL;
ps_codec->apf_inter_pred[1] = (pf_inter_pred)ps_codec->s_func_selector.ihevc_inter_pred_luma_copy_fptr;
ps_codec->apf_inter_pred[2] = (pf_inter_pred)ps_codec->s_func_selector.ihevc_inter_pred_luma_vert_fptr;
ps_codec->apf_inter_pred[3] = (pf_inter_pred)ps_codec->s_func_selector.ihevc_inter_pred_luma_horz_fptr;
ps_codec->apf_inter_pred[4] = (pf_inter_pred)ps_codec->s_func_selector.ihevc_inter_pred_luma_horz_w16out_fptr;
ps_codec->apf_inter_pred[5] = (pf_inter_pred)ps_codec->s_func_selector.ihevc_inter_pred_luma_copy_w16out_fptr;
ps_codec->apf_inter_pred[6] = (pf_inter_pred)ps_codec->s_func_selector.ihevc_inter_pred_luma_vert_w16out_fptr;
ps_codec->apf_inter_pred[7] = (pf_inter_pred)ps_codec->s_func_selector.ihevc_inter_pred_luma_horz_w16out_fptr;
ps_codec->apf_inter_pred[8] = (pf_inter_pred)ps_codec->s_func_selector.ihevc_inter_pred_luma_horz_w16out_fptr;
ps_codec->apf_inter_pred[9] = (pf_inter_pred)ps_codec->s_func_selector.ihevc_inter_pred_luma_vert_w16inp_fptr;
ps_codec->apf_inter_pred[10] = (pf_inter_pred)ps_codec->s_func_selector.ihevc_inter_pred_luma_vert_w16inp_w16out_fptr;
ps_codec->apf_inter_pred[11] = NULL;
ps_codec->apf_inter_pred[12] = (pf_inter_pred)ps_codec->s_func_selector.ihevc_inter_pred_chroma_copy_fptr;
ps_codec->apf_inter_pred[13] = (pf_inter_pred)ps_codec->s_func_selector.ihevc_inter_pred_chroma_vert_fptr;
ps_codec->apf_inter_pred[14] = (pf_inter_pred)ps_codec->s_func_selector.ihevc_inter_pred_chroma_horz_fptr;
ps_codec->apf_inter_pred[15] = (pf_inter_pred)ps_codec->s_func_selector.ihevc_inter_pred_chroma_horz_w16out_fptr;
ps_codec->apf_inter_pred[16] = (pf_inter_pred)ps_codec->s_func_selector.ihevc_inter_pred_chroma_copy_w16out_fptr;
ps_codec->apf_inter_pred[17] = (pf_inter_pred)ps_codec->s_func_selector.ihevc_inter_pred_chroma_vert_w16out_fptr;
ps_codec->apf_inter_pred[18] = (pf_inter_pred)ps_codec->s_func_selector.ihevc_inter_pred_chroma_horz_w16out_fptr;
ps_codec->apf_inter_pred[19] = (pf_inter_pred)ps_codec->s_func_selector.ihevc_inter_pred_chroma_horz_w16out_fptr;
ps_codec->apf_inter_pred[20] = (pf_inter_pred)ps_codec->s_func_selector.ihevc_inter_pred_chroma_vert_w16inp_fptr;
ps_codec->apf_inter_pred[21] = (pf_inter_pred)ps_codec->s_func_selector.ihevc_inter_pred_chroma_vert_w16inp_w16out_fptr;
/* Init intra pred function array */
ps_codec->apf_intra_pred_luma[0] = (pf_intra_pred)NULL;
ps_codec->apf_intra_pred_luma[1] = (pf_intra_pred)ps_codec->s_func_selector.ihevc_intra_pred_luma_planar_fptr;
ps_codec->apf_intra_pred_luma[2] = (pf_intra_pred)ps_codec->s_func_selector.ihevc_intra_pred_luma_dc_fptr;
ps_codec->apf_intra_pred_luma[3] = (pf_intra_pred)ps_codec->s_func_selector.ihevc_intra_pred_luma_mode2_fptr;
ps_codec->apf_intra_pred_luma[4] = (pf_intra_pred)ps_codec->s_func_selector.ihevc_intra_pred_luma_mode_3_to_9_fptr;
ps_codec->apf_intra_pred_luma[5] = (pf_intra_pred)ps_codec->s_func_selector.ihevc_intra_pred_luma_horz_fptr;
ps_codec->apf_intra_pred_luma[6] = (pf_intra_pred)ps_codec->s_func_selector.ihevc_intra_pred_luma_mode_11_to_17_fptr;
ps_codec->apf_intra_pred_luma[7] = (pf_intra_pred)ps_codec->s_func_selector.ihevc_intra_pred_luma_mode_18_34_fptr;
ps_codec->apf_intra_pred_luma[8] = (pf_intra_pred)ps_codec->s_func_selector.ihevc_intra_pred_luma_mode_19_to_25_fptr;
ps_codec->apf_intra_pred_luma[9] = (pf_intra_pred)ps_codec->s_func_selector.ihevc_intra_pred_luma_ver_fptr;
ps_codec->apf_intra_pred_luma[10] = (pf_intra_pred)ps_codec->s_func_selector.ihevc_intra_pred_luma_mode_27_to_33_fptr;
ps_codec->apf_intra_pred_chroma[0] = (pf_intra_pred)NULL;
ps_codec->apf_intra_pred_chroma[1] = (pf_intra_pred)ps_codec->s_func_selector.ihevc_intra_pred_chroma_planar_fptr;
ps_codec->apf_intra_pred_chroma[2] = (pf_intra_pred)ps_codec->s_func_selector.ihevc_intra_pred_chroma_dc_fptr;
ps_codec->apf_intra_pred_chroma[3] = (pf_intra_pred)ps_codec->s_func_selector.ihevc_intra_pred_chroma_mode2_fptr;
ps_codec->apf_intra_pred_chroma[4] = (pf_intra_pred)ps_codec->s_func_selector.ihevc_intra_pred_chroma_mode_3_to_9_fptr;
ps_codec->apf_intra_pred_chroma[5] = (pf_intra_pred)ps_codec->s_func_selector.ihevc_intra_pred_chroma_horz_fptr;
ps_codec->apf_intra_pred_chroma[6] = (pf_intra_pred)ps_codec->s_func_selector.ihevc_intra_pred_chroma_mode_11_to_17_fptr;
ps_codec->apf_intra_pred_chroma[7] = (pf_intra_pred)ps_codec->s_func_selector.ihevc_intra_pred_chroma_mode_18_34_fptr;
ps_codec->apf_intra_pred_chroma[8] = (pf_intra_pred)ps_codec->s_func_selector.ihevc_intra_pred_chroma_mode_19_to_25_fptr;
ps_codec->apf_intra_pred_chroma[9] = (pf_intra_pred)ps_codec->s_func_selector.ihevc_intra_pred_chroma_ver_fptr;
ps_codec->apf_intra_pred_chroma[10] = (pf_intra_pred)ps_codec->s_func_selector.ihevc_intra_pred_chroma_mode_27_to_33_fptr;
/* Init itrans_recon function array */
ps_codec->apf_itrans_recon[0] = (pf_itrans_recon)ps_codec->s_func_selector.ihevc_itrans_recon_4x4_ttype1_fptr;
ps_codec->apf_itrans_recon[1] = (pf_itrans_recon)ps_codec->s_func_selector.ihevc_itrans_recon_4x4_fptr;
ps_codec->apf_itrans_recon[2] = (pf_itrans_recon)ps_codec->s_func_selector.ihevc_itrans_recon_8x8_fptr;
ps_codec->apf_itrans_recon[3] = (pf_itrans_recon)ps_codec->s_func_selector.ihevc_itrans_recon_16x16_fptr;
ps_codec->apf_itrans_recon[4] = (pf_itrans_recon)ps_codec->s_func_selector.ihevc_itrans_recon_32x32_fptr;
ps_codec->apf_itrans_recon[5] = (pf_itrans_recon)ps_codec->s_func_selector.ihevc_chroma_itrans_recon_4x4_fptr;
ps_codec->apf_itrans_recon[6] = (pf_itrans_recon)ps_codec->s_func_selector.ihevc_chroma_itrans_recon_8x8_fptr;
ps_codec->apf_itrans_recon[7] = (pf_itrans_recon)ps_codec->s_func_selector.ihevc_chroma_itrans_recon_16x16_fptr;
/* Init recon function array */
ps_codec->apf_recon[0] = (pf_recon)ps_codec->s_func_selector.ihevc_recon_4x4_ttype1_fptr;
ps_codec->apf_recon[1] = (pf_recon)ps_codec->s_func_selector.ihevc_recon_4x4_fptr;
ps_codec->apf_recon[2] = (pf_recon)ps_codec->s_func_selector.ihevc_recon_8x8_fptr;
ps_codec->apf_recon[3] = (pf_recon)ps_codec->s_func_selector.ihevc_recon_16x16_fptr;
ps_codec->apf_recon[4] = (pf_recon)ps_codec->s_func_selector.ihevc_recon_32x32_fptr;
ps_codec->apf_recon[5] = (pf_recon)ps_codec->s_func_selector.ihevc_chroma_recon_4x4_fptr;
ps_codec->apf_recon[6] = (pf_recon)ps_codec->s_func_selector.ihevc_chroma_recon_8x8_fptr;
ps_codec->apf_recon[7] = (pf_recon)ps_codec->s_func_selector.ihevc_chroma_recon_16x16_fptr;
/* Init itrans_recon_dc function array */
ps_codec->apf_itrans_recon_dc[0] = (pf_itrans_recon_dc)ps_codec->s_func_selector.ihevcd_itrans_recon_dc_luma_fptr;
ps_codec->apf_itrans_recon_dc[1] = (pf_itrans_recon_dc)ps_codec->s_func_selector.ihevcd_itrans_recon_dc_chroma_fptr;
/* Init sao function array */
ps_codec->apf_sao_luma[0] = (pf_sao_luma)ps_codec->s_func_selector.ihevc_sao_edge_offset_class0_fptr;
ps_codec->apf_sao_luma[1] = (pf_sao_luma)ps_codec->s_func_selector.ihevc_sao_edge_offset_class1_fptr;
ps_codec->apf_sao_luma[2] = (pf_sao_luma)ps_codec->s_func_selector.ihevc_sao_edge_offset_class2_fptr;
ps_codec->apf_sao_luma[3] = (pf_sao_luma)ps_codec->s_func_selector.ihevc_sao_edge_offset_class3_fptr;
ps_codec->apf_sao_chroma[0] = (pf_sao_chroma)ps_codec->s_func_selector.ihevc_sao_edge_offset_class0_chroma_fptr;
ps_codec->apf_sao_chroma[1] = (pf_sao_chroma)ps_codec->s_func_selector.ihevc_sao_edge_offset_class1_chroma_fptr;
ps_codec->apf_sao_chroma[2] = (pf_sao_chroma)ps_codec->s_func_selector.ihevc_sao_edge_offset_class2_chroma_fptr;
ps_codec->apf_sao_chroma[3] = (pf_sao_chroma)ps_codec->s_func_selector.ihevc_sao_edge_offset_class3_chroma_fptr;
}
/**
*******************************************************************************
*
* @brief
* Initialize the context. This will be called by init_mem_rec and during
* reset
*
* @par Description:
* Initializes the context
*
* @param[in] ps_codec
* Codec context pointer
*
* @returns Status
*
* @remarks
*
*
*******************************************************************************
*/
WORD32 ihevcd_init(codec_t *ps_codec)
{
WORD32 status = IV_SUCCESS;
WORD32 i;
ps_codec->i4_num_disp_bufs = 1;
ps_codec->i4_flush_mode = 0;
ps_codec->i4_ht = ps_codec->i4_disp_ht = ps_codec->i4_max_ht;
ps_codec->i4_wd = ps_codec->i4_disp_wd = ps_codec->i4_max_wd;
ps_codec->i4_strd = 0;
ps_codec->i4_disp_strd = 0;
ps_codec->i4_num_cores = 1;
ps_codec->u4_pic_cnt = 0;
ps_codec->u4_disp_cnt = 0;
ps_codec->i4_header_mode = 0;
ps_codec->i4_header_in_slice_mode = 0;
ps_codec->i4_sps_done = 0;
ps_codec->i4_pps_done = 0;
ps_codec->i4_init_done = 1;
ps_codec->i4_first_pic_done = 0;
ps_codec->s_parse.i4_first_pic_init = 0;
ps_codec->i4_error_code = 0;
ps_codec->i4_reset_flag = 0;
ps_codec->i4_cra_as_first_pic = 1;
ps_codec->i4_rasl_output_flag = 0;
ps_codec->i4_prev_poc_msb = 0;
ps_codec->i4_prev_poc_lsb = -1;
ps_codec->i4_max_prev_poc_lsb = -1;
ps_codec->s_parse.i4_abs_pic_order_cnt = -1;
/* Set ref chroma format by default to 420SP UV interleaved */
ps_codec->e_ref_chroma_fmt = IV_YUV_420SP_UV;
/* If the codec is in shared mode and required format is 420 SP VU interleaved then change
* reference buffers chroma format
*/
if(IV_YUV_420SP_VU == ps_codec->e_chroma_fmt)
{
ps_codec->e_ref_chroma_fmt = IV_YUV_420SP_VU;
}
ps_codec->i4_disable_deblk_pic = 0;
ps_codec->i4_degrade_pic_cnt = 0;
ps_codec->i4_degrade_pics = 0;
ps_codec->i4_degrade_type = 0;
ps_codec->i4_disable_sao_pic = 0;
ps_codec->i4_fullpel_inter_pred = 0;
ps_codec->u4_enable_fmt_conv_ahead = 0;
ps_codec->i4_share_disp_buf_cnt = 0;
{
sps_t *ps_sps = ps_codec->ps_sps_base;
pps_t *ps_pps = ps_codec->ps_pps_base;
for(i = 0; i < MAX_SPS_CNT; i++)
{
ps_sps->i1_sps_valid = 0;
ps_sps++;
}
for(i = 0; i < MAX_PPS_CNT; i++)
{
ps_pps->i1_pps_valid = 0;
ps_pps++;
}
}
ihevcd_set_default_params(ps_codec);
ps_codec->pv_proc_jobq = ihevcd_jobq_init(ps_codec->pv_proc_jobq_buf, ps_codec->i4_proc_jobq_buf_size);
RETURN_IF((ps_codec->pv_proc_jobq == NULL), IV_FAIL);
/* Update the jobq context to all the threads */
ps_codec->s_parse.pv_proc_jobq = ps_codec->pv_proc_jobq;
for(i = 0; i < MAX_PROCESS_THREADS; i++)
{
ps_codec->as_process[i].pv_proc_jobq = ps_codec->pv_proc_jobq;
ps_codec->as_process[i].i4_id = i;
ps_codec->as_process[i].ps_codec = ps_codec;
/* Set the following to zero assuming it is a single core solution
* When threads are launched these will be set appropriately
*/
ps_codec->as_process[i].i4_check_parse_status = 0;
ps_codec->as_process[i].i4_check_proc_status = 0;
}
/* Initialize MV Bank buffer manager */
ihevc_buf_mgr_init((buf_mgr_t *)ps_codec->pv_mv_buf_mgr);
/* Initialize Picture buffer manager */
ihevc_buf_mgr_init((buf_mgr_t *)ps_codec->pv_pic_buf_mgr);
ps_codec->ps_pic_buf = (pic_buf_t *)ps_codec->pv_pic_buf_base;
memset(ps_codec->ps_pic_buf, 0, BUF_MGR_MAX_CNT * sizeof(pic_buf_t));
/* Initialize display buffer manager */
ihevc_disp_mgr_init((disp_mgr_t *)ps_codec->pv_disp_buf_mgr);
/* Initialize dpb manager */
ihevc_dpb_mgr_init((dpb_mgr_t *)ps_codec->pv_dpb_mgr);
ps_codec->e_processor_soc = SOC_GENERIC;
/* The following can be over-ridden using soc parameter as a hack */
ps_codec->u4_nctb = 0x7FFFFFFF;
ihevcd_init_arch(ps_codec);
ihevcd_init_function_ptr(ps_codec);
ihevcd_update_function_ptr(ps_codec);
return status;
}
/**
*******************************************************************************
*
* @brief
* Gets number of memory records required by the codec
*
* @par Description:
* Gets codec mem record requirements and adds concealment modules
* requirements
*
* @param[in] pv_api_ip
* Pointer to input argument structure
*
* @param[out] pv_api_op
* Pointer to output argument structure
*
* @returns Status
*
* @remarks
*
*
*******************************************************************************
*/
WORD32 ihevcd_get_num_rec(void *pv_api_ip, void *pv_api_op)
{
iv_num_mem_rec_op_t *ps_mem_q_op;
UNUSED(pv_api_ip);
ps_mem_q_op = (iv_num_mem_rec_op_t *)pv_api_op;
ps_mem_q_op->u4_num_mem_rec = MEM_REC_CNT;
DEBUG("Get num mem records without concealment %d\n",
ps_mem_q_op->u4_num_mem_rec);
#ifdef APPLY_CONCEALMENT
{
IV_API_CALL_STATUS_T status;
icncl_num_mem_rec_ip_t cncl_mem_ip;
icncl_num_mem_rec_op_t cncl_mem_op;
cncl_mem_ip.s_ivd_num_rec_ip_t.e_cmd = IV_CMD_GET_NUM_MEM_REC;
cncl_mem_ip.s_ivd_num_rec_ip_t.u4_size = sizeof(icncl_num_mem_rec_ip_t);
status = icncl_api_function(NULL, (void *)&cncl_mem_ip, (void *)&cncl_mem_op);
if(status == IV_SUCCESS)
{
/* Add the concealment library's memory requirements */
ps_mem_q_op->u4_num_mem_rec += cncl_mem_op.s_ivd_num_mem_rec_op_t.u4_num_mem_rec;
DEBUG("Get num mem records %d\n", ps_mem_q_op->u4_num_mem_rec);
return status; /* Nothing else to do, return */
}
else
{
/*
* Something went wrong with the concealment library call.
*/
DEBUG("ERROR: Get num mem records %d\n", ps_mem_q_op->u4_num_mem_rec);
return status;
}
}
#endif //APPLY_CONCEALMENT
return IV_SUCCESS;
}
/**
*******************************************************************************
*
* @brief
* Fills memory requirements of the codec
*
* @par Description:
* Gets codec mem record requirements and adds concealment modules
* requirements
*
* @param[in] pv_api_ip
* Pointer to input argument structure
*
* @param[out] pv_api_op
* Pointer to output argument structure
*
* @returns Status
*
* @remarks
*
*
*******************************************************************************
*/
WORD32 ihevcd_fill_num_mem_rec(void *pv_api_ip, void *pv_api_op)
{
ihevcd_cxa_fill_mem_rec_ip_t *ps_mem_q_ip;
ihevcd_cxa_fill_mem_rec_op_t *ps_mem_q_op;
WORD32 level;
WORD32 num_reorder_frames;
WORD32 num_ref_frames;
WORD32 num_extra_disp_bufs;
WORD32 max_dpb_size;
iv_mem_rec_t *ps_mem_rec;
iv_mem_rec_t *ps_mem_rec_base;
WORD32 no_of_mem_rec_filled;
WORD32 chroma_format, share_disp_buf;
WORD32 max_ctb_cnt;
WORD32 max_wd_luma, max_wd_chroma;
WORD32 max_ht_luma, max_ht_chroma;
WORD32 max_tile_cols, max_tile_rows;
WORD32 max_ctb_rows, max_ctb_cols;
WORD32 max_num_cu_cols;
WORD32 i;
WORD32 max_num_4x4_cols;
IV_API_CALL_STATUS_T status = IV_SUCCESS;
no_of_mem_rec_filled = 0;
//TODO: Remove as and when the following are used
UNUSED(num_extra_disp_bufs);
UNUSED(no_of_mem_rec_filled);
UNUSED(max_wd_chroma);
UNUSED(max_ht_chroma);
ps_mem_q_ip = (ihevcd_cxa_fill_mem_rec_ip_t *)pv_api_ip;
ps_mem_q_op = (ihevcd_cxa_fill_mem_rec_op_t *)pv_api_op;
if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
> offsetof(ihevcd_cxa_fill_mem_rec_ip_t, i4_level))
{
level = ps_mem_q_ip->i4_level;
/* Spec requires level should be multiplied by 30
* API has values where level is multiplied by 10. This keeps it consistent with H264
* Because of the above differences, level is multiplied by 3 here.
*/
level *= 3;
}
else
{
level = MAX_LEVEL;
}
if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
> offsetof(ihevcd_cxa_fill_mem_rec_ip_t,
u4_num_reorder_frames))
{
num_reorder_frames = ps_mem_q_ip->u4_num_reorder_frames;
}
else
{
num_reorder_frames = MAX_REF_CNT;
}
if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
> offsetof(ihevcd_cxa_fill_mem_rec_ip_t, u4_num_ref_frames))
{
num_ref_frames = ps_mem_q_ip->u4_num_ref_frames;
}
else
{
num_ref_frames = MAX_REF_CNT;
}
if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
> offsetof(ihevcd_cxa_fill_mem_rec_ip_t,
u4_num_extra_disp_buf))
{
num_extra_disp_bufs = ps_mem_q_ip->u4_num_extra_disp_buf;
}
else
{
num_extra_disp_bufs = 0;
}
if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
> offsetof(ihevcd_cxa_fill_mem_rec_ip_t, u4_share_disp_buf))
{
#ifndef LOGO_EN
share_disp_buf = ps_mem_q_ip->u4_share_disp_buf;
#else
share_disp_buf = 0;
#endif
}
else
{
share_disp_buf = 0;
}
if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
> offsetof(ihevcd_cxa_fill_mem_rec_ip_t, e_output_format))
{
chroma_format = ps_mem_q_ip->e_output_format;
}
else
{
chroma_format = -1;
}
/* Shared disp buffer mode is supported only for 420SP formats */
if((chroma_format != IV_YUV_420P) &&
(chroma_format != IV_YUV_420SP_UV) &&
(chroma_format != IV_YUV_420SP_VU))
{
share_disp_buf = 0;
}
{
max_ht_luma = ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht;
max_wd_luma = ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd;
max_ht_luma = ALIGN64(max_ht_luma);
max_wd_luma = ALIGN64(max_wd_luma);
max_tile_cols = (max_wd_luma + MIN_TILE_WD - 1) / MIN_TILE_WD;
max_tile_rows = (max_ht_luma + MIN_TILE_HT - 1) / MIN_TILE_HT;
max_ctb_rows = max_ht_luma / MIN_CTB_SIZE;
max_ctb_cols = max_wd_luma / MIN_CTB_SIZE;
max_ctb_cnt = max_ctb_rows * max_ctb_cols;
max_num_cu_cols = max_wd_luma / MIN_CU_SIZE;
max_num_4x4_cols = max_wd_luma / 4;
}
/*
* If level is lesser than 31 and the resolution required is higher,
* then make the level at least 31.
*/
/* if (num_mbs > MAX_NUM_MBS_3_0 && level < MAX_LEVEL)
{
level = MAX_LEVEL;
}
*/
if((level < MIN_LEVEL) || (level > MAX_LEVEL))
{
ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
IHEVCD_LEVEL_UNSUPPORTED;
level = MAX_LEVEL;
}
if(num_ref_frames > MAX_REF_CNT)
{
ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
IHEVCD_NUM_REF_UNSUPPORTED;
num_ref_frames = MAX_REF_CNT;
}
if(num_reorder_frames > MAX_REF_CNT)
{
ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
IHEVCD_NUM_REORDER_UNSUPPORTED;
num_reorder_frames = MAX_REF_CNT;
}
max_dpb_size = ihevcd_get_dpb_size(level, max_wd_luma * max_ht_luma);
ps_mem_rec_base = ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
/* Set all memory reconds as persistent and alignment as 128
* by default
*/
ps_mem_rec = ps_mem_rec_base;
for(i = 0; i < MEM_REC_CNT; i++)
{
ps_mem_rec->u4_mem_alignment = 128;
ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
ps_mem_rec++;
}
/* Request memory for HEVCD object */
ps_mem_rec = &ps_mem_rec_base[MEM_REC_IV_OBJ];
ps_mem_rec->u4_mem_size = sizeof(iv_obj_t);
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_IV_OBJ,
ps_mem_rec->u4_mem_size);
/* Request memory for HEVC Codec context */
ps_mem_rec = &ps_mem_rec_base[MEM_REC_CODEC];
ps_mem_rec->u4_mem_size = sizeof(codec_t);
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CODEC,
ps_mem_rec->u4_mem_size);
/* Request memory for buffer which holds bitstream after emulation prevention */
ps_mem_rec = &ps_mem_rec_base[MEM_REC_BITSBUF];
ps_mem_rec->u4_mem_size = MAX((max_wd_luma * max_ht_luma), MIN_BITSBUF_SIZE);
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_BITSBUF,
ps_mem_rec->u4_mem_size);
/* Request memory for buffer which holds TU structures and coeff data for
* a set of CTBs in the current picture */
/*TODO Currently the buffer is allocated at a frame level. Reduce this to
* allocate for s set of CTBs and add appropriate synchronization logic to
* ensure that this is data is not overwritten before consumption
*/
ps_mem_rec = &ps_mem_rec_base[MEM_REC_TU_DATA];
ps_mem_rec->u4_mem_size = ihevcd_get_tu_data_size(max_wd_luma * max_ht_luma);
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_TU_DATA,
ps_mem_rec->u4_mem_size);
ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBANK];
ps_mem_rec->u4_mem_size = sizeof(buf_mgr_t);
/* Size for holding mv_buf_t for each MV Bank */
/* Note this allocation is done for BUF_MGR_MAX_CNT instead of
* max_dpb_size or MAX_DPB_SIZE for following reasons
* max_dpb_size will be based on max_wd and max_ht
* For higher max_wd and max_ht this number will be smaller than MAX_DPB_SIZE
* But during actual initialization number of buffers allocated can be more
*
* One extra MV Bank is needed to hold current pics MV bank.
* Since this is only a structure allocation and not actual buffer allocation,
* it is allocated for (MAX_DPB_SIZE + 1) entries
*/
ps_mem_rec->u4_mem_size += (MAX_DPB_SIZE + 1) * sizeof(mv_buf_t);
{
/* Allocate for pu_map, pu_t and pic_pu_idx for each MV bank */
/* Note: Number of luma samples is not max_wd * max_ht here, instead it is
* set to maximum number of luma samples allowed at the given level.
* This is done to ensure that any stream with width and height lesser
* than max_wd and max_ht is supported. Number of buffers required can be greater
* for lower width and heights at a given level and this increased number of buffers
* might require more memory than what max_wd and max_ht buffer would have required
* Also note one extra buffer is allocted to store current pictures MV bank
* In case of asynchronous parsing and processing, number of buffers should increase here
* based on when parsing and processing threads are synchronized
*/
WORD32 lvl_idx = ihevcd_get_lvl_idx(level);
WORD32 max_luma_samples = gai4_ihevc_max_luma_pic_size[lvl_idx];
ps_mem_rec->u4_mem_size += (max_dpb_size + 1) *
ihevcd_get_pic_mv_bank_size(max_luma_samples);
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MVBANK,
ps_mem_rec->u4_mem_size);
}
// TODO GPU : Have to creat ping-pong view for VPS,SPS,PPS.
ps_mem_rec = &ps_mem_rec_base[MEM_REC_VPS];
ps_mem_rec->u4_mem_size = MAX_VPS_CNT * sizeof(vps_t);
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_VPS,
ps_mem_rec->u4_mem_size);
ps_mem_rec = &ps_mem_rec_base[MEM_REC_SPS];
ps_mem_rec->u4_mem_size = MAX_SPS_CNT * sizeof(sps_t);
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SPS,
ps_mem_rec->u4_mem_size);
ps_mem_rec = &ps_mem_rec_base[MEM_REC_PPS];
ps_mem_rec->u4_mem_size = MAX_PPS_CNT * sizeof(pps_t);
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PPS,
ps_mem_rec->u4_mem_size);
ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_HDR];
ps_mem_rec->u4_mem_size = MAX_SLICE_HDR_CNT * sizeof(slice_header_t);
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SLICE_HDR,
ps_mem_rec->u4_mem_size);
ps_mem_rec = &ps_mem_rec_base[MEM_REC_TILE];
{
WORD32 tile_size;
tile_size = max_tile_cols * max_tile_rows;
tile_size *= sizeof(tile_t);
ps_mem_rec->u4_mem_size = MAX_PPS_CNT * tile_size;
}
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_TILE,
ps_mem_rec->u4_mem_size);
ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTRY_OFST];
{
WORD32 num_entry_points;
/* One entry point per tile */
num_entry_points = max_tile_cols * max_tile_rows;
/* One entry point per row of CTBs */
/*********************************************************************/
/* Only tiles or entropy sync is enabled at a time in main */
/* profile, but since memory required does not increase too much, */
/* this allocation is done to handle both cases */
/*********************************************************************/
num_entry_points += max_ctb_rows;
ps_mem_rec->u4_mem_size = sizeof(WORD32) * num_entry_points;
}
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ENTRY_OFST,
ps_mem_rec->u4_mem_size);
ps_mem_rec = &ps_mem_rec_base[MEM_REC_SCALING_MAT];
{
WORD32 scaling_mat_size;
SCALING_MAT_SIZE(scaling_mat_size)
ps_mem_rec->u4_mem_size = (MAX_SPS_CNT + MAX_PPS_CNT) * scaling_mat_size * sizeof(WORD16);
}
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SCALING_MAT,
ps_mem_rec->u4_mem_size);
/* Holds one row skip_flag at 8x8 level used during parsing */
ps_mem_rec = &ps_mem_rec_base[MEM_REC_PARSE_SKIP_FLAG];
/* 1 bit per 8x8 */
ps_mem_rec->u4_mem_size = max_num_cu_cols / 8;
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PARSE_SKIP_FLAG,
ps_mem_rec->u4_mem_size);
/* Holds one row skip_flag at 8x8 level used during parsing */
ps_mem_rec = &ps_mem_rec_base[MEM_REC_PARSE_CT_DEPTH];
/* 2 bits per 8x8 */
ps_mem_rec->u4_mem_size = max_num_cu_cols / 4;
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PARSE_CT_DEPTH,
ps_mem_rec->u4_mem_size);
/* Holds one row skip_flag at 8x8 level used during parsing */
ps_mem_rec = &ps_mem_rec_base[MEM_REC_PARSE_INTRA_PRED_MODE];
/* 8 bits per 4x4 */
/* 16 bytes each for top and left 64 pixels and 16 bytes for default mode */
ps_mem_rec->u4_mem_size = 3 * 16 * sizeof(UWORD8);
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PARSE_INTRA_PRED_MODE,
ps_mem_rec->u4_mem_size);
/* Holds one intra mode at 8x8 level for entire picture */
ps_mem_rec = &ps_mem_rec_base[MEM_REC_INTRA_FLAG];
/* 1 bit per 8x8 */
ps_mem_rec->u4_mem_size = (max_wd_luma / MIN_CU_SIZE) * (max_ht_luma / MIN_CU_SIZE) / 8;
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_INTRA_FLAG,
ps_mem_rec->u4_mem_size);
/* Holds one transquant bypass flag at 8x8 level for entire picture */
ps_mem_rec = &ps_mem_rec_base[MEM_REC_TRANSQUANT_BYPASS_FLAG];
/* 1 bit per 8x8 */
/* Extra row and column are allocated for easy processing of top and left blocks while loop filtering */
ps_mem_rec->u4_mem_size = ((max_wd_luma + 64) / MIN_CU_SIZE) * ((max_ht_luma + 64) / MIN_CU_SIZE) / 8;
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_TRANSQUANT_BYPASS_FLAG,
ps_mem_rec->u4_mem_size);
/* Request memory to hold thread handles for each processing thread */
ps_mem_rec = &ps_mem_rec_base[MEM_REC_THREAD_HANDLE];
ps_mem_rec->u4_mem_size = MAX_PROCESS_THREADS * ithread_get_handle_size();
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_THREAD_HANDLE,
ps_mem_rec->u4_mem_size);
{
WORD32 job_queue_size;
WORD32 num_jobs;
ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_JOBQ];
/* One job per row of CTBs */
num_jobs = max_ctb_rows;
/* One each tile a row of CTBs, num_jobs has to incremented */
num_jobs *= max_tile_cols;
/* One format convert/frame copy job per row of CTBs for non-shared mode*/
num_jobs += max_ctb_rows;
job_queue_size = ihevcd_jobq_ctxt_size();
job_queue_size += num_jobs * sizeof(proc_job_t);
ps_mem_rec->u4_mem_size = job_queue_size;
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_JOBQ,
ps_mem_rec->u4_mem_size);
}
ps_mem_rec = &ps_mem_rec_base[MEM_REC_PARSE_MAP];
ps_mem_rec->u4_mem_size = max_ctb_cnt;
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PARSE_MAP,
ps_mem_rec->u4_mem_size);
ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_MAP];
ps_mem_rec->u4_mem_size = max_ctb_cnt;
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_MAP,
ps_mem_rec->u4_mem_size);
ps_mem_rec = &ps_mem_rec_base[MEM_REC_DISP_MGR];
/* size for holding display manager context */
ps_mem_rec->u4_mem_size = sizeof(buf_mgr_t);
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_DISP_MGR,
ps_mem_rec->u4_mem_size);
ps_mem_rec = &ps_mem_rec_base[MEM_REC_DPB_MGR];
/* size for holding dpb manager context */
ps_mem_rec->u4_mem_size = sizeof(dpb_mgr_t);
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_DPB_MGR,
ps_mem_rec->u4_mem_size);
/** Holds top and left neighbor's pu idx into picture level pu array */
/* Only one top row is enough but left has to be replicated for each process context */
ps_mem_rec = &ps_mem_rec_base[MEM_REC_PIC_PU_IDX_NEIGHBOR];
ps_mem_rec->u4_mem_size = (max_num_4x4_cols /* left */ + MAX_PROCESS_THREADS * (MAX_CTB_SIZE / 4)/* top */ + 1/* top right */) * sizeof(WORD32);
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PIC_PU_IDX_NEIGHBOR,
ps_mem_rec->u4_mem_size);
/* TO hold scratch buffers needed for each process context */
ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_SCRATCH];
{
WORD32 size = 0;
WORD32 inter_pred_tmp_buf_size;
WORD32 ntaps_luma;
WORD32 pu_map_size;
WORD32 sao_size = 0;
ntaps_luma = 8;
/* Max inter pred size (number of bytes) */
inter_pred_tmp_buf_size = sizeof(WORD16) * (MAX_CTB_SIZE + ntaps_luma) * MAX_CTB_SIZE;
inter_pred_tmp_buf_size = ALIGN64(inter_pred_tmp_buf_size);
/* To hold pu_index w.r.t. frame level pu_t array for a CTB at 4x4 level*/
/* 16 x 16 4x4 in a CTB of size 64 x 64 and two extra needed for holding
* neighbors
*/
pu_map_size = sizeof(WORD32) * (18 * 18);
pu_map_size = ALIGN64(pu_map_size);
size += pu_map_size;
/* To hold inter pred temporary buffers */
size += 2 * inter_pred_tmp_buf_size;
/* Allocate for each process context */
size *= MAX_PROCESS_THREADS;
/* To hold SAO left buffer for luma */
sao_size += sizeof(UWORD8) * (MAX(max_ht_luma, max_wd_luma));
/* To hold SAO left buffer for chroma */
sao_size += sizeof(UWORD8) * (MAX(max_ht_luma, max_wd_luma));
/* To hold SAO top buffer for luma */
sao_size += sizeof(UWORD8) * max_wd_luma;
/* To hold SAO top buffer for chroma */
sao_size += sizeof(UWORD8) * max_wd_luma;
/* To hold SAO top left luma pixel value for last output ctb in a row*/
sao_size += sizeof(UWORD8) * max_ctb_rows;
/* To hold SAO top left chroma pixel value last output ctb in a row*/
sao_size += sizeof(UWORD8) * max_ctb_rows * 2;
/* To hold SAO top left pixel luma for current ctb - column array*/
sao_size += sizeof(UWORD8) * max_ctb_rows;
/* To hold SAO top left pixel chroma for current ctb-column array*/
sao_size += sizeof(UWORD8) * max_ctb_rows * 2;
/* To hold SAO top right pixel luma pixel value last output ctb in a row*/
sao_size += sizeof(UWORD8) * max_ctb_cols;
/* To hold SAO top right pixel chroma pixel value last output ctb in a row*/
sao_size += sizeof(UWORD8) * max_ctb_cols * 2;
/*To hold SAO botton bottom left pixels for luma*/
sao_size += sizeof(UWORD8) * max_ctb_rows;
/*To hold SAO botton bottom left pixels for luma*/
sao_size += sizeof(UWORD8) * max_ctb_rows * 2;
sao_size = ALIGN64(sao_size);
size += sao_size;
ps_mem_rec->u4_mem_size = size;
}
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_SCRATCH,
ps_mem_rec->u4_mem_size);
/* TO hold scratch buffers needed for each SAO context */
ps_mem_rec = &ps_mem_rec_base[MEM_REC_SAO_SCRATCH];
{
WORD32 size = 0;
size = 4 * MAX_CTB_SIZE * MAX_CTB_SIZE;
/* 2 temporary buffers*/
size *= 2;
size *= MAX_PROCESS_THREADS;
ps_mem_rec->u4_mem_size = size;
}
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SAO_SCRATCH,
ps_mem_rec->u4_mem_size);
ps_mem_rec = &ps_mem_rec_base[MEM_REC_BS_QP];
{
WORD32 size = 0;
WORD32 vert_bs_size, horz_bs_size;
WORD32 qp_const_flag_size;
WORD32 qp_size, num_8x8;
/* Max Number of vertical edges */
vert_bs_size = max_wd_luma / 8 + 2 * MAX_CTB_SIZE / 8;
/* Max Number of horizontal edges - extra MAX_CTB_SIZE / 8 to handle the last 4 rows separately(shifted CTB processing) */
vert_bs_size *= (max_ht_luma + MAX_CTB_SIZE) / MIN_TU_SIZE;
/* Number of bytes */
vert_bs_size /= 8;
/* Two bits per edge */
vert_bs_size *= 2;
/* Max Number of horizontal edges */
horz_bs_size = max_ht_luma / 8 + MAX_CTB_SIZE / 8;
/* Max Number of vertical edges - extra MAX_CTB_SIZE / 8 to handle the last 4 columns separately(shifted CTB processing) */
horz_bs_size *= (max_wd_luma + MAX_CTB_SIZE) / MIN_TU_SIZE;
/* Number of bytes */
horz_bs_size /= 8;
/* Two bits per edge */
horz_bs_size *= 2;
/* Max CTBs in a row */
qp_const_flag_size = max_wd_luma / MIN_CTB_SIZE + 1 /* The last ctb row deblk is done in last ctb + 1 row.*/;
/* Max CTBs in a column */
qp_const_flag_size *= max_ht_luma / MIN_CTB_SIZE;
/* Number of bytes */
qp_const_flag_size = (qp_const_flag_size + 7) >> 3;
/* QP changes at CU level - So store at 8x8 level */
num_8x8 = (max_ht_luma * max_wd_luma) / (MIN_CU_SIZE * MIN_CU_SIZE);
qp_size = num_8x8;
/* To hold vertical boundary strength */
size += vert_bs_size;
/* To hold horizontal boundary strength */
size += horz_bs_size;
/* To hold QP */
size += qp_size;
/* To hold QP const in CTB flags */
size += qp_const_flag_size;
ps_mem_rec->u4_mem_size = size;
}
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_BS_QP,
ps_mem_rec->u4_mem_size);
ps_mem_rec = &ps_mem_rec_base[MEM_REC_TILE_IDX];
{
WORD32 size = 0;
/* Max CTBs in a row */
size = max_wd_luma / MIN_CTB_SIZE + 2 /* Top row and bottom row extra. This ensures accessing left,top in first row
and right in last row will not result in invalid access*/;
/* Max CTBs in a column */
size *= max_ht_luma / MIN_CTB_SIZE;
size *= sizeof(UWORD16);
ps_mem_rec->u4_mem_size = size;
}
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_TILE_IDX,
ps_mem_rec->u4_mem_size);
ps_mem_rec = &ps_mem_rec_base[MEM_REC_SAO];
{
UWORD32 size;
/* 4 bytes per color component per CTB */
size = 3 * 4;
/* MAX number of CTBs in a row */
size *= max_wd_luma / MIN_CTB_SIZE;
/* MAX number of CTBs in a column */
size *= max_ht_luma / MIN_CTB_SIZE;
ps_mem_rec->u4_mem_size = size;
}
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SAO,
ps_mem_rec->u4_mem_size);
ps_mem_rec = &ps_mem_rec_base[MEM_REC_REF_PIC];
/* size for holding buffer manager context */
ps_mem_rec->u4_mem_size = sizeof(buf_mgr_t);
/* Size for holding pic_buf_t for each reference picture */
/* Note this allocation is done for BUF_MGR_MAX_CNT instead of
* max_dpb_size or MAX_DPB_SIZE for following reasons
* max_dpb_size will be based on max_wd and max_ht
* For higher max_wd and max_ht this number will be smaller than MAX_DPB_SIZE
* But during actual initialization number of buffers allocated can be more
*
* Also to handle display depth application can allocate more than what
* codec asks for in case of non-shared mode
* Since this is only a structure allocation and not actual buffer allocation,
* it is allocated for BUF_MGR_MAX_CNT entries
*/
ps_mem_rec->u4_mem_size += BUF_MGR_MAX_CNT * sizeof(pic_buf_t);
/* In case of non-shared mode allocate for reference picture buffers */
/* In case of shared and 420p output, allocate for chroma samples */
if((0 == share_disp_buf) || (chroma_format == IV_YUV_420P))
{
UWORD32 init_num_bufs;
UWORD32 init_extra_bufs;
WORD32 chroma_only;
chroma_only = 0;
init_extra_bufs = 0;
init_num_bufs = num_reorder_frames + num_ref_frames + 1;
/* In case of shared display buffers and chroma format 420P
* Allocate for chroma in reference buffers, luma buffer will be display buffer
*/
if((1 == share_disp_buf) && (chroma_format == IV_YUV_420P))
{
chroma_only = 1;
init_extra_bufs = num_extra_disp_bufs;
}
/* Note: Number of luma samples is not max_wd * max_ht here, instead it is
* set to maximum number of luma samples allowed at the given level.
* This is done to ensure that any stream with width and height lesser
* than max_wd and max_ht is supported. Number of buffers required can be greater
* for lower width and heights at a given level and this increased number of buffers
* might require more memory than what max_wd and max_ht buffer would have required
* Number of buffers is doubled in order to return one frame at a time instead of sending
* multiple outputs during dpb full case.
* Also note one extra buffer is allocted to store current picture
* In case of asynchronous parsing and processing, number of buffers should increase here
* based on when parsing and processing threads are synchronized
*/
ps_mem_rec->u4_mem_size +=
ihevcd_get_total_pic_buf_size(max_wd_luma * max_ht_luma, level, PAD_WD, PAD_HT,
init_num_bufs, init_extra_bufs, chroma_only);
}
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_REF_PIC,
ps_mem_rec->u4_mem_size);
/* Request memory to hold mem records to be returned during retrieve call */
ps_mem_rec = &ps_mem_rec_base[MEM_REC_BACKUP];
ps_mem_rec->u4_mem_size = MEM_REC_CNT * sizeof(iv_mem_rec_t);
DEBUG("\nMemory record Id %d = %d \n", MEM_REC_BACKUP,
ps_mem_rec->u4_mem_size);
/* Each memtab size is aligned to next multiple of 128 bytes */
/* This is to ensure all the memtabs start at different cache lines */
ps_mem_rec = ps_mem_rec_base;
for(i = 0; i < MEM_REC_CNT; i++)
{
ps_mem_rec->u4_mem_size = ALIGN128(ps_mem_rec->u4_mem_size);
ps_mem_rec++;
}
ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_num_mem_rec_filled = MEM_REC_CNT;
#ifdef APPLY_CONCEALMENT
{
IV_API_CALL_STATUS_T status;
icncl_fill_mem_rec_ip_t cncl_fill_ip;
icncl_fill_mem_rec_op_t cncl_fill_op;
UWORD8 mem_loc = MEM_REC_CNT;
cncl_fill_ip.s_ivd_fill_mem_rec_ip_t.e_cmd = IV_CMD_FILL_NUM_MEM_REC;
cncl_fill_ip.s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location = &(memTab[mem_loc]);
cncl_fill_ip.s_ivd_fill_mem_rec_ip_t.u4_size = ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size;
cncl_fill_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd = max_wd_luma;
cncl_fill_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht = max_ht_luma;
status = icncl_api_function(NULL, (void *)&cncl_fill_ip, (void *)&cncl_fill_op);
if(IV_SUCCESS == status)
{
icncl_num_mem_rec_ip_t cncl_mem_ip;
icncl_num_mem_rec_op_t cncl_mem_op;
cncl_mem_ip.s_ivd_num_rec_ip_t.e_cmd = IV_CMD_GET_NUM_MEM_REC;
cncl_mem_ip.s_ivd_num_rec_ip_t.u4_size = sizeof(icncl_num_mem_rec_ip_t);
status = icncl_api_function(NULL, (void *)&cncl_mem_ip, (void *)&cncl_mem_op);
if(IV_SUCCESS == status)
{
ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_num_mem_rec_filled += cncl_mem_op.s_ivd_num_mem_rec_op_t.u4_num_mem_rec;
}
}
return status;
}
#endif //APPLY_CONCEALMENT
DEBUG("Num mem recs in fill call : %d\n",
ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_num_mem_rec_filled);
return (status);
}
/**
*******************************************************************************
*
* @brief
* Initializes from mem records passed to the codec
*
* @par Description:
* Initializes pointers based on mem records passed
*
* @param[in] ps_codec_obj
* Pointer to codec object at API level
*
* @param[in] pv_api_ip
* Pointer to input argument structure
*
* @param[out] pv_api_op
* Pointer to output argument structure
*
* @returns Status
*
* @remarks
*
*
*******************************************************************************
*/
WORD32 ihevcd_init_mem_rec(iv_obj_t *ps_codec_obj,
void *pv_api_ip,
void *pv_api_op)
{
ihevcd_cxa_init_ip_t *dec_init_ip;
ihevcd_cxa_init_op_t *dec_init_op;
WORD32 i;
iv_mem_rec_t *ps_mem_rec, *ps_mem_rec_base;
WORD32 status = IV_SUCCESS;
codec_t *ps_codec;
WORD32 max_tile_cols, max_tile_rows;
dec_init_ip = (ihevcd_cxa_init_ip_t *)pv_api_ip;
dec_init_op = (ihevcd_cxa_init_op_t *)pv_api_op;
ps_mem_rec_base = dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location;
ps_mem_rec = &ps_mem_rec_base[MEM_REC_CODEC];
ps_codec_obj->pv_codec_handle = ps_mem_rec->pv_base;
ps_codec = (codec_t *)(ps_codec_obj->pv_codec_handle);
/* Note this memset can not be done in init() call, since init will called
during reset as well. And calling this during reset will mean all pointers
need to reinitialized*/
memset(ps_codec, 0, sizeof(codec_t));
if(dec_init_ip->s_ivd_init_ip_t.u4_size
> offsetof(ihevcd_cxa_init_ip_t, i4_level))
{
ps_codec->i4_init_level = dec_init_ip->i4_level;
ps_codec->i4_init_level *= 3;
}
else
{
ps_codec->i4_init_level = MAX_LEVEL;
}
if(dec_init_ip->s_ivd_init_ip_t.u4_size
> offsetof(ihevcd_cxa_init_ip_t, u4_num_ref_frames))
{
ps_codec->i4_init_num_ref = dec_init_ip->u4_num_ref_frames;
}
else
{
ps_codec->i4_init_num_ref = MAX_REF_CNT;
}
if(dec_init_ip->s_ivd_init_ip_t.u4_size
> offsetof(ihevcd_cxa_init_ip_t, u4_num_reorder_frames))
{
ps_codec->i4_init_num_reorder = dec_init_ip->u4_num_reorder_frames;
}
else
{
ps_codec->i4_init_num_reorder = MAX_REF_CNT;
}
if(dec_init_ip->s_ivd_init_ip_t.u4_size
> offsetof(ihevcd_cxa_init_ip_t, u4_num_extra_disp_buf))
{
ps_codec->i4_init_num_extra_disp_buf =
dec_init_ip->u4_num_extra_disp_buf;
}
else
{
ps_codec->i4_init_num_extra_disp_buf = 0;
}
if(dec_init_ip->s_ivd_init_ip_t.u4_size
> offsetof(ihevcd_cxa_init_ip_t, u4_share_disp_buf))
{
#ifndef LOGO_EN
ps_codec->i4_share_disp_buf = dec_init_ip->u4_share_disp_buf;
#else
ps_codec->i4_share_disp_buf = 0;
#endif
}
else
{
ps_codec->i4_share_disp_buf = 0;
}
/* Shared display mode is supported only for 420SP and 420P formats */
if((dec_init_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P) &&
(dec_init_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420SP_UV) &&
(dec_init_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420SP_VU))
{
ps_codec->i4_share_disp_buf = 0;
}
if((ps_codec->i4_init_level < MIN_LEVEL)
|| (ps_codec->i4_init_level > MAX_LEVEL))
{
dec_init_op->s_ivd_init_op_t.u4_error_code |= IHEVCD_LEVEL_UNSUPPORTED;
return (IV_FAIL);
}
if(ps_codec->i4_init_num_ref > MAX_REF_CNT)
{
dec_init_op->s_ivd_init_op_t.u4_error_code |=
IHEVCD_NUM_REF_UNSUPPORTED;
ps_codec->i4_init_num_ref = MAX_REF_CNT;
}
if(ps_codec->i4_init_num_reorder > MAX_REF_CNT)
{
dec_init_op->s_ivd_init_op_t.u4_error_code |=
IHEVCD_NUM_REORDER_UNSUPPORTED;
ps_codec->i4_init_num_reorder = MAX_REF_CNT;
}
if(ps_codec->i4_init_num_extra_disp_buf > MAX_REF_CNT)
{
dec_init_op->s_ivd_init_op_t.u4_error_code |=
IHEVCD_NUM_EXTRA_DISP_UNSUPPORTED;
ps_codec->i4_init_num_extra_disp_buf = 0;
}
ps_codec->e_chroma_fmt = dec_init_ip->s_ivd_init_ip_t.e_output_format;
ps_codec->i4_max_wd = dec_init_ip->s_ivd_init_ip_t.u4_frm_max_wd;
ps_codec->i4_max_ht = dec_init_ip->s_ivd_init_ip_t.u4_frm_max_ht;
ps_codec->i4_max_wd = ALIGN64(ps_codec->i4_max_wd);
ps_codec->i4_max_ht = ALIGN64(ps_codec->i4_max_ht);
ps_codec->i4_new_max_wd = ps_codec->i4_max_wd;
ps_codec->i4_new_max_ht = ps_codec->i4_max_ht;
max_tile_cols = (ps_codec->i4_max_wd + MIN_TILE_WD - 1) / MIN_TILE_WD;
max_tile_rows = (ps_codec->i4_max_ht + MIN_TILE_HT - 1) / MIN_TILE_HT;
ps_mem_rec = &ps_mem_rec_base[MEM_REC_BACKUP];
ps_codec->ps_mem_rec_backup = (iv_mem_rec_t *)ps_mem_rec->pv_base;
memcpy(ps_codec->ps_mem_rec_backup, ps_mem_rec_base,
MEM_REC_CNT * sizeof(iv_mem_rec_t));
ps_mem_rec = &ps_mem_rec_base[MEM_REC_BITSBUF];
ps_codec->pu1_bitsbuf = (UWORD8 *)ps_mem_rec->pv_base;
ps_codec->u4_bitsbuf_size = ps_mem_rec->u4_mem_size;
ps_mem_rec = &ps_mem_rec_base[MEM_REC_TU_DATA];
ps_codec->pv_tu_data = ps_mem_rec->pv_base;
ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBANK];
ps_codec->pv_mv_buf_mgr = ps_mem_rec->pv_base;
ps_codec->pv_mv_bank_buf_base = (UWORD8 *)ps_codec->pv_mv_buf_mgr + sizeof(buf_mgr_t);
ps_codec->i4_total_mv_bank_size = ps_mem_rec->u4_mem_size - sizeof(buf_mgr_t);
ps_mem_rec = &ps_mem_rec_base[MEM_REC_VPS];
ps_codec->ps_vps_base = (vps_t *)ps_mem_rec->pv_base;
ps_codec->s_parse.ps_vps_base = ps_codec->ps_vps_base;
ps_mem_rec = &ps_mem_rec_base[MEM_REC_SPS];
ps_codec->ps_sps_base = (sps_t *)ps_mem_rec->pv_base;
ps_codec->s_parse.ps_sps_base = ps_codec->ps_sps_base;
ps_mem_rec = &ps_mem_rec_base[MEM_REC_PPS];
ps_codec->ps_pps_base = (pps_t *)ps_mem_rec->pv_base;
ps_codec->s_parse.ps_pps_base = ps_codec->ps_pps_base;
ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_HDR];
ps_codec->ps_slice_hdr_base = (slice_header_t *)ps_mem_rec->pv_base;
ps_codec->s_parse.ps_slice_hdr_base = ps_codec->ps_slice_hdr_base;
ps_mem_rec = &ps_mem_rec_base[MEM_REC_TILE];
ps_codec->ps_tile = (tile_t *)ps_mem_rec->pv_base;
ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTRY_OFST];
ps_codec->pi4_entry_ofst = (WORD32 *)ps_mem_rec->pv_base;
ps_mem_rec = &ps_mem_rec_base[MEM_REC_SCALING_MAT];
ps_codec->pi2_scaling_mat = (WORD16 *)ps_mem_rec->pv_base;
ps_mem_rec = &ps_mem_rec_base[MEM_REC_PARSE_SKIP_FLAG];
ps_codec->s_parse.pu4_skip_cu_top = (UWORD32 *)ps_mem_rec->pv_base;
ps_mem_rec = &ps_mem_rec_base[MEM_REC_PARSE_CT_DEPTH];
ps_codec->s_parse.pu4_ct_depth_top = (UWORD32 *)ps_mem_rec->pv_base;
ps_mem_rec = &ps_mem_rec_base[MEM_REC_PARSE_INTRA_PRED_MODE];
ps_codec->s_parse.pu1_luma_intra_pred_mode_left =
(UWORD8 *)ps_mem_rec->pv_base;
ps_codec->s_parse.pu1_luma_intra_pred_mode_top =
(UWORD8 *)ps_mem_rec->pv_base + 16;
ps_mem_rec = &ps_mem_rec_base[MEM_REC_INTRA_FLAG];
memset(ps_mem_rec->pv_base, 0, (ps_codec->i4_max_wd / MIN_CU_SIZE) * (ps_codec->i4_max_ht / MIN_CU_SIZE) / 8);
ps_codec->pu1_pic_intra_flag = (UWORD8 *)ps_mem_rec->pv_base;
ps_codec->s_parse.pu1_pic_intra_flag = ps_codec->pu1_pic_intra_flag;
ps_mem_rec = &ps_mem_rec_base[MEM_REC_TRANSQUANT_BYPASS_FLAG];
{
WORD32 loop_filter_size = ((ps_codec->i4_max_wd + 64) / MIN_CU_SIZE) * ((ps_codec->i4_max_ht + 64) / MIN_CU_SIZE) / 8;
WORD32 loop_filter_strd = (ps_codec->i4_max_wd + 63) >> 6;
memset(ps_mem_rec->pv_base, 0, loop_filter_size);
/* The offset is added for easy processing of top and left blocks while loop filtering */
ps_codec->pu1_pic_no_loop_filter_flag = (UWORD8 *)ps_mem_rec->pv_base + loop_filter_strd + 1;
ps_codec->s_parse.pu1_pic_no_loop_filter_flag = ps_codec->pu1_pic_no_loop_filter_flag;
ps_codec->s_parse.s_deblk_ctxt.pu1_pic_no_loop_filter_flag = ps_codec->pu1_pic_no_loop_filter_flag;
ps_codec->s_parse.s_sao_ctxt.pu1_pic_no_loop_filter_flag = ps_codec->pu1_pic_no_loop_filter_flag;
}
/* Initialize pointers in PPS structures */
{
sps_t *ps_sps = ps_codec->ps_sps_base;
pps_t *ps_pps = ps_codec->ps_pps_base;
tile_t *ps_tile = ps_codec->ps_tile;
WORD16 *pi2_scaling_mat = ps_codec->pi2_scaling_mat;
WORD32 scaling_mat_size;
SCALING_MAT_SIZE(scaling_mat_size);
for(i = 0; i < MAX_SPS_CNT; i++)
{
ps_sps->pi2_scaling_mat = pi2_scaling_mat;
pi2_scaling_mat += scaling_mat_size;
ps_sps++;
}
for(i = 0; i < MAX_PPS_CNT; i++)
{
ps_pps->ps_tile = ps_tile;
ps_tile += (max_tile_cols * max_tile_rows);
ps_pps->pi2_scaling_mat = pi2_scaling_mat;
pi2_scaling_mat += scaling_mat_size;
ps_pps++;
}
}
ps_mem_rec = &ps_mem_rec_base[MEM_REC_THREAD_HANDLE];
for(i = 0; i < MAX_PROCESS_THREADS; i++)
{
WORD32 handle_size = ithread_get_handle_size();
ps_codec->apv_process_thread_handle[i] =
(UWORD8 *)ps_mem_rec->pv_base + (i * handle_size);
}
ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_JOBQ];
ps_codec->pv_proc_jobq_buf = ps_mem_rec->pv_base;
ps_codec->i4_proc_jobq_buf_size = ps_mem_rec->u4_mem_size;
ps_mem_rec = &ps_mem_rec_base[MEM_REC_PARSE_MAP];
ps_codec->pu1_parse_map = (UWORD8 *)ps_mem_rec->pv_base;
ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_MAP];
ps_codec->pu1_proc_map = (UWORD8 *)ps_mem_rec->pv_base;
ps_mem_rec = &ps_mem_rec_base[MEM_REC_DISP_MGR];
ps_codec->pv_disp_buf_mgr = ps_mem_rec->pv_base;
ps_mem_rec = &ps_mem_rec_base[MEM_REC_DPB_MGR];
ps_codec->pv_dpb_mgr = ps_mem_rec->pv_base;
ps_mem_rec = &ps_mem_rec_base[MEM_REC_PIC_PU_IDX_NEIGHBOR];
for(i = 0; i < MAX_PROCESS_THREADS; i++)
{
UWORD32 *pu4_buf = (UWORD32 *)ps_mem_rec->pv_base;
ps_codec->as_process[i].pu4_pic_pu_idx_left = pu4_buf + i * (MAX_CTB_SIZE / 4);
memset(ps_codec->as_process[i].pu4_pic_pu_idx_left, 0, sizeof(UWORD32) * MAX_CTB_SIZE / 4);
ps_codec->as_process[i].pu4_pic_pu_idx_top = pu4_buf + MAX_PROCESS_THREADS * (MAX_CTB_SIZE / 4);
}
memset(ps_codec->as_process[0].pu4_pic_pu_idx_top, 0, sizeof(UWORD32) * (ps_codec->i4_max_wd / 4 + 1));
ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_SCRATCH];
{
UWORD8 *pu1_buf = (UWORD8 *)ps_mem_rec->pv_base;
WORD32 pic_pu_idx_map_size;
WORD32 inter_pred_tmp_buf_size, ntaps_luma;
/* Max inter pred size */
ntaps_luma = 8;
inter_pred_tmp_buf_size = sizeof(WORD16) * (MAX_CTB_SIZE + ntaps_luma) * MAX_CTB_SIZE;
inter_pred_tmp_buf_size = ALIGN64(inter_pred_tmp_buf_size);
/* To hold pu_index w.r.t. frame level pu_t array for a CTB */