drm: add zcull info and zcull bind for nouveau

Add struct nv_device_zcull_info_v0, fermi_a_zcull_bind_v0, and their
corresponding method opcodes. These allow the graphics driver to query
parameters of the zcull area, and to bind a separate buffer for saving
the zcull data on a context switch as an optimization.

Bug 1580920

Change-Id: If0a60e310d83a8c25ecf11cadadeeff6b5ea1b5e
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
diff --git a/include/drm/nouveau_class.h b/include/drm/nouveau_class.h
index cbfeea0..3c3196b 100644
--- a/include/drm/nouveau_class.h
+++ b/include/drm/nouveau_class.h
@@ -153,6 +153,7 @@
 };
 
 #define NV_DEVICE_V0_INFO                                                  0x00
+#define NV_DEVICE_V0_ZCULL_INFO                                            0x01
 
 struct nv_device_info_v0 {
 	__u8  version;
@@ -179,6 +180,21 @@
 	__u64 ram_user;
 };
 
+struct nv_device_zcull_info_v0 {
+	__u8  version;
+	__u8  pad03[3];
+	__u32 image_size;
+	__u32 width_align_pixels;
+	__u32 height_align_pixels;
+	__u32 pixel_squares_by_aliquots;
+	__u32 aliquot_total;
+	__u32 region_byte_multiplier;
+	__u32 region_header_size;
+	__u32 subregion_header_size;
+	__u32 subregion_width_align_pixels;
+	__u32 subregion_height_align_pixels;
+	__u32 subregion_count;
+};
 
 /*******************************************************************************
  * context dma
@@ -551,6 +567,7 @@
 
 #define FERMI_A_ZBC_COLOR                                                  0x00
 #define FERMI_A_ZBC_DEPTH                                                  0x01
+#define FERMI_A_ZCULL_BIND                                                 0x02
 
 struct fermi_a_zbc_color_v0 {
 	__u8  version;
@@ -590,6 +607,16 @@
 	__u32 l2;
 };
 
+struct fermi_a_zcull_bind_v0 {
+	__u8  version;
+	__u8  pad03[3];
+#define FERMI_A_ZCULL_BIND_MODE_GLOBAL                                     0x00
+#define FERMI_A_ZCULL_BIND_MODE_NO_CTXSW                                   0x01
+#define FERMI_A_ZCULL_BIND_MODE_SEPARATE_BUFFER                            0x02
+	__u32 mode;
+	__u64 gpu_va;
+};
+
 #define KEPLER_SET_CHANNEL_PRIORITY                                        0x00
 #define KEPLER_SET_CHANNEL_TIMEOUT                                         0x01