| commit | c42e8a2bbceece75ec6a34b0da870582965748e0 | [log] [tgz] |
|---|---|---|
| author | JayYang <jay.yang@intel.com> | Fri Apr 29 15:34:37 2022 +0800 |
| committer | intel-mediadev <mediadev@intel.com> | Fri Apr 29 20:34:17 2022 +0800 |
| tree | 95516f10f6a6e35521823c655c5c859bbc1a94a3 | |
| parent | 5054a321d7f9ccf57778a4a80631f0d7ed5c77e7 [diff] |
[Media Common] [Media Copy] BLT copy 2 plane shift fix For BLT engie, base surface address should be 64 aligned, not 4096 aligned.