commit | f514bcdcb550b3c33edc4b497fb3422f7841a466 | [log] [tgz] |
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author | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | Thu Oct 18 17:56:42 2007 +0000 |
committer | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | Thu Oct 18 17:56:42 2007 +0000 |
tree | bb7b8be5e2fc7ac08411963e830c360a8a299355 | |
parent | 0b57b1f989009ebd6caa3ed80ae65ddf42000d3a [diff] |
Original v2 revision: 2876 Remove hardcoded wait from SPI write/erase routines and check the chip status register instead. This has been tested by Harald Gutmann <harald.gutmann@gmx.net> with a MX25L4005 chip. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://coreboot.org/flashrom/trunk@154 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1