spi25.c: Trivial resync with upstream
BUG=none
BRANCH=none
TEST=none
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Change-Id: If64a5c7b6a712f9fb8fc979ec27842a75c4be1c4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2500812
Tested-by: Edward O'Callaghan <quasisec@chromium.org>
Auto-Submit: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@chromium.org>
Commit-Queue: Edward O'Callaghan <quasisec@chromium.org>
diff --git a/spi25.c b/spi25.c
index 762ff25..1dad467 100644
--- a/spi25.c
+++ b/spi25.c
@@ -31,7 +31,6 @@
RDID,
RDID4,
REMS,
-// RES1, /* TODO */
RES2,
RES3,
NUM_ID_TYPES,
@@ -114,8 +113,8 @@
return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL);
}
-static void rdid_get_ids(unsigned char *readarr,
- int bytes, uint32_t *id1, uint32_t *id2)
+static void rdid_get_ids(unsigned char *readarr, int bytes,
+ uint32_t *id1, uint32_t *id2)
{
if (!oddparity(readarr[0]))
msg_cdbg("RDID byte 0 parity violation. ");
@@ -582,30 +581,21 @@
return spi_chip_erase_c7(flash);
}
-/* Erase 4 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes)
- JEDEC_SE_4BA (21h) instruction is new for 4-bytes addressing flash chips.
- The presence of this instruction for an exact chip should be checked
- by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */
+/* Erase 4 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) */
int spi_block_erase_21(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
{
/* This usually takes 15-800ms, so wait in 10ms steps. */
return spi_write_cmd(flash, 0x21, true, addr, NULL, 0, 10 * 1000);
}
-/* Erase 32 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes)
- JEDEC_BE_5C_4BA (5Ch) instruction is new for 4-bytes addressing flash chips.
- The presence of this instruction for an exact chip should be checked
- by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */
+/* Erase 32 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) */
int spi_block_erase_5c(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
{
/* This usually takes 100-4000ms, so wait in 100ms steps. */
return spi_write_cmd(flash, 0x5c, true, addr, NULL, 0, 100 * 1000);
}
-/* Erase 64 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes)
- JEDEC_BE_DC_4BA (DCh) instruction is new for 4-bytes addressing flash chips.
- The presence of this instruction for an exact chip should be checked
- by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */
+/* Erase 64 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) */
int spi_block_erase_dc(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
{
/* This usually takes 100-4000ms, so wait in 100ms steps. */
