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android / platform / external / flashrom / 66120f1e
commit66120f1e80eccc1435d7d44154392f1aa1deccf6[log] [tgz]
authoruwe <uwe@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1>Wed Mar 17 00:05:59 2010 +0000
committeruwe <uwe@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1>Wed Mar 17 00:05:59 2010 +0000
tree98fc079f1e089f730bacf89ae2b1ae17753c3332
parent667e908b48e59d13199b30ffdb5812619ba28119 [diff]
Mark a bunch of parallel chips I tested as TEST_OK_PRW.

All operations for these chips were tested on hardware. ERASE is not marked
as working yet, as there are multiple erase functions per chip and only one
was (successfully) tested. I'll redo the ERASE test when the respective
infrastructure in flashrom is there.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/flashrom/trunk@945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
1 file changed
tree: 98fc079f1e089f730bacf89ae2b1ae17753c3332
  1. 82802ab.c
  2. atahpt.c
  3. bitbang_spi.c
  4. board_enable.c
  5. buspirate_spi.c
  6. cbtable.c
  7. chipdrivers.h
  8. chipset_enable.c
  9. cli_classic.c
  10. cli_output.c
  11. COPYING
  12. coreboot_tables.h
  13. dediprog.c
  14. dmi.c
  15. drkaiser.c
  16. dummyflasher.c
  17. flash.h
  18. flashchips.c
  19. flashchips.h
  20. flashrom.8
  21. flashrom.c
  22. ft2232_spi.c
  23. gfxnvidia.c
  24. hwaccess.c
  25. hwaccess.h
  26. ichspi.c
  27. internal.c
  28. it87spi.c
  29. jedec.c
  30. layout.c
  31. m29f400bt.c
  32. Makefile
  33. nic3com.c
  34. pcidev.c
  35. physmap.c
  36. pm49fl00x.c
  37. print.c
  38. print_wiki.c
  39. programmer.c
  40. README
  41. satasii.c
  42. sb600spi.c
  43. serial.c
  44. serprog-protocol.txt
  45. serprog.c
  46. sharplhf00l04.c
  47. spi.c
  48. spi.h
  49. spi25.c
  50. sst28sf040.c
  51. sst49lfxxxc.c
  52. sst_fwhub.c
  53. stm50flw0x0x.c
  54. udelay.c
  55. w29ee011.c
  56. w39v040c.c
  57. w39v080fa.c
  58. wbsio_spi.c