UPSTREAM: flashchips: Enable FEATURE_4BA_EAR_1716 for ISSI chips
According to their datasheets, ISSI IS25LP256 and IS25WP256 support
both 0xc5/0xc8 and 0x17/0x16 opcodes to write / read their extended
address register. Flashrom will use 0xc5 by default if available,
so adding the FEATURE_4BA_EAR_1716 flag makes no difference for now
(FEATURE_4BA_EAR_C5C8 is included in the already selected FEATURE_4BA
set). It's better to have a comprehensive description of the chips,
though, in case somebody wants to use them in the future with a
master that restricts available opcodes.
BUG=none
BRANCH=none
TEST=none
(cherry picked from commit e8ce432faafc6794540a2e074af34e5d1fabf138)
Original-Change-Id: I03e4ff825c7742e7ff79b51b75293d53a091d4d4
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65264
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Thomas Heijligen <src@posteo.de>
GitOrigin-RevId: e8ce432faafc6794540a2e074af34e5d1fabf138
Change-Id: I2294bd8fa87089d6648fffc80a58d57049837fa1
Signed-off-by: CopyBot <copybot.service@gmail.com>
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/3720905
Reviewed-by: Sean Paul <sean@poorly.run>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Commit-Queue: Edward O'Callaghan <quasisec@chromium.org>
1 file changed
