soc/intel/cannonlake/fsp_params: Rename FSP_S_CONFIG variable
All newer Intel SoCs use `s_cfg` as the variable name for a FSP_S_CONFIG
struct pointer, so use that for CNL as well to avoid copy/paste errors
when applying changes across SoCs which touch the FSP_S_CONFIG struct.
Change-Id: I5eadb77f312ad6ad1072bc02adf98d97b1940236
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84653
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index a6c1390..db28d41 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -227,30 +227,30 @@
return PCH_SERIAL_IO_INDEX(config->SerialIoDevMode[dev_offset]);
}
-static void parse_devicetree(const config_t *config, FSP_S_CONFIG *params)
+static void parse_devicetree(const config_t *config, FSP_S_CONFIG *s_cfg)
{
#if CONFIG(SOC_INTEL_COMETLAKE)
uint32_t dev_offset = 0;
uint32_t i = 0;
for (i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++, dev_offset++) {
- params->SerialIoI2cMode[i] =
+ s_cfg->SerialIoI2cMode[i] =
get_param_value(config, dev_offset);
}
for (i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++,
dev_offset++) {
- params->SerialIoSpiMode[i] =
+ s_cfg->SerialIoSpiMode[i] =
get_param_value(config, dev_offset);
}
for (i = 0; i < SOC_INTEL_CML_UART_DEV_MAX; i++, dev_offset++) {
- params->SerialIoUartMode[i] =
+ s_cfg->SerialIoUartMode[i] =
get_param_value(config, dev_offset);
}
#else
for (int i = 0; i < ARRAY_SIZE(serial_io_dev); i++)
- params->SerialIoDevMode[i] = get_param_value(config, i);
+ s_cfg->SerialIoDevMode[i] = get_param_value(config, i);
#endif
}
@@ -331,17 +331,17 @@
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
int i;
- FSP_S_CONFIG *params = &supd->FspsConfig;
+ FSP_S_CONFIG *s_cfg = &supd->FspsConfig;
FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;
struct device *dev;
config_t *config = config_of_soc();
/* Parse device tree and enable/disable devices */
- parse_devicetree(config, params);
+ parse_devicetree(config, s_cfg);
/* Load VBT before devicetree-specific config. */
- params->GraphicsConfigPtr = (uintptr_t)vbt_get();
+ s_cfg->GraphicsConfigPtr = (uintptr_t)vbt_get();
mainboard_silicon_init_params(supd);
@@ -355,34 +355,34 @@
}
/* Unlock upper 8 bytes of RTC RAM */
- params->PchLockDownRtcMemoryLock = 0;
+ s_cfg->PchLockDownRtcMemoryLock = 0;
/* SATA */
- params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA);
- if (params->SataEnable) {
- params->SataMode = config->SataMode;
- params->SataPwrOptEnable = config->satapwroptimize;
- params->SataSalpSupport = config->SataSalpSupport;
- memcpy(params->SataPortsEnable, config->SataPortsEnable,
- sizeof(params->SataPortsEnable));
- memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
- sizeof(params->SataPortsDevSlp));
- memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug,
- sizeof(params->SataPortsHotPlug));
+ s_cfg->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA);
+ if (s_cfg->SataEnable) {
+ s_cfg->SataMode = config->SataMode;
+ s_cfg->SataPwrOptEnable = config->satapwroptimize;
+ s_cfg->SataSalpSupport = config->SataSalpSupport;
+ memcpy(s_cfg->SataPortsEnable, config->SataPortsEnable,
+ sizeof(s_cfg->SataPortsEnable));
+ memcpy(s_cfg->SataPortsDevSlp, config->SataPortsDevSlp,
+ sizeof(s_cfg->SataPortsDevSlp));
+ memcpy(s_cfg->SataPortsHotPlug, config->SataPortsHotPlug,
+ sizeof(s_cfg->SataPortsHotPlug));
#if CONFIG(SOC_INTEL_COMETLAKE)
- memcpy(params->SataPortsDevSlpResetConfig,
+ memcpy(s_cfg->SataPortsDevSlpResetConfig,
config->SataPortsDevSlpResetConfig,
- sizeof(params->SataPortsDevSlpResetConfig));
+ sizeof(s_cfg->SataPortsDevSlpResetConfig));
#endif
}
- params->SlpS0WithGbeSupport = 0;
- params->PchPmSlpS0VmRuntimeControl = config->PchPmSlpS0VmRuntimeControl;
- params->PchPmSlpS0Vm070VSupport = config->PchPmSlpS0Vm070VSupport;
- params->PchPmSlpS0Vm075VSupport = config->PchPmSlpS0Vm075VSupport;
+ s_cfg->SlpS0WithGbeSupport = 0;
+ s_cfg->PchPmSlpS0VmRuntimeControl = config->PchPmSlpS0VmRuntimeControl;
+ s_cfg->PchPmSlpS0Vm070VSupport = config->PchPmSlpS0Vm070VSupport;
+ s_cfg->PchPmSlpS0Vm075VSupport = config->PchPmSlpS0Vm075VSupport;
/* Lan */
- params->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE);
- if (params->PchLanEnable) {
+ s_cfg->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE);
+ if (s_cfg->PchLanEnable) {
if (config->s0ix_enable) {
/*
* The VmControl UPDs need to be set as per board
@@ -391,57 +391,57 @@
* But if GbE is enabled, voltage magining cannot be
* enabled, so the Vm control UPDs need to be set to 0.
*/
- params->SlpS0WithGbeSupport = 1;
- params->PchPmSlpS0VmRuntimeControl = 0;
- params->PchPmSlpS0Vm070VSupport = 0;
- params->PchPmSlpS0Vm075VSupport = 0;
+ s_cfg->SlpS0WithGbeSupport = 1;
+ s_cfg->PchPmSlpS0VmRuntimeControl = 0;
+ s_cfg->PchPmSlpS0Vm070VSupport = 0;
+ s_cfg->PchPmSlpS0Vm075VSupport = 0;
ignore_gbe_ltr();
}
}
/* Audio */
- params->PchHdaDspEnable = config->PchHdaDspEnable;
- params->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect;
- params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda;
- params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0;
- params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1;
- params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0;
- params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1;
- params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2;
- params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1;
- params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2;
- params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3;
- params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4;
+ s_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
+ s_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect;
+ s_cfg->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda;
+ s_cfg->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0;
+ s_cfg->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1;
+ s_cfg->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0;
+ s_cfg->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1;
+ s_cfg->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2;
+ s_cfg->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1;
+ s_cfg->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2;
+ s_cfg->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3;
+ s_cfg->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4;
/* eDP device */
- params->DdiPortEdp = config->DdiPortEdp;
+ s_cfg->DdiPortEdp = config->DdiPortEdp;
/* HPD of DDI ports */
- params->DdiPortBHpd = config->DdiPortBHpd;
- params->DdiPortCHpd = config->DdiPortCHpd;
- params->DdiPortDHpd = config->DdiPortDHpd;
- params->DdiPortFHpd = config->DdiPortFHpd;
+ s_cfg->DdiPortBHpd = config->DdiPortBHpd;
+ s_cfg->DdiPortCHpd = config->DdiPortCHpd;
+ s_cfg->DdiPortDHpd = config->DdiPortDHpd;
+ s_cfg->DdiPortFHpd = config->DdiPortFHpd;
/* DDC of DDI ports */
- params->DdiPortBDdc = config->DdiPortBDdc;
- params->DdiPortCDdc = config->DdiPortCDdc;
- params->DdiPortDDdc = config->DdiPortDDdc;
- params->DdiPortFDdc = config->DdiPortFDdc;
+ s_cfg->DdiPortBDdc = config->DdiPortBDdc;
+ s_cfg->DdiPortCDdc = config->DdiPortCDdc;
+ s_cfg->DdiPortDDdc = config->DdiPortDDdc;
+ s_cfg->DdiPortFDdc = config->DdiPortFDdc;
/* WOL */
- params->PchPmPcieWakeFromDeepSx = config->LanWakeFromDeepSx;
- params->PchPmWolEnableOverride = config->WolEnableOverride;
+ s_cfg->PchPmPcieWakeFromDeepSx = config->LanWakeFromDeepSx;
+ s_cfg->PchPmWolEnableOverride = config->WolEnableOverride;
/* S0ix */
- params->PchPmSlpS0Enable = config->s0ix_enable;
+ s_cfg->PchPmSlpS0Enable = config->s0ix_enable;
/* disable Legacy PME */
- memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
+ memset(s_cfg->PcieRpPmSci, 0, sizeof(s_cfg->PcieRpPmSci));
/* Legacy 8254 timer support */
bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
- params->Enable8254ClockGating = !use_8254;
- params->Enable8254ClockGatingOnS3 = !use_8254;
+ s_cfg->Enable8254ClockGating = !use_8254;
+ s_cfg->Enable8254ClockGatingOnS3 = !use_8254;
/*
* Legacy PM ACPI Timer (and TCO Timer)
@@ -450,88 +450,88 @@
* 2) disabling the PM ACPI Timer.
* We handle both by ourself!
*/
- params->EnableTcoTimer = 1;
+ s_cfg->EnableTcoTimer = 1;
/* USB */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
- params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
- params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias;
- params->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias;
- params->Usb2AfePredeemp[i] =
+ s_cfg->PortUsb20Enable[i] = config->usb2_ports[i].enable;
+ s_cfg->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias;
+ s_cfg->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias;
+ s_cfg->Usb2AfePredeemp[i] =
config->usb2_ports[i].tx_emp_enable;
- params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
+ s_cfg->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
if (config->usb2_ports[i].enable)
- params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
+ s_cfg->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
else
- params->Usb2OverCurrentPin[i] = 0xff;
+ s_cfg->Usb2OverCurrentPin[i] = 0xff;
}
if (config->PchUsb2PhySusPgDisable)
- params->PchUsb2PhySusPgEnable = 0;
+ s_cfg->PchUsb2PhySusPgEnable = 0;
for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
- params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
+ s_cfg->PortUsb30Enable[i] = config->usb3_ports[i].enable;
if (config->usb3_ports[i].enable) {
- params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
+ s_cfg->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
} else {
- params->Usb3OverCurrentPin[i] = 0xff;
+ s_cfg->Usb3OverCurrentPin[i] = 0xff;
}
if (config->usb3_ports[i].tx_de_emp) {
- params->Usb3HsioTxDeEmphEnable[i] = 1;
- params->Usb3HsioTxDeEmph[i] =
+ s_cfg->Usb3HsioTxDeEmphEnable[i] = 1;
+ s_cfg->Usb3HsioTxDeEmph[i] =
config->usb3_ports[i].tx_de_emp;
}
if (config->usb3_ports[i].tx_downscale_amp) {
- params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
- params->Usb3HsioTxDownscaleAmp[i] =
+ s_cfg->Usb3HsioTxDownscaleAmpEnable[i] = 1;
+ s_cfg->Usb3HsioTxDownscaleAmp[i] =
config->usb3_ports[i].tx_downscale_amp;
}
#if CONFIG(SOC_INTEL_COMETLAKE)
if (config->usb3_ports[i].gen2_tx_rate0_uniq_tran_enable) {
- params->Usb3HsioTxRate0UniqTranEnable[i] = 1;
- params->Usb3HsioTxRate0UniqTran[i] =
+ s_cfg->Usb3HsioTxRate0UniqTranEnable[i] = 1;
+ s_cfg->Usb3HsioTxRate0UniqTran[i] =
config->usb3_ports[i].gen2_tx_rate0_uniq_tran;
}
if (config->usb3_ports[i].gen2_tx_rate1_uniq_tran_enable) {
- params->Usb3HsioTxRate1UniqTranEnable[i] = 1;
- params->Usb3HsioTxRate1UniqTran[i] =
+ s_cfg->Usb3HsioTxRate1UniqTranEnable[i] = 1;
+ s_cfg->Usb3HsioTxRate1UniqTran[i] =
config->usb3_ports[i].gen2_tx_rate1_uniq_tran;
}
if (config->usb3_ports[i].gen2_tx_rate2_uniq_tran_enable) {
- params->Usb3HsioTxRate2UniqTranEnable[i] = 1;
- params->Usb3HsioTxRate2UniqTran[i] =
+ s_cfg->Usb3HsioTxRate2UniqTranEnable[i] = 1;
+ s_cfg->Usb3HsioTxRate2UniqTran[i] =
config->usb3_ports[i].gen2_tx_rate2_uniq_tran;
}
if (config->usb3_ports[i].gen2_tx_rate3_uniq_tran_enable) {
- params->Usb3HsioTxRate3UniqTranEnable[i] = 1;
- params->Usb3HsioTxRate3UniqTran[i] =
+ s_cfg->Usb3HsioTxRate3UniqTranEnable[i] = 1;
+ s_cfg->Usb3HsioTxRate3UniqTran[i] =
config->usb3_ports[i].gen2_tx_rate3_uniq_tran;
}
#endif
if (config->usb3_ports[i].gen2_rx_tuning_enable) {
- params->PchUsbHsioRxTuningEnable[i] =
+ s_cfg->PchUsbHsioRxTuningEnable[i] =
config->usb3_ports[i].gen2_rx_tuning_enable;
- params->PchUsbHsioRxTuningParameters[i] =
+ s_cfg->PchUsbHsioRxTuningParameters[i] =
config->usb3_ports[i].gen2_rx_tuning_params;
- params->PchUsbHsioFilterSel[i] =
+ s_cfg->PchUsbHsioFilterSel[i] =
config->usb3_ports[i].gen2_rx_filter_sel;
}
}
- params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG);
+ s_cfg->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG);
/* Set Debug serial port */
- params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
+ s_cfg->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
#if !CONFIG(SOC_INTEL_COMETLAKE)
- params->SerialIoEnableDebugUartAfterPost = CONFIG(INTEL_LPSS_UART_FOR_CONSOLE);
+ s_cfg->SerialIoEnableDebugUartAfterPost = CONFIG(INTEL_LPSS_UART_FOR_CONSOLE);
#endif
/* Enable CNVi Wifi if enabled in device tree */
#if CONFIG(SOC_INTEL_COMETLAKE)
- params->CnviMode = is_devfn_enabled(PCH_DEVFN_CNViWIFI);
+ s_cfg->CnviMode = is_devfn_enabled(PCH_DEVFN_CNViWIFI);
#else
- params->PchCnviMode = is_devfn_enabled(PCH_DEVFN_CNViWIFI);
+ s_cfg->PchCnviMode = is_devfn_enabled(PCH_DEVFN_CNViWIFI);
#endif
/* PCI Express */
for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
@@ -540,93 +540,93 @@
else if (config->PcieClkSrcUsage[i] == PCIE_CLK_RP0)
config->PcieClkSrcUsage[i] = 0;
}
- memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,
+ memcpy(s_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage,
sizeof(config->PcieClkSrcUsage));
- memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
+ memcpy(s_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
sizeof(config->PcieClkSrcClkReq));
- memcpy(params->PcieRpAdvancedErrorReporting,
+ memcpy(s_cfg->PcieRpAdvancedErrorReporting,
config->PcieRpAdvancedErrorReporting,
sizeof(config->PcieRpAdvancedErrorReporting));
- memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
+ memcpy(s_cfg->PcieRpLtrEnable, config->PcieRpLtrEnable,
sizeof(config->PcieRpLtrEnable));
- memcpy(params->PcieRpSlotImplemented, config->PcieRpSlotImplemented,
+ memcpy(s_cfg->PcieRpSlotImplemented, config->PcieRpSlotImplemented,
sizeof(config->PcieRpSlotImplemented));
- memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
+ memcpy(s_cfg->PcieRpHotPlug, config->PcieRpHotPlug,
sizeof(config->PcieRpHotPlug));
for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
- params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];
+ s_cfg->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];
if (config->PcieRpAspm[i])
- params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1;
+ s_cfg->PcieRpAspm[i] = config->PcieRpAspm[i] - 1;
};
/* eMMC and SD */
- params->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC);
- if (params->ScsEmmcEnabled) {
- params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
- params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed;
+ s_cfg->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC);
+ if (s_cfg->ScsEmmcEnabled) {
+ s_cfg->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
+ s_cfg->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed;
if (config->EmmcHs400DllNeed == 1) {
- params->PchScsEmmcHs400RxStrobeDll1 =
+ s_cfg->PchScsEmmcHs400RxStrobeDll1 =
config->EmmcHs400RxStrobeDll1;
- params->PchScsEmmcHs400TxDataDll =
+ s_cfg->PchScsEmmcHs400TxDataDll =
config->EmmcHs400TxDataDll;
}
}
- params->ScsSdCardEnabled = is_devfn_enabled(PCH_DEVFN_SDCARD);
- if (params->ScsSdCardEnabled) {
- params->SdCardPowerEnableActiveHigh = CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE);
+ s_cfg->ScsSdCardEnabled = is_devfn_enabled(PCH_DEVFN_SDCARD);
+ if (s_cfg->ScsSdCardEnabled) {
+ s_cfg->SdCardPowerEnableActiveHigh = CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE);
#if CONFIG(SOC_INTEL_COMETLAKE)
- params->ScsSdCardWpPinEnabled = config->ScsSdCardWpPinEnabled;
+ s_cfg->ScsSdCardWpPinEnabled = config->ScsSdCardWpPinEnabled;
#endif
}
- params->ScsUfsEnabled = is_devfn_enabled(PCH_DEVFN_UFS);
+ s_cfg->ScsUfsEnabled = is_devfn_enabled(PCH_DEVFN_UFS);
- params->Heci3Enabled = is_devfn_enabled(PCH_DEVFN_CSE_3);
+ s_cfg->Heci3Enabled = is_devfn_enabled(PCH_DEVFN_CSE_3);
/*
* coreboot will handle disabling of HECI1 device if `DISABLE_HECI1_AT_PRE_BOOT`
* config is selected hence, don't let FSP to disable the HECI1 device and set
* the `Heci1Disabled` UPD to `0`.
*/
- params->Heci1Disabled = 0;
- params->Device4Enable = config->Device4Enable;
+ s_cfg->Heci1Disabled = 0;
+ s_cfg->Device4Enable = config->Device4Enable;
/* Teton Glacier hybrid storage support */
- params->TetonGlacierMode = config->TetonGlacierMode;
+ s_cfg->TetonGlacierMode = config->TetonGlacierMode;
/* VrConfig Settings for 5 domains
* 0 = System Agent, 1 = IA Core, 2 = Ring,
* 3 = GT unsliced, 4 = GT sliced */
for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
- fill_vr_domain_config(params, i, &config->domain_vr_config[i]);
+ fill_vr_domain_config(s_cfg, i, &config->domain_vr_config[i]);
/* Acoustic Noise Mitigation */
- params->AcousticNoiseMitigation = config->AcousticNoiseMitigation;
- params->SlowSlewRateForIa = config->SlowSlewRateForIa;
- params->SlowSlewRateForGt = config->SlowSlewRateForGt;
- params->SlowSlewRateForSa = config->SlowSlewRateForSa;
- params->SlowSlewRateForFivr = config->SlowSlewRateForFivr;
- params->FastPkgCRampDisableIa = config->FastPkgCRampDisableIa;
- params->FastPkgCRampDisableGt = config->FastPkgCRampDisableGt;
- params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa;
- params->FastPkgCRampDisableFivr = config->FastPkgCRampDisableFivr;
+ s_cfg->AcousticNoiseMitigation = config->AcousticNoiseMitigation;
+ s_cfg->SlowSlewRateForIa = config->SlowSlewRateForIa;
+ s_cfg->SlowSlewRateForGt = config->SlowSlewRateForGt;
+ s_cfg->SlowSlewRateForSa = config->SlowSlewRateForSa;
+ s_cfg->SlowSlewRateForFivr = config->SlowSlewRateForFivr;
+ s_cfg->FastPkgCRampDisableIa = config->FastPkgCRampDisableIa;
+ s_cfg->FastPkgCRampDisableGt = config->FastPkgCRampDisableGt;
+ s_cfg->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa;
+ s_cfg->FastPkgCRampDisableFivr = config->FastPkgCRampDisableFivr;
/* Apply minimum assertion width settings if non-zero */
if (config->PchPmSlpS3MinAssert)
- params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert;
+ s_cfg->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert;
if (config->PchPmSlpS4MinAssert)
- params->PchPmSlpS4MinAssert = config->PchPmSlpS4MinAssert;
+ s_cfg->PchPmSlpS4MinAssert = config->PchPmSlpS4MinAssert;
if (config->PchPmSlpSusMinAssert)
- params->PchPmSlpSusMinAssert = config->PchPmSlpSusMinAssert;
+ s_cfg->PchPmSlpSusMinAssert = config->PchPmSlpSusMinAssert;
if (config->PchPmSlpAMinAssert)
- params->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert;
+ s_cfg->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert;
#if CONFIG(SOC_INTEL_COMETLAKE)
if (config->PchPmPwrCycDur)
- params->PchPmPwrCycDur = get_pm_pwr_cyc_dur(config->PchPmSlpS4MinAssert,
+ s_cfg->PchPmPwrCycDur = get_pm_pwr_cyc_dur(config->PchPmSlpS4MinAssert,
config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert,
config->PchPmPwrCycDur);
#endif
@@ -639,8 +639,8 @@
tconfig->PchUnlockGpioPads = config->PchUnlockGpioPads;
/* Set correct Sirq mode based on config */
- params->PchSirqEnable = config->serirq_mode != SERIRQ_OFF;
- params->PchSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS;
+ s_cfg->PchSirqEnable = config->serirq_mode != SERIRQ_OFF;
+ s_cfg->PchSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS;
/*
* GSPI Chip Select parameters
@@ -648,27 +648,27 @@
* therefore only CS0 is configured below.
*/
#if CONFIG(SOC_INTEL_COMETLAKE)
- configure_gspi_cs(0, config, ¶ms->SerialIoSpi0CsPolarity[0],
- ¶ms->SerialIoSpi0CsEnable[0],
- ¶ms->SerialIoSpiDefaultCsOutput[0]);
- configure_gspi_cs(1, config, ¶ms->SerialIoSpi1CsPolarity[0],
- ¶ms->SerialIoSpi1CsEnable[0],
- ¶ms->SerialIoSpiDefaultCsOutput[1]);
- configure_gspi_cs(2, config, ¶ms->SerialIoSpi2CsPolarity[0],
- ¶ms->SerialIoSpi2CsEnable[0],
- ¶ms->SerialIoSpiDefaultCsOutput[2]);
+ configure_gspi_cs(0, config, &s_cfg->SerialIoSpi0CsPolarity[0],
+ &s_cfg->SerialIoSpi0CsEnable[0],
+ &s_cfg->SerialIoSpiDefaultCsOutput[0]);
+ configure_gspi_cs(1, config, &s_cfg->SerialIoSpi1CsPolarity[0],
+ &s_cfg->SerialIoSpi1CsEnable[0],
+ &s_cfg->SerialIoSpiDefaultCsOutput[1]);
+ configure_gspi_cs(2, config, &s_cfg->SerialIoSpi2CsPolarity[0],
+ &s_cfg->SerialIoSpi2CsEnable[0],
+ &s_cfg->SerialIoSpiDefaultCsOutput[2]);
#else
for (i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++)
configure_gspi_cs(i, config,
- ¶ms->SerialIoSpiCsPolarity[0], NULL, NULL);
+ &s_cfg->SerialIoSpiCsPolarity[0], NULL, NULL);
#endif
/* Chipset Lockdown */
const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP;
tconfig->PchLockDownGlobalSmi = lockdown_by_fsp;
tconfig->PchLockDownBiosInterface = lockdown_by_fsp;
- params->PchLockDownBiosLock = lockdown_by_fsp;
- params->PchLockDownRtcMemoryLock = lockdown_by_fsp;
+ s_cfg->PchLockDownBiosLock = lockdown_by_fsp;
+ s_cfg->PchLockDownRtcMemoryLock = lockdown_by_fsp;
tconfig->SkipPamLock = !lockdown_by_fsp;
#if CONFIG(SOC_INTEL_COMETLAKE)
/*
@@ -677,16 +677,16 @@
* So, it becomes coreboot's responsibility to set this bit
* before end of POST for security concerns.
*/
- params->SpiFlashCfgLockDown = lockdown_by_fsp;
+ s_cfg->SpiFlashCfgLockDown = lockdown_by_fsp;
#endif
#if !CONFIG(SOC_INTEL_COMETLAKE)
- params->VrPowerDeliveryDesign = config->VrPowerDeliveryDesign;
+ s_cfg->VrPowerDeliveryDesign = config->VrPowerDeliveryDesign;
#endif
- params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
+ s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
- params->PavpEnable = CONFIG(PAVP);
+ s_cfg->PavpEnable = CONFIG(PAVP);
/*
* Prevent FSP from programming write-once subsystem IDs by providing
@@ -732,8 +732,8 @@
}
}
- params->SiSsidTablePtr = (uintptr_t)ssid_table;
- params->SiNumberOfSsidTableEntry = ARRAY_SIZE(ssid_table);
+ s_cfg->SiSsidTablePtr = (uintptr_t)ssid_table;
+ s_cfg->SiNumberOfSsidTableEntry = ARRAY_SIZE(ssid_table);
/* Assign PCI IRQs */
if (!assign_pci_irqs(irq_constraints, ARRAY_SIZE(irq_constraints)))
@@ -741,8 +741,8 @@
size_t pch_count = 0;
const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count);
- params->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs);
- params->NumOfDevIntConfig = pch_count;
+ s_cfg->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs);
+ s_cfg->NumOfDevIntConfig = pch_count;
printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n");
}
