)]}'
{
  "commit": "8b55ee05dc957bfb5b2a1122c9093059cb9115b3",
  "tree": "7ce19ea4070e9137d0664b78631ff24d664b1c4d",
  "parents": [
    "57f7e2182ec62a92dfcd6f154b47c8760e784d27"
  ],
  "author": {
    "name": "Pranava Y N",
    "email": "pranavayn@google.com",
    "time": "Tue Apr 01 16:24:27 2025 +0530"
  },
  "committer": {
    "name": "Subrata Banik",
    "email": "subratabanik@google.com",
    "time": "Thu Apr 03 11:21:39 2025 +0000"
  },
  "message": "mb/google/brya/var/anahera: Enable RTD3 for SSD to resolve S0ix issue\n\nSome SSDs block the CPU from reaching C10 during the S0ix suspend\nwithout the RTD3 configuration. Add PCIe RTD3 support so NVMe gets\nplaced into D3 state when entering S0ix.\n\nEnable and reset GPIOs are configured as per pin mapping in gpio.c.\n\nBUG\u003db:391612392\nTEST\u003dRun suspend_stress_test on anahera device and verify that the\ndevice suspends to S0ix.\n\nChange-Id: I43a1277efabf8b1ca265e9aca65878da60275b38\nSigned-off-by: Pranava Y N \u003cpranavayn@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/coreboot/+/87057\nReviewed-by: Eric Lai \u003cericllai@google.com\u003e\nReviewed-by: Kapil Porwal \u003ckapilporwal@google.com\u003e\nReviewed-by: Subrata Banik \u003csubratabanik@google.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Jayvik Desai \u003cjayvik@google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "2670e11a8ecf992132576ac6742f199a99236364",
      "old_mode": 33188,
      "old_path": "src/mainboard/google/brya/variants/anahera/overridetree.cb",
      "new_id": "12566087db54498027cba13b81be98da6c0718bf",
      "new_mode": 33188,
      "new_path": "src/mainboard/google/brya/variants/anahera/overridetree.cb"
    }
  ]
}