mb/google/brya: Enable RTD3 for SSD to resolve S0ix issue
Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.
Enable and reset GPIOs are configured as per pin mapping in gpio.c.
BUG=b:391612392
TEST=Run suspend_stress_test on brya device and verify that the device
suspends to S0ix.
Change-Id: Ifc85b85ef57216dc394f9a2e1b25bb7154da658f
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86685
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
index 6160ebf..3a748ea 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
@@ -192,6 +192,13 @@
.clk_req = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
+ chip soc/intel/common/block/pcie/rtd3
+ register "is_storage" = "true"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+ register "srcclk_pin" = "1"
+ device generic 0 on end
+ end
end #PCIE9-12 SSD
device ref uart0 on end
device ref gspi1 on end
