Support MIPS DSP Rev1 intrinsics. 
This patch was reviewed in the llvm-commits list by Jim Grosbach.


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@159366 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/include/clang/Basic/BuiltinsMips.def b/include/clang/Basic/BuiltinsMips.def
new file mode 100644
index 0000000..0ae141c
--- /dev/null
+++ b/include/clang/Basic/BuiltinsMips.def
@@ -0,0 +1,125 @@
+//===-- BuiltinsMips.def - Mips Builtin function database --------*- C++ -*-==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the MIPS-specific builtin function database. Users of
+// this file must define the BUILTIN macro to make use of this information.
+//
+//===----------------------------------------------------------------------===//
+
+// The format of this database matches clang/Basic/Builtins.def.
+
+// Add/subtract with optional saturation
+BUILTIN(__builtin_mips_addu_qb, "V4ScV4ScV4Sc", "nc")
+BUILTIN(__builtin_mips_addu_s_qb, "V4ScV4ScV4Sc", "nc")
+BUILTIN(__builtin_mips_subu_qb, "V4ScV4ScV4Sc", "nc")
+BUILTIN(__builtin_mips_subu_s_qb, "V4ScV4ScV4Sc", "nc")
+
+BUILTIN(__builtin_mips_addq_ph, "V2sV2sV2s", "nc")
+BUILTIN(__builtin_mips_addq_s_ph, "V2sV2sV2s", "nc")
+BUILTIN(__builtin_mips_subq_ph, "V2sV2sV2s", "nc")
+BUILTIN(__builtin_mips_subq_s_ph, "V2sV2sV2s", "nc")
+
+BUILTIN(__builtin_mips_madd, "LLiLLiii", "nc")
+BUILTIN(__builtin_mips_maddu, "LLiLLiUiUi", "nc")
+BUILTIN(__builtin_mips_msub, "LLiLLiii", "nc")
+BUILTIN(__builtin_mips_msubu, "LLiLLiUiUi", "nc")
+
+BUILTIN(__builtin_mips_addq_s_w, "iii", "nc")
+BUILTIN(__builtin_mips_subq_s_w, "iii", "nc")
+
+BUILTIN(__builtin_mips_addsc, "iii", "nc")
+BUILTIN(__builtin_mips_addwc, "iii", "nc")
+
+BUILTIN(__builtin_mips_modsub, "iii", "nc")
+
+BUILTIN(__builtin_mips_raddu_w_qb, "iV4Sc", "nc")
+
+BUILTIN(__builtin_mips_absq_s_ph, "V2sV2s", "nc")
+BUILTIN(__builtin_mips_absq_s_w, "ii", "nc")
+
+BUILTIN(__builtin_mips_precrq_qb_ph, "V4ScV2sV2s", "nc")
+BUILTIN(__builtin_mips_precrqu_s_qb_ph, "V4ScV2sV2s", "nc")
+BUILTIN(__builtin_mips_precrq_ph_w, "V2sii", "nc")
+BUILTIN(__builtin_mips_precrq_rs_ph_w, "V2sii", "nc")
+BUILTIN(__builtin_mips_preceq_w_phl, "iV2s", "nc")
+BUILTIN(__builtin_mips_preceq_w_phr, "iV2s", "nc")
+BUILTIN(__builtin_mips_precequ_ph_qbl, "V2sV4Sc", "nc")
+BUILTIN(__builtin_mips_precequ_ph_qbr, "V2sV4Sc", "nc")
+BUILTIN(__builtin_mips_precequ_ph_qbla, "V2sV4Sc", "nc")
+BUILTIN(__builtin_mips_precequ_ph_qbra, "V2sV4Sc", "nc")
+BUILTIN(__builtin_mips_preceu_ph_qbl, "V2sV4Sc", "nc")
+BUILTIN(__builtin_mips_preceu_ph_qbr, "V2sV4Sc", "nc")
+BUILTIN(__builtin_mips_preceu_ph_qbla, "V2sV4Sc", "nc")
+BUILTIN(__builtin_mips_preceu_ph_qbra, "V2sV4Sc", "nc")
+
+BUILTIN(__builtin_mips_shll_qb, "V4ScV4Sci", "nc")
+BUILTIN(__builtin_mips_shrl_qb, "V4ScV4Sci", "nc")
+BUILTIN(__builtin_mips_shll_ph, "V2sV2si", "nc")
+BUILTIN(__builtin_mips_shll_s_ph, "V2sV2si", "nc")
+BUILTIN(__builtin_mips_shra_ph, "V2sV2si", "nc")
+BUILTIN(__builtin_mips_shra_r_ph, "V2sV2si", "nc")
+BUILTIN(__builtin_mips_shll_s_w, "iii", "nc")
+BUILTIN(__builtin_mips_shra_r_w, "iii", "nc")
+BUILTIN(__builtin_mips_shilo, "iLLii", "nc")
+
+BUILTIN(__builtin_mips_muleu_s_ph_qbl, "V2sV4ScV2s", "nc")
+BUILTIN(__builtin_mips_muleu_s_ph_qbr, "V2sV4ScV2s", "nc")
+BUILTIN(__builtin_mips_mulq_rs_ph, "V2sV2sV2s", "nc")
+BUILTIN(__builtin_mips_muleq_s_w_phl, "iV2sV2s", "nc")
+BUILTIN(__builtin_mips_muleq_s_w_phr, "iV2sV2s", "nc")
+BUILTIN(__builtin_mips_mulsaq_s_w_ph, "LLiLLiV2sV2s", "nc")
+BUILTIN(__builtin_mips_maq_s_w_phl, "LLiLLiV2sV2s", "nc")
+BUILTIN(__builtin_mips_maq_s_w_phr, "LLiLLiV2sV2s", "nc")
+BUILTIN(__builtin_mips_maq_sa_w_phl, "LLiLLiV2sV2s", "nc")
+BUILTIN(__builtin_mips_maq_sa_w_phr, "LLiLLiV2sV2s", "nc")
+BUILTIN(__builtin_mips_mult, "LLiii", "nc")
+BUILTIN(__builtin_mips_multu, "LLiUiUi", "nc")
+
+BUILTIN(__builtin_mips_dpau_h_qbl, "LLiLLiV4ScV4Sc", "nc")
+BUILTIN(__builtin_mips_dpau_h_qbr, "LLiLLiV4ScV4Sc", "nc")
+BUILTIN(__builtin_mips_dpsu_h_qbl, "LLiLLiV4ScV4Sc", "nc")
+BUILTIN(__builtin_mips_dpsu_h_qbr, "LLiLLiV4ScV4Sc", "nc")
+BUILTIN(__builtin_mips_dpaq_s_w_ph, "LLiLLiV2sV2s", "nc")
+BUILTIN(__builtin_mips_dpsq_s_w_ph, "LLiLLiV2sV2s", "nc")
+BUILTIN(__builtin_mips_dpaq_sa_l_w, "LLiLLiii", "nc")
+BUILTIN(__builtin_mips_dpsq_sa_l_w, "LLiLLiii", "nc")
+
+BUILTIN(__builtin_mips_cmpu_eq_qb, "vV4ScV4Sc", "nc")
+BUILTIN(__builtin_mips_cmpu_lt_qb, "vV4ScV4Sc", "nc")
+BUILTIN(__builtin_mips_cmpu_le_qb, "vV4ScV4Sc", "nc")
+BUILTIN(__builtin_mips_cmpgu_eq_qb, "iV4ScV4Sc", "nc")
+BUILTIN(__builtin_mips_cmpgu_lt_qb, "iV4ScV4Sc", "nc")
+BUILTIN(__builtin_mips_cmpgu_le_qb, "iV4ScV4Sc", "nc")
+BUILTIN(__builtin_mips_cmp_eq_ph, "vV2sV2s", "nc")
+BUILTIN(__builtin_mips_cmp_lt_ph, "vV2sV2s", "nc")
+BUILTIN(__builtin_mips_cmp_le_ph, "vV2sV2s", "nc")
+
+BUILTIN(__builtin_mips_extr_s_h, "iLLii", "nc")
+BUILTIN(__builtin_mips_extr_w, "iLLii", "nc")
+BUILTIN(__builtin_mips_extr_rs_w, "iLLii", "nc")
+BUILTIN(__builtin_mips_extr_r_w, "iLLii", "nc")
+BUILTIN(__builtin_mips_extp, "iLLii", "nc")
+BUILTIN(__builtin_mips_extpdp, "iLLii", "nc")
+
+BUILTIN(__builtin_mips_wrdsp, "vii", "nc")
+BUILTIN(__builtin_mips_rddsp, "ii", "nc")
+BUILTIN(__builtin_mips_insv, "iii", "nc")
+BUILTIN(__builtin_mips_bitrev, "ii", "nc")
+BUILTIN(__builtin_mips_packrl_ph, "V2sV2sV2s", "nc")
+BUILTIN(__builtin_mips_repl_qb, "V4Sci", "nc")
+BUILTIN(__builtin_mips_repl_ph, "V2si", "nc")
+BUILTIN(__builtin_mips_pick_qb, "V4ScV4ScV4Sc", "nc")
+BUILTIN(__builtin_mips_pick_ph, "V2sV2sV2s", "nc")
+BUILTIN(__builtin_mips_mthlip, "LLiLLii", "nc")
+BUILTIN(__builtin_mips_bposge32, "i", "nc")
+BUILTIN(__builtin_mips_lbux, "iv*i", "n")
+BUILTIN(__builtin_mips_lhx, "iv*i", "n")
+BUILTIN(__builtin_mips_lwx, "iv*i", "n")
+
+#undef BUILTIN
diff --git a/include/clang/Basic/TargetBuiltins.h b/include/clang/Basic/TargetBuiltins.h
index e9b9f85..9746dfe 100644
--- a/include/clang/Basic/TargetBuiltins.h
+++ b/include/clang/Basic/TargetBuiltins.h
@@ -105,6 +105,16 @@
         LastTSBuiltin
     };
   }
+
+  /// Mips builtins
+  namespace Mips {
+    enum {
+        LastTIBuiltin = clang::Builtin::FirstTSBuiltin-1,
+#define BUILTIN(ID, TYPE, ATTRS) BI##ID,
+#include "clang/Basic/BuiltinsMips.def"
+        LastTSBuiltin
+    };
+  }
 } // end namespace clang.
 
 #endif
diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index 0365148..a633a2c 100644
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -3557,6 +3557,7 @@
 
 namespace {
 class MipsTargetInfoBase : public TargetInfo {
+  static const Builtin::Info BuiltinInfo[];
   std::string CPU;
   bool SoftFloat;
   bool SingleFloat;
@@ -3606,7 +3607,8 @@
                                 MacroBuilder &Builder) const = 0;
   virtual void getTargetBuiltins(const Builtin::Info *&Records,
                                  unsigned &NumRecords) const {
-    // FIXME: Implement!
+    Records = BuiltinInfo;
+    NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
   }
   virtual bool hasFeature(StringRef Feature) const {
     return Feature == "mips";
@@ -3695,6 +3697,13 @@
   }
 };
 
+const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
+#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
+#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
+                                              ALL_LANGUAGES },
+#include "clang/Basic/BuiltinsMips.def"
+};
+
 class Mips32TargetInfoBase : public MipsTargetInfoBase {
 public:
   Mips32TargetInfoBase(const std::string& triple) :
diff --git a/lib/CodeGen/CGBuiltin.cpp b/lib/CodeGen/CGBuiltin.cpp
index a3d4af7..cf5387a 100644
--- a/lib/CodeGen/CGBuiltin.cpp
+++ b/lib/CodeGen/CGBuiltin.cpp
@@ -1380,6 +1380,11 @@
     return EmitPPCBuiltinExpr(BuiltinID, E);
   case llvm::Triple::hexagon:
     return EmitHexagonBuiltinExpr(BuiltinID, E);
+  case llvm::Triple::mips:
+  case llvm::Triple::mipsel:
+  case llvm::Triple::mips64:
+  case llvm::Triple::mips64el:
+    return EmitMipsBuiltinExpr(BuiltinID, E);
   default:
     return 0;
   }
@@ -5123,3 +5128,296 @@
   }
   }
 }
+
+Value *CodeGenFunction::EmitMipsBuiltinExpr(unsigned BuiltinID,
+                                            const CallExpr *E) {
+  llvm::SmallVector<Value*, 4> Ops;
+
+  for (unsigned i = 0, e = E->getNumArgs(); i != e; i++)
+    Ops.push_back(EmitScalarExpr(E->getArg(i)));
+
+  Intrinsic::ID ID = Intrinsic::not_intrinsic;
+
+  switch (BuiltinID) {
+  default: return 0;
+  case Mips::BI__builtin_mips_addu_qb:
+    ID = Intrinsic::mips_addu_qb;
+    break;
+  case Mips::BI__builtin_mips_addu_s_qb:
+    ID = Intrinsic::mips_addu_s_qb;
+    break;
+  case Mips::BI__builtin_mips_subu_qb:
+    ID = Intrinsic::mips_subu_qb;
+    break;
+  case Mips::BI__builtin_mips_subu_s_qb:
+    ID = Intrinsic::mips_subu_s_qb;
+    break;
+  case Mips::BI__builtin_mips_addq_ph:
+    ID = Intrinsic::mips_addq_ph;
+    break;
+  case Mips::BI__builtin_mips_addq_s_ph:
+    ID = Intrinsic::mips_addq_s_ph;
+    break;
+  case Mips::BI__builtin_mips_subq_ph:
+    ID = Intrinsic::mips_subq_ph;
+    break;
+  case Mips::BI__builtin_mips_subq_s_ph:
+    ID = Intrinsic::mips_subq_s_ph;
+    break;
+  case Mips::BI__builtin_mips_madd:
+    ID = Intrinsic::mips_madd;
+    break;
+  case Mips::BI__builtin_mips_maddu:
+    ID = Intrinsic::mips_maddu;
+    break;
+  case Mips::BI__builtin_mips_msub:
+    ID = Intrinsic::mips_msub;
+    break;
+  case Mips::BI__builtin_mips_msubu:
+    ID = Intrinsic::mips_msubu;
+    break;
+  case Mips::BI__builtin_mips_addq_s_w:
+    ID = Intrinsic::mips_addq_s_w;
+    break;
+  case Mips::BI__builtin_mips_subq_s_w:
+    ID = Intrinsic::mips_subq_s_w;
+    break;
+  case Mips::BI__builtin_mips_addsc:
+    ID = Intrinsic::mips_addsc;
+    break;
+  case Mips::BI__builtin_mips_addwc:
+    ID = Intrinsic::mips_addwc;
+    break;
+  case Mips::BI__builtin_mips_modsub:
+    ID = Intrinsic::mips_modsub;
+    break;
+  case Mips::BI__builtin_mips_raddu_w_qb:
+    ID = Intrinsic::mips_raddu_w_qb;
+    break;
+  case Mips::BI__builtin_mips_absq_s_ph:
+    ID = Intrinsic::mips_absq_s_ph;
+    break;
+  case Mips::BI__builtin_mips_absq_s_w:
+    ID = Intrinsic::mips_absq_s_w;
+    break;
+  case Mips::BI__builtin_mips_precrq_qb_ph:
+    ID = Intrinsic::mips_precrq_qb_ph;
+    break;
+  case Mips::BI__builtin_mips_precrqu_s_qb_ph:
+    ID = Intrinsic::mips_precrqu_s_qb_ph;
+    break;
+  case Mips::BI__builtin_mips_precrq_ph_w:
+    ID = Intrinsic::mips_precrq_ph_w;
+    break;
+  case Mips::BI__builtin_mips_precrq_rs_ph_w:
+    ID = Intrinsic::mips_precrq_rs_ph_w;
+    break;
+  case Mips::BI__builtin_mips_preceq_w_phl:
+    ID = Intrinsic::mips_preceq_w_phl;
+    break;
+  case Mips::BI__builtin_mips_preceq_w_phr:
+    ID = Intrinsic::mips_preceq_w_phr;
+    break;
+  case Mips::BI__builtin_mips_precequ_ph_qbl:
+    ID = Intrinsic::mips_precequ_ph_qbl;
+    break;
+  case Mips::BI__builtin_mips_precequ_ph_qbr:
+    ID = Intrinsic::mips_precequ_ph_qbr;
+    break;
+  case Mips::BI__builtin_mips_precequ_ph_qbla:
+    ID = Intrinsic::mips_precequ_ph_qbla;
+    break;
+  case Mips::BI__builtin_mips_precequ_ph_qbra:
+    ID = Intrinsic::mips_precequ_ph_qbra;
+    break;
+  case Mips::BI__builtin_mips_preceu_ph_qbl:
+    ID = Intrinsic::mips_preceu_ph_qbl;
+    break;
+  case Mips::BI__builtin_mips_preceu_ph_qbr:
+    ID = Intrinsic::mips_preceu_ph_qbr;
+    break;
+  case Mips::BI__builtin_mips_preceu_ph_qbla:
+    ID = Intrinsic::mips_preceu_ph_qbla;
+    break;
+  case Mips::BI__builtin_mips_preceu_ph_qbra:
+    ID = Intrinsic::mips_preceu_ph_qbra;
+    break;
+  case Mips::BI__builtin_mips_shll_qb:
+    ID = Intrinsic::mips_shll_qb;
+    break;
+  case Mips::BI__builtin_mips_shrl_qb:
+    ID = Intrinsic::mips_shrl_qb;
+    break;
+  case Mips::BI__builtin_mips_shll_ph:
+    ID = Intrinsic::mips_shll_ph;
+    break;
+  case Mips::BI__builtin_mips_shll_s_ph:
+    ID = Intrinsic::mips_shll_s_ph;
+    break;
+  case Mips::BI__builtin_mips_shra_ph:
+    ID = Intrinsic::mips_shra_ph;
+    break;
+  case Mips::BI__builtin_mips_shra_r_ph:
+    ID = Intrinsic::mips_shra_r_ph;
+    break;
+  case Mips::BI__builtin_mips_shll_s_w:
+    ID = Intrinsic::mips_shll_s_w;
+    break;
+  case Mips::BI__builtin_mips_shra_r_w:
+    ID = Intrinsic::mips_shra_r_w;
+    break;
+  case Mips::BI__builtin_mips_shilo:
+    ID = Intrinsic::mips_shilo;
+    break;
+  case Mips::BI__builtin_mips_muleu_s_ph_qbl:
+    ID = Intrinsic::mips_muleu_s_ph_qbl;
+    break;
+  case Mips::BI__builtin_mips_muleu_s_ph_qbr:
+    ID = Intrinsic::mips_muleu_s_ph_qbr;
+    break;
+  case Mips::BI__builtin_mips_mulq_rs_ph:
+    ID = Intrinsic::mips_mulq_rs_ph;
+    break;
+  case Mips::BI__builtin_mips_muleq_s_w_phl:
+    ID = Intrinsic::mips_muleq_s_w_phl;
+    break;
+  case Mips::BI__builtin_mips_muleq_s_w_phr:
+    ID = Intrinsic::mips_muleq_s_w_phr;
+    break;
+  case Mips::BI__builtin_mips_mulsaq_s_w_ph:
+    ID = Intrinsic::mips_mulsaq_s_w_ph;
+    break;
+  case Mips::BI__builtin_mips_maq_s_w_phl:
+    ID = Intrinsic::mips_maq_s_w_phl;
+    break;
+  case Mips::BI__builtin_mips_maq_s_w_phr:
+    ID = Intrinsic::mips_maq_s_w_phr;
+    break;
+  case Mips::BI__builtin_mips_maq_sa_w_phl:
+    ID = Intrinsic::mips_maq_sa_w_phl;
+    break;
+  case Mips::BI__builtin_mips_maq_sa_w_phr:
+    ID = Intrinsic::mips_maq_sa_w_phr;
+    break;
+  case Mips::BI__builtin_mips_mult:
+    ID = Intrinsic::mips_mult;
+    break;
+  case Mips::BI__builtin_mips_multu:
+    ID = Intrinsic::mips_multu;
+    break;
+  case Mips::BI__builtin_mips_dpau_h_qbl:
+    ID = Intrinsic::mips_dpau_h_qbl;
+    break;
+  case Mips::BI__builtin_mips_dpau_h_qbr:
+    ID = Intrinsic::mips_dpau_h_qbr;
+    break;
+  case Mips::BI__builtin_mips_dpsu_h_qbl:
+    ID = Intrinsic::mips_dpsu_h_qbl;
+    break;
+  case Mips::BI__builtin_mips_dpsu_h_qbr:
+    ID = Intrinsic::mips_dpsu_h_qbr;
+    break;
+  case Mips::BI__builtin_mips_dpaq_s_w_ph:
+    ID = Intrinsic::mips_dpaq_s_w_ph;
+    break;
+  case Mips::BI__builtin_mips_dpsq_s_w_ph:
+    ID = Intrinsic::mips_dpsq_s_w_ph;
+    break;
+  case Mips::BI__builtin_mips_dpaq_sa_l_w:
+    ID = Intrinsic::mips_dpaq_sa_l_w;
+    break;
+  case Mips::BI__builtin_mips_dpsq_sa_l_w:
+    ID = Intrinsic::mips_dpsq_sa_l_w;
+    break;
+  case Mips::BI__builtin_mips_cmpu_eq_qb:
+    ID = Intrinsic::mips_cmpu_eq_qb;
+    break;
+  case Mips::BI__builtin_mips_cmpu_lt_qb:
+    ID = Intrinsic::mips_cmpu_lt_qb;
+    break;
+  case Mips::BI__builtin_mips_cmpu_le_qb:
+    ID = Intrinsic::mips_cmpu_le_qb;
+    break;
+  case Mips::BI__builtin_mips_cmpgu_eq_qb:
+    ID = Intrinsic::mips_cmpgu_eq_qb;
+    break;
+  case Mips::BI__builtin_mips_cmpgu_lt_qb:
+    ID = Intrinsic::mips_cmpgu_lt_qb;
+    break;
+  case Mips::BI__builtin_mips_cmpgu_le_qb:
+    ID = Intrinsic::mips_cmpgu_le_qb;
+    break;
+  case Mips::BI__builtin_mips_cmp_eq_ph:
+    ID = Intrinsic::mips_cmp_eq_ph;
+    break;
+  case Mips::BI__builtin_mips_cmp_lt_ph:
+    ID = Intrinsic::mips_cmp_lt_ph;
+    break;
+  case Mips::BI__builtin_mips_cmp_le_ph:
+    ID = Intrinsic::mips_cmp_le_ph;
+    break;
+  case Mips::BI__builtin_mips_extr_s_h:
+    ID = Intrinsic::mips_extr_s_h;
+    break;
+  case Mips::BI__builtin_mips_extr_w:
+    ID = Intrinsic::mips_extr_w;
+    break;
+  case Mips::BI__builtin_mips_extr_rs_w:
+    ID = Intrinsic::mips_extr_rs_w;
+    break;
+  case Mips::BI__builtin_mips_extr_r_w:
+    ID = Intrinsic::mips_extr_r_w;
+    break;
+  case Mips::BI__builtin_mips_extp:
+    ID = Intrinsic::mips_extp;
+    break;
+  case Mips::BI__builtin_mips_extpdp:
+    ID = Intrinsic::mips_extpdp;
+    break;
+  case Mips::BI__builtin_mips_wrdsp:
+    ID = Intrinsic::mips_wrdsp;
+    break;
+  case Mips::BI__builtin_mips_rddsp:
+    ID = Intrinsic::mips_rddsp;
+    break;
+  case Mips::BI__builtin_mips_insv:
+    ID = Intrinsic::mips_insv;
+    break;
+  case Mips::BI__builtin_mips_bitrev:
+    ID = Intrinsic::mips_bitrev;
+    break;
+  case Mips::BI__builtin_mips_packrl_ph:
+    ID = Intrinsic::mips_packrl_ph;
+    break;
+  case Mips::BI__builtin_mips_repl_qb:
+    ID = Intrinsic::mips_repl_qb;
+    break;
+  case Mips::BI__builtin_mips_repl_ph:
+    ID = Intrinsic::mips_repl_ph;
+    break;
+  case Mips::BI__builtin_mips_pick_qb:
+    ID = Intrinsic::mips_pick_qb;
+    break;
+  case Mips::BI__builtin_mips_pick_ph:
+    ID = Intrinsic::mips_pick_ph;
+    break;
+  case Mips::BI__builtin_mips_mthlip:
+    ID = Intrinsic::mips_mthlip;
+    break;
+  case Mips::BI__builtin_mips_bposge32:
+    ID = Intrinsic::mips_bposge32;
+    break;
+  case Mips::BI__builtin_mips_lbux:
+    ID = Intrinsic::mips_lbux;
+    break;
+  case Mips::BI__builtin_mips_lhx:
+    ID = Intrinsic::mips_lhx;
+    break;
+  case Mips::BI__builtin_mips_lwx:
+    ID = Intrinsic::mips_lwx;
+    break;
+  }
+
+  llvm::Function *F = CGM.getIntrinsic(ID);
+  return Builder.CreateCall(F, Ops, "");
+}
diff --git a/lib/CodeGen/CodeGenFunction.h b/lib/CodeGen/CodeGenFunction.h
index fd93fbb..1147307 100644
--- a/lib/CodeGen/CodeGenFunction.h
+++ b/lib/CodeGen/CodeGenFunction.h
@@ -2266,6 +2266,7 @@
   llvm::Value *EmitX86BuiltinExpr(unsigned BuiltinID, const CallExpr *E);
   llvm::Value *EmitHexagonBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
   llvm::Value *EmitPPCBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
+  llvm::Value *EmitMipsBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
 
   llvm::Value *EmitObjCProtocolExpr(const ObjCProtocolExpr *E);
   llvm::Value *EmitObjCStringLiteral(const ObjCStringLiteral *E);
diff --git a/test/CodeGen/builtins-mips.c b/test/CodeGen/builtins-mips.c
new file mode 100644
index 0000000..8a848af
--- /dev/null
+++ b/test/CodeGen/builtins-mips.c
@@ -0,0 +1,227 @@
+// RUN: %clang_cc1 -triple mips-unknown-linux-gnu -emit-llvm -o %t %s
+// RUN: not grep __builtin %t
+
+typedef int q31;
+typedef int i32;
+typedef unsigned int ui32;
+typedef long long a64;
+
+typedef signed char v4i8 __attribute__ ((vector_size(4)));
+typedef short v2q15 __attribute__ ((vector_size(4)));
+
+void foo() {
+  v2q15 v2q15_r, v2q15_a, v2q15_b, v2q15_c;
+  v4i8 v4i8_r, v4i8_a, v4i8_b, v4i8_c;
+  q31 q31_r, q31_a, q31_b, q31_c;
+  i32 i32_r, i32_a, i32_b, i32_c;
+  ui32 ui32_r, ui32_a, ui32_b, ui32_c;
+  a64 a64_r, a64_a, a64_b;
+
+  // MIPS DSP Rev 1
+
+  v4i8_a = (v4i8) {1, 2, 3, 0xFF};
+  v4i8_b = (v4i8) {2, 4, 6, 8};
+  v4i8_r = __builtin_mips_addu_qb(v4i8_a, v4i8_b);
+  v4i8_r = __builtin_mips_addu_s_qb(v4i8_a, v4i8_b);
+  v4i8_r = __builtin_mips_subu_qb(v4i8_a, v4i8_b);
+  v4i8_r = __builtin_mips_subu_s_qb(v4i8_a, v4i8_b);
+
+  v2q15_a = (v2q15) {0x0000, 0x8000};
+  v2q15_b = (v2q15) {0x8000, 0x8000};
+  v2q15_r = __builtin_mips_addq_ph(v2q15_a, v2q15_b);
+  v2q15_r = __builtin_mips_addq_s_ph(v2q15_a, v2q15_b);
+  v2q15_r = __builtin_mips_subq_ph(v2q15_a, v2q15_b);
+  v2q15_r = __builtin_mips_subq_s_ph(v2q15_a, v2q15_b);
+
+  a64_a = 0x12345678;
+  i32_b = 0x80000000;
+  i32_c = 0x11112222;
+  a64_r = __builtin_mips_madd(a64_a, i32_b, i32_c);
+  a64_a = 0x12345678;
+  ui32_b = 0x80000000;
+  ui32_c = 0x11112222;
+  a64_r = __builtin_mips_maddu(a64_a, ui32_b, ui32_c);
+  a64_a = 0x12345678;
+  i32_b = 0x80000000;
+  i32_c = 0x11112222;
+  a64_r = __builtin_mips_msub(a64_a, i32_b, i32_c);
+  a64_a = 0x12345678;
+  ui32_b = 0x80000000;
+  ui32_c = 0x11112222;
+  a64_r = __builtin_mips_msubu(a64_a, ui32_b, ui32_c);
+
+  q31_a = 0x12345678;
+  q31_b = 0x7FFFFFFF;
+  q31_r = __builtin_mips_addq_s_w(q31_a, q31_b);
+  q31_r = __builtin_mips_subq_s_w(q31_a, q31_b);
+
+  i32_a = 0xFFFFFFFF;
+  i32_b = 1;
+  i32_r = __builtin_mips_addsc(i32_a, i32_b);
+  i32_a = 0;
+  i32_b = 1;
+  i32_r = __builtin_mips_addwc(i32_a, i32_b);
+
+  i32_a = 20;
+  i32_b = 0x1402;
+  i32_r = __builtin_mips_modsub(i32_a, i32_b);
+
+  v4i8_a = (v4i8) {1, 2, 3, 4};
+  i32_r = __builtin_mips_raddu_w_qb(v4i8_a);
+
+  v2q15_a = (v2q15) {0xFFFF, 0x8000};
+  v2q15_r = __builtin_mips_absq_s_ph(v2q15_a);
+  q31_a = 0x80000000;
+  q31_r = __builtin_mips_absq_s_w(q31_a);
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x1111, 0x2222};
+  v4i8_r = __builtin_mips_precrq_qb_ph(v2q15_a, v2q15_b);
+
+  v2q15_a = (v2q15) {0x7F79, 0xFFFF};
+  v2q15_b = (v2q15) {0x7F81, 0x2000};
+  v4i8_r = __builtin_mips_precrqu_s_qb_ph(v2q15_a, v2q15_b);
+  q31_a = 0x12345678;
+  q31_b = 0x11112222;
+  v2q15_r = __builtin_mips_precrq_ph_w(q31_a, q31_b);
+  q31_a = 0x7000FFFF;
+  q31_b = 0x80000000;
+  v2q15_r = __builtin_mips_precrq_rs_ph_w(q31_a, q31_b);
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  q31_r = __builtin_mips_preceq_w_phl(v2q15_a);
+  q31_r = __builtin_mips_preceq_w_phr(v2q15_a);
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v2q15_r = __builtin_mips_precequ_ph_qbl(v4i8_a);
+  v2q15_r = __builtin_mips_precequ_ph_qbr(v4i8_a);
+  v2q15_r = __builtin_mips_precequ_ph_qbla(v4i8_a);
+  v2q15_r = __builtin_mips_precequ_ph_qbra(v4i8_a);
+  v2q15_r = __builtin_mips_preceu_ph_qbl(v4i8_a);
+  v2q15_r = __builtin_mips_preceu_ph_qbr(v4i8_a);
+  v2q15_r = __builtin_mips_preceu_ph_qbla(v4i8_a);
+  v2q15_r = __builtin_mips_preceu_ph_qbra(v4i8_a);
+
+  v4i8_a = (v4i8) {1, 2, 3, 4};
+  v4i8_r = __builtin_mips_shll_qb(v4i8_a, 2);
+  v4i8_a = (v4i8) {128, 64, 32, 16};
+  v4i8_r = __builtin_mips_shrl_qb(v4i8_a, 2);
+  v2q15_a = (v2q15) {0x0001, 0x8000};
+  v2q15_r = __builtin_mips_shll_ph(v2q15_a, 2);
+  v2q15_r = __builtin_mips_shll_s_ph(v2q15_a, 2);
+  v2q15_a = (v2q15) {0x7FFF, 0x8000};
+  v2q15_r = __builtin_mips_shra_ph(v2q15_a, 2);
+  v2q15_r = __builtin_mips_shra_r_ph(v2q15_a, 2);
+  q31_a = 0x70000000;
+  q31_r = __builtin_mips_shll_s_w(q31_a, 2);
+  q31_a = 0x7FFFFFFF;
+  q31_r = __builtin_mips_shra_r_w(q31_a, 2);
+  a64_a = 0x1234567887654321LL;
+  a64_r = __builtin_mips_shilo(a64_a, -8);
+
+  v4i8_a = (v4i8) {0x1, 0x3, 0x5, 0x7};
+  v2q15_b = (v2q15) {0x1234, 0x5678};
+  v2q15_r = __builtin_mips_muleu_s_ph_qbl(v4i8_a, v2q15_b);
+  v2q15_r = __builtin_mips_muleu_s_ph_qbr(v4i8_a, v2q15_b);
+  v2q15_a = (v2q15) {0x7FFF, 0x8000};
+  v2q15_b = (v2q15) {0x7FFF, 0x8000};
+  v2q15_r = __builtin_mips_mulq_rs_ph(v2q15_a, v2q15_b);
+  v2q15_a = (v2q15) {0x1234, 0x8000};
+  v2q15_b = (v2q15) {0x5678, 0x8000};
+  q31_r = __builtin_mips_muleq_s_w_phl(v2q15_a, v2q15_b);
+  q31_r = __builtin_mips_muleq_s_w_phr(v2q15_a, v2q15_b);
+  a64_a = 0;
+  v2q15_a = (v2q15) {0x0001, 0x8000};
+  v2q15_b = (v2q15) {0x0002, 0x8000};
+  a64_r = __builtin_mips_mulsaq_s_w_ph(a64_a, v2q15_b, v2q15_c);
+  a64_a = 0;
+  v2q15_b = (v2q15) {0x0001, 0x8000};
+  v2q15_c = (v2q15) {0x0002, 0x8000};
+  a64_r = __builtin_mips_maq_s_w_phl(a64_a, v2q15_b, v2q15_c);
+  a64_r = __builtin_mips_maq_s_w_phr(a64_a, v2q15_b, v2q15_c);
+  a64_a = 0x7FFFFFF0;
+  a64_r = __builtin_mips_maq_sa_w_phl(a64_a, v2q15_b, v2q15_c);
+  a64_r = __builtin_mips_maq_sa_w_phr(a64_a, v2q15_b, v2q15_c);
+  i32_a = 0x80000000;
+  i32_b = 0x11112222;
+  a64_r = __builtin_mips_mult(i32_a, i32_b);
+  ui32_a = 0x80000000;
+  ui32_b = 0x11112222;
+  a64_r = __builtin_mips_multu(ui32_a, ui32_b);
+
+  a64_a = 0;
+  v4i8_b = (v4i8) {1, 2, 3, 4};
+  v4i8_c = (v4i8) {4, 5, 6, 7};
+  a64_r = __builtin_mips_dpau_h_qbl(a64_a, v4i8_b, v4i8_c);
+  a64_r = __builtin_mips_dpau_h_qbr(a64_a, v4i8_b, v4i8_c);
+  a64_r = __builtin_mips_dpsu_h_qbl(a64_a, v4i8_b, v4i8_c);
+  a64_r = __builtin_mips_dpsu_h_qbr(a64_a, v4i8_b, v4i8_c);
+  a64_a = 0;
+  v2q15_b = (v2q15) {0x0001, 0x8000};
+  v2q15_c = (v2q15) {0x0002, 0x8000};
+  a64_r = __builtin_mips_dpaq_s_w_ph(a64_a, v2q15_b, v2q15_c);
+  a64_r = __builtin_mips_dpsq_s_w_ph(a64_a, v2q15_b, v2q15_c);
+  a64_a = 0;
+  q31_b = 0x80000000;
+  q31_c = 0x80000000;
+  a64_r = __builtin_mips_dpaq_sa_l_w(a64_a, q31_b, q31_c);
+  a64_r = __builtin_mips_dpsq_sa_l_w(a64_a, q31_b, q31_c);
+
+  v4i8_a = (v4i8) {1, 4, 10, 8};
+  v4i8_b = (v4i8) {1, 2, 100, 8};
+  __builtin_mips_cmpu_eq_qb(v4i8_a, v4i8_b);
+  __builtin_mips_cmpu_lt_qb(v4i8_a, v4i8_b);
+  __builtin_mips_cmpu_le_qb(v4i8_a, v4i8_b);
+  i32_r = __builtin_mips_cmpgu_eq_qb(v4i8_a, v4i8_b);
+  i32_r = __builtin_mips_cmpgu_lt_qb(v4i8_a, v4i8_b);
+  i32_r = __builtin_mips_cmpgu_le_qb(v4i8_a, v4i8_b);
+  v2q15_a = (v2q15) {0x1111, 0x1234};
+  v2q15_b = (v2q15) {0x4444, 0x1234};
+  __builtin_mips_cmp_eq_ph(v2q15_a, v2q15_b);
+  __builtin_mips_cmp_lt_ph(v2q15_a, v2q15_b);
+  __builtin_mips_cmp_le_ph(v2q15_a, v2q15_b);
+
+  a64_a = 0xFFFFF81230000000LL;
+  i32_r = __builtin_mips_extr_s_h(a64_a, 4);
+  a64_a = 0x8123456712345678LL;
+  i32_r = __builtin_mips_extr_w(a64_a, 31);
+  i32_r = __builtin_mips_extr_rs_w(a64_a, 31);
+  i32_r = __builtin_mips_extr_r_w(a64_a, 31);
+  a64_a = 0x1234567887654321LL;
+  i32_r = __builtin_mips_extp(a64_a, 3);
+  a64_a = 0x123456789ABCDEF0LL;
+  i32_r = __builtin_mips_extpdp(a64_a, 7);
+
+  __builtin_mips_wrdsp(2052, 3);
+  i32_r = __builtin_mips_rddsp(3);
+  i32_a = 0xFFFFFFFF;
+  i32_b = 0x12345678;
+  __builtin_mips_wrdsp((16<<7) + 4, 3);
+  i32_r = __builtin_mips_insv(i32_a, i32_b);
+  i32_a = 0x1234;
+  i32_r = __builtin_mips_bitrev(i32_a);
+  v2q15_a = (v2q15) {0x1111, 0x2222};
+  v2q15_b = (v2q15) {0x3333, 0x4444};
+  v2q15_r = __builtin_mips_packrl_ph(v2q15_a, v2q15_b);
+  i32_a = 100;
+  v4i8_r = __builtin_mips_repl_qb(i32_a);
+  i32_a = 0x1234;
+  v2q15_r = __builtin_mips_repl_ph(i32_a);
+  v4i8_a = (v4i8) {1, 4, 10, 8};
+  v4i8_b = (v4i8) {1, 2, 100, 8};
+  __builtin_mips_cmpu_eq_qb(v4i8_a, v4i8_b);
+  v4i8_r = __builtin_mips_pick_qb(v4i8_a, v4i8_b);
+  v2q15_a = (v2q15) {0x1111, 0x1234};
+  v2q15_b = (v2q15) {0x4444, 0x1234};
+  __builtin_mips_cmp_eq_ph(v2q15_a, v2q15_b);
+  v2q15_r = __builtin_mips_pick_ph(v2q15_a, v2q15_b);
+  a64_a = 0x1234567887654321LL;
+  i32_b = 0x11112222;
+  __builtin_mips_wrdsp(0, 1);
+  a64_r = __builtin_mips_mthlip(a64_a, i32_b);
+  i32_r = __builtin_mips_bposge32();
+  char array_a[100];
+  i32_r = __builtin_mips_lbux(array_a, 20);
+  short array_b[100];
+  i32_r = __builtin_mips_lhx(array_b, 20);
+  int array_c[100];
+  i32_r = __builtin_mips_lwx(array_c, 20);
+}