tree 331a918c1e5300656a7ad1c766ed2f5d7ebf3471
parent 3133625859b74df42deddd80b705578af6fc2fea
author Pali Rohár <pali@kernel.org> 1621000331 +0200
committer Pali Rohár <pali@kernel.org> 1622639992 +0100

fix(plat/marvell/a3720/uart): fix UART parent clock rate determination

The UART code for the A3K platform assumes that UART parent clock rate
is always 25 MHz. This is incorrect, because the xtal clock can also run
at 40 MHz (this is board specific).

The frequency of the xtal clock is determined by a value on a strapping
pin during SOC reset. The code to determine this frequency is already in
A3K's comphy driver.

Move the get_ref_clk() function from the comphy driver to a separate
file and use it for UART parent clock rate determination.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e