am fe87596a: am c37dcd3d: Merge "Upgrade to dlmalloc 2.8.5."

* commit 'fe87596a5ba5a5b0773b2854f9fce85f49367611':
  Upgrade to dlmalloc 2.8.5.
diff --git a/libc/kernel/common/asm-generic/fcntl.h b/libc/kernel/common/asm-generic/fcntl.h
index 0944a2a..be03cdf 100644
--- a/libc/kernel/common/asm-generic/fcntl.h
+++ b/libc/kernel/common/asm-generic/fcntl.h
@@ -47,8 +47,8 @@
 #define O_NONBLOCK 00004000
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #endif
-#ifndef O_SYNC
-#define O_SYNC 00010000
+#ifndef O_DSYNC
+#define O_DSYNC 00010000  
 #endif
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #ifndef FASYNC
@@ -73,97 +73,120 @@
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define O_NOATIME 01000000
 #endif
+#ifndef O_CLOEXEC
+#define O_CLOEXEC 02000000  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#endif
+#ifndef O_SYNC
+#define __O_SYNC 04000000
+#define O_SYNC (__O_SYNC|O_DSYNC)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#endif
+#ifndef O_PATH
+#define O_PATH 010000000
+#endif
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #ifndef O_NDELAY
 #define O_NDELAY O_NONBLOCK
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #endif
 #define F_DUPFD 0  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define F_GETFD 1  
 #define F_SETFD 2  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define F_GETFL 3  
 #define F_SETFL 4  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #ifndef F_GETLK
 #define F_GETLK 5
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define F_SETLK 6
 #define F_SETLKW 7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #endif
 #ifndef F_SETOWN
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define F_SETOWN 8  
 #define F_GETOWN 9  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #endif
 #ifndef F_SETSIG
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define F_SETSIG 10  
 #define F_GETSIG 11  
-#endif
-#define FD_CLOEXEC 1  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#ifndef F_RDLCK
-#define F_RDLCK 0
-#define F_WRLCK 1
-#define F_UNLCK 2
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#endif
-#ifndef F_EXLCK
-#define F_EXLCK 4  
-#define F_SHLCK 8  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#endif
-#ifndef F_INPROGRESS
-#define F_INPROGRESS 16
-#endif
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define LOCK_SH 1  
-#define LOCK_EX 2  
-#define LOCK_NB 4  
-#define LOCK_UN 8  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define LOCK_MAND 32  
-#define LOCK_READ 64  
-#define LOCK_WRITE 128  
-#define LOCK_RW 192  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define F_LINUX_SPECIFIC_BASE 1024
-#ifndef HAVE_ARCH_STRUCT_FLOCK
-#ifndef __ARCH_FLOCK_PAD
-#define __ARCH_FLOCK_PAD
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#endif
-struct flock {
- short l_type;
- short l_whence;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- off_t l_start;
- off_t l_len;
- pid_t l_pid;
- __ARCH_FLOCK_PAD
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-};
 #endif
 #ifndef F_GETLK64
 #define F_GETLK64 12  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define F_SETLK64 13
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define F_SETLKW64 14
 #endif
-#ifndef HAVE_ARCH_STRUCT_FLOCK64
+#ifndef F_SETOWN_EX
+#define F_SETOWN_EX 15
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#ifndef __ARCH_FLOCK64_PAD
-#define __ARCH_FLOCK64_PAD
+#define F_GETOWN_EX 16
 #endif
-struct flock64 {
+#define F_OWNER_TID 0
+#define F_OWNER_PID 1
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define F_OWNER_PGRP 2
+struct f_owner_ex {
+ int type;
+ __kernel_pid_t pid;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+#define FD_CLOEXEC 1  
+#ifndef F_RDLCK
+#define F_RDLCK 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define F_WRLCK 1
+#define F_UNLCK 2
+#endif
+#ifndef F_EXLCK
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define F_EXLCK 4  
+#define F_SHLCK 8  
+#endif
+#define LOCK_SH 1  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define LOCK_EX 2  
+#define LOCK_NB 4  
+#define LOCK_UN 8  
+#define LOCK_MAND 32  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define LOCK_READ 64  
+#define LOCK_WRITE 128  
+#define LOCK_RW 192  
+#define F_LINUX_SPECIFIC_BASE 1024
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#ifndef HAVE_ARCH_STRUCT_FLOCK
+#ifndef __ARCH_FLOCK_PAD
+#define __ARCH_FLOCK_PAD
+#endif
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct flock {
  short l_type;
  short l_whence;
- loff_t l_start;
- loff_t l_len;
+ __kernel_off_t l_start;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- pid_t l_pid;
+ __kernel_off_t l_len;
+ __kernel_pid_t l_pid;
+ __ARCH_FLOCK_PAD
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#endif
+#ifndef HAVE_ARCH_STRUCT_FLOCK64
+#ifndef __ARCH_FLOCK64_PAD
+#define __ARCH_FLOCK64_PAD
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#endif
+struct flock64 {
+ short l_type;
+ short l_whence;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __kernel_loff_t l_start;
+ __kernel_loff_t l_len;
+ __kernel_pid_t l_pid;
  __ARCH_FLOCK64_PAD
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #endif
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #endif
+
diff --git a/libc/kernel/common/linux/fb.h b/libc/kernel/common/linux/fb.h
old mode 100644
new mode 100755
index 451301c..48eec81
--- a/libc/kernel/common/linux/fb.h
+++ b/libc/kernel/common/linux/fb.h
@@ -51,152 +51,157 @@
 #define FB_TYPE_TEXT 3  
 #define FB_TYPE_VGA_PLANES 4  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define FB_TYPE_FOURCC 5  
 #define FB_AUX_TEXT_MDA 0  
 #define FB_AUX_TEXT_CGA 1  
 #define FB_AUX_TEXT_S3_MMIO 2  
-#define FB_AUX_TEXT_MGA_STEP16 3  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define FB_AUX_TEXT_MGA_STEP16 3  
 #define FB_AUX_TEXT_MGA_STEP8 4  
 #define FB_AUX_TEXT_SVGA_GROUP 8  
 #define FB_AUX_TEXT_SVGA_MASK 7  
-#define FB_AUX_TEXT_SVGA_STEP2 8  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define FB_AUX_TEXT_SVGA_STEP2 8  
 #define FB_AUX_TEXT_SVGA_STEP4 9  
 #define FB_AUX_TEXT_SVGA_STEP8 10  
 #define FB_AUX_TEXT_SVGA_STEP16 11  
-#define FB_AUX_TEXT_SVGA_LAST 15  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define FB_AUX_TEXT_SVGA_LAST 15  
 #define FB_AUX_VGA_PLANES_VGA4 0  
 #define FB_AUX_VGA_PLANES_CFB4 1  
 #define FB_AUX_VGA_PLANES_CFB8 2  
-#define FB_VISUAL_MONO01 0  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define FB_VISUAL_MONO01 0  
 #define FB_VISUAL_MONO10 1  
 #define FB_VISUAL_TRUECOLOR 2  
 #define FB_VISUAL_PSEUDOCOLOR 3  
-#define FB_VISUAL_DIRECTCOLOR 4  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define FB_VISUAL_DIRECTCOLOR 4  
 #define FB_VISUAL_STATIC_PSEUDOCOLOR 5  
+#define FB_VISUAL_FOURCC 6  
 #define FB_ACCEL_NONE 0  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_ATARIBLITT 1  
 #define FB_ACCEL_AMIGABLITT 2  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_S3_TRIO64 3  
 #define FB_ACCEL_NCR_77C32BLT 4  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_S3_VIRGE 5  
 #define FB_ACCEL_ATI_MACH64GX 6  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_DEC_TGA 7  
 #define FB_ACCEL_ATI_MACH64CT 8  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_ATI_MACH64VT 9  
 #define FB_ACCEL_ATI_MACH64GT 10  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_SUN_CREATOR 11  
 #define FB_ACCEL_SUN_CGSIX 12  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_SUN_LEO 13  
 #define FB_ACCEL_IMS_TWINTURBO 14  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_3DLABS_PERMEDIA2 15  
 #define FB_ACCEL_MATROX_MGA2064W 16  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_MATROX_MGA1064SG 17  
 #define FB_ACCEL_MATROX_MGA2164W 18  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_MATROX_MGA2164W_AGP 19  
 #define FB_ACCEL_MATROX_MGAG100 20  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_MATROX_MGAG200 21  
 #define FB_ACCEL_SUN_CG14 22  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_SUN_BWTWO 23  
 #define FB_ACCEL_SUN_CGTHREE 24  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_SUN_TCX 25  
 #define FB_ACCEL_MATROX_MGAG400 26  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_NV3 27  
 #define FB_ACCEL_NV4 28  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_NV5 29  
 #define FB_ACCEL_CT_6555x 30  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_3DFX_BANSHEE 31  
 #define FB_ACCEL_ATI_RAGE128 32  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_IGS_CYBER2000 33  
 #define FB_ACCEL_IGS_CYBER2010 34  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_IGS_CYBER5000 35  
 #define FB_ACCEL_SIS_GLAMOUR 36  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_3DLABS_PERMEDIA3 37  
 #define FB_ACCEL_ATI_RADEON 38  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_I810 39  
 #define FB_ACCEL_SIS_GLAMOUR_2 40  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_SIS_XABRE 41  
 #define FB_ACCEL_I830 42  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_NV_10 43  
 #define FB_ACCEL_NV_20 44  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_NV_30 45  
 #define FB_ACCEL_NV_40 46  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_XGI_VOLARI_V 47  
 #define FB_ACCEL_XGI_VOLARI_Z 48  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_OMAP1610 49  
 #define FB_ACCEL_TRIDENT_TGUI 50  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_TRIDENT_3DIMAGE 51  
 #define FB_ACCEL_TRIDENT_BLADE3D 52  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_TRIDENT_BLADEXP 53  
 #define FB_ACCEL_CIRRUS_ALPINE 53  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_NEOMAGIC_NM2070 90  
 #define FB_ACCEL_NEOMAGIC_NM2090 91  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_NEOMAGIC_NM2093 92  
 #define FB_ACCEL_NEOMAGIC_NM2097 93  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_NEOMAGIC_NM2160 94  
 #define FB_ACCEL_NEOMAGIC_NM2200 95  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_NEOMAGIC_NM2230 96  
 #define FB_ACCEL_NEOMAGIC_NM2360 97  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_NEOMAGIC_NM2380 98  
 #define FB_ACCEL_PXA3XX 99  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_SAVAGE4 0x80  
 #define FB_ACCEL_SAVAGE3D 0x81  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_SAVAGE3D_MV 0x82  
 #define FB_ACCEL_SAVAGE2000 0x83  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_SAVAGE_MX_MV 0x84  
 #define FB_ACCEL_SAVAGE_MX 0x85  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_SAVAGE_IX_MV 0x86  
 #define FB_ACCEL_SAVAGE_IX 0x87  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_PROSAVAGE_PM 0x88  
 #define FB_ACCEL_PROSAVAGE_KM 0x89  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_S3TWISTER_P 0x8a  
 #define FB_ACCEL_S3TWISTER_K 0x8b  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_SUPERSAVAGE 0x8c  
 #define FB_ACCEL_PROSAVAGE_DDR 0x8d  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FB_ACCEL_PROSAVAGE_DDRK 0x8e  
 #define FB_ACCEL_PUV3_UNIGFX 0xa0  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define FB_CAP_FOURCC 1  
 struct fb_fix_screeninfo {
  char id[16];
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned long smem_start;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 smem_len;
  __u32 type;
  __u32 type_aux;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 visual;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u16 xpanstep;
  __u16 ypanstep;
  __u16 ywrapstep;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 line_length;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned long mmio_start;
  __u32 mmio_len;
  __u32 accel;
+ __u16 capabilities;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u16 reserved[3];
+ __u16 reserved[2];
 };
 struct fb_bitfield {
  __u32 offset;
@@ -286,114 +291,116 @@
  __u32 vmode;
  __u32 rotate;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 reserved[5];
+ __u32 colorspace;
+ __u32 reserved[4];
 };
 struct fb_cmap {
- __u32 start;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 start;
  __u32 len;
  __u16 *red;
  __u16 *green;
- __u16 *blue;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u16 *blue;
  __u16 *transp;
 };
 struct fb_con2fbmap {
- __u32 console;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 console;
  __u32 framebuffer;
 };
 #define VESA_NO_BLANKING 0
-#define VESA_VSYNC_SUSPEND 1
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VESA_VSYNC_SUSPEND 1
 #define VESA_HSYNC_SUSPEND 2
 #define VESA_POWERDOWN 3
 enum {
- FB_BLANK_UNBLANK = VESA_NO_BLANKING,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ FB_BLANK_UNBLANK = VESA_NO_BLANKING,
  FB_BLANK_NORMAL = VESA_NO_BLANKING + 1,
  FB_BLANK_VSYNC_SUSPEND = VESA_VSYNC_SUSPEND + 1,
  FB_BLANK_HSYNC_SUSPEND = VESA_HSYNC_SUSPEND + 1,
- FB_BLANK_POWERDOWN = VESA_POWERDOWN + 1
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ FB_BLANK_POWERDOWN = VESA_POWERDOWN + 1
 };
 #define FB_VBLANK_VBLANKING 0x001  
 #define FB_VBLANK_HBLANKING 0x002  
-#define FB_VBLANK_HAVE_VBLANK 0x004  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define FB_VBLANK_HAVE_VBLANK 0x004  
 #define FB_VBLANK_HAVE_HBLANK 0x008  
 #define FB_VBLANK_HAVE_COUNT 0x010  
 #define FB_VBLANK_HAVE_VCOUNT 0x020  
-#define FB_VBLANK_HAVE_HCOUNT 0x040  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define FB_VBLANK_HAVE_HCOUNT 0x040  
 #define FB_VBLANK_VSYNCING 0x080  
 #define FB_VBLANK_HAVE_VSYNC 0x100  
 struct fb_vblank {
- __u32 flags;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 flags;
  __u32 count;
  __u32 vcount;
  __u32 hcount;
- __u32 reserved[4];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 reserved[4];
 };
 #define ROP_COPY 0
 #define ROP_XOR 1
-struct fb_copyarea {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct fb_copyarea {
  __u32 dx;
  __u32 dy;
  __u32 width;
- __u32 height;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 height;
  __u32 sx;
  __u32 sy;
 };
-struct fb_fillrect {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct fb_fillrect {
  __u32 dx;
  __u32 dy;
  __u32 width;
- __u32 height;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 height;
  __u32 color;
  __u32 rop;
 };
-struct fb_image {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct fb_image {
  __u32 dx;
  __u32 dy;
  __u32 width;
- __u32 height;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 height;
  __u32 fg_color;
  __u32 bg_color;
  __u8 depth;
- const char *data;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ const char *data;
  struct fb_cmap cmap;
 };
 #define FB_CUR_SETIMAGE 0x01
-#define FB_CUR_SETPOS 0x02
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define FB_CUR_SETPOS 0x02
 #define FB_CUR_SETHOT 0x04
 #define FB_CUR_SETCMAP 0x08
 #define FB_CUR_SETSHAPE 0x10
-#define FB_CUR_SETSIZE 0x20
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define FB_CUR_SETSIZE 0x20
 #define FB_CUR_SETALL 0xFF
 struct fbcurpos {
  __u16 x, y;
-};
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
 struct fb_cursor {
  __u16 set;
  __u16 enable;
- __u16 rop;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u16 rop;
  const char *mask;
  struct fbcurpos hot;
  struct fb_image image;
-};
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
 #endif
+
diff --git a/libc/kernel/common/linux/genlock.h b/libc/kernel/common/linux/genlock.h
new file mode 100644
index 0000000..36a78dc
--- /dev/null
+++ b/libc/kernel/common/linux/genlock.h
@@ -0,0 +1,46 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ***   To edit the content of this header, modify the corresponding
+ ***   source file (e.g. under external/kernel-headers/original/) then
+ ***   run bionic/libc/kernel/tools/update_all.py
+ ***
+ ***   Any manual change here will be lost the next time this script will
+ ***   be run. You've been warned!
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef _GENLOCK_H_
+#define _GENLOCK_H_
+#define GENLOCK_UNLOCK 0
+#define GENLOCK_WRLOCK 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define GENLOCK_RDLOCK 2
+#define GENLOCK_NOBLOCK (1 << 0)
+#define GENLOCK_WRITE_TO_READ (1 << 1)
+struct genlock_lock {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ int fd;
+ int op;
+ int flags;
+ int timeout;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+#define GENLOCK_IOC_MAGIC 'G'
+#define GENLOCK_IOC_NEW _IO(GENLOCK_IOC_MAGIC, 0)
+#define GENLOCK_IOC_EXPORT _IOR(GENLOCK_IOC_MAGIC, 1,   struct genlock_lock)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define GENLOCK_IOC_ATTACH _IOW(GENLOCK_IOC_MAGIC, 2,   struct genlock_lock)
+#define GENLOCK_IOC_LOCK _IOW(GENLOCK_IOC_MAGIC, 3,   struct genlock_lock)
+#define GENLOCK_IOC_RELEASE _IO(GENLOCK_IOC_MAGIC, 4)
+#define GENLOCK_IOC_WAIT _IOW(GENLOCK_IOC_MAGIC, 5,   struct genlock_lock)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define GENLOCK_IOC_DREADLOCK _IOW(GENLOCK_IOC_MAGIC, 6,   struct genlock_lock)
+#endif
+
diff --git a/libc/kernel/common/linux/media.h b/libc/kernel/common/linux/media.h
new file mode 100644
index 0000000..94dde3f
--- /dev/null
+++ b/libc/kernel/common/linux/media.h
@@ -0,0 +1,126 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ***   To edit the content of this header, modify the corresponding
+ ***   source file (e.g. under external/kernel-headers/original/) then
+ ***   run bionic/libc/kernel/tools/update_all.py
+ ***
+ ***   Any manual change here will be lost the next time this script will
+ ***   be run. You've been warned!
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __LINUX_MEDIA_H
+#define __LINUX_MEDIA_H
+#include <linux/ioctl.h>
+#include <linux/types.h>
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#include <linux/version.h>
+#define MEDIA_API_VERSION KERNEL_VERSION(0, 1, 0)
+struct media_device_info {
+ char driver[16];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ char model[32];
+ char serial[40];
+ char bus_info[32];
+ __u32 media_version;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 hw_revision;
+ __u32 driver_version;
+ __u32 reserved[31];
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MEDIA_ENT_ID_FLAG_NEXT (1 << 31)
+#define MEDIA_ENT_TYPE_SHIFT 16
+#define MEDIA_ENT_TYPE_MASK 0x00ff0000
+#define MEDIA_ENT_SUBTYPE_MASK 0x0000ffff
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MEDIA_ENT_T_DEVNODE (1 << MEDIA_ENT_TYPE_SHIFT)
+#define MEDIA_ENT_T_DEVNODE_V4L (MEDIA_ENT_T_DEVNODE + 1)
+#define MEDIA_ENT_T_DEVNODE_FB (MEDIA_ENT_T_DEVNODE + 2)
+#define MEDIA_ENT_T_DEVNODE_ALSA (MEDIA_ENT_T_DEVNODE + 3)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MEDIA_ENT_T_DEVNODE_DVB (MEDIA_ENT_T_DEVNODE + 4)
+#define MEDIA_ENT_T_V4L2_SUBDEV (2 << MEDIA_ENT_TYPE_SHIFT)
+#define MEDIA_ENT_T_V4L2_SUBDEV_SENSOR (MEDIA_ENT_T_V4L2_SUBDEV + 1)
+#define MEDIA_ENT_T_V4L2_SUBDEV_FLASH (MEDIA_ENT_T_V4L2_SUBDEV + 2)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MEDIA_ENT_T_V4L2_SUBDEV_LENS (MEDIA_ENT_T_V4L2_SUBDEV + 3)
+#define MEDIA_ENT_FL_DEFAULT (1 << 0)
+struct media_entity_desc {
+ __u32 id;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ char name[32];
+ __u32 type;
+ __u32 revision;
+ __u32 flags;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 group_id;
+ __u16 pads;
+ __u16 links;
+ __u32 reserved[4];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ union {
+ struct {
+ __u32 major;
+ __u32 minor;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ } v4l;
+ struct {
+ __u32 major;
+ __u32 minor;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ } fb;
+ struct {
+ __u32 card;
+ __u32 device;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 subdevice;
+ } alsa;
+ int dvb;
+ __u8 raw[184];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ };
+};
+#define MEDIA_PAD_FL_SINK (1 << 0)
+#define MEDIA_PAD_FL_SOURCE (1 << 1)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct media_pad_desc {
+ __u32 entity;
+ __u16 index;
+ __u32 flags;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 reserved[2];
+};
+#define MEDIA_LNK_FL_ENABLED (1 << 0)
+#define MEDIA_LNK_FL_IMMUTABLE (1 << 1)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MEDIA_LNK_FL_DYNAMIC (1 << 2)
+struct media_link_desc {
+ struct media_pad_desc source;
+ struct media_pad_desc sink;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 flags;
+ __u32 reserved[2];
+};
+struct media_links_enum {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 entity;
+ struct media_pad_desc __user *pads;
+ struct media_link_desc __user *links;
+ __u32 reserved[4];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+#define MEDIA_IOC_DEVICE_INFO _IOWR('|', 0x00, struct media_device_info)
+#define MEDIA_IOC_ENUM_ENTITIES _IOWR('|', 0x01, struct media_entity_desc)
+#define MEDIA_IOC_ENUM_LINKS _IOWR('|', 0x02, struct media_links_enum)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MEDIA_IOC_SETUP_LINK _IOWR('|', 0x03, struct media_link_desc)
+#endif
+
diff --git a/libc/kernel/common/linux/mfd/msm-adie-codec.h b/libc/kernel/common/linux/mfd/msm-adie-codec.h
new file mode 100644
index 0000000..e4c9e61
--- /dev/null
+++ b/libc/kernel/common/linux/mfd/msm-adie-codec.h
@@ -0,0 +1,110 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ***   To edit the content of this header, modify the corresponding
+ ***   source file (e.g. under external/kernel-headers/original/) then
+ ***   run bionic/libc/kernel/tools/update_all.py
+ ***
+ ***   Any manual change here will be lost the next time this script will
+ ***   be run. You've been warned!
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __LINUX_MFD_MSM_ADIE_CODEC_H
+#define __LINUX_MFD_MSM_ADIE_CODEC_H
+#include <linux/types.h>
+#define ADIE_CODEC_ACTION_ENTRY 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define ADIE_CODEC_ACTION_DELAY_WAIT 0x2
+#define ADIE_CODEC_ACTION_STAGE_REACHED 0x3
+#define ADIE_CODEC_PATH_OFF 0x0050
+#define ADIE_CODEC_DIGITAL_READY 0x0100
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define ADIE_CODEC_DIGITAL_ANALOG_READY 0x1000
+#define ADIE_CODEC_ANALOG_OFF 0x0750
+#define ADIE_CODEC_DIGITAL_OFF 0x0600
+#define ADIE_CODEC_FLASH_IMAGE 0x0001
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define ADIE_CODEC_RX 0
+#define ADIE_CODEC_TX 1
+#define ADIE_CODEC_LB 3
+#define ADIE_CODEC_MAX 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define ADIE_CODEC_PACK_ENTRY(reg, mask, val) ((val)|(mask << 8)|(reg << 16))
+#define ADIE_CODEC_UNPACK_ENTRY(packed, reg, mask, val)   do {   ((reg) = ((packed >> 16) & (0xff)));   ((mask) = ((packed >> 8) & (0xff)));   ((val) = ((packed) & (0xff)));   } while (0);
+struct adie_codec_action_unit {
+ u32 type;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ u32 action;
+};
+struct adie_codec_hwsetting_entry{
+ struct adie_codec_action_unit *actions;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ u32 action_sz;
+ u32 freq_plan;
+ u32 osr;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct adie_codec_dev_profile {
+ u32 path_type;
+ u32 setting_sz;
+ struct adie_codec_hwsetting_entry *settings;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+struct adie_codec_register {
+ u8 reg;
+ u8 mask;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ u8 val;
+};
+struct adie_codec_register_image {
+ struct adie_codec_register *regs;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ u32 img_sz;
+};
+struct adie_codec_path;
+struct adie_codec_anc_data {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ u32 size;
+ u32 writes[];
+};
+struct adie_codec_operations {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ int codec_id;
+ int (*codec_open) (struct adie_codec_dev_profile *profile,
+ struct adie_codec_path **path_pptr);
+ int (*codec_close) (struct adie_codec_path *path_ptr);
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ int (*codec_setpath) (struct adie_codec_path *path_ptr,
+ u32 freq_plan, u32 osr);
+ int (*codec_proceed_stage) (struct adie_codec_path *path_ptr,
+ u32 state);
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ u32 (*codec_freq_supported) (struct adie_codec_dev_profile *profile,
+ u32 requested_freq);
+ int (*codec_enable_sidetone) (struct adie_codec_path *rx_path_ptr,
+ u32 enable);
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ int (*codec_enable_anc) (struct adie_codec_path *rx_path_ptr,
+ u32 enable, struct adie_codec_anc_data *calibration_writes);
+ int (*codec_set_device_digital_volume) (
+ struct adie_codec_path *path_ptr,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ u32 num_channels,
+ u32 vol_percentage);
+ int (*codec_set_device_analog_volume) (struct adie_codec_path *path_ptr,
+ u32 num_channels,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ u32 volume);
+ int (*codec_set_master_mode) (struct adie_codec_path *path_ptr,
+ u8 master);
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#endif
+
diff --git a/libc/kernel/common/linux/mfd/timpani-audio.h b/libc/kernel/common/linux/mfd/timpani-audio.h
new file mode 100644
index 0000000..26995f6
--- /dev/null
+++ b/libc/kernel/common/linux/mfd/timpani-audio.h
@@ -0,0 +1,4600 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ***   To edit the content of this header, modify the corresponding
+ ***   source file (e.g. under external/kernel-headers/original/) then
+ ***   run bionic/libc/kernel/tools/update_all.py
+ ***
+ ***   Any manual change here will be lost the next time this script will
+ ***   be run. You've been warned!
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __LINUX_MFD_TIMPANI_AUDIO_H
+#define __LINUX_MFD_TIMPANI_AUDIO_H
+#define TIMPANI_A_MREF (0x3)
+#define TIMPANI_MREF_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_MREF_POR 0xe2
+#define TIMPANI_MREF_S 0
+#define TIMPANI_MREF_M 0xFF
+#define TIMPANI_MREF_MREF_BG_EN_S 7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_MREF_MREF_BG_EN_M 0x80
+#define TIMPANI_MREF_MREF_BG_EN_ENABLE 0x0
+#define TIMPANI_MREF_MREF_BG_EN_DISABLE 0x1
+#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_S 6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_M 0x40
+#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_ENABLE_NORMAL_OP 0x0
+#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_DISABLE 0x1
+#define TIMPANI_MREF_MREF_200K_MODE_EN_S 5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_MREF_MREF_200K_MODE_EN_M 0x20
+#define TIMPANI_MREF_MREF_200K_MODE_EN_ENABLE 0x0
+#define TIMPANI_MREF_MREF_200K_MODE_EN_DISABLE 0x1
+#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_M 0x10
+#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_DISABLE 0x0
+#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_ENABLE 0x1
+#define TIMPANI_MREF_MREF_100UA_CUR_CONN_S 3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_MREF_MREF_100UA_CUR_CONN_M 0x8
+#define TIMPANI_MREF_MREF_100UA_CUR_CONN_ON_CHIP_RESISTOR_NORMAL_OP 0x0
+#define TIMPANI_MREF_MREF_100UA_CUR_CONN_ATEST 0x1
+#define TIMPANI_MREF_MREF_PTAT_CURRENT_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_MREF_MREF_PTAT_CURRENT_M 0x4
+#define TIMPANI_MREF_MREF_PTAT_CURRENT_V_10UA_PTAT_NORMAL_OP 0x0
+#define TIMPANI_MREF_MREF_PTAT_CURRENT_V_5UA_PTAT_BIAS_CURRENT 0x1
+#define TIMPANI_MREF_MREF_400K_MODE_EN_S 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_MREF_MREF_400K_MODE_EN_M 0x2
+#define TIMPANI_MREF_MREF_400K_MODE_EN_ENABLE 0x0
+#define TIMPANI_MREF_MREF_400K_MODE_EN_DISABLE 0x1
+#define TIMPANI_MREF_RESERVED_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_MREF_RESERVED_M 0x1
+#define TIMPANI_A_CDAC_IDAC_REF_CUR (0x4)
+#define TIMPANI_CDAC_IDAC_REF_CUR_RWC "RW"
+#define TIMPANI_CDAC_IDAC_REF_CUR_POR 0x8c
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_IDAC_REF_CUR_S 0
+#define TIMPANI_CDAC_IDAC_REF_CUR_M 0xFF
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_S 5
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_M 0xE0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_4UA 0x0
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_6UA 0x1
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_8UA 0x2
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_9UA 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_10UA_NORMAL_OP 0x4
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_11UA 0x5
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_13UA 0x6
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_15UA 0x7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_S 2
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_M 0x1C
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_8_5UA 0x0
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_9_0UA 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_9_5UA 0x2
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_10_0UA_NORMAL_OP 0x3
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_10_5UA 0x4
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_11_0UA 0x5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_11_5UA 0x6
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_12_0UA 0x7
+#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_S 0
+#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_M 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_2UA 0x0
+#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_3UA 0x1
+#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_5UA_NORMAL_OP 0x2
+#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_8UA 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_TXADC12_REF_CURR (0x5)
+#define TIMPANI_TXADC12_REF_CURR_RWC "RW"
+#define TIMPANI_TXADC12_REF_CURR_POR 0xa0
+#define TIMPANI_TXADC12_REF_CURR_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC12_REF_CURR_M 0xFF
+#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_S 6
+#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_M 0xC0
+#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_50UA 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_45UA 0x1
+#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_40UA_NORMAL_OP 0x2
+#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_35UA 0x3
+#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_M 0x30
+#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_50UA 0x0
+#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_45UA 0x1
+#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_40UA_NORMAL_OP 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_35UA 0x3
+#define TIMPANI_TXADC12_REF_CURR_RESERVED_S 0
+#define TIMPANI_TXADC12_REF_CURR_RESERVED_M 0xF
+#define TIMPANI_A_TXADC3_EN (0x9)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC3_EN_RWC "RW"
+#define TIMPANI_TXADC3_EN_POR 0
+#define TIMPANI_TXADC3_EN_S 0
+#define TIMPANI_TXADC3_EN_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_S 7
+#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_M 0x80
+#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_DISABLE 0x0
+#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_ENABLE 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_S 6
+#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_M 0x40
+#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0
+#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_S 5
+#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_M 0x20
+#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_DISABLE 0x0
+#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_ENABLE 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_S 4
+#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_M 0x10
+#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_DISABLE 0x0
+#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_ENABLE 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_S 3
+#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_M 0x8
+#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_DISABLE 0x0
+#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_ENABLE 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_S 2
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_M 0x4
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_DISABLE 0x0
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_ENABLE 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_S 1
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_M 0x2
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_DISABLE 0x0
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_ENABLE 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC3_EN_RESERVED_S 0
+#define TIMPANI_TXADC3_EN_RESERVED_M 0x1
+#define TIMPANI_A_TXADC4_EN (0xA)
+#define TIMPANI_TXADC4_EN_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC4_EN_POR 0
+#define TIMPANI_TXADC4_EN_S 0
+#define TIMPANI_TXADC4_EN_M 0xFF
+#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_S 7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_M 0x80
+#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_DISABLE 0x0
+#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_ENABLE 0x1
+#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_S 6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_M 0x40
+#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0
+#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1
+#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_S 5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_M 0x20
+#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_DISABLE 0x0
+#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_ENABLE 0x1
+#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_M 0x10
+#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_DISABLE 0x0
+#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_ENABLE 0x1
+#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_S 3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_M 0x8
+#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_DISABLE 0x0
+#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_ENABLE 0x1
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_M 0x4
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_DISABLE 0x0
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_ENABLE 0x1
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_S 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_M 0x2
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_DISABLE 0x0
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_ENABLE 0x1
+#define TIMPANI_TXADC4_EN_RESERVED_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC4_EN_RESERVED_M 0x1
+#define TIMPANI_A_CODEC_TXADC_STATUS_REGISTER_1 (0xB)
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RWC "R"
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_S 0
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_M 0xFF
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC1_DEM_ERROR_S 7
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC1_DEM_ERROR_M 0x80
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC2_DEM_ERROR_S 6
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC2_DEM_ERROR_M 0x40
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC3_DEM_ERROR_S 5
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC3_DEM_ERROR_M 0x20
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC4_DEM_ERROR_S 4
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC4_DEM_ERROR_M 0x10
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RESERVED_S 0
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RESERVED_M 0xF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_TXFE1 (0xD)
+#define TIMPANI_TXFE1_RWC "RW"
+#define TIMPANI_TXFE1_POR 0
+#define TIMPANI_TXFE1_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE1_M 0xFF
+#define TIMPANI_TXFE1_TXFE1_EN_S 7
+#define TIMPANI_TXFE1_TXFE1_EN_M 0x80
+#define TIMPANI_TXFE1_TXFE1_EN_DISABLE 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE1_TXFE1_EN_ENABLE 0x1
+#define TIMPANI_TXFE1_TXFE1_GAIN_S 5
+#define TIMPANI_TXFE1_TXFE1_GAIN_M 0x60
+#define TIMPANI_TXFE1_TXFE1_GAIN_V_0DB 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE1_TXFE1_GAIN_V_4_5DB 0x1
+#define TIMPANI_TXFE1_TXFE1_GAIN_V_24DB_1 0x2
+#define TIMPANI_TXFE1_TXFE1_GAIN_V_24DB_2 0x3
+#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_M 0x10
+#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_CONNECT 0x1
+#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_S 3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_M 0x8
+#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_CONNECT 0x1
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_M 0x4
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_CONNECT 0x1
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_S 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_M 0x2
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_CONNECT 0x1
+#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_M 0x1
+#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_CONNECT 0x1
+#define TIMPANI_A_TXFE2 (0xE)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE2_RWC "RW"
+#define TIMPANI_TXFE2_POR 0
+#define TIMPANI_TXFE2_S 0
+#define TIMPANI_TXFE2_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE2_TXFE2_EN_S 7
+#define TIMPANI_TXFE2_TXFE2_EN_M 0x80
+#define TIMPANI_TXFE2_TXFE2_EN_DISABLE 0x0
+#define TIMPANI_TXFE2_TXFE2_EN_ENABLE 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE2_TXFE2_GAIN_S 5
+#define TIMPANI_TXFE2_TXFE2_GAIN_M 0x60
+#define TIMPANI_TXFE2_TXFE2_GAIN_V_0DB 0x0
+#define TIMPANI_TXFE2_TXFE2_GAIN_V_4_5DB 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE2_TXFE2_GAIN_V_24DB_1 0x2
+#define TIMPANI_TXFE2_TXFE2_GAIN_V_24DB_2 0x3
+#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_S 4
+#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_M 0x10
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_CONNECT 0x1
+#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_S 3
+#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_M 0x8
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_CONNECT 0x1
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_S 2
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_M 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_CONNECT 0x1
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_S 1
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_M 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_CONNECT 0x1
+#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_S 0
+#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_M 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_CONNECT 0x1
+#define TIMPANI_A_TXFE12_ATEST (0xF)
+#define TIMPANI_TXFE12_ATEST_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE12_ATEST_POR 0
+#define TIMPANI_TXFE12_ATEST_S 0
+#define TIMPANI_TXFE12_ATEST_M 0xFF
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_S 7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_M 0x80
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_DISABLE 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_ENABLE 0x1
+#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_S 6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_M 0x40
+#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_DISABLE 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_ENABLE 0x1
+#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_S 5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_M 0x20
+#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_CONNECT 0x1
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_M 0x10
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_CONNECT 0x1
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_S 3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_M 0x8
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_DISABLE 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_ENABLE 0x1
+#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_M 0x4
+#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_DISABLE 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_ENABLE 0x1
+#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_S 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_M 0x2
+#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_CONNECT 0x1
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_M 0x1
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_CONNECT 0x1
+#define TIMPANI_A_TXFE_CLT (0x10)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE_CLT_RWC "RW"
+#define TIMPANI_TXFE_CLT_POR 0x68
+#define TIMPANI_TXFE_CLT_S 0
+#define TIMPANI_TXFE_CLT_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_S 5
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_M 0xE0
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_125V 0x0
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_100V 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_075V 0x2
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_050V_NORMAL_OP 0x3
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_025V 0x4
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_000V 0x5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_0_975V 0x6
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_0_950V 0x7
+#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_S 3
+#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_M 0x18
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_3UA 0x0
+#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_4UA_NORMAL_OP 0x1
+#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_6UA 0x2
+#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_8UA 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE_CLT_RESERVED_S 0
+#define TIMPANI_TXFE_CLT_RESERVED_M 0x7
+#define TIMPANI_A_TXADC1_EN (0x11)
+#define TIMPANI_TXADC1_EN_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC1_EN_POR 0
+#define TIMPANI_TXADC1_EN_S 0
+#define TIMPANI_TXADC1_EN_M 0xFF
+#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_S 7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_M 0x80
+#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_DISABLE 0x0
+#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_ENABLE 0x1
+#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_S 6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_M 0x40
+#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0
+#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1
+#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_S 5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_M 0x20
+#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_DISABLE 0x0
+#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_ENABLE 0x1
+#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_M 0x10
+#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_DISABLE 0x0
+#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_ENABLE 0x1
+#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_S 3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_M 0x8
+#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_DISABLE 0x0
+#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_ENABLE 0x1
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_M 0x4
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_DISABLE 0x0
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_ENABLE 0x1
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_S 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_M 0x2
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_DISABLE 0x0
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_ENABLE 0x1
+#define TIMPANI_TXADC1_EN_RESERVED_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC1_EN_RESERVED_M 0x1
+#define TIMPANI_A_TXADC2_EN (0x12)
+#define TIMPANI_TXADC2_EN_RWC "RW"
+#define TIMPANI_TXADC2_EN_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC2_EN_S 0
+#define TIMPANI_TXADC2_EN_M 0xFF
+#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_S 7
+#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_M 0x80
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_DISABLE 0x0
+#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_ENABLE 0x1
+#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_S 6
+#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_M 0x40
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0
+#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1
+#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_S 5
+#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_M 0x20
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_DISABLE 0x0
+#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_ENABLE 0x1
+#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_S 4
+#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_M 0x10
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_DISABLE 0x0
+#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_ENABLE 0x1
+#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_S 3
+#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_M 0x8
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_DISABLE 0x0
+#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_ENABLE 0x1
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_S 2
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_M 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_DISABLE 0x0
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_ENABLE 0x1
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_S 1
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_M 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_DISABLE 0x0
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_ENABLE 0x1
+#define TIMPANI_TXADC2_EN_RESERVED_S 0
+#define TIMPANI_TXADC2_EN_RESERVED_M 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_TXADC_CTL (0x13)
+#define TIMPANI_TXADC_CTL_RWC "RW"
+#define TIMPANI_TXADC_CTL_POR 0x58
+#define TIMPANI_TXADC_CTL_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CTL_M 0xFF
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_S 6
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_M 0xC0
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_5UA 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_10UA_NORMAL_OP 0x1
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_15UA 0x2
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_20UA 0x3
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_M 0x30
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_40UA 0x0
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_80UA 0x1
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_120UA 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_160UA 0x3
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_S 2
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_M 0xC
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_8V 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_7V 0x1
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_6V_NORMAL_OP 0x2
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_5V 0x3
+#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_M 0x3
+#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_20UA_NORMAL_OP 0x0
+#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_40UA 0x1
+#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_80UA 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_160UA 0x3
+#define TIMPANI_A_TXADC_CTL2 (0x14)
+#define TIMPANI_TXADC_CTL2_RWC "RW"
+#define TIMPANI_TXADC_CTL2_POR 0x64
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CTL2_S 0
+#define TIMPANI_TXADC_CTL2_M 0xFF
+#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_S 6
+#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_M 0xC0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_333MV 0x0
+#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_356MV_NORMAL_OP 0x1
+#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_378MV 0x2
+#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_400MV 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_S 4
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_M 0x30
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_50UA 0x0
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_100UA 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_200UA_NORMAL_OP 0x2
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_400UA 0x3
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_S 2
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_M 0xC
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_1V 0x0
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_15V_NORMAL_OP 0x1
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_2V 0x2
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_25V 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_S 1
+#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_M 0x2
+#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_V_50UA_NORMAL_OP 0x0
+#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_V_100UA 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_S 0
+#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_M 0x1
+#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_DISABLE 0x0
+#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_ENABLE_NORMAL_OP 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_TXADC_CTL3 (0x15)
+#define TIMPANI_TXADC_CTL3_RWC "RW"
+#define TIMPANI_TXADC_CTL3_POR 0x64
+#define TIMPANI_TXADC_CTL3_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CTL3_M 0xFF
+#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_S 6
+#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_M 0xC0
+#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_85V 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_90V_NORMAL_OP 0x1
+#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_95V 0x2
+#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_1_00V 0x3
+#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_M 0x30
+#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_10UA 0x0
+#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_15UA 0x1
+#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_20UA_NORMAL_OP 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_25UA 0x3
+#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_S 2
+#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_M 0xC
+#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_5UA 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_10UA_NORMAL_OP 0x1
+#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_15UA 0x2
+#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_20UA 0x3
+#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_S 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_M 0x2
+#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_V_5UA_NORMAL_OP 0x0
+#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_V_10UA 0x1
+#define TIMPANI_TXADC_CTL3_RESERVED_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CTL3_RESERVED_M 0x1
+#define TIMPANI_A_TXADC_CHOP_CTL (0x16)
+#define TIMPANI_TXADC_CHOP_CTL_RWC "RW"
+#define TIMPANI_TXADC_CHOP_CTL_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CHOP_CTL_S 0
+#define TIMPANI_TXADC_CHOP_CTL_M 0xFF
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_S 7
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_M 0x80
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_DISABLE 0x0
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_ENABLE 0x1
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_S 4
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_M 0x70
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_2_NORMAL_OP 0x0
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_4 0x1
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_8 0x2
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_16 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_32 0x4
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_64 0x5
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_128 0x6
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_256 0x7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_S 3
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_M 0x8
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_NORMAL_OP 0x0
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_RESET_CHOP 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_S 2
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_M 0x4
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_FALLING_EDGE_CK1 0x0
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_FALLING_EDGE_CK2 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXADC_CHOP_CTL_RESERVED_S 0
+#define TIMPANI_TXADC_CHOP_CTL_RESERVED_M 0x3
+#define TIMPANI_A_TXFE3 (0x18)
+#define TIMPANI_TXFE3_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE3_POR 0
+#define TIMPANI_TXFE3_S 0
+#define TIMPANI_TXFE3_M 0xFF
+#define TIMPANI_TXFE3_TXFE3_EN_S 7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE3_TXFE3_EN_M 0x80
+#define TIMPANI_TXFE3_TXFE3_EN_DISABLE 0x0
+#define TIMPANI_TXFE3_TXFE3_EN_ENABLE 0x1
+#define TIMPANI_TXFE3_TXFE3_GAIN_S 5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE3_TXFE3_GAIN_M 0x60
+#define TIMPANI_TXFE3_TXFE3_GAIN_V_0DB 0x0
+#define TIMPANI_TXFE3_TXFE3_GAIN_V_4_5DB 0x1
+#define TIMPANI_TXFE3_TXFE3_GAIN_V_24DB_1 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE3_TXFE3_GAIN_V_24DB_2 0x3
+#define TIMPANI_TXFE3_RESERVED_1_S 2
+#define TIMPANI_TXFE3_RESERVED_1_M 0x1C
+#define TIMPANI_TXFE3_TXFE3_IN_CONN_S 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE3_TXFE3_IN_CONN_M 0x2
+#define TIMPANI_TXFE3_TXFE3_IN_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE3_TXFE3_IN_CONN_LINE_IN_L 0x1
+#define TIMPANI_TXFE3_RESERVED_2_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE3_RESERVED_2_M 0x1
+#define TIMPANI_A_TXFE4 (0x19)
+#define TIMPANI_TXFE4_RWC "RW"
+#define TIMPANI_TXFE4_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE4_S 0
+#define TIMPANI_TXFE4_M 0xFF
+#define TIMPANI_TXFE4_TXFE4_EN_S 7
+#define TIMPANI_TXFE4_TXFE4_EN_M 0x80
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE4_TXFE4_EN_DISABLE 0x0
+#define TIMPANI_TXFE4_TXFE4_EN_ENABLE 0x1
+#define TIMPANI_TXFE4_TXFE4_GAIN_S 5
+#define TIMPANI_TXFE4_TXFE4_GAIN_M 0x60
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE4_TXFE4_GAIN_V_0DB 0x0
+#define TIMPANI_TXFE4_TXFE4_GAIN_V_4_5DB 0x1
+#define TIMPANI_TXFE4_TXFE4_GAIN_V_24DB_1 0x2
+#define TIMPANI_TXFE4_TXFE4_GAIN_V_24DB_2 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE4_RESERVED_1_S 2
+#define TIMPANI_TXFE4_RESERVED_1_M 0x1C
+#define TIMPANI_TXFE4_TXFE4_IN_CONN_S 1
+#define TIMPANI_TXFE4_TXFE4_IN_CONN_M 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE4_TXFE4_IN_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE4_TXFE4_IN_CONN_LINE_IN_R 0x1
+#define TIMPANI_TXFE4_RESERVED_2_S 0
+#define TIMPANI_TXFE4_RESERVED_2_M 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_TXFE3_ATEST (0x1A)
+#define TIMPANI_TXFE3_ATEST_RWC "RW"
+#define TIMPANI_TXFE3_ATEST_POR 0
+#define TIMPANI_TXFE3_ATEST_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE3_ATEST_M 0xFF
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_S 7
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_M 0x80
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_DISABLE 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_ENABLE 0x1
+#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_S 6
+#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_M 0x40
+#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_DISABLE 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_ENABLE 0x1
+#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_S 5
+#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_M 0x20
+#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_NO_CONNECT 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_CONNECT 0x1
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_S 4
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_M 0x10
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_NO_CONNECT 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_CONNECT 0x1
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_S 3
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_M 0x8
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_DISABLE 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_ENABLE 0x1
+#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_S 2
+#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_M 0x4
+#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_DISABLE 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_ENABLE 0x1
+#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_S 1
+#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_M 0x2
+#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_NO_CONNECT 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_CONNECT 0x1
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_S 0
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_M 0x1
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_NO_CONNECT 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_CONNECT 0x1
+#define TIMPANI_A_TXFE_DIFF_SE (0x1B)
+#define TIMPANI_TXFE_DIFF_SE_RWC "RW"
+#define TIMPANI_TXFE_DIFF_SE_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE_DIFF_SE_S 0
+#define TIMPANI_TXFE_DIFF_SE_M 0xFF
+#define TIMPANI_TXFE_DIFF_SE_RESERVED_S 4
+#define TIMPANI_TXFE_DIFF_SE_RESERVED_M 0xF0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_S 3
+#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_M 0x8
+#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_DIFF 0x0
+#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_SINGLE_ENDED 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_S 2
+#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_M 0x4
+#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_DIFF 0x0
+#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_SINGLE_ENDED 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_S 1
+#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_M 0x2
+#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_DIFF 0x0
+#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_SINGLE_ENDED 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_S 0
+#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_M 0x1
+#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_DIFF 0x0
+#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_SINGLE_ENDED 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDAC_RX_CLK_CTL (0x20)
+#define TIMPANI_CDAC_RX_CLK_CTL_RWC "RW"
+#define TIMPANI_CDAC_RX_CLK_CTL_POR 0x98
+#define TIMPANI_CDAC_RX_CLK_CTL_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_RX_CLK_CTL_M 0xFF
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_S 7
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_M 0x80
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_DISABLE 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_ENABLE_NORMAL_OP 0x1
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_S 6
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_M 0x40
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_DISABLE_NORMAL_OP 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_ENABLE 0x1
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_S 2
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_M 0x3C
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_6NS 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_8_4NS 0x1
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_10_8NS 0x2
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_13_2NS 0x3
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_15_6NS 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_18NS 0x5
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_20_4NS_NORMAL_OP 0x6
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_22_8NS 0x7
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_25_2NS 0x8
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_27_6NS 0x9
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_30NS 0xA
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_32_4NS 0xB
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_34_8NS 0xC
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_37_2NS 0xD
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_39_6NS 0xE
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_42NS 0xF
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_S 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_M 0x2
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_ENABLE 0x1
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_DISABLE 0x0
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_M 0x1
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_CONNECT 0x1
+#define TIMPANI_A_CDAC_BUFF_CTL (0x21)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_BUFF_CTL_RWC "RW"
+#define TIMPANI_CDAC_BUFF_CTL_POR 0x60
+#define TIMPANI_CDAC_BUFF_CTL_S 0
+#define TIMPANI_CDAC_BUFF_CTL_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_S 5
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_M 0xE0
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_40UA 0x0
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_60UA_NORMAL_OP 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_80UA 0x2
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_100UA 0x3
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_120UA 0x4
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_140UA 0x5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_160UA 0x6
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_180UA 0x7
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_S 3
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_M 0x18
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_20UA 0x0
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_30UA_NORMAL_OP 0x1
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_40UA 0x2
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_50UA 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_S 1
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_M 0x6
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_5UA_5UA 0x0
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_5UA_10UA 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_10UA_5UA 0x2
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_10UA_10UA 0x3
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_S 0
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_M 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_CURRENT_TO_VCOM_NORMAL_OP 0x0
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_MASTER_BIAS_TO_VCOM 0x1
+#define TIMPANI_A_CDAC_REF_CTL1 (0x22)
+#define TIMPANI_CDAC_REF_CTL1_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_REF_CTL1_POR 0xe1
+#define TIMPANI_CDAC_REF_CTL1_S 0
+#define TIMPANI_CDAC_REF_CTL1_M 0xFF
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_S 5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_M 0xE0
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_8V 0x0
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_825V 0x1
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_85V 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_9V 0x3
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_925V 0x4
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_95V_NORMAL_OP 0x5
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_975 0x6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_2_0V 0x7
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_S 2
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_M 0x1C
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_1V 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_125V 0x1
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_15V_NORMAL_OP 0x2
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_175V 0x3
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_2V 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_25V 0x5
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_275V 0x6
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_3V 0x7
+#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_M 0x3
+#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_025V 0x0
+#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_05V_NORMAL_OP 0x1
+#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_075V 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_1V 0x3
+#define TIMPANI_A_IDAC_DWA_FIR_CTL (0x23)
+#define TIMPANI_IDAC_DWA_FIR_CTL_RWC "RW"
+#define TIMPANI_IDAC_DWA_FIR_CTL_POR 0x28
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_IDAC_DWA_FIR_CTL_S 0
+#define TIMPANI_IDAC_DWA_FIR_CTL_M 0xFF
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_S 7
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_M 0x80
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_NORMAL_OP 0x0
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_V_150PSEC_REDUCTION 0x1
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_S 4
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_M 0x70
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR0 0x0
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR1 0x1
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR2 0x2
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR3 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR4 0x4
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_S 3
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_M 0x8
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_INTERNAL_NORMAL_OP 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_EXTERNAL 0x0
+#define TIMPANI_IDAC_DWA_FIR_CTL_RESERVED_S 0
+#define TIMPANI_IDAC_DWA_FIR_CTL_RESERVED_M 0x7
+#define TIMPANI_A_CDAC_REF_CTL2 (0x24)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_REF_CTL2_RWC "RW"
+#define TIMPANI_CDAC_REF_CTL2_POR 0xc
+#define TIMPANI_CDAC_REF_CTL2_S 0
+#define TIMPANI_CDAC_REF_CTL2_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_REF_CTL2_RESERVED_1_S 7
+#define TIMPANI_CDAC_REF_CTL2_RESERVED_1_M 0x80
+#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_S 6
+#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_M 0x40
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_DISABLE 0x0
+#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_ENABLE 0x1
+#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_S 5
+#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_M 0x20
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_DISABLE 0x0
+#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_ENABLE 0x1
+#define TIMPANI_CDAC_REF_CTL2_RESERVED_2_S 4
+#define TIMPANI_CDAC_REF_CTL2_RESERVED_2_M 0x10
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_S 2
+#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_M 0xC
+#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_CLK_SYNC_CK11DBAR 0x1
+#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_CLK_SYNC_CK21 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_S 0
+#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_M 0x3
+#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_256 0x0
+#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_128 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_64 0x3
+#define TIMPANI_A_CDAC_CTL1 (0x25)
+#define TIMPANI_CDAC_CTL1_RWC "RW"
+#define TIMPANI_CDAC_CTL1_POR 0xb
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_CTL1_S 0
+#define TIMPANI_CDAC_CTL1_M 0xFF
+#define TIMPANI_CDAC_CTL1_RESERVED_S 6
+#define TIMPANI_CDAC_CTL1_RESERVED_M 0xC0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_S 5
+#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_M 0x20
+#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_DISABLE 0x0
+#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_ENABLE 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_S 4
+#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_M 0x10
+#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_DISABLE 0x0
+#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_ENABLE 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_S 2
+#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_M 0xC
+#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_0V 0x0
+#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_025V 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_05V_NORMAL_OP 0x2
+#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_0752V 0x3
+#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_S 1
+#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_M 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_DISABLE 0x0
+#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_ENABLE_NORMAL_OP 0x1
+#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_S 0
+#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_M 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_INTERNAL_NORMAL_OP 0x1
+#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_EXTERNAL_REGISTER_RESET 0x0
+#define TIMPANI_A_CDAC_CTL2 (0x26)
+#define TIMPANI_CDAC_CTL2_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_CTL2_POR 0xd0
+#define TIMPANI_CDAC_CTL2_S 0
+#define TIMPANI_CDAC_CTL2_M 0xFF
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_S 5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_M 0xE0
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_10UA 0x0
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_8_75UA 0x1
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_7_5UA 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_6_25UA 0x3
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_5UA 0x4
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_3_75UA 0x5
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_2_5UA_NORMAL_OP 0x6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_1_25UA 0x7
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_S 2
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_M 0x1C
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_10UA 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_8_75UA 0x1
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_7_5UA 0x2
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_6_25UA 0x3
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_5UA_NORMAL_OP 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_3_75UA 0x5
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_2_5UA 0x6
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_1_25UA 0x7
+#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_M 0x3
+#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS 0x0
+#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS_BY_8 0x1
+#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS_BY_16 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_IDAC_L_CTL (0x28)
+#define TIMPANI_IDAC_L_CTL_RWC "RW"
+#define TIMPANI_IDAC_L_CTL_POR 0xe
+#define TIMPANI_IDAC_L_CTL_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_IDAC_L_CTL_M 0xFF
+#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_S 7
+#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_M 0x80
+#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_DISABLE 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_ENABLE 0x1
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_S 5
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_M 0x60
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_GROUND 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_IBIAS_X_R_REF 0x1
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_BG_VOLTAGE_NORMAL_OP 0x2
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_VDD_BY_2 0x3
+#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_S 3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_M 0x18
+#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_NEG_1_5DB 0x0
+#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_V_0_0DB_NORMAL_OP 0x1
+#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_POS_1_5DB 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_POS_3_0DB 0x3
+#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_S 2
+#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_M 0x4
+#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_V_30K 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_V_10K_NORMAL_OP 0x1
+#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_S 1
+#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_M 0x2
+#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_ASYNCHRONOUSLY 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_ENABLE_NORMAL_OP 0x1
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_S 0
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_M 0x1
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_REPLICA_BIAS_NORMAL_OP 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_SERVO_LOOP_BIAS 0x1
+#define TIMPANI_A_IDAC_R_CTL (0x29)
+#define TIMPANI_IDAC_R_CTL_RWC "RW"
+#define TIMPANI_IDAC_R_CTL_POR 0xe
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_IDAC_R_CTL_S 0
+#define TIMPANI_IDAC_R_CTL_M 0xFF
+#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_S 7
+#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_M 0x80
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_DISABLED 0x0
+#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_ENABLED 0x1
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_S 5
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_M 0x60
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_GROUND 0x0
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_IBIAS_X_R_REF 0x1
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_BG_VOLTAGE_NORMAL_OP 0x2
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_VDD_BY_2 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_S 3
+#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_M 0x18
+#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_NEG_1_5DB 0x0
+#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_V_0_0DB_NORMAL_OP 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_POS_1_5DB 0x2
+#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_POS_3_0DB 0x3
+#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_S 2
+#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_M 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_V_30K 0x0
+#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_V_10K_NORMAL_OP 0x1
+#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_S 1
+#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_M 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_ASYNCHRONOUSLY 0x0
+#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_ENABLE_NORMAL_OP 0x1
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_S 0
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_M 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_REPLICA_BIAS_NORMAL_OP 0x0
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_SERVO_LOOP_BIAS 0x1
+#define TIMPANI_A_PA_MASTER_BIAS (0x2D)
+#define TIMPANI_PA_MASTER_BIAS_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_MASTER_BIAS_POR 0x6f
+#define TIMPANI_PA_MASTER_BIAS_S 0
+#define TIMPANI_PA_MASTER_BIAS_M 0xFF
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_S 5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_M 0xE0
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_17_5UA 0x0
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_15_0UA 0x1
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_12_5UA 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_10_0UA 0x3
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_7_5UA 0x4
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_5_0UA 0x5
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_2_5UA 0x6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_0_0UA 0x7
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_S 2
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_M 0x1C
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_17_5UA 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_15_0UA 0x1
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_12_5UA 0x2
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_10_0UA 0x3
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_7_5UA 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_5_0UA 0x5
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_2_5UA 0x6
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_0_0UA 0x7
+#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_M 0x3
+#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_6_25UA 0x0
+#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_5_0UA 0x1
+#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_3_75UA 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_2_5UA 0x3
+#define TIMPANI_A_PA_CLASSD_BIAS (0x2E)
+#define TIMPANI_PA_CLASSD_BIAS_RWC "RW"
+#define TIMPANI_PA_CLASSD_BIAS_POR 0x55
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_BIAS_S 0
+#define TIMPANI_PA_CLASSD_BIAS_M 0xFF
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_S 6
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_M 0xC0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_6_25UA 0x0
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_5_0UA 0x1
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_3_75UA 0x2
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_2_5UA 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_S 4
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_M 0x30
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_6_25UA 0x0
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_5_0U 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_3_75UA 0x2
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_2_5UA 0x3
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_S 2
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_M 0xC
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_6_25UA 0x0
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_5_0UA 0x1
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_3_75UA 0x2
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_2_5UA 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_S 0
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_M 0x3
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_6_25UA 0x0
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_5_0UA 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_3_75UA 0x2
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_2_5UA 0x3
+#define TIMPANI_A_AUXPGA_CUR (0x2F)
+#define TIMPANI_AUXPGA_CUR_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_CUR_POR 0x44
+#define TIMPANI_AUXPGA_CUR_S 0
+#define TIMPANI_AUXPGA_CUR_M 0xFF
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_M 0xF0
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0UA 0x0
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_3125UA 0x1
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_625UA 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_9375UA 0x3
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_25UA 0x4
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_5625UA 0x5
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_875UA 0x6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_1875UA 0x7
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_5UA 0x8
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_8125UA 0x9
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_125UA 0xA
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_4375UA 0xB
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_75UA 0xC
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_0625UA 0xD
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_375UA 0xE
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_6875UA 0xF
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_S 0
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_M 0xF
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0UA 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_3125UA 0x1
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_625UA 0x2
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_9375UA 0x3
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_25UA 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_5625UA 0x5
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_875UA 0x6
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_1875UA 0x7
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_5UA 0x8
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_8125UA 0x9
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_125UA 0xA
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_4375UA 0xB
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_75UA 0xC
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_0625UA 0xD
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_375UA 0xE
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_6875UA 0xF
+#define TIMPANI_A_AUXPGA_CM (0x30)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_CM_RWC "RW"
+#define TIMPANI_AUXPGA_CM_POR 0x92
+#define TIMPANI_AUXPGA_CM_S 0
+#define TIMPANI_AUXPGA_CM_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_S 5
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_M 0xE0
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_7_5UA 0x0
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_7_925UA 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_8_75UA 0x2
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_9_375UA 0x3
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_10UA 0x4
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_10_625UA 0x5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_11_25UA 0x6
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_11_875UA 0x7
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_S 2
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_M 0x1C
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_7_5UA 0x0
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_7_925UA 0x1
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_8_75UA 0x2
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_9_375UA 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_10UA 0x4
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_10_625UA 0x5
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_11_25UA 0x6
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_11_875UA 0x7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_S 1
+#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_M 0x2
+#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_VCMI_TO_R2R_CM 0x1
+#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_R2R_CM_FLOATING 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_S 0
+#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_M 0x1
+#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_GEN_VCM_LOCALLY 0x1
+#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_BG_VCM 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_PA_HPH_EARPA_MSTB_EN (0x31)
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_RWC "RW"
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_POR 0x4
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_M 0xFF
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_S 7
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_M 0x80
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_ENABLE 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_DISABLE 0x0
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_S 6
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_M 0x40
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_ENABLE 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_DISABLE 0x0
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_S 5
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_M 0x20
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_ENABLE 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_DISABLE 0x0
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_S 4
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_M 0x10
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_ENABLE 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_DISABLE 0x0
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_S 3
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_M 0x8
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_ENABLE 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_DISABLE 0x0
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_S 2
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_M 0x4
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_CAPLESS 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_LEGACY 0x0
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_S 1
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_M 0x2
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_ENABLE 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_DISABLE 0x0
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_S 0
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_M 0x1
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_ENABLE 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_DISABLE 0x0
+#define TIMPANI_A_PA_LINE_AUXO_EN (0x32)
+#define TIMPANI_PA_LINE_AUXO_EN_RWC "RW"
+#define TIMPANI_PA_LINE_AUXO_EN_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_AUXO_EN_S 0
+#define TIMPANI_PA_LINE_AUXO_EN_M 0xFF
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_S 7
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_M 0x80
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_DISABLE 0x0
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_S 6
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_M 0x40
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_DISABLE 0x0
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_S 5
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_M 0x20
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_DISABLE 0x0
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_S 4
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_M 0x10
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_DISABLE 0x0
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_S 3
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_M 0x8
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_DISABLE 0x0
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_S 2
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_M 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_DISABLE 0x0
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_S 1
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_M 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_DISABLE 0x0
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_S 0
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_M 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_DISABLE 0x0
+#define TIMPANI_A_PA_CLASSD_AUXPGA_EN (0x33)
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_POR 0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_S 0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_M 0xFF
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_S 7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_M 0x80
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_MUTE 0x1
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_UNMUTE 0x0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_S 6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_M 0x40
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_MUTE 0x1
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_UNMUTE 0x0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_S 5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_M 0x20
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_ENABLE 0x1
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_M 0x10
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_ENABLE 0x1
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_S 3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_M 0x8
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_ENABLE 0x1
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_M 0x4
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_ENABLE 0x1
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_S 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_M 0x2
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_ENABLE 0x1
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_M 0x1
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_ENABLE 0x1
+#define TIMPANI_A_PA_LINE_L_GAIN (0x34)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_L_GAIN_RWC "RW"
+#define TIMPANI_PA_LINE_L_GAIN_POR 0xac
+#define TIMPANI_PA_LINE_L_GAIN_S 0
+#define TIMPANI_PA_LINE_L_GAIN_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_S 2
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_M 0xFC
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_POS_1_5 0x0
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_POS_0_0 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_1_5 0x2
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_3_0 0x3
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_4_5 0x4
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_6_0 0x5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_7_5 0x6
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_9_0 0x7
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_10_5 0x8
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_12_0 0x9
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_13_5 0xA
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_15_0 0xB
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_16_5 0xC
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_18_0 0xD
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_19_5 0xE
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_21_0 0xF
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_22_5 0x10
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_24_0 0x11
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_25_5 0x12
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_27_0 0x13
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_28_5 0x14
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_30_0 0x15
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_31_5 0x16
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_33_0 0x17
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_34_5 0x18
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_36_0 0x19
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_37_5 0x1A
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_39_0 0x1B
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_40_5 0x1C
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_42_0 0x1D
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_43_5 0x1E
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_45_0 0x1F
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_46_5 0x20
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_48_0 0x21
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_49_5 0x22
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_51_0 0x23
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_52_5 0x24
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_54_0 0x25
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_55_5 0x26
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_57_0 0x27
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_58_5 0x28
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_60_0 0x29
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_61_5 0x2A
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_63_0 0x2B
+#define TIMPANI_PA_LINE_L_GAIN_RESERVED_S 0
+#define TIMPANI_PA_LINE_L_GAIN_RESERVED_M 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_PA_LINE_R_GAIN (0x35)
+#define TIMPANI_PA_LINE_R_GAIN_RWC "RW"
+#define TIMPANI_PA_LINE_R_GAIN_POR 0xac
+#define TIMPANI_PA_LINE_R_GAIN_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_R_GAIN_M 0xFF
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_S 2
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_M 0xFC
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_POS_1_5 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_POS_0_0 0x1
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_1_5 0x2
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_3_0 0x3
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_4_5 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_6_0 0x5
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_7_5 0x6
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_9_0 0x7
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_10_5 0x8
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_12_0 0x9
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_13_5 0xA
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_15_0 0xB
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_16_5 0xC
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_18_0 0xD
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_19_5 0xE
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_21_0 0xF
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_22_5 0x10
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_24_0 0x11
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_25_5 0x12
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_27_0 0x13
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_28_5 0x14
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_30_0 0x15
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_31_5 0x16
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_33_0 0x17
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_34_5 0x18
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_36_0 0x19
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_37_5 0x1A
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_39_0 0x1B
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_40_5 0x1C
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_42_0 0x1D
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_43_5 0x1E
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_45_0 0x1F
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_46_5 0x20
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_48_0 0x21
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_49_5 0x22
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_51_0 0x23
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_52_5 0x24
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_54_0 0x25
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_55_5 0x26
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_57_0 0x27
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_58_5 0x28
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_60_0 0x29
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_61_5 0x2A
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_63_0 0x2B
+#define TIMPANI_PA_LINE_R_GAIN_RESERVED_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_R_GAIN_RESERVED_M 0x3
+#define TIMPANI_A_PA_HPH_L_GAIN (0x36)
+#define TIMPANI_PA_HPH_L_GAIN_RWC "RW"
+#define TIMPANI_PA_HPH_L_GAIN_POR 0xae
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_L_GAIN_S 0
+#define TIMPANI_PA_HPH_L_GAIN_M 0xFF
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_S 2
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_M 0xFC
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_POS_1_5 0x0
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_POS_0_0 0x1
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_1_5 0x2
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_3_0 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_4_5 0x4
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_6_0 0x5
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_7_5 0x6
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_9_0 0x7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_10_5 0x8
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_12_0 0x9
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_13_5 0xA
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_15_0 0xB
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_16_5 0xC
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_18_0 0xD
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_19_5 0xE
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_21_0 0xF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_22_5 0x10
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_24_0 0x11
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_25_5 0x12
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_27_0 0x13
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_28_5 0x14
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_30_0 0x15
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_31_5 0x16
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_33_0 0x17
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_34_5 0x18
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_36_0 0x19
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_37_5 0x1A
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_39_0 0x1B
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_40_5 0x1C
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_42_0 0x1D
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_43_5 0x1E
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_45_0 0x1F
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_46_5 0x20
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_48_0 0x21
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_49_5 0x22
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_51_0 0x23
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_52_5 0x24
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_54_0 0x25
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_55_5 0x26
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_57_0 0x27
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_58_5 0x28
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_60_0 0x29
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_61_5 0x2A
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_63_0 0x2B
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_S 1
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_M 0x2
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_MUTE 0x1
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_UNMUTE 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_L_GAIN_RESERVED_S 0
+#define TIMPANI_PA_HPH_L_GAIN_RESERVED_M 0x1
+#define TIMPANI_A_PA_HPH_R_GAIN (0x37)
+#define TIMPANI_PA_HPH_R_GAIN_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_R_GAIN_POR 0xae
+#define TIMPANI_PA_HPH_R_GAIN_S 0
+#define TIMPANI_PA_HPH_R_GAIN_M 0xFF
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_M 0xFC
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_POS_1_5 0x0
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_POS_0_0 0x1
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_1_5 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_3_0 0x3
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_4_5 0x4
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_6_0 0x5
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_7_5 0x6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_9_0 0x7
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_10_5 0x8
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_12_0 0x9
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_13_5 0xA
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_15_0 0xB
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_16_5 0xC
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_18_0 0xD
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_19_5 0xE
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_21_0 0xF
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_22_5 0x10
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_24_0 0x11
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_25_5 0x12
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_27_0 0x13
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_28_5 0x14
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_30_0 0x15
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_31_5 0x16
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_33_0 0x17
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_34_5 0x18
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_36_0 0x19
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_37_5 0x1A
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_39_0 0x1B
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_40_5 0x1C
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_42_0 0x1D
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_43_5 0x1E
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_45_0 0x1F
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_46_5 0x20
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_48_0 0x21
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_49_5 0x22
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_51_0 0x23
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_52_5 0x24
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_54_0 0x25
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_55_5 0x26
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_57_0 0x27
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_58_5 0x28
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_60_0 0x29
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_61_5 0x2A
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_63_0 0x2B
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_S 1
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_M 0x2
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_MUTE 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_UNMUTE 0x0
+#define TIMPANI_PA_HPH_R_GAIN_RESERVED_S 0
+#define TIMPANI_PA_HPH_R_GAIN_RESERVED_M 0x1
+#define TIMPANI_A_AUXPGA_LR_GAIN (0x38)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_LR_GAIN_RWC "RW"
+#define TIMPANI_AUXPGA_LR_GAIN_POR 0xaa
+#define TIMPANI_AUXPGA_LR_GAIN_S 0
+#define TIMPANI_AUXPGA_LR_GAIN_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_S 4
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_M 0xF0
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_30DB 0x0
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_27DB 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_24DB 0x2
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_21DB 0x3
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_18DB 0x4
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_15DB 0x5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_12DB 0x6
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_9_0DB 0x7
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_6_0DB 0x8
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_3_0DB 0x9
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_0_0DB 0xA
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_3_0DB 0xB
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_6_0DB 0xC
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_9_0DB 0xD
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_12_0DB_1 0xE
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_12_0DB_2 0xF
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_S 0
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_M 0xF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_30DB 0x0
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_27DB 0x1
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_24DB 0x2
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_21DB 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_18DB 0x4
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_15DB 0x5
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_12DB 0x6
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_9_0DB 0x7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_6_0DB 0x8
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_3_0DB 0x9
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_0_0DB 0xA
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_3_0DB 0xB
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_6_0DB 0xC
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_9_0DB 0xD
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_12_0DB_1 0xE
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_12_0DB_2 0xF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_PA_AUXO_EARPA_CONN (0x39)
+#define TIMPANI_PA_AUXO_EARPA_CONN_RWC "RW"
+#define TIMPANI_PA_AUXO_EARPA_CONN_POR 0
+#define TIMPANI_PA_AUXO_EARPA_CONN_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_AUXO_EARPA_CONN_M 0xFF
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_S 7
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_M 0x80
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_NO_CONNECT 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_CONNECT 0x1
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_S 6
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_M 0x40
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_NO_CONNECT 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_CONNECT 0x1
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_S 5
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_M 0x20
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_NO_CONNECT 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_CONNECT 0x1
+#define TIMPANI_PA_AUXO_EARPA_CONN_RESERVED_S 4
+#define TIMPANI_PA_AUXO_EARPA_CONN_RESERVED_M 0x10
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_S 3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_M 0x8
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_V_3_52DB 0x1
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_V_2_02DB 0x0
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_M 0x4
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_CONNECT 0x1
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_S 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_M 0x2
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_CONNECT 0x1
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_M 0x1
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_CONNECT 0x1
+#define TIMPANI_A_PA_LINE_ST_CONN (0x3A)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_ST_CONN_RWC "RW"
+#define TIMPANI_PA_LINE_ST_CONN_POR 0
+#define TIMPANI_PA_LINE_ST_CONN_S 0
+#define TIMPANI_PA_LINE_ST_CONN_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_S 7
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_M 0x80
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_CONNECT 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_S 6
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_M 0x40
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_CONNECT 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_S 5
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_M 0x20
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_CONNECT 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_S 4
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_M 0x10
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_CONNECT 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_S 3
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_M 0x8
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_CONNECT 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_S 2
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_M 0x4
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_CONNECT 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_S 0
+#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_M 0x3
+#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_NONE 0x0
+#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_1_25UA 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_2_5UA 0x2
+#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_3_75UA 0x3
+#define TIMPANI_A_PA_LINE_MONO_CONN (0x3B)
+#define TIMPANI_PA_LINE_MONO_CONN_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_MONO_CONN_POR 0
+#define TIMPANI_PA_LINE_MONO_CONN_S 0
+#define TIMPANI_PA_LINE_MONO_CONN_M 0xFF
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_S 7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_M 0x80
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_CONNECT 0x1
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_S 6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_M 0x40
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_CONNECT 0x1
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_S 5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_M 0x20
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_CONNECT 0x1
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_M 0x10
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_CONNECT 0x1
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_S 3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_M 0x8
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_CONNECT 0x1
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_M 0x4
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_CONNECT 0x1
+#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_M 0x3
+#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_NONE 0x0
+#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_1_25UA 0x1
+#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_2_5UA 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_3_75UA 0x3
+#define TIMPANI_A_PA_HPH_ST_CONN (0x3C)
+#define TIMPANI_PA_HPH_ST_CONN_RWC "RW"
+#define TIMPANI_PA_HPH_ST_CONN_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_ST_CONN_S 0
+#define TIMPANI_PA_HPH_ST_CONN_M 0xFF
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_S 7
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_M 0x80
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_CONNECT 0x1
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_S 6
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_M 0x40
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_CONNECT 0x1
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_S 5
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_M 0x20
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_CONNECT 0x1
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_S 4
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_M 0x10
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_CONNECT 0x1
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_S 3
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_M 0x8
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_CONNECT 0x1
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_S 2
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_M 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_CONNECT 0x1
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_S 1
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_M 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_DISABLE 0x1
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_ENABLE 0x0
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_S 0
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_M 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_DISABLE 0x1
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_ENABLE 0x0
+#define TIMPANI_A_PA_HPH_MONO_CONN (0x3D)
+#define TIMPANI_PA_HPH_MONO_CONN_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_MONO_CONN_POR 0
+#define TIMPANI_PA_HPH_MONO_CONN_S 0
+#define TIMPANI_PA_HPH_MONO_CONN_M 0xFF
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_S 7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_M 0x80
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_CONNECT 0x1
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_S 6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_M 0x40
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_CONNECT 0x1
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_S 5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_M 0x20
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_CONNECT 0x1
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_M 0x10
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_CONNECT 0x1
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_S 3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_M 0x8
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_CONNECT 0x1
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_M 0x4
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_CONNECT 0x1
+#define TIMPANI_PA_HPH_MONO_CONN_RESERVED_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_MONO_CONN_RESERVED_M 0x3
+#define TIMPANI_A_PA_CLASSD_CONN (0x3E)
+#define TIMPANI_PA_CLASSD_CONN_RWC "RW"
+#define TIMPANI_PA_CLASSD_CONN_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_CONN_S 0
+#define TIMPANI_PA_CLASSD_CONN_M 0xFF
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_S 7
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_M 0x80
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_CONNECT 0x1
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_S 6
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_M 0x40
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_CONNECT 0x1
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_S 5
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_M 0x20
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_CONNECT 0x1
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_S 4
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_M 0x10
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_MONO_DIFF 0x1
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_STEREO 0x0
+#define TIMPANI_PA_CLASSD_CONN_RESERVED_S 0
+#define TIMPANI_PA_CLASSD_CONN_RESERVED_M 0xF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_PA_CNP_CTL (0x3F)
+#define TIMPANI_PA_CNP_CTL_RWC "RW"
+#define TIMPANI_PA_CNP_CTL_POR 0x07
+#define TIMPANI_PA_CNP_CTL_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CNP_CTL_M 0xFF
+#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_S 6
+#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_M 0xC0
+#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_1_75_NA 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_3_5_NA_NORMAL_OP 0x1
+#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_5_25_NA 0x2
+#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_10_NA 0x3
+#define TIMPANI_PA_CNP_CTL_RESERVED_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CNP_CTL_RESERVED_M 0x30
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_S 3
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_M 0x8
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_DISABLE 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_ENABLE 0x1
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_S 0
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_M 0x7
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_220_V 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_243_V 0x1
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_266_V 0x2
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_290_V 0x3
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_341_V 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_339_V 0x5
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_365_V 0x6
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_391_V 0x7
+#define TIMPANI_A_PA_CLASSD_L_CTL (0x40)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_CTL_RWC "RW"
+#define TIMPANI_PA_CLASSD_L_CTL_POR 0x08
+#define TIMPANI_PA_CLASSD_L_CTL_S 0
+#define TIMPANI_PA_CLASSD_L_CTL_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_CTL_RESERVED_S 6
+#define TIMPANI_PA_CLASSD_L_CTL_RESERVED_M 0xC0
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_S 5
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_M 0x20
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_RESET_PA_LOGIC 0x1
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_S 4
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_M 0x10
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_DISCHARGE_CAPS 0x1
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_S 2
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_M 0xC
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_GND 0x0
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_IBIAS_X_R_REF 0x1
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_BG_VOLTAGE 0x2
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_VDD_BY_2 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_S 1
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_M 0x2
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_PA_OUT_TO_VDD 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_S 0
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_M 0x1
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_PA_OUT_TO_GND 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_PA_CLASSD_R_CTL (0x41)
+#define TIMPANI_PA_CLASSD_R_CTL_RWC "RW"
+#define TIMPANI_PA_CLASSD_R_CTL_POR 0x08
+#define TIMPANI_PA_CLASSD_R_CTL_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_CTL_M 0xFF
+#define TIMPANI_PA_CLASSD_R_CTL_RESERVED_S 6
+#define TIMPANI_PA_CLASSD_R_CTL_RESERVED_M 0xC0
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_S 5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_M 0x20
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_RESET_PA_LOGIC 0x1
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_M 0x10
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_DISCHARGE_CAPS 0x1
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_M 0xC
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_GND 0x0
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_IBIAS_X_R_REF 0x1
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_BG_VOLTAGE 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_VDD_BY_2 0x3
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_S 1
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_M 0x2
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_NORMAL_OP 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_PA_OUT_TO_VDD 0x1
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_S 0
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_M 0x1
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_NORMAL_OP 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_PA_OUT_TO_GND 0x1
+#define TIMPANI_A_PA_CLASSD_INT2_CTL (0x42)
+#define TIMPANI_PA_CLASSD_INT2_CTL_RWC "RW"
+#define TIMPANI_PA_CLASSD_INT2_CTL_POR 0xb0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_INT2_CTL_S 0
+#define TIMPANI_PA_CLASSD_INT2_CTL_M 0xFF
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_S 6
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_M 0xC0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_5_0PF 0x0
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_7_5PF 0x1
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_10PF 0x2
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_15PF 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_S 4
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_M 0x30
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_100K 0x0
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_150K 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_175K 0x2
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_200K 0x3
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_S 2
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_M 0xC
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_5_0PF 0x0
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_7_5PF 0x1
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_10PF 0x2
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_15PF 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_S 0
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_M 0x3
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_100K 0x0
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_150K 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_175K 0x2
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_200K 0x3
+#define TIMPANI_A_PA_HPH_L_OCP_CLK_CTL (0x43)
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_POR 0xf2
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_S 0
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_M 0xFF
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_S 7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_M 0x80
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_DISABLE 0x0
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_S 6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_M 0x40
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_DISABLE 0x0
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_M 0x30
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV2 0x0
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV4 0x1
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV6 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV8 0x3
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_S 3
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_M 0x8
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_CLK_FROM_CH_2 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_CLK_FROM_CH_1 0x0
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_S 2
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_M 0x4
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_ENABLE 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_DISABLE 0x0
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_S 0
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_M 0x3
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_4 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_8 0x1
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_12 0x2
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_16 0x3
+#define TIMPANI_A_PA_CLASSD_L_SW_CTL (0x44)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_SW_CTL_RWC "RW"
+#define TIMPANI_PA_CLASSD_L_SW_CTL_POR 0x37
+#define TIMPANI_PA_CLASSD_L_SW_CTL_S 0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_S 6
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_M 0xC0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_1 0x0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_2 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_3 0x2
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_4 0x3
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_S 4
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_M 0x30
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_3_OF_6_UNITS 0x0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_4_OF_6_UNITS 0x1
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_5_OF_6_UNITS 0x2
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_6_OF_6_UNITS 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_SW_CTL_RESERVED_S 3
+#define TIMPANI_PA_CLASSD_L_SW_CTL_RESERVED_M 0x8
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_S 2
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_M 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_ENABLE 0x1
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_S 1
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_M 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_ENABLE 0x1
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_S 0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_M 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_POWER_GROUND 0x0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_RST_MIDPOINT 0x1
+#define TIMPANI_A_PA_CLASSD_L_OCP1 (0x45)
+#define TIMPANI_PA_CLASSD_L_OCP1_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_OCP1_POR 0xff
+#define TIMPANI_PA_CLASSD_L_OCP1_S 0
+#define TIMPANI_PA_CLASSD_L_OCP1_M 0xFF
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_S 7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_M 0x80
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_ENABLE 0x1
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_S 6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_M 0x40
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_NEVER_LOCKS 0x0
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_LOCKS 0x1
+#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_M 0x30
+#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_100MA_83_3MA_66_7MA_50MA 0x0
+#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_133MA_111MA_88_7MA_66_7MA 0x1
+#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_166MA_138MA_111MA_83_3MA 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_200MA_166MA_133MA_100MA 0x3
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_S 0
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_M 0xF
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_1 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_2 0x2
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_3 0x3
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_4 0x4
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_5 0x5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_6 0x6
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_7 0x7
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_8 0x8
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_9 0x9
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_10 0xA
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_11 0xB
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_12 0xC
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_13 0xD
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_14 0xE
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_15 0xF
+#define TIMPANI_A_PA_CLASSD_L_OCP2 (0x46)
+#define TIMPANI_PA_CLASSD_L_OCP2_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_OCP2_POR 0x77
+#define TIMPANI_PA_CLASSD_L_OCP2_S 0
+#define TIMPANI_PA_CLASSD_L_OCP2_M 0xFF
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_M 0xF0
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_255 0x0
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_511 0x1
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_767 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1023 0x3
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1279 0x4
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1535 0x5
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1791 0x6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2047 0x7
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2303 0x8
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2559 0x9
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2815 0xA
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3071 0xB
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3327 0xC
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3583 0xD
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3839 0xE
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_4095 0xF
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_S 0
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_M 0xF
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_255 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_511 0x1
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_767 0x2
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1023 0x3
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1279 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1535 0x5
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1791 0x6
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2047 0x7
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2303 0x8
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2559 0x9
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2815 0xA
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3071 0xB
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3327 0xC
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3583 0xD
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3839 0xE
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_4095 0xF
+#define TIMPANI_A_PA_HPH_R_OCP_CLK_CTL (0x47)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_RWC "RW"
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_POR 0xf2
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_S 0
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_S 7
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_M 0x80
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_DISABLE 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_S 6
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_M 0x40
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_DISABLE 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_S 4
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_M 0x30
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV2 0x0
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV4 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV6 0x2
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV8 0x3
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_S 3
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_M 0x8
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_CLK_FROM_CH_2 0x1
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_CLK_FROM_CH_1 0x0
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_S 2
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_M 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_DISABLE 0x0
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_S 0
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_M 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_4 0x0
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_8 0x1
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_12 0x2
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_16 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_PA_CLASSD_R_SW_CTL (0x48)
+#define TIMPANI_PA_CLASSD_R_SW_CTL_RWC "RW"
+#define TIMPANI_PA_CLASSD_R_SW_CTL_POR 0x37
+#define TIMPANI_PA_CLASSD_R_SW_CTL_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_SW_CTL_M 0xFF
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_S 6
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_M 0xC0
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_1 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_2 0x1
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_3 0x2
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_4 0x3
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_M 0x30
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_3_OF_6_UNITS 0x0
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_4_OF_6_UNITS 0x1
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_5_OF_6_UNITS 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_6_OF_6_UNITS 0x3
+#define TIMPANI_PA_CLASSD_R_SW_CTL_RESERVED_S 3
+#define TIMPANI_PA_CLASSD_R_SW_CTL_RESERVED_M 0x8
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_M 0x4
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_ENABLE 0x1
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_S 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_M 0x2
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_ENABLE 0x1
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_M 0x1
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_POWER_GROUND 0x0
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_RST_MIDPOINT 0x1
+#define TIMPANI_A_PA_CLASSD_R_OCP1 (0x49)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_OCP1_RWC "RW"
+#define TIMPANI_PA_CLASSD_R_OCP1_POR 0xff
+#define TIMPANI_PA_CLASSD_R_OCP1_S 0
+#define TIMPANI_PA_CLASSD_R_OCP1_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_S 7
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_M 0x80
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_ENABLE 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_S 6
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_M 0x40
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_NEVER_LOCKS 0x0
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_LOCKS 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_S 4
+#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_M 0x30
+#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_100MA_83_3MA_66_7MA_50MA 0x0
+#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_133MA_111MA_88_7MA_66_7MA 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_166MA_138MA_111MA_83_3MA 0x2
+#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_200MA_166MA_133MA_100MA 0x3
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_S 0
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_M 0xF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_1 0x1
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_2 0x2
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_3 0x3
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_4 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_5 0x5
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_6 0x6
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_7 0x7
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_8 0x8
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_9 0x9
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_10 0xA
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_11 0xB
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_12 0xC
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_13 0xD
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_14 0xE
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_15 0xF
+#define TIMPANI_A_PA_CLASSD_R_OCP2 (0x4A)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_OCP2_RWC "RW"
+#define TIMPANI_PA_CLASSD_R_OCP2_POR 0x77
+#define TIMPANI_PA_CLASSD_R_OCP2_S 0
+#define TIMPANI_PA_CLASSD_R_OCP2_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_S 4
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_M 0xF0
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_255 0x0
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_511 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_767 0x2
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1023 0x3
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1279 0x4
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1535 0x5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1791 0x6
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2047 0x7
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2303 0x8
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2559 0x9
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2815 0xA
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3071 0xB
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3327 0xC
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3583 0xD
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3839 0xE
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_4095 0xF
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_S 0
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_M 0xF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_255 0x0
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_511 0x1
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_767 0x2
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1023 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1279 0x4
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1535 0x5
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1791 0x6
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2047 0x7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2303 0x8
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2559 0x9
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2815 0xA
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3071 0xB
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3327 0xC
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3583 0xD
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3839 0xE
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_4095 0xF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_PA_HPH_CTL1 (0x4B)
+#define TIMPANI_PA_HPH_CTL1_RWC "RW"
+#define TIMPANI_PA_HPH_CTL1_POR 0x44
+#define TIMPANI_PA_HPH_CTL1_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_CTL1_M 0xFF
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_S 4
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_M 0xF0
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_400PER 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_200PER 0x2
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_133PER 0x3
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_100PER 0x4
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_66PER 0x6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_50PER 0x8
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_33PER 0xC
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_S 3
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_M 0x8
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_DISABLE 0x0
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_S 0
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_M 0x7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_300MA 0x0
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_350MA 0x2
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_365MA 0x3
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_150MA 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_190MA 0x6
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_220MA 0x7
+#define TIMPANI_A_PA_HPH_CTL2 (0x4C)
+#define TIMPANI_PA_HPH_CTL2_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_CTL2_POR 0xC8
+#define TIMPANI_PA_HPH_CTL2_S 0
+#define TIMPANI_PA_HPH_CTL2_M 0xFF
+#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_S 7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_M 0x80
+#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_VNEG 0x1
+#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_VSS 0x0
+#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_S 6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_M 0x40
+#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_V_1_5 0x1
+#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_V_2_5 0x0
+#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_S 5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_M 0x20
+#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_DISABLE 0x0
+#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_M 0x10
+#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_DISABLE 0x0
+#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_M 0xC
+#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_GROUND 0x0
+#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_IBIAS_ON_RESISTOR 0x1
+#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_BG 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_AVDD_BY_2 0x3
+#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_S 1
+#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_M 0x2
+#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_DISABLE 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_CTL2_RESERVED_S 0
+#define TIMPANI_PA_HPH_CTL2_RESERVED_M 0x1
+#define TIMPANI_A_PA_LINE_AUXO_CTL (0x4D)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_AUXO_CTL_RWC "RW"
+#define TIMPANI_PA_LINE_AUXO_CTL_POR 0x2
+#define TIMPANI_PA_LINE_AUXO_CTL_S 0
+#define TIMPANI_PA_LINE_AUXO_CTL_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_S 6
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_M 0xC0
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_1_75NA 0x0
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_3_5NA 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_5_25NA 0x2
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_10NA 0x3
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_S 4
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_M 0x30
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_60UA 0x0
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_30UA_1 0x1
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_30UA_2 0x2
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_15UA 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_S 2
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_M 0xC
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_60UA 0x0
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_30UA_1 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_30UA_2 0x2
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_15UA 0x3
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_S 0
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_M 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_VSSA 0x0
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_BG 0x2
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_VDDA_BY_2 0x3
+#define TIMPANI_A_PA_AUXO_EARPA_CTL (0x4E)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_AUXO_EARPA_CTL_RWC "RW"
+#define TIMPANI_PA_AUXO_EARPA_CTL_POR 0xe
+#define TIMPANI_PA_AUXO_EARPA_CTL_S 0
+#define TIMPANI_PA_AUXO_EARPA_CTL_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_AUXO_EARPA_CTL_RESERVED_S 6
+#define TIMPANI_PA_AUXO_EARPA_CTL_RESERVED_M 0xC0
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_S 4
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_M 0x30
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_60UA 0x0
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_30UA 0x1
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_30UA_SAME_AS_01 0x2
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_15UA 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_S 3
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_M 0x8
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_NEG_4_5DB 0x1
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_NEG_3_0DB 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_S 1
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_M 0x6
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_12_5UA 0x0
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_10_0UA 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_7_5UA 0x2
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_5_0UA 0x3
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_S 0
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_M 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_BG 0x1
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_LOCAL_VCM 0x0
+#define TIMPANI_A_PA_EARO_CTL (0x4F)
+#define TIMPANI_PA_EARO_CTL_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_EARO_CTL_POR 0x0
+#define TIMPANI_PA_EARO_CTL_S 0
+#define TIMPANI_PA_EARO_CTL_M 0xFF
+#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_S 7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_M 0x80
+#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_NORMAL_OP 0x0
+#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_CONNECT_INPUTS_TO_GROUND 0x1
+#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_S 6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_M 0x40
+#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_NO_BYPASS 0x0
+#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_BYPASS 0x1
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_S 3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_M 0x38
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_213UA 0x0
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_280UA 0x1
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_408UA_1 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_780UA_1 0x3
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_408UA_2 0x4
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_530UA 0x5
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_780UA_2 0x6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_1480UA 0x7
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_S 0
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_M 0x7
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_213UA 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_280UA 0x1
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_408UA_1 0x2
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_780UA_1 0x3
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_408UA_2 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_530UA 0x5
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_780UA_2 0x6
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_1480UA 0x7
+#define TIMPANI_A_PA_MASTER_BIAS_CUR (0x50)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_MASTER_BIAS_CUR_RWC "RW"
+#define TIMPANI_PA_MASTER_BIAS_CUR_POR 0xea
+#define TIMPANI_PA_MASTER_BIAS_CUR_S 0
+#define TIMPANI_PA_MASTER_BIAS_CUR_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_S 7
+#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_M 0x80
+#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_V_2_5UA 0x1
+#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_V_5UA 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_S 5
+#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_M 0x60
+#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_10UA 0x0
+#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_7_5UA 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_5_0UA 0x2
+#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_2_5UA 0x3
+#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_S 3
+#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_M 0x18
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_6_25UA 0x0
+#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_5_0UA 0x1
+#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_3_75UA 0x2
+#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_2_5UA 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_S 1
+#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_M 0x6
+#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_6_25UA 0x0
+#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_5_0UA 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_3_75UA 0x2
+#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_2_5UA 0x3
+#define TIMPANI_PA_MASTER_BIAS_CUR_RESERVED_S 0
+#define TIMPANI_PA_MASTER_BIAS_CUR_RESERVED_M 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_PA_CLASSD_SC_STATUS (0x51)
+#define TIMPANI_PA_CLASSD_SC_STATUS_RWC "R"
+#define TIMPANI_PA_CLASSD_SC_STATUS_POR 0
+#define TIMPANI_PA_CLASSD_SC_STATUS_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_SC_STATUS_M 0xFF
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_S 7
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_M 0x80
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_NORMAL_OP 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_SC_DET 0x1
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_S 6
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_M 0x40
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_NORMAL_OP 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_POWER_STAGE_OFF 0x1
+#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_1_S 4
+#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_1_M 0x30
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_S 3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_M 0x8
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_SC_DET 0x1
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_M 0x4
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_POWER_STAGE_OFF 0x1
+#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_2_S 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_2_M 0x2
+#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_S 0
+#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_M 0x1
+#define TIMPANI_A_PA_HPH_SC_STATUS (0x52)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_SC_STATUS_RWC "R"
+#define TIMPANI_PA_HPH_SC_STATUS_POR 0
+#define TIMPANI_PA_HPH_SC_STATUS_S 0
+#define TIMPANI_PA_HPH_SC_STATUS_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_S 7
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_M 0x80
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_NORMAL_OP 0x0
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_SC_DET 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_1_S 4
+#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_1_M 0x70
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_S 3
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_M 0x8
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_NORMAL_OP 0x0
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_SC_DET 0x1
+#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_2_S 2
+#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_2_M 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_S 0
+#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_M 0x3
+#define TIMPANI_A_ATEST_EN (0x53)
+#define TIMPANI_ATEST_EN_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_EN_POR 0
+#define TIMPANI_ATEST_EN_S 0
+#define TIMPANI_ATEST_EN_M 0xFF
+#define TIMPANI_ATEST_EN_ATEST_EN_S 7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_EN_ATEST_EN_M 0x80
+#define TIMPANI_ATEST_EN_ATEST_EN_DISABLE 0x0
+#define TIMPANI_ATEST_EN_ATEST_EN_ENABLE 0x1
+#define TIMPANI_ATEST_EN_RESERVED_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_EN_RESERVED_M 0x7F
+#define TIMPANI_A_ATEST_TSHKADC (0x54)
+#define TIMPANI_ATEST_TSHKADC_RWC "RW"
+#define TIMPANI_ATEST_TSHKADC_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_TSHKADC_S 0
+#define TIMPANI_ATEST_TSHKADC_M 0xFF
+#define TIMPANI_ATEST_TSHKADC_RESERVED_S 4
+#define TIMPANI_ATEST_TSHKADC_RESERVED_M 0xF0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_S 2
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_M 0xC
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX1 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX2 0x2
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX3 0x3
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_S 0
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_M 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX1 0x1
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX2 0x2
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX3 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_ATEST_TXADC13 (0x55)
+#define TIMPANI_ATEST_TXADC13_RWC "RW"
+#define TIMPANI_ATEST_TXADC13_POR 0
+#define TIMPANI_ATEST_TXADC13_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_TXADC13_M 0xFF
+#define TIMPANI_ATEST_TXADC13_RESERVED_S 7
+#define TIMPANI_ATEST_TXADC13_RESERVED_M 0x80
+#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_S 6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_M 0x40
+#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_TXADC1 0x0
+#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_TXADC3 0x1
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_S 3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_M 0x38
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_ICMP1_TO_ATEST1 0x1
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_IOTA2_TO_ATEST1 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_IOTA1_TO_ATEST1 0x3
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VICM_TO_ATEST1 0x4
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VTH_P_TO_ATEST1 0x5
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VREFP_TO_ATEST1 0x6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_S 0
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_M 0x7
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_IDACREF_TO_ATEST2 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_IB_10U_TO_ATEST2 0x2
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VREFMID_TO_ATEST2 0x3
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VOCM_TO_ATEST2 0x4
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VTH_N_TO_ATEST2 0x5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VREFN_TO_ATEST2 0x6
+#define TIMPANI_A_ATEST_TXADC24 (0x56)
+#define TIMPANI_ATEST_TXADC24_RWC "RW"
+#define TIMPANI_ATEST_TXADC24_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_TXADC24_S 0
+#define TIMPANI_ATEST_TXADC24_M 0xFF
+#define TIMPANI_ATEST_TXADC24_RESERVED_S 7
+#define TIMPANI_ATEST_TXADC24_RESERVED_M 0x80
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_S 6
+#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_M 0x40
+#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_TXADC1 0x0
+#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_TXADC3 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_S 3
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_M 0x38
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_ICMP1_TO_ATEST1 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_IOTA2_TO_ATEST1 0x2
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_IOTA1_TO_ATEST1 0x3
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VICM_TO_ATEST1 0x4
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VTH_P_TO_ATEST1 0x5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VREFP_TO_ATEST1 0x6
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_S 0
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_M 0x7
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_NO_CONNECT 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_IDACREF_TO_ATEST2 0x1
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_IB_10U_TO_ATEST2 0x2
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VREFMID_TO_ATEST2 0x3
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VOCM_TO_ATEST2 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VTH_N_TO_ATEST2 0x5
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VREFN_TO_ATEST2 0x6
+#define TIMPANI_A_ATEST_AUXPGA (0x57)
+#define TIMPANI_ATEST_AUXPGA_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_AUXPGA_POR 0
+#define TIMPANI_ATEST_AUXPGA_S 0
+#define TIMPANI_ATEST_AUXPGA_M 0xFF
+#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_S 7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_M 0x80
+#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_CONNECT 0x1
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_S 6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_M 0x40
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_CONNECT 0x1
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_S 5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_M 0x20
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_CONNECT 0x1
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_M 0x10
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_CONNECT 0x1
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_S 3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_M 0x8
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_CONNECT 0x1
+#define TIMPANI_ATEST_AUXPGA_RESERVED_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_AUXPGA_RESERVED_M 0x7
+#define TIMPANI_A_ATEST_CDAC (0x58)
+#define TIMPANI_ATEST_CDAC_RWC "RW"
+#define TIMPANI_ATEST_CDAC_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_CDAC_S 0
+#define TIMPANI_ATEST_CDAC_M 0xFF
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_S 7
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_M 0x80
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_CONNECT 0x1
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_S 6
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_M 0x40
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_CONNECT 0x1
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_S 5
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_M 0x20
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_CONNECT 0x1
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_S 4
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_M 0x10
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_CONNECT 0x1
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_S 2
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_M 0xC
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST1 0x1
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST2 0x2
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST3 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_S 0
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_M 0x3
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST1 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST2 0x2
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST3 0x3
+#define TIMPANI_A_ATEST_IDAC (0x59)
+#define TIMPANI_ATEST_IDAC_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_IDAC_POR 0
+#define TIMPANI_ATEST_IDAC_S 0
+#define TIMPANI_ATEST_IDAC_M 0xFF
+#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_S 7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_M 0x80
+#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_RIGHT 0x1
+#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_LEFT 0x0
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_M 0x70
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_IDAC_NEG_OUT 0x7
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_CT_FILTER_POS_OUT 0x6
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_CT_FILTER_IBIAS 0x5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_1 0x4
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_2 0x3
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_3 0x2
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_4 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_5 0x0
+#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_S 3
+#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_M 0x8
+#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_RIGHT 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_LEFT 0x0
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_S 0
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_M 0x7
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_IDAC_POS_OUT 0x7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_CT_FILTER_NEG_OUT 0x6
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_IDAC_IBIAS 0x5
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_1 0x4
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_2 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_3 0x2
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_4 0x1
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_5 0x0
+#define TIMPANI_A_ATEST_PA1 (0x5A)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_PA1_RWC "RW"
+#define TIMPANI_ATEST_PA1_POR 0
+#define TIMPANI_ATEST_PA1_S 0
+#define TIMPANI_ATEST_PA1_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_S 7
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_M 0x80
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_EN 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_S 6
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_M 0x40
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_EN 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_S 5
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_M 0x20
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_EN 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_S 4
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_M 0x10
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_EN 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_S 3
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_M 0x8
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_EN 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_S 2
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_M 0x4
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_EN 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_S 1
+#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_M 0x2
+#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_PASS 0x0
+#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_GATE 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_S 0
+#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_M 0x1
+#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_CONNECT 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_ATEST_CLASSD (0x5B)
+#define TIMPANI_ATEST_CLASSD_RWC "RW"
+#define TIMPANI_ATEST_CLASSD_POR 0
+#define TIMPANI_ATEST_CLASSD_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_CLASSD_M 0xFF
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_S 4
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_M 0xF0
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_NO_CONNECT_1 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_SC_OCP 0x1
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_CDAC_CLK 0x2
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_POS_CDAC 0x3
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_BREAK_BEFORE_MAKE_OUT_CP 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_COMP_OUT 0x5
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_INT2_POS_OUT 0x6
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_INT1_POS_OUT 0x7
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_NO_CONNECT_2 0x8
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_SC_OCP_SIGNAL 0x9
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_CDAC_CLK 0xA
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_POS_CDAC 0xB
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_BREAK_BEFORE_MAKE_OUT_CP 0xC
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_COMP_OUT 0xD
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_INT2_POS_OUT 0xE
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_INT1_POS_OUT 0xF
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_M 0xF
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_NO_CONNECT_1 0x0
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_HI_Z_OCP 0x1
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_OCP_CLOCK 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_NEG_CDAC 0x3
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_BREAK_BEFORE_MAKE_OUT_CN 0x4
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_CM_BUFF_OUT 0x5
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_INT2_NEG_OUT 0x6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_INT1_NEG_OUT 0x7
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_NO_CONNECT_2 0x8
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_HI_Z_OCP 0x9
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_OCP_CLOCK 0xA
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_NEGATIVE_CDAC 0xB
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_BREAK_BEFORE_MAKE_OUT_CN 0xC
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_CM_BUFF_OUT 0xD
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_INTR2_NEG_OUT 0xE
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_INT1_NEG_OUT 0xF
+#define TIMPANI_A_ATEST_LINEO_AUXO (0x5C)
+#define TIMPANI_ATEST_LINEO_AUXO_RWC "RW"
+#define TIMPANI_ATEST_LINEO_AUXO_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_LINEO_AUXO_S 0
+#define TIMPANI_ATEST_LINEO_AUXO_M 0xFF
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_S 7
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_M 0x80
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_DISABLE 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_ENABLE 0x1
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_S 6
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_M 0x40
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_CONNECT 0x1
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_S 5
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_M 0x20
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_EN 0x1
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_S 4
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_M 0x10
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_EN 01
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_S 3
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_M 0x8
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_EN 01
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_S 2
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_M 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_DISABLE 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_EN 0x1
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_S 1
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_M 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_DISABLE 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_EN 0x1
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_S 0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_M 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_DISABLE 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_EN 0x1
+#define TIMPANI_A_CDC_RESET_CTL (0x80)
+#define TIMPANI_CDC_RESET_CTL_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RESET_CTL_POR 0
+#define TIMPANI_CDC_RESET_CTL_S 0
+#define TIMPANI_CDC_RESET_CTL_M 0x7F
+#define TIMPANI_CDC_RESET_CTL_ARB_SOFT_RESET_S 6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RESET_CTL_ARB_SOFT_RESET_M 0x40
+#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_R_S 5
+#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_R_M 0x20
+#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_L_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_L_M 0x10
+#define TIMPANI_CDC_RESET_CTL_RX2_SOFT_RESET_S 3
+#define TIMPANI_CDC_RESET_CTL_RX2_SOFT_RESET_M 0x8
+#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_R_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_R_M 0x4
+#define TIMPANI_CDC_RESET_CTL_RX1_SOFT_RESET_S 1
+#define TIMPANI_CDC_RESET_CTL_RX1_SOFT_RESET_M 0x2
+#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_L_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_L_M 0x1
+#define TIMPANI_A_CDC_RX1_CTL (0x81)
+#define TIMPANI_CDC_RX1_CTL_RWC "RW"
+#define TIMPANI_CDC_RX1_CTL_POR 0xc
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX1_CTL_S 0
+#define TIMPANI_CDC_RX1_CTL_M 0x3F
+#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_R_S 5
+#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_R_M 0x20
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_L_S 4
+#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_L_M 0x10
+#define TIMPANI_CDC_RX1_CTL_RX1_RATE_S 2
+#define TIMPANI_CDC_RX1_CTL_RX1_RATE_M 0xC
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_256 0x3
+#define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_128 0x1
+#define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_64 0x0
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_S 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_M 0x2
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_BR_32 0x1
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_BR_64 0x0
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_M 0x1
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_MASTER 0x1
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_SLAVE 0x0
+#define TIMPANI_A_CDC_TX_I2S_CTL (0x82)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX_I2S_CTL_RWC "RW"
+#define TIMPANI_CDC_TX_I2S_CTL_POR 0xc
+#define TIMPANI_CDC_TX_I2S_CTL_S 0
+#define TIMPANI_CDC_TX_I2S_CTL_M 0x3F
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX_I2S_CTL_TX2_I2S_SD_OE_S 5
+#define TIMPANI_CDC_TX_I2S_CTL_TX2_I2S_SD_OE_M 0x20
+#define TIMPANI_CDC_TX_I2S_CTL_TX1_I2S_SD_OE_S 4
+#define TIMPANI_CDC_TX_I2S_CTL_TX1_I2S_SD_OE_M 0x10
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_S 2
+#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_M 0xC
+#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_256 0x3
+#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_128 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_64 0x0
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_S 1
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_M 0x2
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_BR_32 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_BR_64 0x0
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_S 0
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_M 0x1
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_MASTER 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_SLAVE 0x0
+#define TIMPANI_A_CDC_CH_CTL (0x83)
+#define TIMPANI_CDC_CH_CTL_RWC "RW"
+#define TIMPANI_CDC_CH_CTL_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_CH_CTL_S 0
+#define TIMPANI_CDC_CH_CTL_M 0xFF
+#define TIMPANI_CDC_CH_CTL_TX2_EN_R_S 7
+#define TIMPANI_CDC_CH_CTL_TX2_EN_R_M 0x80
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_CH_CTL_TX2_EN_L_S 6
+#define TIMPANI_CDC_CH_CTL_TX2_EN_L_M 0x40
+#define TIMPANI_CDC_CH_CTL_RX2_EN_R_S 5
+#define TIMPANI_CDC_CH_CTL_RX2_EN_R_M 0x20
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_CH_CTL_RX2_EN_L_S 4
+#define TIMPANI_CDC_CH_CTL_RX2_EN_L_M 0x10
+#define TIMPANI_CDC_CH_CTL_TX1_EN_R_S 3
+#define TIMPANI_CDC_CH_CTL_TX1_EN_R_M 0x8
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_CH_CTL_TX1_EN_L_S 2
+#define TIMPANI_CDC_CH_CTL_TX1_EN_L_M 0x4
+#define TIMPANI_CDC_CH_CTL_RX1_EN_R_S 1
+#define TIMPANI_CDC_CH_CTL_RX1_EN_R_M 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_CH_CTL_RX1_EN_L_S 0
+#define TIMPANI_CDC_CH_CTL_RX1_EN_L_M 0x1
+#define TIMPANI_A_CDC_RX1LG (0x84)
+#define TIMPANI_CDC_RX1LG_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX1LG_POR 0xac
+#define TIMPANI_CDC_RX1LG_S 0
+#define TIMPANI_CDC_RX1LG_M 0xFF
+#define TIMPANI_CDC_RX1LG_GAIN_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX1LG_GAIN_M 0xFF
+#define TIMPANI_A_CDC_RX1RG (0x85)
+#define TIMPANI_CDC_RX1RG_RWC "RW"
+#define TIMPANI_CDC_RX1RG_POR 0xac
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX1RG_S 0
+#define TIMPANI_CDC_RX1RG_M 0xFF
+#define TIMPANI_CDC_RX1RG_GAIN_S 0
+#define TIMPANI_CDC_RX1RG_GAIN_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_TX1LG (0x86)
+#define TIMPANI_CDC_TX1LG_RWC "RW"
+#define TIMPANI_CDC_TX1LG_POR 0xac
+#define TIMPANI_CDC_TX1LG_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX1LG_M 0xFF
+#define TIMPANI_CDC_TX1LG_GAIN_S 0
+#define TIMPANI_CDC_TX1LG_GAIN_M 0xFF
+#define TIMPANI_A_CDC_TX1RG (0x87)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX1RG_RWC "RW"
+#define TIMPANI_CDC_TX1RG_POR 0xac
+#define TIMPANI_CDC_TX1RG_S 0
+#define TIMPANI_CDC_TX1RG_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX1RG_GAIN_S 0
+#define TIMPANI_CDC_TX1RG_GAIN_M 0xFF
+#define TIMPANI_A_CDC_RX_PGA_TIMER (0x88)
+#define TIMPANI_CDC_RX_PGA_TIMER_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX_PGA_TIMER_POR 0xff
+#define TIMPANI_CDC_RX_PGA_TIMER_S 0
+#define TIMPANI_CDC_RX_PGA_TIMER_M 0xFF
+#define TIMPANI_CDC_RX_PGA_TIMER_TIMER_VAL_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX_PGA_TIMER_TIMER_VAL_M 0xFF
+#define TIMPANI_A_CDC_TX_PGA_TIMER (0x89)
+#define TIMPANI_CDC_TX_PGA_TIMER_RWC "RW"
+#define TIMPANI_CDC_TX_PGA_TIMER_POR 0xff
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX_PGA_TIMER_S 0
+#define TIMPANI_CDC_TX_PGA_TIMER_M 0xFF
+#define TIMPANI_CDC_TX_PGA_TIMER_TIMER_VAL_S 0
+#define TIMPANI_CDC_TX_PGA_TIMER_TIMER_VAL_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_GCTL1 (0x8A)
+#define TIMPANI_CDC_GCTL1_RWC "RW"
+#define TIMPANI_CDC_GCTL1_POR 0x33
+#define TIMPANI_CDC_GCTL1_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_GCTL1_M 0xFF
+#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_R_S 7
+#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_R_M 0x80
+#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_L_S 6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_L_M 0x40
+#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_R_S 5
+#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_R_M 0x20
+#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_L_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_L_M 0x10
+#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_R_S 3
+#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_R_M 0x8
+#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_L_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_L_M 0x4
+#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_R_S 1
+#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_R_M 0x2
+#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_L_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_L_M 0x1
+#define TIMPANI_A_CDC_TX1L_STG (0x8B)
+#define TIMPANI_CDC_TX1L_STG_RWC "RW"
+#define TIMPANI_CDC_TX1L_STG_POR 0xac
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX1L_STG_S 0
+#define TIMPANI_CDC_TX1L_STG_M 0xFF
+#define TIMPANI_CDC_TX1L_STG_GAIN_S 0
+#define TIMPANI_CDC_TX1L_STG_GAIN_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_ST_CTL (0x8C)
+#define TIMPANI_CDC_ST_CTL_RWC "RW"
+#define TIMPANI_CDC_ST_CTL_POR 0x55
+#define TIMPANI_CDC_ST_CTL_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ST_CTL_M 0xFF
+#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_UPDATE_S 7
+#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_UPDATE_M 0x80
+#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_MUTE_EN_S 6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_MUTE_EN_M 0x40
+#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_UPDATE_S 5
+#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_UPDATE_M 0x20
+#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_MUTE_EN_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_MUTE_EN_M 0x10
+#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_UPDATE_S 3
+#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_UPDATE_M 0x8
+#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_MUTE_EN_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_MUTE_EN_M 0x4
+#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_UPDATE_S 1
+#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_UPDATE_M 0x2
+#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_MUTE_EN_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_MUTE_EN_M 0x1
+#define TIMPANI_A_CDC_RX1L_DCOFFSET (0x8D)
+#define TIMPANI_CDC_RX1L_DCOFFSET_RWC "RW"
+#define TIMPANI_CDC_RX1L_DCOFFSET_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX1L_DCOFFSET_S 0
+#define TIMPANI_CDC_RX1L_DCOFFSET_M 0xFF
+#define TIMPANI_CDC_RX1L_DCOFFSET_OFFSET_S 0
+#define TIMPANI_CDC_RX1L_DCOFFSET_OFFSET_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_RX1R_DCOFFSET (0x8E)
+#define TIMPANI_CDC_RX1R_DCOFFSET_RWC "RW"
+#define TIMPANI_CDC_RX1R_DCOFFSET_POR 0
+#define TIMPANI_CDC_RX1R_DCOFFSET_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX1R_DCOFFSET_M 0xFF
+#define TIMPANI_CDC_RX1R_DCOFFSET_OFFSET_S 0
+#define TIMPANI_CDC_RX1R_DCOFFSET_OFFSET_M 0xFF
+#define TIMPANI_A_CDC_BYPASS_CTL1 (0x8F)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_BYPASS_CTL1_RWC "RW"
+#define TIMPANI_CDC_BYPASS_CTL1_POR 0x2
+#define TIMPANI_CDC_BYPASS_CTL1_S 0
+#define TIMPANI_CDC_BYPASS_CTL1_M 0xF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_BYPASS_CTL1_DITHER_BP_S 3
+#define TIMPANI_CDC_BYPASS_CTL1_DITHER_BP_M 0x8
+#define TIMPANI_CDC_BYPASS_CTL1_DITHER_SHAPE_SEL_S 2
+#define TIMPANI_CDC_BYPASS_CTL1_DITHER_SHAPE_SEL_M 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_BYPASS_CTL1_DITHER_DLY_SEL_S 1
+#define TIMPANI_CDC_BYPASS_CTL1_DITHER_DLY_SEL_M 0x2
+#define TIMPANI_CDC_BYPASS_CTL1_RX1_HPF_BP_S 0
+#define TIMPANI_CDC_BYPASS_CTL1_RX1_HPF_BP_M 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_PDM_CONFIG (0x90)
+#define TIMPANI_CDC_PDM_CONFIG_RWC "RW"
+#define TIMPANI_CDC_PDM_CONFIG_POR 0
+#define TIMPANI_CDC_PDM_CONFIG_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_PDM_CONFIG_M 0xF
+#define TIMPANI_CDC_PDM_CONFIG_PDM_SEL_S 0
+#define TIMPANI_CDC_PDM_CONFIG_PDM_SEL_M 0xF
+#define TIMPANI_A_CDC_TESTMODE1 (0x91)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TESTMODE1_RWC "RW"
+#define TIMPANI_CDC_TESTMODE1_POR 0
+#define TIMPANI_CDC_TESTMODE1_S 0
+#define TIMPANI_CDC_TESTMODE1_M 0x3F
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TESTMODE1_COMP_I2C_TEST_EN_S 5
+#define TIMPANI_CDC_TESTMODE1_COMP_I2C_TEST_EN_M 0x20
+#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_R_S 4
+#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_R_M 0x10
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_L_S 3
+#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_L_M 0x8
+#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_R_S 2
+#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_R_M 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_L_S 1
+#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_L_M 0x2
+#define TIMPANI_CDC_TESTMODE1_A_LOOPBACK_EN1_S 0
+#define TIMPANI_CDC_TESTMODE1_A_LOOPBACK_EN1_M 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_DMIC_CLK_CTL (0x92)
+#define TIMPANI_CDC_DMIC_CLK_CTL_RWC "RW"
+#define TIMPANI_CDC_DMIC_CLK_CTL_POR 0
+#define TIMPANI_CDC_DMIC_CLK_CTL_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_DMIC_CLK_CTL_M 0x3F
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_S 3
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_M 0x38
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_6 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_4 0x3
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_3 0x2
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_2 0x1
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_1 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_S 1
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_M 0x6
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_RX_MCLK2 0x2
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_RX_MCLK1 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_TX_MCLK 0x0
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_CLK_EN_S 0
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_CLK_EN_M 0x1
+#define TIMPANI_A_CDC_ADC12_CLK_CTL (0x93)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ADC12_CLK_CTL_RWC "RW"
+#define TIMPANI_CDC_ADC12_CLK_CTL_POR 0
+#define TIMPANI_CDC_ADC12_CLK_CTL_S 0
+#define TIMPANI_CDC_ADC12_CLK_CTL_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_S 6
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_M 0xC0
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_RX_MCLK2 0x2
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_RX_MCLK1 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_TX_MCLK 0x0
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_S 3
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_M 0x38
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_6 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_4 0x3
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_3 0x2
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_2 0x1
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_1 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_S 0
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_M 0x7
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_6 0x4
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_4 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_3 0x2
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_2 0x1
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_1 0x0
+#define TIMPANI_A_CDC_TX1_CTL (0x94)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX1_CTL_RWC "RW"
+#define TIMPANI_CDC_TX1_CTL_POR 0x1b
+#define TIMPANI_CDC_TX1_CTL_S 0
+#define TIMPANI_CDC_TX1_CTL_M 0x3F
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_R_S 5
+#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_R_M 0x20
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_S 3
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_M 0x18
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_256 0x3
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_128 0x1
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_64 0x0
+#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_L_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_L_M 0x4
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_S 0
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_M 0x3
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_256 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_128 0x1
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_64 0x0
+#define TIMPANI_A_CDC_ADC34_CLK_CTL (0x95)
+#define TIMPANI_CDC_ADC34_CLK_CTL_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ADC34_CLK_CTL_POR 0
+#define TIMPANI_CDC_ADC34_CLK_CTL_S 0
+#define TIMPANI_CDC_ADC34_CLK_CTL_M 0xFF
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_S 6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_M 0xC0
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_RX_MCLK2 0x2
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_RX_MCLK1 0x1
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_TX_MCLK 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_S 3
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_M 0x38
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_6 0x4
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_4 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_3 0x2
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_2 0x1
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_1 0x0
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_M 0x7
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_6 0x4
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_4 0x3
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_3 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_2 0x1
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_1 0x0
+#define TIMPANI_A_CDC_TX2_CTL (0x96)
+#define TIMPANI_CDC_TX2_CTL_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX2_CTL_POR 0x1b
+#define TIMPANI_CDC_TX2_CTL_S 0
+#define TIMPANI_CDC_TX2_CTL_M 0x3F
+#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_R_S 5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_R_M 0x20
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_S 3
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_M 0x18
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_256 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_128 0x1
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_64 0x0
+#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_L_S 2
+#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_L_M 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_S 0
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_M 0x3
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_256 0x3
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_128 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_64 0x0
+#define TIMPANI_A_CDC_RX1_CLK_CTL (0x97)
+#define TIMPANI_CDC_RX1_CLK_CTL_RWC "RW"
+#define TIMPANI_CDC_RX1_CLK_CTL_POR 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX1_CLK_CTL_S 0
+#define TIMPANI_CDC_RX1_CLK_CTL_M 0x1F
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_S 2
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_M 0x1C
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_6 0x4
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_4 0x3
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_3 0x2
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_2 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_1 0x0
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_S 0
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_M 0x3
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_RX_MCLK2 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_RX_MCLK1 0x1
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_TX_MCLK 0x0
+#define TIMPANI_A_CDC_RX2_CLK_CTL (0x98)
+#define TIMPANI_CDC_RX2_CLK_CTL_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX2_CLK_CTL_POR 0x2
+#define TIMPANI_CDC_RX2_CLK_CTL_S 0
+#define TIMPANI_CDC_RX2_CLK_CTL_M 0x1F
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_M 0x1C
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_6 0x4
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_4 0x3
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_3 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_2 0x1
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_1 0x0
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_S 0
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_M 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_RX_MCLK2 0x2
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_RX_MCLK1 0x1
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_TX_MCLK 0x0
+#define TIMPANI_A_CDC_DEC_ADC_SEL (0x99)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_DEC_ADC_SEL_RWC "RW"
+#define TIMPANI_CDC_DEC_ADC_SEL_POR 0
+#define TIMPANI_CDC_DEC_ADC_SEL_S 0
+#define TIMPANI_CDC_DEC_ADC_SEL_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_S 6
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_M 0xC0
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC4 0x3
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC3 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC2 0x1
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC1 0x0
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_S 4
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_M 0x30
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC4 0x3
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC3 0x2
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC2 0x1
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC1 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_S 2
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_M 0xC
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC4 0x3
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC3 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC2 0x1
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC1 0x0
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_S 0
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_M 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC4 0x3
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC3 0x2
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC2 0x1
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC1 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_ANC_INPUT_MUX (0x9A)
+#define TIMPANI_CDC_ANC_INPUT_MUX_RWC "RW"
+#define TIMPANI_CDC_ANC_INPUT_MUX_POR 0
+#define TIMPANI_CDC_ANC_INPUT_MUX_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC_INPUT_MUX_M 0xFF
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_S 6
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_M 0xC0
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX2DOR 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX2DOL 0x2
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX1DOR 0x1
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX1DOL 0x0
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_M 0x30
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC2_DIN_R 0x3
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC2_DIN_L 0x2
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC1_DIN_R 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC1_DIN_L 0x0
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_S 2
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_M 0xC
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX2DOR 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX2DOL 0x2
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX1DOR 0x1
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX1DOL 0x0
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_M 0x3
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC2_DIN_R 0x3
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC2_DIN_L 0x2
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC1_DIN_R 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC1_DIN_L 0x0
+#define TIMPANI_A_CDC_ANC_RX_CLK_NS_SEL (0x9B)
+#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_RWC "RW"
+#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_S 0
+#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_M 0x1
+#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_ANC_RX_CLK_NS_SEL_S 0
+#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_ANC_RX_CLK_NS_SEL_M 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_ANC_FB_TUNE_SEL (0x9C)
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_RWC "RW"
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_POR 0
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_M 0x3
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_S 1
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_M 0x2
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_FB_TUNE_EN 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_FB_TUNE_DIS 0x0
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_S 0
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_M 0x1
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_FB_TUNE_EN 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_FB_TUNE_DIS 0x0
+#define TIMPANI_A_CLK_DIV_SYNC_CTL (0x9E)
+#define TIMPANI_CLK_DIV_SYNC_CTL_RWC "RW"
+#define TIMPANI_CLK_DIV_SYNC_CTL_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CLK_DIV_SYNC_CTL_S 0
+#define TIMPANI_CLK_DIV_SYNC_CTL_M 0x3
+#define TIMPANI_CLK_DIV_SYNC_CTL_GLBL_DIV_SYNC_S 1
+#define TIMPANI_CLK_DIV_SYNC_CTL_GLBL_DIV_SYNC_M 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CLK_DIV_SYNC_CTL_TX_DIV_SYNC_S 0
+#define TIMPANI_CLK_DIV_SYNC_CTL_TX_DIV_SYNC_M 0x1
+#define TIMPANI_A_CDC_ADC_CLK_EN (0x9F)
+#define TIMPANI_CDC_ADC_CLK_EN_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ADC_CLK_EN_POR 0
+#define TIMPANI_CDC_ADC_CLK_EN_S 0
+#define TIMPANI_CDC_ADC_CLK_EN_M 0xF
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_R_EN_S 3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_R_EN_M 0x8
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_L_EN_S 2
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_L_EN_M 0x4
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_R_EN_S 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_R_EN_M 0x2
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_L_EN_S 0
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_L_EN_M 0x1
+#define TIMPANI_A_CDC_ST_MIXING (0xA0)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ST_MIXING_RWC "RW"
+#define TIMPANI_CDC_ST_MIXING_POR 0
+#define TIMPANI_CDC_ST_MIXING_S 0
+#define TIMPANI_CDC_ST_MIXING_M 0xF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ST_MIXING_TX2_R_S 3
+#define TIMPANI_CDC_ST_MIXING_TX2_R_M 0x8
+#define TIMPANI_CDC_ST_MIXING_TX2_L_S 2
+#define TIMPANI_CDC_ST_MIXING_TX2_L_M 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ST_MIXING_TX1_R_S 1
+#define TIMPANI_CDC_ST_MIXING_TX1_R_M 0x2
+#define TIMPANI_CDC_ST_MIXING_TX1_L_S 0
+#define TIMPANI_CDC_ST_MIXING_TX1_L_M 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_RX2_CTL (0xA1)
+#define TIMPANI_CDC_RX2_CTL_RWC "RW"
+#define TIMPANI_CDC_RX2_CTL_POR 0xc
+#define TIMPANI_CDC_RX2_CTL_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX2_CTL_M 0x3F
+#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_R_S 5
+#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_R_M 0x20
+#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_L_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_L_M 0x10
+#define TIMPANI_CDC_RX2_CTL_RX2_RATE_S 2
+#define TIMPANI_CDC_RX2_CTL_RX2_RATE_M 0xC
+#define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_256 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_128 0x1
+#define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_64 0x0
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_S 1
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_M 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_BR_32 0x1
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_BR_64 0x0
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_S 0
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_M 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_MASTER 0x1
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_SLAVE 0x0
+#define TIMPANI_A_CDC_ARB_CLK_EN (0xA2)
+#define TIMPANI_CDC_ARB_CLK_EN_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ARB_CLK_EN_POR 0
+#define TIMPANI_CDC_ARB_CLK_EN_S 0
+#define TIMPANI_CDC_ARB_CLK_EN_M 0x1
+#define TIMPANI_CDC_ARB_CLK_EN_ARB_CLK_EN_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ARB_CLK_EN_ARB_CLK_EN_M 0x1
+#define TIMPANI_A_CDC_I2S_CTL2 (0xA3)
+#define TIMPANI_CDC_I2S_CTL2_RWC "RW"
+#define TIMPANI_CDC_I2S_CTL2_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_I2S_CTL2_S 0
+#define TIMPANI_CDC_I2S_CTL2_M 0x3F
+#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_S 3
+#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_M 0x38
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_DMIC 0x4
+#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX2_R 0x3
+#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX2_L 0x2
+#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX1_R 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX1_L 0x0
+#define TIMPANI_CDC_I2S_CTL2_RX2_I2SCLK_EN_S 2
+#define TIMPANI_CDC_I2S_CTL2_RX2_I2SCLK_EN_M 0x4
+#define TIMPANI_CDC_I2S_CTL2_RX1_I2SCLK_EN_S 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_I2S_CTL2_RX1_I2SCLK_EN_M 0x2
+#define TIMPANI_CDC_I2S_CTL2_TX_I2SCLK_EN_S 0
+#define TIMPANI_CDC_I2S_CTL2_TX_I2SCLK_EN_M 0x1
+#define TIMPANI_A_CDC_RX2LG (0xA4)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX2LG_RWC "RW"
+#define TIMPANI_CDC_RX2LG_POR 0xac
+#define TIMPANI_CDC_RX2LG_S 0
+#define TIMPANI_CDC_RX2LG_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX2LG_GAIN_S 0
+#define TIMPANI_CDC_RX2LG_GAIN_M 0xFF
+#define TIMPANI_A_CDC_RX2RG (0xA5)
+#define TIMPANI_CDC_RX2RG_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX2RG_POR 0xac
+#define TIMPANI_CDC_RX2RG_S 0
+#define TIMPANI_CDC_RX2RG_M 0xFF
+#define TIMPANI_CDC_RX2RG_GAIN_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX2RG_GAIN_M 0xFF
+#define TIMPANI_A_CDC_TX2LG (0xA6)
+#define TIMPANI_CDC_TX2LG_RWC "RW"
+#define TIMPANI_CDC_TX2LG_POR 0xac
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX2LG_S 0
+#define TIMPANI_CDC_TX2LG_M 0xFF
+#define TIMPANI_CDC_TX2LG_GAIN_S 0
+#define TIMPANI_CDC_TX2LG_GAIN_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_TX2RG (0xA7)
+#define TIMPANI_CDC_TX2RG_RWC "RW"
+#define TIMPANI_CDC_TX2RG_POR 0xac
+#define TIMPANI_CDC_TX2RG_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX2RG_M 0xFF
+#define TIMPANI_CDC_TX2RG_GAIN_S 0
+#define TIMPANI_CDC_TX2RG_GAIN_M 0xFF
+#define TIMPANI_A_CDC_DMIC_MUX (0xA8)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_DMIC_MUX_RWC "RW"
+#define TIMPANI_CDC_DMIC_MUX_POR 0
+#define TIMPANI_CDC_DMIC_MUX_S 0
+#define TIMPANI_CDC_DMIC_MUX_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_S 6
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_M 0xC0
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC2_DIN_R 0x3
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC2_DIN_L 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC1_DIN_R 0x1
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC1_DIN_L 0x0
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_S 4
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_M 0x30
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC2_DIN_R 0x3
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC2_DIN_L 0x2
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC1_DIN_R 0x1
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC1_DIN_L 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_S 2
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_M 0xC
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC2_DIN_R 0x3
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC2_DIN_L 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC1_DIN_R 0x1
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC1_DIN_L 0x0
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_S 0
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_M 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC2_DIN_R 0x3
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC2_DIN_L 0x2
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC1_DIN_R 0x1
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC1_DIN_L 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_ARB_CLK_CTL (0xA9)
+#define TIMPANI_CDC_ARB_CLK_CTL_RWC "RW"
+#define TIMPANI_CDC_ARB_CLK_CTL_POR 0
+#define TIMPANI_CDC_ARB_CLK_CTL_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ARB_CLK_CTL_M 0x3
+#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_S 0
+#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_M 0x3
+#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_TX_MCLK 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_RX_MCLK1 0x1
+#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_RX_MCLK2 0x2
+#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_TCXO 0x3
+#define TIMPANI_A_CDC_GCTL2 (0xAA)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_GCTL2_RWC "RW"
+#define TIMPANI_CDC_GCTL2_POR 0x33
+#define TIMPANI_CDC_GCTL2_S 0
+#define TIMPANI_CDC_GCTL2_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_R_S 7
+#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_R_M 0x80
+#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_L_S 6
+#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_L_M 0x40
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_R_S 5
+#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_R_M 0x20
+#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_L_S 4
+#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_L_M 0x10
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_R_S 3
+#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_R_M 0x8
+#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_L_S 2
+#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_L_M 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_R_S 1
+#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_R_M 0x2
+#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_L_S 0
+#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_L_M 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_BYPASS_CTL2 (0xAB)
+#define TIMPANI_CDC_BYPASS_CTL2_RWC "RW"
+#define TIMPANI_CDC_BYPASS_CTL2_POR 0x2D
+#define TIMPANI_CDC_BYPASS_CTL2_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_BYPASS_CTL2_M 0x3F
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_R_S 5
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_R_M 0x20
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_R_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_R_M 0x10
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_R_S 3
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_R_M 0x8
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_L_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_L_M 0x4
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_L_S 1
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_L_M 0x2
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_L_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_L_M 0x1
+#define TIMPANI_A_CDC_BYPASS_CTL3 (0xAC)
+#define TIMPANI_CDC_BYPASS_CTL3_RWC "RW"
+#define TIMPANI_CDC_BYPASS_CTL3_POR 0x2D
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_BYPASS_CTL3_S 0
+#define TIMPANI_CDC_BYPASS_CTL3_M 0x3F
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_R_S 5
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_R_M 0x20
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_R_S 4
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_R_M 0x10
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_R_S 3
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_R_M 0x8
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_L_S 2
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_L_M 0x4
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_L_S 1
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_L_M 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_L_S 0
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_L_M 0x1
+#define TIMPANI_A_CDC_BYPASS_CTL4 (0xAD)
+#define TIMPANI_CDC_BYPASS_CTL4_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_BYPASS_CTL4_POR 0x2
+#define TIMPANI_CDC_BYPASS_CTL4_S 0
+#define TIMPANI_CDC_BYPASS_CTL4_M 0xF
+#define TIMPANI_CDC_BYPASS_CTL4_DITHER_BP_S 3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_BYPASS_CTL4_DITHER_BP_M 0x8
+#define TIMPANI_CDC_BYPASS_CTL4_DITHER_SHAPE_SEL_S 2
+#define TIMPANI_CDC_BYPASS_CTL4_DITHER_SHAPE_SEL_M 0x4
+#define TIMPANI_CDC_BYPASS_CTL4_DITHER_DLY_SEL_S 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_BYPASS_CTL4_DITHER_DLY_SEL_M 0x2
+#define TIMPANI_CDC_BYPASS_CTL4_RX2_HPF_BP_S 0
+#define TIMPANI_CDC_BYPASS_CTL4_RX2_HPF_BP_M 0x1
+#define TIMPANI_A_CDC_RX2L_DCOFFSET (0xAE)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX2L_DCOFFSET_RWC "RW"
+#define TIMPANI_CDC_RX2L_DCOFFSET_POR 0
+#define TIMPANI_CDC_RX2L_DCOFFSET_S 0
+#define TIMPANI_CDC_RX2L_DCOFFSET_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX2L_DCOFFSET_OFFSET_S 0
+#define TIMPANI_CDC_RX2L_DCOFFSET_OFFSET_M 0xFF
+#define TIMPANI_A_CDC_RX2R_DCOFFSET (0xAF)
+#define TIMPANI_CDC_RX2R_DCOFFSET_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX2R_DCOFFSET_POR 0
+#define TIMPANI_CDC_RX2R_DCOFFSET_S 0
+#define TIMPANI_CDC_RX2R_DCOFFSET_M 0xFF
+#define TIMPANI_CDC_RX2R_DCOFFSET_OFFSET_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX2R_DCOFFSET_OFFSET_M 0xFF
+#define TIMPANI_A_CDC_RX_MIX_CTL (0xB0)
+#define TIMPANI_CDC_RX_MIX_CTL_RWC "RW"
+#define TIMPANI_CDC_RX_MIX_CTL_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX_MIX_CTL_S 0
+#define TIMPANI_CDC_RX_MIX_CTL_M 0x3
+#define TIMPANI_CDC_RX_MIX_CTL_RX2TO1_EN_S 1
+#define TIMPANI_CDC_RX_MIX_CTL_RX2TO1_EN_M 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_RX_MIX_CTL_RX1TO2_EN_S 0
+#define TIMPANI_CDC_RX_MIX_CTL_RX1TO2_EN_M 0x1
+#define TIMPANI_A_CDC_SPARE_CTL (0xB1)
+#define TIMPANI_CDC_SPARE_CTL_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_SPARE_CTL_POR 0
+#define TIMPANI_CDC_SPARE_CTL_S 0
+#define TIMPANI_CDC_SPARE_CTL_M 0xFF
+#define TIMPANI_CDC_SPARE_CTL_CDC_SPARE_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_SPARE_CTL_CDC_SPARE_M 0xFF
+#define TIMPANI_A_CDC_TESTMODE2 (0xB2)
+#define TIMPANI_CDC_TESTMODE2_RWC "RW"
+#define TIMPANI_CDC_TESTMODE2_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TESTMODE2_S 0
+#define TIMPANI_CDC_TESTMODE2_M 0x1F
+#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_R_S 4
+#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_R_M 0x10
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_L_S 3
+#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_L_M 0x8
+#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_R_S 2
+#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_R_M 0x4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_L_S 1
+#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_L_M 0x2
+#define TIMPANI_CDC_TESTMODE2_A_LOOPBACK_EN2_S 0
+#define TIMPANI_CDC_TESTMODE2_A_LOOPBACK_EN2_M 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_PDM_OE (0xB3)
+#define TIMPANI_CDC_PDM_OE_RWC "RW"
+#define TIMPANI_CDC_PDM_OE_POR 0
+#define TIMPANI_CDC_PDM_OE_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_PDM_OE_M 0x3F
+#define TIMPANI_CDC_PDM_OE_PDM_23_20_OE_S 5
+#define TIMPANI_CDC_PDM_OE_PDM_23_20_OE_M 0x20
+#define TIMPANI_CDC_PDM_OE_PDM_19_16_OE_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_PDM_OE_PDM_19_16_OE_M 0x10
+#define TIMPANI_CDC_PDM_OE_PDM_15_12_OE_S 3
+#define TIMPANI_CDC_PDM_OE_PDM_15_12_OE_M 0x8
+#define TIMPANI_CDC_PDM_OE_PDM_11_8_OE_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_PDM_OE_PDM_11_8_OE_M 0x4
+#define TIMPANI_CDC_PDM_OE_PDM_7_4_OE_S 1
+#define TIMPANI_CDC_PDM_OE_PDM_7_4_OE_M 0x2
+#define TIMPANI_CDC_PDM_OE_PDM_3_0_OE_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_PDM_OE_PDM_3_0_OE_M 0x1
+#define TIMPANI_A_CDC_TX1R_STG (0xB4)
+#define TIMPANI_CDC_TX1R_STG_RWC "RW"
+#define TIMPANI_CDC_TX1R_STG_POR 0xac
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX1R_STG_S 0
+#define TIMPANI_CDC_TX1R_STG_M 0xFF
+#define TIMPANI_CDC_TX1R_STG_GAIN_S 0
+#define TIMPANI_CDC_TX1R_STG_GAIN_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_TX2L_STG (0xB5)
+#define TIMPANI_CDC_TX2L_STG_RWC "RW"
+#define TIMPANI_CDC_TX2L_STG_POR 0xac
+#define TIMPANI_CDC_TX2L_STG_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX2L_STG_M 0xFF
+#define TIMPANI_CDC_TX2L_STG_GAIN_S 0
+#define TIMPANI_CDC_TX2L_STG_GAIN_M 0xFF
+#define TIMPANI_A_CDC_TX2R_STG (0xB6)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX2R_STG_RWC "RW"
+#define TIMPANI_CDC_TX2R_STG_POR 0xac
+#define TIMPANI_CDC_TX2R_STG_S 0
+#define TIMPANI_CDC_TX2R_STG_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_TX2R_STG_GAIN_S 0
+#define TIMPANI_CDC_TX2R_STG_GAIN_M 0xFF
+#define TIMPANI_A_CDC_ARB_BYPASS_CTL (0xB7)
+#define TIMPANI_CDC_ARB_BYPASS_CTL_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ARB_BYPASS_CTL_POR 0
+#define TIMPANI_CDC_ARB_BYPASS_CTL_S 0
+#define TIMPANI_CDC_ARB_BYPASS_CTL_M 0x1
+#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_M 0x1
+#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_BYPASS 0x1
+#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_NO_BYPASS 0x0
+#define TIMPANI_A_CDC_ANC1_CTL1 (0xC0)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_CTL1_RWC "RW"
+#define TIMPANI_CDC_ANC1_CTL1_POR 0
+#define TIMPANI_CDC_ANC1_CTL1_S 0
+#define TIMPANI_CDC_ANC1_CTL1_M 0x3F
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_S 5
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_M 0x20
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_FF_OUT_DIS 0x1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_FF_OUT_EN 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_S 4
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_M 0x10
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_DMIC 0x1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_ADC 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_S 3
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_M 0x8
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_LR_MIX_EN 0x1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_LR_MIX_DIS 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_S 2
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_M 0x4
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_FB_MIX_EN 0x1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_FB_MIX_DIS 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_S 1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_M 0x2
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_ANC_EN 0x1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_ANC_DIS 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_S 0
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_M 0x1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_ANC_RESET 0x1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_ANC_ACTIVE 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_ANC1_CTL2 (0xC1)
+#define TIMPANI_CDC_ANC1_CTL2_RWC "RW"
+#define TIMPANI_CDC_ANC1_CTL2_POR 0
+#define TIMPANI_CDC_ANC1_CTL2_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_CTL2_M 0x1F
+#define TIMPANI_CDC_ANC1_CTL2_ANC1_FREQ_SEL_S 0
+#define TIMPANI_CDC_ANC1_CTL2_ANC1_FREQ_SEL_M 0x1F
+#define TIMPANI_A_CDC_ANC1_FF_FB_SHIFT (0xC2)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_RWC "RW"
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_POR 0
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_S 0
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FB_LPF_SHIFT_S 4
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FB_LPF_SHIFT_M 0xF0
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FF_LPF_SHIFT_S 0
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FF_LPF_SHIFT_M 0xF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_ANC1_RX_NS (0xC3)
+#define TIMPANI_CDC_ANC1_RX_NS_RWC "RW"
+#define TIMPANI_CDC_ANC1_RX_NS_POR 0x1
+#define TIMPANI_CDC_ANC1_RX_NS_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_RX_NS_M 0x7
+#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_BP_S 2
+#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_BP_M 0x4
+#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_SHAPE_SEL_S 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_SHAPE_SEL_M 0x2
+#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_DLY_SEL_S 0
+#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_DLY_SEL_M 0x1
+#define TIMPANI_A_CDC_ANC1_SPARE (0xC4)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_SPARE_RWC "RW"
+#define TIMPANI_CDC_ANC1_SPARE_POR 0
+#define TIMPANI_CDC_ANC1_SPARE_S 0
+#define TIMPANI_CDC_ANC1_SPARE_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_SPARE_ANC1_SPARE_S 0
+#define TIMPANI_CDC_ANC1_SPARE_ANC1_SPARE_M 0xFF
+#define TIMPANI_A_CDC_ANC1_IIR_COEFF_PTR (0xC5)
+#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_POR 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_S 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_M 0x1F
+#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_ANC1_IIR_COEFF_PTR_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_ANC1_IIR_COEFF_PTR_M 0x1F
+#define TIMPANI_A_CDC_ANC1_IIR_COEFF_MSB (0xC6)
+#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_RWC "RW"
+#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_S 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_M 0x1
+#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_ANC1_IIR_COEFF_MSB_S 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_ANC1_IIR_COEFF_MSB_M 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_ANC1_IIR_COEFF_LSB (0xC7)
+#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_RWC "RW"
+#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_POR 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_M 0xFF
+#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_ANC1_IIR_COEFF_LSB_S 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_ANC1_IIR_COEFF_LSB_M 0xFF
+#define TIMPANI_A_CDC_ANC1_IIR_COEFF_CTL (0xC8)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_RWC "RW"
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_POR 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_S 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_M 0x3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_S 1
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_M 0x2
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_ADAPTIVE 0x1
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_NON_ADAPTIVE 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_S 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_M 0x1
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_UPDATE 0x1
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_NO_UPDATE 0x0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_ANC1_LPF_COEFF_PTR (0xC9)
+#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_RWC "RW"
+#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_POR 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_M 0xF
+#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_ANC1_LPF_COEFF_PTR_S 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_ANC1_LPF_COEFF_PTR_M 0xF
+#define TIMPANI_A_CDC_ANC1_LPF_COEFF_MSB (0xCA)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_RWC "RW"
+#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_POR 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_S 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_M 0xF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_ANC1_LPF_COEFF_MSB_S 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_ANC1_LPF_COEFF_MSB_M 0xF
+#define TIMPANI_A_CDC_ANC1_LPF_COEFF_LSB (0xCB)
+#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_POR 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_S 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_M 0xFF
+#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_ANC1_LPF_COEFF_LSB_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_ANC1_LPF_COEFF_LSB_M 0xFF
+#define TIMPANI_A_CDC_ANC1_SCALE_PTR (0xCC)
+#define TIMPANI_CDC_ANC1_SCALE_PTR_RWC "RW"
+#define TIMPANI_CDC_ANC1_SCALE_PTR_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_SCALE_PTR_S 0
+#define TIMPANI_CDC_ANC1_SCALE_PTR_M 0x7
+#define TIMPANI_CDC_ANC1_SCALE_PTR_ANC1_SCALE_PTR_S 0
+#define TIMPANI_CDC_ANC1_SCALE_PTR_ANC1_SCALE_PTR_M 0x7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_ANC1_SCALE (0xCD)
+#define TIMPANI_CDC_ANC1_SCALE_RWC "RW"
+#define TIMPANI_CDC_ANC1_SCALE_POR 0
+#define TIMPANI_CDC_ANC1_SCALE_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_SCALE_M 0xFF
+#define TIMPANI_CDC_ANC1_SCALE_ANC1_SCALE_S 0
+#define TIMPANI_CDC_ANC1_SCALE_ANC1_SCALE_M 0xFF
+#define TIMPANI_A_CDC_ANC1_DEBUG (0xCE)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_DEBUG_RWC "RW"
+#define TIMPANI_CDC_ANC1_DEBUG_POR 0
+#define TIMPANI_CDC_ANC1_DEBUG_S 0
+#define TIMPANI_CDC_ANC1_DEBUG_M 0xF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC1_DEBUG_ANC1_DEBUG_SEL_S 0
+#define TIMPANI_CDC_ANC1_DEBUG_ANC1_DEBUG_SEL_M 0xF
+#define TIMPANI_A_CDC_ANC2_CTL1 (0xD0)
+#define TIMPANI_CDC_ANC2_CTL1_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_CTL1_POR 0
+#define TIMPANI_CDC_ANC2_CTL1_S 0
+#define TIMPANI_CDC_ANC2_CTL1_M 0x3F
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_S 5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_M 0x20
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_FF_OUT_DIS 0x1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_FF_OUT_EN 0x0
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_M 0x10
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_DMIC 0x1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_ADC 0x0
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_S 3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_M 0x8
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_LR_MIX_EN 0x1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_LR_MIX_DIS 0x0
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_M 0x4
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_FB_MIX_EN 0x1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_FB_MIX_DIS 0x0
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_S 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_M 0x2
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_ANC_EN 0x1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_ANC_DIS 0x0
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_M 0x1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_ANC_RESET 0x1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_ANC_ACTIVE 0x0
+#define TIMPANI_A_CDC_ANC2_CTL2 (0xD1)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_CTL2_RWC "RW"
+#define TIMPANI_CDC_ANC2_CTL2_POR 0
+#define TIMPANI_CDC_ANC2_CTL2_S 0
+#define TIMPANI_CDC_ANC2_CTL2_M 0x1F
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_CTL2_ANC2_FREQ_SEL_S 0
+#define TIMPANI_CDC_ANC2_CTL2_ANC2_FREQ_SEL_M 0x1F
+#define TIMPANI_A_CDC_ANC2_FF_FB_SHIFT (0xD2)
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_POR 0
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_S 0
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_M 0xFF
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FB_LPF_SHIFT_S 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FB_LPF_SHIFT_M 0xF0
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FF_LPF_SHIFT_S 0
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FF_LPF_SHIFT_M 0xF
+#define TIMPANI_A_CDC_ANC2_RX_NS (0xD3)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_RX_NS_RWC "RW"
+#define TIMPANI_CDC_ANC2_RX_NS_POR 0x1
+#define TIMPANI_CDC_ANC2_RX_NS_S 0
+#define TIMPANI_CDC_ANC2_RX_NS_M 0x7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_BP_S 2
+#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_BP_M 0x4
+#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_SHAPE_SEL_S 1
+#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_SHAPE_SEL_M 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_DLY_SEL_S 0
+#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_DLY_SEL_M 0x1
+#define TIMPANI_A_CDC_ANC2_SPARE (0xD4)
+#define TIMPANI_CDC_ANC2_SPARE_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_SPARE_POR 0
+#define TIMPANI_CDC_ANC2_SPARE_S 0
+#define TIMPANI_CDC_ANC2_SPARE_M 0xFF
+#define TIMPANI_CDC_ANC2_SPARE_ANC2_SPARE_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_SPARE_ANC2_SPARE_M 0xFF
+#define TIMPANI_A_CDC_ANC2_IIR_COEFF_PTR (0xD5)
+#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_RWC "RW"
+#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_S 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_M 0x1F
+#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_ANC2_IIR_COEFF_PTR_S 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_ANC2_IIR_COEFF_PTR_M 0x1F
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_ANC2_IIR_COEFF_MSB (0xD6)
+#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_RWC "RW"
+#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_POR 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_M 0x1
+#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_ANC2_IIR_COEFF_MSB_S 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_ANC2_IIR_COEFF_MSB_M 0x1
+#define TIMPANI_A_CDC_ANC2_IIR_COEFF_LSB (0xD7)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_RWC "RW"
+#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_POR 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_S 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_ANC2_IIR_COEFF_LSB_S 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_ANC2_IIR_COEFF_LSB_M 0xFF
+#define TIMPANI_A_CDC_ANC2_IIR_COEFF_CTL (0xD8)
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_POR 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_S 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_M 0x3
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_S 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_M 0x2
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_ADAPTIVE 0x1
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_NON_ADAPTIVE 0x0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_M 0x1
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_UPDATE 0x1
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_NO_UPDATE 0x0
+#define TIMPANI_A_CDC_ANC2_LPF_COEFF_PTR (0xD9)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_RWC "RW"
+#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_POR 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_S 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_M 0xF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_ANC2_LPF_COEFF_PTR_S 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_ANC2_LPF_COEFF_PTR_M 0xF
+#define TIMPANI_A_CDC_ANC2_LPF_COEFF_MSB (0xDA)
+#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_POR 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_S 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_M 0xF
+#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_ANC2_LPF_COEFF_MSB_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_ANC2_LPF_COEFF_MSB_M 0xF
+#define TIMPANI_A_CDC_ANC2_LPF_COEFF_LSB (0xDB)
+#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_RWC "RW"
+#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_S 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_M 0xFF
+#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_ANC2_LPF_COEFF_LSB_S 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_ANC2_LPF_COEFF_LSB_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_ANC2_SCALE_PTR (0xDC)
+#define TIMPANI_CDC_ANC2_SCALE_PTR_RWC "RW"
+#define TIMPANI_CDC_ANC2_SCALE_PTR_POR 0
+#define TIMPANI_CDC_ANC2_SCALE_PTR_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_SCALE_PTR_M 0x7
+#define TIMPANI_CDC_ANC2_SCALE_PTR_ANC2_SCALE_PTR_S 0
+#define TIMPANI_CDC_ANC2_SCALE_PTR_ANC2_SCALE_PTR_M 0x7
+#define TIMPANI_A_CDC_ANC2_SCALE (0xDD)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_SCALE_RWC "RW"
+#define TIMPANI_CDC_ANC2_SCALE_POR 0
+#define TIMPANI_CDC_ANC2_SCALE_S 0
+#define TIMPANI_CDC_ANC2_SCALE_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_SCALE_ANC2_SCALE_S 0
+#define TIMPANI_CDC_ANC2_SCALE_ANC2_SCALE_M 0xFF
+#define TIMPANI_A_CDC_ANC2_DEBUG (0xDE)
+#define TIMPANI_CDC_ANC2_DEBUG_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_DEBUG_POR 0
+#define TIMPANI_CDC_ANC2_DEBUG_S 0
+#define TIMPANI_CDC_ANC2_DEBUG_M 0xF
+#define TIMPANI_CDC_ANC2_DEBUG_ANC2_DEBUG_SEL_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_ANC2_DEBUG_ANC2_DEBUG_SEL_M 0xF
+#define TIMPANI_A_CDC_LINE_L_AVOL (0xE0)
+#define TIMPANI_CDC_LINE_L_AVOL_RWC "RW"
+#define TIMPANI_CDC_LINE_L_AVOL_POR 0xac
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_LINE_L_AVOL_S 0
+#define TIMPANI_CDC_LINE_L_AVOL_M 0xFF
+#define TIMPANI_CDC_LINE_L_AVOL_USER_GAIN_S 2
+#define TIMPANI_CDC_LINE_L_AVOL_USER_GAIN_M 0xFC
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_LINE_L_AVOL_DUMMY_S 0
+#define TIMPANI_CDC_LINE_L_AVOL_DUMMY_M 0x3
+#define TIMPANI_A_CDC_LINE_R_AVOL (0xE1)
+#define TIMPANI_CDC_LINE_R_AVOL_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_LINE_R_AVOL_POR 0xac
+#define TIMPANI_CDC_LINE_R_AVOL_S 0
+#define TIMPANI_CDC_LINE_R_AVOL_M 0xFF
+#define TIMPANI_CDC_LINE_R_AVOL_USER_GAIN_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_LINE_R_AVOL_USER_GAIN_M 0xFC
+#define TIMPANI_CDC_LINE_R_AVOL_DUMMY_S 0
+#define TIMPANI_CDC_LINE_R_AVOL_DUMMY_M 0x3
+#define TIMPANI_A_CDC_HPH_L_AVOL (0xE2)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_HPH_L_AVOL_RWC "RW"
+#define TIMPANI_CDC_HPH_L_AVOL_POR 0xae
+#define TIMPANI_CDC_HPH_L_AVOL_S 0
+#define TIMPANI_CDC_HPH_L_AVOL_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_HPH_L_AVOL_USER_GAIN_S 2
+#define TIMPANI_CDC_HPH_L_AVOL_USER_GAIN_M 0xFC
+#define TIMPANI_CDC_HPH_L_AVOL_MUTE_S 1
+#define TIMPANI_CDC_HPH_L_AVOL_MUTE_M 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_HPH_L_AVOL_MUTE_MUTE 0x1
+#define TIMPANI_CDC_HPH_L_AVOL_MUTE_UNMUTE 0x0
+#define TIMPANI_CDC_HPH_L_AVOL_DUMMY_S 0
+#define TIMPANI_CDC_HPH_L_AVOL_DUMMY_M 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_HPH_R_AVOL (0xE3)
+#define TIMPANI_CDC_HPH_R_AVOL_RWC "RW"
+#define TIMPANI_CDC_HPH_R_AVOL_POR 0xae
+#define TIMPANI_CDC_HPH_R_AVOL_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_HPH_R_AVOL_M 0xFF
+#define TIMPANI_CDC_HPH_R_AVOL_USER_GAIN_S 2
+#define TIMPANI_CDC_HPH_R_AVOL_USER_GAIN_M 0xFC
+#define TIMPANI_CDC_HPH_R_AVOL_MUTE_S 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_HPH_R_AVOL_MUTE_M 0x2
+#define TIMPANI_CDC_HPH_R_AVOL_MUTE_MUTE 0x1
+#define TIMPANI_CDC_HPH_R_AVOL_MUTE_UNMUTE 0x0
+#define TIMPANI_CDC_HPH_R_AVOL_DUMMY_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_HPH_R_AVOL_DUMMY_M 0x1
+#define TIMPANI_A_CDC_COMP_CTL1 (0xE4)
+#define TIMPANI_CDC_COMP_CTL1_RWC "RW"
+#define TIMPANI_CDC_COMP_CTL1_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_COMP_CTL1_S 0
+#define TIMPANI_CDC_COMP_CTL1_M 0xFF
+#define TIMPANI_CDC_COMP_CTL1_LO_CLK_EN_S 7
+#define TIMPANI_CDC_COMP_CTL1_LO_CLK_EN_M 0x80
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_COMP_CTL1_HPH_CLK_EN_S 6
+#define TIMPANI_CDC_COMP_CTL1_HPH_CLK_EN_M 0x40
+#define TIMPANI_CDC_COMP_CTL1_LO_SOFT_RESET_S 5
+#define TIMPANI_CDC_COMP_CTL1_LO_SOFT_RESET_M 0x20
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_COMP_CTL1_HPH_SOFT_RESET_S 4
+#define TIMPANI_CDC_COMP_CTL1_HPH_SOFT_RESET_M 0x10
+#define TIMPANI_CDC_COMP_CTL1_LO_R_EN_S 3
+#define TIMPANI_CDC_COMP_CTL1_LO_R_EN_M 0x8
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_COMP_CTL1_LO_L_EN_S 2
+#define TIMPANI_CDC_COMP_CTL1_LO_L_EN_M 0x4
+#define TIMPANI_CDC_COMP_CTL1_HPH_R_EN_S 1
+#define TIMPANI_CDC_COMP_CTL1_HPH_R_EN_M 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_COMP_CTL1_HPH_L_EN_S 0
+#define TIMPANI_CDC_COMP_CTL1_HPH_L_EN_M 0x1
+#define TIMPANI_A_CDC_COMP_CTL2 (0xE5)
+#define TIMPANI_CDC_COMP_CTL2_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_COMP_CTL2_POR 0xe
+#define TIMPANI_CDC_COMP_CTL2_S 0
+#define TIMPANI_CDC_COMP_CTL2_M 0xF
+#define TIMPANI_CDC_COMP_CTL2_LINEOUT_IN_MUX_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_COMP_CTL2_LINEOUT_IN_MUX_M 0xC
+#define TIMPANI_CDC_COMP_CTL2_HPH_IN_MUX_S 0
+#define TIMPANI_CDC_COMP_CTL2_HPH_IN_MUX_M 0x3
+#define TIMPANI_A_CDC_COMP_PEAK_METER (0xE6)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_COMP_PEAK_METER_RWC "RW"
+#define TIMPANI_CDC_COMP_PEAK_METER_POR 0x9
+#define TIMPANI_CDC_COMP_PEAK_METER_S 0
+#define TIMPANI_CDC_COMP_PEAK_METER_M 0xF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_COMP_PEAK_METER_TIME_OUT_S 0
+#define TIMPANI_CDC_COMP_PEAK_METER_TIME_OUT_M 0xF
+#define TIMPANI_A_CDC_COMP_LEVEL_METER_CTL1 (0xE7)
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_RWC "RW"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_POR 0x7
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_S 0
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_M 0xF
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_DIV_FACTOR_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_DIV_FACTOR_M 0xF
+#define TIMPANI_A_CDC_COMP_LEVEL_METER_CTL2 (0xE8)
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RWC "RW"
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_POR 0x28
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_S 0
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_M 0xFF
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RESAMPLE_RATE_S 0
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RESAMPLE_RATE_M 0xFF
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_COMP_ZONE_SELECT (0xE9)
+#define TIMPANI_CDC_COMP_ZONE_SELECT_RWC "RW"
+#define TIMPANI_CDC_COMP_ZONE_SELECT_POR 0x3b
+#define TIMPANI_CDC_COMP_ZONE_SELECT_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_COMP_ZONE_SELECT_M 0x7F
+#define TIMPANI_CDC_COMP_ZONE_SELECT_ENTRY_S 3
+#define TIMPANI_CDC_COMP_ZONE_SELECT_ENTRY_M 0x78
+#define TIMPANI_CDC_COMP_ZONE_SELECT_SHIFT_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_COMP_ZONE_SELECT_SHIFT_M 0x7
+#define TIMPANI_A_CDC_COMP_ZC_MSB (0xEA)
+#define TIMPANI_CDC_COMP_ZC_MSB_RWC "RW"
+#define TIMPANI_CDC_COMP_ZC_MSB_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_COMP_ZC_MSB_S 0
+#define TIMPANI_CDC_COMP_ZC_MSB_M 0x7
+#define TIMPANI_CDC_COMP_ZC_MSB_DET_WINDOW_S 0
+#define TIMPANI_CDC_COMP_ZC_MSB_DET_WINDOW_M 0x7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_COMP_ZC_LSB (0xEB)
+#define TIMPANI_CDC_COMP_ZC_LSB_RWC "RW"
+#define TIMPANI_CDC_COMP_ZC_LSB_POR 0x1f
+#define TIMPANI_CDC_COMP_ZC_LSB_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_COMP_ZC_LSB_M 0xFF
+#define TIMPANI_CDC_COMP_ZC_LSB_DET_WINDOW_S 0
+#define TIMPANI_CDC_COMP_ZC_LSB_DET_WINDOW_M 0xFF
+#define TIMPANI_A_CDC_COMP_SHUT_DOWN (0xEC)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_COMP_SHUT_DOWN_RWC "RW"
+#define TIMPANI_CDC_COMP_SHUT_DOWN_POR 0x1b
+#define TIMPANI_CDC_COMP_SHUT_DOWN_S 0
+#define TIMPANI_CDC_COMP_SHUT_DOWN_M 0x3F
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_COMP_SHUT_DOWN_HPH_TIMEOUT_S 3
+#define TIMPANI_CDC_COMP_SHUT_DOWN_HPH_TIMEOUT_M 0x38
+#define TIMPANI_CDC_COMP_SHUT_DOWN_LO_TIMEOUT_S 0
+#define TIMPANI_CDC_COMP_SHUT_DOWN_LO_TIMEOUT_M 0x7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_A_CDC_COMP_SHUT_DOWN_STATUS (0xED)
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_RWC "RW"
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_POR 0
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_M 0xF
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_R_S 3
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_R_M 0x8
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_L_S 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_L_M 0x4
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_R_S 1
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_R_M 0x2
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_L_S 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_L_M 0x1
+#define TIMPANI_A_CDC_COMP_HALT (0xEE)
+#define TIMPANI_CDC_COMP_HALT_RWC "RW"
+#define TIMPANI_CDC_COMP_HALT_POR 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TIMPANI_CDC_COMP_HALT_S 0
+#define TIMPANI_CDC_COMP_HALT_M 0x1
+#define TIMPANI_CDC_COMP_HALT_COMPANDER_HALT_S 0
+#define TIMPANI_CDC_COMP_HALT_COMPANDER_HALT_M 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#endif
+
diff --git a/libc/kernel/common/linux/mfd/wcd9xxx/wcd9310_registers.h b/libc/kernel/common/linux/mfd/wcd9xxx/wcd9310_registers.h
new file mode 100644
index 0000000..d6e4cc0
--- /dev/null
+++ b/libc/kernel/common/linux/mfd/wcd9xxx/wcd9310_registers.h
@@ -0,0 +1,1381 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ***   To edit the content of this header, modify the corresponding
+ ***   source file (e.g. under external/kernel-headers/original/) then
+ ***   run bionic/libc/kernel/tools/update_all.py
+ ***
+ ***   Any manual change here will be lost the next time this script will
+ ***   be run. You've been warned!
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef TABLA_CODEC_DIGITAL_H
+#define TABLA_CODEC_DIGITAL_H
+#include <linux/mfd/wcd9xxx/wcd9xxx_registers.h>
+#define TABLA_A_CHIP_CTL WCD9XXX_A_CHIP_CTL
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CHIP_CTL__POR WCD9XXX_A_CHIP_CTL__POR
+#define TABLA_A_CHIP_STATUS WCD9XXX_A_CHIP_STATUS
+#define TABLA_A_CHIP_STATUS__POR WCD9XXX_A_CHIP_STATUS__POR
+#define TABLA_A_CHIP_ID_BYTE_0 WCD9XXX_A_CHIP_ID_BYTE_0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CHIP_ID_BYTE_0__POR WCD9XXX_A_CHIP_ID_BYTE_0__POR
+#define TABLA_A_CHIP_ID_BYTE_1 WCD9XXX_A_CHIP_ID_BYTE_1
+#define TABLA_A_CHIP_ID_BYTE_1__POR WCD9XXX_A_CHIP_ID_BYTE_1__POR
+#define TABLA_A_CHIP_ID_BYTE_2 WCD9XXX_A_CHIP_ID_BYTE_2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CHIP_ID_BYTE_2__POR WCD9XXX_A_CHIP_ID_BYTE_2__POR
+#define TABLA_A_CHIP_ID_BYTE_3 WCD9XXX_A_CHIP_ID_BYTE_3
+#define TABLA_A_CHIP_ID_BYTE_3__POR WCD9XXX_A_CHIP_ID_BYTE_3__POR
+#define TABLA_A_CHIP_VERSION WCD9XXX_A_CHIP_VERSION
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CHIP_VERSION__POR WCD9XXX_A_CHIP_VERSION__POR
+#define TABLA_A_SB_VERSION WCD9XXX_A_SB_VERSION
+#define TABLA_A_SB_VERSION__POR WCD9XXX_A_SB_VERSION__POR
+#define TABLA_A_SLAVE_ID_1 WCD9XXX_A_SLAVE_ID_1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_SLAVE_ID_1__POR WCD9XXX_A_SLAVE_ID_1__POR
+#define TABLA_A_SLAVE_ID_2 WCD9XXX_A_SLAVE_ID_2
+#define TABLA_A_SLAVE_ID_2__POR WCD9XXX_A_SLAVE_ID_2__POR
+#define TABLA_A_SLAVE_ID_3 WCD9XXX_A_SLAVE_ID_3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_SLAVE_ID_3__POR WCD9XXX_A_SLAVE_ID_3__POR
+#define TABLA_A_PIN_CTL_OE0 (0x10)
+#define TABLA_A_PIN_CTL_OE0__POR (0x00000000)
+#define TABLA_A_PIN_CTL_OE1 (0x11)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_PIN_CTL_OE1__POR (0x00000000)
+#define TABLA_A_PIN_CTL_DATA0 (0x12)
+#define TABLA_A_PIN_CTL_DATA0__POR (0x00000000)
+#define TABLA_A_PIN_CTL_DATA1 (0x13)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_PIN_CTL_DATA1__POR (0x00000000)
+#define TABLA_A_HDRIVE_GENERIC (0x18)
+#define TABLA_A_HDRIVE_GENERIC__POR (0x00000000)
+#define TABLA_A_HDRIVE_OVERRIDE (0x19)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_HDRIVE_OVERRIDE__POR (0x00000008)
+#define TABLA_A_ANA_CSR_WAIT_STATE (0x20)
+#define TABLA_A_ANA_CSR_WAIT_STATE__POR (0x00000044)
+#define TABLA_A_PROCESS_MONITOR_CTL0 (0x40)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_PROCESS_MONITOR_CTL0__POR (0x00000080)
+#define TABLA_A_PROCESS_MONITOR_CTL1 (0x41)
+#define TABLA_A_PROCESS_MONITOR_CTL1__POR (0x00000000)
+#define TABLA_A_PROCESS_MONITOR_CTL2 (0x42)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_PROCESS_MONITOR_CTL2__POR (0x00000000)
+#define TABLA_A_PROCESS_MONITOR_CTL3 (0x43)
+#define TABLA_A_PROCESS_MONITOR_CTL3__POR (0x00000001)
+#define TABLA_A_QFUSE_CTL (0x48)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_QFUSE_CTL__POR (0x00000000)
+#define TABLA_A_QFUSE_STATUS (0x49)
+#define TABLA_A_QFUSE_STATUS__POR (0x00000000)
+#define TABLA_A_QFUSE_DATA_OUT0 (0x4A)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_QFUSE_DATA_OUT0__POR (0x00000000)
+#define TABLA_A_QFUSE_DATA_OUT1 (0x4B)
+#define TABLA_A_QFUSE_DATA_OUT1__POR (0x00000000)
+#define TABLA_A_QFUSE_DATA_OUT2 (0x4C)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_QFUSE_DATA_OUT2__POR (0x00000000)
+#define TABLA_A_QFUSE_DATA_OUT3 (0x4D)
+#define TABLA_A_QFUSE_DATA_OUT3__POR (0x00000000)
+#define TABLA_A_CDC_CTL WCD9XXX_A_CDC_CTL
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CTL__POR WCD9XXX_A_CDC_CTL__POR
+#define TABLA_A_LEAKAGE_CTL WCD9XXX_A_LEAKAGE_CTL
+#define TABLA_A_LEAKAGE_CTL__POR WCD9XXX_A_LEAKAGE_CTL__POR
+#define TABLA_A_INTR_MODE (0x90)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_INTR_MODE__POR (0x00000000)
+#define TABLA_A_INTR_MASK0 (0x94)
+#define TABLA_A_INTR_MASK0__POR (0x000000ff)
+#define TABLA_A_INTR_MASK1 (0x95)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_INTR_MASK1__POR (0x000000ff)
+#define TABLA_A_INTR_MASK2 (0x96)
+#define TABLA_A_INTR_MASK2__POR (0x000000ff)
+#define TABLA_A_INTR_STATUS0 (0x98)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_INTR_STATUS0__POR (0x00000000)
+#define TABLA_A_INTR_STATUS1 (0x99)
+#define TABLA_A_INTR_STATUS1__POR (0x00000000)
+#define TABLA_A_INTR_STATUS2 (0x9A)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_INTR_STATUS2__POR (0x00000000)
+#define TABLA_A_INTR_CLEAR0 (0x9C)
+#define TABLA_A_INTR_CLEAR0__POR (0x00000000)
+#define TABLA_A_INTR_CLEAR1 (0x9D)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_INTR_CLEAR1__POR (0x00000000)
+#define TABLA_A_INTR_CLEAR2 (0x9E)
+#define TABLA_A_INTR_CLEAR2__POR (0x00000000)
+#define TABLA_A_INTR_LEVEL0 (0xA0)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_INTR_LEVEL0__POR (0x00000001)
+#define TABLA_A_INTR_LEVEL1 (0xA1)
+#define TABLA_A_INTR_LEVEL1__POR (0x00000000)
+#define TABLA_A_INTR_LEVEL2 (0xA2)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_INTR_LEVEL2__POR (0x00000000)
+#define TABLA_A_INTR_TEST0 (0xA4)
+#define TABLA_A_INTR_TEST0__POR (0x00000000)
+#define TABLA_A_INTR_TEST1 (0xA5)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_INTR_TEST1__POR (0x00000000)
+#define TABLA_A_INTR_TEST2 (0xA6)
+#define TABLA_A_INTR_TEST2__POR (0x00000000)
+#define TABLA_A_INTR_SET0 (0xA8)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_INTR_SET0__POR (0x00000000)
+#define TABLA_A_INTR_SET1 (0xA9)
+#define TABLA_A_INTR_SET1__POR (0x00000000)
+#define TABLA_A_INTR_SET2 (0xAA)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_INTR_SET2__POR (0x00000000)
+#define TABLA_A_CDC_TX_I2S_SCK_MODE (0xC0)
+#define TABLA_A_CDC_TX_I2S_SCK_MODE__POR (0x00000000)
+#define TABLA_A_CDC_TX_I2S_WS_MODE (0xC1)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX_I2S_WS_MODE__POR (0x00000000)
+#define TABLA_A_CDC_DMIC_DATA0_MODE (0xC4)
+#define TABLA_A_CDC_DMIC_DATA0_MODE__POR (0x00000000)
+#define TABLA_A_CDC_DMIC_CLK0_MODE (0xC5)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_DMIC_CLK0_MODE__POR (0x00000000)
+#define TABLA_A_CDC_DMIC_DATA1_MODE (0xC6)
+#define TABLA_A_CDC_DMIC_DATA1_MODE__POR (0x00000000)
+#define TABLA_A_CDC_DMIC_CLK1_MODE (0xC7)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_DMIC_CLK1_MODE__POR (0x00000000)
+#define TABLA_A_CDC_RX_I2S_SCK_MODE (0xC8)
+#define TABLA_A_CDC_RX_I2S_SCK_MODE__POR (0x00000000)
+#define TABLA_A_CDC_RX_I2S_WS_MODE (0xC9)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX_I2S_WS_MODE__POR (0x00000000)
+#define TABLA_A_CDC_DMIC_DATA2_MODE (0xCA)
+#define TABLA_A_CDC_DMIC_DATA2_MODE__POR (0x00000000)
+#define TABLA_A_CDC_DMIC_CLK2_MODE (0xCB)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_DMIC_CLK2_MODE__POR (0x00000000)
+#define TABLA_A_CDC_INTR_MODE (0xCC)
+#define TABLA_A_CDC_INTR_MODE__POR (0x00000000)
+#define TABLA_A_BIAS_REF_CTL (0x0100)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_BIAS_REF_CTL__POR (0x0000001C)
+#define TABLA_A_BIAS_CENTRAL_BG_CTL (0x0101)
+#define TABLA_A_BIAS_CENTRAL_BG_CTL__POR (0x00000050)
+#define TABLA_A_BIAS_PRECHRG_CTL (0x0102)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_BIAS_PRECHRG_CTL__POR (0x00000007)
+#define TABLA_A_BIAS_CURR_CTL_1 (0x0103)
+#define TABLA_A_BIAS_CURR_CTL_1__POR (0x00000052)
+#define TABLA_A_BIAS_CURR_CTL_2 (0x0104)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_BIAS_CURR_CTL_2__POR (0x00000000)
+#define TABLA_A_BIAS_CONFIG_MODE_BG_CTL (0x0105)
+#define TABLA_A_BIAS_CONFIG_MODE_BG_CTL__POR (0x00000016)
+#define TABLA_A_BIAS_BG_STATUS (0x0106)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_BIAS_BG_STATUS__POR (0x00000000)
+#define TABLA_A_CLK_BUFF_EN1 (0x0108)
+#define TABLA_A_CLK_BUFF_EN1__POR (0x00000004)
+#define TABLA_A_CLK_BUFF_EN2 (0x0109)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CLK_BUFF_EN2__POR (0x00000002)
+#define TABLA_A_LDO_H_MODE_1 (0x0110)
+#define TABLA_A_LDO_H_MODE_1__POR (0x00000065)
+#define TABLA_A_LDO_H_MODE_2 (0x0111)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_LDO_H_MODE_2__POR (0x000000A8)
+#define TABLA_A_LDO_H_LOOP_CTL (0x0112)
+#define TABLA_A_LDO_H_LOOP_CTL__POR (0x0000006B)
+#define TABLA_A_LDO_H_COMP_1 (0x0113)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_LDO_H_COMP_1__POR (0x00000084)
+#define TABLA_A_LDO_H_COMP_2 (0x0114)
+#define TABLA_A_LDO_H_COMP_2__POR (0x000000E0)
+#define TABLA_A_LDO_H_BIAS_1 (0x0115)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_LDO_H_BIAS_1__POR (0x0000006D)
+#define TABLA_A_LDO_H_BIAS_2 (0x0116)
+#define TABLA_A_LDO_H_BIAS_2__POR (0x000000A5)
+#define TABLA_A_LDO_H_BIAS_3 (0x0117)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_LDO_H_BIAS_3__POR (0x00000060)
+#define TABLA_A_LDO_L_MODE_1 (0x0118)
+#define TABLA_A_LDO_L_MODE_1__POR (0x00000028)
+#define TABLA_A_LDO_L_MODE_2 (0x0119)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_LDO_L_MODE_2__POR (0x000000A8)
+#define TABLA_A_LDO_L_LOOP_CTL (0x011A)
+#define TABLA_A_LDO_L_LOOP_CTL__POR (0x0000006D)
+#define TABLA_A_LDO_L_COMP_1 (0x011B)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_LDO_L_COMP_1__POR (0x00000031)
+#define TABLA_A_LDO_L_COMP_2 (0x011C)
+#define TABLA_A_LDO_L_COMP_2__POR (0x000000A0)
+#define TABLA_A_LDO_L_BIAS_1 (0x011D)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_LDO_L_BIAS_1__POR (0x0000006D)
+#define TABLA_A_LDO_L_BIAS_2 (0x011E)
+#define TABLA_A_LDO_L_BIAS_2__POR (0x00000065)
+#define TABLA_A_LDO_L_BIAS_3 (0x011F)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_LDO_L_BIAS_3__POR (0x00000050)
+#define TABLA_A_MICB_CFILT_1_CTL (0x0128)
+#define TABLA_A_MICB_CFILT_1_CTL__POR (0x00000040)
+#define TABLA_A_MICB_CFILT_1_VAL (0x0129)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_MICB_CFILT_1_VAL__POR (0x00000080)
+#define TABLA_A_MICB_CFILT_1_PRECHRG (0x012A)
+#define TABLA_A_MICB_CFILT_1_PRECHRG__POR (0x00000038)
+#define TABLA_A_MICB_1_CTL (0x012B)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_MICB_1_CTL__POR (0x00000016)
+#define TABLA_A_MICB_1_INT_RBIAS (0x012C)
+#define TABLA_A_MICB_1_INT_RBIAS__POR (0x00000000)
+#define TABLA_A_MICB_1_MBHC (0x012D)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_MICB_1_MBHC__POR (0x00000001)
+#define TABLA_A_MICB_CFILT_2_CTL (0x012E)
+#define TABLA_A_MICB_CFILT_2_CTL__POR (0x00000040)
+#define TABLA_A_MICB_CFILT_2_VAL (0x012F)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_MICB_CFILT_2_VAL__POR (0x00000080)
+#define TABLA_A_MICB_CFILT_2_PRECHRG (0x0130)
+#define TABLA_A_MICB_CFILT_2_PRECHRG__POR (0x00000038)
+#define TABLA_A_MICB_2_CTL (0x0131)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_MICB_2_CTL__POR (0x00000016)
+#define TABLA_A_MICB_2_INT_RBIAS (0x0132)
+#define TABLA_A_MICB_2_INT_RBIAS__POR (0x00000000)
+#define TABLA_A_MICB_2_MBHC (0x0133)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_MICB_2_MBHC__POR (0x00000000)
+#define TABLA_A_MICB_CFILT_3_CTL (0x0134)
+#define TABLA_A_MICB_CFILT_3_CTL__POR (0x00000040)
+#define TABLA_A_MICB_CFILT_3_VAL (0x0135)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_MICB_CFILT_3_VAL__POR (0x00000080)
+#define TABLA_A_MICB_CFILT_3_PRECHRG (0x0136)
+#define TABLA_A_MICB_CFILT_3_PRECHRG__POR (0x00000038)
+#define TABLA_A_MICB_3_CTL (0x0137)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_MICB_3_CTL__POR (0x00000016)
+#define TABLA_A_MICB_3_INT_RBIAS (0x0138)
+#define TABLA_A_MICB_3_INT_RBIAS__POR (0x00000000)
+#define TABLA_A_MICB_3_MBHC (0x0139)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_MICB_3_MBHC__POR (0x00000000)
+#define TABLA_1_A_MICB_4_CTL (0x013A)
+#define TABLA_2_A_MICB_4_CTL (0x013D)
+#define TABLA_A_MICB_4_CTL__POR (0x00000016)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_1_A_MICB_4_INT_RBIAS (0x013B)
+#define TABLA_2_A_MICB_4_INT_RBIAS (0x013E)
+#define TABLA_A_MICB_4_INT_RBIAS__POR (0x00000000)
+#define TABLA_1_A_MICB_4_MBHC (0x013C)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_2_A_MICB_4_MBHC (0x013F)
+#define TABLA_A_MICB_4_MBHC__POR (0x00000001)
+#define TABLA_A_TX_COM_BIAS (0x014C)
+#define TABLA_A_TX_COM_BIAS__POR (0x000000E0)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_MBHC_SCALING_MUX_1 (0x014E)
+#define TABLA_A_MBHC_SCALING_MUX_1__POR (0x00000000)
+#define TABLA_A_MBHC_SCALING_MUX_2 (0x014F)
+#define TABLA_A_MBHC_SCALING_MUX_2__POR (0x00000080)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_TX_SUP_SWITCH_CTRL_1 (0x0151)
+#define TABLA_A_TX_SUP_SWITCH_CTRL_1__POR (0x00000000)
+#define TABLA_A_TX_SUP_SWITCH_CTRL_2 (0x0152)
+#define TABLA_A_TX_SUP_SWITCH_CTRL_2__POR (0x00000080)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_TX_1_2_EN (0x0153)
+#define TABLA_A_TX_1_2_EN__POR (0x00000000)
+#define TABLA_A_TX_1_2_TEST_EN (0x0154)
+#define TABLA_A_TX_1_2_TEST_EN__POR (0x000000CC)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_TX_1_2_ADC_CH1 (0x0155)
+#define TABLA_A_TX_1_2_ADC_CH1__POR (0x00000044)
+#define TABLA_A_TX_1_2_ADC_CH2 (0x0156)
+#define TABLA_A_TX_1_2_ADC_CH2__POR (0x00000044)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_TX_1_2_ATEST_REFCTRL (0x0157)
+#define TABLA_A_TX_1_2_ATEST_REFCTRL__POR (0x00000000)
+#define TABLA_A_TX_1_2_TEST_CTL (0x0158)
+#define TABLA_A_TX_1_2_TEST_CTL__POR (0x00000038)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_TX_1_2_TEST_BLOCK_EN (0x0159)
+#define TABLA_A_TX_1_2_TEST_BLOCK_EN__POR (0x000000FF)
+#define TABLA_A_TX_1_2_TXFE_CLKDIV (0x015A)
+#define TABLA_A_TX_1_2_TXFE_CLKDIV__POR (0x000000EE)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_TX_1_2_SAR_ERR_CH1 (0x015B)
+#define TABLA_A_TX_1_2_SAR_ERR_CH1__POR (0x00000000)
+#define TABLA_A_TX_1_2_SAR_ERR_CH2 (0x015C)
+#define TABLA_A_TX_1_2_SAR_ERR_CH2__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_TX_3_4_EN (0x015D)
+#define TABLA_A_TX_3_4_EN__POR (0x00000000)
+#define TABLA_A_TX_3_4_TEST_EN (0x015E)
+#define TABLA_A_TX_3_4_TEST_EN__POR (0x000000CC)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_TX_3_4_ADC_CH3 (0x015F)
+#define TABLA_A_TX_3_4_ADC_CH3__POR (0x00000044)
+#define TABLA_A_TX_3_4_ADC_CH4 (0x0160)
+#define TABLA_A_TX_3_4_ADC_CH4__POR (0x00000044)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_TX_3_4_ATEST_REFCTRL (0x0161)
+#define TABLA_A_TX_3_4_ATEST_REFCTRL__POR (0x00000000)
+#define TABLA_A_TX_3_4_TEST_CTL (0x0162)
+#define TABLA_A_TX_3_4_TEST_CTL__POR (0x00000038)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_TX_3_4_TEST_BLOCK_EN (0x0163)
+#define TABLA_A_TX_3_4_TEST_BLOCK_EN__POR (0x000000FF)
+#define TABLA_A_TX_3_4_TXFE_CKDIV (0x0164)
+#define TABLA_A_TX_3_4_TXFE_CKDIV__POR (0x000000EE)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_TX_3_4_SAR_ERR_CH3 (0x0165)
+#define TABLA_A_TX_3_4_SAR_ERR_CH3__POR (0x00000000)
+#define TABLA_A_TX_3_4_SAR_ERR_CH4 (0x0166)
+#define TABLA_A_TX_3_4_SAR_ERR_CH4__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_TX_5_6_EN (0x0167)
+#define TABLA_A_TX_5_6_EN__POR (0x00000011)
+#define TABLA_A_TX_5_6_TEST_EN (0x0168)
+#define TABLA_A_TX_5_6_TEST_EN__POR (0x000000CC)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_TX_5_6_ADC_CH5 (0x0169)
+#define TABLA_A_TX_5_6_ADC_CH5__POR (0x00000044)
+#define TABLA_A_TX_5_6_ADC_CH6 (0x016A)
+#define TABLA_A_TX_5_6_ADC_CH6__POR (0x00000044)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_TX_5_6_ATEST_REFCTRL (0x016B)
+#define TABLA_A_TX_5_6_ATEST_REFCTRL__POR (0x00000000)
+#define TABLA_A_TX_5_6_TEST_CTL (0x016C)
+#define TABLA_A_TX_5_6_TEST_CTL__POR (0x00000038)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_TX_5_6_TEST_BLOCK_EN (0x016D)
+#define TABLA_A_TX_5_6_TEST_BLOCK_EN__POR (0x000000FF)
+#define TABLA_A_TX_5_6_TXFE_CKDIV (0x016E)
+#define TABLA_A_TX_5_6_TXFE_CKDIV__POR (0x000000EE)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_TX_5_6_SAR_ERR_CH5 (0x016F)
+#define TABLA_A_TX_5_6_SAR_ERR_CH5__POR (0x00000000)
+#define TABLA_A_TX_5_6_SAR_ERR_CH6 (0x0170)
+#define TABLA_A_TX_5_6_SAR_ERR_CH6__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_TX_7_MBHC_EN (0x0171)
+#define TABLA_A_TX_7_MBHC_EN__POR (0x0000000C)
+#define TABLA_A_TX_7_MBHC_ATEST_REFCTRL (0x0172)
+#define TABLA_A_TX_7_MBHC_ATEST_REFCTRL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_TX_7_MBHC_ADC (0x0173)
+#define TABLA_A_TX_7_MBHC_ADC__POR (0x00000044)
+#define TABLA_A_TX_7_MBHC_TEST_CTL (0x0174)
+#define TABLA_A_TX_7_MBHC_TEST_CTL__POR (0x00000038)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_TX_7_MBHC_SAR_ERR (0x0175)
+#define TABLA_A_TX_7_MBHC_SAR_ERR__POR (0x00000000)
+#define TABLA_A_TX_7_TXFE_CLKDIV (0x0176)
+#define TABLA_A_TX_7_TXFE_CLKDIV__POR (0x0000001C)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_AUX_COM_CTL (0x0180)
+#define TABLA_A_AUX_COM_CTL__POR (0x00000034)
+#define TABLA_A_AUX_COM_ATEST (0x0181)
+#define TABLA_A_AUX_COM_ATEST__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_AUX_L_EN (0x0182)
+#define TABLA_A_AUX_L_EN__POR (0x00000000)
+#define TABLA_A_AUX_L_GAIN (0x0183)
+#define TABLA_A_AUX_L_GAIN__POR (0x0000001F)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_AUX_L_PA_CONN (0x0184)
+#define TABLA_A_AUX_L_PA_CONN__POR (0x00000000)
+#define TABLA_A_AUX_L_PA_CONN_INV (0x0185)
+#define TABLA_A_AUX_L_PA_CONN_INV__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_AUX_R_EN (0x0186)
+#define TABLA_A_AUX_R_EN__POR (0x00000000)
+#define TABLA_A_AUX_R_GAIN (0x0187)
+#define TABLA_A_AUX_R_GAIN__POR (0x0000001F)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_AUX_R_PA_CONN (0x0188)
+#define TABLA_A_AUX_R_PA_CONN__POR (0x00000000)
+#define TABLA_A_AUX_R_PA_CONN_INV (0x0189)
+#define TABLA_A_AUX_R_PA_CONN_INV__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CP_EN (0x0192)
+#define TABLA_A_CP_EN__POR (0x000000E6)
+#define TABLA_A_CP_CLK (0x0193)
+#define TABLA_A_CP_CLK__POR (0x00000029)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CP_STATIC (0x0194)
+#define TABLA_A_CP_STATIC__POR (0x00000010)
+#define TABLA_A_CP_DCC1 (0x0195)
+#define TABLA_A_CP_DCC1__POR (0x00000052)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CP_DCC3 (0x0196)
+#define TABLA_A_CP_DCC3__POR (0x00000001)
+#define TABLA_A_CP_ATEST (0x0197)
+#define TABLA_A_CP_ATEST__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CP_DTEST (0x0198)
+#define TABLA_A_CP_DTEST__POR (0x00000000)
+#define TABLA_A_RX_COM_TIMER_DIV (0x019E)
+#define TABLA_A_RX_COM_TIMER_DIV__POR (0x000000E8)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_COM_OCP_CTL (0x019F)
+#define TABLA_A_RX_COM_OCP_CTL__POR (0x0000001F)
+#define TABLA_A_RX_COM_OCP_COUNT (0x01A0)
+#define TABLA_A_RX_COM_OCP_COUNT__POR (0x00000077)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_COM_DAC_CTL (0x01A1)
+#define TABLA_A_RX_COM_DAC_CTL__POR (0x00000000)
+#define TABLA_A_RX_COM_BIAS (0x01A2)
+#define TABLA_A_RX_COM_BIAS__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_HPH_BIAS_PA (0x01A6)
+#define TABLA_A_RX_HPH_BIAS_PA__POR (0x000000AA)
+#define TABLA_A_RX_HPH_BIAS_LDO (0x01A7)
+#define TABLA_A_RX_HPH_BIAS_LDO__POR (0x00000086)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_HPH_BIAS_CNP (0x01A8)
+#define TABLA_A_RX_HPH_BIAS_CNP__POR (0x0000008A)
+#define TABLA_A_RX_HPH_BIAS_WG (0x01A9)
+#define TABLA_A_RX_HPH_BIAS_WG__POR (0x00000060)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_HPH_OCP_CTL (0x01AA)
+#define TABLA_A_RX_HPH_OCP_CTL__POR (0x000000E8)
+#define TABLA_A_RX_HPH_CNP_EN (0x01AB)
+#define TABLA_A_RX_HPH_CNP_EN__POR (0x00000080)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_HPH_CNP_WG_CTL (0x01AC)
+#define TABLA_A_RX_HPH_CNP_WG_CTL__POR (0x000000DC)
+#define TABLA_A_RX_HPH_CNP_WG_TIME (0x01AD)
+#define TABLA_A_RX_HPH_CNP_WG_TIME__POR (0x00000028)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_HPH_L_GAIN (0x01AE)
+#define TABLA_A_RX_HPH_L_GAIN__POR (0x00000000)
+#define TABLA_A_RX_HPH_L_TEST (0x01AF)
+#define TABLA_A_RX_HPH_L_TEST__POR (0x00000001)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_HPH_L_PA_CTL (0x01B0)
+#define TABLA_A_RX_HPH_L_PA_CTL__POR (0x00000040)
+#define TABLA_A_RX_HPH_L_DAC_CTL (0x01B1)
+#define TABLA_A_RX_HPH_L_DAC_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_HPH_L_ATEST (0x01B2)
+#define TABLA_A_RX_HPH_L_ATEST__POR (0x00000000)
+#define TABLA_A_RX_HPH_L_STATUS (0x01B3)
+#define TABLA_A_RX_HPH_L_STATUS__POR (0x00000004)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_HPH_R_GAIN (0x01B4)
+#define TABLA_A_RX_HPH_R_GAIN__POR (0x00000000)
+#define TABLA_A_RX_HPH_R_TEST (0x01B5)
+#define TABLA_A_RX_HPH_R_TEST__POR (0x00000001)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_HPH_R_PA_CTL (0x01B6)
+#define TABLA_A_RX_HPH_R_PA_CTL__POR (0x00000040)
+#define TABLA_A_RX_HPH_R_DAC_CTL (0x01B7)
+#define TABLA_A_RX_HPH_R_DAC_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_HPH_R_ATEST (0x01B8)
+#define TABLA_A_RX_HPH_R_ATEST__POR (0x00000000)
+#define TABLA_A_RX_HPH_R_STATUS (0x01B9)
+#define TABLA_A_RX_HPH_R_STATUS__POR (0x00000004)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_EAR_BIAS_PA (0x01BA)
+#define TABLA_A_RX_EAR_BIAS_PA__POR (0x000000AA)
+#define TABLA_A_RX_EAR_BIAS_CMBUFF (0x01BB)
+#define TABLA_A_RX_EAR_BIAS_CMBUFF__POR (0x000000A0)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_EAR_EN (0x01BC)
+#define TABLA_A_RX_EAR_EN__POR (0x00000000)
+#define TABLA_A_RX_EAR_GAIN (0x01BD)
+#define TABLA_A_RX_EAR_GAIN__POR (0x00000008)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_EAR_CMBUFF (0x01BE)
+#define TABLA_A_RX_EAR_CMBUFF__POR (0x00000000)
+#define TABLA_A_RX_EAR_ICTL (0x01BF)
+#define TABLA_A_RX_EAR_ICTL__POR (0x00000040)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_EAR_CCOMP (0x01C0)
+#define TABLA_A_RX_EAR_CCOMP__POR (0x00000008)
+#define TABLA_A_RX_EAR_VCM (0x01C1)
+#define TABLA_A_RX_EAR_VCM__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_EAR_CNP (0x01C2)
+#define TABLA_A_RX_EAR_CNP__POR (0x00000080)
+#define TABLA_A_RX_EAR_ATEST (0x01C3)
+#define TABLA_A_RX_EAR_ATEST__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_EAR_STATUS (0x01C5)
+#define TABLA_A_RX_EAR_STATUS__POR (0x00000004)
+#define TABLA_A_RX_LINE_BIAS_PA (0x01C6)
+#define TABLA_A_RX_LINE_BIAS_PA__POR (0x000000AA)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_LINE_BIAS_DAC (0x01C7)
+#define TABLA_A_RX_LINE_BIAS_DAC__POR (0x000000A0)
+#define TABLA_A_RX_LINE_BIAS_CNP (0x01C8)
+#define TABLA_A_RX_LINE_BIAS_CNP__POR (0x0000003A)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_LINE_COM (0x01C9)
+#define TABLA_A_RX_LINE_COM__POR (0x00000000)
+#define TABLA_A_RX_LINE_CNP_EN (0x01CA)
+#define TABLA_A_RX_LINE_CNP_EN__POR (0x00000080)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_LINE_CNP_WG_CTL (0x01CB)
+#define TABLA_A_RX_LINE_CNP_WG_CTL__POR (0x0000001C)
+#define TABLA_A_RX_LINE_CNP_WG_TIME (0x01CC)
+#define TABLA_A_RX_LINE_CNP_WG_TIME__POR (0x00000064)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_LINE_1_GAIN (0x01CD)
+#define TABLA_A_RX_LINE_1_GAIN__POR (0x00000000)
+#define TABLA_A_RX_LINE_1_TEST (0x01CE)
+#define TABLA_A_RX_LINE_1_TEST__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_LINE_1_DAC_CTL (0x01CF)
+#define TABLA_A_RX_LINE_1_DAC_CTL__POR (0x0000000C)
+#define TABLA_A_RX_LINE_1_STATUS (0x01D0)
+#define TABLA_A_RX_LINE_1_STATUS__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_LINE_2_GAIN (0x01D1)
+#define TABLA_A_RX_LINE_2_GAIN__POR (0x00000000)
+#define TABLA_A_RX_LINE_2_TEST (0x01D2)
+#define TABLA_A_RX_LINE_2_TEST__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_LINE_2_DAC_CTL (0x01D3)
+#define TABLA_A_RX_LINE_2_DAC_CTL__POR (0x0000000C)
+#define TABLA_A_RX_LINE_2_STATUS (0x01D4)
+#define TABLA_A_RX_LINE_2_STATUS__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_LINE_3_GAIN (0x01D5)
+#define TABLA_A_RX_LINE_3_GAIN__POR (0x00000000)
+#define TABLA_A_RX_LINE_3_TEST (0x01D6)
+#define TABLA_A_RX_LINE_3_TEST__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_LINE_3_DAC_CTL (0x01D7)
+#define TABLA_A_RX_LINE_3_DAC_CTL__POR (0x0000000C)
+#define TABLA_A_RX_LINE_3_STATUS (0x01D8)
+#define TABLA_A_RX_LINE_3_STATUS__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_LINE_4_GAIN (0x01D9)
+#define TABLA_A_RX_LINE_4_GAIN__POR (0x00000000)
+#define TABLA_A_RX_LINE_4_TEST (0x01DA)
+#define TABLA_A_RX_LINE_4_TEST__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_LINE_4_DAC_CTL (0x01DB)
+#define TABLA_A_RX_LINE_4_DAC_CTL__POR (0x0000000C)
+#define TABLA_A_RX_LINE_4_STATUS (0x01DC)
+#define TABLA_A_RX_LINE_4_STATUS__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_LINE_5_GAIN (0x01DD)
+#define TABLA_A_RX_LINE_5_GAIN__POR (0x00000000)
+#define TABLA_A_RX_LINE_5_TEST (0x01DE)
+#define TABLA_A_RX_LINE_5_TEST__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_LINE_5_DAC_CTL (0x01DF)
+#define TABLA_A_RX_LINE_5_DAC_CTL__POR (0x0000000C)
+#define TABLA_A_RX_LINE_5_STATUS (0x01E0)
+#define TABLA_A_RX_LINE_5_STATUS__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_RX_LINE_CNP_DBG (0x01EC)
+#define TABLA_A_RX_LINE_CNP_DBG__POR (0x00000000)
+#define TABLA_A_MBHC_HPH (0x01ED)
+#define TABLA_A_MBHC_HPH__POR (0x00000048)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CONFIG_MODE_FREQ (0x01F7)
+#define TABLA_A_CONFIG_MODE_FREQ__POR (0x00000047)
+#define TABLA_A_CONFIG_MODE_TEST (0x01F8)
+#define TABLA_A_CONFIG_MODE_TEST__POR (0x0000000A)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CONFIG_MODE_STATUS (0x01F9)
+#define TABLA_A_CONFIG_MODE_STATUS__POR (0x0000001C)
+#define TABLA_A_CONFIG_MODE_TUNER (0x01FA)
+#define TABLA_A_CONFIG_MODE_TUNER__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_ANC1_CTL (0x00000200)
+#define TABLA_A_CDC_ANC1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_CTL (0x00000280)
+#define TABLA_A_CDC_ANC2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_ANC1_SHIFT (0x00000201)
+#define TABLA_A_CDC_ANC1_SHIFT__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_SHIFT (0x00000281)
+#define TABLA_A_CDC_ANC2_SHIFT__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_ANC1_FILT1_B1_CTL (0x00000202)
+#define TABLA_A_CDC_ANC1_FILT1_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_FILT1_B1_CTL (0x00000282)
+#define TABLA_A_CDC_ANC2_FILT1_B1_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_ANC1_FILT1_B2_CTL (0x00000203)
+#define TABLA_A_CDC_ANC1_FILT1_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_FILT1_B2_CTL (0x00000283)
+#define TABLA_A_CDC_ANC2_FILT1_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_ANC1_FILT1_B3_CTL (0x00000204)
+#define TABLA_A_CDC_ANC1_FILT1_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_FILT1_B3_CTL (0x00000284)
+#define TABLA_A_CDC_ANC2_FILT1_B3_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_ANC1_FILT1_B4_CTL (0x00000205)
+#define TABLA_A_CDC_ANC1_FILT1_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_FILT1_B4_CTL (0x00000285)
+#define TABLA_A_CDC_ANC2_FILT1_B4_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_ANC1_FILT2_B1_CTL (0x00000206)
+#define TABLA_A_CDC_ANC1_FILT2_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_FILT2_B1_CTL (0x00000286)
+#define TABLA_A_CDC_ANC2_FILT2_B1_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_ANC1_FILT2_B2_CTL (0x00000207)
+#define TABLA_A_CDC_ANC1_FILT2_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_FILT2_B2_CTL (0x00000287)
+#define TABLA_A_CDC_ANC2_FILT2_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_ANC1_FILT2_B3_CTL (0x00000208)
+#define TABLA_A_CDC_ANC1_FILT2_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_FILT2_B3_CTL (0x00000288)
+#define TABLA_A_CDC_ANC2_FILT2_B3_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_ANC1_SPARE (0x00000209)
+#define TABLA_A_CDC_ANC1_SPARE__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_SPARE (0x00000289)
+#define TABLA_A_CDC_ANC2_SPARE__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_ANC1_FILT3_CTL (0x0000020A)
+#define TABLA_A_CDC_ANC1_FILT3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_FILT3_CTL (0x0000028A)
+#define TABLA_A_CDC_ANC2_FILT3_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_ANC1_FILT4_CTL (0x0000020B)
+#define TABLA_A_CDC_ANC1_FILT4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_FILT4_CTL (0x0000028B)
+#define TABLA_A_CDC_ANC2_FILT4_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX1_VOL_CTL_TIMER (0x00000220)
+#define TABLA_A_CDC_TX1_VOL_CTL_TIMER__POR (0x00000000)
+#define TABLA_A_CDC_TX2_VOL_CTL_TIMER (0x00000228)
+#define TABLA_A_CDC_TX2_VOL_CTL_TIMER__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX3_VOL_CTL_TIMER (0x00000230)
+#define TABLA_A_CDC_TX3_VOL_CTL_TIMER__POR (0x00000000)
+#define TABLA_A_CDC_TX4_VOL_CTL_TIMER (0x00000238)
+#define TABLA_A_CDC_TX4_VOL_CTL_TIMER__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX5_VOL_CTL_TIMER (0x00000240)
+#define TABLA_A_CDC_TX5_VOL_CTL_TIMER__POR (0x00000000)
+#define TABLA_A_CDC_TX6_VOL_CTL_TIMER (0x00000248)
+#define TABLA_A_CDC_TX6_VOL_CTL_TIMER__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX7_VOL_CTL_TIMER (0x00000250)
+#define TABLA_A_CDC_TX7_VOL_CTL_TIMER__POR (0x00000000)
+#define TABLA_A_CDC_TX8_VOL_CTL_TIMER (0x00000258)
+#define TABLA_A_CDC_TX8_VOL_CTL_TIMER__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX9_VOL_CTL_TIMER (0x00000260)
+#define TABLA_A_CDC_TX9_VOL_CTL_TIMER__POR (0x00000000)
+#define TABLA_A_CDC_TX10_VOL_CTL_TIMER (0x00000268)
+#define TABLA_A_CDC_TX10_VOL_CTL_TIMER__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX1_VOL_CTL_GAIN (0x00000221)
+#define TABLA_A_CDC_TX1_VOL_CTL_GAIN__POR (0x00000000)
+#define TABLA_A_CDC_TX2_VOL_CTL_GAIN (0x00000229)
+#define TABLA_A_CDC_TX2_VOL_CTL_GAIN__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX3_VOL_CTL_GAIN (0x00000231)
+#define TABLA_A_CDC_TX3_VOL_CTL_GAIN__POR (0x00000000)
+#define TABLA_A_CDC_TX4_VOL_CTL_GAIN (0x00000239)
+#define TABLA_A_CDC_TX4_VOL_CTL_GAIN__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX5_VOL_CTL_GAIN (0x00000241)
+#define TABLA_A_CDC_TX5_VOL_CTL_GAIN__POR (0x00000000)
+#define TABLA_A_CDC_TX6_VOL_CTL_GAIN (0x00000249)
+#define TABLA_A_CDC_TX6_VOL_CTL_GAIN__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX7_VOL_CTL_GAIN (0x00000251)
+#define TABLA_A_CDC_TX7_VOL_CTL_GAIN__POR (0x00000000)
+#define TABLA_A_CDC_TX8_VOL_CTL_GAIN (0x00000259)
+#define TABLA_A_CDC_TX8_VOL_CTL_GAIN__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX9_VOL_CTL_GAIN (0x00000261)
+#define TABLA_A_CDC_TX9_VOL_CTL_GAIN__POR (0x00000000)
+#define TABLA_A_CDC_TX10_VOL_CTL_GAIN (0x00000269)
+#define TABLA_A_CDC_TX10_VOL_CTL_GAIN__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX1_VOL_CTL_CFG (0x00000222)
+#define TABLA_A_CDC_TX1_VOL_CTL_CFG__POR (0x00000000)
+#define TABLA_A_CDC_TX2_VOL_CTL_CFG (0x0000022A)
+#define TABLA_A_CDC_TX2_VOL_CTL_CFG__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX3_VOL_CTL_CFG (0x00000232)
+#define TABLA_A_CDC_TX3_VOL_CTL_CFG__POR (0x00000000)
+#define TABLA_A_CDC_TX4_VOL_CTL_CFG (0x0000023A)
+#define TABLA_A_CDC_TX4_VOL_CTL_CFG__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX5_VOL_CTL_CFG (0x00000242)
+#define TABLA_A_CDC_TX5_VOL_CTL_CFG__POR (0x00000000)
+#define TABLA_A_CDC_TX6_VOL_CTL_CFG (0x0000024A)
+#define TABLA_A_CDC_TX6_VOL_CTL_CFG__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX7_VOL_CTL_CFG (0x00000252)
+#define TABLA_A_CDC_TX7_VOL_CTL_CFG__POR (0x00000000)
+#define TABLA_A_CDC_TX8_VOL_CTL_CFG (0x0000025A)
+#define TABLA_A_CDC_TX8_VOL_CTL_CFG__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX9_VOL_CTL_CFG (0x00000262)
+#define TABLA_A_CDC_TX9_VOL_CTL_CFG__POR (0x00000000)
+#define TABLA_A_CDC_TX10_VOL_CTL_CFG (0x0000026A)
+#define TABLA_A_CDC_TX10_VOL_CTL_CFG__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX1_MUX_CTL (0x00000223)
+#define TABLA_A_CDC_TX1_MUX_CTL__POR (0x00000008)
+#define TABLA_A_CDC_TX2_MUX_CTL (0x0000022B)
+#define TABLA_A_CDC_TX2_MUX_CTL__POR (0x00000008)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX3_MUX_CTL (0x00000233)
+#define TABLA_A_CDC_TX3_MUX_CTL__POR (0x00000008)
+#define TABLA_A_CDC_TX4_MUX_CTL (0x0000023B)
+#define TABLA_A_CDC_TX4_MUX_CTL__POR (0x00000008)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX5_MUX_CTL (0x00000243)
+#define TABLA_A_CDC_TX5_MUX_CTL__POR (0x00000008)
+#define TABLA_A_CDC_TX6_MUX_CTL (0x0000024B)
+#define TABLA_A_CDC_TX6_MUX_CTL__POR (0x00000008)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX7_MUX_CTL (0x00000253)
+#define TABLA_A_CDC_TX7_MUX_CTL__POR (0x00000008)
+#define TABLA_A_CDC_TX8_MUX_CTL (0x0000025B)
+#define TABLA_A_CDC_TX8_MUX_CTL__POR (0x00000008)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX9_MUX_CTL (0x00000263)
+#define TABLA_A_CDC_TX9_MUX_CTL__POR (0x00000008)
+#define TABLA_A_CDC_TX10_MUX_CTL (0x0000026B)
+#define TABLA_A_CDC_TX10_MUX_CTL__POR (0x00000008)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX1_CLK_FS_CTL (0x00000224)
+#define TABLA_A_CDC_TX1_CLK_FS_CTL__POR (0x00000003)
+#define TABLA_A_CDC_TX2_CLK_FS_CTL (0x0000022C)
+#define TABLA_A_CDC_TX2_CLK_FS_CTL__POR (0x00000003)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX3_CLK_FS_CTL (0x00000234)
+#define TABLA_A_CDC_TX3_CLK_FS_CTL__POR (0x00000003)
+#define TABLA_A_CDC_TX4_CLK_FS_CTL (0x0000023C)
+#define TABLA_A_CDC_TX4_CLK_FS_CTL__POR (0x00000003)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX5_CLK_FS_CTL (0x00000244)
+#define TABLA_A_CDC_TX5_CLK_FS_CTL__POR (0x00000003)
+#define TABLA_A_CDC_TX6_CLK_FS_CTL (0x0000024C)
+#define TABLA_A_CDC_TX6_CLK_FS_CTL__POR (0x00000003)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX7_CLK_FS_CTL (0x00000254)
+#define TABLA_A_CDC_TX7_CLK_FS_CTL__POR (0x00000003)
+#define TABLA_A_CDC_TX8_CLK_FS_CTL (0x0000025C)
+#define TABLA_A_CDC_TX8_CLK_FS_CTL__POR (0x00000003)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX9_CLK_FS_CTL (0x00000264)
+#define TABLA_A_CDC_TX9_CLK_FS_CTL__POR (0x00000003)
+#define TABLA_A_CDC_TX10_CLK_FS_CTL (0x0000026C)
+#define TABLA_A_CDC_TX10_CLK_FS_CTL__POR (0x00000003)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX1_DMIC_CTL (0x00000225)
+#define TABLA_A_CDC_TX1_DMIC_CTL__POR (0x00000000)
+#define TABLA_A_CDC_TX2_DMIC_CTL (0x0000022D)
+#define TABLA_A_CDC_TX2_DMIC_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX3_DMIC_CTL (0x00000235)
+#define TABLA_A_CDC_TX3_DMIC_CTL__POR (0x00000000)
+#define TABLA_A_CDC_TX4_DMIC_CTL (0x0000023D)
+#define TABLA_A_CDC_TX4_DMIC_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX5_DMIC_CTL (0x00000245)
+#define TABLA_A_CDC_TX5_DMIC_CTL__POR (0x00000000)
+#define TABLA_A_CDC_TX6_DMIC_CTL (0x0000024D)
+#define TABLA_A_CDC_TX6_DMIC_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX7_DMIC_CTL (0x00000255)
+#define TABLA_A_CDC_TX7_DMIC_CTL__POR (0x00000000)
+#define TABLA_A_CDC_TX8_DMIC_CTL (0x0000025D)
+#define TABLA_A_CDC_TX8_DMIC_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TX9_DMIC_CTL (0x00000265)
+#define TABLA_A_CDC_TX9_DMIC_CTL__POR (0x00000000)
+#define TABLA_A_CDC_TX10_DMIC_CTL (0x0000026D)
+#define TABLA_A_CDC_TX10_DMIC_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_SRC1_PDA_CFG (0x000002A0)
+#define TABLA_A_CDC_SRC1_PDA_CFG__POR (0x00000000)
+#define TABLA_A_CDC_SRC2_PDA_CFG (0x000002A8)
+#define TABLA_A_CDC_SRC2_PDA_CFG__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_SRC1_FS_CTL (0x000002A1)
+#define TABLA_A_CDC_SRC1_FS_CTL__POR (0x0000001b)
+#define TABLA_A_CDC_SRC2_FS_CTL (0x000002A9)
+#define TABLA_A_CDC_SRC2_FS_CTL__POR (0x0000001b)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX1_B1_CTL (0x000002B0)
+#define TABLA_A_CDC_RX1_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX2_B1_CTL (0x000002B8)
+#define TABLA_A_CDC_RX2_B1_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX3_B1_CTL (0x000002C0)
+#define TABLA_A_CDC_RX3_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX4_B1_CTL (0x000002C8)
+#define TABLA_A_CDC_RX4_B1_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX5_B1_CTL (0x000002D0)
+#define TABLA_A_CDC_RX5_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX6_B1_CTL (0x000002D8)
+#define TABLA_A_CDC_RX6_B1_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX7_B1_CTL (0x000002E0)
+#define TABLA_A_CDC_RX7_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX1_B2_CTL (0x000002B1)
+#define TABLA_A_CDC_RX1_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX2_B2_CTL (0x000002B9)
+#define TABLA_A_CDC_RX2_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX3_B2_CTL (0x000002C1)
+#define TABLA_A_CDC_RX3_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX4_B2_CTL (0x000002C9)
+#define TABLA_A_CDC_RX4_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX5_B2_CTL (0x000002D1)
+#define TABLA_A_CDC_RX5_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX6_B2_CTL (0x000002D9)
+#define TABLA_A_CDC_RX6_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX7_B2_CTL (0x000002E1)
+#define TABLA_A_CDC_RX7_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX1_B3_CTL (0x000002B2)
+#define TABLA_A_CDC_RX1_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX2_B3_CTL (0x000002BA)
+#define TABLA_A_CDC_RX2_B3_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX3_B3_CTL (0x000002C2)
+#define TABLA_A_CDC_RX3_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX4_B3_CTL (0x000002CA)
+#define TABLA_A_CDC_RX4_B3_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX5_B3_CTL (0x000002D2)
+#define TABLA_A_CDC_RX5_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX6_B3_CTL (0x000002DA)
+#define TABLA_A_CDC_RX6_B3_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX7_B3_CTL (0x000002E2)
+#define TABLA_A_CDC_RX7_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX1_B4_CTL (0x000002B3)
+#define TABLA_A_CDC_RX1_B4_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX2_B4_CTL (0x000002BB)
+#define TABLA_A_CDC_RX2_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX3_B4_CTL (0x000002C3)
+#define TABLA_A_CDC_RX3_B4_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX4_B4_CTL (0x000002CB)
+#define TABLA_A_CDC_RX4_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX5_B4_CTL (0x000002D3)
+#define TABLA_A_CDC_RX5_B4_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX6_B4_CTL (0x000002DB)
+#define TABLA_A_CDC_RX6_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX7_B4_CTL (0x000002E3)
+#define TABLA_A_CDC_RX7_B4_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX1_B5_CTL (0x000002B4)
+#define TABLA_A_CDC_RX1_B5_CTL__POR (0x00000060)
+#define TABLA_A_CDC_RX2_B5_CTL (0x000002BC)
+#define TABLA_A_CDC_RX2_B5_CTL__POR (0x00000060)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX3_B5_CTL (0x000002C4)
+#define TABLA_A_CDC_RX3_B5_CTL__POR (0x00000060)
+#define TABLA_A_CDC_RX4_B5_CTL (0x000002CC)
+#define TABLA_A_CDC_RX4_B5_CTL__POR (0x00000060)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX5_B5_CTL (0x000002D4)
+#define TABLA_A_CDC_RX5_B5_CTL__POR (0x00000060)
+#define TABLA_A_CDC_RX6_B5_CTL (0x000002DC)
+#define TABLA_A_CDC_RX6_B5_CTL__POR (0x00000060)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX7_B5_CTL (0x000002E4)
+#define TABLA_A_CDC_RX7_B5_CTL__POR (0x00000060)
+#define TABLA_A_CDC_RX1_B6_CTL (0x000002B5)
+#define TABLA_A_CDC_RX1_B6_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX2_B6_CTL (0x000002BD)
+#define TABLA_A_CDC_RX2_B6_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX3_B6_CTL (0x000002C5)
+#define TABLA_A_CDC_RX3_B6_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX4_B6_CTL (0x000002CD)
+#define TABLA_A_CDC_RX4_B6_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX5_B6_CTL (0x000002D5)
+#define TABLA_A_CDC_RX5_B6_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX6_B6_CTL (0x000002DD)
+#define TABLA_A_CDC_RX6_B6_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX7_B6_CTL (0x000002E5)
+#define TABLA_A_CDC_RX7_B6_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX1_VOL_CTL_B1_CTL (0x000002B6)
+#define TABLA_A_CDC_RX1_VOL_CTL_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX2_VOL_CTL_B1_CTL (0x000002BE)
+#define TABLA_A_CDC_RX2_VOL_CTL_B1_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX3_VOL_CTL_B1_CTL (0x000002C6)
+#define TABLA_A_CDC_RX3_VOL_CTL_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX4_VOL_CTL_B1_CTL (0x000002CE)
+#define TABLA_A_CDC_RX4_VOL_CTL_B1_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX5_VOL_CTL_B1_CTL (0x000002D6)
+#define TABLA_A_CDC_RX5_VOL_CTL_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX6_VOL_CTL_B1_CTL (0x000002DE)
+#define TABLA_A_CDC_RX6_VOL_CTL_B1_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX7_VOL_CTL_B1_CTL (0x000002E6)
+#define TABLA_A_CDC_RX7_VOL_CTL_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX1_VOL_CTL_B2_CTL (0x000002B7)
+#define TABLA_A_CDC_RX1_VOL_CTL_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX2_VOL_CTL_B2_CTL (0x000002BF)
+#define TABLA_A_CDC_RX2_VOL_CTL_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX3_VOL_CTL_B2_CTL (0x000002C7)
+#define TABLA_A_CDC_RX3_VOL_CTL_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX4_VOL_CTL_B2_CTL (0x000002CF)
+#define TABLA_A_CDC_RX4_VOL_CTL_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX5_VOL_CTL_B2_CTL (0x000002D7)
+#define TABLA_A_CDC_RX5_VOL_CTL_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_RX6_VOL_CTL_B2_CTL (0x000002DF)
+#define TABLA_A_CDC_RX6_VOL_CTL_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX7_VOL_CTL_B2_CTL (0x000002E7)
+#define TABLA_A_CDC_RX7_VOL_CTL_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CLK_ANC_RESET_CTL (0x00000300)
+#define TABLA_A_CDC_CLK_ANC_RESET_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_RX_RESET_CTL (0x00000301)
+#define TABLA_A_CDC_CLK_RX_RESET_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CLK_TX_RESET_B1_CTL (0x00000302)
+#define TABLA_A_CDC_CLK_TX_RESET_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_TX_RESET_B2_CTL (0x00000303)
+#define TABLA_A_CDC_CLK_TX_RESET_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CLK_DMIC_CTL (0x00000304)
+#define TABLA_A_CDC_CLK_DMIC_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_RX_I2S_CTL (0x00000305)
+#define TABLA_A_CDC_CLK_RX_I2S_CTL__POR (0x00000003)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CLK_TX_I2S_CTL (0x00000306)
+#define TABLA_A_CDC_CLK_TX_I2S_CTL__POR (0x00000003)
+#define TABLA_A_CDC_CLK_OTHR_RESET_CTL (0x00000307)
+#define TABLA_A_CDC_CLK_OTHR_RESET_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL (0x00000308)
+#define TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_TX_CLK_EN_B2_CTL (0x00000309)
+#define TABLA_A_CDC_CLK_TX_CLK_EN_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CLK_OTHR_CTL (0x0000030A)
+#define TABLA_A_CDC_CLK_OTHR_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_RDAC_CLK_EN_CTL (0x0000030B)
+#define TABLA_A_CDC_CLK_RDAC_CLK_EN_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CLK_ANC_CLK_EN_CTL (0x0000030C)
+#define TABLA_A_CDC_CLK_ANC_CLK_EN_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_RX_B1_CTL (0x0000030D)
+#define TABLA_A_CDC_CLK_RX_B1_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CLK_RX_B2_CTL (0x0000030E)
+#define TABLA_A_CDC_CLK_RX_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_MCLK_CTL (0x0000030F)
+#define TABLA_A_CDC_CLK_MCLK_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CLK_PDM_CTL (0x00000310)
+#define TABLA_A_CDC_CLK_PDM_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_SD_CTL (0x00000311)
+#define TABLA_A_CDC_CLK_SD_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B1_CTL (0x00000320)
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B1_CTL__POR (0x00000007)
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B2_CTL (0x00000321)
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B2_CTL__POR (0x00000013)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B3_CTL (0x00000322)
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B3_CTL__POR (0x00000053)
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B4_CTL (0x00000323)
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B4_CTL__POR (0x0000007f)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CLSG_GAIN_THRESH_CTL (0x00000324)
+#define TABLA_A_CDC_CLSG_GAIN_THRESH_CTL__POR (0x00000026)
+#define TABLA_A_CDC_CLSG_TIMER_B1_CFG (0x00000325)
+#define TABLA_A_CDC_CLSG_TIMER_B1_CFG__POR (0x0000000a)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CLSG_TIMER_B2_CFG (0x00000326)
+#define TABLA_A_CDC_CLSG_TIMER_B2_CFG__POR (0x00000000)
+#define TABLA_A_CDC_CLSG_CTL (0x00000327)
+#define TABLA_A_CDC_CLSG_CTL__POR (0x00000013)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_IIR1_GAIN_B1_CTL (0x00000340)
+#define TABLA_A_CDC_IIR1_GAIN_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B1_CTL (0x00000350)
+#define TABLA_A_CDC_IIR2_GAIN_B1_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_IIR1_GAIN_B2_CTL (0x00000341)
+#define TABLA_A_CDC_IIR1_GAIN_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B2_CTL (0x00000351)
+#define TABLA_A_CDC_IIR2_GAIN_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_IIR1_GAIN_B3_CTL (0x00000342)
+#define TABLA_A_CDC_IIR1_GAIN_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B3_CTL (0x00000352)
+#define TABLA_A_CDC_IIR2_GAIN_B3_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_IIR1_GAIN_B4_CTL (0x00000343)
+#define TABLA_A_CDC_IIR1_GAIN_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B4_CTL (0x00000353)
+#define TABLA_A_CDC_IIR2_GAIN_B4_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_IIR1_GAIN_B5_CTL (0x00000344)
+#define TABLA_A_CDC_IIR1_GAIN_B5_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B5_CTL (0x00000354)
+#define TABLA_A_CDC_IIR2_GAIN_B5_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_IIR1_GAIN_B6_CTL (0x00000345)
+#define TABLA_A_CDC_IIR1_GAIN_B6_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B6_CTL (0x00000355)
+#define TABLA_A_CDC_IIR2_GAIN_B6_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_IIR1_GAIN_B7_CTL (0x00000346)
+#define TABLA_A_CDC_IIR1_GAIN_B7_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B7_CTL (0x00000356)
+#define TABLA_A_CDC_IIR2_GAIN_B7_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_IIR1_GAIN_B8_CTL (0x00000347)
+#define TABLA_A_CDC_IIR1_GAIN_B8_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B8_CTL (0x00000357)
+#define TABLA_A_CDC_IIR2_GAIN_B8_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_IIR1_CTL (0x00000348)
+#define TABLA_A_CDC_IIR1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_CTL (0x00000358)
+#define TABLA_A_CDC_IIR2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_IIR1_GAIN_TIMER_CTL (0x00000349)
+#define TABLA_A_CDC_IIR1_GAIN_TIMER_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_TIMER_CTL (0x00000359)
+#define TABLA_A_CDC_IIR2_GAIN_TIMER_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_IIR1_COEF_B1_CTL (0x0000034A)
+#define TABLA_A_CDC_IIR1_COEF_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_COEF_B1_CTL (0x0000035A)
+#define TABLA_A_CDC_IIR2_COEF_B1_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_IIR1_COEF_B2_CTL (0x0000034B)
+#define TABLA_A_CDC_IIR1_COEF_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_COEF_B2_CTL (0x0000035B)
+#define TABLA_A_CDC_IIR2_COEF_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_IIR1_COEF_B3_CTL (0x0000034C)
+#define TABLA_A_CDC_IIR1_COEF_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_COEF_B3_CTL (0x0000035C)
+#define TABLA_A_CDC_IIR2_COEF_B3_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_IIR1_COEF_B4_CTL (0x0000034D)
+#define TABLA_A_CDC_IIR1_COEF_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_COEF_B4_CTL (0x0000035D)
+#define TABLA_A_CDC_IIR2_COEF_B4_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_IIR1_COEF_B5_CTL (0x0000034E)
+#define TABLA_A_CDC_IIR1_COEF_B5_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_COEF_B5_CTL (0x0000035E)
+#define TABLA_A_CDC_IIR2_COEF_B5_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_TOP_GAIN_UPDATE (0x00000360)
+#define TABLA_A_CDC_TOP_GAIN_UPDATE__POR (0x00000000)
+#define TABLA_A_CDC_DEBUG_B1_CTL (0x00000368)
+#define TABLA_A_CDC_DEBUG_B1_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_DEBUG_B2_CTL (0x00000369)
+#define TABLA_A_CDC_DEBUG_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_DEBUG_B3_CTL (0x0000036A)
+#define TABLA_A_CDC_DEBUG_B3_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_DEBUG_B4_CTL (0x0000036B)
+#define TABLA_A_CDC_DEBUG_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_DEBUG_B5_CTL (0x0000036C)
+#define TABLA_A_CDC_DEBUG_B5_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_DEBUG_B6_CTL (0x0000036D)
+#define TABLA_A_CDC_DEBUG_B6_CTL__POR (0x00000000)
+#define TABLA_A_CDC_COMP1_B1_CTL (0x00000370)
+#define TABLA_A_CDC_COMP1_B1_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_COMP1_B2_CTL (0x00000371)
+#define TABLA_A_CDC_COMP1_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_COMP1_B3_CTL (0x00000372)
+#define TABLA_A_CDC_COMP1_B3_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_COMP1_B4_CTL (0x00000373)
+#define TABLA_A_CDC_COMP1_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_COMP1_B5_CTL (0x00000374)
+#define TABLA_A_CDC_COMP1_B5_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_COMP1_B6_CTL (0x00000375)
+#define TABLA_A_CDC_COMP1_B6_CTL__POR (0x00000000)
+#define TABLA_A_CDC_COMP1_SHUT_DOWN_STATUS (0x00000376)
+#define TABLA_A_CDC_COMP1_SHUT_DOWN_STATUS__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_COMP1_FS_CFG (0x00000377)
+#define TABLA_A_CDC_COMP1_FS_CFG__POR (0x00000000)
+#define TABLA_A_CDC_COMP2_B1_CTL (0x00000378)
+#define TABLA_A_CDC_COMP2_B1_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_COMP2_B2_CTL (0x00000379)
+#define TABLA_A_CDC_COMP2_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_COMP2_B3_CTL (0x0000037A)
+#define TABLA_A_CDC_COMP2_B3_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_COMP2_B4_CTL (0x0000037B)
+#define TABLA_A_CDC_COMP2_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_COMP2_B5_CTL (0x0000037C)
+#define TABLA_A_CDC_COMP2_B5_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_COMP2_B6_CTL (0x0000037D)
+#define TABLA_A_CDC_COMP2_B6_CTL__POR (0x00000000)
+#define TABLA_A_CDC_COMP2_SHUT_DOWN_STATUS (0x0000037E)
+#define TABLA_A_CDC_COMP2_SHUT_DOWN_STATUS__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_COMP2_FS_CFG (0x0000037F)
+#define TABLA_A_CDC_COMP2_FS_CFG__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX1_B1_CTL (0x00000380)
+#define TABLA_A_CDC_CONN_RX1_B1_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_RX1_B2_CTL (0x00000381)
+#define TABLA_A_CDC_CONN_RX1_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX1_B3_CTL (0x00000382)
+#define TABLA_A_CDC_CONN_RX1_B3_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_RX2_B1_CTL (0x00000383)
+#define TABLA_A_CDC_CONN_RX2_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX2_B2_CTL (0x00000384)
+#define TABLA_A_CDC_CONN_RX2_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_RX2_B3_CTL (0x00000385)
+#define TABLA_A_CDC_CONN_RX2_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX3_B1_CTL (0x00000386)
+#define TABLA_A_CDC_CONN_RX3_B1_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_RX3_B2_CTL (0x00000387)
+#define TABLA_A_CDC_CONN_RX3_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX3_B3_CTL (0x00000388)
+#define TABLA_A_CDC_CONN_RX3_B3_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_RX4_B1_CTL (0x00000389)
+#define TABLA_A_CDC_CONN_RX4_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX4_B2_CTL (0x0000038A)
+#define TABLA_A_CDC_CONN_RX4_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_RX5_B1_CTL (0x0000038B)
+#define TABLA_A_CDC_CONN_RX5_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX5_B2_CTL (0x0000038C)
+#define TABLA_A_CDC_CONN_RX5_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_RX6_B1_CTL (0x0000038D)
+#define TABLA_A_CDC_CONN_RX6_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX6_B2_CTL (0x0000038E)
+#define TABLA_A_CDC_CONN_RX6_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_RX7_B1_CTL (0x0000038F)
+#define TABLA_A_CDC_CONN_RX7_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX7_B2_CTL (0x00000390)
+#define TABLA_A_CDC_CONN_RX7_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_ANC_B1_CTL (0x00000391)
+#define TABLA_A_CDC_CONN_ANC_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_ANC_B2_CTL (0x00000392)
+#define TABLA_A_CDC_CONN_ANC_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_TX_B1_CTL (0x00000393)
+#define TABLA_A_CDC_CONN_TX_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_TX_B2_CTL (0x00000394)
+#define TABLA_A_CDC_CONN_TX_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_TX_B3_CTL (0x00000395)
+#define TABLA_A_CDC_CONN_TX_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_TX_B4_CTL (0x00000396)
+#define TABLA_A_CDC_CONN_TX_B4_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_EQ1_B1_CTL (0x00000397)
+#define TABLA_A_CDC_CONN_EQ1_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_EQ1_B2_CTL (0x00000398)
+#define TABLA_A_CDC_CONN_EQ1_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_EQ1_B3_CTL (0x00000399)
+#define TABLA_A_CDC_CONN_EQ1_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_EQ1_B4_CTL (0x0000039A)
+#define TABLA_A_CDC_CONN_EQ1_B4_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_EQ2_B1_CTL (0x0000039B)
+#define TABLA_A_CDC_CONN_EQ2_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_EQ2_B2_CTL (0x0000039C)
+#define TABLA_A_CDC_CONN_EQ2_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_EQ2_B3_CTL (0x0000039D)
+#define TABLA_A_CDC_CONN_EQ2_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_EQ2_B4_CTL (0x0000039E)
+#define TABLA_A_CDC_CONN_EQ2_B4_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_SRC1_B1_CTL (0x0000039F)
+#define TABLA_A_CDC_CONN_SRC1_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_SRC1_B2_CTL (0x000003A0)
+#define TABLA_A_CDC_CONN_SRC1_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_SRC2_B1_CTL (0x000003A1)
+#define TABLA_A_CDC_CONN_SRC2_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_SRC2_B2_CTL (0x000003A2)
+#define TABLA_A_CDC_CONN_SRC2_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_TX_SB_B1_CTL (0x000003A3)
+#define TABLA_A_CDC_CONN_TX_SB_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B2_CTL (0x000003A4)
+#define TABLA_A_CDC_CONN_TX_SB_B2_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_TX_SB_B3_CTL (0x000003A5)
+#define TABLA_A_CDC_CONN_TX_SB_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B4_CTL (0x000003A6)
+#define TABLA_A_CDC_CONN_TX_SB_B4_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_TX_SB_B5_CTL (0x000003A7)
+#define TABLA_A_CDC_CONN_TX_SB_B5_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B6_CTL (0x000003A8)
+#define TABLA_A_CDC_CONN_TX_SB_B6_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_TX_SB_B7_CTL (0x000003A9)
+#define TABLA_A_CDC_CONN_TX_SB_B7_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B8_CTL (0x000003AA)
+#define TABLA_A_CDC_CONN_TX_SB_B8_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_TX_SB_B9_CTL (0x000003AB)
+#define TABLA_A_CDC_CONN_TX_SB_B9_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B10_CTL (0x000003AC)
+#define TABLA_A_CDC_CONN_TX_SB_B10_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_TX_SB_B11_CTL (0x000003AD)
+#define TABLA_A_CDC_CONN_TX_SB_B11_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX_SB_B1_CTL (0x000003AE)
+#define TABLA_A_CDC_CONN_RX_SB_B1_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_RX_SB_B2_CTL (0x000003AF)
+#define TABLA_A_CDC_CONN_RX_SB_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_CLSG_CTL (0x000003B0)
+#define TABLA_A_CDC_CONN_CLSG_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_CONN_SPARE (0x000003B1)
+#define TABLA_A_CDC_CONN_SPARE__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_EN_CTL (0x000003C0)
+#define TABLA_A_CDC_MBHC_EN_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_MBHC_FEATURE_B1_CFG (0x000003C1)
+#define TABLA_A_CDC_MBHC_FEATURE_B1_CFG__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_FEATURE_B2_CFG (0x000003C2)
+#define TABLA_A_CDC_MBHC_FEATURE_B2_CFG__POR (0x00000006)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_MBHC_TIMER_B1_CTL (0x000003C3)
+#define TABLA_A_CDC_MBHC_TIMER_B1_CTL__POR (0x00000003)
+#define TABLA_A_CDC_MBHC_TIMER_B2_CTL (0x000003C4)
+#define TABLA_A_CDC_MBHC_TIMER_B2_CTL__POR (0x00000009)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_MBHC_TIMER_B3_CTL (0x000003C5)
+#define TABLA_A_CDC_MBHC_TIMER_B3_CTL__POR (0x0000001e)
+#define TABLA_A_CDC_MBHC_TIMER_B4_CTL (0x000003C6)
+#define TABLA_A_CDC_MBHC_TIMER_B4_CTL__POR (0x00000045)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_MBHC_TIMER_B5_CTL (0x000003C7)
+#define TABLA_A_CDC_MBHC_TIMER_B5_CTL__POR (0x00000004)
+#define TABLA_A_CDC_MBHC_TIMER_B6_CTL (0x000003C8)
+#define TABLA_A_CDC_MBHC_TIMER_B6_CTL__POR (0x00000078)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_MBHC_B1_STATUS (0x000003C9)
+#define TABLA_A_CDC_MBHC_B1_STATUS__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_B2_STATUS (0x000003CA)
+#define TABLA_A_CDC_MBHC_B2_STATUS__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_MBHC_B3_STATUS (0x000003CB)
+#define TABLA_A_CDC_MBHC_B3_STATUS__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_B4_STATUS (0x000003CC)
+#define TABLA_A_CDC_MBHC_B4_STATUS__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_MBHC_B5_STATUS (0x000003CD)
+#define TABLA_A_CDC_MBHC_B5_STATUS__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_B1_CTL (0x000003CE)
+#define TABLA_A_CDC_MBHC_B1_CTL__POR (0x000000c0)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_MBHC_B2_CTL (0x000003CF)
+#define TABLA_A_CDC_MBHC_B2_CTL__POR (0x0000005d)
+#define TABLA_A_CDC_MBHC_VOLT_B1_CTL (0x000003D0)
+#define TABLA_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_MBHC_VOLT_B2_CTL (0x000003D1)
+#define TABLA_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_VOLT_B3_CTL (0x000003D2)
+#define TABLA_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_MBHC_VOLT_B4_CTL (0x000003D3)
+#define TABLA_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_VOLT_B5_CTL (0x000003D4)
+#define TABLA_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_MBHC_VOLT_B6_CTL (0x000003D5)
+#define TABLA_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_VOLT_B7_CTL (0x000003D6)
+#define TABLA_A_CDC_MBHC_VOLT_B7_CTL__POR (0x000000ff)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_MBHC_VOLT_B8_CTL (0x000003D7)
+#define TABLA_A_CDC_MBHC_VOLT_B8_CTL__POR (0x00000007)
+#define TABLA_A_CDC_MBHC_VOLT_B9_CTL (0x000003D8)
+#define TABLA_A_CDC_MBHC_VOLT_B9_CTL__POR (0x000000ff)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_MBHC_VOLT_B10_CTL (0x000003D9)
+#define TABLA_A_CDC_MBHC_VOLT_B10_CTL__POR (0x0000007f)
+#define TABLA_A_CDC_MBHC_VOLT_B11_CTL (0x000003DA)
+#define TABLA_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_MBHC_VOLT_B12_CTL (0x000003DB)
+#define TABLA_A_CDC_MBHC_VOLT_B12_CTL__POR (0x00000080)
+#define TABLA_A_CDC_MBHC_CLK_CTL (0x000003DC)
+#define TABLA_A_CDC_MBHC_CLK_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_MBHC_INT_CTL (0x000003DD)
+#define TABLA_A_CDC_MBHC_INT_CTL__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_DEBUG_CTL (0x000003DE)
+#define TABLA_A_CDC_MBHC_DEBUG_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_A_CDC_MBHC_SPARE (0x000003DF)
+#define TABLA_A_CDC_MBHC_SPARE__POR (0x00000000)
+#define TABLA_SLIM_PGD_PORT_INT_EN0 (0x30)
+#define TABLA_SLIM_PGD_PORT_INT_STATUS0 (0x34)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_SLIM_PGD_PORT_INT_CLR0 (0x38)
+#define TABLA_SLIM_PGD_PORT_INT_SOURCE0 (0x60)
+#define TABLA_PACKED_REG_SIZE sizeof(u32)
+#define TABLA_CODEC_PACK_ENTRY(reg, mask, val) ((val & 0xff)|  ((mask & 0xff) << 8)|((reg & 0xffff) << 16))
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define TABLA_CODEC_UNPACK_ENTRY(packed, reg, mask, val)   do {   ((reg) = ((packed >> 16) & (0xffff)));   ((mask) = ((packed >> 8) & (0xff)));   ((val) = ((packed) & (0xff)));   } while (0);
+#endif
+
diff --git a/libc/kernel/common/linux/mfd/wcd9xxx/wcd9xxx_registers.h b/libc/kernel/common/linux/mfd/wcd9xxx/wcd9xxx_registers.h
new file mode 100644
index 0000000..04de85d
--- /dev/null
+++ b/libc/kernel/common/linux/mfd/wcd9xxx/wcd9xxx_registers.h
@@ -0,0 +1,55 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ***   To edit the content of this header, modify the corresponding
+ ***   source file (e.g. under external/kernel-headers/original/) then
+ ***   run bionic/libc/kernel/tools/update_all.py
+ ***
+ ***   Any manual change here will be lost the next time this script will
+ ***   be run. You've been warned!
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef WCD9XXX_CODEC_DIGITAL_H
+#define WCD9XXX_CODEC_DIGITAL_H
+#define WCD9XXX_A_CHIP_CTL (0x00)
+#define WCD9XXX_A_CHIP_CTL__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define WCD9XXX_A_CHIP_STATUS (0x01)
+#define WCD9XXX_A_CHIP_STATUS__POR (0x00000000)
+#define WCD9XXX_A_CHIP_ID_BYTE_0 (0x04)
+#define WCD9XXX_A_CHIP_ID_BYTE_0__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define WCD9XXX_A_CHIP_ID_BYTE_1 (0x05)
+#define WCD9XXX_A_CHIP_ID_BYTE_1__POR (0x00000000)
+#define WCD9XXX_A_CHIP_ID_BYTE_2 (0x06)
+#define WCD9XXX_A_CHIP_ID_BYTE_2__POR (0x00000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define WCD9XXX_A_CHIP_ID_BYTE_3 (0x07)
+#define WCD9XXX_A_CHIP_ID_BYTE_3__POR (0x00000001)
+#define WCD9XXX_A_CHIP_VERSION (0x08)
+#define WCD9XXX_A_CHIP_VERSION__POR (0x00000020)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define WCD9XXX_A_SB_VERSION (0x09)
+#define WCD9XXX_A_SB_VERSION__POR (0x00000010)
+#define WCD9XXX_A_SLAVE_ID_1 (0x0C)
+#define WCD9XXX_A_SLAVE_ID_1__POR (0x00000077)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define WCD9XXX_A_SLAVE_ID_2 (0x0D)
+#define WCD9XXX_A_SLAVE_ID_2__POR (0x00000066)
+#define WCD9XXX_A_SLAVE_ID_3 (0x0E)
+#define WCD9XXX_A_SLAVE_ID_3__POR (0x00000055)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define WCD9XXX_A_CDC_CTL (0x80)
+#define WCD9XXX_A_CDC_CTL__POR (0x00000000)
+#define WCD9XXX_A_LEAKAGE_CTL (0x88)
+#define WCD9XXX_A_LEAKAGE_CTL__POR (0x00000004)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#endif
+
diff --git a/libc/kernel/common/linux/msm_audio.h b/libc/kernel/common/linux/msm_audio.h
index 95dd427..2b42efc 100644
--- a/libc/kernel/common/linux/msm_audio.h
+++ b/libc/kernel/common/linux/msm_audio.h
@@ -21,69 +21,326 @@
 #include <linux/types.h>
 #include <linux/ioctl.h>
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#include <asm/sizes.h>
 #define AUDIO_IOCTL_MAGIC 'a'
 #define AUDIO_START _IOW(AUDIO_IOCTL_MAGIC, 0, unsigned)
 #define AUDIO_STOP _IOW(AUDIO_IOCTL_MAGIC, 1, unsigned)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define AUDIO_FLUSH _IOW(AUDIO_IOCTL_MAGIC, 2, unsigned)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define AUDIO_GET_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 3, unsigned)
 #define AUDIO_SET_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 4, unsigned)
 #define AUDIO_GET_STATS _IOR(AUDIO_IOCTL_MAGIC, 5, unsigned)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define AUDIO_ENABLE_AUDPP _IOW(AUDIO_IOCTL_MAGIC, 6, unsigned)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define AUDIO_SET_ADRC _IOW(AUDIO_IOCTL_MAGIC, 7, unsigned)
 #define AUDIO_SET_EQ _IOW(AUDIO_IOCTL_MAGIC, 8, unsigned)
 #define AUDIO_SET_RX_IIR _IOW(AUDIO_IOCTL_MAGIC, 9, unsigned)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define AUDIO_SET_VOLUME _IOW(AUDIO_IOCTL_MAGIC, 10, unsigned)
-#define AUDIO_ENABLE_AUDPRE _IOW(AUDIO_IOCTL_MAGIC, 11, unsigned)
-#define AUDIO_SET_AGC _IOW(AUDIO_IOCTL_MAGIC, 12, unsigned)
-#define AUDIO_SET_NS _IOW(AUDIO_IOCTL_MAGIC, 13, unsigned)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define AUDIO_SET_TX_IIR _IOW(AUDIO_IOCTL_MAGIC, 14, unsigned)
+#define AUDIO_PAUSE _IOW(AUDIO_IOCTL_MAGIC, 11, unsigned)
+#define AUDIO_PLAY_DTMF _IOW(AUDIO_IOCTL_MAGIC, 12, unsigned)
+#define AUDIO_GET_EVENT _IOR(AUDIO_IOCTL_MAGIC, 13, unsigned)
+#define AUDIO_ABORT_GET_EVENT _IOW(AUDIO_IOCTL_MAGIC, 14, unsigned)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_REGISTER_PMEM _IOW(AUDIO_IOCTL_MAGIC, 15, unsigned)
+#define AUDIO_DEREGISTER_PMEM _IOW(AUDIO_IOCTL_MAGIC, 16, unsigned)
+#define AUDIO_ASYNC_WRITE _IOW(AUDIO_IOCTL_MAGIC, 17, unsigned)
+#define AUDIO_ASYNC_READ _IOW(AUDIO_IOCTL_MAGIC, 18, unsigned)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_SET_INCALL _IOW(AUDIO_IOCTL_MAGIC, 19, struct msm_voicerec_mode)
+#define AUDIO_GET_NUM_SND_DEVICE _IOR(AUDIO_IOCTL_MAGIC, 20, unsigned)
+#define AUDIO_GET_SND_DEVICES _IOWR(AUDIO_IOCTL_MAGIC, 21,   struct msm_snd_device_list)
+#define AUDIO_ENABLE_SND_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 22, unsigned)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_DISABLE_SND_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 23, unsigned)
+#define AUDIO_ROUTE_STREAM _IOW(AUDIO_IOCTL_MAGIC, 24,   struct msm_audio_route_config)
+#define AUDIO_GET_PCM_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 30, unsigned)
+#define AUDIO_SET_PCM_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 31, unsigned)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_SWITCH_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 32, unsigned)
+#define AUDIO_SET_MUTE _IOW(AUDIO_IOCTL_MAGIC, 33, unsigned)
+#define AUDIO_UPDATE_ACDB _IOW(AUDIO_IOCTL_MAGIC, 34, unsigned)
+#define AUDIO_START_VOICE _IOW(AUDIO_IOCTL_MAGIC, 35, unsigned)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_STOP_VOICE _IOW(AUDIO_IOCTL_MAGIC, 36, unsigned)
+#define AUDIO_REINIT_ACDB _IOW(AUDIO_IOCTL_MAGIC, 39, unsigned)
+#define AUDIO_OUTPORT_FLUSH _IOW(AUDIO_IOCTL_MAGIC, 40, unsigned short)
+#define AUDIO_SET_ERR_THRESHOLD_VALUE _IOW(AUDIO_IOCTL_MAGIC, 41,   unsigned short)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_GET_BITSTREAM_ERROR_INFO _IOR(AUDIO_IOCTL_MAGIC, 42,   struct msm_audio_bitstream_error_info)
+#define AUDIO_SET_SRS_TRUMEDIA_PARAM _IOW(AUDIO_IOCTL_MAGIC, 43, unsigned)
+#define AUDIO_SET_STREAM_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 80,   struct msm_audio_stream_config)
+#define AUDIO_GET_STREAM_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 81,   struct msm_audio_stream_config)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_GET_SESSION_ID _IOR(AUDIO_IOCTL_MAGIC, 82, unsigned short)
+#define AUDIO_GET_STREAM_INFO _IOR(AUDIO_IOCTL_MAGIC, 83,   struct msm_audio_bitstream_info)
+#define AUDIO_SET_PAN _IOW(AUDIO_IOCTL_MAGIC, 84, unsigned)
+#define AUDIO_SET_QCONCERT_PLUS _IOW(AUDIO_IOCTL_MAGIC, 85, unsigned)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_SET_MBADRC _IOW(AUDIO_IOCTL_MAGIC, 86, unsigned)
+#define AUDIO_SET_VOLUME_PATH _IOW(AUDIO_IOCTL_MAGIC, 87,   struct msm_vol_info)
+#define AUDIO_SET_MAX_VOL_ALL _IOW(AUDIO_IOCTL_MAGIC, 88, unsigned)
+#define AUDIO_ENABLE_AUDPRE _IOW(AUDIO_IOCTL_MAGIC, 89, unsigned)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_SET_AGC _IOW(AUDIO_IOCTL_MAGIC, 90, unsigned)
+#define AUDIO_SET_NS _IOW(AUDIO_IOCTL_MAGIC, 91, unsigned)
+#define AUDIO_SET_TX_IIR _IOW(AUDIO_IOCTL_MAGIC, 92, unsigned)
+#define AUDIO_GET_BUF_CFG _IOW(AUDIO_IOCTL_MAGIC, 93,   struct msm_audio_buf_cfg)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_SET_BUF_CFG _IOW(AUDIO_IOCTL_MAGIC, 94,   struct msm_audio_buf_cfg)
+#define AUDIO_SET_ACDB_BLK _IOW(AUDIO_IOCTL_MAGIC, 95,   struct msm_acdb_cmd_device)
+#define AUDIO_GET_ACDB_BLK _IOW(AUDIO_IOCTL_MAGIC, 96,   struct msm_acdb_cmd_device)
+#define AUDIO_REGISTER_ION _IOW(AUDIO_IOCTL_MAGIC, 97, unsigned)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_DEREGISTER_ION _IOW(AUDIO_IOCTL_MAGIC, 98, unsigned)
+#define AUDIO_MAX_COMMON_IOCTL_NUM 100
+#define HANDSET_MIC 0x01
+#define HANDSET_SPKR 0x02
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define HEADSET_MIC 0x03
+#define HEADSET_SPKR_MONO 0x04
+#define HEADSET_SPKR_STEREO 0x05
+#define SPKR_PHONE_MIC 0x06
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define SPKR_PHONE_MONO 0x07
+#define SPKR_PHONE_STEREO 0x08
+#define BT_SCO_MIC 0x09
+#define BT_SCO_SPKR 0x0A
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define BT_A2DP_SPKR 0x0B
+#define TTY_HEADSET_MIC 0x0C
+#define TTY_HEADSET_SPKR 0x0D
+#define DEFAULT_TX 0x0E
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define DEFAULT_RX 0x0F
+#define BT_A2DP_TX 0x10
+#define HEADSET_MONO_PLUS_SPKR_MONO_RX 0x11
+#define HEADSET_MONO_PLUS_SPKR_STEREO_RX 0x12
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define HEADSET_STEREO_PLUS_SPKR_MONO_RX 0x13
+#define HEADSET_STEREO_PLUS_SPKR_STEREO_RX 0x14
+#define I2S_RX 0x20
+#define I2S_TX 0x21
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define ADRC_ENABLE 0x0001
+#define EQ_ENABLE 0x0002
+#define IIR_ENABLE 0x0004
+#define QCONCERT_PLUS_ENABLE 0x0008
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MBADRC_ENABLE 0x0010
+#define SRS_ENABLE 0x0020
+#define SRS_DISABLE 0x0040
+#define AGC_ENABLE 0x0001
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define NS_ENABLE 0x0002
+#define TX_IIR_ENABLE 0x0004
+#define FLUENCE_ENABLE 0x0008
+#define VOC_REC_UPLINK 0x00
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VOC_REC_DOWNLINK 0x01
+#define VOC_REC_BOTH 0x02
 struct msm_audio_config {
  uint32_t buffer_size;
- uint32_t buffer_count;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t buffer_count;
  uint32_t channel_count;
  uint32_t sample_rate;
  uint32_t type;
- uint32_t unused[3];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t meta_field;
+ uint32_t bits;
+ uint32_t unused[3];
 };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct msm_audio_stream_config {
+ uint32_t buffer_size;
+ uint32_t buffer_count;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct msm_audio_buf_cfg{
+ uint32_t meta_info_enable;
+ uint32_t frames_per_buf;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct msm_audio_stats {
  uint32_t byte_count;
  uint32_t sample_count;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  uint32_t unused[2];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
+struct msm_audio_ion_info {
+ int fd;
+ void *vaddr;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+struct msm_audio_pmem_info {
+ int fd;
+ void *vaddr;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+struct msm_audio_aio_buf {
+ void *buf_addr;
+ uint32_t buf_len;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t data_len;
+ void *private_data;
+ unsigned short mfield_sz;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SND_IOCTL_MAGIC 's'
 #define SND_MUTE_UNMUTED 0
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SND_MUTE_MUTED 1
+struct msm_mute_info {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t mute;
+ uint32_t path;
+};
+struct msm_vol_info {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t vol;
+ uint32_t path;
+};
+struct msm_voicerec_mode {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t rec_mode;
+};
 struct msm_snd_device_config {
  uint32_t device;
- uint32_t ear_mute;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t ear_mute;
  uint32_t mic_mute;
 };
 #define SND_SET_DEVICE _IOW(SND_IOCTL_MAGIC, 2, struct msm_device_config *)
-#define SND_METHOD_VOICE 0
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define SND_METHOD_VOICE 0
 struct msm_snd_volume_config {
  uint32_t device;
  uint32_t method;
- uint32_t volume;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t volume;
 };
 #define SND_SET_VOLUME _IOW(SND_IOCTL_MAGIC, 3, struct msm_snd_volume_config *)
 #define SND_GET_NUM_ENDPOINTS _IOR(SND_IOCTL_MAGIC, 4, unsigned *)
-struct msm_snd_endpoint {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct msm_snd_endpoint {
  int id;
  char name[64];
 };
-#define SND_GET_ENDPOINT _IOWR(SND_IOCTL_MAGIC, 5, struct msm_snd_endpoint *)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define SND_GET_ENDPOINT _IOWR(SND_IOCTL_MAGIC, 5, struct msm_snd_endpoint *)
+#define SND_AVC_CTL _IOW(SND_IOCTL_MAGIC, 6, unsigned *)
+#define SND_AGC_CTL _IOW(SND_IOCTL_MAGIC, 7, unsigned *)
+struct msm_audio_pcm_config {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t pcm_feedback;
+ uint32_t buffer_count;
+ uint32_t buffer_size;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_EVENT_SUSPEND 0
+#define AUDIO_EVENT_RESUME 1
+#define AUDIO_EVENT_WRITE_DONE 2
+#define AUDIO_EVENT_READ_DONE 3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_EVENT_STREAM_INFO 4
+#define AUDIO_EVENT_BITSTREAM_ERROR_INFO 5
+#define AUDIO_CODEC_TYPE_MP3 0
+#define AUDIO_CODEC_TYPE_AAC 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct msm_audio_bitstream_info {
+ uint32_t codec_type;
+ uint32_t chan_info;
+ uint32_t sample_rate;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t bit_stream_info;
+ uint32_t bit_rate;
+ uint32_t unused[3];
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct msm_audio_bitstream_error_info {
+ uint32_t dec_id;
+ uint32_t err_msg_indicator;
+ uint32_t err_type;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+union msm_audio_event_payload {
+ struct msm_audio_aio_buf aio_buf;
+ struct msm_audio_bitstream_info stream_info;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ struct msm_audio_bitstream_error_info error_info;
+ int reserved;
+};
+struct msm_audio_event {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ int event_type;
+ int timeout_ms;
+ union msm_audio_event_payload event_payload;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSM_SNDDEV_CAP_RX 0x1
+#define MSM_SNDDEV_CAP_TX 0x2
+#define MSM_SNDDEV_CAP_VOICE 0x4
+struct msm_snd_device_info {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t dev_id;
+ uint32_t dev_cap;
+ char dev_name[64];
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct msm_snd_device_list {
+ uint32_t num_dev;
+ struct msm_snd_device_info *list;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct msm_dtmf_config {
+ uint16_t path;
+ uint16_t dtmf_hi;
+ uint16_t dtmf_low;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint16_t duration;
+ uint16_t tx_gain;
+ uint16_t rx_gain;
+ uint16_t mixing;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+#define AUDIO_ROUTE_STREAM_VOICE_RX 0
+#define AUDIO_ROUTE_STREAM_VOICE_TX 1
+#define AUDIO_ROUTE_STREAM_PLAYBACK 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_ROUTE_STREAM_REC 3
+struct msm_audio_route_config {
+ uint32_t stream_type;
+ uint32_t stream_id;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t dev_id;
+};
+#define AUDIO_MAX_EQ_BANDS 12
+struct msm_audio_eq_band {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint16_t band_idx;
+ uint32_t filter_type;
+ uint32_t center_freq_hz;
+ uint32_t filter_gain;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t q_factor;
+} __attribute__ ((packed));
+struct msm_audio_eq_stream_config {
+ uint32_t enable;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t num_bands;
+ struct msm_audio_eq_band eq_bands[AUDIO_MAX_EQ_BANDS];
+} __attribute__ ((packed));
+struct msm_acdb_cmd_device {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t command_id;
+ uint32_t device_id;
+ uint32_t network_id;
+ uint32_t sample_rate_id;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t interface_id;
+ uint32_t algorithm_block_id;
+ uint32_t total_bytes;
+ uint32_t *phys_buf;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
 #endif
+
diff --git a/libc/kernel/common/linux/msm_audio_aac.h b/libc/kernel/common/linux/msm_audio_aac.h
new file mode 100644
index 0000000..2aaa1c4
--- /dev/null
+++ b/libc/kernel/common/linux/msm_audio_aac.h
@@ -0,0 +1,80 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ***   To edit the content of this header, modify the corresponding
+ ***   source file (e.g. under external/kernel-headers/original/) then
+ ***   run bionic/libc/kernel/tools/update_all.py
+ ***
+ ***   Any manual change here will be lost the next time this script will
+ ***   be run. You've been warned!
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __MSM_AUDIO_AAC_H
+#define __MSM_AUDIO_AAC_H
+#include <linux/msm_audio.h>
+#define AUDIO_SET_AAC_CONFIG _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_GET_AAC_CONFIG _IOR(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned)
+#define AUDIO_SET_AAC_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+3), struct msm_audio_aac_enc_config)
+#define AUDIO_GET_AAC_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+4), struct msm_audio_aac_enc_config)
+#define AUDIO_AAC_FORMAT_ADTS -1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_AAC_FORMAT_RAW 0x0000
+#define AUDIO_AAC_FORMAT_PSUEDO_RAW 0x0001
+#define AUDIO_AAC_FORMAT_LOAS 0x0002
+#define AUDIO_AAC_FORMAT_ADIF 0x0003
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_AAC_OBJECT_LC 0x0002
+#define AUDIO_AAC_OBJECT_LTP 0x0004
+#define AUDIO_AAC_OBJECT_ERLC 0x0011
+#define AUDIO_AAC_OBJECT_BSAC 0x0016
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_AAC_SEC_DATA_RES_ON 0x0001
+#define AUDIO_AAC_SEC_DATA_RES_OFF 0x0000
+#define AUDIO_AAC_SCA_DATA_RES_ON 0x0001
+#define AUDIO_AAC_SCA_DATA_RES_OFF 0x0000
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_AAC_SPEC_DATA_RES_ON 0x0001
+#define AUDIO_AAC_SPEC_DATA_RES_OFF 0x0000
+#define AUDIO_AAC_SBR_ON_FLAG_ON 0x0001
+#define AUDIO_AAC_SBR_ON_FLAG_OFF 0x0000
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_AAC_SBR_PS_ON_FLAG_ON 0x0001
+#define AUDIO_AAC_SBR_PS_ON_FLAG_OFF 0x0000
+#define AUDIO_AAC_DUAL_MONO_PL_PR 0
+#define AUDIO_AAC_DUAL_MONO_SL_SR 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_AAC_DUAL_MONO_SL_PR 2
+#define AUDIO_AAC_DUAL_MONO_PL_SR 3
+struct msm_audio_aac_config {
+ signed short format;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned short audio_object;
+ unsigned short ep_config;
+ unsigned short aac_section_data_resilience_flag;
+ unsigned short aac_scalefactor_data_resilience_flag;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned short aac_spectral_data_resilience_flag;
+ unsigned short sbr_on_flag;
+ unsigned short sbr_ps_on_flag;
+ unsigned short dual_mono_mode;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned short channel_configuration;
+};
+struct msm_audio_aac_enc_config {
+ uint32_t channels;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t sample_rate;
+ uint32_t bit_rate;
+ uint32_t stream_format;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#endif
+
diff --git a/libc/kernel/common/linux/msm_audio_acdb.h b/libc/kernel/common/linux/msm_audio_acdb.h
new file mode 100644
index 0000000..831e265
--- /dev/null
+++ b/libc/kernel/common/linux/msm_audio_acdb.h
@@ -0,0 +1,71 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ***   To edit the content of this header, modify the corresponding
+ ***   source file (e.g. under external/kernel-headers/original/) then
+ ***   run bionic/libc/kernel/tools/update_all.py
+ ***
+ ***   Any manual change here will be lost the next time this script will
+ ***   be run. You've been warned!
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __MSM_AUDIO_ACDB_H
+#define __MSM_AUDIO_ACDB_H
+#include <linux/msm_audio.h>
+#define AUDIO_SET_VOCPROC_CAL _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_SET_VOCPROC_STREAM_CAL _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned)
+#define AUDIO_SET_VOCPROC_VOL_CAL _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+2), unsigned)
+#define AUDIO_SET_AUDPROC_RX_CAL _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+3), unsigned)
+#define AUDIO_SET_AUDPROC_RX_STREAM_CAL _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+4), unsigned)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_SET_AUDPROC_RX_VOL_CAL _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+5), unsigned)
+#define AUDIO_SET_AUDPROC_TX_CAL _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+6), unsigned)
+#define AUDIO_SET_AUDPROC_TX_STREAM_CAL _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+7), unsigned)
+#define AUDIO_SET_AUDPROC_TX_VOL_CAL _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+8), unsigned)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_SET_SIDETONE_CAL _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+9), unsigned)
+#define AUDIO_SET_ANC_CAL _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+10), unsigned)
+#define AUDIO_SET_VOICE_RX_TOPOLOGY _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+11), unsigned)
+#define AUDIO_SET_VOICE_TX_TOPOLOGY _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+12), unsigned)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_SET_ADM_RX_TOPOLOGY _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+13), unsigned)
+#define AUDIO_SET_ADM_TX_TOPOLOGY _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+14), unsigned)
+#define AUDIO_SET_ASM_TOPOLOGY _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+15), unsigned)
+#define AUDIO_SET_AFE_TX_CAL _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+16), unsigned)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_SET_AFE_RX_CAL _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+17), unsigned)
+#define AUDIO_MAX_ACDB_IOCTL (AUDIO_MAX_COMMON_IOCTL_NUM+30)
+struct cal_block {
+ uint32_t cal_size;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t cal_offset;
+};
+struct sidetone_cal {
+ uint16_t enable;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint16_t gain;
+};
+#define AUDIO_GET_RTAC_ADM_INFO _IOR(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_ACDB_IOCTL+1), unsigned)
+#define AUDIO_GET_RTAC_VOICE_INFO _IOR(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_ACDB_IOCTL+2), unsigned)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_GET_RTAC_ADM_CAL _IOWR(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_ACDB_IOCTL+3), unsigned)
+#define AUDIO_SET_RTAC_ADM_CAL _IOWR(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_ACDB_IOCTL+4), unsigned)
+#define AUDIO_GET_RTAC_ASM_CAL _IOWR(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_ACDB_IOCTL+5), unsigned)
+#define AUDIO_SET_RTAC_ASM_CAL _IOWR(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_ACDB_IOCTL+6), unsigned)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_GET_RTAC_CVS_CAL _IOWR(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_ACDB_IOCTL+7), unsigned)
+#define AUDIO_SET_RTAC_CVS_CAL _IOWR(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_ACDB_IOCTL+8), unsigned)
+#define AUDIO_GET_RTAC_CVP_CAL _IOWR(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_ACDB_IOCTL+9), unsigned)
+#define AUDIO_SET_RTAC_CVP_CAL _IOWR(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_ACDB_IOCTL+10), unsigned)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_MAX_RTAC_IOCTL (AUDIO_MAX_ACDB_IOCTL+20)
+#endif
+
diff --git a/libc/kernel/common/linux/msm_audio_wma.h b/libc/kernel/common/linux/msm_audio_wma.h
new file mode 100644
index 0000000..fc89cb6
--- /dev/null
+++ b/libc/kernel/common/linux/msm_audio_wma.h
@@ -0,0 +1,49 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ***   To edit the content of this header, modify the corresponding
+ ***   source file (e.g. under external/kernel-headers/original/) then
+ ***   run bionic/libc/kernel/tools/update_all.py
+ ***
+ ***   Any manual change here will be lost the next time this script will
+ ***   be run. You've been warned!
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __MSM_AUDIO_WMA_H
+#define __MSM_AUDIO_WMA_H
+#define AUDIO_GET_WMA_CONFIG _IOR(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned)
+#define AUDIO_SET_WMA_CONFIG _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AUDIO_GET_WMA_CONFIG_V2 _IOR(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+2), struct msm_audio_wma_config_v2)
+#define AUDIO_SET_WMA_CONFIG_V2 _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+3), struct msm_audio_wma_config_v2)
+struct msm_audio_wma_config {
+ unsigned short armdatareqthr;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned short channelsdecoded;
+ unsigned short wmabytespersec;
+ unsigned short wmasamplingfreq;
+ unsigned short wmaencoderopts;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+struct msm_audio_wma_config_v2 {
+ unsigned short format_tag;
+ unsigned short numchannels;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t samplingrate;
+ uint32_t avgbytespersecond;
+ unsigned short block_align;
+ unsigned short validbitspersample;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t channelmask;
+ unsigned short encodeopt;
+};
+#endif
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+
diff --git a/libc/kernel/common/linux/msm_audio_wmapro.h b/libc/kernel/common/linux/msm_audio_wmapro.h
new file mode 100644
index 0000000..3e5d7c6
--- /dev/null
+++ b/libc/kernel/common/linux/msm_audio_wmapro.h
@@ -0,0 +1,41 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ***   To edit the content of this header, modify the corresponding
+ ***   source file (e.g. under external/kernel-headers/original/) then
+ ***   run bionic/libc/kernel/tools/update_all.py
+ ***
+ ***   Any manual change here will be lost the next time this script will
+ ***   be run. You've been warned!
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __MSM_AUDIO_WMAPRO_H
+#define __MSM_AUDIO_WMAPRO_H
+#define AUDIO_GET_WMAPRO_CONFIG _IOR(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned)
+#define AUDIO_SET_WMAPRO_CONFIG _IOW(AUDIO_IOCTL_MAGIC,   (AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct msm_audio_wmapro_config {
+ unsigned short armdatareqthr;
+ uint8_t validbitspersample;
+ uint8_t numchannels;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned short formattag;
+ unsigned short samplingrate;
+ unsigned short avgbytespersecond;
+ unsigned short asfpacketlength;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned short channelmask;
+ unsigned short encodeopt;
+ unsigned short advancedencodeopt;
+ uint32_t advancedencodeopt2;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+#endif
+
diff --git a/libc/kernel/common/linux/msm_charm.h b/libc/kernel/common/linux/msm_charm.h
new file mode 100644
index 0000000..171084a
--- /dev/null
+++ b/libc/kernel/common/linux/msm_charm.h
@@ -0,0 +1,39 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ***   To edit the content of this header, modify the corresponding
+ ***   source file (e.g. under external/kernel-headers/original/) then
+ ***   run bionic/libc/kernel/tools/update_all.py
+ ***
+ ***   Any manual change here will be lost the next time this script will
+ ***   be run. You've been warned!
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef _ARCH_ARM_MACH_MSM_MDM_IOCTLS_H
+#define _ARXH_ARM_MACH_MSM_MDM_IOCTLS_H
+#define CHARM_CODE 0xCC
+#define WAKE_CHARM _IO(CHARM_CODE, 1)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define RESET_CHARM _IO(CHARM_CODE, 2)
+#define CHECK_FOR_BOOT _IOR(CHARM_CODE, 3, int)
+#define WAIT_FOR_BOOT _IO(CHARM_CODE, 4)
+#define NORMAL_BOOT_DONE _IOW(CHARM_CODE, 5, int)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define RAM_DUMP_DONE _IOW(CHARM_CODE, 6, int)
+#define WAIT_FOR_RESTART _IOR(CHARM_CODE, 7, int)
+#define GET_DLOAD_STATUS _IOR(CHARM_CODE, 8, int)
+enum charm_boot_type {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ CHARM_NORMAL_BOOT = 0,
+ CHARM_RAM_DUMPS,
+};
+#endif
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+
diff --git a/libc/kernel/common/linux/msm_dsps.h b/libc/kernel/common/linux/msm_dsps.h
new file mode 100644
index 0000000..1978328
--- /dev/null
+++ b/libc/kernel/common/linux/msm_dsps.h
@@ -0,0 +1,31 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ***   To edit the content of this header, modify the corresponding
+ ***   source file (e.g. under external/kernel-headers/original/) then
+ ***   run bionic/libc/kernel/tools/update_all.py
+ ***
+ ***   Any manual change here will be lost the next time this script will
+ ***   be run. You've been warned!
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef _DSPS_H_
+#define _DSPS_H_
+#include <linux/ioctl.h>
+#define DSPS_IOCTL_MAGIC 'd'
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define DSPS_IOCTL_ON _IO(DSPS_IOCTL_MAGIC, 1)
+#define DSPS_IOCTL_OFF _IO(DSPS_IOCTL_MAGIC, 2)
+#define DSPS_IOCTL_READ_SLOW_TIMER _IOR(DSPS_IOCTL_MAGIC, 3, unsigned int*)
+#define DSPS_IOCTL_READ_FAST_TIMER _IOR(DSPS_IOCTL_MAGIC, 4, unsigned int*)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define DSPS_IOCTL_RESET _IO(DSPS_IOCTL_MAGIC, 5)
+#endif
+
diff --git a/libc/kernel/common/linux/msm_ion.h b/libc/kernel/common/linux/msm_ion.h
new file mode 100644
index 0000000..b6625f6
--- /dev/null
+++ b/libc/kernel/common/linux/msm_ion.h
@@ -0,0 +1,105 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ***   To edit the content of this header, modify the corresponding
+ ***   source file (e.g. under external/kernel-headers/original/) then
+ ***   run bionic/libc/kernel/tools/update_all.py
+ ***
+ ***   Any manual change here will be lost the next time this script will
+ ***   be run. You've been warned!
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __LINUX_MSM_ION_H__
+#define __LINUX_MSM_ION_H__
+#include <linux/ion.h>
+enum msm_ion_heap_types {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ ION_HEAP_TYPE_IOMMU = ION_HEAP_TYPE_CUSTOM + 1,
+ ION_HEAP_TYPE_CP = ION_HEAP_TYPE_CUSTOM + 2,
+};
+enum ion_heap_ids {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ INVALID_HEAP_ID = -1,
+ ION_CP_MM_HEAP_ID = 8,
+ ION_CP_MFC_HEAP_ID = 12,
+ ION_CP_WB_HEAP_ID = 16,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ ION_CAMERA_HEAP_ID = 20,
+ ION_SF_HEAP_ID = 24,
+ ION_IOMMU_HEAP_ID = 25,
+ ION_QSECOM_HEAP_ID = 27,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ ION_AUDIO_HEAP_ID = 28,
+ ION_MM_FIRMWARE_HEAP_ID = 29,
+ ION_SYSTEM_HEAP_ID = 30,
+ ION_HEAP_ID_RESERVED = 31
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+enum ion_fixed_position {
+ NOT_FIXED,
+ FIXED_LOW,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ FIXED_MIDDLE,
+ FIXED_HIGH,
+};
+enum cp_mem_usage {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ VIDEO_BITSTREAM = 0x1,
+ VIDEO_PIXEL = 0x2,
+ VIDEO_NONPIXEL = 0x3,
+ MAX_USAGE = 0x4,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ UNKNOWN = 0x7FFFFFFF,
+};
+#define ION_HEAP_CP_MASK (1 << ION_HEAP_TYPE_CP)
+#define ION_SECURE (1 << ION_HEAP_ID_RESERVED)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define ION_HEAP(bit) (1 << (bit))
+#define ION_VMALLOC_HEAP_NAME "vmalloc"
+#define ION_AUDIO_HEAP_NAME "audio"
+#define ION_SF_HEAP_NAME "sf"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define ION_MM_HEAP_NAME "mm"
+#define ION_CAMERA_HEAP_NAME "camera_preview"
+#define ION_IOMMU_HEAP_NAME "iommu"
+#define ION_MFC_HEAP_NAME "mfc"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define ION_WB_HEAP_NAME "wb"
+#define ION_MM_FIRMWARE_HEAP_NAME "mm_fw"
+#define ION_QSECOM_HEAP_NAME "qsecom"
+#define ION_FMEM_HEAP_NAME "fmem"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define CACHED 1
+#define UNCACHED 0
+#define ION_CACHE_SHIFT 0
+#define ION_SET_CACHE(__cache) ((__cache) << ION_CACHE_SHIFT)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define ION_IS_CACHED(__flags) ((__flags) & (1 << ION_CACHE_SHIFT))
+struct ion_flush_data {
+ struct ion_handle *handle;
+ int fd;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ void *vaddr;
+ unsigned int offset;
+ unsigned int length;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct ion_flag_data {
+ struct ion_handle *handle;
+ unsigned long flags;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define ION_IOC_CLEAN_CACHES _IOWR(ION_IOC_MAGIC, 7,   struct ion_flush_data)
+#define ION_IOC_INV_CACHES _IOWR(ION_IOC_MAGIC, 8,   struct ion_flush_data)
+#define ION_IOC_CLEAN_INV_CACHES _IOWR(ION_IOC_MAGIC, 9,   struct ion_flush_data)
+#define ION_IOC_GET_FLAGS _IOWR(ION_IOC_MAGIC, 10,   struct ion_flag_data)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#endif
+
diff --git a/libc/kernel/common/linux/msm_kgsl.h b/libc/kernel/common/linux/msm_kgsl.h
index ca5c96e..9721549 100644
--- a/libc/kernel/common/linux/msm_kgsl.h
+++ b/libc/kernel/common/linux/msm_kgsl.h
@@ -18,26 +18,66 @@
  ****************************************************************************/
 #ifndef _MSM_KGSL_H
 #define _MSM_KGSL_H
-#define KGSL_CONTEXT_SAVE_GMEM 1
-#define KGSL_CONTEXT_NO_GMEM_ALLOC 2
+#define KGSL_VERSION_MAJOR 3
+#define KGSL_VERSION_MINOR 11
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define KGSL_CONTEXT_SAVE_GMEM 0x00000001
+#define KGSL_CONTEXT_NO_GMEM_ALLOC 0x00000002
+#define KGSL_CONTEXT_SUBMIT_IB_LIST 0x00000004
+#define KGSL_CONTEXT_CTX_SWITCH 0x00000008
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define KGSL_CONTEXT_PREAMBLE 0x00000010
+#define KGSL_CONTEXT_TRASH_STATE 0x00000020
+#define KGSL_CONTEXT_PER_CONTEXT_TS 0x00000040
+#define KGSL_CONTEXT_INVALID 0xffffffff
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define KGSL_MEMFLAGS_GPUREADONLY 0x01000000
 #define KGSL_FLAGS_NORMALMODE 0x00000000
 #define KGSL_FLAGS_SAFEMODE 0x00000001
 #define KGSL_FLAGS_INITIALIZED0 0x00000002
-#define KGSL_FLAGS_INITIALIZED 0x00000004
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define KGSL_FLAGS_INITIALIZED 0x00000004
 #define KGSL_FLAGS_STARTED 0x00000008
 #define KGSL_FLAGS_ACTIVE 0x00000010
 #define KGSL_FLAGS_RESERVED0 0x00000020
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define KGSL_FLAGS_RESERVED1 0x00000040
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define KGSL_FLAGS_RESERVED2 0x00000080
-enum kgsl_deviceid {
- KGSL_DEVICE_ANY = 0x00000000,
- KGSL_DEVICE_YAMATO = 0x00000001,
+#define KGSL_FLAGS_SOFT_RESET 0x00000100
+#define KGSL_FLAGS_PER_CONTEXT_TIMESTAMPS 0x00000200
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- KGSL_DEVICE_G12 = 0x00000002,
- KGSL_DEVICE_MAX = 0x00000002
+#define KGSL_CLK_SRC 0x00000001
+#define KGSL_CLK_CORE 0x00000002
+#define KGSL_CLK_IFACE 0x00000004
+#define KGSL_CLK_MEM 0x00000008
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define KGSL_CLK_MEM_IFACE 0x00000010
+#define KGSL_CLK_AXI 0x00000020
+enum kgsl_ctx_reset_stat {
+ KGSL_CTX_STAT_NO_ERROR = 0x00000000,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ KGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT = 0x00000001,
+ KGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT = 0x00000002,
+ KGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT = 0x00000003
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define KGSL_MAX_PWRLEVELS 5
+#define KGSL_CONVERT_TO_MBPS(val)   (val*1000*1000U)
+enum kgsl_deviceid {
+ KGSL_DEVICE_3D0 = 0x00000000,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ KGSL_DEVICE_2D0 = 0x00000001,
+ KGSL_DEVICE_2D1 = 0x00000002,
+ KGSL_DEVICE_MAX = 0x00000003
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+enum kgsl_user_mem_type {
+ KGSL_USER_MEM_TYPE_PMEM = 0x00000000,
+ KGSL_USER_MEM_TYPE_ASHMEM = 0x00000001,
+ KGSL_USER_MEM_TYPE_ADDR = 0x00000002,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ KGSL_USER_MEM_TYPE_ION = 0x00000003,
+ KGSL_USER_MEM_TYPE_MAX = 0x00000004,
 };
 struct kgsl_devinfo {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -46,7 +86,7 @@
  unsigned int mmu_enabled;
  unsigned int gmem_gpubaseaddr;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int gmem_hostbaseaddr;
+ unsigned int gpu_id;
  unsigned int gmem_sizebytes;
 };
 struct kgsl_devmemstore {
@@ -61,69 +101,99 @@
  volatile unsigned int ref_wait_ts;
  unsigned int sbz4;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned int current_context;
+ unsigned int sbz5;
 };
-#define KGSL_DEVICE_MEMSTORE_OFFSET(field)   offsetof(struct kgsl_devmemstore, field)
+#define KGSL_MEMSTORE_OFFSET(ctxt_id, field)   ((ctxt_id)*sizeof(struct kgsl_devmemstore) +   offsetof(struct kgsl_devmemstore, field))
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 enum kgsl_timestamp_type {
  KGSL_TIMESTAMP_CONSUMED = 0x00000001,
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  KGSL_TIMESTAMP_RETIRED = 0x00000002,
- KGSL_TIMESTAMP_MAX = 0x00000002,
+ KGSL_TIMESTAMP_QUEUED = 0x00000003,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 enum kgsl_property_type {
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  KGSL_PROP_DEVICE_INFO = 0x00000001,
  KGSL_PROP_DEVICE_SHADOW = 0x00000002,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  KGSL_PROP_DEVICE_POWER = 0x00000003,
  KGSL_PROP_SHMEM = 0x00000004,
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  KGSL_PROP_SHMEM_APERTURES = 0x00000005,
  KGSL_PROP_MMU_ENABLE = 0x00000006,
- KGSL_PROP_INTERRUPT_WAITS = 0x00000007,
-};
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ KGSL_PROP_INTERRUPT_WAITS = 0x00000007,
+ KGSL_PROP_VERSION = 0x00000008,
+ KGSL_PROP_GPU_RESET_STAT = 0x00000009,
+ KGSL_PROP_PWRCTRL = 0x0000000E,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
 struct kgsl_shadowprop {
  unsigned int gpuaddr;
  unsigned int size;
- unsigned int flags;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned int flags;
+};
+struct kgsl_pwrlevel {
+ unsigned int gpu_freq;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned int bus_freq;
+ unsigned int io_fraction;
+};
+struct kgsl_version {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned int drv_major;
+ unsigned int drv_minor;
+ unsigned int dev_major;
+ unsigned int dev_minor;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+struct kgsl_ibdesc {
+ unsigned int gpuaddr;
+ void *hostptr;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned int sizedwords;
+ unsigned int ctrl;
 };
 #define KGSL_IOC_TYPE 0x09
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct kgsl_device_getproperty {
  unsigned int type;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  void *value;
  unsigned int sizebytes;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define IOCTL_KGSL_DEVICE_GETPROPERTY   _IOWR(KGSL_IOC_TYPE, 0x2, struct kgsl_device_getproperty)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-struct kgsl_device_regread {
- unsigned int offsetwords;
- unsigned int value;
-};
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IOCTL_KGSL_DEVICE_REGREAD   _IOWR(KGSL_IOC_TYPE, 0x3, struct kgsl_device_regread)
 struct kgsl_device_waittimestamp {
  unsigned int timestamp;
- unsigned int timeout;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned int timeout;
 };
 #define IOCTL_KGSL_DEVICE_WAITTIMESTAMP   _IOW(KGSL_IOC_TYPE, 0x6, struct kgsl_device_waittimestamp)
+struct kgsl_device_waittimestamp_ctxtid {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned int context_id;
+ unsigned int timestamp;
+ unsigned int timeout;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP_CTXTID   _IOW(KGSL_IOC_TYPE, 0x7, struct kgsl_device_waittimestamp_ctxtid)
 struct kgsl_ringbuffer_issueibcmds {
  unsigned int drawctxt_id;
+ unsigned int ibdesc_addr;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int ibaddr;
- unsigned int sizedwords;
+ unsigned int numibs;
  unsigned int timestamp;
  unsigned int flags;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define IOCTL_KGSL_RINGBUFFER_ISSUEIBCMDS   _IOWR(KGSL_IOC_TYPE, 0x10, struct kgsl_ringbuffer_issueibcmds)
 struct kgsl_cmdstream_readtimestamp {
  unsigned int type;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned int timestamp;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
-#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP   _IOR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp)
+#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_OLD   _IOR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp)
+#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP   _IOWR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp)
 struct kgsl_cmdstream_freememontimestamp {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned int gpuaddr;
@@ -131,18 +201,48 @@
  unsigned int timestamp;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP   _IOR(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp)
+#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP   _IOW(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp)
+#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_OLD   _IOR(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp)
 struct kgsl_drawctxt_create {
  unsigned int flags;
- unsigned int drawctxt_id;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned int drawctxt_id;
 };
 #define IOCTL_KGSL_DRAWCTXT_CREATE   _IOWR(KGSL_IOC_TYPE, 0x13, struct kgsl_drawctxt_create)
 struct kgsl_drawctxt_destroy {
- unsigned int drawctxt_id;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned int drawctxt_id;
 };
 #define IOCTL_KGSL_DRAWCTXT_DESTROY   _IOW(KGSL_IOC_TYPE, 0x14, struct kgsl_drawctxt_destroy)
+struct kgsl_map_user_mem {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ int fd;
+ unsigned int gpuaddr;
+ unsigned int len;
+ unsigned int offset;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned int hostptr;
+ enum kgsl_user_mem_type memtype;
+ unsigned int reserved;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define IOCTL_KGSL_MAP_USER_MEM   _IOWR(KGSL_IOC_TYPE, 0x15, struct kgsl_map_user_mem)
+struct kgsl_cmdstream_readtimestamp_ctxtid {
+ unsigned int context_id;
+ unsigned int type;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned int timestamp;
+};
+#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_CTXTID   _IOWR(KGSL_IOC_TYPE, 0x16, struct kgsl_cmdstream_readtimestamp_ctxtid)
+struct kgsl_cmdstream_freememontimestamp_ctxtid {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned int context_id;
+ unsigned int gpuaddr;
+ unsigned int type;
+ unsigned int timestamp;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_CTXTID   _IOW(KGSL_IOC_TYPE, 0x17,   struct kgsl_cmdstream_freememontimestamp_ctxtid)
 struct kgsl_sharedmem_from_pmem {
  int pmem_fd;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -157,49 +257,110 @@
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define IOCTL_KGSL_SHAREDMEM_FREE   _IOW(KGSL_IOC_TYPE, 0x21, struct kgsl_sharedmem_free)
+struct kgsl_cff_user_event {
+ unsigned char cff_opcode;
+ unsigned int op1;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned int op2;
+ unsigned int op3;
+ unsigned int op4;
+ unsigned int op5;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned int __pad[2];
+};
+#define IOCTL_KGSL_CFF_USER_EVENT   _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_cff_user_event)
 struct kgsl_gmem_desc {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned int x;
  unsigned int y;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned int width;
  unsigned int height;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned int pitch;
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct kgsl_buffer_desc {
  void *hostptr;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned int gpuaddr;
  int size;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned int format;
  unsigned int pitch;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned int enabled;
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct kgsl_bind_gmem_shadow {
  unsigned int drawctxt_id;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  struct kgsl_gmem_desc gmem_desc;
  unsigned int shadow_x;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned int shadow_y;
  struct kgsl_buffer_desc shadow_buffer;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned int buffer_id;
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW   _IOW(KGSL_IOC_TYPE, 0x22, struct kgsl_bind_gmem_shadow)
 struct kgsl_sharedmem_from_vmalloc {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned int gpuaddr;
  unsigned int hostptr;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int force_no_low_watermark;
+ unsigned int flags;
 };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC   _IOWR(KGSL_IOC_TYPE, 0x23, struct kgsl_sharedmem_from_vmalloc)
 #define IOCTL_KGSL_SHAREDMEM_FLUSH_CACHE   _IOW(KGSL_IOC_TYPE, 0x24, struct kgsl_sharedmem_free)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct kgsl_drawctxt_set_bin_base_offset {
  unsigned int drawctxt_id;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned int offset;
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define IOCTL_KGSL_DRAWCTXT_SET_BIN_BASE_OFFSET   _IOW(KGSL_IOC_TYPE, 0x25, struct kgsl_drawctxt_set_bin_base_offset)
+enum kgsl_cmdwindow_type {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ KGSL_CMDWINDOW_MIN = 0x00000000,
+ KGSL_CMDWINDOW_2D = 0x00000000,
+ KGSL_CMDWINDOW_3D = 0x00000001,
+ KGSL_CMDWINDOW_MMU = 0x00000002,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ KGSL_CMDWINDOW_ARBITER = 0x000000FF,
+ KGSL_CMDWINDOW_MAX = 0x000000FF,
+};
+struct kgsl_cmdwindow_write {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ enum kgsl_cmdwindow_type target;
+ unsigned int addr;
+ unsigned int data;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define IOCTL_KGSL_CMDWINDOW_WRITE   _IOW(KGSL_IOC_TYPE, 0x2e, struct kgsl_cmdwindow_write)
+struct kgsl_gpumem_alloc {
+ unsigned long gpuaddr;
+ size_t size;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned int flags;
+};
+#define IOCTL_KGSL_GPUMEM_ALLOC   _IOWR(KGSL_IOC_TYPE, 0x2f, struct kgsl_gpumem_alloc)
+struct kgsl_cff_syncmem {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned int gpuaddr;
+ unsigned int len;
+ unsigned int __pad[2];
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define IOCTL_KGSL_CFF_SYNCMEM   _IOW(KGSL_IOC_TYPE, 0x30, struct kgsl_cff_syncmem)
+struct kgsl_timestamp_event {
+ int type;
+ unsigned int timestamp;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned int context_id;
+ void *priv;
+ size_t len;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define IOCTL_KGSL_TIMESTAMP_EVENT   _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_timestamp_event)
+#define KGSL_TIMESTAMP_EVENT_GENLOCK 1
+struct kgsl_timestamp_event_genlock {
+ int handle;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+#define IOCTL_KGSL_SETPROPERTY   _IOW(KGSL_IOC_TYPE, 0x32, struct kgsl_device_getproperty)
 #endif
diff --git a/libc/kernel/common/linux/msm_mdp.h b/libc/kernel/common/linux/msm_mdp.h
index cfb91a9..75d595f 100644
--- a/libc/kernel/common/linux/msm_mdp.h
+++ b/libc/kernel/common/linux/msm_mdp.h
@@ -19,15 +19,65 @@
 #ifndef _MSM_MDP_H_
 #define _MSM_MDP_H_
 #include <linux/types.h>
-#define MSMFB_IOCTL_MAGIC 'm'
+#include <linux/fb.h>
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSMFB_IOCTL_MAGIC 'm'
 #define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int)
 #define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int)
+#define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int)
+#define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor)
+#define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap)
+#define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs)
+#define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs)
+#define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135,   struct mdp_overlay)
+#define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137,   struct msmfb_overlay_data)
+#define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY
+#define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138,   struct mdp_page_protection)
+#define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139,   struct mdp_page_protection)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140,   struct mdp_overlay)
+#define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int)
+#define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142,   struct msmfb_overlay_blt)
+#define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144,   struct mdp_histogram_start_req)
+#define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int)
+#define MSMFB_NOTIFY_UPDATE _IOW(MSMFB_IOCTL_MAGIC, 146, unsigned int)
+#define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147,   struct msmfb_overlay_3d)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148,   struct msmfb_mixer_info_req)
+#define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149,   struct msmfb_overlay_data)
+#define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150)
+#define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152)
+#define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153,   struct msmfb_data)
+#define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154,   struct msmfb_data)
+#define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp)
+#define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int)
+#define FB_TYPE_3D_PANEL 0x10101010
+#define MDP_IMGTYPE2_START 0x10000
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSMFB_DRIVER_VERSION 0xF9E8D701
+enum {
+ NOTIFY_UPDATE_START,
+ NOTIFY_UPDATE_STOP,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
 enum {
  MDP_RGB_565,
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  MDP_XRGB_8888,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  MDP_Y_CBCR_H2V2,
+ MDP_Y_CBCR_H2V2_ADRENO,
  MDP_ARGB_8888,
  MDP_RGB_888,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -36,17 +86,47 @@
  MDP_Y_CRCB_H2V1,
  MDP_Y_CBCR_H2V1,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ MDP_Y_CRCB_H1V2,
+ MDP_Y_CBCR_H1V2,
  MDP_RGBA_8888,
  MDP_BGRA_8888,
- MDP_RGBX_8888,
- MDP_IMGTYPE_LIMIT
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ MDP_RGBX_8888,
+ MDP_Y_CRCB_H2V2_TILE,
+ MDP_Y_CBCR_H2V2_TILE,
+ MDP_Y_CR_CB_H2V2,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ MDP_Y_CR_CB_GH2V2,
+ MDP_Y_CB_CR_H2V2,
+ MDP_Y_CRCB_H1V1,
+ MDP_Y_CBCR_H1V1,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ MDP_YCRCB_H1V1,
+ MDP_YCBCR_H1V1,
+ MDP_BGR_565,
+ MDP_IMGTYPE_LIMIT,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ MDP_RGB_BORDERFILL,
+ MDP_FB_FORMAT = MDP_IMGTYPE2_START,
+ MDP_IMGTYPE_LIMIT2
 };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 enum {
  PMEM_IMG,
  FB_IMG,
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+enum {
+ HSIC_HUE = 0,
+ HSIC_SAT,
+ HSIC_INT,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ HSIC_CON,
+ NUM_HSIC_PARAM,
+};
+#define MDSS_MDP_ROT_ONLY 0x80
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MDSS_MDP_RIGHT_MIXER 0x100
 #define MDP_ROT_NOP 0
 #define MDP_FLIP_LR 0x1
 #define MDP_FLIP_UD 0x2
@@ -58,39 +138,364 @@
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define MDP_BLUR 0x10
 #define MDP_BLEND_FG_PREMULT 0x20000
+#define MDP_DEINTERLACE 0x80000000
+#define MDP_SHARPENING 0x40000000
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MDP_NO_DMA_BARRIER_START 0x20000000
+#define MDP_NO_DMA_BARRIER_END 0x10000000
+#define MDP_NO_BLIT 0x08000000
+#define MDP_BLIT_WITH_DMA_BARRIERS 0x000
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MDP_BLIT_WITH_NO_DMA_BARRIERS   (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END)
+#define MDP_BLIT_SRC_GEM 0x04000000
+#define MDP_BLIT_DST_GEM 0x02000000
+#define MDP_BLIT_NON_CACHED 0x01000000
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MDP_OV_PIPE_SHARE 0x00800000
+#define MDP_DEINTERLACE_ODD 0x00400000
+#define MDP_OV_PLAY_NOWAIT 0x00200000
+#define MDP_SOURCE_ROTATED_90 0x00100000
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MDP_OVERLAY_PP_CFG_EN 0x00080000
+#define MDP_BACKEND_COMPOSITION 0x00040000
+#define MDP_BORDERFILL_SUPPORTED 0x00010000
+#define MDP_SECURE_OVERLAY_SESSION 0x00008000
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MDP_MEMORY_ID_TYPE_FB 0x00001000
 #define MDP_TRANSP_NOP 0xffffffff
 #define MDP_ALPHA_NOP 0xff
+#define MDP_FB_PAGE_PROTECTION_NONCACHED (0)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1)
+#define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2)
+#define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3)
+#define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MDP_FB_PAGE_PROTECTION_INVALID (5)
+#define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5)
 struct mdp_rect {
  uint32_t x;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  uint32_t y;
  uint32_t w;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  uint32_t h;
 };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct mdp_img {
  uint32_t width;
+ uint32_t height;
+ uint32_t format;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t offset;
+ int memory_id;
+ uint32_t priv;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MDP_CCS_RGB2YUV 0
+#define MDP_CCS_YUV2RGB 1
+#define MDP_CCS_SIZE 9
+#define MDP_BV_SIZE 3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct mdp_ccs {
+ int direction;
+ uint16_t ccs[MDP_CCS_SIZE];
+ uint16_t bv[MDP_BV_SIZE];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+struct mdp_csc {
+ int id;
+ uint32_t csc_mv[9];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t csc_pre_bv[3];
+ uint32_t csc_post_bv[3];
+ uint32_t csc_pre_lv[6];
+ uint32_t csc_post_lv[6];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+#define MDP_BLIT_REQ_VERSION 2
+struct mdp_blit_req {
+ struct mdp_img src;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ struct mdp_img dst;
+ struct mdp_rect src_rect;
+ struct mdp_rect dst_rect;
+ uint32_t alpha;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t transp_mask;
+ uint32_t flags;
+ int sharpening_strength;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct mdp_blit_req_list {
+ uint32_t count;
+ struct mdp_blit_req req[];
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSMFB_DATA_VERSION 2
+struct msmfb_data {
+ uint32_t offset;
+ int memory_id;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ int id;
+ uint32_t flags;
+ uint32_t priv;
+ uint32_t iova;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+#define MSMFB_NEW_REQUEST -1
+struct msmfb_overlay_data {
+ uint32_t id;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ struct msmfb_data data;
+ uint32_t version_key;
+ struct msmfb_data plane1_data;
+ struct msmfb_data plane2_data;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ struct msmfb_data dst_data;
+};
+struct msmfb_img {
+ uint32_t width;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  uint32_t height;
  uint32_t format;
- uint32_t offset;
- int memory_id;
+};
+#define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct msmfb_writeback_data {
+ struct msmfb_data buf_info;
+ struct msmfb_img img;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MDP_PP_OPS_READ 0x2
+#define MDP_PP_OPS_WRITE 0x4
+struct mdp_qseed_cfg {
+ uint32_t table_num;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t ops;
+ uint32_t len;
+ uint32_t *data;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct mdp_qseed_cfg_data {
+ uint32_t block;
+ struct mdp_qseed_cfg qseed_data;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MDP_OVERLAY_PP_CSC_CFG 0x1
+#define MDP_OVERLAY_PP_QSEED_CFG 0x2
+#define MDP_CSC_FLAG_ENABLE 0x1
+#define MDP_CSC_FLAG_YUV_IN 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MDP_CSC_FLAG_YUV_OUT 0x4
+struct mdp_csc_cfg {
+ uint32_t flags;
+ uint32_t csc_mv[9];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t csc_pre_bv[3];
+ uint32_t csc_post_bv[3];
+ uint32_t csc_pre_lv[6];
+ uint32_t csc_post_lv[6];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
-struct mdp_blit_req {
- struct mdp_img src;
- struct mdp_img dst;
+struct mdp_csc_cfg_data {
+ uint32_t block;
+ struct mdp_csc_cfg csc_data;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+struct mdp_overlay_pp_params {
+ uint32_t config_ops;
+ struct mdp_csc_cfg csc_cfg;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ struct mdp_qseed_cfg qseed_cfg[2];
+};
+struct mdp_overlay {
+ struct msmfb_img src;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  struct mdp_rect src_rect;
  struct mdp_rect dst_rect;
+ uint32_t z_order;
+ uint32_t is_fg;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  uint32_t alpha;
  uint32_t transp_mask;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  uint32_t flags;
-};
-struct mdp_blit_req_list {
- uint32_t count;
+ uint32_t id;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct mdp_blit_req req[];
+ uint32_t user_data[8];
+ struct mdp_overlay_pp_params overlay_pp_cfg;
+};
+struct msmfb_overlay_3d {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t is_3d;
+ uint32_t width;
+ uint32_t height;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct msmfb_overlay_blt {
+ uint32_t enable;
+ uint32_t offset;
+ uint32_t width;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t height;
+ uint32_t bpp;
+};
+struct mdp_histogram {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t frame_cnt;
+ uint32_t bin_cnt;
+ uint32_t *r;
+ uint32_t *g;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t *b;
+};
+enum {
+ MDP_BLOCK_RESERVED = 0,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ MDP_BLOCK_OVERLAY_0,
+ MDP_BLOCK_OVERLAY_1,
+ MDP_BLOCK_VG_1,
+ MDP_BLOCK_VG_2,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ MDP_BLOCK_RGB_1,
+ MDP_BLOCK_RGB_2,
+ MDP_BLOCK_DMA_P,
+ MDP_BLOCK_DMA_S,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ MDP_BLOCK_DMA_E,
+ MDP_BLOCK_OVERLAY_2,
+ MDP_BLOCK_MAX,
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct mdp_histogram_start_req {
+ uint32_t block;
+ uint8_t frame_cnt;
+ uint8_t bit_mask;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint8_t num_bins;
+};
+struct mdp_histogram_data {
+ uint32_t block;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint8_t bin_cnt;
+ uint32_t *c0;
+ uint32_t *c1;
+ uint32_t *c2;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t *extra_info;
+};
+struct mdp_pcc_coeff {
+ uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+struct mdp_pcc_cfg_data {
+ uint32_t block;
+ uint32_t ops;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ struct mdp_pcc_coeff r, g, b;
+};
+enum {
+ mdp_lut_igc,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ mdp_lut_pgc,
+ mdp_lut_hist,
+ mdp_lut_max,
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct mdp_igc_lut_data {
+ uint32_t block;
+ uint32_t len, ops;
+ uint32_t *c0_c1_data;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t *c2_data;
+};
+struct mdp_ar_gc_lut_data {
+ uint32_t x_start;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t slope;
+ uint32_t offset;
+};
+struct mdp_pgc_lut_data {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t block;
+ uint32_t flags;
+ uint8_t num_r_stages;
+ uint8_t num_g_stages;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint8_t num_b_stages;
+ struct mdp_ar_gc_lut_data *r_data;
+ struct mdp_ar_gc_lut_data *g_data;
+ struct mdp_ar_gc_lut_data *b_data;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+struct mdp_hist_lut_data {
+ uint32_t block;
+ uint32_t ops;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t len;
+ uint32_t *data;
+};
+struct mdp_lut_cfg_data {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t lut_type;
+ union {
+ struct mdp_igc_lut_data igc_lut_data;
+ struct mdp_pgc_lut_data pgc_lut_data;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ struct mdp_hist_lut_data hist_lut_data;
+ } data;
+};
+struct mdp_bl_scale_data {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t min_lvl;
+ uint32_t scale;
+};
+enum {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ mdp_op_pcc_cfg,
+ mdp_op_csc_cfg,
+ mdp_op_lut_cfg,
+ mdp_op_qseed_cfg,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ mdp_bl_scale_cfg,
+ mdp_op_max,
+};
+struct msmfb_mdp_pp {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t op;
+ union {
+ struct mdp_pcc_cfg_data pcc_cfg_data;
+ struct mdp_csc_cfg_data csc_cfg_data;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ struct mdp_lut_cfg_data lut_cfg_data;
+ struct mdp_qseed_cfg_data qseed_cfg_data;
+ struct mdp_bl_scale_data bl_scale_data;
+ } data;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+struct mdp_page_protection {
+ uint32_t page_protection;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct mdp_mixer_info {
+ int pndx;
+ int pnum;
+ int ptype;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ int mixer_num;
+ int z_order;
+};
+#define MAX_PIPE_PER_MIXER 4
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct msmfb_mixer_info_req {
+ int mixer_num;
+ int cnt;
+ struct mdp_mixer_info info[MAX_PIPE_PER_MIXER];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+enum {
+ DISPLAY_SUBSYSTEM_ID,
+ ROTATOR_SUBSYSTEM_ID,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #endif
+
diff --git a/libc/kernel/common/linux/msm_rmnet.h b/libc/kernel/common/linux/msm_rmnet.h
new file mode 100644
index 0000000..88ddd3a
--- /dev/null
+++ b/libc/kernel/common/linux/msm_rmnet.h
@@ -0,0 +1,54 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ***   To edit the content of this header, modify the corresponding
+ ***   source file (e.g. under external/kernel-headers/original/) then
+ ***   run bionic/libc/kernel/tools/update_all.py
+ ***
+ ***   Any manual change here will be lost the next time this script will
+ ***   be run. You've been warned!
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef _MSM_RMNET_H_
+#define _MSM_RMNET_H_
+#define RMNET_MODE_NONE (0x00)
+#define RMNET_MODE_LLP_ETH (0x01)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define RMNET_MODE_LLP_IP (0x02)
+#define RMNET_MODE_QOS (0x04)
+#define RMNET_MODE_MASK (RMNET_MODE_LLP_ETH |   RMNET_MODE_LLP_IP |   RMNET_MODE_QOS)
+#define RMNET_IS_MODE_QOS(mode)   ((mode & RMNET_MODE_QOS) == RMNET_MODE_QOS)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define RMNET_IS_MODE_IP(mode)   ((mode & RMNET_MODE_LLP_IP) == RMNET_MODE_LLP_IP)
+enum rmnet_ioctl_cmds_e {
+ RMNET_IOCTL_SET_LLP_ETHERNET = 0x000089F1,
+ RMNET_IOCTL_SET_LLP_IP = 0x000089F2,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ RMNET_IOCTL_GET_LLP = 0x000089F3,
+ RMNET_IOCTL_SET_QOS_ENABLE = 0x000089F4,
+ RMNET_IOCTL_SET_QOS_DISABLE = 0x000089F5,
+ RMNET_IOCTL_GET_QOS = 0x000089F6,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ RMNET_IOCTL_GET_OPMODE = 0x000089F7,
+ RMNET_IOCTL_OPEN = 0x000089F8,
+ RMNET_IOCTL_CLOSE = 0x000089F9,
+ RMNET_IOCTL_MAX
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+#define QMI_QOS_HDR_S __attribute((__packed__)) qmi_qos_hdr_s
+struct QMI_QOS_HDR_S {
+ unsigned char version;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned char flags;
+ unsigned long flow_id;
+};
+#endif
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+
diff --git a/libc/kernel/common/linux/msm_rotator.h b/libc/kernel/common/linux/msm_rotator.h
new file mode 100644
index 0000000..2e57191
--- /dev/null
+++ b/libc/kernel/common/linux/msm_rotator.h
@@ -0,0 +1,76 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ***   To edit the content of this header, modify the corresponding
+ ***   source file (e.g. under external/kernel-headers/original/) then
+ ***   run bionic/libc/kernel/tools/update_all.py
+ ***
+ ***   Any manual change here will be lost the next time this script will
+ ***   be run. You've been warned!
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __MSM_ROTATOR_H__
+#define __MSM_ROTATOR_H__
+#include <linux/types.h>
+#include <linux/msm_mdp.h>
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSM_ROTATOR_IOCTL_MAGIC 'R'
+#define MSM_ROTATOR_IOCTL_START   _IOWR(MSM_ROTATOR_IOCTL_MAGIC, 1, struct msm_rotator_img_info)
+#define MSM_ROTATOR_IOCTL_ROTATE   _IOW(MSM_ROTATOR_IOCTL_MAGIC, 2, struct msm_rotator_data_info)
+#define MSM_ROTATOR_IOCTL_FINISH   _IOW(MSM_ROTATOR_IOCTL_MAGIC, 3, int)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define ROTATOR_VERSION_01 0xA5B4C301
+enum rotator_clk_type {
+ ROTATOR_CORE_CLK,
+ ROTATOR_PCLK,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ ROTATOR_IMEM_CLK
+};
+struct msm_rotator_img_info {
+ unsigned int session_id;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ struct msmfb_img src;
+ struct msmfb_img dst;
+ struct mdp_rect src_rect;
+ unsigned int dst_x;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned int dst_y;
+ unsigned char rotations;
+ int enable;
+ unsigned int downscale_ratio;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned int secure;
+};
+struct msm_rotator_data_info {
+ int session_id;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ struct msmfb_data src;
+ struct msmfb_data dst;
+ unsigned int version_key;
+ struct msmfb_data src_chroma;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ struct msmfb_data dst_chroma;
+};
+struct msm_rot_clocks {
+ const char *clk_name;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ enum rotator_clk_type clk_type;
+ unsigned int clk_rate;
+};
+struct msm_rotator_platform_data {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned int number_of_clocks;
+ unsigned int hardware_version_number;
+ struct msm_rot_clocks *rotator_clks;
+ char rot_iommu_split_domain;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+#endif
+
diff --git a/libc/kernel/common/linux/msm_vidc_dec.h b/libc/kernel/common/linux/msm_vidc_dec.h
index 2a5587a..09a7136 100644
--- a/libc/kernel/common/linux/msm_vidc_dec.h
+++ b/libc/kernel/common/linux/msm_vidc_dec.h
@@ -39,92 +39,112 @@
 #define VDEC_S_ENOTSUPP (VDEC_S_BASE + 11)
 #define VDEC_S_ENOTIMPL (VDEC_S_BASE + 12)
 #define VDEC_S_BUSY (VDEC_S_BASE + 13)
-#define VDEC_INTF_VER 1
+#define VDEC_S_INPUT_BITSTREAM_ERR (VDEC_S_BASE + 14)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VDEC_INTF_VER 1
 #define VDEC_MSG_BASE 0x0000000
 #define VDEC_MSG_INVALID (VDEC_MSG_BASE + 0)
 #define VDEC_MSG_RESP_INPUT_BUFFER_DONE (VDEC_MSG_BASE + 1)
-#define VDEC_MSG_RESP_OUTPUT_BUFFER_DONE (VDEC_MSG_BASE + 2)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VDEC_MSG_RESP_OUTPUT_BUFFER_DONE (VDEC_MSG_BASE + 2)
 #define VDEC_MSG_RESP_INPUT_FLUSHED (VDEC_MSG_BASE + 3)
 #define VDEC_MSG_RESP_OUTPUT_FLUSHED (VDEC_MSG_BASE + 4)
 #define VDEC_MSG_RESP_FLUSH_INPUT_DONE (VDEC_MSG_BASE + 5)
-#define VDEC_MSG_RESP_FLUSH_OUTPUT_DONE (VDEC_MSG_BASE + 6)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VDEC_MSG_RESP_FLUSH_OUTPUT_DONE (VDEC_MSG_BASE + 6)
 #define VDEC_MSG_RESP_START_DONE (VDEC_MSG_BASE + 7)
 #define VDEC_MSG_RESP_STOP_DONE (VDEC_MSG_BASE + 8)
 #define VDEC_MSG_RESP_PAUSE_DONE (VDEC_MSG_BASE + 9)
-#define VDEC_MSG_RESP_RESUME_DONE (VDEC_MSG_BASE + 10)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VDEC_MSG_RESP_RESUME_DONE (VDEC_MSG_BASE + 10)
 #define VDEC_MSG_RESP_RESOURCE_LOADED (VDEC_MSG_BASE + 11)
 #define VDEC_EVT_RESOURCES_LOST (VDEC_MSG_BASE + 12)
 #define VDEC_MSG_EVT_CONFIG_CHANGED (VDEC_MSG_BASE + 13)
-#define VDEC_MSG_EVT_HW_ERROR (VDEC_MSG_BASE + 14)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VDEC_MSG_EVT_HW_ERROR (VDEC_MSG_BASE + 14)
+#define VDEC_MSG_EVT_INFO_CONFIG_CHANGED (VDEC_MSG_BASE + 15)
+#define VDEC_MSG_EVT_INFO_FIELD_DROPPED (VDEC_MSG_BASE + 16)
 #define VDEC_BUFFERFLAG_EOS 0x00000001
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VDEC_BUFFERFLAG_DECODEONLY 0x00000004
 #define VDEC_BUFFERFLAG_DATACORRUPT 0x00000008
 #define VDEC_BUFFERFLAG_ENDOFFRAME 0x00000010
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VDEC_BUFFERFLAG_SYNCFRAME 0x00000020
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VDEC_BUFFERFLAG_EXTRADATA 0x00000040
 #define VDEC_BUFFERFLAG_CODECCONFIG 0x00000080
-#define VDEC_EXTRADATA_QP 0x00000001
+#define VDEC_EXTRADATA_NONE 0x001
+#define VDEC_EXTRADATA_QP 0x004
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define VDEC_EXTRADATA_SEI 0x00000002
-#define VDEC_EXTRADATA_VUI 0x00000004
-#define VDEC_EXTRADATA_MB_ERROR_MAP 0x00000008
+#define VDEC_EXTRADATA_MB_ERROR_MAP 0x008
+#define VDEC_EXTRADATA_SEI 0x010
+#define VDEC_EXTRADATA_VUI 0x020
+#define VDEC_EXTRADATA_VC1 0x040
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VDEC_CMDBASE 0x800
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VDEC_CMD_SET_INTF_VERSION (VDEC_CMDBASE)
 #define VDEC_IOCTL_MAGIC 'v'
 struct vdec_ioctl_msg {
- void *inputparam;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- void *outputparam;
+ void __user *in;
+ void __user *out;
 };
 #define VDEC_IOCTL_GET_PROFILE_LEVEL_SUPPORTED   _IOWR(VDEC_IOCTL_MAGIC, 0, struct vdec_ioctl_msg)
-#define VDEC_IOCTL_GET_INTERLACE_FORMAT   _IOR(VDEC_IOCTL_MAGIC, 1, struct vdec_ioctl_msg)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VDEC_IOCTL_GET_INTERLACE_FORMAT   _IOR(VDEC_IOCTL_MAGIC, 1, struct vdec_ioctl_msg)
 #define VDEC_IOCTL_GET_CURRENT_PROFILE_LEVEL   _IOWR(VDEC_IOCTL_MAGIC, 2, struct vdec_ioctl_msg)
 #define VDEC_IOCTL_SET_OUTPUT_FORMAT   _IOWR(VDEC_IOCTL_MAGIC, 3, struct vdec_ioctl_msg)
 #define VDEC_IOCTL_GET_OUTPUT_FORMAT   _IOWR(VDEC_IOCTL_MAGIC, 4, struct vdec_ioctl_msg)
-#define VDEC_IOCTL_SET_CODEC   _IOW(VDEC_IOCTL_MAGIC, 5, struct vdec_ioctl_msg)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VDEC_IOCTL_SET_CODEC   _IOW(VDEC_IOCTL_MAGIC, 5, struct vdec_ioctl_msg)
 #define VDEC_IOCTL_GET_CODEC   _IOR(VDEC_IOCTL_MAGIC, 6, struct vdec_ioctl_msg)
 #define VDEC_IOCTL_SET_PICRES   _IOW(VDEC_IOCTL_MAGIC, 7, struct vdec_ioctl_msg)
 #define VDEC_IOCTL_GET_PICRES   _IOR(VDEC_IOCTL_MAGIC, 8, struct vdec_ioctl_msg)
-#define VDEC_IOCTL_SET_EXTRADATA   _IOW(VDEC_IOCTL_MAGIC, 9, struct vdec_ioctl_msg)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VDEC_IOCTL_SET_EXTRADATA   _IOW(VDEC_IOCTL_MAGIC, 9, struct vdec_ioctl_msg)
 #define VDEC_IOCTL_GET_EXTRADATA   _IOR(VDEC_IOCTL_MAGIC, 10, struct vdec_ioctl_msg)
 #define VDEC_IOCTL_SET_SEQUENCE_HEADER   _IOW(VDEC_IOCTL_MAGIC, 11, struct vdec_ioctl_msg)
 #define VDEC_IOCTL_SET_BUFFER_REQ   _IOW(VDEC_IOCTL_MAGIC, 12, struct vdec_ioctl_msg)
-#define VDEC_IOCTL_GET_BUFFER_REQ   _IOR(VDEC_IOCTL_MAGIC, 13, struct vdec_ioctl_msg)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VDEC_IOCTL_GET_BUFFER_REQ   _IOR(VDEC_IOCTL_MAGIC, 13, struct vdec_ioctl_msg)
 #define VDEC_IOCTL_ALLOCATE_BUFFER   _IOWR(VDEC_IOCTL_MAGIC, 14, struct vdec_ioctl_msg)
 #define VDEC_IOCTL_FREE_BUFFER   _IOW(VDEC_IOCTL_MAGIC, 15, struct vdec_ioctl_msg)
 #define VDEC_IOCTL_SET_BUFFER   _IOW(VDEC_IOCTL_MAGIC, 16, struct vdec_ioctl_msg)
-#define VDEC_IOCTL_FILL_OUTPUT_BUFFER   _IOW(VDEC_IOCTL_MAGIC, 17, struct vdec_ioctl_msg)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VDEC_IOCTL_FILL_OUTPUT_BUFFER   _IOW(VDEC_IOCTL_MAGIC, 17, struct vdec_ioctl_msg)
 #define VDEC_IOCTL_DECODE_FRAME   _IOW(VDEC_IOCTL_MAGIC, 18, struct vdec_ioctl_msg)
 #define VDEC_IOCTL_LOAD_RESOURCES _IO(VDEC_IOCTL_MAGIC, 19)
 #define VDEC_IOCTL_CMD_START _IO(VDEC_IOCTL_MAGIC, 20)
-#define VDEC_IOCTL_CMD_STOP _IO(VDEC_IOCTL_MAGIC, 21)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VDEC_IOCTL_CMD_STOP _IO(VDEC_IOCTL_MAGIC, 21)
 #define VDEC_IOCTL_CMD_PAUSE _IO(VDEC_IOCTL_MAGIC, 22)
 #define VDEC_IOCTL_CMD_RESUME _IO(VDEC_IOCTL_MAGIC, 23)
 #define VDEC_IOCTL_CMD_FLUSH _IOW(VDEC_IOCTL_MAGIC, 24, struct vdec_ioctl_msg)
-#define VDEC_IOCTL_GET_NEXT_MSG   _IOR(VDEC_IOCTL_MAGIC, 25, struct vdec_ioctl_msg)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VDEC_IOCTL_GET_NEXT_MSG   _IOR(VDEC_IOCTL_MAGIC, 25, struct vdec_ioctl_msg)
 #define VDEC_IOCTL_STOP_NEXT_MSG _IO(VDEC_IOCTL_MAGIC, 26)
 #define VDEC_IOCTL_GET_NUMBER_INSTANCES   _IOR(VDEC_IOCTL_MAGIC, 27, struct vdec_ioctl_msg)
+#define VDEC_IOCTL_SET_PICTURE_ORDER   _IOW(VDEC_IOCTL_MAGIC, 28, struct vdec_ioctl_msg)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VDEC_IOCTL_SET_FRAME_RATE   _IOW(VDEC_IOCTL_MAGIC, 29, struct vdec_ioctl_msg)
+#define VDEC_IOCTL_SET_H264_MV_BUFFER   _IOW(VDEC_IOCTL_MAGIC, 30, struct vdec_ioctl_msg)
+#define VDEC_IOCTL_FREE_H264_MV_BUFFER   _IOW(VDEC_IOCTL_MAGIC, 31, struct vdec_ioctl_msg)
+#define VDEC_IOCTL_GET_MV_BUFFER_SIZE   _IOR(VDEC_IOCTL_MAGIC, 32, struct vdec_ioctl_msg)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VDEC_IOCTL_SET_IDR_ONLY_DECODING   _IO(VDEC_IOCTL_MAGIC, 33)
+#define VDEC_IOCTL_SET_CONT_ON_RECONFIG   _IO(VDEC_IOCTL_MAGIC, 34)
+#define VDEC_IOCTL_SET_DISABLE_DMX   _IOW(VDEC_IOCTL_MAGIC, 35, struct vdec_ioctl_msg)
+#define VDEC_IOCTL_GET_DISABLE_DMX   _IOR(VDEC_IOCTL_MAGIC, 36, struct vdec_ioctl_msg)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VDEC_IOCTL_GET_DISABLE_DMX_SUPPORT   _IOR(VDEC_IOCTL_MAGIC, 37, struct vdec_ioctl_msg)
 enum vdec_picture {
  PICTURE_TYPE_I,
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  PICTURE_TYPE_P,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  PICTURE_TYPE_B,
  PICTURE_TYPE_BI,
  PICTURE_TYPE_SKIP,
+ PICTURE_TYPE_IDR,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  PICTURE_TYPE_UNKNOWN
 };
@@ -139,19 +159,19 @@
  uint32_t mincount;
  uint32_t maxcount;
  uint32_t actualcount;
- uint32_t buffer_size;
+ size_t buffer_size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  uint32_t alignment;
  uint32_t buf_poolid;
 };
 struct vdec_bufferpayload {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint8_t *bufferaddr;
- uint32_t buffer_len;
+ void __user *bufferaddr;
+ size_t buffer_len;
  int pmem_fd;
- uint32_t offset;
+ size_t offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t mmaped_size;
+ size_t mmaped_size;
 };
 struct vdec_setbuffer_cmd {
  enum vdec_buffer buffer_type;
@@ -413,6 +433,11 @@
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  VDEC_YUV_FORMAT_TILE_4x2 = 0x2
 };
+enum vdec_output_order {
+ VDEC_ORDER_DISPLAY = 0x1,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ VDEC_ORDER_DECODE = 0x2
+};
 struct vdec_picsize {
  uint32_t frame_width;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -422,62 +447,94 @@
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct vdec_seqheader {
- uint8_t *ptr_seqheader;
- uint32_t seq_header_len;
+ void __user *ptr_seqheader;
+ size_t seq_header_len;
  int pmem_fd;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t pmem_offset;
+ size_t pmem_offset;
 };
 struct vdec_mberror {
- uint8_t *ptr_errormap;
+ void __user *ptr_errormap;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t err_mapsize;
+ size_t err_mapsize;
 };
 struct vdec_input_frameinfo {
- uint8_t *bufferaddr;
+ void __user *bufferaddr;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t offset;
- uint32_t datalen;
+ size_t offset;
+ size_t datalen;
  uint32_t flags;
  int64_t timestamp;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  void *client_data;
  int pmem_fd;
- uint32_t pmem_offset;
+ size_t pmem_offset;
+ void __user *desc_addr;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t desc_size;
+};
+struct vdec_framesize {
+ uint32_t left;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t top;
+ uint32_t right;
+ uint32_t bottom;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-struct vdec_framesize {
- uint32_t n_left;
- uint32_t n_top;
- uint32_t n_right;
+struct vdec_aspectratioinfo {
+ uint32_t aspect_ratio;
+ uint32_t par_width;
+ uint32_t par_height;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t n_bottom;
 };
 struct vdec_output_frameinfo {
- uint8_t *phy_addr;
+ void __user *bufferaddr;
+ size_t offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint8_t *bufferaddr;
- uint32_t offset;
- uint32_t len;
+ size_t len;
  uint32_t flags;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  int64_t time_stamp;
+ enum vdec_picture pic_type;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  void *client_data;
  void *input_frame_clientdata;
  struct vdec_framesize framesize;
+ enum vdec_interlaced_format interlaced_format;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ struct vdec_aspectratioinfo aspect_ratio_info;
 };
 union vdec_msgdata {
  struct vdec_output_frameinfo output_frame;
- void *input_frame_clientdata;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ void *input_frame_clientdata;
 };
 struct vdec_msginfo {
  uint32_t status_code;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  uint32_t msgcode;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  union vdec_msgdata msgdata;
- uint32_t msgdatasize;
+ size_t msgdatasize;
 };
-#endif
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct vdec_framerate {
+ unsigned long fps_denominator;
+ unsigned long fps_numerator;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct vdec_h264_mv{
+ size_t size;
+ int count;
+ int pmem_fd;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ int offset;
+};
+struct vdec_mv_buff_size{
+ int width;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ int height;
+ int size;
+ int alignment;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#endif
+
diff --git a/libc/kernel/common/linux/msm_vidc_enc.h b/libc/kernel/common/linux/msm_vidc_enc.h
index 87b81d5..2325686 100644
--- a/libc/kernel/common/linux/msm_vidc_enc.h
+++ b/libc/kernel/common/linux/msm_vidc_enc.h
@@ -68,248 +68,268 @@
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_BUFFLAG_EXTRADATA 0x00000040
 #define VEN_BUFFLAG_CODECCONFIG 0x00000080
+#define VEN_EXTRADATA_NONE 0x001
+#define VEN_EXTRADATA_QCOMFILLER 0x002
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VEN_EXTRADATA_SLICEINFO 0x100
 #define VEN_FRAME_TYPE_I 1 
 #define VEN_FRAME_TYPE_P 2 
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_FRAME_TYPE_B 3 
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_CODEC_MPEG4 1 
 #define VEN_CODEC_H264 2 
 #define VEN_CODEC_H263 3 
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_PROFILE_MPEG4_SP 1 
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_PROFILE_MPEG4_ASP 2 
 #define VEN_PROFILE_H264_BASELINE 3 
 #define VEN_PROFILE_H264_MAIN 4 
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_PROFILE_H264_HIGH 5 
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_PROFILE_H263_BASELINE 6 
 #define VEN_LEVEL_MPEG4_0 0x1 
 #define VEN_LEVEL_MPEG4_1 0x2 
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_LEVEL_MPEG4_2 0x3 
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_LEVEL_MPEG4_3 0x4 
 #define VEN_LEVEL_MPEG4_4 0x5 
 #define VEN_LEVEL_MPEG4_5 0x6 
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_LEVEL_MPEG4_3b 0x7 
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_LEVEL_MPEG4_6 0x8 
 #define VEN_LEVEL_H264_1 0x9 
 #define VEN_LEVEL_H264_1b 0xA 
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_LEVEL_H264_1p1 0xB 
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_LEVEL_H264_1p2 0xC 
 #define VEN_LEVEL_H264_1p3 0xD 
 #define VEN_LEVEL_H264_2 0xE 
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_LEVEL_H264_2p1 0xF 
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_LEVEL_H264_2p2 0x10 
 #define VEN_LEVEL_H264_3 0x11 
 #define VEN_LEVEL_H264_3p1 0x12 
+#define VEN_LEVEL_H264_3p2 0x13 
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define VEN_LEVEL_H263_10 0x13 
-#define VEN_LEVEL_H263_20 0x14 
-#define VEN_LEVEL_H263_30 0x15 
-#define VEN_LEVEL_H263_40 0x16 
+#define VEN_LEVEL_H264_4 0x14 
+#define VEN_LEVEL_H263_10 0x15 
+#define VEN_LEVEL_H263_20 0x16 
+#define VEN_LEVEL_H263_30 0x17 
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define VEN_LEVEL_H263_45 0x17 
-#define VEN_LEVEL_H263_50 0x18 
-#define VEN_LEVEL_H263_60 0x19 
-#define VEN_LEVEL_H263_70 0x1A 
+#define VEN_LEVEL_H263_40 0x18 
+#define VEN_LEVEL_H263_45 0x19 
+#define VEN_LEVEL_H263_50 0x1A 
+#define VEN_LEVEL_H263_60 0x1B 
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VEN_LEVEL_H263_70 0x1C 
 #define VEN_ENTROPY_MODEL_CAVLC 1
 #define VEN_ENTROPY_MODEL_CABAC 2
 #define VEN_CABAC_MODEL_0 1 
-#define VEN_CABAC_MODEL_1 2 
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VEN_CABAC_MODEL_1 2 
 #define VEN_CABAC_MODEL_2 3 
 #define VEN_DB_DISABLE 1 
 #define VEN_DB_ALL_BLKG_BNDRY 2 
-#define VEN_DB_SKIP_SLICE_BNDRY 3 
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VEN_DB_SKIP_SLICE_BNDRY 3 
 #define VEN_MSLICE_OFF 1
 #define VEN_MSLICE_CNT_MB 2  
 #define VEN_MSLICE_CNT_BYTE 3  
-#define VEN_MSLICE_GOB 4  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VEN_MSLICE_GOB 4  
 #define VEN_RC_OFF 1
 #define VEN_RC_VBR_VFR 2
 #define VEN_RC_VBR_CFR 3
-#define VEN_RC_CBR_VFR 4
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VEN_RC_CBR_VFR 4
+#define VEN_RC_CBR_CFR 5
 #define VEN_FLUSH_INPUT 1
 #define VEN_FLUSH_OUTPUT 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_FLUSH_ALL 3
 #define VEN_INPUTFMT_NV12 1 
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_INPUTFMT_NV21 2 
+#define VEN_INPUTFMT_NV12_16M2KA 3 
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_ROTATION_0 1 
 #define VEN_ROTATION_90 2 
 #define VEN_ROTATION_180 3 
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_ROTATION_270 4 
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_TIMEOUT_INFINITE 0xffffffff
 #define VEN_IR_OFF 1
 #define VEN_IR_CYCLIC 2
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IR_RANDOM 3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTLBASE_NENC 0x800
 #define VEN_IOCTLBASE_ENC 0x850
 struct venc_ioctl_msg{
+ void __user *in;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- void *inputparam;
- void *outputparam;
+ void __user *out;
 };
 #define VEN_IOCTL_SET_INTF_VERSION   _IOW(VEN_IOCTLBASE_NENC, 0, struct venc_ioctl_msg)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_CMD_READ_NEXT_MSG   _IOWR(VEN_IOCTLBASE_NENC, 1, struct venc_ioctl_msg)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_CMD_STOP_READ_MSG _IO(VEN_IOCTLBASE_NENC, 2)
 #define VEN_IOCTL_SET_INPUT_BUFFER_REQ   _IOW(VEN_IOCTLBASE_NENC, 3, struct venc_ioctl_msg)
 #define VEN_IOCTL_GET_INPUT_BUFFER_REQ   _IOR(VEN_IOCTLBASE_NENC, 4, struct venc_ioctl_msg)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_CMD_ALLOC_INPUT_BUFFER   _IOW(VEN_IOCTLBASE_NENC, 5, struct venc_ioctl_msg)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_SET_INPUT_BUFFER   _IOW(VEN_IOCTLBASE_NENC, 6, struct venc_ioctl_msg)
 #define VEN_IOCTL_CMD_FREE_INPUT_BUFFER   _IOW(VEN_IOCTLBASE_NENC, 7, struct venc_ioctl_msg)
 #define VEN_IOCTL_SET_OUTPUT_BUFFER_REQ   _IOW(VEN_IOCTLBASE_NENC, 8, struct venc_ioctl_msg)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_GET_OUTPUT_BUFFER_REQ   _IOR(VEN_IOCTLBASE_NENC, 9, struct venc_ioctl_msg)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_CMD_ALLOC_OUTPUT_BUFFER   _IOW(VEN_IOCTLBASE_NENC, 10, struct venc_ioctl_msg)
 #define VEN_IOCTL_SET_OUTPUT_BUFFER   _IOW(VEN_IOCTLBASE_NENC, 11, struct venc_ioctl_msg)
 #define VEN_IOCTL_CMD_FREE_OUTPUT_BUFFER   _IOW(VEN_IOCTLBASE_NENC, 12, struct venc_ioctl_msg)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_CMD_START _IO(VEN_IOCTLBASE_NENC, 13)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_CMD_ENCODE_FRAME   _IOW(VEN_IOCTLBASE_NENC, 14, struct venc_ioctl_msg)
 #define VEN_IOCTL_CMD_FILL_OUTPUT_BUFFER   _IOW(VEN_IOCTLBASE_NENC, 15, struct venc_ioctl_msg)
 #define VEN_IOCTL_CMD_FLUSH   _IOW(VEN_IOCTLBASE_NENC, 16, struct venc_ioctl_msg)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_CMD_PAUSE _IO(VEN_IOCTLBASE_NENC, 17)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_CMD_RESUME _IO(VEN_IOCTLBASE_NENC, 18)
 #define VEN_IOCTL_CMD_STOP _IO(VEN_IOCTLBASE_NENC, 19)
-#define VEN_IOCTL_SET_BASE_CFG   _IOW(VEN_IOCTLBASE_ENC, 1, struct venc_ioctl_msg)
+#define VEN_IOCTL_SET_RECON_BUFFER   _IOW(VEN_IOCTLBASE_NENC, 20, struct venc_ioctl_msg)
+#define VEN_IOCTL_FREE_RECON_BUFFER   _IOW(VEN_IOCTLBASE_NENC, 21, struct venc_ioctl_msg)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VEN_IOCTL_GET_RECON_BUFFER_SIZE   _IOW(VEN_IOCTLBASE_NENC, 22, struct venc_ioctl_msg)
+#define VEN_IOCTL_SET_BASE_CFG   _IOW(VEN_IOCTLBASE_ENC, 1, struct venc_ioctl_msg)
 #define VEN_IOCTL_GET_BASE_CFG   _IOR(VEN_IOCTLBASE_ENC, 2, struct venc_ioctl_msg)
 #define VEN_IOCTL_SET_LIVE_MODE   _IOW(VEN_IOCTLBASE_ENC, 3, struct venc_ioctl_msg)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_GET_LIVE_MODE   _IOR(VEN_IOCTLBASE_ENC, 4, struct venc_ioctl_msg)
 #define VEN_IOCTL_SET_CODEC_PROFILE   _IOW(VEN_IOCTLBASE_ENC, 5, struct venc_ioctl_msg)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_GET_CODEC_PROFILE   _IOR(VEN_IOCTLBASE_ENC, 6, struct venc_ioctl_msg)
 #define VEN_IOCTL_SET_PROFILE_LEVEL   _IOW(VEN_IOCTLBASE_ENC, 7, struct venc_ioctl_msg)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_GET_PROFILE_LEVEL   _IOR(VEN_IOCTLBASE_ENC, 8, struct venc_ioctl_msg)
 #define VEN_IOCTL_SET_SHORT_HDR   _IOW(VEN_IOCTLBASE_ENC, 9, struct venc_ioctl_msg)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_GET_SHORT_HDR   _IOR(VEN_IOCTLBASE_ENC, 10, struct venc_ioctl_msg)
 #define VEN_IOCTL_SET_SESSION_QP   _IOW(VEN_IOCTLBASE_ENC, 11, struct venc_ioctl_msg)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_GET_SESSION_QP   _IOR(VEN_IOCTLBASE_ENC, 12, struct venc_ioctl_msg)
 #define VEN_IOCTL_SET_INTRA_PERIOD   _IOW(VEN_IOCTLBASE_ENC, 13, struct venc_ioctl_msg)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_GET_INTRA_PERIOD   _IOR(VEN_IOCTLBASE_ENC, 14, struct venc_ioctl_msg)
 #define VEN_IOCTL_CMD_REQUEST_IFRAME _IO(VEN_IOCTLBASE_ENC, 15)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_GET_CAPABILITY   _IOR(VEN_IOCTLBASE_ENC, 16, struct venc_ioctl_msg)
 #define VEN_IOCTL_GET_SEQUENCE_HDR   _IOR(VEN_IOCTLBASE_ENC, 17, struct venc_ioctl_msg)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_SET_ENTROPY_CFG   _IOW(VEN_IOCTLBASE_ENC, 18, struct venc_ioctl_msg)
 #define VEN_IOCTL_GET_ENTROPY_CFG   _IOR(VEN_IOCTLBASE_ENC, 19, struct venc_ioctl_msg)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_SET_DEBLOCKING_CFG   _IOW(VEN_IOCTLBASE_ENC, 20, struct venc_ioctl_msg)
 #define VEN_IOCTL_GET_DEBLOCKING_CFG   _IOR(VEN_IOCTLBASE_ENC, 21, struct venc_ioctl_msg)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_SET_INTRA_REFRESH   _IOW(VEN_IOCTLBASE_ENC, 22, struct venc_ioctl_msg)
 #define VEN_IOCTL_GET_INTRA_REFRESH   _IOR(VEN_IOCTLBASE_ENC, 23, struct venc_ioctl_msg)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_SET_MULTI_SLICE_CFG   _IOW(VEN_IOCTLBASE_ENC, 24, struct venc_ioctl_msg)
 #define VEN_IOCTL_GET_MULTI_SLICE_CFG   _IOR(VEN_IOCTLBASE_ENC, 25, struct venc_ioctl_msg)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_SET_RATE_CTRL_CFG   _IOW(VEN_IOCTLBASE_ENC, 26, struct venc_ioctl_msg)
 #define VEN_IOCTL_GET_RATE_CTRL_CFG   _IOR(VEN_IOCTLBASE_ENC, 27, struct venc_ioctl_msg)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_SET_VOP_TIMING_CFG   _IOW(VEN_IOCTLBASE_ENC, 28, struct venc_ioctl_msg)
 #define VEN_IOCTL_GET_VOP_TIMING_CFG   _IOR(VEN_IOCTLBASE_ENC, 29, struct venc_ioctl_msg)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_SET_FRAME_RATE   _IOW(VEN_IOCTLBASE_ENC, 30, struct venc_ioctl_msg)
 #define VEN_IOCTL_GET_FRAME_RATE   _IOR(VEN_IOCTLBASE_ENC, 31, struct venc_ioctl_msg)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_SET_TARGET_BITRATE   _IOW(VEN_IOCTLBASE_ENC, 32, struct venc_ioctl_msg)
 #define VEN_IOCTL_GET_TARGET_BITRATE   _IOR(VEN_IOCTLBASE_ENC, 33, struct venc_ioctl_msg)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_SET_ROTATION   _IOW(VEN_IOCTLBASE_ENC, 34, struct venc_ioctl_msg)
 #define VEN_IOCTL_GET_ROTATION   _IOR(VEN_IOCTLBASE_ENC, 35, struct venc_ioctl_msg)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_SET_HEC   _IOW(VEN_IOCTLBASE_ENC, 36, struct venc_ioctl_msg)
 #define VEN_IOCTL_GET_HEC   _IOR(VEN_IOCTLBASE_ENC, 37, struct venc_ioctl_msg)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_SET_DATA_PARTITION   _IOW(VEN_IOCTLBASE_ENC, 38, struct venc_ioctl_msg)
 #define VEN_IOCTL_GET_DATA_PARTITION   _IOR(VEN_IOCTLBASE_ENC, 39, struct venc_ioctl_msg)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_SET_RVLC   _IOW(VEN_IOCTLBASE_ENC, 40, struct venc_ioctl_msg)
 #define VEN_IOCTL_GET_RVLC   _IOR(VEN_IOCTLBASE_ENC, 41, struct venc_ioctl_msg)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_SET_AC_PREDICTION   _IOW(VEN_IOCTLBASE_ENC, 42, struct venc_ioctl_msg)
 #define VEN_IOCTL_GET_AC_PREDICTION   _IOR(VEN_IOCTLBASE_ENC, 43, struct venc_ioctl_msg)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VEN_IOCTL_SET_QP_RANGE   _IOW(VEN_IOCTLBASE_ENC, 44, struct venc_ioctl_msg)
 #define VEN_IOCTL_GET_QP_RANGE   _IOR(VEN_IOCTLBASE_ENC, 45, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_NUMBER_INSTANCES   _IOR(VEN_IOCTLBASE_ENC, 46, struct venc_ioctl_msg)
+#define VEN_IOCTL_SET_METABUFFER_MODE   _IOW(VEN_IOCTLBASE_ENC, 47, struct venc_ioctl_msg)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VEN_IOCTL_SET_EXTRADATA   _IOW(VEN_IOCTLBASE_ENC, 48, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_EXTRADATA   _IOR(VEN_IOCTLBASE_ENC, 49, struct venc_ioctl_msg)
+#define VEN_IOCTL_SET_SLICE_DELIVERY_MODE   _IO(VEN_IOCTLBASE_ENC, 50)
 struct venc_switch{
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned char status;
 };
 struct venc_allocatorproperty{
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned long mincount;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned long maxcount;
  unsigned long actualcount;
  unsigned long datasize;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned long suffixsize;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned long alignment;
  unsigned long bufpoolid;
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct venc_bufferpayload{
- unsigned char *pbuffer;
- unsigned long nsize;
- int fd;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned char *pbuffer;
+ size_t sz;
+ int fd;
  unsigned int offset;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned int maped_size;
  unsigned long filled_len;
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct venc_buffer{
- unsigned char *ptrbuffer;
- unsigned long size;
- unsigned long len;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned char *ptrbuffer;
+ unsigned long sz;
+ unsigned long len;
  unsigned long offset;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  long long timestamp;
  unsigned long flags;
  void *clientdata;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct venc_basecfg{
  unsigned long input_width;
  unsigned long input_height;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned long dvs_width;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned long dvs_height;
  unsigned long codectype;
  unsigned long fps_num;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned long fps_den;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned long targetbitrate;
  unsigned long inputformat;
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct venc_profile{
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned long profile;
 };
 struct ven_profilelevel{
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned long level;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct venc_sessionqp{
  unsigned long iframeqp;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned long pframqp;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct venc_qprange{
  unsigned long maxqp;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  unsigned long minqp;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct venc_intraperiod{
  unsigned long num_pframes;
+ unsigned long num_bframes;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct venc_seqheader{
@@ -389,5 +409,21 @@
  struct venc_buffer buf;
  unsigned long msgdata_size;
 };
+struct venc_recon_addr{
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned char *pbuffer;
+ unsigned long buffer_size;
+ unsigned long pmem_fd;
+ unsigned long offset;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+struct venc_recon_buff_size{
+ int width;
+ int height;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ int size;
+ int alignment;
+};
 #endif
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+
diff --git a/libc/kernel/common/linux/uhid.h b/libc/kernel/common/linux/uhid.h
new file mode 100644
index 0000000..60b66fc
--- /dev/null
+++ b/libc/kernel/common/linux/uhid.h
@@ -0,0 +1,108 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ***   To edit the content of this header, modify the corresponding
+ ***   source file (e.g. under external/kernel-headers/original/) then
+ ***   run bionic/libc/kernel/tools/update_all.py
+ ***
+ ***   Any manual change here will be lost the next time this script will
+ ***   be run. You've been warned!
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __UHID_H_
+#define __UHID_H_
+#include <linux/input.h>
+#include <linux/types.h>
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+enum uhid_event_type {
+ UHID_CREATE,
+ UHID_DESTROY,
+ UHID_START,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ UHID_STOP,
+ UHID_OPEN,
+ UHID_CLOSE,
+ UHID_OUTPUT,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ UHID_OUTPUT_EV,
+ UHID_INPUT,
+ UHID_FEATURE,
+ UHID_FEATURE_ANSWER,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+struct uhid_create_req {
+ __u8 name[128];
+ __u8 phys[64];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u8 uniq[64];
+ __u8 __user *rd_data;
+ __u16 rd_size;
+ __u16 bus;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 vendor;
+ __u32 product;
+ __u32 version;
+ __u32 country;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+} __attribute__((__packed__));
+#define UHID_DATA_MAX 4096
+enum uhid_report_type {
+ UHID_FEATURE_REPORT,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ UHID_OUTPUT_REPORT,
+ UHID_INPUT_REPORT,
+};
+struct uhid_input_req {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u8 data[UHID_DATA_MAX];
+ __u16 size;
+} __attribute__((__packed__));
+struct uhid_output_req {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u8 data[UHID_DATA_MAX];
+ __u16 size;
+ __u8 rtype;
+} __attribute__((__packed__));
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct uhid_output_ev_req {
+ __u16 type;
+ __u16 code;
+ __s32 value;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+} __attribute__((__packed__));
+struct uhid_feature_req {
+ __u32 id;
+ __u8 rnum;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u8 rtype;
+} __attribute__((__packed__));
+struct uhid_feature_answer_req {
+ __u32 id;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u16 err;
+ __u16 size;
+ __u8 data[UHID_DATA_MAX];
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct uhid_event {
+ __u32 type;
+ union {
+ struct uhid_create_req create;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ struct uhid_input_req input;
+ struct uhid_output_req output;
+ struct uhid_output_ev_req output_ev;
+ struct uhid_feature_req feature;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ struct uhid_feature_answer_req feature_answer;
+ } u;
+} __attribute__((__packed__));
+#endif
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
diff --git a/libc/kernel/common/linux/videodev2.h b/libc/kernel/common/linux/videodev2.h
index 05c2cf3..4937330 100644
--- a/libc/kernel/common/linux/videodev2.h
+++ b/libc/kernel/common/linux/videodev2.h
@@ -136,804 +136,819 @@
  __u32 version;
  __u32 capabilities;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 reserved[4];
+ __u32 device_caps;
+ __u32 reserved[3];
 };
 #define V4L2_CAP_VIDEO_CAPTURE 0x00000001  
-#define V4L2_CAP_VIDEO_OUTPUT 0x00000002  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CAP_VIDEO_OUTPUT 0x00000002  
 #define V4L2_CAP_VIDEO_OVERLAY 0x00000004  
 #define V4L2_CAP_VBI_CAPTURE 0x00000010  
 #define V4L2_CAP_VBI_OUTPUT 0x00000020  
-#define V4L2_CAP_SLICED_VBI_CAPTURE 0x00000040  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CAP_SLICED_VBI_CAPTURE 0x00000040  
 #define V4L2_CAP_SLICED_VBI_OUTPUT 0x00000080  
 #define V4L2_CAP_RDS_CAPTURE 0x00000100  
 #define V4L2_CAP_VIDEO_OUTPUT_OVERLAY 0x00000200  
-#define V4L2_CAP_HW_FREQ_SEEK 0x00000400  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CAP_HW_FREQ_SEEK 0x00000400  
 #define V4L2_CAP_RDS_OUTPUT 0x00000800  
 #define V4L2_CAP_VIDEO_CAPTURE_MPLANE 0x00001000
 #define V4L2_CAP_VIDEO_OUTPUT_MPLANE 0x00002000
-#define V4L2_CAP_TUNER 0x00010000  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CAP_TUNER 0x00010000  
 #define V4L2_CAP_AUDIO 0x00020000  
 #define V4L2_CAP_RADIO 0x00040000  
 #define V4L2_CAP_MODULATOR 0x00080000  
-#define V4L2_CAP_READWRITE 0x01000000  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CAP_READWRITE 0x01000000  
 #define V4L2_CAP_ASYNCIO 0x02000000  
 #define V4L2_CAP_STREAMING 0x04000000  
+#define V4L2_CAP_DEVICE_CAPS 0x80000000  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_pix_format {
  __u32 width;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 height;
  __u32 pixelformat;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  enum v4l2_field field;
  __u32 bytesperline;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 sizeimage;
  enum v4l2_colorspace colorspace;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 priv;
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_RGB332 v4l2_fourcc('R', 'G', 'B', '1')  
 #define V4L2_PIX_FMT_RGB444 v4l2_fourcc('R', '4', '4', '4')  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_RGB555 v4l2_fourcc('R', 'G', 'B', 'O')  
 #define V4L2_PIX_FMT_RGB565 v4l2_fourcc('R', 'G', 'B', 'P')  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R', 'G', 'B', 'Q')  
 #define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R', 'G', 'B', 'R')  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_BGR666 v4l2_fourcc('B', 'G', 'R', 'H')  
 #define V4L2_PIX_FMT_BGR24 v4l2_fourcc('B', 'G', 'R', '3')  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_RGB24 v4l2_fourcc('R', 'G', 'B', '3')  
 #define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B', 'G', 'R', '4')  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_RGB32 v4l2_fourcc('R', 'G', 'B', '4')  
 #define V4L2_PIX_FMT_GREY v4l2_fourcc('G', 'R', 'E', 'Y')  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_Y4 v4l2_fourcc('Y', '0', '4', ' ')  
 #define V4L2_PIX_FMT_Y6 v4l2_fourcc('Y', '0', '6', ' ')  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_Y10 v4l2_fourcc('Y', '1', '0', ' ')  
 #define V4L2_PIX_FMT_Y12 v4l2_fourcc('Y', '1', '2', ' ')  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_Y16 v4l2_fourcc('Y', '1', '6', ' ')  
 #define V4L2_PIX_FMT_Y10BPACK v4l2_fourcc('Y', '1', '0', 'B')  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_PAL8 v4l2_fourcc('P', 'A', 'L', '8')  
 #define V4L2_PIX_FMT_YVU410 v4l2_fourcc('Y', 'V', 'U', '9')  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_YVU420 v4l2_fourcc('Y', 'V', '1', '2')  
 #define V4L2_PIX_FMT_YUYV v4l2_fourcc('Y', 'U', 'Y', 'V')  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_YYUV v4l2_fourcc('Y', 'Y', 'U', 'V')  
 #define V4L2_PIX_FMT_YVYU v4l2_fourcc('Y', 'V', 'Y', 'U')  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_UYVY v4l2_fourcc('U', 'Y', 'V', 'Y')  
 #define V4L2_PIX_FMT_VYUY v4l2_fourcc('V', 'Y', 'U', 'Y')  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_YUV422P v4l2_fourcc('4', '2', '2', 'P')  
 #define V4L2_PIX_FMT_YUV411P v4l2_fourcc('4', '1', '1', 'P')  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_Y41P v4l2_fourcc('Y', '4', '1', 'P')  
 #define V4L2_PIX_FMT_YUV444 v4l2_fourcc('Y', '4', '4', '4')  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_YUV555 v4l2_fourcc('Y', 'U', 'V', 'O')  
 #define V4L2_PIX_FMT_YUV565 v4l2_fourcc('Y', 'U', 'V', 'P')  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_YUV32 v4l2_fourcc('Y', 'U', 'V', '4')  
 #define V4L2_PIX_FMT_YUV410 v4l2_fourcc('Y', 'U', 'V', '9')  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_YUV420 v4l2_fourcc('Y', 'U', '1', '2')  
 #define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4')  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2')  
 #define V4L2_PIX_FMT_M420 v4l2_fourcc('M', '4', '2', '0')  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2')  
 #define V4L2_PIX_FMT_NV21 v4l2_fourcc('N', 'V', '2', '1')  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_NV16 v4l2_fourcc('N', 'V', '1', '6')  
 #define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1')  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4')  
 #define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2')  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2')  
 #define V4L2_PIX_FMT_NV12MT v4l2_fourcc('T', 'M', '1', '2')  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_YUV420M v4l2_fourcc('Y', 'M', '1', '2')  
 #define V4L2_PIX_FMT_SBGGR8 v4l2_fourcc('B', 'A', '8', '1')  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_SGBRG8 v4l2_fourcc('G', 'B', 'R', 'G')  
 #define V4L2_PIX_FMT_SGRBG8 v4l2_fourcc('G', 'R', 'B', 'G')  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_SRGGB8 v4l2_fourcc('R', 'G', 'G', 'B')  
 #define V4L2_PIX_FMT_SBGGR10 v4l2_fourcc('B', 'G', '1', '0')  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_SGBRG10 v4l2_fourcc('G', 'B', '1', '0')  
 #define V4L2_PIX_FMT_SGRBG10 v4l2_fourcc('B', 'A', '1', '0')  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_SRGGB10 v4l2_fourcc('R', 'G', '1', '0')  
 #define V4L2_PIX_FMT_SBGGR12 v4l2_fourcc('B', 'G', '1', '2')  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_SGBRG12 v4l2_fourcc('G', 'B', '1', '2')  
 #define V4L2_PIX_FMT_SGRBG12 v4l2_fourcc('B', 'A', '1', '2')  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_SRGGB12 v4l2_fourcc('R', 'G', '1', '2')  
 #define V4L2_PIX_FMT_SGRBG10DPCM8 v4l2_fourcc('B', 'D', '1', '0')
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_SBGGR16 v4l2_fourcc('B', 'Y', 'R', '2')  
 #define V4L2_PIX_FMT_MJPEG v4l2_fourcc('M', 'J', 'P', 'G')  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_JPEG v4l2_fourcc('J', 'P', 'E', 'G')  
 #define V4L2_PIX_FMT_DV v4l2_fourcc('d', 'v', 's', 'd')  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_MPEG v4l2_fourcc('M', 'P', 'E', 'G')  
 #define V4L2_PIX_FMT_H264 v4l2_fourcc('H', '2', '6', '4')  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_H264_NO_SC v4l2_fourcc('A', 'V', 'C', '1')  
 #define V4L2_PIX_FMT_H263 v4l2_fourcc('H', '2', '6', '3')  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_MPEG1 v4l2_fourcc('M', 'P', 'G', '1')  
 #define V4L2_PIX_FMT_MPEG2 v4l2_fourcc('M', 'P', 'G', '2')  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_MPEG4 v4l2_fourcc('M', 'P', 'G', '4')  
 #define V4L2_PIX_FMT_XVID v4l2_fourcc('X', 'V', 'I', 'D')  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_PIX_FMT_VC1_ANNEX_G v4l2_fourcc('V', 'C', '1', 'G')  
 #define V4L2_PIX_FMT_VC1_ANNEX_L v4l2_fourcc('V', 'C', '1', 'L')  
-#define V4L2_PIX_FMT_CPIA1 v4l2_fourcc('C', 'P', 'I', 'A')  
-#define V4L2_PIX_FMT_WNVA v4l2_fourcc('W', 'N', 'V', 'A')  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_PIX_FMT_DIVX_311 v4l2_fourcc('D', 'I', 'V', '3')  
+#define V4L2_PIX_FMT_DIVX v4l2_fourcc('D', 'I', 'V', 'X')  
+#define V4L2_PIX_FMT_VP8 v4l2_fourcc('V', 'P', '8', '0')  
+#define V4L2_PIX_FMT_CPIA1 v4l2_fourcc('C', 'P', 'I', 'A')  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_PIX_FMT_WNVA v4l2_fourcc('W', 'N', 'V', 'A')  
 #define V4L2_PIX_FMT_SN9C10X v4l2_fourcc('S', '9', '1', '0')  
 #define V4L2_PIX_FMT_SN9C20X_I420 v4l2_fourcc('S', '9', '2', '0')  
 #define V4L2_PIX_FMT_PWC1 v4l2_fourcc('P', 'W', 'C', '1')  
-#define V4L2_PIX_FMT_PWC2 v4l2_fourcc('P', 'W', 'C', '2')  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_PIX_FMT_PWC2 v4l2_fourcc('P', 'W', 'C', '2')  
 #define V4L2_PIX_FMT_ET61X251 v4l2_fourcc('E', '6', '2', '5')  
 #define V4L2_PIX_FMT_SPCA501 v4l2_fourcc('S', '5', '0', '1')  
 #define V4L2_PIX_FMT_SPCA505 v4l2_fourcc('S', '5', '0', '5')  
-#define V4L2_PIX_FMT_SPCA508 v4l2_fourcc('S', '5', '0', '8')  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_PIX_FMT_SPCA508 v4l2_fourcc('S', '5', '0', '8')  
 #define V4L2_PIX_FMT_SPCA561 v4l2_fourcc('S', '5', '6', '1')  
 #define V4L2_PIX_FMT_PAC207 v4l2_fourcc('P', '2', '0', '7')  
 #define V4L2_PIX_FMT_MR97310A v4l2_fourcc('M', '3', '1', '0')  
-#define V4L2_PIX_FMT_JL2005BCD v4l2_fourcc('J', 'L', '2', '0')  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_PIX_FMT_JL2005BCD v4l2_fourcc('J', 'L', '2', '0')  
 #define V4L2_PIX_FMT_SN9C2028 v4l2_fourcc('S', 'O', 'N', 'X')  
 #define V4L2_PIX_FMT_SQ905C v4l2_fourcc('9', '0', '5', 'C')  
 #define V4L2_PIX_FMT_PJPG v4l2_fourcc('P', 'J', 'P', 'G')  
-#define V4L2_PIX_FMT_OV511 v4l2_fourcc('O', '5', '1', '1')  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_PIX_FMT_OV511 v4l2_fourcc('O', '5', '1', '1')  
 #define V4L2_PIX_FMT_OV518 v4l2_fourcc('O', '5', '1', '8')  
 #define V4L2_PIX_FMT_STV0680 v4l2_fourcc('S', '6', '8', '0')  
 #define V4L2_PIX_FMT_TM6000 v4l2_fourcc('T', 'M', '6', '0')  
-#define V4L2_PIX_FMT_CIT_YYVYUY v4l2_fourcc('C', 'I', 'T', 'V')  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_PIX_FMT_CIT_YYVYUY v4l2_fourcc('C', 'I', 'T', 'V')  
 #define V4L2_PIX_FMT_KONICA420 v4l2_fourcc('K', 'O', 'N', 'I')  
 #define V4L2_PIX_FMT_JPGL v4l2_fourcc('J', 'P', 'G', 'L')  
 #define V4L2_PIX_FMT_SE401 v4l2_fourcc('S', '4', '0', '1')  
-struct v4l2_fmtdesc {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct v4l2_fmtdesc {
  __u32 index;
  enum v4l2_buf_type type;
  __u32 flags;
- __u8 description[32];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u8 description[32];
  __u32 pixelformat;
  __u32 reserved[4];
 };
-#define V4L2_FMT_FLAG_COMPRESSED 0x0001
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_FMT_FLAG_COMPRESSED 0x0001
 #define V4L2_FMT_FLAG_EMULATED 0x0002
 enum v4l2_frmsizetypes {
  V4L2_FRMSIZE_TYPE_DISCRETE = 1,
- V4L2_FRMSIZE_TYPE_CONTINUOUS = 2,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_FRMSIZE_TYPE_CONTINUOUS = 2,
  V4L2_FRMSIZE_TYPE_STEPWISE = 3,
 };
 struct v4l2_frmsize_discrete {
- __u32 width;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 width;
  __u32 height;
 };
 struct v4l2_frmsize_stepwise {
- __u32 min_width;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 min_width;
  __u32 max_width;
  __u32 step_width;
  __u32 min_height;
- __u32 max_height;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 max_height;
  __u32 step_height;
 };
 struct v4l2_frmsizeenum {
- __u32 index;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 index;
  __u32 pixel_format;
  __u32 type;
  union {
- struct v4l2_frmsize_discrete discrete;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ struct v4l2_frmsize_discrete discrete;
  struct v4l2_frmsize_stepwise stepwise;
  };
  __u32 reserved[2];
-};
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
 enum v4l2_frmivaltypes {
  V4L2_FRMIVAL_TYPE_DISCRETE = 1,
  V4L2_FRMIVAL_TYPE_CONTINUOUS = 2,
- V4L2_FRMIVAL_TYPE_STEPWISE = 3,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_FRMIVAL_TYPE_STEPWISE = 3,
 };
 struct v4l2_frmival_stepwise {
  struct v4l2_fract min;
- struct v4l2_fract max;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ struct v4l2_fract max;
  struct v4l2_fract step;
 };
 struct v4l2_frmivalenum {
- __u32 index;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 index;
  __u32 pixel_format;
  __u32 width;
  __u32 height;
- __u32 type;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 type;
  union {
  struct v4l2_fract discrete;
  struct v4l2_frmival_stepwise stepwise;
- };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ };
  __u32 reserved[2];
 };
 struct v4l2_timecode {
- __u32 type;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 type;
  __u32 flags;
  __u8 frames;
  __u8 seconds;
- __u8 minutes;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u8 minutes;
  __u8 hours;
  __u8 userbits[4];
 };
-#define V4L2_TC_TYPE_24FPS 1
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_TC_TYPE_24FPS 1
 #define V4L2_TC_TYPE_25FPS 2
 #define V4L2_TC_TYPE_30FPS 3
 #define V4L2_TC_TYPE_50FPS 4
-#define V4L2_TC_TYPE_60FPS 5
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_TC_TYPE_60FPS 5
 #define V4L2_TC_FLAG_DROPFRAME 0x0001  
 #define V4L2_TC_FLAG_COLORFRAME 0x0002
 #define V4L2_TC_USERBITS_field 0x000C
-#define V4L2_TC_USERBITS_USERDEFINED 0x0000
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_TC_USERBITS_USERDEFINED 0x0000
 #define V4L2_TC_USERBITS_8BITCHARS 0x0008
 struct v4l2_jpegcompression {
  int quality;
- int APPn;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ int APPn;
  int APP_len;
  char APP_data[60];
  int COM_len;
- char COM_data[60];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ char COM_data[60];
  __u32 jpeg_markers;
 #define V4L2_JPEG_MARKER_DHT (1<<3)  
 #define V4L2_JPEG_MARKER_DQT (1<<4)  
-#define V4L2_JPEG_MARKER_DRI (1<<5)  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_JPEG_MARKER_DRI (1<<5)  
 #define V4L2_JPEG_MARKER_COM (1<<6)  
 #define V4L2_JPEG_MARKER_APP (1<<7)  
 };
-struct v4l2_requestbuffers {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct v4l2_requestbuffers {
  __u32 count;
  enum v4l2_buf_type type;
  enum v4l2_memory memory;
- __u32 reserved[2];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 reserved[2];
 };
 struct v4l2_plane {
  __u32 bytesused;
- __u32 length;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 length;
  union {
  __u32 mem_offset;
  unsigned long userptr;
- } m;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ } m;
  __u32 data_offset;
  __u32 reserved[11];
 };
-struct v4l2_buffer {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct v4l2_buffer {
  __u32 index;
  enum v4l2_buf_type type;
  __u32 bytesused;
- __u32 flags;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 flags;
  enum v4l2_field field;
  struct timeval timestamp;
  struct v4l2_timecode timecode;
- __u32 sequence;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 sequence;
  enum v4l2_memory memory;
  union {
  __u32 offset;
- unsigned long userptr;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned long userptr;
  struct v4l2_plane *planes;
  } m;
  __u32 length;
- __u32 input;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 input;
  __u32 reserved;
 };
 #define V4L2_BUF_FLAG_MAPPED 0x0001  
-#define V4L2_BUF_FLAG_QUEUED 0x0002  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_BUF_FLAG_QUEUED 0x0002  
 #define V4L2_BUF_FLAG_DONE 0x0004  
 #define V4L2_BUF_FLAG_KEYFRAME 0x0008  
 #define V4L2_BUF_FLAG_PFRAME 0x0010  
-#define V4L2_BUF_FLAG_BFRAME 0x0020  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_BUF_FLAG_BFRAME 0x0020  
 #define V4L2_BUF_FLAG_ERROR 0x0040
 #define V4L2_BUF_FLAG_TIMECODE 0x0100  
 #define V4L2_BUF_FLAG_INPUT 0x0200  
-#define V4L2_BUF_FLAG_PREPARED 0x0400  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_BUF_FLAG_PREPARED 0x0400  
 #define V4L2_BUF_FLAG_NO_CACHE_INVALIDATE 0x0800
 #define V4L2_BUF_FLAG_NO_CACHE_CLEAN 0x1000
+#define V4L2_BUF_FLAG_EOS 0x2000
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_framebuffer {
  __u32 capability;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 flags;
  void *base;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  struct v4l2_pix_format fmt;
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_FBUF_CAP_EXTERNOVERLAY 0x0001
 #define V4L2_FBUF_CAP_CHROMAKEY 0x0002
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_FBUF_CAP_LIST_CLIPPING 0x0004
 #define V4L2_FBUF_CAP_BITMAP_CLIPPING 0x0008
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_FBUF_CAP_LOCAL_ALPHA 0x0010
 #define V4L2_FBUF_CAP_GLOBAL_ALPHA 0x0020
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_FBUF_CAP_LOCAL_INV_ALPHA 0x0040
 #define V4L2_FBUF_CAP_SRC_CHROMAKEY 0x0080
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_FBUF_FLAG_PRIMARY 0x0001
 #define V4L2_FBUF_FLAG_OVERLAY 0x0002
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_FBUF_FLAG_CHROMAKEY 0x0004
 #define V4L2_FBUF_FLAG_LOCAL_ALPHA 0x0008
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_FBUF_FLAG_GLOBAL_ALPHA 0x0010
 #define V4L2_FBUF_FLAG_LOCAL_INV_ALPHA 0x0020
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_FBUF_FLAG_SRC_CHROMAKEY 0x0040
 struct v4l2_clip {
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  struct v4l2_rect c;
  struct v4l2_clip __user *next;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct v4l2_window {
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  struct v4l2_rect w;
  enum v4l2_field field;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 chromakey;
  struct v4l2_clip __user *clips;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 clipcount;
  void __user *bitmap;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u8 global_alpha;
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_captureparm {
  __u32 capability;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 capturemode;
  struct v4l2_fract timeperframe;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 extendedmode;
  __u32 readbuffers;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 reserved[4];
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_MODE_HIGHQUALITY 0x0001  
 #define V4L2_CAP_TIMEPERFRAME 0x1000  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CAP_QCOM_FRAMESKIP 0x2000  
+struct v4l2_qcom_frameskip {
+ __u64 maxframeinterval;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_outputparm {
  __u32 capability;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 outputmode;
  struct v4l2_fract timeperframe;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 extendedmode;
  __u32 writebuffers;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 reserved[4];
 };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_cropcap {
  enum v4l2_buf_type type;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  struct v4l2_rect bounds;
  struct v4l2_rect defrect;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  struct v4l2_fract pixelaspect;
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_crop {
  enum v4l2_buf_type type;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  struct v4l2_rect c;
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_SEL_FLAG_GE 0x00000001
 #define V4L2_SEL_FLAG_LE 0x00000002
-#define V4L2_SEL_TGT_CROP_ACTIVE 0
-#define V4L2_SEL_TGT_CROP_DEFAULT 1
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define V4L2_SEL_TGT_CROP_BOUNDS 2
-#define V4L2_SEL_TGT_COMPOSE_ACTIVE 256
-#define V4L2_SEL_TGT_COMPOSE_DEFAULT 257
-#define V4L2_SEL_TGT_COMPOSE_BOUNDS 258
+#define V4L2_SEL_TGT_CROP_ACTIVE 0x0000
+#define V4L2_SEL_TGT_CROP_DEFAULT 0x0001
+#define V4L2_SEL_TGT_CROP_BOUNDS 0x0002
+#define V4L2_SEL_TGT_COMPOSE_ACTIVE 0x0100
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define V4L2_SEL_TGT_COMPOSE_PADDED 259
+#define V4L2_SEL_TGT_COMPOSE_DEFAULT 0x0101
+#define V4L2_SEL_TGT_COMPOSE_BOUNDS 0x0102
+#define V4L2_SEL_TGT_COMPOSE_PADDED 0x0103
 struct v4l2_selection {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 type;
  __u32 target;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 flags;
  struct v4l2_rect r;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 reserved[9];
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef __u64 v4l2_std_id;
 #define V4L2_STD_PAL_B ((v4l2_std_id)0x00000001)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_PAL_B1 ((v4l2_std_id)0x00000002)
 #define V4L2_STD_PAL_G ((v4l2_std_id)0x00000004)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_PAL_H ((v4l2_std_id)0x00000008)
 #define V4L2_STD_PAL_I ((v4l2_std_id)0x00000010)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_PAL_D ((v4l2_std_id)0x00000020)
 #define V4L2_STD_PAL_D1 ((v4l2_std_id)0x00000040)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_PAL_K ((v4l2_std_id)0x00000080)
 #define V4L2_STD_PAL_M ((v4l2_std_id)0x00000100)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_PAL_N ((v4l2_std_id)0x00000200)
 #define V4L2_STD_PAL_Nc ((v4l2_std_id)0x00000400)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_PAL_60 ((v4l2_std_id)0x00000800)
 #define V4L2_STD_NTSC_M ((v4l2_std_id)0x00001000)  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_NTSC_M_JP ((v4l2_std_id)0x00002000)  
 #define V4L2_STD_NTSC_443 ((v4l2_std_id)0x00004000)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_NTSC_M_KR ((v4l2_std_id)0x00008000)  
 #define V4L2_STD_SECAM_B ((v4l2_std_id)0x00010000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_SECAM_D ((v4l2_std_id)0x00020000)
 #define V4L2_STD_SECAM_G ((v4l2_std_id)0x00040000)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_SECAM_H ((v4l2_std_id)0x00080000)
 #define V4L2_STD_SECAM_K ((v4l2_std_id)0x00100000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_SECAM_K1 ((v4l2_std_id)0x00200000)
 #define V4L2_STD_SECAM_L ((v4l2_std_id)0x00400000)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_SECAM_LC ((v4l2_std_id)0x00800000)
 #define V4L2_STD_ATSC_8_VSB ((v4l2_std_id)0x01000000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_ATSC_16_VSB ((v4l2_std_id)0x02000000)
 #define V4L2_STD_NTSC (V4L2_STD_NTSC_M |  V4L2_STD_NTSC_M_JP |  V4L2_STD_NTSC_M_KR)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_SECAM_DK (V4L2_STD_SECAM_D |  V4L2_STD_SECAM_K |  V4L2_STD_SECAM_K1)
 #define V4L2_STD_SECAM (V4L2_STD_SECAM_B |  V4L2_STD_SECAM_G |  V4L2_STD_SECAM_H |  V4L2_STD_SECAM_DK |  V4L2_STD_SECAM_L |  V4L2_STD_SECAM_LC)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_PAL_BG (V4L2_STD_PAL_B |  V4L2_STD_PAL_B1 |  V4L2_STD_PAL_G)
 #define V4L2_STD_PAL_DK (V4L2_STD_PAL_D |  V4L2_STD_PAL_D1 |  V4L2_STD_PAL_K)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_PAL (V4L2_STD_PAL_BG |  V4L2_STD_PAL_DK |  V4L2_STD_PAL_H |  V4L2_STD_PAL_I)
 #define V4L2_STD_B (V4L2_STD_PAL_B |  V4L2_STD_PAL_B1 |  V4L2_STD_SECAM_B)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_G (V4L2_STD_PAL_G |  V4L2_STD_SECAM_G)
 #define V4L2_STD_H (V4L2_STD_PAL_H |  V4L2_STD_SECAM_H)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_L (V4L2_STD_SECAM_L |  V4L2_STD_SECAM_LC)
 #define V4L2_STD_GH (V4L2_STD_G |  V4L2_STD_H)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_DK (V4L2_STD_PAL_DK |  V4L2_STD_SECAM_DK)
 #define V4L2_STD_BG (V4L2_STD_B |  V4L2_STD_G)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_MN (V4L2_STD_PAL_M |  V4L2_STD_PAL_N |  V4L2_STD_PAL_Nc |  V4L2_STD_NTSC)
 #define V4L2_STD_MTS (V4L2_STD_NTSC_M |  V4L2_STD_PAL_M |  V4L2_STD_PAL_N |  V4L2_STD_PAL_Nc)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_525_60 (V4L2_STD_PAL_M |  V4L2_STD_PAL_60 |  V4L2_STD_NTSC |  V4L2_STD_NTSC_443)
 #define V4L2_STD_625_50 (V4L2_STD_PAL |  V4L2_STD_PAL_N |  V4L2_STD_PAL_Nc |  V4L2_STD_SECAM)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_ATSC (V4L2_STD_ATSC_8_VSB |  V4L2_STD_ATSC_16_VSB)
 #define V4L2_STD_UNKNOWN 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_STD_ALL (V4L2_STD_525_60 |  V4L2_STD_625_50)
 struct v4l2_standard {
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 index;
  v4l2_std_id id;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u8 name[24];
  struct v4l2_fract frameperiod;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 framelines;
  __u32 reserved[4];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct v4l2_dv_preset {
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 preset;
  __u32 reserved[4];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct v4l2_dv_enum_preset {
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 index;
  __u32 preset;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u8 name[32];
  __u32 width;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 height;
  __u32 reserved[4];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define V4L2_DV_INVALID 0
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_DV_480P59_94 1  
 #define V4L2_DV_576P50 2  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_DV_720P24 3  
 #define V4L2_DV_720P25 4  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_DV_720P30 5  
 #define V4L2_DV_720P50 6  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_DV_720P59_94 7  
 #define V4L2_DV_720P60 8  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_DV_1080I29_97 9  
 #define V4L2_DV_1080I30 10  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_DV_1080I25 11  
 #define V4L2_DV_1080I50 12  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_DV_1080I60 13  
 #define V4L2_DV_1080P24 14  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_DV_1080P25 15  
 #define V4L2_DV_1080P30 16  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_DV_1080P50 17  
 #define V4L2_DV_1080P60 18  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_bt_timings {
  __u32 width;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 height;
  __u32 interlaced;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 polarities;
  __u64 pixelclock;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 hfrontporch;
  __u32 hsync;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 hbackporch;
  __u32 vfrontporch;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 vsync;
  __u32 vbackporch;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 il_vfrontporch;
  __u32 il_vsync;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 il_vbackporch;
  __u32 reserved[16];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } __attribute__ ((packed));
 #define V4L2_DV_PROGRESSIVE 0
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_DV_INTERLACED 1
 #define V4L2_DV_VSYNC_POS_POL 0x00000001
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_DV_HSYNC_POS_POL 0x00000002
 struct v4l2_dv_timings {
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 type;
  union {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  struct v4l2_bt_timings bt;
  __u32 reserved[32];
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  };
 } __attribute__ ((packed));
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_DV_BT_656_1120 0  
 struct v4l2_input {
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 index;
  __u8 name[32];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 type;
  __u32 audioset;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 tuner;
  v4l2_std_id std;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 status;
  __u32 capabilities;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 reserved[3];
 };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_INPUT_TYPE_TUNER 1
 #define V4L2_INPUT_TYPE_CAMERA 2
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_IN_ST_NO_POWER 0x00000001  
 #define V4L2_IN_ST_NO_SIGNAL 0x00000002
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_IN_ST_NO_COLOR 0x00000004
 #define V4L2_IN_ST_HFLIP 0x00000010  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_IN_ST_VFLIP 0x00000020  
 #define V4L2_IN_ST_NO_H_LOCK 0x00000100  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_IN_ST_COLOR_KILL 0x00000200  
 #define V4L2_IN_ST_NO_SYNC 0x00010000  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_IN_ST_NO_EQU 0x00020000  
 #define V4L2_IN_ST_NO_CARRIER 0x00040000  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_IN_ST_MACROVISION 0x01000000  
 #define V4L2_IN_ST_NO_ACCESS 0x02000000  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_IN_ST_VTR 0x04000000  
 #define V4L2_IN_CAP_PRESETS 0x00000001  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_IN_CAP_CUSTOM_TIMINGS 0x00000002  
 #define V4L2_IN_CAP_STD 0x00000004  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_output {
  __u32 index;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u8 name[32];
  __u32 type;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 audioset;
  __u32 modulator;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  v4l2_std_id std;
  __u32 capabilities;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 reserved[3];
 };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_OUTPUT_TYPE_MODULATOR 1
 #define V4L2_OUTPUT_TYPE_ANALOG 2
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_OUTPUT_TYPE_ANALOGVGAOVERLAY 3
 #define V4L2_OUT_CAP_PRESETS 0x00000001  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_OUT_CAP_CUSTOM_TIMINGS 0x00000002  
 #define V4L2_OUT_CAP_STD 0x00000004  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_control {
  __u32 id;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __s32 value;
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_ext_control {
  __u32 id;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 size;
  __u32 reserved2[1];
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  union {
  __s32 value;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __s64 value64;
  char *string;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  };
 } __attribute__ ((packed));
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_ext_controls {
  __u32 ctrl_class;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 count;
  __u32 error_idx;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 reserved[2];
  struct v4l2_ext_control *controls;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define V4L2_CTRL_CLASS_USER 0x00980000  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CTRL_CLASS_MPEG 0x00990000  
 #define V4L2_CTRL_CLASS_CAMERA 0x009a0000  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CTRL_CLASS_FM_TX 0x009b0000  
 #define V4L2_CTRL_CLASS_FLASH 0x009c0000  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CTRL_CLASS_JPEG 0x009d0000  
 #define V4L2_CTRL_ID_MASK (0x0fffffff)
 #define V4L2_CTRL_ID2CLASS(id) ((id) & 0x0fff0000UL)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CTRL_DRIVER_PRIV(id) (((id) & 0xffff) >= 0x1000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 enum v4l2_ctrl_type {
  V4L2_CTRL_TYPE_INTEGER = 1,
  V4L2_CTRL_TYPE_BOOLEAN = 2,
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_CTRL_TYPE_MENU = 3,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_CTRL_TYPE_BUTTON = 4,
  V4L2_CTRL_TYPE_INTEGER64 = 5,
  V4L2_CTRL_TYPE_CTRL_CLASS = 6,
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_CTRL_TYPE_STRING = 7,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_CTRL_TYPE_BITMASK = 8,
 };
 struct v4l2_queryctrl {
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 id;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  enum v4l2_ctrl_type type;
  __u8 name[32];
  __s32 minimum;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __s32 maximum;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __s32 step;
  __s32 default_value;
  __u32 flags;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 reserved[2];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct v4l2_querymenu {
  __u32 id;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 index;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u8 name[32];
  __u32 reserved;
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CTRL_FLAG_DISABLED 0x0001
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CTRL_FLAG_GRABBED 0x0002
 #define V4L2_CTRL_FLAG_READ_ONLY 0x0004
 #define V4L2_CTRL_FLAG_UPDATE 0x0008
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CTRL_FLAG_INACTIVE 0x0010
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CTRL_FLAG_SLIDER 0x0020
 #define V4L2_CTRL_FLAG_WRITE_ONLY 0x0040
 #define V4L2_CTRL_FLAG_VOLATILE 0x0080
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CTRL_FLAG_NEXT_CTRL 0x80000000
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_MAX_CTRLS 1024
 #define V4L2_CID_BASE (V4L2_CTRL_CLASS_USER | 0x900)
 #define V4L2_CID_USER_BASE V4L2_CID_BASE
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_PRIVATE_BASE 0x08000000
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_USER_CLASS (V4L2_CTRL_CLASS_USER | 1)
 #define V4L2_CID_BRIGHTNESS (V4L2_CID_BASE+0)
 #define V4L2_CID_CONTRAST (V4L2_CID_BASE+1)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_SATURATION (V4L2_CID_BASE+2)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_HUE (V4L2_CID_BASE+3)
 #define V4L2_CID_AUDIO_VOLUME (V4L2_CID_BASE+5)
 #define V4L2_CID_AUDIO_BALANCE (V4L2_CID_BASE+6)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_AUDIO_BASS (V4L2_CID_BASE+7)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_AUDIO_TREBLE (V4L2_CID_BASE+8)
 #define V4L2_CID_AUDIO_MUTE (V4L2_CID_BASE+9)
 #define V4L2_CID_AUDIO_LOUDNESS (V4L2_CID_BASE+10)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_BLACK_LEVEL (V4L2_CID_BASE+11)  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_AUTO_WHITE_BALANCE (V4L2_CID_BASE+12)
 #define V4L2_CID_DO_WHITE_BALANCE (V4L2_CID_BASE+13)
 #define V4L2_CID_RED_BALANCE (V4L2_CID_BASE+14)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_BLUE_BALANCE (V4L2_CID_BASE+15)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_GAMMA (V4L2_CID_BASE+16)
 #define V4L2_CID_WHITENESS (V4L2_CID_GAMMA)  
 #define V4L2_CID_EXPOSURE (V4L2_CID_BASE+17)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_AUTOGAIN (V4L2_CID_BASE+18)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_GAIN (V4L2_CID_BASE+19)
 #define V4L2_CID_HFLIP (V4L2_CID_BASE+20)
 #define V4L2_CID_VFLIP (V4L2_CID_BASE+21)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_HCENTER (V4L2_CID_BASE+22)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_VCENTER (V4L2_CID_BASE+23)
 #define V4L2_CID_POWER_LINE_FREQUENCY (V4L2_CID_BASE+24)
 enum v4l2_power_line_frequency {
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_CID_POWER_LINE_FREQUENCY_DISABLED = 0,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_CID_POWER_LINE_FREQUENCY_50HZ = 1,
  V4L2_CID_POWER_LINE_FREQUENCY_60HZ = 2,
  V4L2_CID_POWER_LINE_FREQUENCY_AUTO = 3,
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_HUE_AUTO (V4L2_CID_BASE+25)
 #define V4L2_CID_WHITE_BALANCE_TEMPERATURE (V4L2_CID_BASE+26)
 #define V4L2_CID_SHARPNESS (V4L2_CID_BASE+27)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_BACKLIGHT_COMPENSATION (V4L2_CID_BASE+28)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_CHROMA_AGC (V4L2_CID_BASE+29)
 #define V4L2_CID_COLOR_KILLER (V4L2_CID_BASE+30)
 #define V4L2_CID_COLORFX (V4L2_CID_BASE+31)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 enum v4l2_colorfx {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_COLORFX_NONE = 0,
  V4L2_COLORFX_BW = 1,
  V4L2_COLORFX_SEPIA = 2,
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_COLORFX_NEGATIVE = 3,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_COLORFX_EMBOSS = 4,
  V4L2_COLORFX_SKETCH = 5,
  V4L2_COLORFX_SKY_BLUE = 6,
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_COLORFX_GRASS_GREEN = 7,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_COLORFX_SKIN_WHITEN = 8,
  V4L2_COLORFX_VIVID = 9,
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_AUTOBRIGHTNESS (V4L2_CID_BASE+32)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_BAND_STOP_FILTER (V4L2_CID_BASE+33)
 #define V4L2_CID_ROTATE (V4L2_CID_BASE+34)
 #define V4L2_CID_BG_COLOR (V4L2_CID_BASE+35)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_CHROMA_GAIN (V4L2_CID_BASE+36)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_ILLUMINATORS_1 (V4L2_CID_BASE+37)
 #define V4L2_CID_ILLUMINATORS_2 (V4L2_CID_BASE+38)
 #define V4L2_CID_MIN_BUFFERS_FOR_CAPTURE (V4L2_CID_BASE+39)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_MIN_BUFFERS_FOR_OUTPUT (V4L2_CID_BASE+40)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_ALPHA_COMPONENT (V4L2_CID_BASE+41)
 #define V4L2_CID_LASTP1 (V4L2_CID_BASE+42)
+#define V4L2_CID_SPECIAL_EFFECT (V4L2_CID_BASE+43)
 #define V4L2_CID_MPEG_BASE (V4L2_CTRL_CLASS_MPEG | 0x900)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_MPEG_CLASS (V4L2_CTRL_CLASS_MPEG | 1)
@@ -1104,851 +1119,1017 @@
  V4L2_MPEG_AUDIO_AC3_BITRATE_576K = 17,
  V4L2_MPEG_AUDIO_AC3_BITRATE_640K = 18,
 };
-#define V4L2_CID_MPEG_VIDEO_ENCODING (V4L2_CID_MPEG_BASE+200)
+#define V4L2_CID_MPEG_AUDIO_DEC_PLAYBACK (V4L2_CID_MPEG_BASE+112)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+enum v4l2_mpeg_audio_dec_playback {
+ V4L2_MPEG_AUDIO_DEC_PLAYBACK_AUTO = 0,
+ V4L2_MPEG_AUDIO_DEC_PLAYBACK_STEREO = 1,
+ V4L2_MPEG_AUDIO_DEC_PLAYBACK_LEFT = 2,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_AUDIO_DEC_PLAYBACK_RIGHT = 3,
+ V4L2_MPEG_AUDIO_DEC_PLAYBACK_MONO = 4,
+ V4L2_MPEG_AUDIO_DEC_PLAYBACK_SWAPPED_STEREO = 5,
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_AUDIO_DEC_MULTILINGUAL_PLAYBACK (V4L2_CID_MPEG_BASE+113)
+#define V4L2_CID_MPEG_VIDEO_ENCODING (V4L2_CID_MPEG_BASE+200)
 enum v4l2_mpeg_video_encoding {
  V4L2_MPEG_VIDEO_ENCODING_MPEG_1 = 0,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_MPEG_VIDEO_ENCODING_MPEG_2 = 1,
  V4L2_MPEG_VIDEO_ENCODING_MPEG_4_AVC = 2,
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define V4L2_CID_MPEG_VIDEO_ASPECT (V4L2_CID_MPEG_BASE+201)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 enum v4l2_mpeg_video_aspect {
  V4L2_MPEG_VIDEO_ASPECT_1x1 = 0,
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_MPEG_VIDEO_ASPECT_4x3 = 1,
  V4L2_MPEG_VIDEO_ASPECT_16x9 = 2,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_MPEG_VIDEO_ASPECT_221x100 = 3,
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_MPEG_VIDEO_B_FRAMES (V4L2_CID_MPEG_BASE+202)
 #define V4L2_CID_MPEG_VIDEO_GOP_SIZE (V4L2_CID_MPEG_BASE+203)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_MPEG_VIDEO_GOP_CLOSURE (V4L2_CID_MPEG_BASE+204)
 #define V4L2_CID_MPEG_VIDEO_PULLDOWN (V4L2_CID_MPEG_BASE+205)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_MPEG_VIDEO_BITRATE_MODE (V4L2_CID_MPEG_BASE+206)
 enum v4l2_mpeg_video_bitrate_mode {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_MPEG_VIDEO_BITRATE_MODE_VBR = 0,
  V4L2_MPEG_VIDEO_BITRATE_MODE_CBR = 1,
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define V4L2_CID_MPEG_VIDEO_BITRATE (V4L2_CID_MPEG_BASE+207)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_MPEG_VIDEO_BITRATE_PEAK (V4L2_CID_MPEG_BASE+208)
 #define V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION (V4L2_CID_MPEG_BASE+209)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_MPEG_VIDEO_MUTE (V4L2_CID_MPEG_BASE+210)
 #define V4L2_CID_MPEG_VIDEO_MUTE_YUV (V4L2_CID_MPEG_BASE+211)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE (V4L2_CID_MPEG_BASE+212)
 #define V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER (V4L2_CID_MPEG_BASE+213)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB (V4L2_CID_MPEG_BASE+214)
 #define V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE (V4L2_CID_MPEG_BASE+215)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_MPEG_VIDEO_HEADER_MODE (V4L2_CID_MPEG_BASE+216)
 enum v4l2_mpeg_video_header_mode {
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE = 0,
  V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME = 1,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_I_FRAME = 2,
 };
 #define V4L2_CID_MPEG_VIDEO_MAX_REF_PIC (V4L2_CID_MPEG_BASE+217)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE (V4L2_CID_MPEG_BASE+218)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES (V4L2_CID_MPEG_BASE+219)
 #define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB (V4L2_CID_MPEG_BASE+220)
 #define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE (V4L2_CID_MPEG_BASE+221)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 enum v4l2_mpeg_video_multi_slice_mode {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE = 0,
  V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB = 1,
  V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES = 2,
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
-#define V4L2_CID_MPEG_VIDEO_VBV_SIZE (V4L2_CID_MPEG_BASE+222)
-#define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP (V4L2_CID_MPEG_BASE+300)
-#define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP (V4L2_CID_MPEG_BASE+301)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_VIDEO_VBV_SIZE (V4L2_CID_MPEG_BASE+222)
+#define V4L2_CID_MPEG_VIDEO_DEC_PTS (V4L2_CID_MPEG_BASE+223)
+#define V4L2_CID_MPEG_VIDEO_DEC_FRAME (V4L2_CID_MPEG_BASE+224)
+#define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP (V4L2_CID_MPEG_BASE+300)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP (V4L2_CID_MPEG_BASE+301)
 #define V4L2_CID_MPEG_VIDEO_H263_B_FRAME_QP (V4L2_CID_MPEG_BASE+302)
 #define V4L2_CID_MPEG_VIDEO_H263_MIN_QP (V4L2_CID_MPEG_BASE+303)
 #define V4L2_CID_MPEG_VIDEO_H263_MAX_QP (V4L2_CID_MPEG_BASE+304)
-#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP (V4L2_CID_MPEG_BASE+350)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP (V4L2_CID_MPEG_BASE+350)
 #define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP (V4L2_CID_MPEG_BASE+351)
 #define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP (V4L2_CID_MPEG_BASE+352)
 #define V4L2_CID_MPEG_VIDEO_H264_MIN_QP (V4L2_CID_MPEG_BASE+353)
-#define V4L2_CID_MPEG_VIDEO_H264_MAX_QP (V4L2_CID_MPEG_BASE+354)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_VIDEO_H264_MAX_QP (V4L2_CID_MPEG_BASE+354)
 #define V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM (V4L2_CID_MPEG_BASE+355)
 #define V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE (V4L2_CID_MPEG_BASE+356)
 #define V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE (V4L2_CID_MPEG_BASE+357)
-enum v4l2_mpeg_video_h264_entropy_mode {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+enum v4l2_mpeg_video_h264_entropy_mode {
  V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC = 0,
  V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC = 1,
 };
-#define V4L2_CID_MPEG_VIDEO_H264_I_PERIOD (V4L2_CID_MPEG_BASE+358)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_VIDEO_H264_I_PERIOD (V4L2_CID_MPEG_BASE+358)
 #define V4L2_CID_MPEG_VIDEO_H264_LEVEL (V4L2_CID_MPEG_BASE+359)
 enum v4l2_mpeg_video_h264_level {
  V4L2_MPEG_VIDEO_H264_LEVEL_1_0 = 0,
- V4L2_MPEG_VIDEO_H264_LEVEL_1B = 1,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_VIDEO_H264_LEVEL_1B = 1,
  V4L2_MPEG_VIDEO_H264_LEVEL_1_1 = 2,
  V4L2_MPEG_VIDEO_H264_LEVEL_1_2 = 3,
  V4L2_MPEG_VIDEO_H264_LEVEL_1_3 = 4,
- V4L2_MPEG_VIDEO_H264_LEVEL_2_0 = 5,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_VIDEO_H264_LEVEL_2_0 = 5,
  V4L2_MPEG_VIDEO_H264_LEVEL_2_1 = 6,
  V4L2_MPEG_VIDEO_H264_LEVEL_2_2 = 7,
  V4L2_MPEG_VIDEO_H264_LEVEL_3_0 = 8,
- V4L2_MPEG_VIDEO_H264_LEVEL_3_1 = 9,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_VIDEO_H264_LEVEL_3_1 = 9,
  V4L2_MPEG_VIDEO_H264_LEVEL_3_2 = 10,
  V4L2_MPEG_VIDEO_H264_LEVEL_4_0 = 11,
  V4L2_MPEG_VIDEO_H264_LEVEL_4_1 = 12,
- V4L2_MPEG_VIDEO_H264_LEVEL_4_2 = 13,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_VIDEO_H264_LEVEL_4_2 = 13,
  V4L2_MPEG_VIDEO_H264_LEVEL_5_0 = 14,
  V4L2_MPEG_VIDEO_H264_LEVEL_5_1 = 15,
 };
-#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA (V4L2_CID_MPEG_BASE+360)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA (V4L2_CID_MPEG_BASE+360)
 #define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA (V4L2_CID_MPEG_BASE+361)
 #define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE (V4L2_CID_MPEG_BASE+362)
 enum v4l2_mpeg_video_h264_loop_filter_mode {
- V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED = 0,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED = 0,
  V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED = 1,
  V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY = 2,
 };
-#define V4L2_CID_MPEG_VIDEO_H264_PROFILE (V4L2_CID_MPEG_BASE+363)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_VIDEO_H264_PROFILE (V4L2_CID_MPEG_BASE+363)
 enum v4l2_mpeg_video_h264_profile {
  V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE = 0,
  V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE = 1,
- V4L2_MPEG_VIDEO_H264_PROFILE_MAIN = 2,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_VIDEO_H264_PROFILE_MAIN = 2,
  V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED = 3,
  V4L2_MPEG_VIDEO_H264_PROFILE_HIGH = 4,
  V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10 = 5,
- V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422 = 6,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422 = 6,
  V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE = 7,
  V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10_INTRA = 8,
  V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422_INTRA = 9,
- V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_INTRA = 10,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_INTRA = 10,
  V4L2_MPEG_VIDEO_H264_PROFILE_CAVLC_444_INTRA = 11,
  V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_BASELINE = 12,
  V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH = 13,
- V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH_INTRA = 14,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH_INTRA = 14,
  V4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH = 15,
  V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH = 16,
 };
-#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT (V4L2_CID_MPEG_BASE+364)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT (V4L2_CID_MPEG_BASE+364)
 #define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH (V4L2_CID_MPEG_BASE+365)
 #define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE (V4L2_CID_MPEG_BASE+366)
 #define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC (V4L2_CID_MPEG_BASE+367)
-enum v4l2_mpeg_video_h264_vui_sar_idc {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+enum v4l2_mpeg_video_h264_vui_sar_idc {
  V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED = 0,
  V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1 = 1,
  V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_12x11 = 2,
- V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_10x11 = 3,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_10x11 = 3,
  V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_16x11 = 4,
  V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_40x33 = 5,
  V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_24x11 = 6,
- V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_20x11 = 7,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_20x11 = 7,
  V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_32x11 = 8,
  V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_80x33 = 9,
  V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_18x11 = 10,
- V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_15x11 = 11,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_15x11 = 11,
  V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_64x33 = 12,
  V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_160x99 = 13,
  V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_4x3 = 14,
- V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_3x2 = 15,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_3x2 = 15,
  V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_2x1 = 16,
  V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED = 17,
 };
-#define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (V4L2_CID_MPEG_BASE+400)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (V4L2_CID_MPEG_BASE+400)
 #define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP (V4L2_CID_MPEG_BASE+401)
 #define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP (V4L2_CID_MPEG_BASE+402)
 #define V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP (V4L2_CID_MPEG_BASE+403)
-#define V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP (V4L2_CID_MPEG_BASE+404)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP (V4L2_CID_MPEG_BASE+404)
 #define V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL (V4L2_CID_MPEG_BASE+405)
 enum v4l2_mpeg_video_mpeg4_level {
  V4L2_MPEG_VIDEO_MPEG4_LEVEL_0 = 0,
- V4L2_MPEG_VIDEO_MPEG4_LEVEL_0B = 1,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_VIDEO_MPEG4_LEVEL_0B = 1,
  V4L2_MPEG_VIDEO_MPEG4_LEVEL_1 = 2,
  V4L2_MPEG_VIDEO_MPEG4_LEVEL_2 = 3,
  V4L2_MPEG_VIDEO_MPEG4_LEVEL_3 = 4,
- V4L2_MPEG_VIDEO_MPEG4_LEVEL_3B = 5,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_VIDEO_MPEG4_LEVEL_3B = 5,
  V4L2_MPEG_VIDEO_MPEG4_LEVEL_4 = 6,
  V4L2_MPEG_VIDEO_MPEG4_LEVEL_5 = 7,
 };
-#define V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE (V4L2_CID_MPEG_BASE+406)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE (V4L2_CID_MPEG_BASE+406)
 enum v4l2_mpeg_video_mpeg4_profile {
  V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE = 0,
  V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE = 1,
- V4L2_MPEG_VIDEO_MPEG4_PROFILE_CORE = 2,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_VIDEO_MPEG4_PROFILE_CORE = 2,
  V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE_SCALABLE = 3,
  V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_CODING_EFFICIENCY = 4,
 };
-#define V4L2_CID_MPEG_VIDEO_MPEG4_QPEL (V4L2_CID_MPEG_BASE+407)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_VIDEO_MPEG4_QPEL (V4L2_CID_MPEG_BASE+407)
 #define V4L2_CID_MPEG_CX2341X_BASE (V4L2_CTRL_CLASS_MPEG | 0x1000)
 #define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+0)
 enum v4l2_mpeg_cx2341x_video_spatial_filter_mode {
- V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_MANUAL = 0,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_MANUAL = 0,
  V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_AUTO = 1,
 };
 #define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE+1)
-#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+2)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+2)
 enum v4l2_mpeg_cx2341x_video_luma_spatial_filter_type {
  V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_OFF = 0,
  V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_HOR = 1,
- V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_VERT = 2,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_VERT = 2,
  V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_HV_SEPARABLE = 3,
  V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_SYM_NON_SEPARABLE = 4,
 };
-#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+3)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+3)
 enum v4l2_mpeg_cx2341x_video_chroma_spatial_filter_type {
  V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_OFF = 0,
  V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_1D_HOR = 1,
-};
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
 #define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+4)
 enum v4l2_mpeg_cx2341x_video_temporal_filter_mode {
  V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_MANUAL = 0,
- V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_AUTO = 1,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_AUTO = 1,
 };
 #define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE+5)
 #define V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+6)
-enum v4l2_mpeg_cx2341x_video_median_filter_type {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+enum v4l2_mpeg_cx2341x_video_median_filter_type {
  V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_OFF = 0,
  V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR = 1,
  V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_VERT = 2,
- V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR_VERT = 3,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR_VERT = 3,
  V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_DIAG = 4,
 };
 #define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE+7)
-#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+8)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+8)
 #define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE+9)
 #define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+10)
 #define V4L2_CID_MPEG_CX2341X_STREAM_INSERT_NAV_PACKETS (V4L2_CID_MPEG_CX2341X_BASE+11)
-#define V4L2_CID_MPEG_MFC51_BASE (V4L2_CTRL_CLASS_MPEG | 0x1100)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_MFC51_BASE (V4L2_CTRL_CLASS_MPEG | 0x1100)
+#define V4L2_CID_MPEG_QCOM_BASE (V4L2_CTRL_CLASS_MPEG | 0x2100)
+#define V4L2_CID_MPEG_QCOM_SET_PERF_LEVEL (V4L2_CID_MPEG_QCOM_BASE + 0)
+enum v3l2_mpeg_qcom_perf_level {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_CID_MPEG_QCOM_PERF_LEVEL_PERFORMANCE = 0,
+ V4L2_CID_MPEG_QCOM_PERF_LEVEL_TURBO = 1,
+};
 #define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY (V4L2_CID_MPEG_MFC51_BASE+0)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY_ENABLE (V4L2_CID_MPEG_MFC51_BASE+1)
 #define V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE (V4L2_CID_MPEG_MFC51_BASE+2)
 enum v4l2_mpeg_mfc51_video_frame_skip_mode {
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_DISABLED = 0,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT = 1,
  V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT = 2,
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE (V4L2_CID_MPEG_MFC51_BASE+3)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 enum v4l2_mpeg_mfc51_video_force_frame_type {
  V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_DISABLED = 0,
  V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_I_FRAME = 1,
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_NOT_CODED = 2,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define V4L2_CID_MPEG_MFC51_VIDEO_PADDING (V4L2_CID_MPEG_MFC51_BASE+4)
 #define V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV (V4L2_CID_MPEG_MFC51_BASE+5)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT (V4L2_CID_MPEG_MFC51_BASE+6)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF (V4L2_CID_MPEG_MFC51_BASE+7)
 #define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY (V4L2_CID_MPEG_MFC51_BASE+50)
 #define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK (V4L2_CID_MPEG_MFC51_BASE+51)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH (V4L2_CID_MPEG_MFC51_BASE+52)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC (V4L2_CID_MPEG_MFC51_BASE+53)
 #define V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P (V4L2_CID_MPEG_MFC51_BASE+54)
-#define V4L2_CID_CAMERA_CLASS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x900)
+#define V4L2_CID_MPEG_MSM_VIDC_BASE (V4L2_CTRL_CLASS_MPEG | 0x2000)
+#define V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_PICTURE_TYPE   (V4L2_CID_MPEG_MSM_VIDC_BASE+0)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_VIDC_VIDEO_KEEP_ASPECT_RATIO   (V4L2_CID_MPEG_MSM_VIDC_BASE+1)
+#define V4L2_CID_MPEG_VIDC_VIDEO_POST_LOOP_DEBLOCKER_MODE   (V4L2_CID_MPEG_MSM_VIDC_BASE+2)
+#define V4L2_CID_MPEG_VIDC_VIDEO_DIVX_FORMAT   (V4L2_CID_MPEG_MSM_VIDC_BASE+3)
+enum v4l2_mpeg_vidc_video_divx_format_type {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_4 = 0,
+ V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_5 = 1,
+ V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_6 = 2,
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_VIDC_VIDEO_MB_ERROR_MAP_REPORTING   (V4L2_CID_MPEG_MSM_VIDC_BASE+4)
+#define V4L2_CID_MPEG_VIDC_VIDEO_CONTINUE_DATA_TRANSFER   (V4L2_CID_MPEG_MSM_VIDC_BASE+5)
+#define V4L2_CID_MPEG_VIDC_VIDEO_STREAM_FORMAT (V4L2_CID_MPEG_MSM_VIDC_BASE+6)
+enum v4l2_mpeg_vidc_video_stream_format {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_STARTCODES = 0,
+ V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_ONE_NAL_PER_BUFFER = 1,
+ V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_ONE_BYTE_LENGTH = 2,
+ V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_TWO_BYTE_LENGTH = 3,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_FOUR_BYTE_LENGTH = 4,
+};
+#define V4L2_CID_MPEG_VIDC_VIDEO_OUTPUT_ORDER (V4L2_CID_MPEG_MSM_VIDC_BASE+7)
+enum v4l2_mpeg_vidc_video_output_order {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_MPEG_VIDC_VIDEO_OUTPUT_ORDER_DISPLAY = 0,
+ V4L2_MPEG_VIDC_VIDEO_OUTPUT_ORDER_DECODE = 1,
+};
+#define V4L2_CID_MPEG_VIDC_VIDEO_FRAME_RATE (V4L2_CID_MPEG_MSM_VIDC_BASE+8)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_VIDC_VIDEO_IDR_PERIOD (V4L2_CID_MPEG_MSM_VIDC_BASE+9)
+#define V4L2_CID_MPEG_VIDC_VIDEO_NUM_P_FRAMES (V4L2_CID_MPEG_MSM_VIDC_BASE+10)
+#define V4L2_CID_MPEG_VIDC_VIDEO_NUM_B_FRAMES (V4L2_CID_MPEG_MSM_VIDC_BASE+11)
+#define V4L2_CID_MPEG_VIDC_VIDEO_REQUEST_IFRAME (V4L2_CID_MPEG_MSM_VIDC_BASE+12)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL (V4L2_CID_MPEG_MSM_VIDC_BASE+13)
+enum v4l2_mpeg_vidc_video_rate_control {
+ V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_OFF = 0,
+ V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_VFR = 1,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_CFR = 2,
+ V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_VFR = 3,
+ V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_CFR = 4,
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_VIDC_VIDEO_ROTATION (V4L2_CID_MPEG_MSM_VIDC_BASE+14)
+enum v4l2_mpeg_vidc_video_rotation {
+ V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_NONE = 0,
+ V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_90 = 1,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_180 = 2,
+ V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_270 = 3,
+};
+#define MSM_VIDC_BASE V4L2_CID_MPEG_MSM_VIDC_BASE
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL (MSM_VIDC_BASE+15)
+enum v4l2_mpeg_vidc_h264_cabac_model {
+ V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_0 = 0,
+ V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_1 = 1,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_2 = 2,
+};
+#define V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_MODE (MSM_VIDC_BASE+16)
+enum v4l2_mpeg_vidc_video_intra_refresh_mode {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_NONE = 0,
+ V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_CYCLIC = 1,
+ V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_ADAPTIVE = 2,
+ V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_CYCLIC_ADAPTIVE = 3,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_RANDOM = 4,
+};
+#define V4L2_CID_MPEG_VIDC_VIDEO_AIR_MBS (V4L2_CID_MPEG_MSM_VIDC_BASE+17)
+#define V4L2_CID_MPEG_VIDC_VIDEO_AIR_REF (V4L2_CID_MPEG_MSM_VIDC_BASE+18)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_MPEG_VIDC_VIDEO_CIR_MBS (V4L2_CID_MPEG_MSM_VIDC_BASE+19)
+#define V4L2_CID_CAMERA_CLASS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x900)
 #define V4L2_CID_CAMERA_CLASS (V4L2_CTRL_CLASS_CAMERA | 1)
 #define V4L2_CID_EXPOSURE_AUTO (V4L2_CID_CAMERA_CLASS_BASE+1)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 enum v4l2_exposure_auto_type {
  V4L2_EXPOSURE_AUTO = 0,
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_EXPOSURE_MANUAL = 1,
  V4L2_EXPOSURE_SHUTTER_PRIORITY = 2,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_EXPOSURE_APERTURE_PRIORITY = 3
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_EXPOSURE_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+2)
 #define V4L2_CID_EXPOSURE_AUTO_PRIORITY (V4L2_CID_CAMERA_CLASS_BASE+3)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_PAN_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+4)
 #define V4L2_CID_TILT_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+5)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_PAN_RESET (V4L2_CID_CAMERA_CLASS_BASE+6)
 #define V4L2_CID_TILT_RESET (V4L2_CID_CAMERA_CLASS_BASE+7)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_PAN_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+8)
 #define V4L2_CID_TILT_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+9)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_FOCUS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+10)
 #define V4L2_CID_FOCUS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+11)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_FOCUS_AUTO (V4L2_CID_CAMERA_CLASS_BASE+12)
 #define V4L2_CID_ZOOM_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+13)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_ZOOM_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+14)
 #define V4L2_CID_ZOOM_CONTINUOUS (V4L2_CID_CAMERA_CLASS_BASE+15)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_PRIVACY (V4L2_CID_CAMERA_CLASS_BASE+16)
 #define V4L2_CID_IRIS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+17)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_IRIS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+18)
 #define V4L2_CID_FM_TX_CLASS_BASE (V4L2_CTRL_CLASS_FM_TX | 0x900)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_FM_TX_CLASS (V4L2_CTRL_CLASS_FM_TX | 1)
 #define V4L2_CID_RDS_TX_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 1)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_RDS_TX_PI (V4L2_CID_FM_TX_CLASS_BASE + 2)
 #define V4L2_CID_RDS_TX_PTY (V4L2_CID_FM_TX_CLASS_BASE + 3)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_RDS_TX_PS_NAME (V4L2_CID_FM_TX_CLASS_BASE + 5)
 #define V4L2_CID_RDS_TX_RADIO_TEXT (V4L2_CID_FM_TX_CLASS_BASE + 6)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_AUDIO_LIMITER_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 64)
 #define V4L2_CID_AUDIO_LIMITER_RELEASE_TIME (V4L2_CID_FM_TX_CLASS_BASE + 65)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_AUDIO_LIMITER_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 66)
 #define V4L2_CID_AUDIO_COMPRESSION_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 80)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_AUDIO_COMPRESSION_GAIN (V4L2_CID_FM_TX_CLASS_BASE + 81)
 #define V4L2_CID_AUDIO_COMPRESSION_THRESHOLD (V4L2_CID_FM_TX_CLASS_BASE + 82)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_AUDIO_COMPRESSION_ATTACK_TIME (V4L2_CID_FM_TX_CLASS_BASE + 83)
 #define V4L2_CID_AUDIO_COMPRESSION_RELEASE_TIME (V4L2_CID_FM_TX_CLASS_BASE + 84)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_PILOT_TONE_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 96)
 #define V4L2_CID_PILOT_TONE_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 97)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_PILOT_TONE_FREQUENCY (V4L2_CID_FM_TX_CLASS_BASE + 98)
 #define V4L2_CID_TUNE_PREEMPHASIS (V4L2_CID_FM_TX_CLASS_BASE + 112)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 enum v4l2_preemphasis {
  V4L2_PREEMPHASIS_DISABLED = 0,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_PREEMPHASIS_50_uS = 1,
  V4L2_PREEMPHASIS_75_uS = 2,
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define V4L2_CID_TUNE_POWER_LEVEL (V4L2_CID_FM_TX_CLASS_BASE + 113)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_TUNE_ANTENNA_CAPACITOR (V4L2_CID_FM_TX_CLASS_BASE + 114)
 #define V4L2_CID_FLASH_CLASS_BASE (V4L2_CTRL_CLASS_FLASH | 0x900)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_FLASH_CLASS (V4L2_CTRL_CLASS_FLASH | 1)
 #define V4L2_CID_FLASH_LED_MODE (V4L2_CID_FLASH_CLASS_BASE + 1)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 enum v4l2_flash_led_mode {
  V4L2_FLASH_LED_MODE_NONE,
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_FLASH_LED_MODE_FLASH,
  V4L2_FLASH_LED_MODE_TORCH,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define V4L2_CID_FLASH_STROBE_SOURCE (V4L2_CID_FLASH_CLASS_BASE + 2)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 enum v4l2_flash_strobe_source {
  V4L2_FLASH_STROBE_SOURCE_SOFTWARE,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  V4L2_FLASH_STROBE_SOURCE_EXTERNAL,
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_FLASH_STROBE (V4L2_CID_FLASH_CLASS_BASE + 3)
 #define V4L2_CID_FLASH_STROBE_STOP (V4L2_CID_FLASH_CLASS_BASE + 4)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_FLASH_STROBE_STATUS (V4L2_CID_FLASH_CLASS_BASE + 5)
 #define V4L2_CID_FLASH_TIMEOUT (V4L2_CID_FLASH_CLASS_BASE + 6)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_FLASH_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 7)
 #define V4L2_CID_FLASH_TORCH_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 8)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_FLASH_INDICATOR_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 9)
 #define V4L2_CID_FLASH_FAULT (V4L2_CID_FLASH_CLASS_BASE + 10)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_FLASH_FAULT_OVER_VOLTAGE (1 << 0)
 #define V4L2_FLASH_FAULT_TIMEOUT (1 << 1)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_FLASH_FAULT_OVER_TEMPERATURE (1 << 2)
 #define V4L2_FLASH_FAULT_SHORT_CIRCUIT (1 << 3)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_FLASH_FAULT_OVER_CURRENT (1 << 4)
 #define V4L2_FLASH_FAULT_INDICATOR (1 << 5)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CID_FLASH_CHARGE (V4L2_CID_FLASH_CLASS_BASE + 11)
 #define V4L2_CID_FLASH_READY (V4L2_CID_FLASH_CLASS_BASE + 12)
+#define V4L2_CID_JPEG_CLASS_BASE (V4L2_CTRL_CLASS_JPEG | 0x900)
+#define V4L2_CID_JPEG_CLASS (V4L2_CTRL_CLASS_JPEG | 1)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_CID_JPEG_CHROMA_SUBSAMPLING (V4L2_CID_JPEG_CLASS_BASE + 1)
+enum v4l2_jpeg_chroma_subsampling {
+ V4L2_JPEG_CHROMA_SUBSAMPLING_444 = 0,
+ V4L2_JPEG_CHROMA_SUBSAMPLING_422 = 1,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ V4L2_JPEG_CHROMA_SUBSAMPLING_420 = 2,
+ V4L2_JPEG_CHROMA_SUBSAMPLING_411 = 3,
+ V4L2_JPEG_CHROMA_SUBSAMPLING_410 = 4,
+ V4L2_JPEG_CHROMA_SUBSAMPLING_GRAY = 5,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+#define V4L2_CID_JPEG_RESTART_INTERVAL (V4L2_CID_JPEG_CLASS_BASE + 2)
+#define V4L2_CID_JPEG_COMPRESSION_QUALITY (V4L2_CID_JPEG_CLASS_BASE + 3)
+#define V4L2_CID_JPEG_ACTIVE_MARKER (V4L2_CID_JPEG_CLASS_BASE + 4)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_JPEG_ACTIVE_MARKER_APP0 (1 << 0)
+#define V4L2_JPEG_ACTIVE_MARKER_APP1 (1 << 1)
+#define V4L2_JPEG_ACTIVE_MARKER_COM (1 << 16)
+#define V4L2_JPEG_ACTIVE_MARKER_DQT (1 << 17)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_JPEG_ACTIVE_MARKER_DHT (1 << 18)
 struct v4l2_tuner {
  __u32 index;
  __u8 name[32];
- enum v4l2_tuner_type type;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ enum v4l2_tuner_type type;
  __u32 capability;
  __u32 rangelow;
  __u32 rangehigh;
- __u32 rxsubchans;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 rxsubchans;
  __u32 audmode;
  __s32 signal;
  __s32 afc;
- __u32 reserved[4];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 reserved[4];
 };
 struct v4l2_modulator {
  __u32 index;
- __u8 name[32];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u8 name[32];
  __u32 capability;
  __u32 rangelow;
  __u32 rangehigh;
- __u32 txsubchans;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 txsubchans;
  __u32 reserved[4];
 };
 #define V4L2_TUNER_CAP_LOW 0x0001
-#define V4L2_TUNER_CAP_NORM 0x0002
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_TUNER_CAP_NORM 0x0002
 #define V4L2_TUNER_CAP_STEREO 0x0010
 #define V4L2_TUNER_CAP_LANG2 0x0020
 #define V4L2_TUNER_CAP_SAP 0x0020
-#define V4L2_TUNER_CAP_LANG1 0x0040
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_TUNER_CAP_LANG1 0x0040
 #define V4L2_TUNER_CAP_RDS 0x0080
 #define V4L2_TUNER_CAP_RDS_BLOCK_IO 0x0100
 #define V4L2_TUNER_CAP_RDS_CONTROLS 0x0200
-#define V4L2_TUNER_SUB_MONO 0x0001
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_TUNER_SUB_MONO 0x0001
 #define V4L2_TUNER_SUB_STEREO 0x0002
 #define V4L2_TUNER_SUB_LANG2 0x0004
 #define V4L2_TUNER_SUB_SAP 0x0004
-#define V4L2_TUNER_SUB_LANG1 0x0008
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_TUNER_SUB_LANG1 0x0008
 #define V4L2_TUNER_SUB_RDS 0x0010
 #define V4L2_TUNER_MODE_MONO 0x0000
 #define V4L2_TUNER_MODE_STEREO 0x0001
-#define V4L2_TUNER_MODE_LANG2 0x0002
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_TUNER_MODE_LANG2 0x0002
 #define V4L2_TUNER_MODE_SAP 0x0002
 #define V4L2_TUNER_MODE_LANG1 0x0003
 #define V4L2_TUNER_MODE_LANG1_LANG2 0x0004
-struct v4l2_frequency {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct v4l2_frequency {
  __u32 tuner;
  enum v4l2_tuner_type type;
  __u32 frequency;
- __u32 reserved[8];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 reserved[8];
 };
 struct v4l2_hw_freq_seek {
  __u32 tuner;
- enum v4l2_tuner_type type;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ enum v4l2_tuner_type type;
  __u32 seek_upward;
  __u32 wrap_around;
  __u32 spacing;
- __u32 reserved[7];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 reserved[7];
 };
 struct v4l2_rds_data {
  __u8 lsb;
- __u8 msb;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u8 msb;
  __u8 block;
 } __attribute__ ((packed));
 #define V4L2_RDS_BLOCK_MSK 0x7
-#define V4L2_RDS_BLOCK_A 0
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_RDS_BLOCK_A 0
 #define V4L2_RDS_BLOCK_B 1
 #define V4L2_RDS_BLOCK_C 2
 #define V4L2_RDS_BLOCK_D 3
-#define V4L2_RDS_BLOCK_C_ALT 4
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_RDS_BLOCK_C_ALT 4
 #define V4L2_RDS_BLOCK_INVALID 7
 #define V4L2_RDS_BLOCK_CORRECTED 0x40
 #define V4L2_RDS_BLOCK_ERROR 0x80
-struct v4l2_audio {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct v4l2_audio {
  __u32 index;
  __u8 name[32];
  __u32 capability;
- __u32 mode;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 mode;
  __u32 reserved[2];
 };
 #define V4L2_AUDCAP_STEREO 0x00001
-#define V4L2_AUDCAP_AVL 0x00002
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_AUDCAP_AVL 0x00002
 #define V4L2_AUDMODE_AVL 0x00001
 struct v4l2_audioout {
  __u32 index;
- __u8 name[32];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u8 name[32];
  __u32 capability;
  __u32 mode;
  __u32 reserved[2];
-};
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
 #define V4L2_ENC_IDX_FRAME_I (0)
 #define V4L2_ENC_IDX_FRAME_P (1)
 #define V4L2_ENC_IDX_FRAME_B (2)
-#define V4L2_ENC_IDX_FRAME_MASK (0xf)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_ENC_IDX_FRAME_MASK (0xf)
 struct v4l2_enc_idx_entry {
  __u64 offset;
  __u64 pts;
- __u32 length;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 length;
  __u32 flags;
  __u32 reserved[2];
 };
-#define V4L2_ENC_IDX_ENTRIES (64)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_ENC_IDX_ENTRIES (64)
 struct v4l2_enc_idx {
  __u32 entries;
  __u32 entries_cap;
- __u32 reserved[4];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 reserved[4];
  struct v4l2_enc_idx_entry entry[V4L2_ENC_IDX_ENTRIES];
 };
 #define V4L2_ENC_CMD_START (0)
-#define V4L2_ENC_CMD_STOP (1)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_ENC_CMD_STOP (1)
 #define V4L2_ENC_CMD_PAUSE (2)
 #define V4L2_ENC_CMD_RESUME (3)
 #define V4L2_ENC_CMD_STOP_AT_GOP_END (1 << 0)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_encoder_cmd {
+ __u32 cmd;
+ __u32 flags;
+ union {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ struct {
+ __u32 data[8];
+ } raw;
+ };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+#define V4L2_DEC_CMD_START (0)
+#define V4L2_DEC_CMD_STOP (1)
+#define V4L2_DEC_CMD_PAUSE (2)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_DEC_CMD_RESUME (3)
+#define V4L2_DEC_CMD_START_MUTE_AUDIO (1 << 0)
+#define V4L2_DEC_CMD_PAUSE_TO_BLACK (1 << 0)
+#define V4L2_DEC_CMD_STOP_TO_BLACK (1 << 0)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_DEC_CMD_STOP_IMMEDIATELY (1 << 1)
+#define V4L2_DEC_START_FMT_NONE (0)
+#define V4L2_DEC_START_FMT_GOP (1)
+struct v4l2_decoder_cmd {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 cmd;
  __u32 flags;
  union {
  struct {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 data[8];
+ __u64 pts;
+ } stop;
+ struct {
+ __s32 speed;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ __u32 format;
+ } start;
+ struct {
+ __u32 data[16];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  } raw;
  };
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_vbi_format {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 sampling_rate;
  __u32 offset;
  __u32 samples_per_line;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 sample_format;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __s32 start[2];
  __u32 count[2];
  __u32 flags;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 reserved[2];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define V4L2_VBI_UNSYNC (1 << 0)
 #define V4L2_VBI_INTERLACED (1 << 1)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_sliced_vbi_format {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u16 service_set;
  __u16 service_lines[2][24];
  __u32 io_size;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 reserved[2];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define V4L2_SLICED_TELETEXT_B (0x0001)
 #define V4L2_SLICED_VPS (0x0400)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_SLICED_CAPTION_525 (0x1000)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_SLICED_WSS_625 (0x4000)
 #define V4L2_SLICED_VBI_525 (V4L2_SLICED_CAPTION_525)
 #define V4L2_SLICED_VBI_625 (V4L2_SLICED_TELETEXT_B | V4L2_SLICED_VPS | V4L2_SLICED_WSS_625)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_sliced_vbi_cap {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u16 service_set;
  __u16 service_lines[2][24];
  enum v4l2_buf_type type;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 reserved[3];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct v4l2_sliced_vbi_data {
  __u32 id;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 field;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 line;
  __u32 reserved;
  __u8 data[48];
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_MPEG_VBI_IVTV_TELETEXT_B (1)
 #define V4L2_MPEG_VBI_IVTV_CAPTION_525 (4)
 #define V4L2_MPEG_VBI_IVTV_WSS_625 (5)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_MPEG_VBI_IVTV_VPS (7)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_mpeg_vbi_itv0_line {
  __u8 id;
  __u8 data[42];
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } __attribute__ ((packed));
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_mpeg_vbi_itv0 {
  __le32 linemask[2];
  struct v4l2_mpeg_vbi_itv0_line line[35];
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } __attribute__ ((packed));
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_mpeg_vbi_ITV0 {
  struct v4l2_mpeg_vbi_itv0_line line[36];
 } __attribute__ ((packed));
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_MPEG_VBI_IVTV_MAGIC0 "itv0"
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_MPEG_VBI_IVTV_MAGIC1 "ITV0"
 struct v4l2_mpeg_vbi_fmt_ivtv {
  __u8 magic[4];
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  union {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  struct v4l2_mpeg_vbi_itv0 itv0;
  struct v4l2_mpeg_vbi_ITV0 ITV0;
  };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } __attribute__ ((packed));
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_plane_pix_format {
  __u32 sizeimage;
  __u16 bytesperline;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u16 reserved[7];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } __attribute__ ((packed));
 struct v4l2_pix_format_mplane {
  __u32 width;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 height;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 pixelformat;
  enum v4l2_field field;
  enum v4l2_colorspace colorspace;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  struct v4l2_plane_pix_format plane_fmt[VIDEO_MAX_PLANES];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u8 num_planes;
  __u8 reserved[11];
 } __attribute__ ((packed));
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_format {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  enum v4l2_buf_type type;
  union {
  struct v4l2_pix_format pix;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  struct v4l2_pix_format_mplane pix_mp;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  struct v4l2_window win;
  struct v4l2_vbi_format vbi;
  struct v4l2_sliced_vbi_format sliced;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u8 raw_data[200];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  } fmt;
 };
 struct v4l2_streamparm {
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  enum v4l2_buf_type type;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  union {
  struct v4l2_captureparm capture;
  struct v4l2_outputparm output;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u8 raw_data[200];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  } parm;
 };
 #define V4L2_EVENT_ALL 0
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_EVENT_VSYNC 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_EVENT_EOS 2
 #define V4L2_EVENT_CTRL 3
 #define V4L2_EVENT_FRAME_SYNC 4
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_EVENT_PRIVATE_START 0x08000000
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define V4L2_EVENT_MSM_VIDC_START (V4L2_EVENT_PRIVATE_START + 0x00001000)
+#define V4L2_EVENT_MSM_VIDC_FLUSH_DONE (V4L2_EVENT_PRIVATE_START + 1)
+#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_CHANGED   (V4L2_EVENT_PRIVATE_START + 2)
+#define V4L2_EVENT_MSM_VIDC_CLOSE_DONE (V4L2_EVENT_PRIVATE_START + 3)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_event_vsync {
  __u8 field;
 } __attribute__ ((packed));
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_EVENT_CTRL_CH_VALUE (1 << 0)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_EVENT_CTRL_CH_FLAGS (1 << 1)
 struct v4l2_event_ctrl {
  __u32 changes;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 type;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  union {
  __s32 value;
  __s64 value64;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 flags;
  __s32 minimum;
  __s32 maximum;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __s32 step;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __s32 default_value;
 };
 struct v4l2_event_frame_sync {
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 frame_sequence;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct v4l2_event {
  __u32 type;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  union {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  struct v4l2_event_vsync vsync;
  struct v4l2_event_ctrl ctrl;
  struct v4l2_event_frame_sync frame_sync;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u8 data[64];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  } u;
  __u32 pending;
  __u32 sequence;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  struct timespec timestamp;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 id;
  __u32 reserved[8];
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_EVENT_SUB_FL_SEND_INITIAL (1 << 0)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_EVENT_SUB_FL_ALLOW_FEEDBACK (1 << 1)
 struct v4l2_event_subscription {
  __u32 type;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 id;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 flags;
  __u32 reserved[5];
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CHIP_MATCH_HOST 0  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define V4L2_CHIP_MATCH_I2C_DRIVER 1  
 #define V4L2_CHIP_MATCH_I2C_ADDR 2  
 #define V4L2_CHIP_MATCH_AC97 3  
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_dbg_match {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 type;
  union {
  __u32 addr;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  char name[32];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  };
 } __attribute__ ((packed));
 struct v4l2_dbg_register {
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  struct v4l2_dbg_match match;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 size;
  __u64 reg;
  __u64 val;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } __attribute__ ((packed));
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct v4l2_dbg_chip_ident {
  struct v4l2_dbg_match match;
  __u32 ident;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 revision;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } __attribute__ ((packed));
 struct v4l2_create_buffers {
  __u32 index;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  __u32 count;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  enum v4l2_memory memory;
  struct v4l2_format format;
  __u32 reserved[8];
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_QUERYCAP _IOR('V', 0, struct v4l2_capability)
 #define VIDIOC_RESERVED _IO('V', 1)
 #define VIDIOC_ENUM_FMT _IOWR('V', 2, struct v4l2_fmtdesc)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_G_FMT _IOWR('V', 4, struct v4l2_format)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_S_FMT _IOWR('V', 5, struct v4l2_format)
 #define VIDIOC_REQBUFS _IOWR('V', 8, struct v4l2_requestbuffers)
 #define VIDIOC_QUERYBUF _IOWR('V', 9, struct v4l2_buffer)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_G_FBUF _IOR('V', 10, struct v4l2_framebuffer)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_S_FBUF _IOW('V', 11, struct v4l2_framebuffer)
 #define VIDIOC_OVERLAY _IOW('V', 14, int)
 #define VIDIOC_QBUF _IOWR('V', 15, struct v4l2_buffer)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_DQBUF _IOWR('V', 17, struct v4l2_buffer)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_STREAMON _IOW('V', 18, int)
 #define VIDIOC_STREAMOFF _IOW('V', 19, int)
 #define VIDIOC_G_PARM _IOWR('V', 21, struct v4l2_streamparm)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_S_PARM _IOWR('V', 22, struct v4l2_streamparm)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_G_STD _IOR('V', 23, v4l2_std_id)
 #define VIDIOC_S_STD _IOW('V', 24, v4l2_std_id)
 #define VIDIOC_ENUMSTD _IOWR('V', 25, struct v4l2_standard)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_ENUMINPUT _IOWR('V', 26, struct v4l2_input)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_G_CTRL _IOWR('V', 27, struct v4l2_control)
 #define VIDIOC_S_CTRL _IOWR('V', 28, struct v4l2_control)
 #define VIDIOC_G_TUNER _IOWR('V', 29, struct v4l2_tuner)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_S_TUNER _IOW('V', 30, struct v4l2_tuner)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_G_AUDIO _IOR('V', 33, struct v4l2_audio)
 #define VIDIOC_S_AUDIO _IOW('V', 34, struct v4l2_audio)
 #define VIDIOC_QUERYCTRL _IOWR('V', 36, struct v4l2_queryctrl)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_QUERYMENU _IOWR('V', 37, struct v4l2_querymenu)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_G_INPUT _IOR('V', 38, int)
 #define VIDIOC_S_INPUT _IOWR('V', 39, int)
 #define VIDIOC_G_OUTPUT _IOR('V', 46, int)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_S_OUTPUT _IOWR('V', 47, int)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_ENUMOUTPUT _IOWR('V', 48, struct v4l2_output)
 #define VIDIOC_G_AUDOUT _IOR('V', 49, struct v4l2_audioout)
 #define VIDIOC_S_AUDOUT _IOW('V', 50, struct v4l2_audioout)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_G_MODULATOR _IOWR('V', 54, struct v4l2_modulator)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_S_MODULATOR _IOW('V', 55, struct v4l2_modulator)
 #define VIDIOC_G_FREQUENCY _IOWR('V', 56, struct v4l2_frequency)
 #define VIDIOC_S_FREQUENCY _IOW('V', 57, struct v4l2_frequency)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_CROPCAP _IOWR('V', 58, struct v4l2_cropcap)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_G_CROP _IOWR('V', 59, struct v4l2_crop)
 #define VIDIOC_S_CROP _IOW('V', 60, struct v4l2_crop)
 #define VIDIOC_G_JPEGCOMP _IOR('V', 61, struct v4l2_jpegcompression)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_S_JPEGCOMP _IOW('V', 62, struct v4l2_jpegcompression)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_QUERYSTD _IOR('V', 63, v4l2_std_id)
 #define VIDIOC_TRY_FMT _IOWR('V', 64, struct v4l2_format)
 #define VIDIOC_ENUMAUDIO _IOWR('V', 65, struct v4l2_audio)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_ENUMAUDOUT _IOWR('V', 66, struct v4l2_audioout)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_G_PRIORITY _IOR('V', 67, enum v4l2_priority)
 #define VIDIOC_S_PRIORITY _IOW('V', 68, enum v4l2_priority)
 #define VIDIOC_G_SLICED_VBI_CAP _IOWR('V', 69, struct v4l2_sliced_vbi_cap)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_LOG_STATUS _IO('V', 70)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_G_EXT_CTRLS _IOWR('V', 71, struct v4l2_ext_controls)
 #define VIDIOC_S_EXT_CTRLS _IOWR('V', 72, struct v4l2_ext_controls)
 #define VIDIOC_TRY_EXT_CTRLS _IOWR('V', 73, struct v4l2_ext_controls)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_ENUM_FRAMESIZES _IOWR('V', 74, struct v4l2_frmsizeenum)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_ENUM_FRAMEINTERVALS _IOWR('V', 75, struct v4l2_frmivalenum)
 #define VIDIOC_G_ENC_INDEX _IOR('V', 76, struct v4l2_enc_idx)
 #define VIDIOC_ENCODER_CMD _IOWR('V', 77, struct v4l2_encoder_cmd)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_TRY_ENCODER_CMD _IOWR('V', 78, struct v4l2_encoder_cmd)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_DBG_S_REGISTER _IOW('V', 79, struct v4l2_dbg_register)
 #define VIDIOC_DBG_G_REGISTER _IOWR('V', 80, struct v4l2_dbg_register)
 #define VIDIOC_DBG_G_CHIP_IDENT _IOWR('V', 81, struct v4l2_dbg_chip_ident)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_S_HW_FREQ_SEEK _IOW('V', 82, struct v4l2_hw_freq_seek)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_ENUM_DV_PRESETS _IOWR('V', 83, struct v4l2_dv_enum_preset)
 #define VIDIOC_S_DV_PRESET _IOWR('V', 84, struct v4l2_dv_preset)
 #define VIDIOC_G_DV_PRESET _IOWR('V', 85, struct v4l2_dv_preset)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_QUERY_DV_PRESET _IOR('V', 86, struct v4l2_dv_preset)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_S_DV_TIMINGS _IOWR('V', 87, struct v4l2_dv_timings)
 #define VIDIOC_G_DV_TIMINGS _IOWR('V', 88, struct v4l2_dv_timings)
 #define VIDIOC_DQEVENT _IOR('V', 89, struct v4l2_event)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_SUBSCRIBE_EVENT _IOW('V', 90, struct v4l2_event_subscription)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_UNSUBSCRIBE_EVENT _IOW('V', 91, struct v4l2_event_subscription)
 #define VIDIOC_CREATE_BUFS _IOWR('V', 92, struct v4l2_create_buffers)
 #define VIDIOC_PREPARE_BUF _IOWR('V', 93, struct v4l2_buffer)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIDIOC_G_SELECTION _IOWR('V', 94, struct v4l2_selection)
-#define VIDIOC_S_SELECTION _IOWR('V', 95, struct v4l2_selection)
-#define BASE_VIDIOC_PRIVATE 192  
-#endif
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define VIDIOC_S_SELECTION _IOWR('V', 95, struct v4l2_selection)
+#define VIDIOC_DECODER_CMD _IOWR('V', 96, struct v4l2_decoder_cmd)
+#define VIDIOC_TRY_DECODER_CMD _IOWR('V', 97, struct v4l2_decoder_cmd)
+#define BASE_VIDIOC_PRIVATE 192  
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#endif
 
diff --git a/libc/kernel/common/media/msm_camera.h b/libc/kernel/common/media/msm_camera.h
index e2bd930..623f8f9 100644
--- a/libc/kernel/common/media/msm_camera.h
+++ b/libc/kernel/common/media/msm_camera.h
@@ -18,153 +18,383 @@
  ****************************************************************************/
 #ifndef __LINUX_MSM_CAMERA_H
 #define __LINUX_MSM_CAMERA_H
-#include <linux/types.h>
-#include <asm/sizes.h>
+#ifdef MSM_CAMERA_BIONIC
+#include <sys/types.h>
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#endif
+#include <linux/types.h>
 #include <linux/ioctl.h>
+#ifdef MSM_CAMERA_GCC
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#include <time.h>
+#else
+#include <linux/time.h>
+#endif
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#include <linux/ion.h>
+#define BIT(nr) (1UL << (nr))
 #define MSM_CAM_IOCTL_MAGIC 'm'
 #define MSM_CAM_IOCTL_GET_SENSOR_INFO   _IOR(MSM_CAM_IOCTL_MAGIC, 1, struct msm_camsensor_info *)
-#define MSM_CAM_IOCTL_REGISTER_PMEM   _IOW(MSM_CAM_IOCTL_MAGIC, 2, struct msm_pmem_info *)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSM_CAM_IOCTL_REGISTER_PMEM   _IOW(MSM_CAM_IOCTL_MAGIC, 2, struct msm_pmem_info *)
 #define MSM_CAM_IOCTL_UNREGISTER_PMEM   _IOW(MSM_CAM_IOCTL_MAGIC, 3, unsigned)
 #define MSM_CAM_IOCTL_CTRL_COMMAND   _IOW(MSM_CAM_IOCTL_MAGIC, 4, struct msm_ctrl_cmd *)
 #define MSM_CAM_IOCTL_CONFIG_VFE   _IOW(MSM_CAM_IOCTL_MAGIC, 5, struct msm_camera_vfe_cfg_cmd *)
-#define MSM_CAM_IOCTL_GET_STATS   _IOR(MSM_CAM_IOCTL_MAGIC, 6, struct msm_camera_stats_event_ctrl *)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSM_CAM_IOCTL_GET_STATS   _IOR(MSM_CAM_IOCTL_MAGIC, 6, struct msm_camera_stats_event_ctrl *)
 #define MSM_CAM_IOCTL_GETFRAME   _IOR(MSM_CAM_IOCTL_MAGIC, 7, struct msm_camera_get_frame *)
 #define MSM_CAM_IOCTL_ENABLE_VFE   _IOW(MSM_CAM_IOCTL_MAGIC, 8, struct camera_enable_cmd *)
 #define MSM_CAM_IOCTL_CTRL_CMD_DONE   _IOW(MSM_CAM_IOCTL_MAGIC, 9, struct camera_cmd *)
-#define MSM_CAM_IOCTL_CONFIG_CMD   _IOW(MSM_CAM_IOCTL_MAGIC, 10, struct camera_cmd *)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSM_CAM_IOCTL_CONFIG_CMD   _IOW(MSM_CAM_IOCTL_MAGIC, 10, struct camera_cmd *)
 #define MSM_CAM_IOCTL_DISABLE_VFE   _IOW(MSM_CAM_IOCTL_MAGIC, 11, struct camera_enable_cmd *)
 #define MSM_CAM_IOCTL_PAD_REG_RESET2   _IOW(MSM_CAM_IOCTL_MAGIC, 12, struct camera_enable_cmd *)
 #define MSM_CAM_IOCTL_VFE_APPS_RESET   _IOW(MSM_CAM_IOCTL_MAGIC, 13, struct camera_enable_cmd *)
-#define MSM_CAM_IOCTL_RELEASE_FRAME_BUFFER   _IOW(MSM_CAM_IOCTL_MAGIC, 14, struct camera_enable_cmd *)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSM_CAM_IOCTL_RELEASE_FRAME_BUFFER   _IOW(MSM_CAM_IOCTL_MAGIC, 14, struct camera_enable_cmd *)
 #define MSM_CAM_IOCTL_RELEASE_STATS_BUFFER   _IOW(MSM_CAM_IOCTL_MAGIC, 15, struct msm_stats_buf *)
 #define MSM_CAM_IOCTL_AXI_CONFIG   _IOW(MSM_CAM_IOCTL_MAGIC, 16, struct msm_camera_vfe_cfg_cmd *)
-#define MSM_CAM_IOCTL_GET_PICTURE   _IOW(MSM_CAM_IOCTL_MAGIC, 17, struct msm_camera_ctrl_cmd *)
+#define MSM_CAM_IOCTL_GET_PICTURE   _IOW(MSM_CAM_IOCTL_MAGIC, 17, struct msm_frame *)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define MSM_CAM_IOCTL_SET_CROP   _IOW(MSM_CAM_IOCTL_MAGIC, 18, struct crop_info *)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MSM_CAM_IOCTL_PP   _IOW(MSM_CAM_IOCTL_MAGIC, 19, uint8_t *)
-#define MSM_CAM_IOCTL_PP_DONE   _IOW(MSM_CAM_IOCTL_MAGIC, 20, struct msm_snapshot_pp_status *)
+#define MSM_CAM_IOCTL_PICT_PP   _IOW(MSM_CAM_IOCTL_MAGIC, 19, uint8_t *)
+#define MSM_CAM_IOCTL_PICT_PP_DONE   _IOW(MSM_CAM_IOCTL_MAGIC, 20, struct msm_snapshot_pp_status *)
 #define MSM_CAM_IOCTL_SENSOR_IO_CFG   _IOW(MSM_CAM_IOCTL_MAGIC, 21, struct sensor_cfg_data *)
-#define MSM_CAMERA_LED_OFF 0
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MSM_CAMERA_LED_LOW 1
-#define MSM_CAMERA_LED_HIGH 2
 #define MSM_CAM_IOCTL_FLASH_LED_CFG   _IOW(MSM_CAM_IOCTL_MAGIC, 22, unsigned *)
 #define MSM_CAM_IOCTL_UNBLOCK_POLL_FRAME   _IO(MSM_CAM_IOCTL_MAGIC, 23)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define MSM_CAM_IOCTL_CTRL_COMMAND_2   _IOW(MSM_CAM_IOCTL_MAGIC, 24, struct msm_ctrl_cmd *)
-#define MSM_CAM_IOCTL_ENABLE_OUTPUT_IND   _IOW(MSM_CAM_IOCTL_MAGIC, 25, uint32_t *)
-#define MSM_CAM_IOCTL_AF_CTRL   _IOR(MSM_CAM_IOCTL_MAGIC, 26, struct msm_ctrl_cmt_t *)
-#define MSM_CAM_IOCTL_AF_CTRL_DONE   _IOW(MSM_CAM_IOCTL_MAGIC, 27, struct msm_ctrl_cmt_t *)
+#define MSM_CAM_IOCTL_AF_CTRL   _IOR(MSM_CAM_IOCTL_MAGIC, 25, struct msm_ctrl_cmt_t *)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MAX_SENSOR_NUM 3
+#define MSM_CAM_IOCTL_AF_CTRL_DONE   _IOW(MSM_CAM_IOCTL_MAGIC, 26, struct msm_ctrl_cmt_t *)
+#define MSM_CAM_IOCTL_CONFIG_VPE   _IOW(MSM_CAM_IOCTL_MAGIC, 27, struct msm_camera_vpe_cfg_cmd *)
+#define MSM_CAM_IOCTL_AXI_VPE_CONFIG   _IOW(MSM_CAM_IOCTL_MAGIC, 28, struct msm_camera_vpe_cfg_cmd *)
+#define MSM_CAM_IOCTL_STROBE_FLASH_CFG   _IOW(MSM_CAM_IOCTL_MAGIC, 29, uint32_t *)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSM_CAM_IOCTL_STROBE_FLASH_CHARGE   _IOW(MSM_CAM_IOCTL_MAGIC, 30, uint32_t *)
+#define MSM_CAM_IOCTL_STROBE_FLASH_RELEASE   _IO(MSM_CAM_IOCTL_MAGIC, 31)
+#define MSM_CAM_IOCTL_FLASH_CTRL   _IOW(MSM_CAM_IOCTL_MAGIC, 32, struct flash_ctrl_data *)
+#define MSM_CAM_IOCTL_ERROR_CONFIG   _IOW(MSM_CAM_IOCTL_MAGIC, 33, uint32_t *)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSM_CAM_IOCTL_ABORT_CAPTURE   _IO(MSM_CAM_IOCTL_MAGIC, 34)
+#define MSM_CAM_IOCTL_SET_FD_ROI   _IOW(MSM_CAM_IOCTL_MAGIC, 35, struct fd_roi_info *)
+#define MSM_CAM_IOCTL_GET_CAMERA_INFO   _IOR(MSM_CAM_IOCTL_MAGIC, 36, struct msm_camera_info *)
+#define MSM_CAM_IOCTL_UNBLOCK_POLL_PIC_FRAME   _IO(MSM_CAM_IOCTL_MAGIC, 37)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSM_CAM_IOCTL_RELEASE_PIC_BUFFER   _IOW(MSM_CAM_IOCTL_MAGIC, 38, struct camera_enable_cmd *)
+#define MSM_CAM_IOCTL_PUT_ST_FRAME   _IOW(MSM_CAM_IOCTL_MAGIC, 39, struct msm_camera_st_frame *)
+#define MSM_CAM_IOCTL_V4L2_EVT_NOTIFY   _IOR(MSM_CAM_IOCTL_MAGIC, 40, struct v4l2_event *)
+#define MSM_CAM_IOCTL_SET_MEM_MAP_INFO   _IOR(MSM_CAM_IOCTL_MAGIC, 41, struct msm_mem_map_info *)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSM_CAM_IOCTL_ACTUATOR_IO_CFG   _IOW(MSM_CAM_IOCTL_MAGIC, 42, struct msm_actuator_cfg_data *)
+#define MSM_CAM_IOCTL_MCTL_POST_PROC   _IOW(MSM_CAM_IOCTL_MAGIC, 43, struct msm_mctl_post_proc_cmd *)
+#define MSM_CAM_IOCTL_RESERVE_FREE_FRAME   _IOW(MSM_CAM_IOCTL_MAGIC, 44, struct msm_cam_evt_divert_frame *)
+#define MSM_CAM_IOCTL_RELEASE_FREE_FRAME   _IOR(MSM_CAM_IOCTL_MAGIC, 45, struct msm_cam_evt_divert_frame *)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSM_CAM_IOCTL_PICT_PP_DIVERT_DONE   _IOR(MSM_CAM_IOCTL_MAGIC, 46, struct msm_pp_frame *)
+#define MSM_CAM_IOCTL_SENSOR_V4l2_S_CTRL   _IOR(MSM_CAM_IOCTL_MAGIC, 47, struct v4l2_control)
+#define MSM_CAM_IOCTL_SENSOR_V4l2_QUERY_CTRL   _IOR(MSM_CAM_IOCTL_MAGIC, 48, struct v4l2_queryctrl)
+#define MSM_CAM_IOCTL_GET_KERNEL_SYSTEM_TIME   _IOW(MSM_CAM_IOCTL_MAGIC, 49, struct timeval *)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSM_CAM_IOCTL_SET_VFE_OUTPUT_TYPE   _IOW(MSM_CAM_IOCTL_MAGIC, 50, uint32_t *)
+#define MSM_CAM_IOCTL_MCTL_DIVERT_DONE   _IOR(MSM_CAM_IOCTL_MAGIC, 51, struct msm_cam_evt_divert_frame *)
+#define MSM_CAM_IOCTL_GET_ACTUATOR_INFO   _IOW(MSM_CAM_IOCTL_MAGIC, 52, struct msm_actuator_cfg_data *)
+#define MSM_CAM_IOCTL_EEPROM_IO_CFG   _IOW(MSM_CAM_IOCTL_MAGIC, 53, struct msm_eeprom_cfg_data *)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSM_CAM_IOCTL_ISPIF_IO_CFG   _IOR(MSM_CAM_IOCTL_MAGIC, 54, struct ispif_cfg_data *)
+#define MSM_CAM_IOCTL_STATS_REQBUF   _IOR(MSM_CAM_IOCTL_MAGIC, 55, struct msm_stats_reqbuf *)
+#define MSM_CAM_IOCTL_STATS_ENQUEUEBUF   _IOR(MSM_CAM_IOCTL_MAGIC, 56, struct msm_stats_buf_info *)
+#define MSM_CAM_IOCTL_STATS_FLUSH_BUFQ   _IOR(MSM_CAM_IOCTL_MAGIC, 57, struct msm_stats_flush_bufq *)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSM_CAM_IOCTL_SET_MCTL_SDEV   _IOW(MSM_CAM_IOCTL_MAGIC, 58, struct msm_mctl_set_sdev_data *)
+#define MSM_CAM_IOCTL_UNSET_MCTL_SDEV   _IOW(MSM_CAM_IOCTL_MAGIC, 59, struct msm_mctl_set_sdev_data *)
+#define MSM_CAM_IOCTL_GET_INST_HANDLE   _IOR(MSM_CAM_IOCTL_MAGIC, 60, uint32_t *)
+#define MSM_CAM_IOCTL_STATS_UNREG_BUF   _IOR(MSM_CAM_IOCTL_MAGIC, 61, struct msm_stats_flush_bufq *)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct msm_stats_reqbuf {
+ int num_buf;
+ int stats_type;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct msm_stats_flush_bufq {
+ int stats_type;
+};
+struct msm_mctl_pp_cmd {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ int32_t id;
+ uint16_t length;
+ void *value;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct msm_mctl_post_proc_cmd {
+ int32_t type;
+ struct msm_mctl_pp_cmd cmd;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSM_CAMERA_LED_OFF 0
+#define MSM_CAMERA_LED_LOW 1
+#define MSM_CAMERA_LED_HIGH 2
+#define MSM_CAMERA_LED_INIT 3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSM_CAMERA_LED_RELEASE 4
+#define MSM_CAMERA_STROBE_FLASH_NONE 0
+#define MSM_CAMERA_STROBE_FLASH_XENON 1
+#define MSM_MAX_CAMERA_SENSORS 5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define MAX_SENSOR_NAME 32
-#define PP_SNAP 1
-#define PP_RAW_SNAP (1<<1)
+#define MAX_CAM_NAME_SIZE 32
+#define MAX_ACT_MOD_NAME_SIZE 32
+#define MAX_ACT_NAME_SIZE 32
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PP_PREV (1<<2)
-#define PP_MASK (PP_SNAP|PP_RAW_SNAP|PP_PREV)
+#define NUM_ACTUATOR_DIR 2
+#define MAX_ACTUATOR_SCENARIO 8
+#define MAX_ACTUATOR_REGION 5
+#define MAX_ACTUATOR_INIT_SET 12
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MAX_ACTUATOR_TYPE_SIZE 32
+#define MAX_ACTUATOR_REG_TBL_SIZE 8
+#define MSM_MAX_CAMERA_CONFIGS 2
+#define PP_SNAP 0x01
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define PP_RAW_SNAP ((0x01)<<1)
+#define PP_PREV ((0x01)<<2)
+#define PP_THUMB ((0x01)<<3)
+#define PP_MASK (PP_SNAP|PP_RAW_SNAP|PP_PREV|PP_THUMB)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define MSM_CAM_CTRL_CMD_DONE 0
 #define MSM_CAM_SENSOR_VFE_CMD 1
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MAX_PLANES 8
 struct msm_ctrl_cmd {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  uint16_t type;
  uint16_t length;
  void *value;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  uint16_t status;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  uint32_t timeout_ms;
  int resp_fd;
+ int vnode_id;
+ int queue_idx;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t evt_id;
+ uint32_t stream_type;
+ int config_ident;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-struct msm_vfe_evt_msg {
+struct msm_cam_evt_msg {
  unsigned short type;
  unsigned short msg_id;
  unsigned int len;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t frame_id;
  void *data;
+ struct timespec timestamp;
 };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct msm_pp_frame_sp {
+ unsigned long phy_addr;
+ uint32_t y_off;
+ uint32_t cbcr_off;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t length;
+ int32_t fd;
+ uint32_t addr_offset;
+ unsigned long vaddr;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+struct msm_pp_frame_mp {
+ unsigned long phy_addr;
+ uint32_t data_offset;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t length;
+ int32_t fd;
+ uint32_t addr_offset;
+ unsigned long vaddr;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+struct msm_pp_frame {
+ uint32_t handle;
+ uint32_t frame_id;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned short buf_idx;
+ int path;
+ unsigned short image_type;
+ unsigned short num_planes;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ struct timeval timestamp;
+ union {
+ struct msm_pp_frame_sp sp;
+ struct msm_pp_frame_mp mp[MAX_PLANES];
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ };
+ int node_type;
+ uint32_t inst_handle;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct msm_cam_evt_divert_frame {
+ unsigned short image_mode;
+ unsigned short op_mode;
+ unsigned short inst_idx;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned short node_idx;
+ struct msm_pp_frame frame;
+ int do_pp;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct msm_mctl_pp_cmd_ack_event {
+ uint32_t cmd;
+ int status;
+ uint32_t cookie;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+struct msm_mctl_pp_event_info {
+ int32_t event;
+ union {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ struct msm_mctl_pp_cmd_ack_event ack;
+ };
+};
+struct msm_isp_event_ctrl {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned short resptype;
+ union {
+ struct msm_cam_evt_msg isp_msg;
+ struct msm_ctrl_cmd ctrl;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ struct msm_cam_evt_divert_frame div_frame;
+ struct msm_mctl_pp_event_info pp_event_info;
+ } isp_data;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define MSM_CAM_RESP_CTRL 0
 #define MSM_CAM_RESP_STAT_EVT_MSG 1
+#define MSM_CAM_RESP_STEREO_OP_1 2
+#define MSM_CAM_RESP_STEREO_OP_2 3
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MSM_CAM_RESP_V4L2 2
-#define MSM_CAM_RESP_MAX 3
+#define MSM_CAM_RESP_V4L2 4
+#define MSM_CAM_RESP_DIV_FRAME_EVT_MSG 5
+#define MSM_CAM_RESP_DONE_EVENT 6
+#define MSM_CAM_RESP_MCTL_PP_EVENT 7
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSM_CAM_RESP_MAX 8
+#define MSM_CAM_APP_NOTIFY_EVENT 0
+#define MSM_CAM_APP_NOTIFY_ERROR_EVENT 1
 struct msm_stats_event_ctrl {
- int resptype;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ int resptype;
  int timeout_ms;
  struct msm_ctrl_cmd ctrl_cmd;
- struct msm_vfe_evt_msg stats_event;
-};
+ struct msm_cam_evt_msg stats_event;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
 struct msm_camera_cfg_cmd {
  uint16_t cfg_type;
  uint16_t cmd_type;
- uint16_t queue;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint16_t queue;
  uint16_t length;
  void *value;
 };
-#define CMD_GENERAL 0
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define CMD_GENERAL 0
 #define CMD_AXI_CFG_OUT1 1
 #define CMD_AXI_CFG_SNAP_O1_AND_O2 2
 #define CMD_AXI_CFG_OUT2 3
-#define CMD_PICT_T_AXI_CFG 4
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define CMD_PICT_T_AXI_CFG 4
 #define CMD_PICT_M_AXI_CFG 5
 #define CMD_RAW_PICT_AXI_CFG 6
-#define CMD_STATS_AXI_CFG 7
-#define CMD_STATS_AF_AXI_CFG 8
+#define CMD_FRAME_BUF_RELEASE 7
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define CMD_FRAME_BUF_RELEASE 9
-#define CMD_PREV_BUF_CFG 10
-#define CMD_SNAP_BUF_RELEASE 11
-#define CMD_SNAP_BUF_CFG 12
+#define CMD_PREV_BUF_CFG 8
+#define CMD_SNAP_BUF_RELEASE 9
+#define CMD_SNAP_BUF_CFG 10
+#define CMD_STATS_DISABLE 11
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define CMD_STATS_DISABLE 13
-#define CMD_STATS_AEC_AWB_ENABLE 14
-#define CMD_STATS_AF_ENABLE 15
-#define CMD_STATS_BUF_RELEASE 16
+#define CMD_STATS_AEC_AWB_ENABLE 12
+#define CMD_STATS_AF_ENABLE 13
+#define CMD_STATS_AEC_ENABLE 14
+#define CMD_STATS_AWB_ENABLE 15
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define CMD_STATS_AF_BUF_RELEASE 17
-#define CMD_STATS_ENABLE 18
-#define UPDATE_STATS_INVALID 19
-#define CMD_STATS_AEC_ENABLE 20
+#define CMD_STATS_ENABLE 16
+#define CMD_STATS_AXI_CFG 17
+#define CMD_STATS_AEC_AXI_CFG 18
+#define CMD_STATS_AF_AXI_CFG 19
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define CMD_STATS_AWB_ENABLE 21
-#define CMD_STATS_AEC_AXI_CFG 22
-#define CMD_STATS_AWB_AXI_CFG 23
-#define CMD_STATS_RS_AXI_CFG 24
+#define CMD_STATS_AWB_AXI_CFG 20
+#define CMD_STATS_RS_AXI_CFG 21
+#define CMD_STATS_CS_AXI_CFG 22
+#define CMD_STATS_IHIST_AXI_CFG 23
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define CMD_STATS_CS_AXI_CFG 25
-#define CMD_STATS_IHIST_AXI_CFG 26
-#define CMD_STATS_SKIN_AXI_CFG 27
-#define CMD_STATS_AEC_BUF_RELEASE 28
+#define CMD_STATS_SKIN_AXI_CFG 24
+#define CMD_STATS_BUF_RELEASE 25
+#define CMD_STATS_AEC_BUF_RELEASE 26
+#define CMD_STATS_AF_BUF_RELEASE 27
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define CMD_STATS_AWB_BUF_RELEASE 29
-#define CMD_STATS_RS_BUF_RELEASE 30
-#define CMD_STATS_CS_BUF_RELEASE 31
-#define CMD_STATS_IHIST_BUF_RELEASE 32
+#define CMD_STATS_AWB_BUF_RELEASE 28
+#define CMD_STATS_RS_BUF_RELEASE 29
+#define CMD_STATS_CS_BUF_RELEASE 30
+#define CMD_STATS_IHIST_BUF_RELEASE 31
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define CMD_STATS_SKIN_BUF_RELEASE 33
+#define CMD_STATS_SKIN_BUF_RELEASE 32
+#define UPDATE_STATS_INVALID 33
 #define CMD_AXI_CFG_SNAP_GEMINI 34
 #define CMD_AXI_CFG_SNAP 35
-#define CMD_AXI_CFG_PREVIEW 36
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define CMD_AXI_CFG_PREVIEW 36
 #define CMD_AXI_CFG_VIDEO 37
 #define CMD_STATS_IHIST_ENABLE 38
 #define CMD_STATS_RS_ENABLE 39
-#define CMD_STATS_CS_ENABLE 40
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define CMD_AXI_CFG_O1_AND_O2 41  
+#define CMD_STATS_CS_ENABLE 40
+#define CMD_VPE 41
+#define CMD_AXI_CFG_VPE 42
+#define CMD_AXI_CFG_ZSL 43
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define CMD_AXI_CFG_SNAP_VPE 44
+#define CMD_AXI_CFG_SNAP_THUMB_VPE 45
+#define CMD_CONFIG_PING_ADDR 46
+#define CMD_CONFIG_PONG_ADDR 47
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define CMD_CONFIG_FREE_BUF_ADDR 48
+#define CMD_AXI_CFG_ZSL_ALL_CHNLS 49
+#define CMD_AXI_CFG_VIDEO_ALL_CHNLS 50
+#define CMD_VFE_BUFFER_RELEASE 51
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define CMD_VFE_PROCESS_IRQ 52
+#define CMD_STATS_BG_ENABLE 53
+#define CMD_STATS_BF_ENABLE 54
+#define CMD_STATS_BHIST_ENABLE 55
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define CMD_STATS_BG_BUF_RELEASE 56
+#define CMD_STATS_BF_BUF_RELEASE 57
+#define CMD_STATS_BHIST_BUF_RELEASE 58
+#define CMD_AXI_CFG_PRIM BIT(8)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define CMD_AXI_CFG_PRIM_ALL_CHNLS BIT(9)
+#define CMD_AXI_CFG_SEC BIT(10)
+#define CMD_AXI_CFG_SEC_ALL_CHNLS BIT(11)
+#define CMD_AXI_CFG_TERT1 BIT(12)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define CMD_AXI_CFG_TERT2 BIT(13)
+#define CMD_AXI_START 0xE1
+#define CMD_AXI_STOP 0xE2
+#define AXI_CMD_PREVIEW BIT(0)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define AXI_CMD_CAPTURE BIT(1)
+#define AXI_CMD_RECORD BIT(2)
+#define AXI_CMD_ZSL BIT(3)
+#define AXI_CMD_RAW_CAPTURE BIT(4)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct msm_vfe_cfg_cmd {
  int cmd_type;
  uint16_t length;
+ void *value;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+struct msm_vpe_cfg_cmd {
+ int cmd_type;
+ uint16_t length;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  void *value;
 };
@@ -193,172 +423,617 @@
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define MSM_PMEM_VIDEO 14
 #define MSM_PMEM_PREVIEW 15
-#define MSM_PMEM_MAX 16
-#define FRAME_PREVIEW_OUTPUT1 0
+#define MSM_PMEM_VIDEO_VPE 16
+#define MSM_PMEM_C2D 17
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSM_PMEM_MAINIMG_VPE 18
+#define MSM_PMEM_THUMBNAIL_VPE 19
+#define MSM_PMEM_BAYER_GRID 20
+#define MSM_PMEM_BAYER_FOCUS 21
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSM_PMEM_BAYER_HIST 22
+#define MSM_PMEM_MAX 23
+#define STAT_AEAW 0
+#define STAT_AEC 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define STAT_AF 2
+#define STAT_AWB 3
+#define STAT_RS 4
+#define STAT_CS 5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define STAT_IHIST 6
+#define STAT_SKIN 7
+#define STAT_BG 8
+#define STAT_BF 9
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define STAT_BHIST 10
+#define STAT_MAX 11
+#define FRAME_PREVIEW_OUTPUT1 0
 #define FRAME_PREVIEW_OUTPUT2 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FRAME_SNAPSHOT 2
 #define FRAME_THUMBNAIL 3
 #define FRAME_RAW_SNAPSHOT 4
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define FRAME_MAX 5
-struct msm_pmem_info {
- int type;
- int fd;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+enum msm_stats_enum_type {
+ MSM_STATS_TYPE_AEC,
+ MSM_STATS_TYPE_AF,
+ MSM_STATS_TYPE_AWB,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ MSM_STATS_TYPE_RS,
+ MSM_STATS_TYPE_CS,
+ MSM_STATS_TYPE_IHIST,
+ MSM_STATS_TYPE_SKIN,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ MSM_STATS_TYPE_BG,
+ MSM_STATS_TYPE_BF,
+ MSM_STATS_TYPE_BHIST,
+ MSM_STATS_TYPE_AE_AW,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ MSM_STATS_TYPE_MAX
+};
+struct msm_stats_buf_info {
+ int type;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ int fd;
  void *vaddr;
  uint32_t offset;
  uint32_t len;
- uint32_t y_off;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t y_off;
  uint32_t cbcr_off;
- uint8_t vfe_can_write;
+ uint32_t planar0_off;
+ uint32_t planar1_off;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t planar2_off;
+ uint8_t active;
+ int buf_idx;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct msm_pmem_info {
+ int type;
+ int fd;
+ void *vaddr;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t offset;
+ uint32_t len;
+ uint32_t y_off;
+ uint32_t cbcr_off;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t planar0_off;
+ uint32_t planar1_off;
+ uint32_t planar2_off;
+ uint8_t active;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct outputCfg {
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  uint32_t height;
  uint32_t width;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  uint32_t window_height_firstline;
  uint32_t window_height_lastline;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
+#define VIDEO_NODE 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MCTL_NODE 1
 #define OUTPUT_1 0
 #define OUTPUT_2 1
-#define OUTPUT_1_AND_2 2
+#define OUTPUT_1_AND_2 2  
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define CAMIF_TO_AXI_VIA_OUTPUT_2 3
-#define OUTPUT_1_AND_CAMIF_TO_AXI_VIA_OUTPUT_2 4
-#define OUTPUT_2_AND_CAMIF_TO_AXI_VIA_OUTPUT_1 5
-#define OUTPUT_1_AND_3 6
+#define OUTPUT_1_AND_3 3  
+#define CAMIF_TO_AXI_VIA_OUTPUT_2 4
+#define OUTPUT_1_AND_CAMIF_TO_AXI_VIA_OUTPUT_2 5
+#define OUTPUT_2_AND_CAMIF_TO_AXI_VIA_OUTPUT_1 6
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define LAST_AXI_OUTPUT_MODE_ENUM = OUTPUT_1_AND_3 7  
+#define OUTPUT_1_2_AND_3 7
+#define OUTPUT_ALL_CHNLS 8
+#define OUTPUT_VIDEO_ALL_CHNLS 9
+#define OUTPUT_ZSL_ALL_CHNLS 10
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define LAST_AXI_OUTPUT_MODE_ENUM = OUTPUT_ZSL_ALL_CHNLS
+#define OUTPUT_PRIM BIT(8)
+#define OUTPUT_PRIM_ALL_CHNLS BIT(9)
+#define OUTPUT_SEC BIT(10)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define OUTPUT_SEC_ALL_CHNLS BIT(11)
+#define OUTPUT_TERT1 BIT(12)
+#define OUTPUT_TERT2 BIT(13)
 #define MSM_FRAME_PREV_1 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define MSM_FRAME_PREV_2 1
 #define MSM_FRAME_ENC 2
+#define OUTPUT_TYPE_P BIT(0)
+#define OUTPUT_TYPE_T BIT(1)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OUTPUT_TYPE_P 1
-#define OUTPUT_TYPE_T 2
-#define OUTPUT_TYPE_S 3
-#define OUTPUT_TYPE_V 4
+#define OUTPUT_TYPE_S BIT(2)
+#define OUTPUT_TYPE_V BIT(3)
+#define OUTPUT_TYPE_L BIT(4)
+#define OUTPUT_TYPE_ST_L BIT(5)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define OUTPUT_TYPE_ST_R BIT(6)
+#define OUTPUT_TYPE_ST_D BIT(7)
+#define OUTPUT_TYPE_R BIT(8)
+#define OUTPUT_TYPE_R1 BIT(9)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct fd_roi_info {
+ void *info;
+ int info_len;
+};
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+struct msm_mem_map_info {
+ uint32_t cookie;
+ uint32_t length;
+ uint32_t mem_type;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+#define MSM_MEM_MMAP 0
+#define MSM_MEM_USERPTR 1
+#define MSM_PLANE_MAX 8
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSM_PLANE_Y 0
+#define MSM_PLANE_UV 1
 struct msm_frame {
- int path;
- unsigned long buffer;
- uint32_t y_off;
+ struct timespec ts;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ int path;
+ int type;
+ unsigned long buffer;
+ uint32_t phy_offset;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t y_off;
  uint32_t cbcr_off;
+ uint32_t planar0_off;
+ uint32_t planar1_off;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t planar2_off;
  int fd;
  void *cropinfo;
  int croplen;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t error_code;
+ struct fd_roi_info roi_info;
+ uint32_t frame_id;
+ int stcam_quality_ind;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t stcam_conv_value;
+ struct ion_allocation_data ion_alloc;
+ struct ion_fd_data fd_data;
+ int ion_dev_fd;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
-#define STAT_AEAW 0
-#define STAT_AF 1
-#define STAT_AEC 2
+enum msm_st_frame_packing {
+ SIDE_BY_SIDE_HALF,
+ SIDE_BY_SIDE_FULL,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define STAT_AWB 3
-#define STAT_RS 4
-#define STAT_CS 5
-#define STAT_IHIST 6
+ TOP_DOWN_HALF,
+ TOP_DOWN_FULL,
+};
+struct msm_st_crop {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define STAT_SKIN 7
-#define STAT_MAX 8
-struct msm_stats_buf {
+ uint32_t in_w;
+ uint32_t in_h;
+ uint32_t out_w;
+ uint32_t out_h;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+struct msm_st_half {
+ uint32_t buf_p0_off;
+ uint32_t buf_p1_off;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint32_t buf_p0_stride;
+ uint32_t buf_p1_stride;
+ uint32_t pix_x_off;
+ uint32_t pix_y_off;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ struct msm_st_crop stCropInfo;
+};
+struct msm_st_frame {
+ struct msm_frame buf_info;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
  int type;
+ enum msm_st_frame_packing packing;
+ struct msm_st_half L;
+ struct msm_st_half R;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned long buffer;
+ int frame_id;
+};
+#define MSM_CAMERA_ERR_MASK (0xFFFFFFFF & 1)
+struct stats_buff {
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ unsigned long buff;
  int fd;
 };
-#define MSM_V4L2_VID_CAP_TYPE 0
+struct msm_stats_buf {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ uint8_t awb_ymin;
+ struct stats_buff aec;
+ struct stats_buff awb;
+ struct stats_buff af;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ struct stats_buff ihist;
+ struct stats_buff rs;
+ struct stats_buff cs;
+ struct stats_buff skin;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ int type;
+ uint32_t status_bits;
+ unsigned long buffer;
+ int fd;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+ int length;
+ struct ion_handle *handle;
+ uint32_t frame_id;
+ int buf_idx;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+};
+#define MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT 0
+#define MSM_V4L2_EXT_CAPTURE_MODE_PREVIEW   (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+1)
+#define MSM_V4L2_EXT_CAPTURE_MODE_VIDEO   (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+2)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define MSM_V4L2_EXT_CAPTURE_MODE_MAIN (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+3)
+#define MSM_V4L2_EXT_CAPTURE_MODE_THUMBNAIL   (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+4)
+#define MSM_V4L2_EXT_CAPTURE_MODE_RAW   (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+5)
+#define MSM_V4L2_EXT_CAPTURE_MODE_RDI   (MSM_V4L2_EXT_CAPTURE_MOD