commit 2e50fa7cf802a544345d456ae108e7f8eeefc720
author jaishank <jaishankar.rajendran@intel.com> Tue Nov 12 08:57:14 2019 +0530
committer Elliott Hughes <enh@google.com> Tue Nov 12 15:58:34 2019 +0000
tree 8a35529dbf463696fcab7835c8a288be95eded5e
parent ebe5bfefe1a01fbd5c64bdbb5a9ad06bd1a72e2d

Optimized L2 Cache value for Intel(R) Core Architectures.

Performance Gain:
AnTuTu             - 4.80%
3D Mark Sling Shot - 3.47%
BaseMarkGPU        - 5.51%
GeekBench          - 3.19%

Test: ./tests/run-on-host.sh 64

Change-Id: I6122835a3f5fd97cc291623d1062fe25843a2d93
Signed-off-by: jaishank <jaishankar.rajendran@intel.com>

libc/arch-x86_64/string/cache.h

diff --git a/libc/arch-x86_64/string/cache.h b/libc/arch-x86_64/string/cache.h
index 38acc6e..4131509 100644
--- a/libc/arch-x86_64/string/cache.h
+++ b/libc/arch-x86_64/string/cache.h
@@ -28,9 +28,9 @@
 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
-/* Values are optimized for Silvermont */
-#define SHARED_CACHE_SIZE	(1024*1024)			/* Silvermont L2 Cache */
-#define DATA_CACHE_SIZE		(24*1024)			/* Silvermont L1 Data Cache */
+/* Values are optimized for Core Architecture */
+#define SHARED_CACHE_SIZE (4096*1024)  /* Core Architecture L2 Cache */
+#define DATA_CACHE_SIZE   (24*1024)    /* Core Architecture L1 Data Cache */
 
-#define SHARED_CACHE_SIZE_HALF	(SHARED_CACHE_SIZE / 2)
-#define DATA_CACHE_SIZE_HALF	(DATA_CACHE_SIZE / 2)
+#define SHARED_CACHE_SIZE_HALF (SHARED_CACHE_SIZE / 2)
+#define DATA_CACHE_SIZE_HALF   (DATA_CACHE_SIZE / 2)