riscv64: rewrite `CreateTrampoline` using assembler to generate code.
Previously we did not have an assembler for RISC-V, so the instructions
were hardcoded manually. This commit does not change the generated
instructions (aside from using a different temporary register).
Also, fix a clang-tidy error triggered by this commit (add noexcept to
constructor).
Bug: 283082089
Test: boot cuttlefish, observe no crashes in zygote:
$ lunch aosp_cf_riscv64_phone-userdebug && m
$ launch_cvd --gpu_mode=drm_virgl
Test: lunch aosp_arm64-userdebug && m art-tidy
Change-Id: I512a1d408ee3837a4a7631cad6e5da6244b402d4
2 files changed
