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/*
* Copyright (C) 2015 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "code_generator_mips.h"
#include "arch/mips/entrypoints_direct_mips.h"
#include "arch/mips/instruction_set_features_mips.h"
#include "art_method.h"
#include "code_generator_utils.h"
#include "entrypoints/quick/quick_entrypoints.h"
#include "entrypoints/quick/quick_entrypoints_enum.h"
#include "gc/accounting/card_table.h"
#include "intrinsics.h"
#include "intrinsics_mips.h"
#include "mirror/array-inl.h"
#include "mirror/class-inl.h"
#include "offsets.h"
#include "thread.h"
#include "utils/assembler.h"
#include "utils/mips/assembler_mips.h"
#include "utils/stack_checks.h"
namespace art {
namespace mips {
static constexpr int kCurrentMethodStackOffset = 0;
static constexpr Register kMethodRegisterArgument = A0;
// We need extra temporary/scratch registers (in addition to AT) in some cases.
static constexpr FRegister FTMP = F8;
Location MipsReturnLocation(Primitive::Type return_type) {
switch (return_type) {
case Primitive::kPrimBoolean:
case Primitive::kPrimByte:
case Primitive::kPrimChar:
case Primitive::kPrimShort:
case Primitive::kPrimInt:
case Primitive::kPrimNot:
return Location::RegisterLocation(V0);
case Primitive::kPrimLong:
return Location::RegisterPairLocation(V0, V1);
case Primitive::kPrimFloat:
case Primitive::kPrimDouble:
return Location::FpuRegisterLocation(F0);
case Primitive::kPrimVoid:
return Location();
}
UNREACHABLE();
}
Location InvokeDexCallingConventionVisitorMIPS::GetReturnLocation(Primitive::Type type) const {
return MipsReturnLocation(type);
}
Location InvokeDexCallingConventionVisitorMIPS::GetMethodLocation() const {
return Location::RegisterLocation(kMethodRegisterArgument);
}
Location InvokeDexCallingConventionVisitorMIPS::GetNextLocation(Primitive::Type type) {
Location next_location;
switch (type) {
case Primitive::kPrimBoolean:
case Primitive::kPrimByte:
case Primitive::kPrimChar:
case Primitive::kPrimShort:
case Primitive::kPrimInt:
case Primitive::kPrimNot: {
uint32_t gp_index = gp_index_++;
if (gp_index < calling_convention.GetNumberOfRegisters()) {
next_location = Location::RegisterLocation(calling_convention.GetRegisterAt(gp_index));
} else {
size_t stack_offset = calling_convention.GetStackOffsetOf(stack_index_);
next_location = Location::StackSlot(stack_offset);
}
break;
}
case Primitive::kPrimLong: {
uint32_t gp_index = gp_index_;
gp_index_ += 2;
if (gp_index + 1 < calling_convention.GetNumberOfRegisters()) {
if (calling_convention.GetRegisterAt(gp_index) == A1) {
gp_index_++; // Skip A1, and use A2_A3 instead.
gp_index++;
}
Register low_even = calling_convention.GetRegisterAt(gp_index);
Register high_odd = calling_convention.GetRegisterAt(gp_index + 1);
DCHECK_EQ(low_even + 1, high_odd);
next_location = Location::RegisterPairLocation(low_even, high_odd);
} else {
size_t stack_offset = calling_convention.GetStackOffsetOf(stack_index_);
next_location = Location::DoubleStackSlot(stack_offset);
}
break;
}
// Note: both float and double types are stored in even FPU registers. On 32 bit FPU, double
// will take up the even/odd pair, while floats are stored in even regs only.
// On 64 bit FPU, both double and float are stored in even registers only.
case Primitive::kPrimFloat:
case Primitive::kPrimDouble: {
uint32_t float_index = float_index_++;
if (float_index < calling_convention.GetNumberOfFpuRegisters()) {
next_location = Location::FpuRegisterLocation(
calling_convention.GetFpuRegisterAt(float_index));
} else {
size_t stack_offset = calling_convention.GetStackOffsetOf(stack_index_);
next_location = Primitive::Is64BitType(type) ? Location::DoubleStackSlot(stack_offset)
: Location::StackSlot(stack_offset);
}
break;
}
case Primitive::kPrimVoid:
LOG(FATAL) << "Unexpected parameter type " << type;
break;
}
// Space on the stack is reserved for all arguments.
stack_index_ += Primitive::Is64BitType(type) ? 2 : 1;
return next_location;
}
Location InvokeRuntimeCallingConvention::GetReturnLocation(Primitive::Type type) {
return MipsReturnLocation(type);
}
#define __ down_cast<CodeGeneratorMIPS*>(codegen)->GetAssembler()->
#define QUICK_ENTRY_POINT(x) QUICK_ENTRYPOINT_OFFSET(kMipsWordSize, x).Int32Value()
class BoundsCheckSlowPathMIPS : public SlowPathCodeMIPS {
public:
explicit BoundsCheckSlowPathMIPS(HBoundsCheck* instruction) : instruction_(instruction) {}
void EmitNativeCode(CodeGenerator* codegen) OVERRIDE {
LocationSummary* locations = instruction_->GetLocations();
CodeGeneratorMIPS* mips_codegen = down_cast<CodeGeneratorMIPS*>(codegen);
__ Bind(GetEntryLabel());
if (instruction_->CanThrowIntoCatchBlock()) {
// Live registers will be restored in the catch block if caught.
SaveLiveRegisters(codegen, instruction_->GetLocations());
}
// We're moving two locations to locations that could overlap, so we need a parallel
// move resolver.
InvokeRuntimeCallingConvention calling_convention;
codegen->EmitParallelMoves(locations->InAt(0),
Location::RegisterLocation(calling_convention.GetRegisterAt(0)),
Primitive::kPrimInt,
locations->InAt(1),
Location::RegisterLocation(calling_convention.GetRegisterAt(1)),
Primitive::kPrimInt);
mips_codegen->InvokeRuntime(QUICK_ENTRY_POINT(pThrowArrayBounds),
instruction_,
instruction_->GetDexPc(),
this,
IsDirectEntrypoint(kQuickThrowArrayBounds));
CheckEntrypointTypes<kQuickThrowArrayBounds, void, int32_t, int32_t>();
}
bool IsFatal() const OVERRIDE { return true; }
const char* GetDescription() const OVERRIDE { return "BoundsCheckSlowPathMIPS"; }
private:
HBoundsCheck* const instruction_;
DISALLOW_COPY_AND_ASSIGN(BoundsCheckSlowPathMIPS);
};
class DivZeroCheckSlowPathMIPS : public SlowPathCodeMIPS {
public:
explicit DivZeroCheckSlowPathMIPS(HDivZeroCheck* instruction) : instruction_(instruction) {}
void EmitNativeCode(CodeGenerator* codegen) OVERRIDE {
CodeGeneratorMIPS* mips_codegen = down_cast<CodeGeneratorMIPS*>(codegen);
__ Bind(GetEntryLabel());
if (instruction_->CanThrowIntoCatchBlock()) {
// Live registers will be restored in the catch block if caught.
SaveLiveRegisters(codegen, instruction_->GetLocations());
}
mips_codegen->InvokeRuntime(QUICK_ENTRY_POINT(pThrowDivZero),
instruction_,
instruction_->GetDexPc(),
this,
IsDirectEntrypoint(kQuickThrowDivZero));
CheckEntrypointTypes<kQuickThrowDivZero, void, void>();
}
bool IsFatal() const OVERRIDE { return true; }
const char* GetDescription() const OVERRIDE { return "DivZeroCheckSlowPathMIPS"; }
private:
HDivZeroCheck* const instruction_;
DISALLOW_COPY_AND_ASSIGN(DivZeroCheckSlowPathMIPS);
};
class LoadClassSlowPathMIPS : public SlowPathCodeMIPS {
public:
LoadClassSlowPathMIPS(HLoadClass* cls,
HInstruction* at,
uint32_t dex_pc,
bool do_clinit)
: cls_(cls), at_(at), dex_pc_(dex_pc), do_clinit_(do_clinit) {
DCHECK(at->IsLoadClass() || at->IsClinitCheck());
}
void EmitNativeCode(CodeGenerator* codegen) OVERRIDE {
LocationSummary* locations = at_->GetLocations();
CodeGeneratorMIPS* mips_codegen = down_cast<CodeGeneratorMIPS*>(codegen);
__ Bind(GetEntryLabel());
SaveLiveRegisters(codegen, locations);
InvokeRuntimeCallingConvention calling_convention;
__ LoadConst32(calling_convention.GetRegisterAt(0), cls_->GetTypeIndex());
int32_t entry_point_offset = do_clinit_ ? QUICK_ENTRY_POINT(pInitializeStaticStorage)
: QUICK_ENTRY_POINT(pInitializeType);
bool direct = do_clinit_ ? IsDirectEntrypoint(kQuickInitializeStaticStorage)
: IsDirectEntrypoint(kQuickInitializeType);
mips_codegen->InvokeRuntime(entry_point_offset, at_, dex_pc_, this, direct);
if (do_clinit_) {
CheckEntrypointTypes<kQuickInitializeStaticStorage, void*, uint32_t>();
} else {
CheckEntrypointTypes<kQuickInitializeType, void*, uint32_t>();
}
// Move the class to the desired location.
Location out = locations->Out();
if (out.IsValid()) {
DCHECK(out.IsRegister() && !locations->GetLiveRegisters()->ContainsCoreRegister(out.reg()));
Primitive::Type type = at_->GetType();
mips_codegen->MoveLocation(out, calling_convention.GetReturnLocation(type), type);
}
RestoreLiveRegisters(codegen, locations);
__ B(GetExitLabel());
}
const char* GetDescription() const OVERRIDE { return "LoadClassSlowPathMIPS"; }
private:
// The class this slow path will load.
HLoadClass* const cls_;
// The instruction where this slow path is happening.
// (Might be the load class or an initialization check).
HInstruction* const at_;
// The dex PC of `at_`.
const uint32_t dex_pc_;
// Whether to initialize the class.
const bool do_clinit_;
DISALLOW_COPY_AND_ASSIGN(LoadClassSlowPathMIPS);
};
class LoadStringSlowPathMIPS : public SlowPathCodeMIPS {
public:
explicit LoadStringSlowPathMIPS(HLoadString* instruction) : instruction_(instruction) {}
void EmitNativeCode(CodeGenerator* codegen) OVERRIDE {
LocationSummary* locations = instruction_->GetLocations();
DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg()));
CodeGeneratorMIPS* mips_codegen = down_cast<CodeGeneratorMIPS*>(codegen);
__ Bind(GetEntryLabel());
SaveLiveRegisters(codegen, locations);
InvokeRuntimeCallingConvention calling_convention;
__ LoadConst32(calling_convention.GetRegisterAt(0), instruction_->GetStringIndex());
mips_codegen->InvokeRuntime(QUICK_ENTRY_POINT(pResolveString),
instruction_,
instruction_->GetDexPc(),
this,
IsDirectEntrypoint(kQuickResolveString));
CheckEntrypointTypes<kQuickResolveString, void*, uint32_t>();
Primitive::Type type = instruction_->GetType();
mips_codegen->MoveLocation(locations->Out(),
calling_convention.GetReturnLocation(type),
type);
RestoreLiveRegisters(codegen, locations);
__ B(GetExitLabel());
}
const char* GetDescription() const OVERRIDE { return "LoadStringSlowPathMIPS"; }
private:
HLoadString* const instruction_;
DISALLOW_COPY_AND_ASSIGN(LoadStringSlowPathMIPS);
};
class NullCheckSlowPathMIPS : public SlowPathCodeMIPS {
public:
explicit NullCheckSlowPathMIPS(HNullCheck* instr) : instruction_(instr) {}
void EmitNativeCode(CodeGenerator* codegen) OVERRIDE {
CodeGeneratorMIPS* mips_codegen = down_cast<CodeGeneratorMIPS*>(codegen);
__ Bind(GetEntryLabel());
if (instruction_->CanThrowIntoCatchBlock()) {
// Live registers will be restored in the catch block if caught.
SaveLiveRegisters(codegen, instruction_->GetLocations());
}
mips_codegen->InvokeRuntime(QUICK_ENTRY_POINT(pThrowNullPointer),
instruction_,
instruction_->GetDexPc(),
this,
IsDirectEntrypoint(kQuickThrowNullPointer));
CheckEntrypointTypes<kQuickThrowNullPointer, void, void>();
}
bool IsFatal() const OVERRIDE { return true; }
const char* GetDescription() const OVERRIDE { return "NullCheckSlowPathMIPS"; }
private:
HNullCheck* const instruction_;
DISALLOW_COPY_AND_ASSIGN(NullCheckSlowPathMIPS);
};
class SuspendCheckSlowPathMIPS : public SlowPathCodeMIPS {
public:
SuspendCheckSlowPathMIPS(HSuspendCheck* instruction, HBasicBlock* successor)
: instruction_(instruction), successor_(successor) {}
void EmitNativeCode(CodeGenerator* codegen) OVERRIDE {
CodeGeneratorMIPS* mips_codegen = down_cast<CodeGeneratorMIPS*>(codegen);
__ Bind(GetEntryLabel());
SaveLiveRegisters(codegen, instruction_->GetLocations());
mips_codegen->InvokeRuntime(QUICK_ENTRY_POINT(pTestSuspend),
instruction_,
instruction_->GetDexPc(),
this,
IsDirectEntrypoint(kQuickTestSuspend));
CheckEntrypointTypes<kQuickTestSuspend, void, void>();
RestoreLiveRegisters(codegen, instruction_->GetLocations());
if (successor_ == nullptr) {
__ B(GetReturnLabel());
} else {
__ B(mips_codegen->GetLabelOf(successor_));
}
}
MipsLabel* GetReturnLabel() {
DCHECK(successor_ == nullptr);
return &return_label_;
}
const char* GetDescription() const OVERRIDE { return "SuspendCheckSlowPathMIPS"; }
private:
HSuspendCheck* const instruction_;
// If not null, the block to branch to after the suspend check.
HBasicBlock* const successor_;
// If `successor_` is null, the label to branch to after the suspend check.
MipsLabel return_label_;
DISALLOW_COPY_AND_ASSIGN(SuspendCheckSlowPathMIPS);
};
class TypeCheckSlowPathMIPS : public SlowPathCodeMIPS {
public:
explicit TypeCheckSlowPathMIPS(HInstruction* instruction) : instruction_(instruction) {}
void EmitNativeCode(CodeGenerator* codegen) OVERRIDE {
LocationSummary* locations = instruction_->GetLocations();
Location object_class = instruction_->IsCheckCast() ? locations->GetTemp(0) : locations->Out();
uint32_t dex_pc = instruction_->GetDexPc();
DCHECK(instruction_->IsCheckCast()
|| !locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg()));
CodeGeneratorMIPS* mips_codegen = down_cast<CodeGeneratorMIPS*>(codegen);
__ Bind(GetEntryLabel());
SaveLiveRegisters(codegen, locations);
// We're moving two locations to locations that could overlap, so we need a parallel
// move resolver.
InvokeRuntimeCallingConvention calling_convention;
codegen->EmitParallelMoves(locations->InAt(1),
Location::RegisterLocation(calling_convention.GetRegisterAt(0)),
Primitive::kPrimNot,
object_class,
Location::RegisterLocation(calling_convention.GetRegisterAt(1)),
Primitive::kPrimNot);
if (instruction_->IsInstanceOf()) {
mips_codegen->InvokeRuntime(QUICK_ENTRY_POINT(pInstanceofNonTrivial),
instruction_,
dex_pc,
this,
IsDirectEntrypoint(kQuickInstanceofNonTrivial));
CheckEntrypointTypes<
kQuickInstanceofNonTrivial, uint32_t, const mirror::Class*, const mirror::Class*>();
Primitive::Type ret_type = instruction_->GetType();
Location ret_loc = calling_convention.GetReturnLocation(ret_type);
mips_codegen->MoveLocation(locations->Out(), ret_loc, ret_type);
} else {
DCHECK(instruction_->IsCheckCast());
mips_codegen->InvokeRuntime(QUICK_ENTRY_POINT(pCheckCast),
instruction_,
dex_pc,
this,
IsDirectEntrypoint(kQuickCheckCast));
CheckEntrypointTypes<kQuickCheckCast, void, const mirror::Class*, const mirror::Class*>();
}
RestoreLiveRegisters(codegen, locations);
__ B(GetExitLabel());
}
const char* GetDescription() const OVERRIDE { return "TypeCheckSlowPathMIPS"; }
private:
HInstruction* const instruction_;
DISALLOW_COPY_AND_ASSIGN(TypeCheckSlowPathMIPS);
};
class DeoptimizationSlowPathMIPS : public SlowPathCodeMIPS {
public:
explicit DeoptimizationSlowPathMIPS(HDeoptimize* instruction)
: instruction_(instruction) {}
void EmitNativeCode(CodeGenerator* codegen) OVERRIDE {
CodeGeneratorMIPS* mips_codegen = down_cast<CodeGeneratorMIPS*>(codegen);
__ Bind(GetEntryLabel());
SaveLiveRegisters(codegen, instruction_->GetLocations());
mips_codegen->InvokeRuntime(QUICK_ENTRY_POINT(pDeoptimize),
instruction_,
instruction_->GetDexPc(),
this,
IsDirectEntrypoint(kQuickDeoptimize));
CheckEntrypointTypes<kQuickDeoptimize, void, void>();
}
const char* GetDescription() const OVERRIDE { return "DeoptimizationSlowPathMIPS"; }
private:
HDeoptimize* const instruction_;
DISALLOW_COPY_AND_ASSIGN(DeoptimizationSlowPathMIPS);
};
CodeGeneratorMIPS::CodeGeneratorMIPS(HGraph* graph,
const MipsInstructionSetFeatures& isa_features,
const CompilerOptions& compiler_options,
OptimizingCompilerStats* stats)
: CodeGenerator(graph,
kNumberOfCoreRegisters,
kNumberOfFRegisters,
kNumberOfRegisterPairs,
ComputeRegisterMask(reinterpret_cast<const int*>(kCoreCalleeSaves),
arraysize(kCoreCalleeSaves)),
ComputeRegisterMask(reinterpret_cast<const int*>(kFpuCalleeSaves),
arraysize(kFpuCalleeSaves)),
compiler_options,
stats),
block_labels_(nullptr),
location_builder_(graph, this),
instruction_visitor_(graph, this),
move_resolver_(graph->GetArena(), this),
assembler_(&isa_features),
isa_features_(isa_features) {
// Save RA (containing the return address) to mimic Quick.
AddAllocatedRegister(Location::RegisterLocation(RA));
}
#undef __
#define __ down_cast<MipsAssembler*>(GetAssembler())->
#define QUICK_ENTRY_POINT(x) QUICK_ENTRYPOINT_OFFSET(kMipsWordSize, x).Int32Value()
void CodeGeneratorMIPS::Finalize(CodeAllocator* allocator) {
// Ensure that we fix up branches.
__ FinalizeCode();
// Adjust native pc offsets in stack maps.
for (size_t i = 0, num = stack_map_stream_.GetNumberOfStackMaps(); i != num; ++i) {
uint32_t old_position = stack_map_stream_.GetStackMap(i).native_pc_offset;
uint32_t new_position = __ GetAdjustedPosition(old_position);
DCHECK_GE(new_position, old_position);
stack_map_stream_.SetStackMapNativePcOffset(i, new_position);
}
// Adjust pc offsets for the disassembly information.
if (disasm_info_ != nullptr) {
GeneratedCodeInterval* frame_entry_interval = disasm_info_->GetFrameEntryInterval();
frame_entry_interval->start = __ GetAdjustedPosition(frame_entry_interval->start);
frame_entry_interval->end = __ GetAdjustedPosition(frame_entry_interval->end);
for (auto& it : *disasm_info_->GetInstructionIntervals()) {
it.second.start = __ GetAdjustedPosition(it.second.start);
it.second.end = __ GetAdjustedPosition(it.second.end);
}
for (auto& it : *disasm_info_->GetSlowPathIntervals()) {
it.code_interval.start = __ GetAdjustedPosition(it.code_interval.start);
it.code_interval.end = __ GetAdjustedPosition(it.code_interval.end);
}
}
CodeGenerator::Finalize(allocator);
}
MipsAssembler* ParallelMoveResolverMIPS::GetAssembler() const {
return codegen_->GetAssembler();
}
void ParallelMoveResolverMIPS::EmitMove(size_t index) {
DCHECK_LT(index, moves_.size());
MoveOperands* move = moves_[index];
codegen_->MoveLocation(move->GetDestination(), move->GetSource(), move->GetType());
}
void ParallelMoveResolverMIPS::EmitSwap(size_t index) {
DCHECK_LT(index, moves_.size());
MoveOperands* move = moves_[index];
Primitive::Type type = move->GetType();
Location loc1 = move->GetDestination();
Location loc2 = move->GetSource();
DCHECK(!loc1.IsConstant());
DCHECK(!loc2.IsConstant());
if (loc1.Equals(loc2)) {
return;
}
if (loc1.IsRegister() && loc2.IsRegister()) {
// Swap 2 GPRs.
Register r1 = loc1.AsRegister<Register>();
Register r2 = loc2.AsRegister<Register>();
__ Move(TMP, r2);
__ Move(r2, r1);
__ Move(r1, TMP);
} else if (loc1.IsFpuRegister() && loc2.IsFpuRegister()) {
FRegister f1 = loc1.AsFpuRegister<FRegister>();
FRegister f2 = loc2.AsFpuRegister<FRegister>();
if (type == Primitive::kPrimFloat) {
__ MovS(FTMP, f2);
__ MovS(f2, f1);
__ MovS(f1, FTMP);
} else {
DCHECK_EQ(type, Primitive::kPrimDouble);
__ MovD(FTMP, f2);
__ MovD(f2, f1);
__ MovD(f1, FTMP);
}
} else if ((loc1.IsRegister() && loc2.IsFpuRegister()) ||
(loc1.IsFpuRegister() && loc2.IsRegister())) {
// Swap FPR and GPR.
DCHECK_EQ(type, Primitive::kPrimFloat); // Can only swap a float.
FRegister f1 = loc1.IsFpuRegister() ? loc1.AsFpuRegister<FRegister>()
: loc2.AsFpuRegister<FRegister>();
Register r2 = loc1.IsRegister() ? loc1.AsRegister<Register>()
: loc2.AsRegister<Register>();
__ Move(TMP, r2);
__ Mfc1(r2, f1);
__ Mtc1(TMP, f1);
} else if (loc1.IsRegisterPair() && loc2.IsRegisterPair()) {
// Swap 2 GPR register pairs.
Register r1 = loc1.AsRegisterPairLow<Register>();
Register r2 = loc2.AsRegisterPairLow<Register>();
__ Move(TMP, r2);
__ Move(r2, r1);
__ Move(r1, TMP);
r1 = loc1.AsRegisterPairHigh<Register>();
r2 = loc2.AsRegisterPairHigh<Register>();
__ Move(TMP, r2);
__ Move(r2, r1);
__ Move(r1, TMP);
} else if ((loc1.IsRegisterPair() && loc2.IsFpuRegister()) ||
(loc1.IsFpuRegister() && loc2.IsRegisterPair())) {
// Swap FPR and GPR register pair.
DCHECK_EQ(type, Primitive::kPrimDouble);
FRegister f1 = loc1.IsFpuRegister() ? loc1.AsFpuRegister<FRegister>()
: loc2.AsFpuRegister<FRegister>();
Register r2_l = loc1.IsRegisterPair() ? loc1.AsRegisterPairLow<Register>()
: loc2.AsRegisterPairLow<Register>();
Register r2_h = loc1.IsRegisterPair() ? loc1.AsRegisterPairHigh<Register>()
: loc2.AsRegisterPairHigh<Register>();
// Use 2 temporary registers because we can't first swap the low 32 bits of an FPR and
// then swap the high 32 bits of the same FPR. mtc1 makes the high 32 bits of an FPR
// unpredictable and the following mfch1 will fail.
__ Mfc1(TMP, f1);
__ MoveFromFpuHigh(AT, f1);
__ Mtc1(r2_l, f1);
__ MoveToFpuHigh(r2_h, f1);
__ Move(r2_l, TMP);
__ Move(r2_h, AT);
} else if (loc1.IsStackSlot() && loc2.IsStackSlot()) {
Exchange(loc1.GetStackIndex(), loc2.GetStackIndex(), /* double_slot */ false);
} else if (loc1.IsDoubleStackSlot() && loc2.IsDoubleStackSlot()) {
Exchange(loc1.GetStackIndex(), loc2.GetStackIndex(), /* double_slot */ true);
} else if ((loc1.IsRegister() && loc2.IsStackSlot()) ||
(loc1.IsStackSlot() && loc2.IsRegister())) {
Register reg = loc1.IsRegister() ? loc1.AsRegister<Register>()
: loc2.AsRegister<Register>();
intptr_t offset = loc1.IsStackSlot() ? loc1.GetStackIndex()
: loc2.GetStackIndex();
__ Move(TMP, reg);
__ LoadFromOffset(kLoadWord, reg, SP, offset);
__ StoreToOffset(kStoreWord, TMP, SP, offset);
} else if ((loc1.IsRegisterPair() && loc2.IsDoubleStackSlot()) ||
(loc1.IsDoubleStackSlot() && loc2.IsRegisterPair())) {
Register reg_l = loc1.IsRegisterPair() ? loc1.AsRegisterPairLow<Register>()
: loc2.AsRegisterPairLow<Register>();
Register reg_h = loc1.IsRegisterPair() ? loc1.AsRegisterPairHigh<Register>()
: loc2.AsRegisterPairHigh<Register>();
intptr_t offset_l = loc1.IsDoubleStackSlot() ? loc1.GetStackIndex()
: loc2.GetStackIndex();
intptr_t offset_h = loc1.IsDoubleStackSlot() ? loc1.GetHighStackIndex(kMipsWordSize)
: loc2.GetHighStackIndex(kMipsWordSize);
__ Move(TMP, reg_l);
__ Move(AT, reg_h);
__ LoadFromOffset(kLoadWord, reg_l, SP, offset_l);
__ LoadFromOffset(kLoadWord, reg_h, SP, offset_h);
__ StoreToOffset(kStoreWord, TMP, SP, offset_l);
__ StoreToOffset(kStoreWord, AT, SP, offset_h);
} else {
LOG(FATAL) << "Swap between " << loc1 << " and " << loc2 << " is unsupported";
}
}
void ParallelMoveResolverMIPS::RestoreScratch(int reg) {
__ Pop(static_cast<Register>(reg));
}
void ParallelMoveResolverMIPS::SpillScratch(int reg) {
__ Push(static_cast<Register>(reg));
}
void ParallelMoveResolverMIPS::Exchange(int index1, int index2, bool double_slot) {
// Allocate a scratch register other than TMP, if available.
// Else, spill V0 (arbitrary choice) and use it as a scratch register (it will be
// automatically unspilled when the scratch scope object is destroyed).
ScratchRegisterScope ensure_scratch(this, TMP, V0, codegen_->GetNumberOfCoreRegisters());
// If V0 spills onto the stack, SP-relative offsets need to be adjusted.
int stack_offset = ensure_scratch.IsSpilled() ? kMipsWordSize : 0;
for (int i = 0; i <= (double_slot ? 1 : 0); i++, stack_offset += kMipsWordSize) {
__ LoadFromOffset(kLoadWord,
Register(ensure_scratch.GetRegister()),
SP,
index1 + stack_offset);
__ LoadFromOffset(kLoadWord,
TMP,
SP,
index2 + stack_offset);
__ StoreToOffset(kStoreWord,
Register(ensure_scratch.GetRegister()),
SP,
index2 + stack_offset);
__ StoreToOffset(kStoreWord, TMP, SP, index1 + stack_offset);
}
}
static dwarf::Reg DWARFReg(Register reg) {
return dwarf::Reg::MipsCore(static_cast<int>(reg));
}
// TODO: mapping of floating-point registers to DWARF.
void CodeGeneratorMIPS::GenerateFrameEntry() {
__ Bind(&frame_entry_label_);
bool do_overflow_check = FrameNeedsStackCheck(GetFrameSize(), kMips) || !IsLeafMethod();
if (do_overflow_check) {
__ LoadFromOffset(kLoadWord,
ZERO,
SP,
-static_cast<int32_t>(GetStackOverflowReservedBytes(kMips)));
RecordPcInfo(nullptr, 0);
}
if (HasEmptyFrame()) {
return;
}
// Make sure the frame size isn't unreasonably large.
if (GetFrameSize() > GetStackOverflowReservedBytes(kMips)) {
LOG(FATAL) << "Stack frame larger than " << GetStackOverflowReservedBytes(kMips) << " bytes";
}
// Spill callee-saved registers.
// Note that their cumulative size is small and they can be indexed using
// 16-bit offsets.
// TODO: increment/decrement SP in one step instead of two or remove this comment.
uint32_t ofs = FrameEntrySpillSize();
bool unaligned_float = ofs & 0x7;
bool fpu_32bit = isa_features_.Is32BitFloatingPoint();
__ IncreaseFrameSize(ofs);
for (int i = arraysize(kCoreCalleeSaves) - 1; i >= 0; --i) {
Register reg = kCoreCalleeSaves[i];
if (allocated_registers_.ContainsCoreRegister(reg)) {
ofs -= kMipsWordSize;
__ Sw(reg, SP, ofs);
__ cfi().RelOffset(DWARFReg(reg), ofs);
}
}
for (int i = arraysize(kFpuCalleeSaves) - 1; i >= 0; --i) {
FRegister reg = kFpuCalleeSaves[i];
if (allocated_registers_.ContainsFloatingPointRegister(reg)) {
ofs -= kMipsDoublewordSize;
// TODO: Change the frame to avoid unaligned accesses for fpu registers.
if (unaligned_float) {
if (fpu_32bit) {
__ Swc1(reg, SP, ofs);
__ Swc1(static_cast<FRegister>(reg + 1), SP, ofs + 4);
} else {
__ Mfhc1(TMP, reg);
__ Swc1(reg, SP, ofs);
__ Sw(TMP, SP, ofs + 4);
}
} else {
__ Sdc1(reg, SP, ofs);
}
// TODO: __ cfi().RelOffset(DWARFReg(reg), ofs);
}
}
// Allocate the rest of the frame and store the current method pointer
// at its end.
__ IncreaseFrameSize(GetFrameSize() - FrameEntrySpillSize());
static_assert(IsInt<16>(kCurrentMethodStackOffset),
"kCurrentMethodStackOffset must fit into int16_t");
__ Sw(kMethodRegisterArgument, SP, kCurrentMethodStackOffset);
}
void CodeGeneratorMIPS::GenerateFrameExit() {
__ cfi().RememberState();
if (!HasEmptyFrame()) {
// Deallocate the rest of the frame.
__ DecreaseFrameSize(GetFrameSize() - FrameEntrySpillSize());
// Restore callee-saved registers.
// Note that their cumulative size is small and they can be indexed using
// 16-bit offsets.
// TODO: increment/decrement SP in one step instead of two or remove this comment.
uint32_t ofs = 0;
bool unaligned_float = FrameEntrySpillSize() & 0x7;
bool fpu_32bit = isa_features_.Is32BitFloatingPoint();
for (size_t i = 0; i < arraysize(kFpuCalleeSaves); ++i) {
FRegister reg = kFpuCalleeSaves[i];
if (allocated_registers_.ContainsFloatingPointRegister(reg)) {
if (unaligned_float) {
if (fpu_32bit) {
__ Lwc1(reg, SP, ofs);
__ Lwc1(static_cast<FRegister>(reg + 1), SP, ofs + 4);
} else {
__ Lwc1(reg, SP, ofs);
__ Lw(TMP, SP, ofs + 4);
__ Mthc1(TMP, reg);
}
} else {
__ Ldc1(reg, SP, ofs);
}
ofs += kMipsDoublewordSize;
// TODO: __ cfi().Restore(DWARFReg(reg));
}
}
for (size_t i = 0; i < arraysize(kCoreCalleeSaves); ++i) {
Register reg = kCoreCalleeSaves[i];
if (allocated_registers_.ContainsCoreRegister(reg)) {
__ Lw(reg, SP, ofs);
ofs += kMipsWordSize;
__ cfi().Restore(DWARFReg(reg));
}
}
DCHECK_EQ(ofs, FrameEntrySpillSize());
__ DecreaseFrameSize(ofs);
}
__ Jr(RA);
__ Nop();
__ cfi().RestoreState();
__ cfi().DefCFAOffset(GetFrameSize());
}
void CodeGeneratorMIPS::Bind(HBasicBlock* block) {
__ Bind(GetLabelOf(block));
}
void CodeGeneratorMIPS::MoveLocation(Location dst, Location src, Primitive::Type dst_type) {
if (src.Equals(dst)) {
return;
}
if (src.IsConstant()) {
MoveConstant(dst, src.GetConstant());
} else {
if (Primitive::Is64BitType(dst_type)) {
Move64(dst, src);
} else {
Move32(dst, src);
}
}
}
void CodeGeneratorMIPS::Move32(Location destination, Location source) {
if (source.Equals(destination)) {
return;
}
if (destination.IsRegister()) {
if (source.IsRegister()) {
__ Move(destination.AsRegister<Register>(), source.AsRegister<Register>());
} else if (source.IsFpuRegister()) {
__ Mfc1(destination.AsRegister<Register>(), source.AsFpuRegister<FRegister>());
} else {
DCHECK(source.IsStackSlot()) << "Cannot move from " << source << " to " << destination;
__ LoadFromOffset(kLoadWord, destination.AsRegister<Register>(), SP, source.GetStackIndex());
}
} else if (destination.IsFpuRegister()) {
if (source.IsRegister()) {
__ Mtc1(source.AsRegister<Register>(), destination.AsFpuRegister<FRegister>());
} else if (source.IsFpuRegister()) {
__ MovS(destination.AsFpuRegister<FRegister>(), source.AsFpuRegister<FRegister>());
} else {
DCHECK(source.IsStackSlot()) << "Cannot move from " << source << " to " << destination;
__ LoadSFromOffset(destination.AsFpuRegister<FRegister>(), SP, source.GetStackIndex());
}
} else {
DCHECK(destination.IsStackSlot()) << destination;
if (source.IsRegister()) {
__ StoreToOffset(kStoreWord, source.AsRegister<Register>(), SP, destination.GetStackIndex());
} else if (source.IsFpuRegister()) {
__ StoreSToOffset(source.AsFpuRegister<FRegister>(), SP, destination.GetStackIndex());
} else {
DCHECK(source.IsStackSlot()) << "Cannot move from " << source << " to " << destination;
__ LoadFromOffset(kLoadWord, TMP, SP, source.GetStackIndex());
__ StoreToOffset(kStoreWord, TMP, SP, destination.GetStackIndex());
}
}
}
void CodeGeneratorMIPS::Move64(Location destination, Location source) {
if (source.Equals(destination)) {
return;
}
if (destination.IsRegisterPair()) {
if (source.IsRegisterPair()) {
__ Move(destination.AsRegisterPairHigh<Register>(), source.AsRegisterPairHigh<Register>());
__ Move(destination.AsRegisterPairLow<Register>(), source.AsRegisterPairLow<Register>());
} else if (source.IsFpuRegister()) {
Register dst_high = destination.AsRegisterPairHigh<Register>();
Register dst_low = destination.AsRegisterPairLow<Register>();
FRegister src = source.AsFpuRegister<FRegister>();
__ Mfc1(dst_low, src);
__ MoveFromFpuHigh(dst_high, src);
} else {
DCHECK(source.IsDoubleStackSlot()) << "Cannot move from " << source << " to " << destination;
int32_t off = source.GetStackIndex();
Register r = destination.AsRegisterPairLow<Register>();
__ LoadFromOffset(kLoadDoubleword, r, SP, off);
}
} else if (destination.IsFpuRegister()) {
if (source.IsRegisterPair()) {
FRegister dst = destination.AsFpuRegister<FRegister>();
Register src_high = source.AsRegisterPairHigh<Register>();
Register src_low = source.AsRegisterPairLow<Register>();
__ Mtc1(src_low, dst);
__ MoveToFpuHigh(src_high, dst);
} else if (source.IsFpuRegister()) {
__ MovD(destination.AsFpuRegister<FRegister>(), source.AsFpuRegister<FRegister>());
} else {
DCHECK(source.IsDoubleStackSlot()) << "Cannot move from " << source << " to " << destination;
__ LoadDFromOffset(destination.AsFpuRegister<FRegister>(), SP, source.GetStackIndex());
}
} else {
DCHECK(destination.IsDoubleStackSlot()) << destination;
int32_t off = destination.GetStackIndex();
if (source.IsRegisterPair()) {
__ StoreToOffset(kStoreDoubleword, source.AsRegisterPairLow<Register>(), SP, off);
} else if (source.IsFpuRegister()) {
__ StoreDToOffset(source.AsFpuRegister<FRegister>(), SP, off);
} else {
DCHECK(source.IsDoubleStackSlot()) << "Cannot move from " << source << " to " << destination;
__ LoadFromOffset(kLoadWord, TMP, SP, source.GetStackIndex());
__ StoreToOffset(kStoreWord, TMP, SP, off);
__ LoadFromOffset(kLoadWord, TMP, SP, source.GetStackIndex() + 4);
__ StoreToOffset(kStoreWord, TMP, SP, off + 4);
}
}
}
void CodeGeneratorMIPS::MoveConstant(Location destination, HConstant* c) {
if (c->IsIntConstant() || c->IsNullConstant()) {
// Move 32 bit constant.
int32_t value = GetInt32ValueOf(c);
if (destination.IsRegister()) {
Register dst = destination.AsRegister<Register>();
__ LoadConst32(dst, value);
} else {
DCHECK(destination.IsStackSlot())
<< "Cannot move " << c->DebugName() << " to " << destination;
__ StoreConst32ToOffset(value, SP, destination.GetStackIndex(), TMP);
}
} else if (c->IsLongConstant()) {
// Move 64 bit constant.
int64_t value = GetInt64ValueOf(c);
if (destination.IsRegisterPair()) {
Register r_h = destination.AsRegisterPairHigh<Register>();
Register r_l = destination.AsRegisterPairLow<Register>();
__ LoadConst64(r_h, r_l, value);
} else {
DCHECK(destination.IsDoubleStackSlot())
<< "Cannot move " << c->DebugName() << " to " << destination;
__ StoreConst64ToOffset(value, SP, destination.GetStackIndex(), TMP);
}
} else if (c->IsFloatConstant()) {
// Move 32 bit float constant.
int32_t value = GetInt32ValueOf(c);
if (destination.IsFpuRegister()) {
__ LoadSConst32(destination.AsFpuRegister<FRegister>(), value, TMP);
} else {
DCHECK(destination.IsStackSlot())
<< "Cannot move " << c->DebugName() << " to " << destination;
__ StoreConst32ToOffset(value, SP, destination.GetStackIndex(), TMP);
}
} else {
// Move 64 bit double constant.
DCHECK(c->IsDoubleConstant()) << c->DebugName();
int64_t value = GetInt64ValueOf(c);
if (destination.IsFpuRegister()) {
FRegister fd = destination.AsFpuRegister<FRegister>();
__ LoadDConst64(fd, value, TMP);
} else {
DCHECK(destination.IsDoubleStackSlot())
<< "Cannot move " << c->DebugName() << " to " << destination;
__ StoreConst64ToOffset(value, SP, destination.GetStackIndex(), TMP);
}
}
}
void CodeGeneratorMIPS::MoveConstant(Location destination, int32_t value) {
DCHECK(destination.IsRegister());
Register dst = destination.AsRegister<Register>();
__ LoadConst32(dst, value);
}
void CodeGeneratorMIPS::Move(HInstruction* instruction,
Location location,
HInstruction* move_for) {
LocationSummary* locations = instruction->GetLocations();
Primitive::Type type = instruction->GetType();
DCHECK_NE(type, Primitive::kPrimVoid);
if (instruction->IsCurrentMethod()) {
Move32(location, Location::StackSlot(kCurrentMethodStackOffset));
} else if (locations != nullptr && locations->Out().Equals(location)) {
return;
} else if (instruction->IsIntConstant()
|| instruction->IsLongConstant()
|| instruction->IsNullConstant()) {
MoveConstant(location, instruction->AsConstant());
} else if (instruction->IsTemporary()) {
Location temp_location = GetTemporaryLocation(instruction->AsTemporary());
if (temp_location.IsStackSlot()) {
Move32(location, temp_location);
} else {
DCHECK(temp_location.IsDoubleStackSlot());
Move64(location, temp_location);
}
} else if (instruction->IsLoadLocal()) {
uint32_t stack_slot = GetStackSlot(instruction->AsLoadLocal()->GetLocal());
if (Primitive::Is64BitType(type)) {
Move64(location, Location::DoubleStackSlot(stack_slot));
} else {
Move32(location, Location::StackSlot(stack_slot));
}
} else {
DCHECK((instruction->GetNext() == move_for) || instruction->GetNext()->IsTemporary());
if (Primitive::Is64BitType(type)) {
Move64(location, locations->Out());
} else {
Move32(location, locations->Out());
}
}
}
void CodeGeneratorMIPS::AddLocationAsTemp(Location location, LocationSummary* locations) {
if (location.IsRegister()) {
locations->AddTemp(location);
} else if (location.IsRegisterPair()) {
locations->AddTemp(Location::RegisterLocation(location.AsRegisterPairLow<Register>()));
locations->AddTemp(Location::RegisterLocation(location.AsRegisterPairHigh<Register>()));
} else {
UNIMPLEMENTED(FATAL) << "AddLocationAsTemp not implemented for location " << location;
}
}
Location CodeGeneratorMIPS::GetStackLocation(HLoadLocal* load) const {
Primitive::Type type = load->GetType();
switch (type) {
case Primitive::kPrimNot:
case Primitive::kPrimInt:
case Primitive::kPrimFloat:
return Location::StackSlot(GetStackSlot(load->GetLocal()));
case Primitive::kPrimLong:
case Primitive::kPrimDouble:
return Location::DoubleStackSlot(GetStackSlot(load->GetLocal()));
case Primitive::kPrimBoolean:
case Primitive::kPrimByte:
case Primitive::kPrimChar:
case Primitive::kPrimShort:
case Primitive::kPrimVoid:
LOG(FATAL) << "Unexpected type " << type;
}
LOG(FATAL) << "Unreachable";
return Location::NoLocation();
}
void CodeGeneratorMIPS::MarkGCCard(Register object, Register value) {
MipsLabel done;
Register card = AT;
Register temp = TMP;
__ Beqz(value, &done);
__ LoadFromOffset(kLoadWord,
card,
TR,
Thread::CardTableOffset<kMipsWordSize>().Int32Value());
__ Srl(temp, object, gc::accounting::CardTable::kCardShift);
__ Addu(temp, card, temp);
__ Sb(card, temp, 0);
__ Bind(&done);
}
void CodeGeneratorMIPS::SetupBlockedRegisters() const {
// Don't allocate the dalvik style register pair passing.
blocked_register_pairs_[A1_A2] = true;
// ZERO, K0, K1, GP, SP, RA are always reserved and can't be allocated.
blocked_core_registers_[ZERO] = true;
blocked_core_registers_[K0] = true;
blocked_core_registers_[K1] = true;
blocked_core_registers_[GP] = true;
blocked_core_registers_[SP] = true;
blocked_core_registers_[RA] = true;
// AT and TMP(T8) are used as temporary/scratch registers
// (similar to how AT is used by MIPS assemblers).
blocked_core_registers_[AT] = true;
blocked_core_registers_[TMP] = true;
blocked_fpu_registers_[FTMP] = true;
// Reserve suspend and thread registers.
blocked_core_registers_[S0] = true;
blocked_core_registers_[TR] = true;
// Reserve T9 for function calls
blocked_core_registers_[T9] = true;
// Reserve odd-numbered FPU registers.
for (size_t i = 1; i < kNumberOfFRegisters; i += 2) {
blocked_fpu_registers_[i] = true;
}
UpdateBlockedPairRegisters();
}
void CodeGeneratorMIPS::UpdateBlockedPairRegisters() const {
for (int i = 0; i < kNumberOfRegisterPairs; i++) {
MipsManagedRegister current =
MipsManagedRegister::FromRegisterPair(static_cast<RegisterPair>(i));
if (blocked_core_registers_[current.AsRegisterPairLow()]
|| blocked_core_registers_[current.AsRegisterPairHigh()]) {
blocked_register_pairs_[i] = true;
}
}
}
size_t CodeGeneratorMIPS::SaveCoreRegister(size_t stack_index, uint32_t reg_id) {
__ StoreToOffset(kStoreWord, Register(reg_id), SP, stack_index);
return kMipsWordSize;
}
size_t CodeGeneratorMIPS::RestoreCoreRegister(size_t stack_index, uint32_t reg_id) {
__ LoadFromOffset(kLoadWord, Register(reg_id), SP, stack_index);
return kMipsWordSize;
}
size_t CodeGeneratorMIPS::SaveFloatingPointRegister(size_t stack_index, uint32_t reg_id) {
__ StoreDToOffset(FRegister(reg_id), SP, stack_index);
return kMipsDoublewordSize;
}
size_t CodeGeneratorMIPS::RestoreFloatingPointRegister(size_t stack_index, uint32_t reg_id) {
__ LoadDFromOffset(FRegister(reg_id), SP, stack_index);
return kMipsDoublewordSize;
}
void CodeGeneratorMIPS::DumpCoreRegister(std::ostream& stream, int reg) const {
stream << MipsManagedRegister::FromCoreRegister(Register(reg));
}
void CodeGeneratorMIPS::DumpFloatingPointRegister(std::ostream& stream, int reg) const {
stream << MipsManagedRegister::FromFRegister(FRegister(reg));
}
void CodeGeneratorMIPS::InvokeRuntime(QuickEntrypointEnum entrypoint,
HInstruction* instruction,
uint32_t dex_pc,
SlowPathCode* slow_path) {
InvokeRuntime(GetThreadOffset<kMipsWordSize>(entrypoint).Int32Value(),
instruction,
dex_pc,
slow_path,
IsDirectEntrypoint(entrypoint));
}
constexpr size_t kMipsDirectEntrypointRuntimeOffset = 16;
void CodeGeneratorMIPS::InvokeRuntime(int32_t entry_point_offset,
HInstruction* instruction,
uint32_t dex_pc,
SlowPathCode* slow_path,
bool is_direct_entrypoint) {
__ LoadFromOffset(kLoadWord, T9, TR, entry_point_offset);
__ Jalr(T9);
if (is_direct_entrypoint) {
// Reserve argument space on stack (for $a0-$a3) for
// entrypoints that directly reference native implementations.
// Called function may use this space to store $a0-$a3 regs.
__ IncreaseFrameSize(kMipsDirectEntrypointRuntimeOffset); // Single instruction in delay slot.
__ DecreaseFrameSize(kMipsDirectEntrypointRuntimeOffset);
} else {
__ Nop(); // In delay slot.
}
RecordPcInfo(instruction, dex_pc, slow_path);
}
void InstructionCodeGeneratorMIPS::GenerateClassInitializationCheck(SlowPathCodeMIPS* slow_path,
Register class_reg) {
__ LoadFromOffset(kLoadWord, TMP, class_reg, mirror::Class::StatusOffset().Int32Value());
__ LoadConst32(AT, mirror::Class::kStatusInitialized);
__ Blt(TMP, AT, slow_path->GetEntryLabel());
// Even if the initialized flag is set, we need to ensure consistent memory ordering.
__ Sync(0);
__ Bind(slow_path->GetExitLabel());
}
void InstructionCodeGeneratorMIPS::GenerateMemoryBarrier(MemBarrierKind kind ATTRIBUTE_UNUSED) {
__ Sync(0); // Only stype 0 is supported.
}
void InstructionCodeGeneratorMIPS::GenerateSuspendCheck(HSuspendCheck* instruction,
HBasicBlock* successor) {
SuspendCheckSlowPathMIPS* slow_path =
new (GetGraph()->GetArena()) SuspendCheckSlowPathMIPS(instruction, successor);
codegen_->AddSlowPath(slow_path);
__ LoadFromOffset(kLoadUnsignedHalfword,
TMP,
TR,
Thread::ThreadFlagsOffset<kMipsWordSize>().Int32Value());
if (successor == nullptr) {
__ Bnez(TMP, slow_path->GetEntryLabel());
__ Bind(slow_path->GetReturnLabel());
} else {
__ Beqz(TMP, codegen_->GetLabelOf(successor));
__ B(slow_path->GetEntryLabel());
// slow_path will return to GetLabelOf(successor).
}
}
InstructionCodeGeneratorMIPS::InstructionCodeGeneratorMIPS(HGraph* graph,
CodeGeneratorMIPS* codegen)
: InstructionCodeGenerator(graph, codegen),
assembler_(codegen->GetAssembler()),
codegen_(codegen) {}
void LocationsBuilderMIPS::HandleBinaryOp(HBinaryOperation* instruction) {
DCHECK_EQ(instruction->InputCount(), 2U);
LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(instruction);
Primitive::Type type = instruction->GetResultType();
switch (type) {
case Primitive::kPrimInt: {
locations->SetInAt(0, Location::RequiresRegister());
HInstruction* right = instruction->InputAt(1);
bool can_use_imm = false;
if (right->IsConstant()) {
int32_t imm = CodeGenerator::GetInt32ValueOf(right->AsConstant());
if (instruction->IsAnd() || instruction->IsOr() || instruction->IsXor()) {
can_use_imm = IsUint<16>(imm);
} else if (instruction->IsAdd()) {
can_use_imm = IsInt<16>(imm);
} else {
DCHECK(instruction->IsSub());
can_use_imm = IsInt<16>(-imm);
}
}
if (can_use_imm)
locations->SetInAt(1, Location::ConstantLocation(right->AsConstant()));
else
locations->SetInAt(1, Location::RequiresRegister());
locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
break;
}
case Primitive::kPrimLong: {
locations->SetInAt(0, Location::RequiresRegister());
locations->SetInAt(1, Location::RegisterOrConstant(instruction->InputAt(1)));
locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
break;
}
case Primitive::kPrimFloat:
case Primitive::kPrimDouble:
DCHECK(instruction->IsAdd() || instruction->IsSub());
locations->SetInAt(0, Location::RequiresFpuRegister());
locations->SetInAt(1, Location::RequiresFpuRegister());
locations->SetOut(Location::RequiresFpuRegister(), Location::kNoOutputOverlap);
break;
default:
LOG(FATAL) << "Unexpected " << instruction->DebugName() << " type " << type;
}
}
void InstructionCodeGeneratorMIPS::HandleBinaryOp(HBinaryOperation* instruction) {
Primitive::Type type = instruction->GetType();
LocationSummary* locations = instruction->GetLocations();
switch (type) {
case Primitive::kPrimInt: {
Register dst = locations->Out().AsRegister<Register>();
Register lhs = locations->InAt(0).AsRegister<Register>();
Location rhs_location = locations->InAt(1);
Register rhs_reg = ZERO;
int32_t rhs_imm = 0;
bool use_imm = rhs_location.IsConstant();
if (use_imm) {
rhs_imm = CodeGenerator::GetInt32ValueOf(rhs_location.GetConstant());
} else {
rhs_reg = rhs_location.AsRegister<Register>();
}
if (instruction->IsAnd()) {
if (use_imm)
__ Andi(dst, lhs, rhs_imm);
else
__ And(dst, lhs, rhs_reg);
} else if (instruction->IsOr()) {
if (use_imm)
__ Ori(dst, lhs, rhs_imm);
else
__ Or(dst, lhs, rhs_reg);
} else if (instruction->IsXor()) {
if (use_imm)
__ Xori(dst, lhs, rhs_imm);
else
__ Xor(dst, lhs, rhs_reg);
} else if (instruction->IsAdd()) {
if (use_imm)
__ Addiu(dst, lhs, rhs_imm);
else
__ Addu(dst, lhs, rhs_reg);
} else {
DCHECK(instruction->IsSub());
if (use_imm)
__ Addiu(dst, lhs, -rhs_imm);
else
__ Subu(dst, lhs, rhs_reg);
}
break;
}
case Primitive::kPrimLong: {
Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
Register dst_low = locations->Out().AsRegisterPairLow<Register>();
Register lhs_high = locations->InAt(0).AsRegisterPairHigh<Register>();
Register lhs_low = locations->InAt(0).AsRegisterPairLow<Register>();
Location rhs_location = locations->InAt(1);
bool use_imm = rhs_location.IsConstant();
if (!use_imm) {
Register rhs_high = rhs_location.AsRegisterPairHigh<Register>();
Register rhs_low = rhs_location.AsRegisterPairLow<Register>();
if (instruction->IsAnd()) {
__ And(dst_low, lhs_low, rhs_low);
__ And(dst_high, lhs_high, rhs_high);
} else if (instruction->IsOr()) {
__ Or(dst_low, lhs_low, rhs_low);
__ Or(dst_high, lhs_high, rhs_high);
} else if (instruction->IsXor()) {
__ Xor(dst_low, lhs_low, rhs_low);
__ Xor(dst_high, lhs_high, rhs_high);
} else if (instruction->IsAdd()) {
if (lhs_low == rhs_low) {
// Special case for lhs = rhs and the sum potentially overwriting both lhs and rhs.
__ Slt(TMP, lhs_low, ZERO);
__ Addu(dst_low, lhs_low, rhs_low);
} else {
__ Addu(dst_low, lhs_low, rhs_low);
// If the sum overwrites rhs, lhs remains unchanged, otherwise rhs remains unchanged.
__ Sltu(TMP, dst_low, (dst_low == rhs_low) ? lhs_low : rhs_low);
}
__ Addu(dst_high, lhs_high, rhs_high);
__ Addu(dst_high, dst_high, TMP);
} else {
DCHECK(instruction->IsSub());
__ Sltu(TMP, lhs_low, rhs_low);
__ Subu(dst_low, lhs_low, rhs_low);
__ Subu(dst_high, lhs_high, rhs_high);
__ Subu(dst_high, dst_high, TMP);
}
} else {
int64_t value = CodeGenerator::GetInt64ValueOf(rhs_location.GetConstant()->AsConstant());
if (instruction->IsOr()) {
uint32_t low = Low32Bits(value);
uint32_t high = High32Bits(value);
if (IsUint<16>(low)) {
if (dst_low != lhs_low || low != 0) {
__ Ori(dst_low, lhs_low, low);
}
} else {
__ LoadConst32(TMP, low);
__ Or(dst_low, lhs_low, TMP);
}
if (IsUint<16>(high)) {
if (dst_high != lhs_high || high != 0) {
__ Ori(dst_high, lhs_high, high);
}
} else {
if (high != low) {
__ LoadConst32(TMP, high);
}
__ Or(dst_high, lhs_high, TMP);
}
} else if (instruction->IsXor()) {
uint32_t low = Low32Bits(value);
uint32_t high = High32Bits(value);
if (IsUint<16>(low)) {
if (dst_low != lhs_low || low != 0) {
__ Xori(dst_low, lhs_low, low);
}
} else {
__ LoadConst32(TMP, low);
__ Xor(dst_low, lhs_low, TMP);
}
if (IsUint<16>(high)) {
if (dst_high != lhs_high || high != 0) {
__ Xori(dst_high, lhs_high, high);
}
} else {
if (high != low) {
__ LoadConst32(TMP, high);
}
__ Xor(dst_high, lhs_high, TMP);
}
} else if (instruction->IsAnd()) {
uint32_t low = Low32Bits(value);
uint32_t high = High32Bits(value);
if (IsUint<16>(low)) {
__ Andi(dst_low, lhs_low, low);
} else if (low != 0xFFFFFFFF) {
__ LoadConst32(TMP, low);
__ And(dst_low, lhs_low, TMP);
} else if (dst_low != lhs_low) {
__ Move(dst_low, lhs_low);
}
if (IsUint<16>(high)) {
__ Andi(dst_high, lhs_high, high);
} else if (high != 0xFFFFFFFF) {
if (high != low) {
__ LoadConst32(TMP, high);
}
__ And(dst_high, lhs_high, TMP);
} else if (dst_high != lhs_high) {
__ Move(dst_high, lhs_high);
}
} else {
if (instruction->IsSub()) {
value = -value;
} else {
DCHECK(instruction->IsAdd());
}
int32_t low = Low32Bits(value);
int32_t high = High32Bits(value);
if (IsInt<16>(low)) {
if (dst_low != lhs_low || low != 0) {
__ Addiu(dst_low, lhs_low, low);
}
if (low != 0) {
__ Sltiu(AT, dst_low, low);
}
} else {
__ LoadConst32(TMP, low);
__ Addu(dst_low, lhs_low, TMP);
__ Sltu(AT, dst_low, TMP);
}
if (IsInt<16>(high)) {
if (dst_high != lhs_high || high != 0) {
__ Addiu(dst_high, lhs_high, high);
}
} else {
if (high != low) {
__ LoadConst32(TMP, high);
}
__ Addu(dst_high, lhs_high, TMP);
}
if (low != 0) {
__ Addu(dst_high, dst_high, AT);
}
}
}
break;
}
case Primitive::kPrimFloat:
case Primitive::kPrimDouble: {
FRegister dst = locations->Out().AsFpuRegister<FRegister>();
FRegister lhs = locations->InAt(0).AsFpuRegister<FRegister>();
FRegister rhs = locations->InAt(1).AsFpuRegister<FRegister>();
if (instruction->IsAdd()) {
if (type == Primitive::kPrimFloat) {
__ AddS(dst, lhs, rhs);
} else {
__ AddD(dst, lhs, rhs);
}
} else {
DCHECK(instruction->IsSub());
if (type == Primitive::kPrimFloat) {
__ SubS(dst, lhs, rhs);
} else {
__ SubD(dst, lhs, rhs);
}
}
break;
}
default:
LOG(FATAL) << "Unexpected binary operation type " << type;
}
}
void LocationsBuilderMIPS::HandleShift(HBinaryOperation* instr) {
DCHECK(instr->IsShl() || instr->IsShr() || instr->IsUShr() || instr->IsRor());
LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(instr);
Primitive::Type type = instr->GetResultType();
switch (type) {
case Primitive::kPrimInt:
locations->SetInAt(0, Location::RequiresRegister());
locations->SetInAt(1, Location::RegisterOrConstant(instr->InputAt(1)));
locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
break;
case Primitive::kPrimLong:
locations->SetInAt(0, Location::RequiresRegister());
locations->SetInAt(1, Location::RegisterOrConstant(instr->InputAt(1)));
locations->SetOut(Location::RequiresRegister());
break;
default:
LOG(FATAL) << "Unexpected shift type " << type;
}
}
static constexpr size_t kMipsBitsPerWord = kMipsWordSize * kBitsPerByte;
void InstructionCodeGeneratorMIPS::HandleShift(HBinaryOperation* instr) {
DCHECK(instr->IsShl() || instr->IsShr() || instr->IsUShr() || instr->IsRor());
LocationSummary* locations = instr->GetLocations();
Primitive::Type type = instr->GetType();
Location rhs_location = locations->InAt(1);
bool use_imm = rhs_location.IsConstant();
Register rhs_reg = use_imm ? ZERO : rhs_location.AsRegister<Register>();
int64_t rhs_imm = use_imm ? CodeGenerator::GetInt64ValueOf(rhs_location.GetConstant()) : 0;
const uint32_t shift_mask = (type == Primitive::kPrimInt)
? kMaxIntShiftValue
: kMaxLongShiftValue;
const uint32_t shift_value = rhs_imm & shift_mask;
// Are the INS (Insert Bit Field) and ROTR instructions supported?
bool has_ins_rotr = codegen_->GetInstructionSetFeatures().IsMipsIsaRevGreaterThanEqual2();
switch (type) {
case Primitive::kPrimInt: {
Register dst = locations->Out().AsRegister<Register>();
Register lhs = locations->InAt(0).AsRegister<Register>();
if (use_imm) {
if (shift_value == 0) {
if (dst != lhs) {
__ Move(dst, lhs);
}
} else if (instr->IsShl()) {
__ Sll(dst, lhs, shift_value);
} else if (instr->IsShr()) {
__ Sra(dst, lhs, shift_value);
} else if (instr->IsUShr()) {
__ Srl(dst, lhs, shift_value);
} else {
if (has_ins_rotr) {
__ Rotr(dst, lhs, shift_value);
} else {
__ Sll(TMP, lhs, (kMipsBitsPerWord - shift_value) & shift_mask);
__ Srl(dst, lhs, shift_value);
__ Or(dst, dst, TMP);
}
}
} else {
if (instr->IsShl()) {
__ Sllv(dst, lhs, rhs_reg);
} else if (instr->IsShr()) {
__ Srav(dst, lhs, rhs_reg);
} else if (instr->IsUShr()) {
__ Srlv(dst, lhs, rhs_reg);
} else {
if (has_ins_rotr) {
__ Rotrv(dst, lhs, rhs_reg);
} else {
__ Subu(TMP, ZERO, rhs_reg);
// 32-bit shift instructions use the 5 least significant bits of the shift count, so
// shifting by `-rhs_reg` is equivalent to shifting by `(32 - rhs_reg) & 31`. The case
// when `rhs_reg & 31 == 0` is OK even though we don't shift `lhs` left all the way out
// by 32, because the result in this case is computed as `(lhs >> 0) | (lhs << 0)`,
// IOW, the OR'd values are equal.
__ Sllv(TMP, lhs, TMP);
__ Srlv(dst, lhs, rhs_reg);
__ Or(dst, dst, TMP);
}
}
}
break;
}
case Primitive::kPrimLong: {
Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
Register dst_low = locations->Out().AsRegisterPairLow<Register>();
Register lhs_high = locations->InAt(0).AsRegisterPairHigh<Register>();
Register lhs_low = locations->InAt(0).AsRegisterPairLow<Register>();
if (use_imm) {
if (shift_value == 0) {
codegen_->Move64(locations->Out(), locations->InAt(0));
} else if (shift_value < kMipsBitsPerWord) {
if (has_ins_rotr) {
if (instr->IsShl()) {
__ Srl(dst_high, lhs_low, kMipsBitsPerWord - shift_value);
__ Ins(dst_high, lhs_high, shift_value, kMipsBitsPerWord - shift_value);
__ Sll(dst_low, lhs_low, shift_value);
} else if (instr->IsShr()) {
__ Srl(dst_low, lhs_low, shift_value);
__ Ins(dst_low, lhs_high, kMipsBitsPerWord - shift_value, shift_value);
__ Sra(dst_high, lhs_high, shift_value);
} else if (instr->IsUShr()) {
__ Srl(dst_low, lhs_low, shift_value);
__ Ins(dst_low, lhs_high, kMipsBitsPerWord - shift_value, shift_value);
__ Srl(dst_high, lhs_high, shift_value);
} else {
__ Srl(dst_low, lhs_low, shift_value);
__ Ins(dst_low, lhs_high, kMipsBitsPerWord - shift_value, shift_value);
__ Srl(dst_high, lhs_high, shift_value);
__ Ins(dst_high, lhs_low, kMipsBitsPerWord - shift_value, shift_value);
}
} else {
if (instr->IsShl()) {
__ Sll(dst_low, lhs_low, shift_value);
__ Srl(TMP, lhs_low, kMipsBitsPerWord - shift_value);
__ Sll(dst_high, lhs_high, shift_value);
__ Or(dst_high, dst_high, TMP);
} else if (instr->IsShr()) {
__ Sra(dst_high, lhs_high, shift_value);
__ Sll(TMP, lhs_high, kMipsBitsPerWord - shift_value);
__ Srl(dst_low, lhs_low, shift_value);
__ Or(dst_low, dst_low, TMP);
} else if (instr->IsUShr()) {
__ Srl(dst_high, lhs_high, shift_value);
__ Sll(TMP, lhs_high, kMipsBitsPerWord - shift_value);
__ Srl(dst_low, lhs_low, shift_value);
__ Or(dst_low, dst_low, TMP);
} else {
__ Srl(TMP, lhs_low, shift_value);
__ Sll(dst_low, lhs_high, kMipsBitsPerWord - shift_value);
__ Or(dst_low, dst_low, TMP);
__ Srl(TMP, lhs_high, shift_value);
__ Sll(dst_high, lhs_low, kMipsBitsPerWord - shift_value);
__ Or(dst_high, dst_high, TMP);
}
}
} else {
const uint32_t shift_value_high = shift_value - kMipsBitsPerWord;
if (instr->IsShl()) {
__ Sll(dst_high, lhs_low, shift_value_high);
__ Move(dst_low, ZERO);
} else if (instr->IsShr()) {
__ Sra(dst_low, lhs_high, shift_value_high);
__ Sra(dst_high, dst_low, kMipsBitsPerWord - 1);
} else if (instr->IsUShr()) {
__ Srl(dst_low, lhs_high, shift_value_high);
__ Move(dst_high, ZERO);
} else {
if (shift_value == kMipsBitsPerWord) {
// 64-bit rotation by 32 is just a swap.
__ Move(dst_low, lhs_high);
__ Move(dst_high, lhs_low);
} else {
if (has_ins_rotr) {
__ Srl(dst_low, lhs_high, shift_value_high);
__ Ins(dst_low, lhs_low, kMipsBitsPerWord - shift_value_high, shift_value_high);
__ Srl(dst_high, lhs_low, shift_value_high);
__ Ins(dst_high, lhs_high, kMipsBitsPerWord - shift_value_high, shift_value_high);
} else {
__ Sll(TMP, lhs_low, kMipsBitsPerWord - shift_value_high);
__ Srl(dst_low, lhs_high, shift_value_high);
__ Or(dst_low, dst_low, TMP);
__ Sll(TMP, lhs_high, kMipsBitsPerWord - shift_value_high);
__ Srl(dst_high, lhs_low, shift_value_high);
__ Or(dst_high, dst_high, TMP);
}
}
}
}
} else {
MipsLabel done;
if (instr->IsShl()) {
__ Sllv(dst_low, lhs_low, rhs_reg);
__ Nor(AT, ZERO, rhs_reg);
__ Srl(TMP, lhs_low, 1);
__ Srlv(TMP, TMP, AT);
__ Sllv(dst_high, lhs_high, rhs_reg);
__ Or(dst_high, dst_high, TMP);
__ Andi(TMP, rhs_reg, kMipsBitsPerWord);
__ Beqz(TMP, &done);
__ Move(dst_high, dst_low);
__ Move(dst_low, ZERO);
} else if (instr->IsShr()) {
__ Srav(dst_high, lhs_high, rhs_reg);
__ Nor(AT, ZERO, rhs_reg);
__ Sll(TMP, lhs_high, 1);
__ Sllv(TMP, TMP, AT);
__ Srlv(dst_low, lhs_low, rhs_reg);
__ Or(dst_low, dst_low, TMP);
__ Andi(TMP, rhs_reg, kMipsBitsPerWord);
__ Beqz(TMP, &done);
__ Move(dst_low, dst_high);
__ Sra(dst_high, dst_high, 31);
} else if (instr->IsUShr()) {
__ Srlv(dst_high, lhs_high, rhs_reg);
__ Nor(AT, ZERO, rhs_reg);
__ Sll(TMP, lhs_high, 1);
__ Sllv(TMP, TMP, AT);
__ Srlv(dst_low, lhs_low, rhs_reg);
__ Or(dst_low, dst_low, TMP);
__ Andi(TMP, rhs_reg, kMipsBitsPerWord);
__ Beqz(TMP, &done);
__ Move(dst_low, dst_high);
__ Move(dst_high, ZERO);
} else {
__ Nor(AT, ZERO, rhs_reg);
__ Srlv(TMP, lhs_low, rhs_reg);
__ Sll(dst_low, lhs_high, 1);
__ Sllv(dst_low, dst_low, AT);
__ Or(dst_low, dst_low, TMP);
__ Srlv(TMP, lhs_high, rhs_reg);
__ Sll(dst_high, lhs_low, 1);
__ Sllv(dst_high, dst_high, AT);
__ Or(dst_high, dst_high, TMP);
__ Andi(TMP, rhs_reg, kMipsBitsPerWord);
__ Beqz(TMP, &done);
__ Move(TMP, dst_high);
__ Move(dst_high, dst_low);
__ Move(dst_low, TMP);
}
__ Bind(&done);
}
break;
}
default:
LOG(FATAL) << "Unexpected shift operation type " << type;
}
}
void LocationsBuilderMIPS::VisitAdd(HAdd* instruction) {
HandleBinaryOp(instruction);
}
void InstructionCodeGeneratorMIPS::VisitAdd(HAdd* instruction) {
HandleBinaryOp(instruction);
}
void LocationsBuilderMIPS::VisitAnd(HAnd* instruction) {
HandleBinaryOp(instruction);
}
void InstructionCodeGeneratorMIPS::VisitAnd(HAnd* instruction) {
HandleBinaryOp(instruction);
}
void LocationsBuilderMIPS::VisitArrayGet(HArrayGet* instruction) {
LocationSummary* locations =
new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kNoCall);
locations->SetInAt(0, Location::RequiresRegister());
locations->SetInAt(1, Location::RegisterOrConstant(instruction->InputAt(1)));
if (Primitive::IsFloatingPointType(instruction->GetType())) {
locations->SetOut(Location::RequiresFpuRegister(), Location::kNoOutputOverlap);
} else {
locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
}
}
void InstructionCodeGeneratorMIPS::VisitArrayGet(HArrayGet* instruction) {
LocationSummary* locations = instruction->GetLocations();
Register obj = locations->InAt(0).AsRegister<Register>();
Location index = locations->InAt(1);
Primitive::Type type = instruction->GetType();
switch (type) {
case Primitive::kPrimBoolean: {
uint32_t data_offset = mirror::Array::DataOffset(sizeof(uint8_t)).Uint32Value();
Register out = locations->Out().AsRegister<Register>();
if (index.IsConstant()) {
size_t offset =
(index.GetConstant()->AsIntConstant()->GetValue() << TIMES_1) + data_offset;
__ LoadFromOffset(kLoadUnsignedByte, out, obj, offset);
} else {
__ Addu(TMP, obj, index.AsRegister<Register>());
__ LoadFromOffset(kLoadUnsignedByte, out, TMP, data_offset);
}
break;
}
case Primitive::kPrimByte: {
uint32_t data_offset = mirror::Array::DataOffset(sizeof(int8_t)).Uint32Value();
Register out = locations->Out().AsRegister<Register>();
if (index.IsConstant()) {
size_t offset =
(index.GetConstant()->AsIntConstant()->GetValue() << TIMES_1) + data_offset;
__ LoadFromOffset(kLoadSignedByte, out, obj, offset);
} else {
__ Addu(TMP, obj, index.AsRegister<Register>());
__ LoadFromOffset(kLoadSignedByte, out, TMP, data_offset);
}
break;
}
case Primitive::kPrimShort: {
uint32_t data_offset = mirror::Array::DataOffset(sizeof(int16_t)).Uint32Value();
Register out = locations->Out().AsRegister<Register>();
if (index.IsConstant()) {
size_t offset =
(index.GetConstant()->AsIntConstant()->GetValue() << TIMES_2) + data_offset;
__ LoadFromOffset(kLoadSignedHalfword, out, obj, offset);
} else {
__ Sll(TMP, index.AsRegister<Register>(), TIMES_2);
__ Addu(TMP, obj, TMP);
__ LoadFromOffset(kLoadSignedHalfword, out, TMP, data_offset);
}
break;
}
case Primitive::kPrimChar: {
uint32_t data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Uint32Value();
Register out = locations->Out().AsRegister<Register>();
if (index.IsConstant()) {
size_t offset =
(index.GetConstant()->AsIntConstant()->GetValue() << TIMES_2) + data_offset;
__ LoadFromOffset(kLoadUnsignedHalfword, out, obj, offset);
} else {
__ Sll(TMP, index.AsRegister<Register>(), TIMES_2);
__ Addu(TMP, obj, TMP);
__ LoadFromOffset(kLoadUnsignedHalfword, out, TMP, data_offset);
}
break;
}
case Primitive::kPrimInt:
case Primitive::kPrimNot: {
DCHECK_EQ(sizeof(mirror::HeapReference<mirror::Object>), sizeof(int32_t));
uint32_t data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Uint32Value();
Register out = locations->Out().AsRegister<Register>();
if (index.IsConstant()) {
size_t offset =
(index.GetConstant()->AsIntConstant()->GetValue() << TIMES_4) + data_offset;
__ LoadFromOffset(kLoadWord, out, obj, offset);
} else {
__ Sll(TMP, index.AsRegister<Register>(), TIMES_4);
__ Addu(TMP, obj, TMP);
__ LoadFromOffset(kLoadWord, out, TMP, data_offset);
}
break;
}
case Primitive::kPrimLong: {
uint32_t data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Uint32Value();
Register out = locations->Out().AsRegisterPairLow<Register>();
if (index.IsConstant()) {
size_t offset =
(index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset;
__ LoadFromOffset(kLoadDoubleword, out, obj, offset);
} else {
__ Sll(TMP, index.AsRegister<Register>(), TIMES_8);
__ Addu(TMP, obj, TMP);
__ LoadFromOffset(kLoadDoubleword, out, TMP, data_offset);
}
break;
}
case Primitive::kPrimFloat: {
uint32_t data_offset = mirror::Array::DataOffset(sizeof(float)).Uint32Value();
FRegister out = locations->Out().AsFpuRegister<FRegister>();
if (index.IsConstant()) {
size_t offset =
(index.GetConstant()->AsIntConstant()->GetValue() << TIMES_4) + data_offset;
__ LoadSFromOffset(out, obj, offset);
} else {
__ Sll(TMP, index.AsRegister<Register>(), TIMES_4);
__ Addu(TMP, obj, TMP);
__ LoadSFromOffset(out, TMP, data_offset);
}
break;
}
case Primitive::kPrimDouble: {
uint32_t data_offset = mirror::Array::DataOffset(sizeof(double)).Uint32Value();
FRegister out = locations->Out().AsFpuRegister<FRegister>();
if (index.IsConstant()) {
size_t offset =
(index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset;
__ LoadDFromOffset(out, obj, offset);
} else {
__ Sll(TMP, index.AsRegister<Register>(), TIMES_8);
__ Addu(TMP, obj, TMP);
__ LoadDFromOffset(out, TMP, data_offset);
}
break;
}
case Primitive::kPrimVoid:
LOG(FATAL) << "Unreachable type " << instruction->GetType();
UNREACHABLE();
}
codegen_->MaybeRecordImplicitNullCheck(instruction);
}
void LocationsBuilderMIPS::VisitArrayLength(HArrayLength* instruction) {
LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(instruction);
locations->SetInAt(0, Location::RequiresRegister());
locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
}
void InstructionCodeGeneratorMIPS::VisitArrayLength(HArrayLength* instruction) {
LocationSummary* locations = instruction->GetLocations();
uint32_t offset = mirror::Array::LengthOffset().Uint32Value();
Register obj = locations->InAt(0).AsRegister<Register>();
Register out = locations->Out().AsRegister<Register>();
__ LoadFromOffset(kLoadWord, out, obj, offset);
codegen_->MaybeRecordImplicitNullCheck(instruction);
}
void LocationsBuilderMIPS::VisitArraySet(HArraySet* instruction) {
bool needs_runtime_call = instruction->NeedsTypeCheck();
LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(
instruction,
needs_runtime_call ? LocationSummary::kCall : LocationSummary::kNoCall);
if (needs_runtime_call) {
InvokeRuntimeCallingConvention calling_convention;
locations->SetInAt(0, Location::RegisterLocation(calling_convention.GetRegisterAt(0)));
locations->SetInAt(1, Location::RegisterLocation(calling_convention.GetRegisterAt(1)));
locations->SetInAt(2, Location::RegisterLocation(calling_convention.GetRegisterAt(2)));
} else {
locations->SetInAt(0, Location::RequiresRegister());
locations->SetInAt(1, Location::RegisterOrConstant(instruction->InputAt(1)));
if (Primitive::IsFloatingPointType(instruction->InputAt(2)->GetType())) {
locations->SetInAt(2, Location::RequiresFpuRegister());
} else {
locations->SetInAt(2, Location::RequiresRegister());
}
}
}
void InstructionCodeGeneratorMIPS::VisitArraySet(HArraySet* instruction) {
LocationSummary* locations = instruction->GetLocations();
Register obj = locations->InAt(0).AsRegister<Register>();
Location index = locations->InAt(1);
Primitive::Type value_type = instruction->GetComponentType();
bool needs_runtime_call = locations->WillCall();
bool needs_write_barrier =
CodeGenerator::StoreNeedsWriteBarrier(value_type, instruction->GetValue());
switch (value_type) {
case Primitive::kPrimBoolean:
case Primitive::kPrimByte: {
uint32_t data_offset = mirror::Array::DataOffset(sizeof(uint8_t)).Uint32Value();
Register value = locations->InAt(2).AsRegister<Register>();
if (index.IsConstant()) {
size_t offset =
(index.GetConstant()->AsIntConstant()->GetValue() << TIMES_1) + data_offset;
__ StoreToOffset(kStoreByte, value, obj, offset);
} else {
__ Addu(TMP, obj, index.AsRegister<Register>());
__ StoreToOffset(kStoreByte, value, TMP, data_offset);
}
break;
}
case Primitive::kPrimShort:
case Primitive::kPrimChar: {
uint32_t data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Uint32Value();
Register value = locations->InAt(2).AsRegister<Register>();
if (index.IsConstant()) {
size_t offset =
(index.GetConstant()->AsIntConstant()->GetValue() << TIMES_2) + data_offset;
__ StoreToOffset(kStoreHalfword, value, obj, offset);
} else {
__ Sll(TMP, index.AsRegister<Register>(), TIMES_2);
__ Addu(TMP, obj, TMP);
__ StoreToOffset(kStoreHalfword, value, TMP, data_offset);
}
break;
}
case Primitive::kPrimInt:
case Primitive::kPrimNot: {
if (!needs_runtime_call) {
uint32_t data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Uint32Value();
Register value = locations->InAt(2).AsRegister<Register>();
if (index.IsConstant()) {
size_t offset =
(index.GetConstant()->AsIntConstant()->GetValue() << TIMES_4) + data_offset;
__ StoreToOffset(kStoreWord, value, obj, offset);
} else {
DCHECK(index.IsRegister()) << index;
__ Sll(TMP, index.AsRegister<Register>(), TIMES_4);
__ Addu(TMP, obj, TMP);
__ StoreToOffset(kStoreWord, value, TMP, data_offset);
}
codegen_->MaybeRecordImplicitNullCheck(instruction);
if (needs_write_barrier) {
DCHECK_EQ(value_type, Primitive::kPrimNot);
codegen_->MarkGCCard(obj, value);
}
} else {
DCHECK_EQ(value_type, Primitive::kPrimNot);
codegen_->InvokeRuntime(QUICK_ENTRY_POINT(pAputObject),
instruction,
instruction->GetDexPc(),
nullptr,
IsDirectEntrypoint(kQuickAputObject));
CheckEntrypointTypes<kQuickAputObject, void, mirror::Array*, int32_t, mirror::Object*>();
}
break;
}
case Primitive::kPrimLong: {
uint32_t data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Uint32Value();
Register value = locations->InAt(2).AsRegisterPairLow<Register>();
if (index.IsConstant()) {
size_t offset =
(index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset;
__ StoreToOffset(kStoreDoubleword, value, obj, offset);
} else {
__ Sll(TMP, index.AsRegister<Register>(), TIMES_8);
__ Addu(TMP, obj, TMP);
__ StoreToOffset(kStoreDoubleword, value, TMP, data_offset);
}
break;
}
case Primitive::kPrimFloat: {
uint32_t data_offset = mirror::Array::DataOffset(sizeof(float)).Uint32Value();
FRegister value = locations->InAt(2).AsFpuRegister<FRegister>();
DCHECK(locations->InAt(2).IsFpuRegister());
if (index.IsConstant()) {
size_t offset =
(index.GetConstant()->AsIntConstant()->GetValue() << TIMES_4) + data_offset;
__ StoreSToOffset(value, obj, offset);
} else {
__ Sll(TMP, index.AsRegister<Register>(), TIMES_4);
__ Addu(TMP, obj, TMP);
__ StoreSToOffset(value, TMP, data_offset);
}
break;
}
case Primitive::kPrimDouble: {
uint32_t data_offset = mirror::Array::DataOffset(sizeof(double)).Uint32Value();
FRegister value = locations->InAt(2).AsFpuRegister<FRegister>();
DCHECK(locations->InAt(2).IsFpuRegister());
if (index.IsConstant()) {
size_t offset =
(index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset;
__ StoreDToOffset(value, obj, offset);
} else {
__ Sll(TMP, index.AsRegister<Register>(), TIMES_8);
__ Addu(TMP, obj, TMP);
__ StoreDToOffset(value, TMP, data_offset);
}
break;
}
case Primitive::kPrimVoid:
LOG(FATAL) << "Unreachable type " << instruction->GetType();
UNREACHABLE();
}
// Ints and objects are handled in the switch.
if (value_type != Primitive::kPrimInt && value_type != Primitive::kPrimNot) {
codegen_->MaybeRecordImplicitNullCheck(instruction);
}
}
void LocationsBuilderMIPS::VisitBoundsCheck(HBoundsCheck* instruction) {
LocationSummary::CallKind call_kind = instruction->CanThrowIntoCatchBlock()
? LocationSummary::kCallOnSlowPath
: LocationSummary::kNoCall;
LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(instruction, call_kind);
locations->SetInAt(0, Location::RequiresRegister());
locations->SetInAt(1, Location::RequiresRegister());
if (instruction->HasUses()) {
locations->SetOut(Location::SameAsFirstInput());
}
}
void InstructionCodeGeneratorMIPS::VisitBoundsCheck(HBoundsCheck* instruction) {
LocationSummary* locations = instruction->GetLocations();
BoundsCheckSlowPathMIPS* slow_path =
new (GetGraph()->GetArena()) BoundsCheckSlowPathMIPS(instruction);
codegen_->AddSlowPath(slow_path);
Register index = locations->InAt(0).AsRegister<Register>();
Register length = locations->InAt(1).AsRegister<Register>();
// length is limited by the maximum positive signed 32-bit integer.
// Unsigned comparison of length and index checks for index < 0
// and for length <= index simultaneously.
__ Bgeu(index, length, slow_path->GetEntryLabel());
}
void LocationsBuilderMIPS::VisitCheckCast(HCheckCast* instruction) {
LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(
instruction,
LocationSummary::kCallOnSlowPath);
locations->SetInAt(0, Location::RequiresRegister());
locations->SetInAt(1, Location::RequiresRegister());
// Note that TypeCheckSlowPathMIPS uses this register too.
locations->AddTemp(Location::RequiresRegister());
}
void InstructionCodeGeneratorMIPS::VisitCheckCast(HCheckCast* instruction) {
LocationSummary* locations = instruction->GetLocations();
Register obj = locations->InAt(0).AsRegister<Register>();
Register cls = locations->InAt(1).AsRegister<Register>();
Register obj_cls = locations->GetTemp(0).AsRegister<Register>();
SlowPathCodeMIPS* slow_path = new (GetGraph()->GetArena()) TypeCheckSlowPathMIPS(instruction);
codegen_->AddSlowPath(slow_path);
// TODO: avoid this check if we know obj is not null.
__ Beqz(obj, slow_path->GetExitLabel());
// Compare the class of `obj` with `cls`.
__ LoadFromOffset(kLoadWord, obj_cls, obj, mirror::Object::ClassOffset().Int32Value());
__ Bne(obj_cls, cls, slow_path->GetEntryLabel());
__ Bind(slow_path->GetExitLabel());
}
void LocationsBuilderMIPS::VisitClinitCheck(HClinitCheck* check) {
LocationSummary* locations =
new (GetGraph()->GetArena()) LocationSummary(check, LocationSummary::kCallOnSlowPath);
locations->SetInAt(0, Location::RequiresRegister());
if (check->HasUses()) {
locations->SetOut(Location::SameAsFirstInput());
}
}
void InstructionCodeGeneratorMIPS::VisitClinitCheck(HClinitCheck* check) {
// We assume the class is not null.
SlowPathCodeMIPS* slow_path = new (GetGraph()->GetArena()) LoadClassSlowPathMIPS(
check->GetLoadClass(),
check,
check->GetDexPc(),
true);
codegen_->AddSlowPath(slow_path);
GenerateClassInitializationCheck(slow_path,
check->GetLocations()->InAt(0).AsRegister<Register>());
}
void LocationsBuilderMIPS::VisitCompare(HCompare* compare) {
Primitive::Type in_type = compare->InputAt(0)->GetType();
LocationSummary* locations =
new (GetGraph()->GetArena()) LocationSummary(compare, LocationSummary::kNoCall);
switch (in_type) {
case Primitive::kPrimLong:
locations->SetInAt(0, Location::RequiresRegister());
locations->SetInAt(1, Location::RequiresRegister());
// Output overlaps because it is written before doing the low comparison.
locations->SetOut(Location::RequiresRegister(), Location::kOutputOverlap);
break;
case Primitive::kPrimFloat:
case Primitive::kPrimDouble:
locations->SetInAt(0, Location::RequiresFpuRegister());
locations->SetInAt(1, Location::RequiresFpuRegister());
locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
break;
default:
LOG(FATAL) << "Unexpected type for compare operation " << in_type;
}
}
void InstructionCodeGeneratorMIPS::VisitCompare(HCompare* instruction) {
LocationSummary* locations = instruction->GetLocations();
Register res = locations->Out().AsRegister<Register>();
Primitive::Type in_type = instruction->InputAt(0)->GetType();
bool gt_bias = instruction->IsGtBias();
bool isR6 = codegen_->GetInstructionSetFeatures().IsR6();
// 0 if: left == right
// 1 if: left > right
// -1 if: left < right
switch (in_type) {
case Primitive::kPrimLong: {
MipsLabel done;
Register lhs_high = locations->InAt(0).AsRegisterPairHigh<Register>();
Register lhs_low = locations->InAt(0).AsRegisterPairLow<Register>();
Register rhs_high = locations->InAt(1).AsRegisterPairHigh<Register>();
Register rhs_low = locations->InAt(1).AsRegisterPairLow<Register>();
// TODO: more efficient (direct) comparison with a constant.
__ Slt(TMP, lhs_high, rhs_high);
__ Slt(AT, rhs_high, lhs_high); // Inverted: is actually gt.
__ Subu(res, AT, TMP); // Result -1:1:0 for [ <, >, == ].
__ Bnez(res, &done); // If we compared ==, check if lower bits are also equal.
__ Sltu(TMP, lhs_low, rhs_low);
__ Sltu(AT, rhs_low, lhs_low); // Inverted: is actually gt.
__ Subu(res, AT, TMP); // Result -1:1:0 for [ <, >, == ].
__ Bind(&done);
break;
}
case Primitive::kPrimFloat: {
FRegister lhs = locations->InAt(0).AsFpuRegister<FRegister>();
FRegister rhs = locations->InAt(1).AsFpuRegister<FRegister>();
MipsLabel done;
if (isR6) {
__ CmpEqS(FTMP, lhs, rhs);
__ LoadConst32(res, 0);
__ Bc1nez(FTMP, &done);
if (gt_bias) {
__ CmpLtS(FTMP, lhs, rhs);
__ LoadConst32(res, -1);
__ Bc1nez(FTMP, &done);
__ LoadConst32(res, 1);
} else {
__ CmpLtS(FTMP, rhs, lhs);
__ LoadConst32(res, 1);
__ Bc1nez(FTMP, &done);
__ LoadConst32(res, -1);
}
} else {
if (gt_bias) {
__ ColtS(0, lhs, rhs);
__ LoadConst32(res, -1);
__ Bc1t(0, &done);
__ CeqS(0, lhs, rhs);
__ LoadConst32(res, 1);
__ Movt(res, ZERO, 0);
} else {
__ ColtS(0, rhs, lhs);
__ LoadConst32(res, 1);
__ Bc1t(0, &done);
__ CeqS(0, lhs, rhs);
__ LoadConst32(res, -1);
__ Movt(res, ZERO, 0);
}
}
__ Bind(&done);
break;
}
case Primitive::kPrimDouble: {
FRegister lhs = locations->InAt(0).AsFpuRegister<FRegister>();
FRegister rhs = locations->InAt(1).AsFpuRegister<FRegister>();
MipsLabel done;
if (isR6) {
__ CmpEqD(FTMP, lhs, rhs);
__ LoadConst32(res, 0);
__ Bc1nez(FTMP, &done);
if (gt_bias) {
__ CmpLtD(FTMP, lhs, rhs);
__ LoadConst32(res, -1);
__ Bc1nez(FTMP, &done);
__ LoadConst32(res, 1);
} else {
__ CmpLtD(FTMP, rhs, lhs);
__ LoadConst32(res, 1);
__ Bc1nez(FTMP, &done);
__ LoadConst32(res, -1);
}
} else {
if (gt_bias) {
__ ColtD(0, lhs, rhs);
__ LoadConst32(res, -1);
__ Bc1t(0, &done);
__ CeqD(0, lhs, rhs);
__ LoadConst32(res, 1);
__ Movt(res, ZERO, 0);
} else {
__ ColtD(0, rhs, lhs);
__ LoadConst32(res, 1);
__ Bc1t(0, &done);
__ CeqD(0, lhs, rhs);
__ LoadConst32(res, -1);
__ Movt(res, ZERO, 0);
}
}
__ Bind(&done);
break;
}
default:
LOG(FATAL) << "Unimplemented compare type " << in_type;
}
}
void LocationsBuilderMIPS::HandleCondition(HCondition* instruction) {
LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(instruction);
switch (instruction->InputAt(0)->GetType()) {
default:
case Primitive::kPrimLong:
locations->SetInAt(0, Location::RequiresRegister());
locations->SetInAt(1, Location::RegisterOrConstant(instruction->InputAt(1)));
break;
case Primitive::kPrimFloat:
case Primitive::kPrimDouble:
locations->SetInAt(0, Location::RequiresFpuRegister());
locations->SetInAt(1, Location::RequiresFpuRegister());
break;
}
if (!instruction->IsEmittedAtUseSite()) {
locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
}
}
void InstructionCodeGeneratorMIPS::HandleCondition(HCondition* instruction) {
if (instruction->IsEmittedAtUseSite()) {
return;
}
Primitive::Type type = instruction->InputAt(0)->GetType();
LocationSummary* locations = instruction->GetLocations();
Register dst = locations->Out().AsRegister<Register>();
MipsLabel true_label;
switch (type) {
default:
// Integer case.
GenerateIntCompare(instruction->GetCondition(), locations);
return;
case Primitive::kPrimLong:
// TODO: don't use branches.
GenerateLongCompareAndBranch(instruction->GetCondition(), locations, &true_label);
break;
case Primitive::kPrimFloat:
case Primitive::kPrimDouble:
// TODO: don't use branches.
GenerateFpCompareAndBranch(instruction->GetCondition(),
instruction->IsGtBias(),
type,
locations,
&true_label);
break;
}
// Convert the branches into the result.
MipsLabel done;
// False case: result = 0.
__ LoadConst32(dst, 0);
__ B(&done);
// True case: result = 1.
__ Bind(&true_label);
__ LoadConst32(dst, 1);
__ Bind(&done);
}
void InstructionCodeGeneratorMIPS::DivRemOneOrMinusOne(HBinaryOperation* instruction) {
DCHECK(instruction->IsDiv() || instruction->IsRem());
DCHECK_EQ(instruction->GetResultType(), Primitive::kPrimInt);
LocationSummary* locations = instruction->GetLocations();
Location second = locations->InAt(1);
DCHECK(second.IsConstant());
Register out = locations->Out().AsRegister<Register>();
Register dividend = locations->InAt(0).AsRegister<Register>();
int32_t imm = second.GetConstant()->AsIntConstant()->GetValue();
DCHECK(imm == 1 || imm == -1);
if (instruction->IsRem()) {
__ Move(out, ZERO);
} else {
if (imm == -1) {
__ Subu(out, ZERO, dividend);
} else if (out != dividend) {
__ Move(out, dividend);
}
}
}
void InstructionCodeGeneratorMIPS::DivRemByPowerOfTwo(HBinaryOperation* instruction) {
DCHECK(instruction->IsDiv() || instruction->IsRem());
DCHECK_EQ(instruction->GetResultType(), Primitive::kPrimInt);
LocationSummary* locations = instruction->GetLocations();
Location second = locations->InAt(1);
DCHECK(second