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/*
* This file was generated automatically by gen-mterp.py for 'arm64'.
*
* --> DO NOT EDIT <--
*/
/* File: arm64/header.S */
/*
* Copyright (C) 2016 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
Art assembly interpreter notes:
First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't
handle invoke, allows higher-level code to create frame & shadow frame.
Once that's working, support direct entry code & eliminate shadow frame (and
excess locals allocation.
Some (hopefully) temporary ugliness. We'll treat xFP as pointing to the
base of the vreg array within the shadow frame. Access the other fields,
dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue
the shadow frame mechanism of double-storing object references - via xFP &
number_of_vregs_.
*/
/*
ARM64 Runtime register usage conventions.
r0 : w0 is 32-bit return register and x0 is 64-bit.
r0-r7 : Argument registers.
r8-r15 : Caller save registers (used as temporary registers).
r16-r17: Also known as ip0-ip1, respectively. Used as scratch registers by
the linker, by the trampolines and other stubs (the backend uses
these as temporary registers).
r18 : Caller save register (used as temporary register).
r19 : Pointer to thread-local storage.
r20-r29: Callee save registers.
r30 : (lr) is reserved (the link register).
rsp : (sp) is reserved (the stack pointer).
rzr : (zr) is reserved (the zero register).
Floating-point registers
v0-v31
v0 : s0 is return register for singles (32-bit) and d0 for doubles (64-bit).
This is analogous to the C/C++ (hard-float) calling convention.
v0-v7 : Floating-point argument registers in both Dalvik and C/C++ conventions.
Also used as temporary and codegen scratch registers.
v0-v7 and v16-v31 : trashed across C calls.
v8-v15 : bottom 64-bits preserved across C calls (d8-d15 are preserved).
v16-v31: Used as codegen temp/scratch.
v8-v15 : Can be used for promotion.
Must maintain 16-byte stack alignment.
Mterp notes:
The following registers have fixed assignments:
reg nick purpose
x20 xPC interpreted program counter, used for fetching instructions
x21 xFP interpreted frame pointer, used for accessing locals and args
x22 xSELF self (Thread) pointer
x23 xINST first 16-bit code unit of current instruction
x24 xIBASE interpreted instruction base pointer, used for computed goto
x25 xREFS base of object references in shadow frame (ideally, we'll get rid of this later).
x26 wPROFILE jit profile hotness countdown
x16 ip scratch reg
x17 ip2 scratch reg (used by macros)
Macros are provided for common operations. They MUST NOT alter unspecified registers or condition
codes.
*/
/*
* This is a #include, not a %include, because we want the C pre-processor
* to expand the macros into assembler assignment statements.
*/
#include "asm_support.h"
#define MTERP_PROFILE_BRANCHES 1
#define MTERP_LOGGING 0
/* During bringup, we'll use the shadow frame model instead of xFP */
/* single-purpose registers, given names for clarity */
#define xPC x20
#define xFP x21
#define xSELF x22
#define xINST x23
#define wINST w23
#define xIBASE x24
#define xREFS x25
#define wPROFILE w26
#define xPROFILE x26
#define ip x16
#define ip2 x17
/*
* Instead of holding a pointer to the shadow frame, we keep xFP at the base of the vregs. So,
* to access other shadow frame fields, we need to use a backwards offset. Define those here.
*/
#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET)
#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET)
#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET)
#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET)
#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET)
#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET)
#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET)
#define OFF_FP_CODE_ITEM OFF_FP(SHADOWFRAME_CODE_ITEM_OFFSET)
#define OFF_FP_SHADOWFRAME OFF_FP(0)
/*
* "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must
* be done *before* something throws.
*
* It's okay to do this more than once.
*
* NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped
* dex byte codes. However, the rest of the runtime expects dex pc to be an instruction
* offset into the code_items_[] array. For effiency, we will "export" the
* current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC
* to convert to a dex pc when needed.
*/
.macro EXPORT_PC
str xPC, [xFP, #OFF_FP_DEX_PC_PTR]
.endm
/*
* Fetch the next instruction from xPC into wINST. Does not advance xPC.
*/
.macro FETCH_INST
ldrh wINST, [xPC]
.endm
/*
* Fetch the next instruction from the specified offset. Advances xPC
* to point to the next instruction. "_count" is in 16-bit code units.
*
* Because of the limited size of immediate constants on ARM, this is only
* suitable for small forward movements (i.e. don't try to implement "goto"
* with this).
*
* This must come AFTER anything that can throw an exception, or the
* exception catch may miss. (This also implies that it must come after
* EXPORT_PC.)
*/
.macro FETCH_ADVANCE_INST count
ldrh wINST, [xPC, #((\count)*2)]!
.endm
/*
* The operation performed here is similar to FETCH_ADVANCE_INST, except the
* src and dest registers are parameterized (not hard-wired to xPC and xINST).
*/
.macro PREFETCH_ADVANCE_INST dreg, sreg, count
ldrh \dreg, [\sreg, #((\count)*2)]!
.endm
/*
* Similar to FETCH_ADVANCE_INST, but does not update xPC. Used to load
* xINST ahead of possible exception point. Be sure to manually advance xPC
* later.
*/
.macro PREFETCH_INST count
ldrh wINST, [xPC, #((\count)*2)]
.endm
/* Advance xPC by some number of code units. */
.macro ADVANCE count
add xPC, xPC, #((\count)*2)
.endm
/*
* Fetch the next instruction from an offset specified by _reg and advance xPC.
* xPC to point to the next instruction. "_reg" must specify the distance
* in bytes, *not* 16-bit code units, and may be a signed value. Must not set flags.
*
*/
.macro FETCH_ADVANCE_INST_RB reg
add xPC, xPC, \reg, sxtw
ldrh wINST, [xPC]
.endm
/*
* Fetch a half-word code unit from an offset past the current PC. The
* "_count" value is in 16-bit code units. Does not advance xPC.
*
* The "_S" variant works the same but treats the value as signed.
*/
.macro FETCH reg, count
ldrh \reg, [xPC, #((\count)*2)]
.endm
.macro FETCH_S reg, count
ldrsh \reg, [xPC, #((\count)*2)]
.endm
/*
* Fetch one byte from an offset past the current PC. Pass in the same
* "_count" as you would for FETCH, and an additional 0/1 indicating which
* byte of the halfword you want (lo/hi).
*/
.macro FETCH_B reg, count, byte
ldrb \reg, [xPC, #((\count)*2+(\byte))]
.endm
/*
* Put the instruction's opcode field into the specified register.
*/
.macro GET_INST_OPCODE reg
and \reg, xINST, #255
.endm
/*
* Put the prefetched instruction's opcode field into the specified register.
*/
.macro GET_PREFETCHED_OPCODE oreg, ireg
and \oreg, \ireg, #255
.endm
/*
* Begin executing the opcode in _reg. Clobbers reg
*/
.macro GOTO_OPCODE reg
add \reg, xIBASE, \reg, lsl #7
br \reg
.endm
.macro GOTO_OPCODE_BASE base,reg
add \reg, \base, \reg, lsl #7
br \reg
.endm
/*
* Get/set the 32-bit value from a Dalvik register.
*/
.macro GET_VREG reg, vreg
ldr \reg, [xFP, \vreg, uxtw #2]
.endm
.macro SET_VREG reg, vreg
str \reg, [xFP, \vreg, uxtw #2]
str wzr, [xREFS, \vreg, uxtw #2]
.endm
.macro SET_VREG_OBJECT reg, vreg, tmpreg
str \reg, [xFP, \vreg, uxtw #2]
str \reg, [xREFS, \vreg, uxtw #2]
.endm
/*
* Get/set the 64-bit value from a Dalvik register.
* TUNING: can we do better here?
*/
.macro GET_VREG_WIDE reg, vreg
add ip2, xFP, \vreg, lsl #2
ldr \reg, [ip2]
.endm
.macro SET_VREG_WIDE reg, vreg
add ip2, xFP, \vreg, lsl #2
str \reg, [ip2]
add ip2, xREFS, \vreg, lsl #2
str xzr, [ip2]
.endm
/*
* Convert a virtual register index into an address.
*/
.macro VREG_INDEX_TO_ADDR reg, vreg
add \reg, xFP, \vreg, lsl #2 /* WARNING: handle shadow frame vreg zero if store */
.endm
/*
* Refresh handler table.
*/
.macro REFRESH_IBASE
ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET]
.endm
/* File: arm64/entry.S */
/*
* Copyright (C) 2016 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
.text
/*
* Interpreter entry point.
* On entry:
* x0 Thread* self/
* x1 code_item
* x2 ShadowFrame
* x3 JValue* result_register
*
*/
.global ExecuteMterpImpl
.type ExecuteMterpImpl, %function
.balign 16
ExecuteMterpImpl:
.cfi_startproc
stp xPROFILE, x27, [sp, #-80]!
stp xIBASE, xREFS, [sp, #16]
stp xSELF, xINST, [sp, #32]
stp xPC, xFP, [sp, #48]
stp fp, lr, [sp, #64]
add fp, sp, #64
/* Remember the return register */
str x3, [x2, #SHADOWFRAME_RESULT_REGISTER_OFFSET]
/* Remember the code_item */
str x1, [x2, #SHADOWFRAME_CODE_ITEM_OFFSET]
/* set up "named" registers */
mov xSELF, x0
ldr w0, [x2, #SHADOWFRAME_NUMBER_OF_VREGS_OFFSET]
add xFP, x2, #SHADOWFRAME_VREGS_OFFSET // point to vregs.
add xREFS, xFP, w0, lsl #2 // point to reference array in shadow frame
ldr w0, [x2, #SHADOWFRAME_DEX_PC_OFFSET] // Get starting dex_pc.
add xPC, x1, #CODEITEM_INSNS_OFFSET // Point to base of insns[]
add xPC, xPC, w0, lsl #1 // Create direct pointer to 1st dex opcode
EXPORT_PC
/* Starting ibase */
ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET]
/* Set up for backwards branches & osr profiling */
ldr x0, [xFP, #OFF_FP_METHOD]
add x1, xFP, #OFF_FP_SHADOWFRAME
bl MterpSetUpHotnessCountdown
mov wPROFILE, w0 // Starting hotness countdown to xPROFILE
/* start executing the instruction at rPC */
FETCH_INST // load wINST from rPC
GET_INST_OPCODE ip // extract opcode from wINST
GOTO_OPCODE ip // jump to next instruction
/* NOTE: no fallthrough */
.global artMterpAsmInstructionStart
.type artMterpAsmInstructionStart, %function
artMterpAsmInstructionStart = .L_op_nop
.text
/* ------------------------------ */
.balign 128
.L_op_nop: /* 0x00 */
/* File: arm64/op_nop.S */
FETCH_ADVANCE_INST 1 // advance to next instr, load rINST
GET_INST_OPCODE ip // ip<- opcode from rINST
GOTO_OPCODE ip // execute it
/* ------------------------------ */
.balign 128
.L_op_move: /* 0x01 */
/* File: arm64/op_move.S */
/* for move, move-object, long-to-int */
/* op vA, vB */
lsr w1, wINST, #12 // x1<- B from 15:12
ubfx w0, wINST, #8, #4 // x0<- A from 11:8
FETCH_ADVANCE_INST 1 // advance rPC, load wINST
GET_VREG w2, w1 // x2<- fp[B]
GET_INST_OPCODE ip // ip<- opcode from wINST
.if 0
SET_VREG_OBJECT w2, w0 // fp[A]<- x2
.else
SET_VREG w2, w0 // fp[A]<- x2
.endif
GOTO_OPCODE ip // execute next instruction
/* ------------------------------ */
.balign 128
.L_op_move_from16: /* 0x02 */
/* File: arm64/op_move_from16.S */
/* for: move/from16, move-object/from16 */
/* op vAA, vBBBB */
FETCH w1, 1 // r1<- BBBB
lsr w0, wINST, #8 // r0<- AA
FETCH_ADVANCE_INST 2 // advance rPC, load wINST
GET_VREG w2, w1 // r2<- fp[BBBB]
GET_INST_OPCODE ip // extract opcode from wINST
.if 0
SET_VREG_OBJECT w2, w0 // fp[AA]<- r2
.else
SET_VREG w2, w0 // fp[AA]<- r2
.endif
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_move_16: /* 0x03 */
/* File: arm64/op_move_16.S */
/* for: move/16, move-object/16 */
/* op vAAAA, vBBBB */
FETCH w1, 2 // w1<- BBBB
FETCH w0, 1 // w0<- AAAA
FETCH_ADVANCE_INST 3 // advance xPC, load xINST
GET_VREG w2, w1 // w2<- fp[BBBB]
GET_INST_OPCODE ip // extract opcode from xINST
.if 0
SET_VREG_OBJECT w2, w0 // fp[AAAA]<- w2
.else
SET_VREG w2, w0 // fp[AAAA]<- w2
.endif
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_move_wide: /* 0x04 */
/* File: arm64/op_move_wide.S */
/* move-wide vA, vB */
/* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
lsr w3, wINST, #12 // w3<- B
ubfx w2, wINST, #8, #4 // w2<- A
GET_VREG_WIDE x3, w3
FETCH_ADVANCE_INST 1 // advance rPC, load wINST
GET_INST_OPCODE ip // extract opcode from wINST
SET_VREG_WIDE x3, w2
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_move_wide_from16: /* 0x05 */
/* File: arm64/op_move_wide_from16.S */
/* move-wide/from16 vAA, vBBBB */
/* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
FETCH w3, 1 // w3<- BBBB
lsr w2, wINST, #8 // w2<- AA
GET_VREG_WIDE x3, w3
FETCH_ADVANCE_INST 2 // advance rPC, load wINST
GET_INST_OPCODE ip // extract opcode from wINST
SET_VREG_WIDE x3, w2
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_move_wide_16: /* 0x06 */
/* File: arm64/op_move_wide_16.S */
/* move-wide/16 vAAAA, vBBBB */
/* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
FETCH w3, 2 // w3<- BBBB
FETCH w2, 1 // w2<- AAAA
GET_VREG_WIDE x3, w3
FETCH_ADVANCE_INST 3 // advance rPC, load rINST
SET_VREG_WIDE x3, w2
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_move_object: /* 0x07 */
/* File: arm64/op_move_object.S */
/* File: arm64/op_move.S */
/* for move, move-object, long-to-int */
/* op vA, vB */
lsr w1, wINST, #12 // x1<- B from 15:12
ubfx w0, wINST, #8, #4 // x0<- A from 11:8
FETCH_ADVANCE_INST 1 // advance rPC, load wINST
GET_VREG w2, w1 // x2<- fp[B]
GET_INST_OPCODE ip // ip<- opcode from wINST
.if 1
SET_VREG_OBJECT w2, w0 // fp[A]<- x2
.else
SET_VREG w2, w0 // fp[A]<- x2
.endif
GOTO_OPCODE ip // execute next instruction
/* ------------------------------ */
.balign 128
.L_op_move_object_from16: /* 0x08 */
/* File: arm64/op_move_object_from16.S */
/* File: arm64/op_move_from16.S */
/* for: move/from16, move-object/from16 */
/* op vAA, vBBBB */
FETCH w1, 1 // r1<- BBBB
lsr w0, wINST, #8 // r0<- AA
FETCH_ADVANCE_INST 2 // advance rPC, load wINST
GET_VREG w2, w1 // r2<- fp[BBBB]
GET_INST_OPCODE ip // extract opcode from wINST
.if 1
SET_VREG_OBJECT w2, w0 // fp[AA]<- r2
.else
SET_VREG w2, w0 // fp[AA]<- r2
.endif
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_move_object_16: /* 0x09 */
/* File: arm64/op_move_object_16.S */
/* File: arm64/op_move_16.S */
/* for: move/16, move-object/16 */
/* op vAAAA, vBBBB */
FETCH w1, 2 // w1<- BBBB
FETCH w0, 1 // w0<- AAAA
FETCH_ADVANCE_INST 3 // advance xPC, load xINST
GET_VREG w2, w1 // w2<- fp[BBBB]
GET_INST_OPCODE ip // extract opcode from xINST
.if 1
SET_VREG_OBJECT w2, w0 // fp[AAAA]<- w2
.else
SET_VREG w2, w0 // fp[AAAA]<- w2
.endif
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_move_result: /* 0x0a */
/* File: arm64/op_move_result.S */
/* for: move-result, move-result-object */
/* op vAA */
lsr w2, wINST, #8 // r2<- AA
FETCH_ADVANCE_INST 1 // advance rPC, load wINST
ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType.
ldr w0, [x0] // r0 <- result.i.
GET_INST_OPCODE ip // extract opcode from wINST
.if 0
SET_VREG_OBJECT w0, w2, w1 // fp[AA]<- r0
.else
SET_VREG w0, w2 // fp[AA]<- r0
.endif
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_move_result_wide: /* 0x0b */
/* File: arm64/op_move_result_wide.S */
/* for: move-result-wide */
/* op vAA */
lsr w2, wINST, #8 // r2<- AA
FETCH_ADVANCE_INST 1 // advance rPC, load wINST
ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType.
ldr x0, [x0] // r0 <- result.i.
GET_INST_OPCODE ip // extract opcode from wINST
SET_VREG_WIDE x0, x2 // fp[AA]<- r0
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_move_result_object: /* 0x0c */
/* File: arm64/op_move_result_object.S */
/* File: arm64/op_move_result.S */
/* for: move-result, move-result-object */
/* op vAA */
lsr w2, wINST, #8 // r2<- AA
FETCH_ADVANCE_INST 1 // advance rPC, load wINST
ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType.
ldr w0, [x0] // r0 <- result.i.
GET_INST_OPCODE ip // extract opcode from wINST
.if 1
SET_VREG_OBJECT w0, w2, w1 // fp[AA]<- r0
.else
SET_VREG w0, w2 // fp[AA]<- r0
.endif
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_move_exception: /* 0x0d */
/* File: arm64/op_move_exception.S */
/* move-exception vAA */
lsr w2, wINST, #8 // w2<- AA
ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET]
mov x1, #0 // w1<- 0
FETCH_ADVANCE_INST 1 // advance rPC, load rINST
SET_VREG_OBJECT w3, w2 // fp[AA]<- exception obj
GET_INST_OPCODE ip // extract opcode from rINST
str x1, [xSELF, #THREAD_EXCEPTION_OFFSET] // clear exception
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_return_void: /* 0x0e */
/* File: arm64/op_return_void.S */
.extern MterpThreadFenceForConstructor
bl MterpThreadFenceForConstructor
ldr w7, [xSELF, #THREAD_FLAGS_OFFSET]
mov x0, xSELF
ands w7, w7, #(THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
b.ne .Lop_return_void_check
.Lop_return_void_return:
mov x0, #0
b MterpReturn
.Lop_return_void_check:
bl MterpSuspendCheck // (self)
b .Lop_return_void_return
/* ------------------------------ */
.balign 128
.L_op_return: /* 0x0f */
/* File: arm64/op_return.S */
/*
* Return a 32-bit value.
*
* for: return, return-object
*/
/* op vAA */
.extern MterpThreadFenceForConstructor
bl MterpThreadFenceForConstructor
ldr w7, [xSELF, #THREAD_FLAGS_OFFSET]
mov x0, xSELF
ands w7, w7, #(THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
b.ne .Lop_return_check
.Lop_return_return:
lsr w2, wINST, #8 // r2<- AA
GET_VREG w0, w2 // r0<- vAA
b MterpReturn
.Lop_return_check:
bl MterpSuspendCheck // (self)
b .Lop_return_return
/* ------------------------------ */
.balign 128
.L_op_return_wide: /* 0x10 */
/* File: arm64/op_return_wide.S */
/*
* Return a 64-bit value.
*/
/* return-wide vAA */
/* op vAA */
.extern MterpThreadFenceForConstructor
bl MterpThreadFenceForConstructor
ldr w7, [xSELF, #THREAD_FLAGS_OFFSET]
mov x0, xSELF
ands w7, w7, #(THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
b.ne .Lop_return_wide_check
.Lop_return_wide_return:
lsr w2, wINST, #8 // w2<- AA
GET_VREG_WIDE x0, w2 // x0<- vAA
b MterpReturn
.Lop_return_wide_check:
bl MterpSuspendCheck // (self)
b .Lop_return_wide_return
/* ------------------------------ */
.balign 128
.L_op_return_object: /* 0x11 */
/* File: arm64/op_return_object.S */
/* File: arm64/op_return.S */
/*
* Return a 32-bit value.
*
* for: return, return-object
*/
/* op vAA */
.extern MterpThreadFenceForConstructor
bl MterpThreadFenceForConstructor
ldr w7, [xSELF, #THREAD_FLAGS_OFFSET]
mov x0, xSELF
ands w7, w7, #(THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
b.ne .Lop_return_object_check
.Lop_return_object_return:
lsr w2, wINST, #8 // r2<- AA
GET_VREG w0, w2 // r0<- vAA
b MterpReturn
.Lop_return_object_check:
bl MterpSuspendCheck // (self)
b .Lop_return_object_return
/* ------------------------------ */
.balign 128
.L_op_const_4: /* 0x12 */
/* File: arm64/op_const_4.S */
/* const/4 vA, #+B */
lsl w1, wINST, #16 // w1<- Bxxx0000
ubfx w0, wINST, #8, #4 // w0<- A
FETCH_ADVANCE_INST 1 // advance xPC, load wINST
asr w1, w1, #28 // w1<- sssssssB (sign-extended)
GET_INST_OPCODE ip // ip<- opcode from xINST
SET_VREG w1, w0 // fp[A]<- w1
GOTO_OPCODE ip // execute next instruction
/* ------------------------------ */
.balign 128
.L_op_const_16: /* 0x13 */
/* File: arm64/op_const_16.S */
/* const/16 vAA, #+BBBB */
FETCH_S w0, 1 // w0<- ssssBBBB (sign-extended
lsr w3, wINST, #8 // w3<- AA
FETCH_ADVANCE_INST 2 // advance xPC, load wINST
SET_VREG w0, w3 // vAA<- w0
GET_INST_OPCODE ip // extract opcode from wINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_const: /* 0x14 */
/* File: arm64/op_const.S */
/* const vAA, #+BBBBbbbb */
lsr w3, wINST, #8 // w3<- AA
FETCH w0, 1 // w0<- bbbb (low
FETCH w1, 2 // w1<- BBBB (high
FETCH_ADVANCE_INST 3 // advance rPC, load wINST
orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb
GET_INST_OPCODE ip // extract opcode from wINST
SET_VREG w0, w3 // vAA<- w0
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_const_high16: /* 0x15 */
/* File: arm64/op_const_high16.S */
/* const/high16 vAA, #+BBBB0000 */
FETCH w0, 1 // r0<- 0000BBBB (zero-extended
lsr w3, wINST, #8 // r3<- AA
lsl w0, w0, #16 // r0<- BBBB0000
FETCH_ADVANCE_INST 2 // advance rPC, load rINST
SET_VREG w0, w3 // vAA<- r0
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_const_wide_16: /* 0x16 */
/* File: arm64/op_const_wide_16.S */
/* const-wide/16 vAA, #+BBBB */
FETCH_S w0, 1 // w0<- ssssBBBB (sign-extended
lsr w3, wINST, #8 // w3<- AA
FETCH_ADVANCE_INST 2 // advance rPC, load rINST
sbfm x0, x0, 0, 31
GET_INST_OPCODE ip // extract opcode from rINST
SET_VREG_WIDE x0, w3
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_const_wide_32: /* 0x17 */
/* File: arm64/op_const_wide_32.S */
/* const-wide/32 vAA, #+BBBBbbbb */
FETCH w0, 1 // w0<- 0000bbbb (low)
lsr w3, wINST, #8 // w3<- AA
FETCH_S w2, 2 // w2<- ssssBBBB (high)
FETCH_ADVANCE_INST 3 // advance rPC, load wINST
GET_INST_OPCODE ip // extract opcode from wINST
orr w0, w0, w2, lsl #16 // w0<- BBBBbbbb
sbfm x0, x0, 0, 31
SET_VREG_WIDE x0, w3
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_const_wide: /* 0x18 */
/* File: arm64/op_const_wide.S */
/* const-wide vAA, #+HHHHhhhhBBBBbbbb */
FETCH w0, 1 // w0<- bbbb (low)
FETCH w1, 2 // w1<- BBBB (low middle)
FETCH w2, 3 // w2<- hhhh (high middle)
FETCH w3, 4 // w3<- HHHH (high)
lsr w4, wINST, #8 // r4<- AA
FETCH_ADVANCE_INST 5 // advance rPC, load wINST
GET_INST_OPCODE ip // extract opcode from wINST
orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb
orr x0, x0, x2, lsl #32 // w0<- hhhhBBBBbbbb
orr x0, x0, x3, lsl #48 // w0<- HHHHhhhhBBBBbbbb
SET_VREG_WIDE x0, w4
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_const_wide_high16: /* 0x19 */
/* File: arm64/op_const_wide_high16.S */
/* const-wide/high16 vAA, #+BBBB000000000000 */
FETCH w0, 1 // w0<- 0000BBBB (zero-extended)
lsr w1, wINST, #8 // w1<- AA
FETCH_ADVANCE_INST 2 // advance rPC, load wINST
lsl x0, x0, #48
SET_VREG_WIDE x0, w1
GET_INST_OPCODE ip // extract opcode from wINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_const_string: /* 0x1a */
/* File: arm64/op_const_string.S */
/* const/string vAA, String//BBBB */
EXPORT_PC
FETCH w0, 1 // w0<- BBBB
lsr w1, wINST, #8 // w1<- AA
add x2, xFP, #OFF_FP_SHADOWFRAME
mov x3, xSELF
bl MterpConstString // (index, tgt_reg, shadow_frame, self)
PREFETCH_INST 2 // load rINST
cbnz w0, MterpPossibleException // let reference interpreter deal with it.
ADVANCE 2 // advance rPC
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_const_string_jumbo: /* 0x1b */
/* File: arm64/op_const_string_jumbo.S */
/* const/string vAA, String//BBBBBBBB */
EXPORT_PC
FETCH w0, 1 // w0<- bbbb (low
FETCH w2, 2 // w2<- BBBB (high
lsr w1, wINST, #8 // w1<- AA
orr w0, w0, w2, lsl #16 // w1<- BBBBbbbb
add x2, xFP, #OFF_FP_SHADOWFRAME
mov x3, xSELF
bl MterpConstString // (index, tgt_reg, shadow_frame, self)
PREFETCH_INST 3 // advance rPC
cbnz w0, MterpPossibleException // let reference interpreter deal with it.
ADVANCE 3 // advance rPC
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_const_class: /* 0x1c */
/* File: arm64/op_const_class.S */
/* const/class vAA, Class//BBBB */
EXPORT_PC
FETCH w0, 1 // w0<- BBBB
lsr w1, wINST, #8 // w1<- AA
add x2, xFP, #OFF_FP_SHADOWFRAME
mov x3, xSELF
bl MterpConstClass // (index, tgt_reg, shadow_frame, self)
PREFETCH_INST 2
cbnz w0, MterpPossibleException
ADVANCE 2
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_monitor_enter: /* 0x1d */
/* File: arm64/op_monitor_enter.S */
/*
* Synchronize on an object.
*/
/* monitor-enter vAA */
EXPORT_PC
lsr w2, wINST, #8 // w2<- AA
GET_VREG w0, w2 // w0<- vAA (object)
mov x1, xSELF // w1<- self
bl artLockObjectFromCode
cbnz w0, MterpException
FETCH_ADVANCE_INST 1
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_monitor_exit: /* 0x1e */
/* File: arm64/op_monitor_exit.S */
/*
* Unlock an object.
*
* Exceptions that occur when unlocking a monitor need to appear as
* if they happened at the following instruction. See the Dalvik
* instruction spec.
*/
/* monitor-exit vAA */
EXPORT_PC
lsr w2, wINST, #8 // w2<- AA
GET_VREG w0, w2 // w0<- vAA (object)
mov x1, xSELF // w0<- self
bl artUnlockObjectFromCode // w0<- success for unlock(self, obj)
cbnz w0, MterpException
FETCH_ADVANCE_INST 1 // before throw: advance rPC, load rINST
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_check_cast: /* 0x1f */
/* File: arm64/op_check_cast.S */
/*
* Check to see if a cast from one class to another is allowed.
*/
/* check-cast vAA, class//BBBB */
EXPORT_PC
FETCH w0, 1 // w0<- BBBB
lsr w1, wINST, #8 // w1<- AA
VREG_INDEX_TO_ADDR x1, w1 // w1<- &object
ldr x2, [xFP, #OFF_FP_METHOD] // w2<- method
mov x3, xSELF // w3<- self
bl MterpCheckCast // (index, &obj, method, self)
PREFETCH_INST 2
cbnz w0, MterpPossibleException
ADVANCE 2
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_instance_of: /* 0x20 */
/* File: arm64/op_instance_of.S */
/*
* Check to see if an object reference is an instance of a class.
*
* Most common situation is a non-null object, being compared against
* an already-resolved class.
*/
/* instance-of vA, vB, class//CCCC */
EXPORT_PC
FETCH w0, 1 // w0<- CCCC
lsr w1, wINST, #12 // w1<- B
VREG_INDEX_TO_ADDR x1, w1 // w1<- &object
ldr x2, [xFP, #OFF_FP_METHOD] // w2<- method
mov x3, xSELF // w3<- self
bl MterpInstanceOf // (index, &obj, method, self)
ldr x1, [xSELF, #THREAD_EXCEPTION_OFFSET]
lsr w2, wINST, #8 // w2<- A+
and w2, w2, #15 // w2<- A
PREFETCH_INST 2
cbnz x1, MterpException
ADVANCE 2 // advance rPC
SET_VREG w0, w2 // vA<- w0
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_array_length: /* 0x21 */
/* File: arm64/op_array_length.S */
/*
* Return the length of an array.
*/
lsr w1, wINST, #12 // w1<- B
ubfx w2, wINST, #8, #4 // w2<- A
GET_VREG w0, w1 // w0<- vB (object ref)
cbz w0, common_errNullObject // yup, fail
FETCH_ADVANCE_INST 1 // advance rPC, load rINST
ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- array length
GET_INST_OPCODE ip // extract opcode from rINST
SET_VREG w3, w2 // vB<- length
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_new_instance: /* 0x22 */
/* File: arm64/op_new_instance.S */
/*
* Create a new instance of a class.
*/
/* new-instance vAA, class//BBBB */
EXPORT_PC
add x0, xFP, #OFF_FP_SHADOWFRAME
mov x1, xSELF
mov w2, wINST
bl MterpNewInstance // (shadow_frame, self, inst_data)
cbz w0, MterpPossibleException
FETCH_ADVANCE_INST 2 // advance rPC, load rINST
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_new_array: /* 0x23 */
/* File: arm64/op_new_array.S */
/*
* Allocate an array of objects, specified with the array class
* and a count.
*
* The verifier guarantees that this is an array class, so we don't
* check for it here.
*/
/* new-array vA, vB, class//CCCC */
EXPORT_PC
add x0, xFP, #OFF_FP_SHADOWFRAME
mov x1, xPC
mov w2, wINST
mov x3, xSELF
bl MterpNewArray
cbz w0, MterpPossibleException
FETCH_ADVANCE_INST 2 // advance rPC, load rINST
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_filled_new_array: /* 0x24 */
/* File: arm64/op_filled_new_array.S */
/*
* Create a new array with elements filled from registers.
*
* for: filled-new-array, filled-new-array/range
*/
/* op vB, {vD, vE, vF, vG, vA}, class//CCCC */
/* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */
.extern MterpFilledNewArray
EXPORT_PC
add x0, xFP, #OFF_FP_SHADOWFRAME
mov x1, xPC
mov x2, xSELF
bl MterpFilledNewArray
cbz w0, MterpPossibleException
FETCH_ADVANCE_INST 3 // advance rPC, load rINST
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_filled_new_array_range: /* 0x25 */
/* File: arm64/op_filled_new_array_range.S */
/* File: arm64/op_filled_new_array.S */
/*
* Create a new array with elements filled from registers.
*
* for: filled-new-array, filled-new-array/range
*/
/* op vB, {vD, vE, vF, vG, vA}, class//CCCC */
/* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */
.extern MterpFilledNewArrayRange
EXPORT_PC
add x0, xFP, #OFF_FP_SHADOWFRAME
mov x1, xPC
mov x2, xSELF
bl MterpFilledNewArrayRange
cbz w0, MterpPossibleException
FETCH_ADVANCE_INST 3 // advance rPC, load rINST
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_fill_array_data: /* 0x26 */
/* File: arm64/op_fill_array_data.S */
/* fill-array-data vAA, +BBBBBBBB */
EXPORT_PC
FETCH w0, 1 // w0<- bbbb (lo)
FETCH w1, 2 // w1<- BBBB (hi)
lsr w3, wINST, #8 // w3<- AA
orr w1, w0, w1, lsl #16 // w1<- BBBBbbbb
GET_VREG w0, w3 // w0<- vAA (array object)
add x1, xPC, w1, lsl #1 // w1<- PC + BBBBbbbb*2 (array data off.)
bl MterpFillArrayData // (obj, payload)
cbz w0, MterpPossibleException // exception?
FETCH_ADVANCE_INST 3 // advance rPC, load rINST
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_throw: /* 0x27 */
/* File: arm64/op_throw.S */
/*
* Throw an exception object in the current thread.
*/
/* throw vAA */
EXPORT_PC
lsr w2, wINST, #8 // r2<- AA
GET_VREG w1, w2 // r1<- vAA (exception object)
cbz w1, common_errNullObject
str x1, [xSELF, #THREAD_EXCEPTION_OFFSET] // thread->exception<- obj
b MterpException
/* ------------------------------ */
.balign 128
.L_op_goto: /* 0x28 */
/* File: arm64/op_goto.S */
/*
* Unconditional branch, 8-bit offset.
*
* The branch distance is a signed code-unit offset, which we need to
* double to get a byte offset.
*/
/* goto +AA */
sbfx wINST, wINST, #8, #8 // wINST<- ssssssAA (sign-extended)
b MterpCommonTakenBranchNoFlags
/* ------------------------------ */
.balign 128
.L_op_goto_16: /* 0x29 */
/* File: arm64/op_goto_16.S */
/*
* Unconditional branch, 16-bit offset.
*
* The branch distance is a signed code-unit offset, which we need to
* double to get a byte offset.
*/
/* goto/16 +AAAA */
FETCH_S wINST, 1 // wINST<- ssssAAAA (sign-extended)
b MterpCommonTakenBranchNoFlags
/* ------------------------------ */
.balign 128
.L_op_goto_32: /* 0x2a */
/* File: arm64/op_goto_32.S */
/*
* Unconditional branch, 32-bit offset.
*
* The branch distance is a signed code-unit offset, which we need to
* double to get a byte offset.
*
* Unlike most opcodes, this one is allowed to branch to itself, so
* our "backward branch" test must be "<=0" instead of "<0". Because
* we need the V bit set, we'll use an adds to convert from Dalvik
* offset to byte offset.
*/
/* goto/32 +AAAAAAAA */
FETCH w0, 1 // w0<- aaaa (lo)
FETCH w1, 2 // w1<- AAAA (hi)
orr wINST, w0, w1, lsl #16 // wINST<- AAAAaaaa
b MterpCommonTakenBranchNoFlags
/* ------------------------------ */
.balign 128
.L_op_packed_switch: /* 0x2b */
/* File: arm64/op_packed_switch.S */
/*
* Handle a packed-switch or sparse-switch instruction. In both cases
* we decode it and hand it off to a helper function.
*
* We don't really expect backward branches in a switch statement, but
* they're perfectly legal, so we check for them here.
*
* for: packed-switch, sparse-switch
*/
/* op vAA, +BBBB */
FETCH w0, 1 // w0<- bbbb (lo)
FETCH w1, 2 // w1<- BBBB (hi)
lsr w3, wINST, #8 // w3<- AA
orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb
GET_VREG w1, w3 // w1<- vAA
add x0, xPC, w0, lsl #1 // w0<- PC + BBBBbbbb*2
bl MterpDoPackedSwitch // w0<- code-unit branch offset
sbfm xINST, x0, 0, 31
b MterpCommonTakenBranchNoFlags
/* ------------------------------ */
.balign 128
.L_op_sparse_switch: /* 0x2c */
/* File: arm64/op_sparse_switch.S */
/* File: arm64/op_packed_switch.S */
/*
* Handle a packed-switch or sparse-switch instruction. In both cases
* we decode it and hand it off to a helper function.
*
* We don't really expect backward branches in a switch statement, but
* they're perfectly legal, so we check for them here.
*
* for: packed-switch, sparse-switch
*/
/* op vAA, +BBBB */
FETCH w0, 1 // w0<- bbbb (lo)
FETCH w1, 2 // w1<- BBBB (hi)
lsr w3, wINST, #8 // w3<- AA
orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb
GET_VREG w1, w3 // w1<- vAA
add x0, xPC, w0, lsl #1 // w0<- PC + BBBBbbbb*2
bl MterpDoSparseSwitch // w0<- code-unit branch offset
sbfm xINST, x0, 0, 31
b MterpCommonTakenBranchNoFlags
/* ------------------------------ */
.balign 128
.L_op_cmpl_float: /* 0x2d */
/* File: arm64/op_cmpl_float.S */
/* File: arm64/fcmp.S */
/*
* Compare two floating-point values. Puts 0, 1, or -1 into the
* destination register based on the results of the comparison.
*/
/* op vAA, vBB, vCC */
FETCH w0, 1 // w0<- CCBB
lsr w4, wINST, #8 // w4<- AA
and w2, w0, #255 // w2<- BB
lsr w3, w0, #8 // w3<- CC
GET_VREG s1, w2
GET_VREG s2, w3
mov w0, #-1
fcmp s1, s2
csneg w0, w0, w0, le
csel w0, wzr, w0, eq
FETCH_ADVANCE_INST 2 // advance rPC, load rINST
GET_INST_OPCODE ip // extract opcode from rINST
SET_VREG w0, w4 // vAA<- w0
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_cmpg_float: /* 0x2e */
/* File: arm64/op_cmpg_float.S */
/* File: arm64/fcmp.S */
/*
* Compare two floating-point values. Puts 0, 1, or -1 into the
* destination register based on the results of the comparison.
*/
/* op vAA, vBB, vCC */
FETCH w0, 1 // w0<- CCBB
lsr w4, wINST, #8 // w4<- AA
and w2, w0, #255 // w2<- BB
lsr w3, w0, #8 // w3<- CC
GET_VREG s1, w2
GET_VREG s2, w3
mov w0, #1
fcmp s1, s2
csneg w0, w0, w0, pl
csel w0, wzr, w0, eq
FETCH_ADVANCE_INST 2 // advance rPC, load rINST
GET_INST_OPCODE ip // extract opcode from rINST
SET_VREG w0, w4 // vAA<- w0
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_cmpl_double: /* 0x2f */
/* File: arm64/op_cmpl_double.S */
/* File: arm64/fcmp.S */
/*
* Compare two floating-point values. Puts 0, 1, or -1 into the
* destination register based on the results of the comparison.
*/
/* op vAA, vBB, vCC */
FETCH w0, 1 // w0<- CCBB
lsr w4, wINST, #8 // w4<- AA
and w2, w0, #255 // w2<- BB
lsr w3, w0, #8 // w3<- CC
GET_VREG_WIDE d1, w2
GET_VREG_WIDE d2, w3
mov w0, #-1
fcmp d1, d2
csneg w0, w0, w0, le
csel w0, wzr, w0, eq
FETCH_ADVANCE_INST 2 // advance rPC, load rINST
GET_INST_OPCODE ip // extract opcode from rINST
SET_VREG w0, w4 // vAA<- w0
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_cmpg_double: /* 0x30 */
/* File: arm64/op_cmpg_double.S */
/* File: arm64/fcmp.S */
/*
* Compare two floating-point values. Puts 0, 1, or -1 into the
* destination register based on the results of the comparison.
*/
/* op vAA, vBB, vCC */
FETCH w0, 1 // w0<- CCBB
lsr w4, wINST, #8 // w4<- AA
and w2, w0, #255 // w2<- BB
lsr w3, w0, #8 // w3<- CC
GET_VREG_WIDE d1, w2
GET_VREG_WIDE d2, w3
mov w0, #1
fcmp d1, d2
csneg w0, w0, w0, pl
csel w0, wzr, w0, eq
FETCH_ADVANCE_INST 2 // advance rPC, load rINST
GET_INST_OPCODE ip // extract opcode from rINST
SET_VREG w0, w4 // vAA<- w0
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_cmp_long: /* 0x31 */
/* File: arm64/op_cmp_long.S */
FETCH w0, 1 // w0<- CCBB
lsr w4, wINST, #8 // w4<- AA
and w2, w0, #255 // w2<- BB
lsr w3, w0, #8 // w3<- CC
GET_VREG_WIDE x1, w2
GET_VREG_WIDE x2, w3
cmp x1, x2
csinc w0, wzr, wzr, eq
csneg w0, w0, w0, ge
FETCH_ADVANCE_INST 2 // advance rPC, load wINST
SET_VREG w0, w4
GET_INST_OPCODE ip // extract opcode from wINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_if_eq: /* 0x32 */
/* File: arm64/op_if_eq.S */
/* File: arm64/bincmp.S */
/*
* Generic two-operand compare-and-branch operation. Provide a "condition"
* fragment that specifies the comparison to perform.
*
* For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
*/
/* if-cmp vA, vB, +CCCC */
lsr w1, wINST, #12 // w1<- B
ubfx w0, wINST, #8, #4 // w0<- A
GET_VREG w3, w1 // w3<- vB
GET_VREG w2, w0 // w2<- vA
FETCH_S wINST, 1 // wINST<- branch offset, in code units
cmp w2, w3 // compare (vA, vB)
b.eq MterpCommonTakenBranchNoFlags
cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry?
b.eq .L_check_not_taken_osr
FETCH_ADVANCE_INST 2
GET_INST_OPCODE ip // extract opcode from wINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_if_ne: /* 0x33 */
/* File: arm64/op_if_ne.S */
/* File: arm64/bincmp.S */
/*
* Generic two-operand compare-and-branch operation. Provide a "condition"
* fragment that specifies the comparison to perform.
*
* For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
*/
/* if-cmp vA, vB, +CCCC */
lsr w1, wINST, #12 // w1<- B
ubfx w0, wINST, #8, #4 // w0<- A
GET_VREG w3, w1 // w3<- vB
GET_VREG w2, w0 // w2<- vA
FETCH_S wINST, 1 // wINST<- branch offset, in code units
cmp w2, w3 // compare (vA, vB)
b.ne MterpCommonTakenBranchNoFlags
cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry?
b.eq .L_check_not_taken_osr
FETCH_ADVANCE_INST 2
GET_INST_OPCODE ip // extract opcode from wINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_if_lt: /* 0x34 */
/* File: arm64/op_if_lt.S */
/* File: arm64/bincmp.S */
/*
* Generic two-operand compare-and-branch operation. Provide a "condition"
* fragment that specifies the comparison to perform.
*
* For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
*/
/* if-cmp vA, vB, +CCCC */
lsr w1, wINST, #12 // w1<- B
ubfx w0, wINST, #8, #4 // w0<- A
GET_VREG w3, w1 // w3<- vB
GET_VREG w2, w0 // w2<- vA
FETCH_S wINST, 1 // wINST<- branch offset, in code units
cmp w2, w3 // compare (vA, vB)
b.lt MterpCommonTakenBranchNoFlags
cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry?
b.eq .L_check_not_taken_osr
FETCH_ADVANCE_INST 2
GET_INST_OPCODE ip // extract opcode from wINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_if_ge: /* 0x35 */
/* File: arm64/op_if_ge.S */
/* File: arm64/bincmp.S */
/*
* Generic two-operand compare-and-branch operation. Provide a "condition"
* fragment that specifies the comparison to perform.
*
* For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
*/
/* if-cmp vA, vB, +CCCC */
lsr w1, wINST, #12 // w1<- B
ubfx w0, wINST, #8, #4 // w0<- A
GET_VREG w3, w1 // w3<- vB
GET_VREG w2, w0 // w2<- vA
FETCH_S wINST, 1 // wINST<- branch offset, in code units
cmp w2, w3 // compare (vA, vB)
b.ge MterpCommonTakenBranchNoFlags
cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry?
b.eq .L_check_not_taken_osr
FETCH_ADVANCE_INST 2
GET_INST_OPCODE ip // extract opcode from wINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_if_gt: /* 0x36 */
/* File: arm64/op_if_gt.S */
/* File: arm64/bincmp.S */
/*
* Generic two-operand compare-and-branch operation. Provide a "condition"
* fragment that specifies the comparison to perform.
*
* For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
*/
/* if-cmp vA, vB, +CCCC */
lsr w1, wINST, #12 // w1<- B
ubfx w0, wINST, #8, #4 // w0<- A
GET_VREG w3, w1 // w3<- vB
GET_VREG w2, w0 // w2<- vA
FETCH_S wINST, 1 // wINST<- branch offset, in code units
cmp w2, w3 // compare (vA, vB)
b.gt MterpCommonTakenBranchNoFlags
cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry?
b.eq .L_check_not_taken_osr
FETCH_ADVANCE_INST 2
GET_INST_OPCODE ip // extract opcode from wINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_if_le: /* 0x37 */
/* File: arm64/op_if_le.S */
/* File: arm64/bincmp.S */
/*
* Generic two-operand compare-and-branch operation. Provide a "condition"
* fragment that specifies the comparison to perform.
*
* For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
*/
/* if-cmp vA, vB, +CCCC */
lsr w1, wINST, #12 // w1<- B
ubfx w0, wINST, #8, #4 // w0<- A
GET_VREG w3, w1 // w3<- vB
GET_VREG w2, w0 // w2<- vA
FETCH_S wINST, 1 // wINST<- branch offset, in code units
cmp w2, w3 // compare (vA, vB)
b.le MterpCommonTakenBranchNoFlags
cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry?
b.eq .L_check_not_taken_osr
FETCH_ADVANCE_INST 2
GET_INST_OPCODE ip // extract opcode from wINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_if_eqz: /* 0x38 */
/* File: arm64/op_if_eqz.S */
/* File: arm64/zcmp.S */
/*
* Generic one-operand compare-and-branch operation. Provide a "condition"
* fragment that specifies the comparison to perform.
*
* for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
*/
/* if-cmp vAA, +BBBB */
lsr w0, wINST, #8 // w0<- AA
GET_VREG w2, w0 // w2<- vAA
FETCH_S wINST, 1 // w1<- branch offset, in code units
cmp w2, #0 // compare (vA, 0)
b.eq MterpCommonTakenBranchNoFlags
cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry?
b.eq .L_check_not_taken_osr
FETCH_ADVANCE_INST 2
GET_INST_OPCODE ip // extract opcode from wINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_if_nez: /* 0x39 */
/* File: arm64/op_if_nez.S */
/* File: arm64/zcmp.S */
/*
* Generic one-operand compare-and-branch operation. Provide a "condition"
* fragment that specifies the comparison to perform.
*
* for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
*/
/* if-cmp vAA, +BBBB */
lsr w0, wINST, #8 // w0<- AA
GET_VREG w2, w0 // w2<- vAA
FETCH_S wINST, 1 // w1<- branch offset, in code units
cmp w2, #0 // compare (vA, 0)
b.ne MterpCommonTakenBranchNoFlags
cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry?
b.eq .L_check_not_taken_osr
FETCH_ADVANCE_INST 2
GET_INST_OPCODE ip // extract opcode from wINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_if_ltz: /* 0x3a */
/* File: arm64/op_if_ltz.S */
/* File: arm64/zcmp.S */
/*
* Generic one-operand compare-and-branch operation. Provide a "condition"
* fragment that specifies the comparison to perform.
*
* for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
*/
/* if-cmp vAA, +BBBB */
lsr w0, wINST, #8 // w0<- AA
GET_VREG w2, w0 // w2<- vAA
FETCH_S wINST, 1 // w1<- branch offset, in code units
cmp w2, #0 // compare (vA, 0)
b.lt MterpCommonTakenBranchNoFlags
cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry?
b.eq .L_check_not_taken_osr
FETCH_ADVANCE_INST 2
GET_INST_OPCODE ip // extract opcode from wINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_if_gez: /* 0x3b */
/* File: arm64/op_if_gez.S */
/* File: arm64/zcmp.S */
/*
* Generic one-operand compare-and-branch operation. Provide a "condition"
* fragment that specifies the comparison to perform.
*
* for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
*/
/* if-cmp vAA, +BBBB */
lsr w0, wINST, #8 // w0<- AA
GET_VREG w2, w0 // w2<- vAA
FETCH_S wINST, 1 // w1<- branch offset, in code units
cmp w2, #0 // compare (vA, 0)
b.ge MterpCommonTakenBranchNoFlags
cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry?
b.eq .L_check_not_taken_osr
FETCH_ADVANCE_INST 2
GET_INST_OPCODE ip // extract opcode from wINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_if_gtz: /* 0x3c */
/* File: arm64/op_if_gtz.S */
/* File: arm64/zcmp.S */
/*
* Generic one-operand compare-and-branch operation. Provide a "condition"
* fragment that specifies the comparison to perform.
*
* for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
*/
/* if-cmp vAA, +BBBB */
lsr w0, wINST, #8 // w0<- AA
GET_VREG w2, w0 // w2<- vAA
FETCH_S wINST, 1 // w1<- branch offset, in code units
cmp w2, #0 // compare (vA, 0)
b.gt MterpCommonTakenBranchNoFlags
cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry?
b.eq .L_check_not_taken_osr
FETCH_ADVANCE_INST 2
GET_INST_OPCODE ip // extract opcode from wINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_if_lez: /* 0x3d */
/* File: arm64/op_if_lez.S */
/* File: arm64/zcmp.S */
/*
* Generic one-operand compare-and-branch operation. Provide a "condition"
* fragment that specifies the comparison to perform.
*
* for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
*/
/* if-cmp vAA, +BBBB */
lsr w0, wINST, #8 // w0<- AA
GET_VREG w2, w0 // w2<- vAA
FETCH_S wINST, 1 // w1<- branch offset, in code units
cmp w2, #0 // compare (vA, 0)
b.le MterpCommonTakenBranchNoFlags
cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry?
b.eq .L_check_not_taken_osr
FETCH_ADVANCE_INST 2
GET_INST_OPCODE ip // extract opcode from wINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_unused_3e: /* 0x3e */
/* File: arm64/op_unused_3e.S */
/* File: arm64/unused.S */
/*
* Bail to reference interpreter to throw.
*/
b MterpFallback
/* ------------------------------ */
.balign 128
.L_op_unused_3f: /* 0x3f */
/* File: arm64/op_unused_3f.S */
/* File: arm64/unused.S */
/*
* Bail to reference interpreter to throw.
*/
b MterpFallback
/* ------------------------------ */
.balign 128
.L_op_unused_40: /* 0x40 */
/* File: arm64/op_unused_40.S */
/* File: arm64/unused.S */
/*
* Bail to reference interpreter to throw.
*/
b MterpFallback
/* ------------------------------ */
.balign 128
.L_op_unused_41: /* 0x41 */
/* File: arm64/op_unused_41.S */
/* File: arm64/unused.S */
/*
* Bail to reference interpreter to throw.
*/
b MterpFallback
/* ------------------------------ */
.balign 128
.L_op_unused_42: /* 0x42 */
/* File: arm64/op_unused_42.S */
/* File: arm64/unused.S */
/*
* Bail to reference interpreter to throw.
*/
b MterpFallback
/* ------------------------------ */
.balign 128
.L_op_unused_43: /* 0x43 */
/* File: arm64/op_unused_43.S */
/* File: arm64/unused.S */
/*
* Bail to reference interpreter to throw.
*/
b MterpFallback
/* ------------------------------ */
.balign 128
.L_op_aget: /* 0x44 */
/* File: arm64/op_aget.S */
/*
* Array get, 32 bits or less. vAA <- vBB[vCC].
*
* Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
* instructions. We use a pair of FETCH_Bs instead.
*
* for: aget, aget-boolean, aget-byte, aget-char, aget-short
*
* NOTE: assumes data offset for arrays is the same for all non-wide types.
* If this changes, specialize.
*/
/* op vAA, vBB, vCC */
FETCH_B w2, 1, 0 // w2<- BB
lsr w9, wINST, #8 // w9<- AA
FETCH_B w3, 1, 1 // w3<- CC
GET_VREG w0, w2 // w0<- vBB (array object)
GET_VREG w1, w3 // w1<- vCC (requested index)
cbz x0, common_errNullObject // bail if null array object.
ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length
add x0, x0, w1, uxtw #2 // w0<- arrayObj + index*width
cmp w1, w3 // compare unsigned index, length
bcs common_errArrayIndex // index >= length, bail
FETCH_ADVANCE_INST 2 // advance rPC, load rINST
ldr w2, [x0, #MIRROR_INT_ARRAY_DATA_OFFSET] // w2<- vBB[vCC]
GET_INST_OPCODE ip // extract opcode from rINST
SET_VREG w2, w9 // vAA<- w2
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_aget_wide: /* 0x45 */
/* File: arm64/op_aget_wide.S */
/*
* Array get, 64 bits. vAA <- vBB[vCC].
*
*/
/* aget-wide vAA, vBB, vCC */
FETCH w0, 1 // w0<- CCBB
lsr w4, wINST, #8 // w4<- AA
and w2, w0, #255 // w2<- BB
lsr w3, w0, #8 // w3<- CC
GET_VREG w0, w2 // w0<- vBB (array object)
GET_VREG w1, w3 // w1<- vCC (requested index)
cbz w0, common_errNullObject // yes, bail
ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length
add x0, x0, w1, lsl #3 // w0<- arrayObj + index*width
cmp w1, w3 // compare unsigned index, length
bcs common_errArrayIndex // index >= length, bail
FETCH_ADVANCE_INST 2 // advance rPC, load wINST
ldr x2, [x0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] // x2<- vBB[vCC]
GET_INST_OPCODE ip // extract opcode from wINST
SET_VREG_WIDE x2, w4
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_aget_object: /* 0x46 */
/* File: arm64/op_aget_object.S */
/*
* Array object get. vAA <- vBB[vCC].
*
* for: aget-object
*/
/* op vAA, vBB, vCC */
FETCH_B w2, 1, 0 // w2<- BB
FETCH_B w3, 1, 1 // w3<- CC
EXPORT_PC
GET_VREG w0, w2 // w0<- vBB (array object)
GET_VREG w1, w3 // w1<- vCC (requested index)
bl artAGetObjectFromMterp // (array, index)
ldr x1, [xSELF, #THREAD_EXCEPTION_OFFSET]
lsr w2, wINST, #8 // w9<- AA
PREFETCH_INST 2
cbnz w1, MterpException
SET_VREG_OBJECT w0, w2
ADVANCE 2
GET_INST_OPCODE ip
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_aget_boolean: /* 0x47 */
/* File: arm64/op_aget_boolean.S */
/* File: arm64/op_aget.S */
/*
* Array get, 32 bits or less. vAA <- vBB[vCC].
*
* Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
* instructions. We use a pair of FETCH_Bs instead.
*
* for: aget, aget-boolean, aget-byte, aget-char, aget-short
*
* NOTE: assumes data offset for arrays is the same for all non-wide types.
* If this changes, specialize.
*/
/* op vAA, vBB, vCC */
FETCH_B w2, 1, 0 // w2<- BB
lsr w9, wINST, #8 // w9<- AA
FETCH_B w3, 1, 1 // w3<- CC
GET_VREG w0, w2 // w0<- vBB (array object)
GET_VREG w1, w3 // w1<- vCC (requested index)
cbz x0, common_errNullObject // bail if null array object.
ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length
add x0, x0, w1, uxtw #0 // w0<- arrayObj + index*width
cmp w1, w3 // compare unsigned index, length
bcs common_errArrayIndex // index >= length, bail
FETCH_ADVANCE_INST 2 // advance rPC, load rINST
ldrb w2, [x0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] // w2<- vBB[vCC]
GET_INST_OPCODE ip // extract opcode from rINST
SET_VREG w2, w9 // vAA<- w2
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_aget_byte: /* 0x48 */
/* File: arm64/op_aget_byte.S */
/* File: arm64/op_aget.S */
/*
* Array get, 32 bits or less. vAA <- vBB[vCC].
*
* Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
* instructions. We use a pair of FETCH_Bs instead.
*
* for: aget, aget-boolean, aget-byte, aget-char, aget-short
*
* NOTE: assumes data offset for arrays is the same for all non-wide types.
* If this changes, specialize.
*/
/* op vAA, vBB, vCC */
FETCH_B w2, 1, 0 // w2<- BB
lsr w9, wINST, #8 // w9<- AA
FETCH_B w3, 1, 1 // w3<- CC
GET_VREG w0, w2 // w0<- vBB (array object)
GET_VREG w1, w3 // w1<- vCC (requested index)
cbz x0, common_errNullObject // bail if null array object.
ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length
add x0, x0, w1, uxtw #0 // w0<- arrayObj + index*width
cmp w1, w3 // compare unsigned index, length
bcs common_errArrayIndex // index >= length, bail
FETCH_ADVANCE_INST 2 // advance rPC, load rINST
ldrsb w2, [x0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] // w2<- vBB[vCC]
GET_INST_OPCODE ip // extract opcode from rINST
SET_VREG w2, w9 // vAA<- w2
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_aget_char: /* 0x49 */
/* File: arm64/op_aget_char.S */
/* File: arm64/op_aget.S */
/*
* Array get, 32 bits or less. vAA <- vBB[vCC].
*
* Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
* instructions. We use a pair of FETCH_Bs instead.
*
* for: aget, aget-boolean, aget-byte, aget-char, aget-short
*
* NOTE: assumes data offset for arrays is the same for all non-wide types.
* If this changes, specialize.
*/
/* op vAA, vBB, vCC */
FETCH_B w2, 1, 0 // w2<- BB
lsr w9, wINST, #8 // w9<- AA
FETCH_B w3, 1, 1 // w3<- CC
GET_VREG w0, w2 // w0<- vBB (array object)
GET_VREG w1, w3 // w1<- vCC (requested index)
cbz x0, common_errNullObject // bail if null array object.
ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length
add x0, x0, w1, uxtw #1 // w0<- arrayObj + index*width
cmp w1, w3 // compare unsigned index, length
bcs common_errArrayIndex // index >= length, bail
FETCH_ADVANCE_INST 2 // advance rPC, load rINST
ldrh w2, [x0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] // w2<- vBB[vCC]
GET_INST_OPCODE ip // extract opcode from rINST
SET_VREG w2, w9 // vAA<- w2
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_aget_short: /* 0x4a */
/* File: arm64/op_aget_short.S */
/* File: arm64/op_aget.S */
/*
* Array get, 32 bits or less. vAA <- vBB[vCC].
*
* Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
* instructions. We use a pair of FETCH_Bs instead.
*
* for: aget, aget-boolean, aget-byte, aget-char, aget-short
*
* NOTE: assumes data offset for arrays is the same for all non-wide types.
* If this changes, specialize.
*/
/* op vAA, vBB, vCC */
FETCH_B w2, 1, 0 // w2<- BB
lsr w9, wINST, #8 // w9<- AA
FETCH_B w3, 1, 1 // w3<- CC
GET_VREG w0, w2 // w0<- vBB (array object)
GET_VREG w1, w3 // w1<- vCC (requested index)
cbz x0, common_errNullObject // bail if null array object.
ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length
add x0, x0, w1, uxtw #1 // w0<- arrayObj + index*width
cmp w1, w3 // compare unsigned index, length
bcs common_errArrayIndex // index >= length, bail
FETCH_ADVANCE_INST 2 // advance rPC, load rINST
ldrsh w2, [x0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] // w2<- vBB[vCC]
GET_INST_OPCODE ip // extract opcode from rINST
SET_VREG w2, w9 // vAA<- w2
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_aput: /* 0x4b */
/* File: arm64/op_aput.S */
/*
* Array put, 32 bits or less. vBB[vCC] <- vAA.
*
* Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
* instructions. We use a pair of FETCH_Bs instead.
*
* for: aput, aput-boolean, aput-byte, aput-char, aput-short
*
* NOTE: this assumes data offset for arrays is the same for all non-wide types.
* If this changes, specialize.
*/
/* op vAA, vBB, vCC */
FETCH_B w2, 1, 0 // w2<- BB
lsr w9, wINST, #8 // w9<- AA
FETCH_B w3, 1, 1 // w3<- CC
GET_VREG w0, w2 // w0<- vBB (array object)
GET_VREG w1, w3 // w1<- vCC (requested index)
cbz w0, common_errNullObject // bail if null
ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length
add x0, x0, w1, lsl #2 // w0<- arrayObj + index*width
cmp w1, w3 // compare unsigned index, length
bcs common_errArrayIndex // index >= length, bail
FETCH_ADVANCE_INST 2 // advance rPC, load rINST
GET_VREG w2, w9 // w2<- vAA
GET_INST_OPCODE ip // extract opcode from rINST
str w2, [x0, #MIRROR_INT_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_aput_wide: /* 0x4c */
/* File: arm64/op_aput_wide.S */
/*
* Array put, 64 bits. vBB[vCC] <- vAA.
*
*/
/* aput-wide vAA, vBB, vCC */
FETCH w0, 1 // w0<- CCBB
lsr w4, wINST, #8 // w4<- AA
and w2, w0, #255 // w2<- BB
lsr w3, w0, #8 // w3<- CC
GET_VREG w0, w2 // w0<- vBB (array object)
GET_VREG w1, w3 // w1<- vCC (requested index)
cbz w0, common_errNullObject // bail if null
ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length
add x0, x0, w1, lsl #3 // w0<- arrayObj + index*width
cmp w1, w3 // compare unsigned index, length
bcs common_errArrayIndex // index >= length, bail
GET_VREG_WIDE x1, w4
FETCH_ADVANCE_INST 2 // advance rPC, load wINST
GET_INST_OPCODE ip // extract opcode from wINST
str x1, [x0, #MIRROR_WIDE_ARRAY_DATA_OFFSET]
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_aput_object: /* 0x4d */
/* File: arm64/op_aput_object.S */
/*
* Store an object into an array. vBB[vCC] <- vAA.
*/
/* op vAA, vBB, vCC */
EXPORT_PC
add x0, xFP, #OFF_FP_SHADOWFRAME
mov x1, xPC
mov w2, wINST
bl MterpAputObject
cbz w0, MterpPossibleException
FETCH_ADVANCE_INST 2 // advance rPC, load rINST
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_aput_boolean: /* 0x4e */
/* File: arm64/op_aput_boolean.S */
/* File: arm64/op_aput.S */
/*
* Array put, 32 bits or less. vBB[vCC] <- vAA.
*
* Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
* instructions. We use a pair of FETCH_Bs instead.
*
* for: aput, aput-boolean, aput-byte, aput-char, aput-short
*
* NOTE: this assumes data offset for arrays is the same for all non-wide types.
* If this changes, specialize.
*/
/* op vAA, vBB, vCC */
FETCH_B w2, 1, 0 // w2<- BB
lsr w9, wINST, #8 // w9<- AA
FETCH_B w3, 1, 1 // w3<- CC
GET_VREG w0, w2 // w0<- vBB (array object)
GET_VREG w1, w3 // w1<- vCC (requested index)
cbz w0, common_errNullObject // bail if null
ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length
add x0, x0, w1, lsl #0 // w0<- arrayObj + index*width
cmp w1, w3 // compare unsigned index, length
bcs common_errArrayIndex // index >= length, bail
FETCH_ADVANCE_INST 2 // advance rPC, load rINST
GET_VREG w2, w9 // w2<- vAA
GET_INST_OPCODE ip // extract opcode from rINST
strb w2, [x0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_aput_byte: /* 0x4f */
/* File: arm64/op_aput_byte.S */
/* File: arm64/op_aput.S */
/*
* Array put, 32 bits or less. vBB[vCC] <- vAA.
*
* Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
* instructions. We use a pair of FETCH_Bs instead.
*
* for: aput, aput-boolean, aput-byte, aput-char, aput-short
*
* NOTE: this assumes data offset for arrays is the same for all non-wide types.
* If this changes, specialize.
*/
/* op vAA, vBB, vCC */
FETCH_B w2, 1, 0 // w2<- BB
lsr w9, wINST, #8 // w9<- AA
FETCH_B w3, 1, 1 // w3<- CC
GET_VREG w0, w2 // w0<- vBB (array object)
GET_VREG w1, w3 // w1<- vCC (requested index)
cbz w0, common_errNullObject // bail if null
ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length
add x0, x0, w1, lsl #0 // w0<- arrayObj + index*width
cmp w1, w3 // compare unsigned index, length
bcs common_errArrayIndex // index >= length, bail
FETCH_ADVANCE_INST 2 // advance rPC, load rINST
GET_VREG w2, w9 // w2<- vAA
GET_INST_OPCODE ip // extract opcode from rINST
strb w2, [x0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_aput_char: /* 0x50 */
/* File: arm64/op_aput_char.S */
/* File: arm64/op_aput.S */
/*
* Array put, 32 bits or less. vBB[vCC] <- vAA.
*
* Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
* instructions. We use a pair of FETCH_Bs instead.
*
* for: aput, aput-boolean, aput-byte, aput-char, aput-short
*
* NOTE: this assumes data offset for arrays is the same for all non-wide types.
* If this changes, specialize.
*/
/* op vAA, vBB, vCC */
FETCH_B w2, 1, 0 // w2<- BB
lsr w9, wINST, #8 // w9<- AA
FETCH_B w3, 1, 1 // w3<- CC
GET_VREG w0, w2 // w0<- vBB (array object)
GET_VREG w1, w3 // w1<- vCC (requested index)
cbz w0, common_errNullObject // bail if null
ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length
add x0, x0, w1, lsl #1 // w0<- arrayObj + index*width
cmp w1, w3 // compare unsigned index, length
bcs common_errArrayIndex // index >= length, bail
FETCH_ADVANCE_INST 2 // advance rPC, load rINST
GET_VREG w2, w9 // w2<- vAA
GET_INST_OPCODE ip // extract opcode from rINST
strh w2, [x0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_aput_short: /* 0x51 */
/* File: arm64/op_aput_short.S */
/* File: arm64/op_aput.S */
/*
* Array put, 32 bits or less. vBB[vCC] <- vAA.
*
* Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
* instructions. We use a pair of FETCH_Bs instead.
*
* for: aput, aput-boolean, aput-byte, aput-char, aput-short
*
* NOTE: this assumes data offset for arrays is the same for all non-wide types.
* If this changes, specialize.
*/
/* op vAA, vBB, vCC */
FETCH_B w2, 1, 0 // w2<- BB
lsr w9, wINST, #8 // w9<- AA
FETCH_B w3, 1, 1 // w3<- CC
GET_VREG w0, w2 // w0<- vBB (array object)
GET_VREG w1, w3 // w1<- vCC (requested index)
cbz w0, common_errNullObject // bail if null
ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length
add x0, x0, w1, lsl #1 // w0<- arrayObj + index*width
cmp w1, w3 // compare unsigned index, length
bcs common_errArrayIndex // index >= length, bail
FETCH_ADVANCE_INST 2 // advance rPC, load rINST
GET_VREG w2, w9 // w2<- vAA
GET_INST_OPCODE ip // extract opcode from rINST
strh w2, [x0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_iget: /* 0x52 */
/* File: arm64/op_iget.S */
/*
* General instance field get.
*
* for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
*/
EXPORT_PC
FETCH w0, 1 // w0<- field ref CCCC
lsr w1, wINST, #12 // w1<- B
GET_VREG w1, w1 // w1<- fp[B], the object pointer
ldr x2, [xFP, #OFF_FP_METHOD] // w2<- referrer
mov x3, xSELF // w3<- self
bl artGet32InstanceFromCode
ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET]
ubfx w2, wINST, #8, #4 // w2<- A
PREFETCH_INST 2
cbnz x3, MterpPossibleException // bail out
.if 0
SET_VREG_OBJECT w0, w2 // fp[A]<- w0
.else
SET_VREG w0, w2 // fp[A]<- w0
.endif
ADVANCE 2
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_iget_wide: /* 0x53 */
/* File: arm64/op_iget_wide.S */
/*
* 64-bit instance field get.
*
* for: iget-wide
*/
EXPORT_PC
FETCH w0, 1 // w0<- field ref CCCC
lsr w1, wINST, #12 // w1<- B
GET_VREG w1, w1 // w1<- fp[B], the object pointer
ldr x2, [xFP, #OFF_FP_METHOD] // w2<- referrer
mov x3, xSELF // w3<- self
bl artGet64InstanceFromCode
ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET]
ubfx w2, wINST, #8, #4 // w2<- A
PREFETCH_INST 2
cmp w3, #0
cbnz w3, MterpException // bail out
SET_VREG_WIDE x0, w2
ADVANCE 2
GET_INST_OPCODE ip // extract opcode from wINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_iget_object: /* 0x54 */
/* File: arm64/op_iget_object.S */
/* File: arm64/op_iget.S */
/*
* General instance field get.
*
* for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
*/
EXPORT_PC
FETCH w0, 1 // w0<- field ref CCCC
lsr w1, wINST, #12 // w1<- B
GET_VREG w1, w1 // w1<- fp[B], the object pointer
ldr x2, [xFP, #OFF_FP_METHOD] // w2<- referrer
mov x3, xSELF // w3<- self
bl artGetObjInstanceFromCode
ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET]
ubfx w2, wINST, #8, #4 // w2<- A
PREFETCH_INST 2
cbnz x3, MterpPossibleException // bail out
.if 1
SET_VREG_OBJECT w0, w2 // fp[A]<- w0
.else
SET_VREG w0, w2 // fp[A]<- w0
.endif
ADVANCE 2
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_iget_boolean: /* 0x55 */
/* File: arm64/op_iget_boolean.S */
/* File: arm64/op_iget.S */
/*
* General instance field get.
*
* for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
*/
EXPORT_PC
FETCH w0, 1 // w0<- field ref CCCC
lsr w1, wINST, #12 // w1<- B
GET_VREG w1, w1 // w1<- fp[B], the object pointer
ldr x2, [xFP, #OFF_FP_METHOD] // w2<- referrer
mov x3, xSELF // w3<- self
bl artGetBooleanInstanceFromCode
ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET]
uxtb w0, w0
ubfx w2, wINST, #8, #4 // w2<- A
PREFETCH_INST 2
cbnz x3, MterpPossibleException // bail out
.if 0
SET_VREG_OBJECT w0, w2 // fp[A]<- w0
.else
SET_VREG w0, w2 // fp[A]<- w0
.endif
ADVANCE 2
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_iget_byte: /* 0x56 */
/* File: arm64/op_iget_byte.S */
/* File: arm64/op_iget.S */
/*
* General instance field get.
*
* for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
*/
EXPORT_PC
FETCH w0, 1 // w0<- field ref CCCC
lsr w1, wINST, #12 // w1<- B
GET_VREG w1, w1 // w1<- fp[B], the object pointer
ldr x2, [xFP, #OFF_FP_METHOD] // w2<- referrer
mov x3, xSELF // w3<- self
bl artGetByteInstanceFromCode
ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET]
sxtb w0, w0
ubfx w2, wINST, #8, #4 // w2<- A
PREFETCH_INST 2
cbnz x3, MterpPossibleException // bail out
.if 0
SET_VREG_OBJECT w0, w2 // fp[A]<- w0
.else
SET_VREG w0, w2 // fp[A]<- w0
.endif
ADVANCE 2
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_iget_char: /* 0x57 */
/* File: arm64/op_iget_char.S */
/* File: arm64/op_iget.S */
/*
* General instance field get.
*
* for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
*/
EXPORT_PC
FETCH w0, 1 // w0<- field ref CCCC
lsr w1, wINST, #12 // w1<- B
GET_VREG w1, w1 // w1<- fp[B], the object pointer
ldr x2, [xFP, #OFF_FP_METHOD] // w2<- referrer
mov x3, xSELF // w3<- self
bl artGetCharInstanceFromCode
ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET]
uxth w0, w0
ubfx w2, wINST, #8, #4 // w2<- A
PREFETCH_INST 2
cbnz x3, MterpPossibleException // bail out
.if 0
SET_VREG_OBJECT w0, w2 // fp[A]<- w0
.else
SET_VREG w0, w2 // fp[A]<- w0
.endif
ADVANCE 2
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_iget_short: /* 0x58 */
/* File: arm64/op_iget_short.S */
/* File: arm64/op_iget.S */
/*
* General instance field get.
*
* for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
*/
EXPORT_PC
FETCH w0, 1 // w0<- field ref CCCC
lsr w1, wINST, #12 // w1<- B
GET_VREG w1, w1 // w1<- fp[B], the object pointer
ldr x2, [xFP, #OFF_FP_METHOD] // w2<- referrer
mov x3, xSELF // w3<- self
bl artGetShortInstanceFromCode
ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET]
sxth w0, w0
ubfx w2, wINST, #8, #4 // w2<- A
PREFETCH_INST 2
cbnz x3, MterpPossibleException // bail out
.if 0
SET_VREG_OBJECT w0, w2 // fp[A]<- w0
.else
SET_VREG w0, w2 // fp[A]<- w0
.endif
ADVANCE 2
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_iput: /* 0x59 */
/* File: arm64/op_iput.S */
/*
* General 32-bit instance field put.
*
* for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short
*/
/* op vA, vB, field//CCCC */
.extern artSet32InstanceFromMterp
EXPORT_PC
FETCH w0, 1 // w0<- field ref CCCC
lsr w1, wINST, #12 // w1<- B
GET_VREG w1, w1 // w1<- fp[B], the object pointer
ubfx w2, wINST, #8, #4 // w2<- A
GET_VREG w2, w2 // w2<- fp[A]
ldr x3, [xFP, #OFF_FP_METHOD] // w3<- referrer
PREFETCH_INST 2
bl artSet32InstanceFromMterp
cbnz w0, MterpPossibleException
ADVANCE 2 // advance rPC
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_iput_wide: /* 0x5a */
/* File: arm64/op_iput_wide.S */
/* iput-wide vA, vB, field//CCCC */
.extern artSet64InstanceFromMterp
EXPORT_PC
FETCH w0, 1 // w0<- field ref CCCC
lsr w1, wINST, #12 // w1<- B
GET_VREG w1, w1 // w1<- fp[B], the object pointer
ubfx w2, wINST, #8, #4 // w2<- A
VREG_INDEX_TO_ADDR x2, x2 // w2<- &fp[A]
ldr x3, [xFP, #OFF_FP_METHOD] // w3<- referrer
PREFETCH_INST 2
bl artSet64InstanceFromMterp
cbnz w0, MterpPossibleException
ADVANCE 2 // advance rPC
GET_INST_OPCODE ip // extract opcode from wINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_iput_object: /* 0x5b */
/* File: arm64/op_iput_object.S */
EXPORT_PC
add x0, xFP, #OFF_FP_SHADOWFRAME
mov x1, xPC
mov w2, wINST
mov x3, xSELF
bl MterpIputObject
cbz w0, MterpException
FETCH_ADVANCE_INST 2 // advance rPC, load rINST
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_iput_boolean: /* 0x5c */
/* File: arm64/op_iput_boolean.S */
/* File: arm64/op_iput.S */
/*
* General 32-bit instance field put.
*
* for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short
*/
/* op vA, vB, field//CCCC */
.extern artSet8InstanceFromMterp
EXPORT_PC
FETCH w0, 1 // w0<- field ref CCCC
lsr w1, wINST, #12 // w1<- B
GET_VREG w1, w1 // w1<- fp[B], the object pointer
ubfx w2, wINST, #8, #4 // w2<- A
GET_VREG w2, w2 // w2<- fp[A]
ldr x3, [xFP, #OFF_FP_METHOD] // w3<- referrer
PREFETCH_INST 2
bl artSet8InstanceFromMterp
cbnz w0, MterpPossibleException
ADVANCE 2 // advance rPC
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_iput_byte: /* 0x5d */
/* File: arm64/op_iput_byte.S */
/* File: arm64/op_iput.S */
/*
* General 32-bit instance field put.
*
* for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short
*/
/* op vA, vB, field//CCCC */
.extern artSet8InstanceFromMterp
EXPORT_PC
FETCH w0, 1 // w0<- field ref CCCC
lsr w1, wINST, #12 // w1<- B
GET_VREG w1, w1 // w1<- fp[B], the object pointer
ubfx w2, wINST, #8, #4 // w2<- A
GET_VREG w2, w2 // w2<- fp[A]
ldr x3, [xFP, #OFF_FP_METHOD] // w3<- referrer
PREFETCH_INST 2
bl artSet8InstanceFromMterp
cbnz w0, MterpPossibleException
ADVANCE 2 // advance rPC
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_iput_char: /* 0x5e */
/* File: arm64/op_iput_char.S */
/* File: arm64/op_iput.S */
/*
* General 32-bit instance field put.
*
* for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short
*/
/* op vA, vB, field//CCCC */
.extern artSet16InstanceFromMterp
EXPORT_PC
FETCH w0, 1 // w0<- field ref CCCC
lsr w1, wINST, #12 // w1<- B
GET_VREG w1, w1 // w1<- fp[B], the object pointer
ubfx w2, wINST, #8, #4 // w2<- A
GET_VREG w2, w2 // w2<- fp[A]
ldr x3, [xFP, #OFF_FP_METHOD] // w3<- referrer
PREFETCH_INST 2
bl artSet16InstanceFromMterp
cbnz w0, MterpPossibleException
ADVANCE 2 // advance rPC
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_iput_short: /* 0x5f */
/* File: arm64/op_iput_short.S */
/* File: arm64/op_iput.S */
/*
* General 32-bit instance field put.
*
* for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short
*/
/* op vA, vB, field//CCCC */
.extern artSet16InstanceFromMterp
EXPORT_PC
FETCH w0, 1 // w0<- field ref CCCC
lsr w1, wINST, #12 // w1<- B
GET_VREG w1, w1 // w1<- fp[B], the object pointer
ubfx w2, wINST, #8, #4 // w2<- A
GET_VREG w2, w2 // w2<- fp[A]
ldr x3, [xFP, #OFF_FP_METHOD] // w3<- referrer
PREFETCH_INST 2
bl artSet16InstanceFromMterp
cbnz w0, MterpPossibleException
ADVANCE 2 // advance rPC
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_sget: /* 0x60 */
/* File: arm64/op_sget.S */
/*
* General SGET handler wrapper.
*
* for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
*/
/* op vAA, field//BBBB */
.extern artGet32StaticFromCode
EXPORT_PC
FETCH w0, 1 // w0<- field ref BBBB
ldr x1, [xFP, #OFF_FP_METHOD]
mov x2, xSELF
bl artGet32StaticFromCode
ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET]
lsr w2, wINST, #8 // w2<- AA
PREFETCH_INST 2
cbnz x3, MterpException // bail out
.if 0
SET_VREG_OBJECT w0, w2 // fp[AA]<- w0
.else
SET_VREG w0, w2 // fp[AA]<- w0
.endif
ADVANCE 2
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip
/* ------------------------------ */
.balign 128
.L_op_sget_wide: /* 0x61 */
/* File: arm64/op_sget_wide.S */
/*
* SGET_WIDE handler wrapper.
*
*/
/* sget-wide vAA, field//BBBB */
.extern artGet64StaticFromCode
EXPORT_PC
FETCH w0, 1 // w0<- field ref BBBB
ldr x1, [xFP, #OFF_FP_METHOD]
mov x2, xSELF
bl artGet64StaticFromCode
ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET]
lsr w4, wINST, #8 // w4<- AA
cbnz x3, MterpException // bail out
FETCH_ADVANCE_INST 2 // advance rPC, load wINST
SET_VREG_WIDE x0, w4
GET_INST_OPCODE ip // extract opcode from wINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_sget_object: /* 0x62 */
/* File: arm64/op_sget_object.S */
/* File: arm64/op_sget.S */
/*
* General SGET handler wrapper.
*
* for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
*/
/* op vAA, field//BBBB */
.extern artGetObjStaticFromCode
EXPORT_PC
FETCH w0, 1 // w0<- field ref BBBB
ldr x1, [xFP, #OFF_FP_METHOD]
mov x2, xSELF
bl artGetObjStaticFromCode
ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET]
lsr w2, wINST, #8 // w2<- AA
PREFETCH_INST 2
cbnz x3, MterpException // bail out
.if 1
SET_VREG_OBJECT w0, w2 // fp[AA]<- w0
.else
SET_VREG w0, w2 // fp[AA]<- w0
.endif
ADVANCE 2
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip
/* ------------------------------ */
.balign 128
.L_op_sget_boolean: /* 0x63 */
/* File: arm64/op_sget_boolean.S */
/* File: arm64/op_sget.S */
/*
* General SGET handler wrapper.
*
* for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
*/
/* op vAA, field//BBBB */
.extern artGetBooleanStaticFromCode
EXPORT_PC
FETCH w0, 1 // w0<- field ref BBBB
ldr x1, [xFP, #OFF_FP_METHOD]
mov x2, xSELF
bl artGetBooleanStaticFromCode
ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET]
lsr w2, wINST, #8 // w2<- AA
uxtb w0, w0
PREFETCH_INST 2
cbnz x3, MterpException // bail out
.if 0
SET_VREG_OBJECT w0, w2 // fp[AA]<- w0
.else
SET_VREG w0, w2 // fp[AA]<- w0
.endif
ADVANCE 2
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip
/* ------------------------------ */
.balign 128
.L_op_sget_byte: /* 0x64 */
/* File: arm64/op_sget_byte.S */
/* File: arm64/op_sget.S */
/*
* General SGET handler wrapper.
*
* for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
*/
/* op vAA, field//BBBB */
.extern artGetByteStaticFromCode
EXPORT_PC
FETCH w0, 1 // w0<- field ref BBBB
ldr x1, [xFP, #OFF_FP_METHOD]
mov x2, xSELF
bl artGetByteStaticFromCode
ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET]
lsr w2, wINST, #8 // w2<- AA
sxtb w0, w0
PREFETCH_INST 2
cbnz x3, MterpException // bail out
.if 0
SET_VREG_OBJECT w0, w2 // fp[AA]<- w0
.else
SET_VREG w0, w2 // fp[AA]<- w0
.endif
ADVANCE 2
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip
/* ------------------------------ */
.balign 128
.L_op_sget_char: /* 0x65 */
/* File: arm64/op_sget_char.S */
/* File: arm64/op_sget.S */
/*
* General SGET handler wrapper.
*
* for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
*/
/* op vAA, field//BBBB */
.extern artGetCharStaticFromCode
EXPORT_PC
FETCH w0, 1 // w0<- field ref BBBB
ldr x1, [xFP, #OFF_FP_METHOD]
mov x2, xSELF
bl artGetCharStaticFromCode
ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET]
lsr w2, wINST, #8 // w2<- AA
uxth w0, w0
PREFETCH_INST 2
cbnz x3, MterpException // bail out
.if 0
SET_VREG_OBJECT w0, w2 // fp[AA]<- w0
.else
SET_VREG w0, w2 // fp[AA]<- w0
.endif
ADVANCE 2
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip
/* ------------------------------ */
.balign 128
.L_op_sget_short: /* 0x66 */
/* File: arm64/op_sget_short.S */
/* File: arm64/op_sget.S */
/*
* General SGET handler wrapper.
*
* for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
*/
/* op vAA, field//BBBB */
.extern artGetShortStaticFromCode
EXPORT_PC
FETCH w0, 1 // w0<- field ref BBBB
ldr x1, [xFP, #OFF_FP_METHOD]
mov x2, xSELF
bl artGetShortStaticFromCode
ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET]
lsr w2, wINST, #8 // w2<- AA
sxth w0, w0
PREFETCH_INST 2
cbnz x3, MterpException // bail out
.if 0
SET_VREG_OBJECT w0, w2 // fp[AA]<- w0
.else
SET_VREG w0, w2 // fp[AA]<- w0
.endif
ADVANCE 2
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip
/* ------------------------------ */
.balign 128
.L_op_sput: /* 0x67 */
/* File: arm64/op_sput.S */
/*
* General SPUT handler wrapper.
*
* for: sput, sput-boolean, sput-byte, sput-char, sput-short
*/
/* op vAA, field//BBBB */
EXPORT_PC
FETCH w0, 1 // r0<- field ref BBBB
lsr w3, wINST, #8 // r3<- AA
GET_VREG w1, w3 // r1<= fp[AA]
ldr x2, [xFP, #OFF_FP_METHOD]
mov x3, xSELF
PREFETCH_INST 2 // Get next inst, but don't advance rPC
bl artSet32StaticFromCode
cbnz w0, MterpException // 0 on success
ADVANCE 2 // Past exception point - now advance rPC
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_sput_wide: /* 0x68 */
/* File: arm64/op_sput_wide.S */
/*
* SPUT_WIDE handler wrapper.
*
*/
/* sput-wide vAA, field//BBBB */
.extern artSet64IndirectStaticFromMterp
EXPORT_PC
FETCH w0, 1 // w0<- field ref BBBB
ldr x1, [xFP, #OFF_FP_METHOD]
lsr w2, wINST, #8 // w3<- AA
VREG_INDEX_TO_ADDR x2, w2
mov x3, xSELF
PREFETCH_INST 2 // Get next inst, but don't advance rPC
bl artSet64IndirectStaticFromMterp
cbnz w0, MterpException // 0 on success, -1 on failure
ADVANCE 2 // Past exception point - now advance rPC
GET_INST_OPCODE ip // extract opcode from wINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_sput_object: /* 0x69 */
/* File: arm64/op_sput_object.S */
EXPORT_PC
add x0, xFP, #OFF_FP_SHADOWFRAME
mov x1, xPC
mov x2, xINST
mov x3, xSELF
bl MterpSputObject
cbz w0, MterpException
FETCH_ADVANCE_INST 2 // advance rPC, load rINST
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_sput_boolean: /* 0x6a */
/* File: arm64/op_sput_boolean.S */
/* File: arm64/op_sput.S */
/*
* General SPUT handler wrapper.
*
* for: sput, sput-boolean, sput-byte, sput-char, sput-short
*/
/* op vAA, field//BBBB */
EXPORT_PC
FETCH w0, 1 // r0<- field ref BBBB
lsr w3, wINST, #8 // r3<- AA
GET_VREG w1, w3 // r1<= fp[AA]
ldr x2, [xFP, #OFF_FP_METHOD]
mov x3, xSELF
PREFETCH_INST 2 // Get next inst, but don't advance rPC
bl artSet8StaticFromCode
cbnz w0, MterpException // 0 on success
ADVANCE 2 // Past exception point - now advance rPC
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_sput_byte: /* 0x6b */
/* File: arm64/op_sput_byte.S */
/* File: arm64/op_sput.S */
/*
* General SPUT handler wrapper.
*
* for: sput, sput-boolean, sput-byte, sput-char, sput-short
*/
/* op vAA, field//BBBB */
EXPORT_PC
FETCH w0, 1 // r0<- field ref BBBB
lsr w3, wINST, #8 // r3<- AA
GET_VREG w1, w3 // r1<= fp[AA]
ldr x2, [xFP, #OFF_FP_METHOD]
mov x3, xSELF
PREFETCH_INST 2 // Get next inst, but don't advance rPC
bl artSet8StaticFromCode
cbnz w0, MterpException // 0 on success
ADVANCE 2 // Past exception point - now advance rPC
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_sput_char: /* 0x6c */
/* File: arm64/op_sput_char.S */
/* File: arm64/op_sput.S */
/*
* General SPUT handler wrapper.
*
* for: sput, sput-boolean, sput-byte, sput-char, sput-short
*/
/* op vAA, field//BBBB */
EXPORT_PC
FETCH w0, 1 // r0<- field ref BBBB
lsr w3, wINST, #8 // r3<- AA
GET_VREG w1, w3 // r1<= fp[AA]
ldr x2, [xFP, #OFF_FP_METHOD]
mov x3, xSELF
PREFETCH_INST 2 // Get next inst, but don't advance rPC
bl artSet16StaticFromCode
cbnz w0, MterpException // 0 on success
ADVANCE 2 // Past exception point - now advance rPC
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_sput_short: /* 0x6d */
/* File: arm64/op_sput_short.S */
/* File: arm64/op_sput.S */
/*
* General SPUT handler wrapper.
*
* for: sput, sput-boolean, sput-byte, sput-char, sput-short
*/
/* op vAA, field//BBBB */
EXPORT_PC
FETCH w0, 1 // r0<- field ref BBBB
lsr w3, wINST, #8 // r3<- AA
GET_VREG w1, w3 // r1<= fp[AA]
ldr x2, [xFP, #OFF_FP_METHOD]
mov x3, xSELF
PREFETCH_INST 2 // Get next inst, but don't advance rPC
bl artSet16StaticFromCode
cbnz w0, MterpException // 0 on success
ADVANCE 2 // Past exception point - now advance rPC
GET_INST_OPCODE ip // extract opcode from rINST
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_invoke_virtual: /* 0x6e */
/* File: arm64/op_invoke_virtual.S */
/* File: arm64/invoke.S */
/*
* Generic invoke handler wrapper.
*/
/* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
/* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
.extern MterpInvokeVirtual
EXPORT_PC
mov x0, xSELF
add x1, xFP, #OFF_FP_SHADOWFRAME
mov x2, xPC
mov x3, xINST
bl MterpInvokeVirtual
cbz w0, MterpException
FETCH_ADVANCE_INST 3
bl MterpShouldSwitchInterpreters
cbnz w0, MterpFallback
GET_INST_OPCODE ip
GOTO_OPCODE ip
/*
* Handle a virtual method call.
*
* for: invoke-virtual, invoke-virtual/range
*/
/* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
/* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
/* ------------------------------ */
.balign 128
.L_op_invoke_super: /* 0x6f */
/* File: arm64/op_invoke_super.S */
/* File: arm64/invoke.S */
/*
* Generic invoke handler wrapper.
*/
/* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
/* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
.extern MterpInvokeSuper
EXPORT_PC
mov x0, xSELF
add x1, xFP, #OFF_FP_SHADOWFRAME
mov x2, xPC
mov x3, xINST
bl MterpInvokeSuper
cbz w0, MterpException
FETCH_ADVANCE_INST 3
bl MterpShouldSwitchInterpreters
cbnz w0, MterpFallback
GET_INST_OPCODE ip
GOTO_OPCODE ip
/*
* Handle a "super" method call.
*
* for: invoke-super, invoke-super/range
*/
/* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
/* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
/* ------------------------------ */
.balign 128
.L_op_invoke_direct: /* 0x70 */
/* File: arm64/op_invoke_direct.S */
/* File: arm64/invoke.S */
/*
* Generic invoke handler wrapper.
*/
/* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
/* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
.extern MterpInvokeDirect
EXPORT_PC
mov x0, xSELF
add x1, xFP, #OFF_FP_SHADOWFRAME
mov x2, xPC
mov x3, xINST
bl MterpInvokeDirect
cbz w0, MterpException
FETCH_ADVANCE_INST 3
bl MterpShouldSwitchInterpreters
cbnz w0, MterpFallback
GET_INST_OPCODE ip
GOTO_OPCODE ip
/* ------------------------------ */
.balign 128
.L_op_invoke_static: /* 0x71 */
/* File: arm64/op_invoke_static.S */
/* File: arm64/invoke.S */
/*
* Generic invoke handler wrapper.
*/
/* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
/* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
.extern MterpInvokeStatic
EXPORT_PC
mov x0, xSELF
add x1, xFP, #OFF_FP_SHADOWFRAME
mov x2, xPC
mov x3, xINST
bl MterpInvokeStatic
cbz w0, MterpException
FETCH_ADVANCE_INST 3
bl MterpShouldSwitchInterpreters
cbnz w0, MterpFallback
GET_INST_OPCODE ip
GOTO_OPCODE ip
/* ------------------------------ */
.balign 128
.L_op_invoke_interface: /* 0x72 */
/* File: arm64/op_invoke_interface.S */
/* File: arm64/invoke.S */
/*
* Generic invoke handler wrapper.
*/
/* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
/* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
.extern MterpInvokeInterface
EXPORT_PC
mov x0, xSELF
add x1, xFP, #OFF_FP_SHADOWFRAME
mov x2, xPC
mov x3, xINST
bl MterpInvokeInterface
cbz w0, MterpException
FETCH_ADVANCE_INST 3
bl MterpShouldSwitchInterpreters
cbnz w0, MterpFallback
GET_INST_OPCODE ip
GOTO_OPCODE ip
/*
* Handle an interface method call.
*
* for: invoke-interface, invoke-interface/range
*/
/* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
/* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
/* ------------------------------ */
.balign 128
.L_op_return_void_no_barrier: /* 0x73 */
/* File: arm64/op_return_void_no_barrier.S */
ldr w7, [xSELF, #THREAD_FLAGS_OFFSET]
mov x0, xSELF
ands w7, w7, #(THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
b.ne .Lop_return_void_no_barrier_check
.Lop_return_void_no_barrier_return:
mov x0, #0
b MterpReturn
.Lop_return_void_no_barrier_check:
bl MterpSuspendCheck // (self)
b .Lop_return_void_no_barrier_return
/* ------------------------------ */
.balign 128
.L_op_invoke_virtual_range: /* 0x74 */
/* File: arm64/op_invoke_virtual_range.S */
/* File: arm64/invoke.S */
/*
* Generic invoke handler wrapper.
*/
/* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
/* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
.extern MterpInvokeVirtualRange
EXPORT_PC
mov x0, xSELF
add x1, xFP, #OFF_FP_SHADOWFRAME
mov x2, xPC
mov x3, xINST
bl MterpInvokeVirtualRange
cbz w0, MterpException
FETCH_ADVANCE_INST 3
bl MterpShouldSwitchInterpreters
cbnz w0, MterpFallback
GET_INST_OPCODE ip
GOTO_OPCODE ip
/* ------------------------------ */
.balign 128
.L_op_invoke_super_range: /* 0x75 */
/* File: arm64/op_invoke_super_range.S */
/* File: arm64/invoke.S */
/*
* Generic invoke handler wrapper.
*/
/* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
/* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
.extern MterpInvokeSuperRange
EXPORT_PC
mov x0, xSELF
add x1, xFP, #OFF_FP_SHADOWFRAME
mov x2, xPC
mov x3, xINST
bl MterpInvokeSuperRange
cbz w0, MterpException
FETCH_ADVANCE_INST 3
bl MterpShouldSwitchInterpreters
cbnz w0, MterpFallback
GET_INST_OPCODE ip
GOTO_OPCODE ip
/* ------------------------------ */
.balign 128
.L_op_invoke_direct_range: /* 0x76 */
/* File: arm64/op_invoke_direct_range.S */
/* File: arm64/invoke.S */
/*
* Generic invoke handler wrapper.
*/
/* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
/* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
.extern MterpInvokeDirectRange
EXPORT_PC
mov x0, xSELF
add x1, xFP, #OFF_FP_SHADOWFRAME
mov x2, xPC
mov x3, xINST
bl MterpInvokeDirectRange
cbz w0, MterpException
FETCH_ADVANCE_INST 3
bl MterpShouldSwitchInterpreters
cbnz w0, MterpFallback
GET_INST_OPCODE ip
GOTO_OPCODE ip
/* ------------------------------ */
.balign 128
.L_op_invoke_static_range: /* 0x77 */
/* File: arm64/op_invoke_static_range.S */
/* File: arm64/invoke.S */
/*
* Generic invoke handler wrapper.
*/
/* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
/* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
.extern MterpInvokeStaticRange
EXPORT_PC
mov x0, xSELF
add x1, xFP, #OFF_FP_SHADOWFRAME
mov x2, xPC
mov x3, xINST
bl MterpInvokeStaticRange
cbz w0, MterpException
FETCH_ADVANCE_INST 3
bl MterpShouldSwitchInterpreters
cbnz w0, MterpFallback
GET_INST_OPCODE ip
GOTO_OPCODE ip
/* ------------------------------ */
.balign 128
.L_op_invoke_interface_range: /* 0x78 */
/* File: arm64/op_invoke_interface_range.S */
/* File: arm64/invoke.S */
/*
* Generic invoke handler wrapper.
*/
/* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
/* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
.extern MterpInvokeInterfaceRange
EXPORT_PC
mov x0, xSELF
add x1, xFP, #OFF_FP_SHADOWFRAME
mov x2, xPC
mov x3, xINST
bl MterpInvokeInterfaceRange
cbz w0, MterpException
FETCH_ADVANCE_INST 3
bl MterpShouldSwitchInterpreters
cbnz w0, MterpFallback
GET_INST_OPCODE ip
GOTO_OPCODE ip
/* ------------------------------ */
.balign 128
.L_op_unused_79: /* 0x79 */
/* File: arm64/op_unused_79.S */
/* File: arm64/unused.S */
/*
* Bail to reference interpreter to throw.
*/
b MterpFallback
/* ------------------------------ */
.balign 128
.L_op_unused_7a: /* 0x7a */
/* File: arm64/op_unused_7a.S */
/* File: arm64/unused.S */
/*
* Bail to reference interpreter to throw.
*/
b MterpFallback
/* ------------------------------ */
.balign 128
.L_op_neg_int: /* 0x7b */
/* File: arm64/op_neg_int.S */
/* File: arm64/unop.S */
/*
* Generic 32-bit unary operation. Provide an "instr" line that
* specifies an instruction that performs "result = op w0".
* This could be an ARM instruction or a function call.
*
* for: neg-int, not-int, neg-float, int-to-float, float-to-int,
* int-to-byte, int-to-char, int-to-short
*/
/* unop vA, vB */
lsr w3, wINST, #12 // w3<- B
GET_VREG w0, w3 // w0<- vB
ubfx w9, wINST, #8, #4 // w9<- A
// optional op; may set condition codes
FETCH_ADVANCE_INST 1 // advance rPC, load rINST
sub w0, wzr, w0 // w0<- op, w0-w3 changed
GET_INST_OPCODE ip // extract opcode from rINST
SET_VREG w0, w9 // vAA<- w0
GOTO_OPCODE ip // jump to next instruction
/* 8-9 instructions */
/* ------------------------------ */
.balign 128
.L_op_not_int: /* 0x7c */
/* File: arm64/op_not_int.S */
/* File: arm64/unop.S */
/*
* Generic 32-bit unary operation. Provide an "instr" line that
* specifies an instruction that performs "result = op w0".
* This could be an ARM instruction or a function call.
*
* for: neg-int, not-int, neg-float, int-to-float, float-to-int,
* int-to-byte, int-to-char, int-to-short
*/
/* unop vA, vB */
lsr w3, wINST, #12 // w3<- B
GET_VREG w0, w3 // w0<- vB
ubfx w9, wINST, #8, #4 // w9<- A
// optional op; may set condition codes
FETCH_ADVANCE_INST 1 // advance rPC, load rINST
mvn w0, w0 // w0<- op, w0-w3 changed
GET_INST_OPCODE ip // extract opcode from rINST
SET_VREG w0, w9 // vAA<- w0
GOTO_OPCODE ip // jump to next instruction
/* 8-9 instructions */
/* ------------------------------ */
.balign 128
.L_op_neg_long: /* 0x7d */
/* File: arm64/op_neg_long.S */
/* File: arm64/unopWide.S */
/*
* Generic 64-bit unary operation. Provide an "instr" line that
* specifies an instruction that performs "result = op x0".
*
* For: neg-long, not-long
*/
/* unop vA, vB */
lsr w3, wINST, #12 // w3<- B
ubfx w4, wINST, #8, #4 // w4<- A
GET_VREG_WIDE x0, w3
FETCH_ADVANCE_INST 1 // advance rPC, load wINST
sub x0, xzr, x0
GET_INST_OPCODE ip // extract opcode from wINST
SET_VREG_WIDE x0, w4
GOTO_OPCODE ip // jump to next instruction
/* 10-11 instructions */
/* ------------------------------ */
.balign 128
.L_op_not_long: /* 0x7e */
/* File: arm64/op_not_long.S */
/* File: arm64/unopWide.S */
/*
* Generic 64-bit unary operation. Provide an "instr" line that
* specifies an instruction that performs "result = op x0".
*
* For: neg-long, not-long
*/
/* unop vA, vB */
lsr w3, wINST, #12 // w3<- B
ubfx w4, wINST, #8, #4 // w4<- A
GET_VREG_WIDE x0, w3
FETCH_ADVANCE_INST 1 // advance rPC, load wINST
mvn x0, x0
GET_INST_OPCODE ip // extract opcode from wINST
SET_VREG_WIDE x0, w4
GOTO_OPCODE ip // jump to next instruction
/* 10-11 instructions */
/* ------------------------------ */
.balign 128
.L_op_neg_float: /* 0x7f */
/* File: arm64/op_neg_float.S */
/* File: arm64/unop.S */
/*
* Generic 32-bit unary operation. Provide an "instr" line that
* specifies an instruction that performs "result = op w0".
* This could be an ARM instruction or a function call.
*
* for: neg-int, not-int, neg-float, int-to-float, float-to-int,
* int-to-byte, int-to-char, int-to-short
*/
/* unop vA, vB */
lsr w3, wINST, #12 // w3<- B
GET_VREG w0, w3 // w0<- vB
ubfx w9, wINST, #8, #4 // w9<- A
mov w4, #0x80000000 // optional op; may set condition codes
FETCH_ADVANCE_INST 1 // advance rPC, load rINST
add w0, w0, w4 // w0<- op, w0-w3 changed
GET_INST_OPCODE ip // extract opcode from rINST
SET_VREG w0, w9 // vAA<- w0
GOTO_OPCODE ip // jump to next instruction
/* 8-9 instructions */
/* ------------------------------ */
.balign 128
.L_op_neg_double: /* 0x80 */
/* File: arm64/op_neg_double.S */
/* File: arm64/unopWide.S */
/*
* Generic 64-bit unary operation. Provide an "instr" line that
* specifies an instruction that performs "result = op x0".
*
* For: neg-long, not-long
*/
/* unop vA, vB */
lsr w3, wINST, #12 // w3<- B
ubfx w4, wINST, #8, #4 // w4<- A
GET_VREG_WIDE x0, w3
FETCH_ADVANCE_INST 1 // advance rPC, load wINST
mov x1, #0x8000000000000000
add x0, x0, x1
GET_INST_OPCODE ip // extract opcode from wINST
SET_VREG_WIDE x0, w4
GOTO_OPCODE ip // jump to next instruction
/* 10-11 instructions */
/* ------------------------------ */
.balign 128
.L_op_int_to_long: /* 0x81 */
/* File: arm64/op_int_to_long.S */
/* File: arm64/funopWider.S */
/*
* Generic 32bit-to-64bit floating point unary operation. Provide an
* "instr" line that specifies an instruction that performs "x0 = op w0".
*
* For: int-to-double, float-to-double, float-to-long
*/
/* unop vA, vB */
lsr w3, wINST, #12 // w3<- B
lsr w4, wINST, #8 // w4<- A+
GET_VREG w0, w3
FETCH_ADVANCE_INST 1 // advance rPC, load wINST
and w4, w4, #15 // w4<- A
sbfm x0, x0, 0, 31 // d0<- op
GET_INST_OPCODE ip // extract opcode from wINST
SET_VREG_WIDE x0, w4 // vA<- d0
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_int_to_float: /* 0x82 */
/* File: arm64/op_int_to_float.S */
/* File: arm64/funopNarrow.S */
/*
* Generic 32bit-to-32bit floating point unary operation. Provide an
* "instr" line that specifies an instruction that performs "s0 = op w0".
*
* For: int-to-float, float-to-int
* TODO: refactor all of the conversions - parameterize width and use same template.
*/
/* unop vA, vB */
lsr w3, wINST, #12 // w3<- B
lsr w4, wINST, #8 // w4<- A+
GET_VREG w0, w3
FETCH_ADVANCE_INST 1 // advance rPC, load wINST
and w4, w4, #15 // w4<- A
scvtf s0, w0 // d0<- op
GET_INST_OPCODE ip // extract opcode from wINST
SET_VREG s0, w4 // vA<- d0
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_int_to_double: /* 0x83 */
/* File: arm64/op_int_to_double.S */
/* File: arm64/funopWider.S */
/*
* Generic 32bit-to-64bit floating point unary operation. Provide an
* "instr" line that specifies an instruction that performs "d0 = op w0".
*
* For: int-to-double, float-to-double, float-to-long
*/
/* unop vA, vB */
lsr w3, wINST, #12 // w3<- B
lsr w4, wINST, #8 // w4<- A+
GET_VREG w0, w3
FETCH_ADVANCE_INST 1 // advance rPC, load wINST
and w4, w4, #15 // w4<- A
scvtf d0, w0 // d0<- op
GET_INST_OPCODE ip // extract opcode from wINST
SET_VREG_WIDE d0, w4 // vA<- d0
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_long_to_int: /* 0x84 */
/* File: arm64/op_long_to_int.S */
/* File: arm64/funopNarrower.S */
/*
* Generic 64bit-to-32bit floating point unary operation. Provide an
* "instr" line that specifies an instruction that performs "w0 = op x0".
*
* For: int-to-double, float-to-double, float-to-long
*/
/* unop vA, vB */
lsr w3, wINST, #12 // w3<- B
lsr w4, wINST, #8 // w4<- A+
GET_VREG_WIDE x0, w3
FETCH_ADVANCE_INST 1 // advance rPC, load wINST
and w4, w4, #15 // w4<- A
// d0<- op
GET_INST_OPCODE ip // extract opcode from wINST
SET_VREG w0, w4 // vA<- d0
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_long_to_float: /* 0x85 */
/* File: arm64/op_long_to_float.S */
/* File: arm64/funopNarrower.S */
/*
* Generic 64bit-to-32bit floating point unary operation. Provide an
* "instr" line that specifies an instruction that performs "s0 = op x0".
*
* For: int-to-double, float-to-double, float-to-long
*/
/* unop vA, vB */
lsr w3, wINST, #12 // w3<- B
lsr w4, wINST, #8 // w4<- A+
GET_VREG_WIDE x0, w3
FETCH_ADVANCE_INST 1 // advance rPC, load wINST
and w4, w4, #15 // w4<- A
scvtf s0, x0 // d0<- op
GET_INST_OPCODE ip // extract opcode from wINST
SET_VREG s0, w4 // vA<- d0
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_long_to_double: /* 0x86 */
/* File: arm64/op_long_to_double.S */
/* File: arm64/funopWide.S */
/*
* Generic 64bit-to-64bit floating point unary operation. Provide an
* "instr" line that specifies an instruction that performs "d0 = op x0".
*
* For: long-to-double, double-to-long
*/
/* unop vA, vB */
lsr w3, wINST, #12 // w3<- B
lsr w4, wINST, #8 // w4<- A+
GET_VREG_WIDE x0, w3
FETCH_ADVANCE_INST 1 // advance rPC, load wINST
and w4, w4, #15 // w4<- A
scvtf d0, x0 // d0<- op
GET_INST_OPCODE ip // extract opcode from wINST
SET_VREG_WIDE d0, w4 // vA<- d0
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_float_to_int: /* 0x87 */
/* File: arm64/op_float_to_int.S */
/* File: arm64/funopNarrow.S */
/*
* Generic 32bit-to-32bit floating point unary operation. Provide an
* "instr" line that specifies an instruction that performs "w0 = op s0".
*
* For: int-to-float, float-to-int
* TODO: refactor all of the conversions - parameterize width and use same template.
*/
/* unop vA, vB */
lsr w3, wINST, #12 // w3<- B
lsr w4, wINST, #8 // w4<- A+
GET_VREG s0, w3
FETCH_ADVANCE_INST 1 // advance rPC, load wINST
and w4, w4, #15 // w4<- A
fcvtzs w0, s0 // d0<- op
GET_INST_OPCODE ip // extract opcode from wINST
SET_VREG w0, w4 // vA<- d0
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_float_to_long: /* 0x88 */
/* File: arm64/op_float_to_long.S */
/* File: arm64/funopWider.S */
/*
* Generic 32bit-to-64bit floating point unary operation. Provide an
* "instr" line that specifies an instruction that performs "x0 = op s0".
*
* For: int-to-double, float-to-double, float-to-long
*/
/* unop vA, vB */
lsr w3, wINST, #12 // w3<- B
lsr w4, wINST, #8 // w4<- A+
GET_VREG s0, w3
FETCH_ADVANCE_INST 1 // advance rPC, load wINST
and w4, w4, #15 // w4<- A
fcvtzs x0, s0 // d0<- op
GET_INST_OPCODE ip // extract opcode from wINST
SET_VREG_WIDE x0, w4 // vA<- d0
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_float_to_double: /* 0x89 */
/* File: arm64/op_float_to_double.S */
/* File: arm64/funopWider.S */
/*
* Generic 32bit-to-64bit floating point unary operation. Provide an
* "instr" line that specifies an instruction that performs "d0 = op s0".
*
* For: int-to-double, float-to-double, float-to-long
*/
/* unop vA, vB */
lsr w3, wINST, #12 // w3<- B
lsr w4, wINST, #8 // w4<- A+
GET_VREG s0, w3
FETCH_ADVANCE_INST 1 // advance rPC, load wINST
and w4, w4, #15 // w4<- A
fcvt d0, s0 // d0<- op
GET_INST_OPCODE ip // extract opcode from wINST
SET_VREG_WIDE d0, w4 // vA<- d0
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_double_to_int: /* 0x8a */
/* File: arm64/op_double_to_int.S */
/* File: arm64/funopNarrower.S */
/*
* Generic 64bit-to-32bit floating point unary operation. Provide an
* "instr" line that specifies an instruction that performs "w0 = op d0".
*
* For: int-to-double, float-to-double, float-to-long
*/
/* unop vA, vB */
lsr w3, wINST, #12 // w3<- B
lsr w4, wINST, #8 // w4<- A+
GET_VREG_WIDE d0, w3
FETCH_ADVANCE_INST 1 // advance rPC, load wINST
and w4, w4, #15 // w4<- A
fcvtzs w0, d0 // d0<- op
GET_INST_OPCODE ip // extract opcode from wINST
SET_VREG w0, w4 // vA<- d0
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_double_to_long: /* 0x8b */
/* File: arm64/op_double_to_long.S */
/* File: arm64/funopWide.S */
/*
* Generic 64bit-to-64bit floating point unary operation. Provide an
* "instr" line that specifies an instruction that performs "x0 = op d0".
*
* For: long-to-double, double-to-long
*/
/* unop vA, vB */
lsr w3, wINST, #12 // w3<- B
lsr w4, wINST, #8 // w4<- A+
GET_VREG_WIDE d0, w3
FETCH_ADVANCE_INST 1 // advance rPC, load wINST
and w4, w4, #15 // w4<- A
fcvtzs x0, d0 // d0<- op
GET_INST_OPCODE ip // extract opcode from wINST
SET_VREG_WIDE x0, w4 // vA<- d0
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_double_to_float: /* 0x8c */
/* File: arm64/op_double_to_float.S */
/* File: arm64/funopNarrower.S */
/*
* Generic 64bit-to-32bit floating point unary operation. Provide an
* "instr" line that specifies an instruction that performs "s0 = op d0".
*
* For: int-to-double, float-to-double, float-to-long
*/
/* unop vA, vB */
lsr w3, wINST, #12 // w3<- B
lsr w4, wINST, #8 // w4<- A+
GET_VREG_WIDE d0, w3
FETCH_ADVANCE_INST 1 // advance rPC, load wINST
and w4, w4, #15 // w4<- A
fcvt s0, d0 // d0<- op
GET_INST_OPCODE ip // extract opcode from wINST
SET_VREG s0, w4 // vA<- d0
GOTO_OPCODE ip // jump to next instruction
/* ------------------------------ */
.balign 128
.L_op_int_to_byte: /* 0x8d */
/* File: arm64/op_int_to_byte.S */
/* File: arm64/unop.S */
/*
* Generic 32-bit unary operation. Provide an "instr" line that
* specifies an instruction that performs "result = op w0".
* This could be an ARM instruction or a function call.
*
* for: neg-int, not-int, neg-float, int-to-float, float-to-int,
* int-to-byte, int-to-char, int-to-short
*/
/* unop vA, vB */
lsr w3, wINST, #12 // w3<- B
GET_VREG w0, w3 // w0<- vB
ubfx w9, wINST, #8, #4 // w9<- A
// optional op; may set condition codes
FETCH_ADVANCE_INST 1 // advance rPC, load rINST
sxtb w0, w0 // w0<- op, w0-w3 changed
GET_INST_OPCODE ip // extract opcode from rINST
SET_VREG w0, w9 // vAA<- w0
GOTO_OPCODE ip // jump to next instruction
/* 8-9 instructions */
/* ------------------------------ */
.balign 128
.L_op_int_to_char: /* 0x8e */
/* File: arm64/op_int_to_char.S */
/* File: arm64/unop.S */
/*
* Generic 32-bit unary operation. Provide an "instr" line that
* specifies an instruction that performs "result = op w0".
* This could be an ARM instruction or a function call.
*
* for: neg-int, not-int, neg-float, int-to-float, float-to-int,
* int-to-byte, int-to-char, int-to-short
*/
/* unop vA, vB */
lsr w3, wINST, #12 // w3<- B
GET_VREG w0, w3 // w0<- vB
ubfx w9, wINST, #8, #4 // w9<- A
// optional op; may set condition codes
FETCH_ADVANCE_INST 1 // advance rPC, load rINST
uxth w0, w0 // w0<- op, w0-w3 changed