commit b3cdf93d70256c4b0a9f6ed55ba4601f8c70bad4
author Mark Mendell <mark.p.mendell@intel.com> Tue Jan 27 09:51:26 2015 -0500
committer Mark Mendell <mark.p.mendell@intel.com> Mon Feb 02 16:09:25 2015 -0500
tree 28056f0958616f3e1c8322fdaddef96969dc25ca
parent 4336b97fc291d28f883607c88feaff202a684a59

ART: Fix to X86Mir2Lir::GenReduceVector

When generating the result to memory, the existing code didn't set the
aliasing correctly.

Mark the result as going to a Dalvik VR, and mark it as only a write.

Change-Id: I12f3156b7f84548b320a4fc142ff5a87a14e73d1
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>

compiler/dex/quick/x86/target_x86.cc

diff --git a/compiler/dex/quick/x86/target_x86.cc b/compiler/dex/quick/x86/target_x86.cc
index 0337096..43ebf55 100755
--- a/compiler/dex/quick/x86/target_x86.cc
+++ b/compiler/dex/quick/x86/target_x86.cc
@@ -2303,9 +2303,9 @@
       StoreFinalValue(rl_dest, rl_result);
     } else {
       int displacement = SRegOffset(rl_result.s_reg_low);
+      ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
       LIR *l = NewLIR4(extr_opcode, rs_rX86_SP_32.GetReg(), displacement, vector_src.GetReg(),
                        extract_index);
-      AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, is_wide /* is_64bit */);
       AnnotateDalvikRegAccess(l, displacement >> 2, false /* is_load */, is_wide /* is_64bit */);
     }
   }