diff --git a/build/Android.common.mk b/build/Android.common.mk
index 1ba92ab..74eee0b 100644
--- a/build/Android.common.mk
+++ b/build/Android.common.mk
@@ -56,8 +56,7 @@
 	external/icu4c/i18n \
 	external/valgrind/dynamic_annotations \
 	external/zlib \
-	art/src \
-	dalvik/libdex
+	art/src
 
 art_cflags := \
 	-O2 \
diff --git a/build/Android.libart.mk b/build/Android.libart.mk
index 9bfb15e..db05eac 100644
--- a/build/Android.libart.mk
+++ b/build/Android.libart.mk
@@ -140,7 +140,6 @@
       LOCAL_LDLIBS += -lrt
     endif
   endif
-  LOCAL_STATIC_LIBRARIES += libdex
   ifeq ($$(art_target_or_host),target)
     ifeq ($(ART_USE_LLVM_COMPILER),true)
       include $(LLVM_GEN_INTRINSICS_MK)
diff --git a/src/compiler/Compiler.h b/src/compiler/Compiler.h
index 1d89c66..a1f7ffb 100644
--- a/src/compiler/Compiler.h
+++ b/src/compiler/Compiler.h
@@ -18,6 +18,7 @@
 #define ART_SRC_COMPILER_COMPILER_H_
 
 #include "dex_file.h"
+#include "dex_instruction.h"
 
 namespace art {
 
@@ -198,7 +199,7 @@
 bool oatClearVisitedFlag(struct CompilationUnit* cUnit,
                                  struct BasicBlock* bb);
 char* oatGetDalvikDisassembly(CompilationUnit* cUnit,
-                              const DecodedInstruction* insn,
+                              const DecodedInstruction& insn,
                               const char* note);
 char* oatFullDisassembler(struct CompilationUnit* cUnit,
                           const struct MIR* mir);
diff --git a/src/compiler/CompilerIR.h b/src/compiler/CompilerIR.h
index 4c8bd44..953e3b1 100644
--- a/src/compiler/CompilerIR.h
+++ b/src/compiler/CompilerIR.h
@@ -490,7 +490,7 @@
     int offset;
     const u2* table;           // Original dex table
     int size;
-    int vaddr;                 // Dalvik offset of OP_FILL_ARRAY_DATA opcode
+    int vaddr;                 // Dalvik offset of FILL_ARRAY_DATA opcode
 } FillArrayData;
 
 
diff --git a/src/compiler/Dalvik.h b/src/compiler/Dalvik.h
index 9af49aa..d1b0e1c 100644
--- a/src/compiler/Dalvik.h
+++ b/src/compiler/Dalvik.h
@@ -46,15 +46,6 @@
 typedef int64_t             s8;
 typedef unsigned long long  u8;
 
-//Skip old DexFile.h
-#define LIBDEX_DEXFILE_H_
-//Skip old vm/Common.h
-#define DALVIK_COMMON_H_
-//Make inlines inline
-#define DEX_INLINE inline
-#include "DexOpcodes.h"
-#include "InstrUtils.h"
-
 #include "Compiler.h"
 
 #endif
diff --git a/src/compiler/Dataflow.cc b/src/compiler/Dataflow.cc
index 733552c..ad522bf4 100644
--- a/src/compiler/Dataflow.cc
+++ b/src/compiler/Dataflow.cc
@@ -16,7 +16,6 @@
 
 #include "Dalvik.h"
 #include "Dataflow.h"
-//#include "libdex/DexOpcodes.h"
 
 namespace art {
 
@@ -30,777 +29,777 @@
  * scope of optimizations but will not cause mis-optimizations.
  */
 const int oatDataFlowAttributes[kMirOpLast] = {
-    // 00 OP_NOP
+    // 00 NOP
     DF_NOP,
 
-    // 01 OP_MOVE vA, vB
+    // 01 MOVE vA, vB
     DF_DA | DF_UB | DF_IS_MOVE,
 
-    // 02 OP_MOVE_FROM16 vAA, vBBBB
+    // 02 MOVE_FROM16 vAA, vBBBB
     DF_DA | DF_UB | DF_IS_MOVE,
 
-    // 03 OP_MOVE_16 vAAAA, vBBBB
+    // 03 MOVE_16 vAAAA, vBBBB
     DF_DA | DF_UB | DF_IS_MOVE,
 
-    // 04 OP_MOVE_WIDE vA, vB
+    // 04 MOVE_WIDE vA, vB
     DF_DA_WIDE | DF_UB_WIDE | DF_IS_MOVE,
 
-    // 05 OP_MOVE_WIDE_FROM16 vAA, vBBBB
+    // 05 MOVE_WIDE_FROM16 vAA, vBBBB
     DF_DA_WIDE | DF_UB_WIDE | DF_IS_MOVE,
 
-    // 06 OP_MOVE_WIDE_16 vAAAA, vBBBB
+    // 06 MOVE_WIDE_16 vAAAA, vBBBB
     DF_DA_WIDE | DF_UB_WIDE | DF_IS_MOVE,
 
-    // 07 OP_MOVE_OBJECT vA, vB
+    // 07 MOVE_OBJECT vA, vB
     DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_CORE_A | DF_CORE_B,
 
-    // 08 OP_MOVE_OBJECT_FROM16 vAA, vBBBB
+    // 08 MOVE_OBJECT_FROM16 vAA, vBBBB
     DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_CORE_A | DF_CORE_B,
 
-    // 09 OP_MOVE_OBJECT_16 vAAAA, vBBBB
+    // 09 MOVE_OBJECT_16 vAAAA, vBBBB
     DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_CORE_A | DF_CORE_B,
 
-    // 0A OP_MOVE_RESULT vAA
+    // 0A MOVE_RESULT vAA
     DF_DA,
 
-    // 0B OP_MOVE_RESULT_WIDE vAA
+    // 0B MOVE_RESULT_WIDE vAA
     DF_DA_WIDE,
 
-    // 0C OP_MOVE_RESULT_OBJECT vAA
+    // 0C MOVE_RESULT_OBJECT vAA
     DF_DA | DF_CORE_A,
 
-    // 0D OP_MOVE_EXCEPTION vAA
+    // 0D MOVE_EXCEPTION vAA
     DF_DA | DF_CORE_A,
 
-    // 0E OP_RETURN_VOID
+    // 0E RETURN_VOID
     DF_NOP,
 
-    // 0F OP_RETURN vAA
+    // 0F RETURN vAA
     DF_UA,
 
-    // 10 OP_RETURN_WIDE vAA
+    // 10 RETURN_WIDE vAA
     DF_UA_WIDE,
 
-    // 11 OP_RETURN_OBJECT vAA
+    // 11 RETURN_OBJECT vAA
     DF_UA | DF_CORE_A,
 
-    // 12 OP_CONST_4 vA, #+B
+    // 12 CONST_4 vA, #+B
     DF_DA | DF_SETS_CONST,
 
-    // 13 OP_CONST_16 vAA, #+BBBB
+    // 13 CONST_16 vAA, #+BBBB
     DF_DA | DF_SETS_CONST,
 
-    // 14 OP_CONST vAA, #+BBBBBBBB
+    // 14 CONST vAA, #+BBBBBBBB
     DF_DA | DF_SETS_CONST,
 
-    // 15 OP_CONST_HIGH16 VAA, #+BBBB0000
+    // 15 CONST_HIGH16 VAA, #+BBBB0000
     DF_DA | DF_SETS_CONST,
 
-    // 16 OP_CONST_WIDE_16 vAA, #+BBBB
+    // 16 CONST_WIDE_16 vAA, #+BBBB
     DF_DA_WIDE | DF_SETS_CONST,
 
-    // 17 OP_CONST_WIDE_32 vAA, #+BBBBBBBB
+    // 17 CONST_WIDE_32 vAA, #+BBBBBBBB
     DF_DA_WIDE | DF_SETS_CONST,
 
-    // 18 OP_CONST_WIDE vAA, #+BBBBBBBBBBBBBBBB
+    // 18 CONST_WIDE vAA, #+BBBBBBBBBBBBBBBB
     DF_DA_WIDE | DF_SETS_CONST,
 
-    // 19 OP_CONST_WIDE_HIGH16 vAA, #+BBBB000000000000
+    // 19 CONST_WIDE_HIGH16 vAA, #+BBBB000000000000
     DF_DA_WIDE | DF_SETS_CONST,
 
-    // 1A OP_CONST_STRING vAA, string@BBBB
+    // 1A CONST_STRING vAA, string@BBBB
     DF_DA | DF_CORE_A,
 
-    // 1B OP_CONST_STRING_JUMBO vAA, string@BBBBBBBB
+    // 1B CONST_STRING_JUMBO vAA, string@BBBBBBBB
     DF_DA | DF_CORE_A,
 
-    // 1C OP_CONST_CLASS vAA, type@BBBB
+    // 1C CONST_CLASS vAA, type@BBBB
     DF_DA | DF_CORE_A,
 
-    // 1D OP_MONITOR_ENTER vAA
+    // 1D MONITOR_ENTER vAA
     DF_UA | DF_NULL_CHK_0 | DF_CORE_A,
 
-    // 1E OP_MONITOR_EXIT vAA
+    // 1E MONITOR_EXIT vAA
     DF_UA | DF_NULL_CHK_0 | DF_CORE_A,
 
-    // 1F OP_CHK_CAST vAA, type@BBBB
+    // 1F CHK_CAST vAA, type@BBBB
     DF_UA | DF_CORE_A,
 
-    // 20 OP_INSTANCE_OF vA, vB, type@CCCC
+    // 20 INSTANCE_OF vA, vB, type@CCCC
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // 21 OP_ARRAY_LENGTH vA, vB
+    // 21 ARRAY_LENGTH vA, vB
     DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_A | DF_CORE_B,
 
-    // 22 OP_NEW_INSTANCE vAA, type@BBBB
+    // 22 NEW_INSTANCE vAA, type@BBBB
     DF_DA | DF_NON_NULL_DST | DF_CORE_A,
 
-    // 23 OP_NEW_ARRAY vA, vB, type@CCCC
+    // 23 NEW_ARRAY vA, vB, type@CCCC
     DF_DA | DF_UB | DF_NON_NULL_DST | DF_CORE_A | DF_CORE_B,
 
-    // 24 OP_FILLED_NEW_ARRAY {vD, vE, vF, vG, vA}
+    // 24 FILLED_NEW_ARRAY {vD, vE, vF, vG, vA}
     DF_FORMAT_35C | DF_NON_NULL_RET,
 
-    // 25 OP_FILLED_NEW_ARRAY_RANGE {vCCCC .. vNNNN}, type@BBBB
+    // 25 FILLED_NEW_ARRAY_RANGE {vCCCC .. vNNNN}, type@BBBB
     DF_FORMAT_3RC | DF_NON_NULL_RET,
 
-    // 26 OP_FILL_ARRAY_DATA vAA, +BBBBBBBB
+    // 26 FILL_ARRAY_DATA vAA, +BBBBBBBB
     DF_UA | DF_CORE_A,
 
-    // 27 OP_THROW vAA
+    // 27 THROW vAA
     DF_UA | DF_CORE_A,
 
-    // 28 OP_GOTO
+    // 28 GOTO
     DF_NOP,
 
-    // 29 OP_GOTO_16
+    // 29 GOTO_16
     DF_NOP,
 
-    // 2A OP_GOTO_32
+    // 2A GOTO_32
     DF_NOP,
 
-    // 2B OP_PACKED_SWITCH vAA, +BBBBBBBB
+    // 2B PACKED_SWITCH vAA, +BBBBBBBB
     DF_UA,
 
-    // 2C OP_SPARSE_SWITCH vAA, +BBBBBBBB
+    // 2C SPARSE_SWITCH vAA, +BBBBBBBB
     DF_UA,
 
-    // 2D OP_CMPL_FLOAT vAA, vBB, vCC
+    // 2D CMPL_FLOAT vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_FP_B | DF_FP_C | DF_CORE_A,
 
-    // 2E OP_CMPG_FLOAT vAA, vBB, vCC
+    // 2E CMPG_FLOAT vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_FP_B | DF_FP_C | DF_CORE_A,
 
-    // 2F OP_CMPL_DOUBLE vAA, vBB, vCC
+    // 2F CMPL_DOUBLE vAA, vBB, vCC
     DF_DA | DF_UB_WIDE | DF_UC_WIDE | DF_FP_B | DF_FP_C | DF_CORE_A,
 
-    // 30 OP_CMPG_DOUBLE vAA, vBB, vCC
+    // 30 CMPG_DOUBLE vAA, vBB, vCC
     DF_DA | DF_UB_WIDE | DF_UC_WIDE | DF_FP_B | DF_FP_C | DF_CORE_A,
 
-    // 31 OP_CMP_LONG vAA, vBB, vCC
+    // 31 CMP_LONG vAA, vBB, vCC
     DF_DA | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // 32 OP_IF_EQ vA, vB, +CCCC
+    // 32 IF_EQ vA, vB, +CCCC
     DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // 33 OP_IF_NE vA, vB, +CCCC
+    // 33 IF_NE vA, vB, +CCCC
     DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // 34 OP_IF_LT vA, vB, +CCCC
+    // 34 IF_LT vA, vB, +CCCC
     DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // 35 OP_IF_GE vA, vB, +CCCC
+    // 35 IF_GE vA, vB, +CCCC
     DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // 36 OP_IF_GT vA, vB, +CCCC
+    // 36 IF_GT vA, vB, +CCCC
     DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // 37 OP_IF_LE vA, vB, +CCCC
+    // 37 IF_LE vA, vB, +CCCC
     DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
 
 
-    // 38 OP_IF_EQZ vAA, +BBBB
+    // 38 IF_EQZ vAA, +BBBB
     DF_UA | DF_CORE_A,
 
-    // 39 OP_IF_NEZ vAA, +BBBB
+    // 39 IF_NEZ vAA, +BBBB
     DF_UA | DF_CORE_A,
 
-    // 3A OP_IF_LTZ vAA, +BBBB
+    // 3A IF_LTZ vAA, +BBBB
     DF_UA | DF_CORE_A,
 
-    // 3B OP_IF_GEZ vAA, +BBBB
+    // 3B IF_GEZ vAA, +BBBB
     DF_UA | DF_CORE_A,
 
-    // 3C OP_IF_GTZ vAA, +BBBB
+    // 3C IF_GTZ vAA, +BBBB
     DF_UA | DF_CORE_A,
 
-    // 3D OP_IF_LEZ vAA, +BBBB
+    // 3D IF_LEZ vAA, +BBBB
     DF_UA | DF_CORE_A,
 
-    // 3E OP_UNUSED_3E
+    // 3E UNUSED_3E
     DF_NOP,
 
-    // 3F OP_UNUSED_3F
+    // 3F UNUSED_3F
     DF_NOP,
 
-    // 40 OP_UNUSED_40
+    // 40 UNUSED_40
     DF_NOP,
 
-    // 41 OP_UNUSED_41
+    // 41 UNUSED_41
     DF_NOP,
 
-    // 42 OP_UNUSED_42
+    // 42 UNUSED_42
     DF_NOP,
 
-    // 43 OP_UNUSED_43
+    // 43 UNUSED_43
     DF_NOP,
 
-    // 44 OP_AGET vAA, vBB, vCC
+    // 44 AGET vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_IS_GETTER | DF_CORE_B | DF_CORE_C,
 
-    // 45 OP_AGET_WIDE vAA, vBB, vCC
+    // 45 AGET_WIDE vAA, vBB, vCC
     DF_DA_WIDE | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_IS_GETTER | DF_CORE_B | DF_CORE_C,
 
-    // 46 OP_AGET_OBJECT vAA, vBB, vCC
+    // 46 AGET_OBJECT vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_IS_GETTER | DF_CORE_B | DF_CORE_C,
 
-    // 47 OP_AGET_BOOLEAN vAA, vBB, vCC
+    // 47 AGET_BOOLEAN vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_IS_GETTER | DF_CORE_B | DF_CORE_C,
 
-    // 48 OP_AGET_BYTE vAA, vBB, vCC
+    // 48 AGET_BYTE vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_IS_GETTER | DF_CORE_B | DF_CORE_C,
 
-    // 49 OP_AGET_CHAR vAA, vBB, vCC
+    // 49 AGET_CHAR vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_IS_GETTER | DF_CORE_B | DF_CORE_C,
 
-    // 4A OP_AGET_SHORT vAA, vBB, vCC
+    // 4A AGET_SHORT vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_IS_GETTER | DF_CORE_B | DF_CORE_C,
 
-    // 4B OP_APUT vAA, vBB, vCC
+    // 4B APUT vAA, vBB, vCC
     DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_IS_SETTER | DF_CORE_B | DF_CORE_C,
 
-    // 4C OP_APUT_WIDE vAA, vBB, vCC
+    // 4C APUT_WIDE vAA, vBB, vCC
     DF_UA_WIDE | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_IS_SETTER | DF_CORE_B | DF_CORE_C,
 
-    // 4D OP_APUT_OBJECT vAA, vBB, vCC
+    // 4D APUT_OBJECT vAA, vBB, vCC
     DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_IS_SETTER | DF_CORE_B | DF_CORE_C,
 
-    // 4E OP_APUT_BOOLEAN vAA, vBB, vCC
+    // 4E APUT_BOOLEAN vAA, vBB, vCC
     DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_IS_SETTER | DF_CORE_B | DF_CORE_C,
 
-    // 4F OP_APUT_BYTE vAA, vBB, vCC
+    // 4F APUT_BYTE vAA, vBB, vCC
     DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_IS_SETTER | DF_CORE_B | DF_CORE_C,
 
-    // 50 OP_APUT_CHAR vAA, vBB, vCC
+    // 50 APUT_CHAR vAA, vBB, vCC
     DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_IS_SETTER | DF_CORE_B | DF_CORE_C,
 
-    // 51 OP_APUT_SHORT vAA, vBB, vCC
+    // 51 APUT_SHORT vAA, vBB, vCC
     DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_IS_SETTER | DF_CORE_B | DF_CORE_C,
 
-    // 52 OP_IGET vA, vB, field@CCCC
+    // 52 IGET vA, vB, field@CCCC
     DF_DA | DF_UB | DF_NULL_CHK_0 | DF_IS_GETTER | DF_CORE_B,
 
-    // 53 OP_IGET_WIDE vA, vB, field@CCCC
+    // 53 IGET_WIDE vA, vB, field@CCCC
     DF_DA_WIDE | DF_UB | DF_NULL_CHK_0 | DF_IS_GETTER | DF_CORE_B,
 
-    // 54 OP_IGET_OBJECT vA, vB, field@CCCC
+    // 54 IGET_OBJECT vA, vB, field@CCCC
     DF_DA | DF_UB | DF_NULL_CHK_0 | DF_IS_GETTER | DF_CORE_B,
 
-    // 55 OP_IGET_BOOLEAN vA, vB, field@CCCC
+    // 55 IGET_BOOLEAN vA, vB, field@CCCC
     DF_DA | DF_UB | DF_NULL_CHK_0 | DF_IS_GETTER | DF_CORE_B,
 
-    // 56 OP_IGET_BYTE vA, vB, field@CCCC
+    // 56 IGET_BYTE vA, vB, field@CCCC
     DF_DA | DF_UB | DF_NULL_CHK_0 | DF_IS_GETTER | DF_CORE_B,
 
-    // 57 OP_IGET_CHAR vA, vB, field@CCCC
+    // 57 IGET_CHAR vA, vB, field@CCCC
     DF_DA | DF_UB | DF_NULL_CHK_0 | DF_IS_GETTER | DF_CORE_B,
 
-    // 58 OP_IGET_SHORT vA, vB, field@CCCC
+    // 58 IGET_SHORT vA, vB, field@CCCC
     DF_DA | DF_UB | DF_NULL_CHK_0 | DF_IS_GETTER | DF_CORE_B,
 
-    // 59 OP_IPUT vA, vB, field@CCCC
+    // 59 IPUT vA, vB, field@CCCC
     DF_UA | DF_UB | DF_NULL_CHK_1 | DF_IS_SETTER | DF_CORE_B,
 
-    // 5A OP_IPUT_WIDE vA, vB, field@CCCC
+    // 5A IPUT_WIDE vA, vB, field@CCCC
     DF_UA_WIDE | DF_UB | DF_NULL_CHK_1 | DF_IS_SETTER | DF_CORE_B,
 
-    // 5B OP_IPUT_OBJECT vA, vB, field@CCCC
+    // 5B IPUT_OBJECT vA, vB, field@CCCC
     DF_UA | DF_UB | DF_NULL_CHK_1 | DF_IS_SETTER | DF_CORE_B,
 
-    // 5C OP_IPUT_BOOLEAN vA, vB, field@CCCC
+    // 5C IPUT_BOOLEAN vA, vB, field@CCCC
     DF_UA | DF_UB | DF_NULL_CHK_1 | DF_IS_SETTER | DF_CORE_B,
 
-    // 5D OP_IPUT_BYTE vA, vB, field@CCCC
+    // 5D IPUT_BYTE vA, vB, field@CCCC
     DF_UA | DF_UB | DF_NULL_CHK_1 | DF_IS_SETTER | DF_CORE_B,
 
-    // 5E OP_IPUT_CHAR vA, vB, field@CCCC
+    // 5E IPUT_CHAR vA, vB, field@CCCC
     DF_UA | DF_UB | DF_NULL_CHK_1 | DF_IS_SETTER | DF_CORE_B,
 
-    // 5F OP_IPUT_SHORT vA, vB, field@CCCC
+    // 5F IPUT_SHORT vA, vB, field@CCCC
     DF_UA | DF_UB | DF_NULL_CHK_1 | DF_IS_SETTER | DF_CORE_B,
 
-    // 60 OP_SGET vAA, field@BBBB
+    // 60 SGET vAA, field@BBBB
     DF_DA | DF_IS_GETTER,
 
-    // 61 OP_SGET_WIDE vAA, field@BBBB
+    // 61 SGET_WIDE vAA, field@BBBB
     DF_DA_WIDE | DF_IS_GETTER,
 
-    // 62 OP_SGET_OBJECT vAA, field@BBBB
+    // 62 SGET_OBJECT vAA, field@BBBB
     DF_DA | DF_IS_GETTER | DF_CORE_A,
 
-    // 63 OP_SGET_BOOLEAN vAA, field@BBBB
+    // 63 SGET_BOOLEAN vAA, field@BBBB
     DF_DA | DF_IS_GETTER,
 
-    // 64 OP_SGET_BYTE vAA, field@BBBB
+    // 64 SGET_BYTE vAA, field@BBBB
     DF_DA | DF_IS_GETTER,
 
-    // 65 OP_SGET_CHAR vAA, field@BBBB
+    // 65 SGET_CHAR vAA, field@BBBB
     DF_DA | DF_IS_GETTER,
 
-    // 66 OP_SGET_SHORT vAA, field@BBBB
+    // 66 SGET_SHORT vAA, field@BBBB
     DF_DA | DF_IS_GETTER,
 
-    // 67 OP_SPUT vAA, field@BBBB
+    // 67 SPUT vAA, field@BBBB
     DF_UA | DF_IS_SETTER,
 
-    // 68 OP_SPUT_WIDE vAA, field@BBBB
+    // 68 SPUT_WIDE vAA, field@BBBB
     DF_UA_WIDE | DF_IS_SETTER,
 
-    // 69 OP_SPUT_OBJECT vAA, field@BBBB
+    // 69 SPUT_OBJECT vAA, field@BBBB
     DF_UA | DF_IS_SETTER | DF_CORE_A,
 
-    // 6A OP_SPUT_BOOLEAN vAA, field@BBBB
+    // 6A SPUT_BOOLEAN vAA, field@BBBB
     DF_UA | DF_IS_SETTER,
 
-    // 6B OP_SPUT_BYTE vAA, field@BBBB
+    // 6B SPUT_BYTE vAA, field@BBBB
     DF_UA | DF_IS_SETTER,
 
-    // 6C OP_SPUT_CHAR vAA, field@BBBB
+    // 6C SPUT_CHAR vAA, field@BBBB
     DF_UA | DF_IS_SETTER,
 
-    // 6D OP_SPUT_SHORT vAA, field@BBBB
+    // 6D SPUT_SHORT vAA, field@BBBB
     DF_UA | DF_IS_SETTER,
 
-    // 6E OP_INVOKE_VIRTUAL {vD, vE, vF, vG, vA}
+    // 6E INVOKE_VIRTUAL {vD, vE, vF, vG, vA}
     DF_FORMAT_35C | DF_NULL_CHK_OUT0,
 
-    // 6F OP_INVOKE_SUPER {vD, vE, vF, vG, vA}
+    // 6F INVOKE_SUPER {vD, vE, vF, vG, vA}
     DF_FORMAT_35C | DF_NULL_CHK_OUT0,
 
-    // 70 OP_INVOKE_DIRECT {vD, vE, vF, vG, vA}
+    // 70 INVOKE_DIRECT {vD, vE, vF, vG, vA}
     DF_FORMAT_35C | DF_NULL_CHK_OUT0,
 
-    // 71 OP_INVOKE_STATIC {vD, vE, vF, vG, vA}
+    // 71 INVOKE_STATIC {vD, vE, vF, vG, vA}
     DF_FORMAT_35C,
 
-    // 72 OP_INVOKE_INTERFACE {vD, vE, vF, vG, vA}
+    // 72 INVOKE_INTERFACE {vD, vE, vF, vG, vA}
     DF_FORMAT_35C,
 
-    // 73 OP_UNUSED_73
+    // 73 UNUSED_73
     DF_NOP,
 
-    // 74 OP_INVOKE_VIRTUAL_RANGE {vCCCC .. vNNNN}
+    // 74 INVOKE_VIRTUAL_RANGE {vCCCC .. vNNNN}
     DF_FORMAT_3RC | DF_NULL_CHK_OUT0,
 
-    // 75 OP_INVOKE_SUPER_RANGE {vCCCC .. vNNNN}
+    // 75 INVOKE_SUPER_RANGE {vCCCC .. vNNNN}
     DF_FORMAT_3RC | DF_NULL_CHK_OUT0,
 
-    // 76 OP_INVOKE_DIRECT_RANGE {vCCCC .. vNNNN}
+    // 76 INVOKE_DIRECT_RANGE {vCCCC .. vNNNN}
     DF_FORMAT_3RC | DF_NULL_CHK_OUT0,
 
-    // 77 OP_INVOKE_STATIC_RANGE {vCCCC .. vNNNN}
+    // 77 INVOKE_STATIC_RANGE {vCCCC .. vNNNN}
     DF_FORMAT_3RC,
 
-    // 78 OP_INVOKE_INTERFACE_RANGE {vCCCC .. vNNNN}
+    // 78 INVOKE_INTERFACE_RANGE {vCCCC .. vNNNN}
     DF_FORMAT_3RC,
 
-    // 79 OP_UNUSED_79
+    // 79 UNUSED_79
     DF_NOP,
 
-    // 7A OP_UNUSED_7A
+    // 7A UNUSED_7A
     DF_NOP,
 
-    // 7B OP_NEG_INT vA, vB
+    // 7B NEG_INT vA, vB
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // 7C OP_NOT_INT vA, vB
+    // 7C NOT_INT vA, vB
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // 7D OP_NEG_LONG vA, vB
+    // 7D NEG_LONG vA, vB
     DF_DA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
 
-    // 7E OP_NOT_LONG vA, vB
+    // 7E NOT_LONG vA, vB
     DF_DA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
 
-    // 7F OP_NEG_FLOAT vA, vB
+    // 7F NEG_FLOAT vA, vB
     DF_DA | DF_UB | DF_FP_A | DF_FP_B,
 
-    // 80 OP_NEG_DOUBLE vA, vB
+    // 80 NEG_DOUBLE vA, vB
     DF_DA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
 
-    // 81 OP_INT_TO_LONG vA, vB
+    // 81 INT_TO_LONG vA, vB
     DF_DA_WIDE | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // 82 OP_INT_TO_FLOAT vA, vB
+    // 82 INT_TO_FLOAT vA, vB
     DF_DA | DF_UB | DF_FP_A | DF_CORE_B,
 
-    // 83 OP_INT_TO_DOUBLE vA, vB
+    // 83 INT_TO_DOUBLE vA, vB
     DF_DA_WIDE | DF_UB | DF_FP_A | DF_CORE_B,
 
-    // 84 OP_LONG_TO_INT vA, vB
+    // 84 LONG_TO_INT vA, vB
     DF_DA | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
 
-    // 85 OP_LONG_TO_FLOAT vA, vB
+    // 85 LONG_TO_FLOAT vA, vB
     DF_DA | DF_UB_WIDE | DF_FP_A | DF_CORE_B,
 
-    // 86 OP_LONG_TO_DOUBLE vA, vB
+    // 86 LONG_TO_DOUBLE vA, vB
     DF_DA_WIDE | DF_UB_WIDE | DF_FP_A | DF_CORE_B,
 
-    // 87 OP_FLOAT_TO_INT vA, vB
+    // 87 FLOAT_TO_INT vA, vB
     DF_DA | DF_UB | DF_FP_B | DF_CORE_A,
 
-    // 88 OP_FLOAT_TO_LONG vA, vB
+    // 88 FLOAT_TO_LONG vA, vB
     DF_DA_WIDE | DF_UB | DF_FP_B | DF_CORE_A,
 
-    // 89 OP_FLOAT_TO_DOUBLE vA, vB
+    // 89 FLOAT_TO_DOUBLE vA, vB
     DF_DA_WIDE | DF_UB | DF_FP_A | DF_FP_B,
 
-    // 8A OP_DOUBLE_TO_INT vA, vB
+    // 8A DOUBLE_TO_INT vA, vB
     DF_DA | DF_UB_WIDE | DF_FP_B | DF_CORE_A,
 
-    // 8B OP_DOUBLE_TO_LONG vA, vB
+    // 8B DOUBLE_TO_LONG vA, vB
     DF_DA_WIDE | DF_UB_WIDE | DF_FP_B | DF_CORE_A,
 
-    // 8C OP_DOUBLE_TO_FLOAT vA, vB
+    // 8C DOUBLE_TO_FLOAT vA, vB
     DF_DA | DF_UB_WIDE | DF_FP_A | DF_FP_B,
 
-    // 8D OP_INT_TO_BYTE vA, vB
+    // 8D INT_TO_BYTE vA, vB
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // 8E OP_INT_TO_CHAR vA, vB
+    // 8E INT_TO_CHAR vA, vB
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // 8F OP_INT_TO_SHORT vA, vB
+    // 8F INT_TO_SHORT vA, vB
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // 90 OP_ADD_INT vAA, vBB, vCC
+    // 90 ADD_INT vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_IS_LINEAR | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // 91 OP_SUB_INT vAA, vBB, vCC
+    // 91 SUB_INT vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_IS_LINEAR | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // 92 OP_MUL_INT vAA, vBB, vCC
+    // 92 MUL_INT vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // 93 OP_DIV_INT vAA, vBB, vCC
+    // 93 DIV_INT vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // 94 OP_REM_INT vAA, vBB, vCC
+    // 94 REM_INT vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // 95 OP_AND_INT vAA, vBB, vCC
+    // 95 AND_INT vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // 96 OP_OR_INT vAA, vBB, vCC
+    // 96 OR_INT vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // 97 OP_XOR_INT vAA, vBB, vCC
+    // 97 XOR_INT vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // 98 OP_SHL_INT vAA, vBB, vCC
+    // 98 SHL_INT vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // 99 OP_SHR_INT vAA, vBB, vCC
+    // 99 SHR_INT vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // 9A OP_USHR_INT vAA, vBB, vCC
+    // 9A USHR_INT vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // 9B OP_ADD_LONG vAA, vBB, vCC
+    // 9B ADD_LONG vAA, vBB, vCC
     DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // 9C OP_SUB_LONG vAA, vBB, vCC
+    // 9C SUB_LONG vAA, vBB, vCC
     DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // 9D OP_MUL_LONG vAA, vBB, vCC
+    // 9D MUL_LONG vAA, vBB, vCC
     DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // 9E OP_DIV_LONG vAA, vBB, vCC
+    // 9E DIV_LONG vAA, vBB, vCC
     DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // 9F OP_REM_LONG vAA, vBB, vCC
+    // 9F REM_LONG vAA, vBB, vCC
     DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // A0 OP_AND_LONG vAA, vBB, vCC
+    // A0 AND_LONG vAA, vBB, vCC
     DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // A1 OP_OR_LONG vAA, vBB, vCC
+    // A1 OR_LONG vAA, vBB, vCC
     DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // A2 OP_XOR_LONG vAA, vBB, vCC
+    // A2 XOR_LONG vAA, vBB, vCC
     DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // A3 OP_SHL_LONG vAA, vBB, vCC
+    // A3 SHL_LONG vAA, vBB, vCC
     DF_DA_WIDE | DF_UB_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // A4 OP_SHR_LONG vAA, vBB, vCC
+    // A4 SHR_LONG vAA, vBB, vCC
     DF_DA_WIDE | DF_UB_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // A5 OP_USHR_LONG vAA, vBB, vCC
+    // A5 USHR_LONG vAA, vBB, vCC
     DF_DA_WIDE | DF_UB_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
-    // A6 OP_ADD_FLOAT vAA, vBB, vCC
+    // A6 ADD_FLOAT vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
 
-    // A7 OP_SUB_FLOAT vAA, vBB, vCC
+    // A7 SUB_FLOAT vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
 
-    // A8 OP_MUL_FLOAT vAA, vBB, vCC
+    // A8 MUL_FLOAT vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
 
-    // A9 OP_DIV_FLOAT vAA, vBB, vCC
+    // A9 DIV_FLOAT vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
 
-    // AA OP_REM_FLOAT vAA, vBB, vCC
+    // AA REM_FLOAT vAA, vBB, vCC
     DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
 
-    // AB OP_ADD_DOUBLE vAA, vBB, vCC
+    // AB ADD_DOUBLE vAA, vBB, vCC
     DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
 
-    // AC OP_SUB_DOUBLE vAA, vBB, vCC
+    // AC SUB_DOUBLE vAA, vBB, vCC
     DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
 
-    // AD OP_MUL_DOUBLE vAA, vBB, vCC
+    // AD MUL_DOUBLE vAA, vBB, vCC
     DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
 
-    // AE OP_DIV_DOUBLE vAA, vBB, vCC
+    // AE DIV_DOUBLE vAA, vBB, vCC
     DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
 
-    // AF OP_REM_DOUBLE vAA, vBB, vCC
+    // AF REM_DOUBLE vAA, vBB, vCC
     DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
 
-    // B0 OP_ADD_INT_2ADDR vA, vB
+    // B0 ADD_INT_2ADDR vA, vB
     DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // B1 OP_SUB_INT_2ADDR vA, vB
+    // B1 SUB_INT_2ADDR vA, vB
     DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // B2 OP_MUL_INT_2ADDR vA, vB
+    // B2 MUL_INT_2ADDR vA, vB
     DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // B3 OP_DIV_INT_2ADDR vA, vB
+    // B3 DIV_INT_2ADDR vA, vB
     DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // B4 OP_REM_INT_2ADDR vA, vB
+    // B4 REM_INT_2ADDR vA, vB
     DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // B5 OP_AND_INT_2ADDR vA, vB
+    // B5 AND_INT_2ADDR vA, vB
     DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // B6 OP_OR_INT_2ADDR vA, vB
+    // B6 OR_INT_2ADDR vA, vB
     DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // B7 OP_XOR_INT_2ADDR vA, vB
+    // B7 XOR_INT_2ADDR vA, vB
     DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // B8 OP_SHL_INT_2ADDR vA, vB
+    // B8 SHL_INT_2ADDR vA, vB
     DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // B9 OP_SHR_INT_2ADDR vA, vB
+    // B9 SHR_INT_2ADDR vA, vB
     DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // BA OP_USHR_INT_2ADDR vA, vB
+    // BA USHR_INT_2ADDR vA, vB
     DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // BB OP_ADD_LONG_2ADDR vA, vB
+    // BB ADD_LONG_2ADDR vA, vB
     DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
 
-    // BC OP_SUB_LONG_2ADDR vA, vB
+    // BC SUB_LONG_2ADDR vA, vB
     DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
 
-    // BD OP_MUL_LONG_2ADDR vA, vB
+    // BD MUL_LONG_2ADDR vA, vB
     DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
 
-    // BE OP_DIV_LONG_2ADDR vA, vB
+    // BE DIV_LONG_2ADDR vA, vB
     DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
 
-    // BF OP_REM_LONG_2ADDR vA, vB
+    // BF REM_LONG_2ADDR vA, vB
     DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
 
-    // C0 OP_AND_LONG_2ADDR vA, vB
+    // C0 AND_LONG_2ADDR vA, vB
     DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
 
-    // C1 OP_OR_LONG_2ADDR vA, vB
+    // C1 OR_LONG_2ADDR vA, vB
     DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
 
-    // C2 OP_XOR_LONG_2ADDR vA, vB
+    // C2 XOR_LONG_2ADDR vA, vB
     DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
 
-    // C3 OP_SHL_LONG_2ADDR vA, vB
+    // C3 SHL_LONG_2ADDR vA, vB
     DF_DA_WIDE | DF_UA_WIDE | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // C4 OP_SHR_LONG_2ADDR vA, vB
+    // C4 SHR_LONG_2ADDR vA, vB
     DF_DA_WIDE | DF_UA_WIDE | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // C5 OP_USHR_LONG_2ADDR vA, vB
+    // C5 USHR_LONG_2ADDR vA, vB
     DF_DA_WIDE | DF_UA_WIDE | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // C6 OP_ADD_FLOAT_2ADDR vA, vB
+    // C6 ADD_FLOAT_2ADDR vA, vB
     DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
 
-    // C7 OP_SUB_FLOAT_2ADDR vA, vB
+    // C7 SUB_FLOAT_2ADDR vA, vB
     DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
 
-    // C8 OP_MUL_FLOAT_2ADDR vA, vB
+    // C8 MUL_FLOAT_2ADDR vA, vB
     DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
 
-    // C9 OP_DIV_FLOAT_2ADDR vA, vB
+    // C9 DIV_FLOAT_2ADDR vA, vB
     DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
 
-    // CA OP_REM_FLOAT_2ADDR vA, vB
+    // CA REM_FLOAT_2ADDR vA, vB
     DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
 
-    // CB OP_ADD_DOUBLE_2ADDR vA, vB
+    // CB ADD_DOUBLE_2ADDR vA, vB
     DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
 
-    // CC OP_SUB_DOUBLE_2ADDR vA, vB
+    // CC SUB_DOUBLE_2ADDR vA, vB
     DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
 
-    // CD OP_MUL_DOUBLE_2ADDR vA, vB
+    // CD MUL_DOUBLE_2ADDR vA, vB
     DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
 
-    // CE OP_DIV_DOUBLE_2ADDR vA, vB
+    // CE DIV_DOUBLE_2ADDR vA, vB
     DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
 
-    // CF OP_REM_DOUBLE_2ADDR vA, vB
+    // CF REM_DOUBLE_2ADDR vA, vB
     DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
 
-    // D0 OP_ADD_INT_LIT16 vA, vB, #+CCCC
+    // D0 ADD_INT_LIT16 vA, vB, #+CCCC
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // D1 OP_RSUB_INT vA, vB, #+CCCC
+    // D1 RSUB_INT vA, vB, #+CCCC
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // D2 OP_MUL_INT_LIT16 vA, vB, #+CCCC
+    // D2 MUL_INT_LIT16 vA, vB, #+CCCC
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // D3 OP_DIV_INT_LIT16 vA, vB, #+CCCC
+    // D3 DIV_INT_LIT16 vA, vB, #+CCCC
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // D4 OP_REM_INT_LIT16 vA, vB, #+CCCC
+    // D4 REM_INT_LIT16 vA, vB, #+CCCC
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // D5 OP_AND_INT_LIT16 vA, vB, #+CCCC
+    // D5 AND_INT_LIT16 vA, vB, #+CCCC
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // D6 OP_OR_INT_LIT16 vA, vB, #+CCCC
+    // D6 OR_INT_LIT16 vA, vB, #+CCCC
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // D7 OP_XOR_INT_LIT16 vA, vB, #+CCCC
+    // D7 XOR_INT_LIT16 vA, vB, #+CCCC
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // D8 OP_ADD_INT_LIT8 vAA, vBB, #+CC
+    // D8 ADD_INT_LIT8 vAA, vBB, #+CC
     DF_DA | DF_UB | DF_IS_LINEAR | DF_CORE_A | DF_CORE_B,
 
-    // D9 OP_RSUB_INT_LIT8 vAA, vBB, #+CC
+    // D9 RSUB_INT_LIT8 vAA, vBB, #+CC
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // DA OP_MUL_INT_LIT8 vAA, vBB, #+CC
+    // DA MUL_INT_LIT8 vAA, vBB, #+CC
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // DB OP_DIV_INT_LIT8 vAA, vBB, #+CC
+    // DB DIV_INT_LIT8 vAA, vBB, #+CC
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // DC OP_REM_INT_LIT8 vAA, vBB, #+CC
+    // DC REM_INT_LIT8 vAA, vBB, #+CC
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // DD OP_AND_INT_LIT8 vAA, vBB, #+CC
+    // DD AND_INT_LIT8 vAA, vBB, #+CC
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // DE OP_OR_INT_LIT8 vAA, vBB, #+CC
+    // DE OR_INT_LIT8 vAA, vBB, #+CC
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // DF OP_XOR_INT_LIT8 vAA, vBB, #+CC
+    // DF XOR_INT_LIT8 vAA, vBB, #+CC
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // E0 OP_SHL_INT_LIT8 vAA, vBB, #+CC
+    // E0 SHL_INT_LIT8 vAA, vBB, #+CC
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // E1 OP_SHR_INT_LIT8 vAA, vBB, #+CC
+    // E1 SHR_INT_LIT8 vAA, vBB, #+CC
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // E2 OP_USHR_INT_LIT8 vAA, vBB, #+CC
+    // E2 USHR_INT_LIT8 vAA, vBB, #+CC
     DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
-    // E3 OP_IGET_VOLATILE
+    // E3 IGET_VOLATILE
     DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_B,
 
-    // E4 OP_IPUT_VOLATILE
+    // E4 IPUT_VOLATILE
     DF_UA | DF_UB | DF_NULL_CHK_1 | DF_CORE_B,
 
-    // E5 OP_SGET_VOLATILE
+    // E5 SGET_VOLATILE
     DF_DA,
 
-    // E6 OP_SPUT_VOLATILE
+    // E6 SPUT_VOLATILE
     DF_UA,
 
-    // E7 OP_IGET_OBJECT_VOLATILE
+    // E7 IGET_OBJECT_VOLATILE
     DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_A | DF_CORE_B,
 
-    // E8 OP_IGET_WIDE_VOLATILE
+    // E8 IGET_WIDE_VOLATILE
     DF_DA_WIDE | DF_UB | DF_NULL_CHK_0 | DF_CORE_B,
 
-    // E9 OP_IPUT_WIDE_VOLATILE
+    // E9 IPUT_WIDE_VOLATILE
     DF_UA_WIDE | DF_UB | DF_NULL_CHK_1 | DF_CORE_B,
 
-    // EA OP_SGET_WIDE_VOLATILE
+    // EA SGET_WIDE_VOLATILE
     DF_DA_WIDE,
 
-    // EB OP_SPUT_WIDE_VOLATILE
+    // EB SPUT_WIDE_VOLATILE
     DF_UA_WIDE,
 
-    // EC OP_BREAKPOINT
+    // EC BREAKPOINT
     DF_NOP,
 
-    // ED OP_THROW_VERIFICATION_ERROR
+    // ED THROW_VERIFICATION_ERROR
     DF_NOP,
 
-    // EE OP_EXECUTE_INLINE
+    // EE EXECUTE_INLINE
     DF_FORMAT_35C,
 
-    // EF OP_EXECUTE_INLINE_RANGE
+    // EF EXECUTE_INLINE_RANGE
     DF_FORMAT_3RC,
 
-    // F0 OP_INVOKE_OBJECT_INIT_RANGE
+    // F0 INVOKE_OBJECT_INIT_RANGE
     DF_NOP | DF_NULL_CHK_0,
 
-    // F1 OP_RETURN_VOID_BARRIER
+    // F1 RETURN_VOID_BARRIER
     DF_NOP,
 
-    // F2 OP_IGET_QUICK
+    // F2 IGET_QUICK
     DF_DA | DF_UB | DF_NULL_CHK_0 | DF_IS_GETTER,
 
-    // F3 OP_IGET_WIDE_QUICK
+    // F3 IGET_WIDE_QUICK
     DF_DA_WIDE | DF_UB | DF_NULL_CHK_0 | DF_IS_GETTER,
 
-    // F4 OP_IGET_OBJECT_QUICK
+    // F4 IGET_OBJECT_QUICK
     DF_DA | DF_UB | DF_NULL_CHK_0 | DF_IS_GETTER,
 
-    // F5 OP_IPUT_QUICK
+    // F5 IPUT_QUICK
     DF_UA | DF_UB | DF_NULL_CHK_1 | DF_IS_SETTER,
 
-    // F6 OP_IPUT_WIDE_QUICK
+    // F6 IPUT_WIDE_QUICK
     DF_UA_WIDE | DF_UB | DF_NULL_CHK_1 |DF_IS_SETTER,
 
-    // F7 OP_IPUT_OBJECT_QUICK
+    // F7 IPUT_OBJECT_QUICK
     DF_UA | DF_UB | DF_NULL_CHK_1 | DF_IS_SETTER,
 
-    // F8 OP_INVOKE_VIRTUAL_QUICK
+    // F8 INVOKE_VIRTUAL_QUICK
     DF_FORMAT_35C | DF_NULL_CHK_OUT0,
 
-    // F9 OP_INVOKE_VIRTUAL_QUICK_RANGE
+    // F9 INVOKE_VIRTUAL_QUICK_RANGE
     DF_FORMAT_3RC | DF_NULL_CHK_OUT0,
 
-    // FA OP_INVOKE_SUPER_QUICK
+    // FA INVOKE_SUPER_QUICK
     DF_FORMAT_35C | DF_NULL_CHK_OUT0,
 
-    // FB OP_INVOKE_SUPER_QUICK_RANGE
+    // FB INVOKE_SUPER_QUICK_RANGE
     DF_FORMAT_3RC | DF_NULL_CHK_OUT0,
 
-    // FC OP_IPUT_OBJECT_VOLATILE
+    // FC IPUT_OBJECT_VOLATILE
     DF_UA | DF_UB | DF_NULL_CHK_1 | DF_CORE_A | DF_CORE_B,
 
-    // FD OP_SGET_OBJECT_VOLATILE
+    // FD SGET_OBJECT_VOLATILE
     DF_DA | DF_CORE_A,
 
-    // FE OP_SPUT_OBJECT_VOLATILE
+    // FE SPUT_OBJECT_VOLATILE
     DF_UA | DF_CORE_A,
 
-    // FF OP_UNUSED_FF
+    // FF UNUSED_FF
     DF_NOP,
 
     // Beginning of extended MIR opcodes
-    // 100 OP_MIR_PHI
+    // 100 MIR_PHI
     DF_PHI | DF_DA | DF_NULL_TRANSFER_N,
     /*
      * For extended MIR inserted at the MIR2LIR stage, it is okay to have
@@ -820,10 +819,10 @@
  * ssaToDalvikMap list to get the subscript[31..16]/dalvik_reg[15..0] mapping.
  */
 char* oatGetDalvikDisassembly(CompilationUnit* cUnit,
-                              const DecodedInstruction* insn, const char* note)
+                              const DecodedInstruction& insn, const char* note)
 {
     char buffer[256];
-    Opcode opcode = insn->opcode;
+    Instruction::Code opcode = insn.opcode;
     int dfAttributes = oatDataFlowAttributes[opcode];
     int flags;
     char* ret;
@@ -832,37 +831,35 @@
     if ((int)opcode >= (int)kMirOpFirst) {
         if ((int)opcode == (int)kMirOpPhi) {
             strcpy(buffer, "PHI");
-        }
-        else {
+        } else {
             sprintf(buffer, "Opcode %#x", opcode);
         }
         flags = 0;
     } else {
-        strcpy(buffer, dexGetOpcodeName(opcode));
-        flags = dexGetFlagsFromOpcode(insn->opcode);
+        strcpy(buffer, Instruction::Name(opcode));
+        flags = Instruction::Flags(opcode);
     }
 
     if (note)
         strcat(buffer, note);
 
     /* For branches, decode the instructions to print out the branch targets */
-    if (flags & kInstrCanBranch) {
-        InstructionFormat dalvikFormat = dexGetFormatFromOpcode(insn->opcode);
+    if (flags & Instruction::kBranch) {
+        Instruction::Format dalvikFormat = Instruction::FormatOf(insn.opcode);
         int offset = 0;
         switch (dalvikFormat) {
-            case kFmt21t:
-                snprintf(buffer + strlen(buffer), 256, " v%d,", insn->vA);
-                offset = (int) insn->vB;
+            case Instruction::k21t:
+                snprintf(buffer + strlen(buffer), 256, " v%d,", insn.vA);
+                offset = (int) insn.vB;
                 break;
-            case kFmt22t:
-                snprintf(buffer + strlen(buffer), 256, " v%d, v%d,",
-                         insn->vA, insn->vB);
-                offset = (int) insn->vC;
+            case Instruction::k22t:
+                snprintf(buffer + strlen(buffer), 256, " v%d, v%d,", insn.vA, insn.vB);
+                offset = (int) insn.vC;
                 break;
-            case kFmt10t:
-            case kFmt20t:
-            case kFmt30t:
-                offset = (int) insn->vA;
+            case Instruction::k10t:
+            case Instruction::k20t:
+            case Instruction::k30t:
+                offset = (int) insn.vA;
                 break;
             default:
                 LOG(FATAL) << "Unexpected branch format " << (int)dalvikFormat
@@ -873,30 +870,30 @@
                  offset > 0 ? offset : -offset);
     } else if (dfAttributes & DF_FORMAT_35C) {
         unsigned int i;
-        for (i = 0; i < insn->vA; i++) {
+        for (i = 0; i < insn.vA; i++) {
             if (i != 0) strcat(buffer, ",");
-            snprintf(buffer + strlen(buffer), 256, " v%d", insn->arg[i]);
+            snprintf(buffer + strlen(buffer), 256, " v%d", insn.arg[i]);
         }
     }
     else if (dfAttributes & DF_FORMAT_3RC) {
         snprintf(buffer + strlen(buffer), 256,
-                 " v%d..v%d", insn->vC, insn->vC + insn->vA - 1);
+                 " v%d..v%d", insn.vC, insn.vC + insn.vA - 1);
     }
     else {
         if (dfAttributes & DF_A_IS_REG) {
-            snprintf(buffer + strlen(buffer), 256, " v%d", insn->vA);
+            snprintf(buffer + strlen(buffer), 256, " v%d", insn.vA);
         }
         if (dfAttributes & DF_B_IS_REG) {
-            snprintf(buffer + strlen(buffer), 256, ", v%d", insn->vB);
+            snprintf(buffer + strlen(buffer), 256, ", v%d", insn.vB);
         }
         else if ((int)opcode < (int)kMirOpFirst) {
-            snprintf(buffer + strlen(buffer), 256, ", (#%d)", insn->vB);
+            snprintf(buffer + strlen(buffer), 256, ", (#%d)", insn.vB);
         }
         if (dfAttributes & DF_C_IS_REG) {
-            snprintf(buffer + strlen(buffer), 256, ", v%d", insn->vC);
+            snprintf(buffer + strlen(buffer), 256, ", v%d", insn.vC);
         }
         else if ((int)opcode < (int)kMirOpFirst) {
-            snprintf(buffer + strlen(buffer), 256, ", (#%d)", insn->vC);
+            snprintf(buffer + strlen(buffer), 256, ", (#%d)", insn.vC);
         }
     }
     int length = strlen(buffer) + 1;
@@ -921,16 +918,15 @@
 {
     char buffer[256];
     char operand0[32], operand1[32];
-    const DecodedInstruction *insn = &mir->dalvikInsn;
-    int opcode = insn->opcode;
+    const DecodedInstruction* insn = &mir->dalvikInsn;
+    Instruction::Code opcode = insn->opcode;
     int dfAttributes = oatDataFlowAttributes[opcode];
     char* ret;
     int length;
-    OpcodeFlags flags;
 
     buffer[0] = 0;
-    if (opcode >= kMirOpFirst) {
-        if (opcode == kMirOpPhi) {
+    if (static_cast<int>(opcode) >= static_cast<int>(kMirOpFirst)) {
+        if (static_cast<int>(opcode) == static_cast<int>(kMirOpPhi)) {
             snprintf(buffer, 256, "PHI %s = (%s",
                      getSSAName(cUnit, mir->ssaRep->defs[0], operand0),
                      getSSAName(cUnit, mir->ssaRep->uses[0], operand1));
@@ -946,29 +942,28 @@
         }
         goto done;
     } else {
-        strcpy(buffer, dexGetOpcodeName((Opcode)opcode));
+        strcpy(buffer, Instruction::Name(opcode));
     }
 
-    flags = dexGetFlagsFromOpcode((Opcode)opcode);
     /* For branches, decode the instructions to print out the branch targets */
-    if (flags & kInstrCanBranch) {
-        InstructionFormat dalvikFormat = dexGetFormatFromOpcode(insn->opcode);
+    if (Instruction::Flags(insn->opcode) & Instruction::kBranch) {
+        Instruction::Format dalvikFormat = Instruction::FormatOf(insn->opcode);
         int delta = 0;
         switch (dalvikFormat) {
-            case kFmt21t:
+            case Instruction::k21t:
                 snprintf(buffer + strlen(buffer), 256, " %s, ",
                          getSSAName(cUnit, mir->ssaRep->uses[0], operand0));
                 delta = (int) insn->vB;
                 break;
-            case kFmt22t:
+            case Instruction::k22t:
                 snprintf(buffer + strlen(buffer), 256, " %s, %s, ",
                          getSSAName(cUnit, mir->ssaRep->uses[0], operand0),
                          getSSAName(cUnit, mir->ssaRep->uses[1], operand1));
                 delta = (int) insn->vC;
                 break;
-            case kFmt10t:
-            case kFmt20t:
-            case kFmt30t:
+            case Instruction::k10t:
+            case Instruction::k20t:
+            case Instruction::k30t:
                 delta = (int) insn->vA;
                 break;
             default:
@@ -1003,27 +998,25 @@
                          getSSAName(cUnit, mir->ssaRep->uses[udIdx], operand0));
             }
         }
-        if (opcode < kMirOpFirst) {
-            InstructionFormat dalvikFormat =
-                dexGetFormatFromOpcode((Opcode)opcode);
+        if (static_cast<int>(opcode) < static_cast<int>(kMirOpFirst)) {
+            Instruction::Format dalvikFormat = Instruction::FormatOf(opcode);
             switch (dalvikFormat) {
-                case kFmt11n:        // op vA, #+B
-                case kFmt21s:        // op vAA, #+BBBB
-                case kFmt21h:        // op vAA, #+BBBB00000[00000000]
-                case kFmt31i:        // op vAA, #+BBBBBBBB
-                case kFmt51l:        // op vAA, #+BBBBBBBBBBBBBBBB
+                case Instruction::k11n:        // op vA, #+B
+                case Instruction::k21s:        // op vAA, #+BBBB
+                case Instruction::k21h:        // op vAA, #+BBBB00000[00000000]
+                case Instruction::k31i:        // op vAA, #+BBBBBBBB
+                case Instruction::k51l:        // op vAA, #+BBBBBBBBBBBBBBBB
                     snprintf(buffer + strlen(buffer), 256, " #%#x", insn->vB);
                     break;
-                case kFmt21c:        // op vAA, thing@BBBB
-                case kFmt31c:        // op vAA, thing@BBBBBBBB
+                case Instruction::k21c:        // op vAA, thing@BBBB
+                case Instruction::k31c:        // op vAA, thing@BBBBBBBB
                     snprintf(buffer + strlen(buffer), 256, " @%#x", insn->vB);
                     break;
-                case kFmt22b:        // op vAA, vBB, #+CC
-                case kFmt22s:        // op vA, vB, #+CCCC
+                case Instruction::k22b:        // op vAA, vBB, #+CC
+                case Instruction::k22s:        // op vA, vB, #+CCCC
                     snprintf(buffer + strlen(buffer), 256, " #%#x", insn->vC);
                     break;
-                case kFmt22c:        // op vA, vB, thing@CCCC
-                case kFmt22cs:       // [opt] op vA, vB, field offset CCCC
+                case Instruction::k22c:        // op vA, vB, thing@CCCC
                     snprintf(buffer + strlen(buffer), 256, " @%#x", insn->vC);
                     break;
                     /* No need for special printing */
@@ -1243,14 +1236,14 @@
             oatDataFlowAttributes[mir->dalvikInsn.opcode];
 
         // If not a pseudo-op, note non-leaf or can throw
-        if (mir->dalvikInsn.opcode < kNumPackedOpcodes) {
-            int flags = dexGetFlagsFromOpcode(mir->dalvikInsn.opcode);
+        if (static_cast<int>(mir->dalvikInsn.opcode) < static_cast<int>(kNumPackedOpcodes)) {
+            int flags = Instruction::Flags(mir->dalvikInsn.opcode);
 
-            if (flags & kInstrCanThrow) {
+            if (flags & Instruction::kThrow) {
                 cUnit->attrs &= ~METHOD_IS_THROW_FREE;
             }
 
-            if (flags & kInstrInvoke) {
+            if (flags & Instruction::kInvoke) {
                 cUnit->attrs &= ~METHOD_IS_LEAF;
             }
         }
@@ -1392,12 +1385,12 @@
         if (dfAttributes & DF_SETS_CONST) {
             if (dfAttributes & DF_DA) {
                 switch (dInsn->opcode) {
-                    case OP_CONST_4:
-                    case OP_CONST_16:
-                    case OP_CONST:
+                    case Instruction::CONST_4:
+                    case Instruction::CONST_16:
+                    case Instruction::CONST:
                         setConstant(cUnit, mir->ssaRep->defs[0], dInsn->vB);
                         break;
-                    case OP_CONST_HIGH16:
+                    case Instruction::CONST_HIGH16:
                         setConstant(cUnit, mir->ssaRep->defs[0],
                                     dInsn->vB << 16);
                         break;
@@ -1406,18 +1399,18 @@
                 }
             } else if (dfAttributes & DF_DA_WIDE) {
                 switch (dInsn->opcode) {
-                    case OP_CONST_WIDE_16:
-                    case OP_CONST_WIDE_32:
+                    case Instruction::CONST_WIDE_16:
+                    case Instruction::CONST_WIDE_32:
                         setConstant(cUnit, mir->ssaRep->defs[0], dInsn->vB);
                         setConstant(cUnit, mir->ssaRep->defs[1], 0);
                         break;
-                    case OP_CONST_WIDE:
+                    case Instruction::CONST_WIDE:
                         setConstant(cUnit, mir->ssaRep->defs[0],
                                     (int) dInsn->vB_wide);
                         setConstant(cUnit, mir->ssaRep->defs[1],
                                     (int) (dInsn->vB_wide >> 32));
                         break;
-                    case OP_CONST_WIDE_HIGH16:
+                    case Instruction::CONST_WIDE_HIGH16:
                         setConstant(cUnit, mir->ssaRep->defs[0], 0);
                         setConstant(cUnit, mir->ssaRep->defs[1],
                                     dInsn->vB << 16);
@@ -1698,8 +1691,8 @@
         // Mark non-null returns from invoke-style NEW*
         if (dfAttributes & DF_NON_NULL_RET) {
             MIR* nextMir = mir->next;
-            // Next should be an OP_MOVE_RESULT_OBJECT
-            if (nextMir && nextMir->dalvikInsn.opcode == OP_MOVE_RESULT_OBJECT) {
+            // Next should be an MOVE_RESULT_OBJECT
+            if (nextMir && nextMir->dalvikInsn.opcode == Instruction::MOVE_RESULT_OBJECT) {
                 // Mark as null checked
                 oatSetBit(cUnit, cUnit->tempSSARegisterV,
                           nextMir->ssaRep->defs[0]);
@@ -1715,8 +1708,8 @@
                        if ((int)tmir->dalvikInsn.opcode >= (int)kMirOpFirst) {
                            continue;
                        }
-                       // First non-pseudo should be OP_MOVE_RESULT_OBJECT
-                       if (tmir->dalvikInsn.opcode == OP_MOVE_RESULT_OBJECT) {
+                       // First non-pseudo should be MOVE_RESULT_OBJECT
+                       if (tmir->dalvikInsn.opcode == Instruction::MOVE_RESULT_OBJECT) {
                            // Mark as null checked
                            oatSetBit(cUnit, cUnit->tempSSARegisterV,
                                      tmir->ssaRep->defs[0]);
diff --git a/src/compiler/Frontend.cc b/src/compiler/Frontend.cc
index 92ffefc..d7bf51f 100644
--- a/src/compiler/Frontend.cc
+++ b/src/compiler/Frontend.cc
@@ -51,66 +51,63 @@
 
 inline bool contentIsInsn(const u2* codePtr) {
     u2 instr = *codePtr;
-    Opcode opcode = (Opcode)(instr & 0xff);
+    Instruction::Code opcode = (Instruction::Code)(instr & 0xff);
 
     /*
-     * Since the low 8-bit in metadata may look like OP_NOP, we need to check
+     * Since the low 8-bit in metadata may look like NOP, we need to check
      * both the low and whole sub-word to determine whether it is code or data.
      */
-    return (opcode != OP_NOP || instr == 0);
+    return (opcode != Instruction::NOP || instr == 0);
 }
 
 /*
  * Parse an instruction, return the length of the instruction
  */
 inline int parseInsn(CompilationUnit* cUnit, const u2* codePtr,
-                            DecodedInstruction* decInsn, bool printMe)
+                     DecodedInstruction* decoded_instruction, bool printMe)
 {
-    // Don't parse instruction data
-    if (!contentIsInsn(codePtr)) {
-        return 0;
-    }
+  // Don't parse instruction data
+  if (!contentIsInsn(codePtr)) {
+    return 0;
+  }
 
-    u2 instr = *codePtr;
-    Opcode opcode = dexOpcodeFromCodeUnit(instr);
+  const Instruction* instruction = Instruction::At(codePtr);
+  *decoded_instruction = DecodedInstruction(instruction);
 
-    dexDecodeInstruction(codePtr, decInsn);
-    if (printMe) {
-        char* decodedString = oatGetDalvikDisassembly(cUnit, decInsn, NULL);
-        LOG(INFO) << codePtr << ": 0x" << std::hex << (int)opcode <<
-        " " << decodedString;
-    }
-    return dexGetWidthFromOpcode(opcode);
+  if (printMe) {
+    char* decodedString = oatGetDalvikDisassembly(cUnit, *decoded_instruction, NULL);
+    LOG(INFO) << codePtr << ": 0x" << std::hex << static_cast<int>(decoded_instruction->opcode)
+              << " " << decodedString;
+  }
+  return instruction->SizeInCodeUnits();
 }
 
 #define UNKNOWN_TARGET 0xffffffff
 
-inline bool isGoto(MIR* insn)
-{
-    switch (insn->dalvikInsn.opcode) {
-        case OP_GOTO:
-        case OP_GOTO_16:
-        case OP_GOTO_32:
-            return true;
-        default:
-            return false;
+inline bool isGoto(MIR* insn) {
+  switch (insn->dalvikInsn.opcode) {
+    case Instruction::GOTO:
+    case Instruction::GOTO_16:
+    case Instruction::GOTO_32:
+      return true;
+    default:
+      return false;
     }
 }
 
 /*
  * Identify unconditional branch instructions
  */
-inline bool isUnconditionalBranch(MIR* insn)
-{
-    switch (insn->dalvikInsn.opcode) {
-        case OP_RETURN_VOID:
-        case OP_RETURN:
-        case OP_RETURN_WIDE:
-        case OP_RETURN_OBJECT:
-            return true;
-        default:
-            return isGoto(insn);
-    }
+inline bool isUnconditionalBranch(MIR* insn) {
+  switch (insn->dalvikInsn.opcode) {
+    case Instruction::RETURN_VOID:
+    case Instruction::RETURN:
+    case Instruction::RETURN_WIDE:
+    case Instruction::RETURN_OBJECT:
+      return true;
+    default:
+      return isGoto(insn);
+  }
 }
 
 /* Split an existing block from the specified code offset into two */
@@ -301,9 +298,7 @@
                     bb->firstMIRInsn ? " | " : " ");
             for (mir = bb->firstMIRInsn; mir; mir = mir->next) {
                 fprintf(file, "    {%04x %s\\l}%s\\\n", mir->offset,
-                        mir->ssaRep ?
-                            oatFullDisassembler(cUnit, mir) :
-                            dexGetOpcodeName(mir->dalvikInsn.opcode),
+                        mir->ssaRep ? oatFullDisassembler(cUnit, mir) : Instruction::Name(mir->dalvikInsn.opcode),
                         mir->next ? " | " : " ");
             }
             fprintf(file, "  }\"];\n\n");
@@ -479,37 +474,37 @@
     }
 }
 
-/* Process instructions with the kInstrCanBranch flag */
+/* Process instructions with the kBranch flag */
 BasicBlock* processCanBranch(CompilationUnit* cUnit, BasicBlock* curBlock,
                              MIR* insn, int curOffset, int width, int flags,
                              const u2* codePtr, const u2* codeEnd)
 {
     int target = curOffset;
     switch (insn->dalvikInsn.opcode) {
-        case OP_GOTO:
-        case OP_GOTO_16:
-        case OP_GOTO_32:
+        case Instruction::GOTO:
+        case Instruction::GOTO_16:
+        case Instruction::GOTO_32:
             target += (int) insn->dalvikInsn.vA;
             break;
-        case OP_IF_EQ:
-        case OP_IF_NE:
-        case OP_IF_LT:
-        case OP_IF_GE:
-        case OP_IF_GT:
-        case OP_IF_LE:
+        case Instruction::IF_EQ:
+        case Instruction::IF_NE:
+        case Instruction::IF_LT:
+        case Instruction::IF_GE:
+        case Instruction::IF_GT:
+        case Instruction::IF_LE:
             target += (int) insn->dalvikInsn.vC;
             break;
-        case OP_IF_EQZ:
-        case OP_IF_NEZ:
-        case OP_IF_LTZ:
-        case OP_IF_GEZ:
-        case OP_IF_GTZ:
-        case OP_IF_LEZ:
+        case Instruction::IF_EQZ:
+        case Instruction::IF_NEZ:
+        case Instruction::IF_LTZ:
+        case Instruction::IF_GEZ:
+        case Instruction::IF_GTZ:
+        case Instruction::IF_LEZ:
             target += (int) insn->dalvikInsn.vB;
             break;
         default:
             LOG(FATAL) << "Unexpected opcode(" << (int)insn->dalvikInsn.opcode
-                << ") with kInstrCanBranch set";
+                << ") with kBranch set";
     }
     BasicBlock *takenBlock = findBlock(cUnit, target,
                                        /* split */
@@ -522,7 +517,7 @@
     oatInsertGrowableList(cUnit, takenBlock->predecessors, (intptr_t)curBlock);
 
     /* Always terminate the current block for conditional branches */
-    if (flags & kInstrCanContinue) {
+    if (flags & Instruction::kContinue) {
         BasicBlock *fallthroughBlock = findBlock(cUnit,
                                                  curOffset +  width,
                                                  /*
@@ -546,7 +541,7 @@
         oatInsertGrowableList(cUnit, fallthroughBlock->predecessors,
                               (intptr_t)curBlock);
     } else if (codePtr < codeEnd) {
-        /* Create a fallthrough block for real instructions (incl. OP_NOP) */
+        /* Create a fallthrough block for real instructions (incl. NOP) */
         if (contentIsInsn(codePtr)) {
             findBlock(cUnit, curOffset + width,
                       /* split */
@@ -560,7 +555,7 @@
     return curBlock;
 }
 
-/* Process instructions with the kInstrCanSwitch flag */
+/* Process instructions with the kSwitch flag */
 void processCanSwitch(CompilationUnit* cUnit, BasicBlock* curBlock,
                       MIR* insn, int curOffset, int width, int flags)
 {
@@ -581,8 +576,8 @@
      *
      * Total size is (4+size*2) 16-bit code units.
      */
-    if (insn->dalvikInsn.opcode == OP_PACKED_SWITCH) {
-        DCHECK_EQ(switchData[0], kPackedSwitchSignature);
+    if (insn->dalvikInsn.opcode == Instruction::PACKED_SWITCH) {
+        DCHECK_EQ(static_cast<int>(switchData[0]), static_cast<int>(Instruction::kPackedSwitchSignature));
         size = switchData[1];
         firstKey = switchData[2] | (switchData[3] << 16);
         targetTable = (int *) &switchData[4];
@@ -597,7 +592,7 @@
      * Total size is (2+size*4) 16-bit code units.
      */
     } else {
-        DCHECK_EQ(switchData[0], kSparseSwitchSignature);
+        DCHECK_EQ(static_cast<int>(switchData[0]), static_cast<int>(Instruction::kSparseSwitchSignature));
         size = switchData[1];
         keyTable = (int *) &switchData[2];
         targetTable = (int *) &switchData[2 + size*2];
@@ -609,7 +604,7 @@
              (int)curBlock->successorBlockList.blockListType;
     }
     curBlock->successorBlockList.blockListType =
-        (insn->dalvikInsn.opcode == OP_PACKED_SWITCH) ?
+        (insn->dalvikInsn.opcode == Instruction::PACKED_SWITCH) ?
         kPackedSwitch : kSparseSwitch;
     oatInitGrowableList(cUnit, &curBlock->successorBlockList.blocks, size,
                         kListSuccessorBlocks);
@@ -626,7 +621,7 @@
             (SuccessorBlockInfo *) oatNew(cUnit, sizeof(SuccessorBlockInfo),
                                           false, kAllocSuccessor);
         successorBlockInfo->block = caseBlock;
-        successorBlockInfo->key = (insn->dalvikInsn.opcode == OP_PACKED_SWITCH)?
+        successorBlockInfo->key = (insn->dalvikInsn.opcode == Instruction::PACKED_SWITCH)?
                                   firstKey + i : keyTable[i];
         oatInsertGrowableList(cUnit, &curBlock->successorBlockList.blocks,
                               (intptr_t) successorBlockInfo);
@@ -648,7 +643,7 @@
                           (intptr_t)curBlock);
 }
 
-/* Process instructions with the kInstrCanThrow flag */
+/* Process instructions with the kThrow flag */
 void processCanThrow(CompilationUnit* cUnit, BasicBlock* curBlock, MIR* insn,
                      int curOffset, int width, int flags,
                      ArenaBitVector* tryBlockAddr, const u2* codePtr,
@@ -701,7 +696,7 @@
      * whether it is code or data.
      */
     if (codePtr < codeEnd) {
-        /* Create a fallthrough block for real instructions (incl. OP_NOP) */
+        /* Create a fallthrough block for real instructions (incl. NOP) */
         if (contentIsInsn(codePtr)) {
             BasicBlock *fallthroughBlock = findBlock(cUnit,
                                                      curOffset + width,
@@ -712,13 +707,13 @@
                                                      /* immedPredBlockP */
                                                      NULL);
             /*
-             * OP_THROW is an unconditional branch.  NOTE:
-             * OP_THROW_VERIFICATION_ERROR is also an unconditional
+             * THROW is an unconditional branch.  NOTE:
+             * THROW_VERIFICATION_ERROR is also an unconditional
              * branch, but we shouldn't treat it as such until we have
              * a dead code elimination pass (which won't be important
              * until inlining w/ constant propogation is implemented.
              */
-            if (insn->dalvikInsn.opcode != OP_THROW) {
+            if (insn->dalvikInsn.opcode != Instruction::THROW) {
                 curBlock->fallThrough = fallthroughBlock;
                 oatInsertGrowableList(cUnit, fallthroughBlock->predecessors,
                                       (intptr_t)curBlock);
@@ -866,7 +861,7 @@
         oatAppendMIR(curBlock, insn);
 
         codePtr += width;
-        int flags = dexGetFlagsFromOpcode(insn->dalvikInsn.opcode);
+        int flags = Instruction::Flags(insn->dalvikInsn.opcode);
 
         int dfFlags = oatDataFlowAttributes[insn->dalvikInsn.opcode];
 
@@ -874,10 +869,10 @@
             cUnit->defCount += (dfFlags & DF_DA_WIDE) ? 2 : 1;
         }
 
-        if (flags & kInstrCanBranch) {
+        if (flags & Instruction::kBranch) {
             curBlock = processCanBranch(cUnit.get(), curBlock, insn, curOffset,
                                         width, flags, codePtr, codeEnd);
-        } else if (flags & kInstrCanReturn) {
+        } else if (flags & Instruction::kReturn) {
             curBlock->fallThrough = exitBlock;
             oatInsertGrowableList(cUnit.get(), exitBlock->predecessors,
                                   (intptr_t)curBlock);
@@ -888,7 +883,7 @@
             if (codePtr < codeEnd) {
                 /*
                  * Create a fallthrough block for real instructions
-                 * (incl. OP_NOP).
+                 * (incl. NOP).
                  */
                 if (contentIsInsn(codePtr)) {
                     findBlock(cUnit.get(), curOffset + width,
@@ -900,10 +895,10 @@
                               NULL);
                 }
             }
-        } else if (flags & kInstrCanThrow) {
+        } else if (flags & Instruction::kThrow) {
             processCanThrow(cUnit.get(), curBlock, insn, curOffset, width, flags,
                             tryBlockAddr, codePtr, codeEnd);
-        } else if (flags & kInstrCanSwitch) {
+        } else if (flags & Instruction::kSwitch) {
             processCanSwitch(cUnit.get(), curBlock, insn, curOffset, width, flags);
         }
         curOffset += width;
@@ -925,8 +920,7 @@
                    curBlock->fallThrough == nextBlock ||
                    curBlock->fallThrough == exitBlock);
 
-            if ((curBlock->fallThrough == NULL) &&
-                (flags & kInstrCanContinue)) {
+            if ((curBlock->fallThrough == NULL) && (flags & Instruction::kContinue)) {
                 curBlock->fallThrough = nextBlock;
                 oatInsertGrowableList(cUnit.get(), nextBlock->predecessors,
                                       (intptr_t)curBlock);
diff --git a/src/compiler/Ralloc.cc b/src/compiler/Ralloc.cc
index 09c2b7e..7223d7b 100644
--- a/src/compiler/Ralloc.cc
+++ b/src/compiler/Ralloc.cc
@@ -72,8 +72,8 @@
 {
     SSARepresentation* res = NULL;
     for (; mir; mir = mir->next) {
-        if ((mir->dalvikInsn.opcode == OP_MOVE_RESULT) ||
-            (mir->dalvikInsn.opcode == OP_MOVE_RESULT_WIDE)) {
+      if ((mir->dalvikInsn.opcode == Instruction::MOVE_RESULT) ||
+          (mir->dalvikInsn.opcode == Instruction::MOVE_RESULT_WIDE)) {
             res = mir->ssaRep;
             break;
         }
@@ -156,11 +156,9 @@
             }
 
             // Special-case handling for format 35c/3rc invokes
-            Opcode opcode = mir->dalvikInsn.opcode;
-            int flags = (opcode >= kNumPackedOpcodes) ? 0 :
-                dexGetFlagsFromOpcode(opcode);
-            if ((flags & kInstrInvoke) &&
-                (attrs & (DF_FORMAT_35C | DF_FORMAT_3RC))) {
+            Instruction::Code opcode = mir->dalvikInsn.opcode;
+            int flags = (static_cast<int>(opcode) >= kNumPackedOpcodes) ? 0 : Instruction::Flags(mir->dalvikInsn.opcode);
+            if ((flags & Instruction::kInvoke) && (attrs & (DF_FORMAT_35C | DF_FORMAT_3RC))) {
                 DCHECK_EQ(next, 0);
                 int target_idx = mir->dalvikInsn.vB;
                 const char* shorty =
@@ -185,8 +183,8 @@
                 }
                 int numUses = mir->dalvikInsn.vA;
                 // If this is a non-static invoke, skip implicit "this"
-                if (((mir->dalvikInsn.opcode != OP_INVOKE_STATIC) &&
-                     (mir->dalvikInsn.opcode != OP_INVOKE_STATIC_RANGE))) {
+                if (((mir->dalvikInsn.opcode != Instruction::INVOKE_STATIC) &&
+                    (mir->dalvikInsn.opcode != Instruction::INVOKE_STATIC_RANGE))) {
                    cUnit->regLocation[ssaRep->uses[next]].defined = true;
                    cUnit->regLocation[ssaRep->uses[next]].core = true;
                    next++;
@@ -258,7 +256,7 @@
                  * during verification can eliminate some type information,
                  * leaving us confused.  The real fix here is either to
                  * add explicit type information to Dalvik byte codes,
-                 * or to recognize OP_THROW_VERIFICATION_ERROR as
+                 * or to recognize THROW_VERIFICATION_ERROR as
                  * an unconditional branch and support dead code elimination.
                  * As a workaround we can detect this situation and
                  * disable register promotion (which is the only thing that
diff --git a/src/compiler/SSATransformation.cc b/src/compiler/SSATransformation.cc
index 352828f..cdb711e 100644
--- a/src/compiler/SSATransformation.cc
+++ b/src/compiler/SSATransformation.cc
@@ -644,7 +644,7 @@
             /* Variable will be clobbered before being used - no need for phi */
             if (!oatIsBitSet(phiBB->dataFlowInfo->liveInV, dalvikReg)) continue;
             MIR *phi = (MIR *) oatNew(cUnit, sizeof(MIR), true, kAllocDFInfo);
-            phi->dalvikInsn.opcode = (Opcode)kMirOpPhi;
+            phi->dalvikInsn.opcode = (Instruction::Code)kMirOpPhi;
             phi->dalvikInsn.vA = dalvikReg;
             phi->offset = phiBB->startOffset;
             phi->meta.phiNext = cUnit->phiList;
@@ -666,7 +666,7 @@
 
     /* Phi nodes are at the beginning of each block */
     for (mir = bb->firstMIRInsn; mir; mir = mir->next) {
-        if (mir->dalvikInsn.opcode != (Opcode)kMirOpPhi)
+        if (mir->dalvikInsn.opcode != (Instruction::Code)kMirOpPhi)
             return true;
         int ssaReg = mir->ssaRep->defs[0];
         int encodedDalvikValue =
diff --git a/src/compiler/codegen/CodegenUtil.cc b/src/compiler/codegen/CodegenUtil.cc
index 9186e23..3cb426f 100644
--- a/src/compiler/codegen/CodegenUtil.cc
+++ b/src/compiler/codegen/CodegenUtil.cc
@@ -603,7 +603,7 @@
         if (cUnit->printMe) {
             LOG(INFO) << "Switch table for offset 0x" << std::hex << bxOffset;
         }
-        if (tabRec->table[0] == kSparseSwitchSignature) {
+        if (tabRec->table[0] == Instruction::kSparseSwitchSignature) {
             int* keys = (int*)&(tabRec->table[2]);
             for (int elems = 0; elems < tabRec->table[1]; elems++) {
                 int disp = tabRec->targets[elems]->offset - bxOffset;
@@ -617,7 +617,7 @@
                     tabRec->targets[elems]->offset - bxOffset);
             }
         } else {
-            DCHECK_EQ(tabRec->table[0], kPackedSwitchSignature);
+            DCHECK_EQ(static_cast<int>(tabRec->table[0]), static_cast<int>(Instruction::kPackedSwitchSignature));
             for (int elems = 0; elems < tabRec->table[1]; elems++) {
                 int disp = tabRec->targets[elems]->offset - bxOffset;
                 if (cUnit->printMe) {
@@ -690,10 +690,10 @@
              &iterator);
         if (tabRec == NULL) break;
         tabRec->offset = offset;
-        if (tabRec->table[0] == kSparseSwitchSignature) {
+        if (tabRec->table[0] == Instruction::kSparseSwitchSignature) {
             offset += tabRec->table[1] * (sizeof(int) * 2);
         } else {
-            DCHECK_EQ(tabRec->table[0], kPackedSwitchSignature);
+            DCHECK_EQ(static_cast<int>(tabRec->table[0]), static_cast<int>(Instruction::kPackedSwitchSignature));
             offset += tabRec->table[1] * sizeof(int);
         }
     }
@@ -838,11 +838,11 @@
         SwitchTable *tabRec = (SwitchTable *) oatGrowableListIteratorNext(
              &iterator);
         if (tabRec == NULL) break;
-        if (tabRec->table[0] == kPackedSwitchSignature)
+        if (tabRec->table[0] == Instruction::kPackedSwitchSignature) {
             markPackedCaseLabels(cUnit, tabRec);
-        else if (tabRec->table[0] == kSparseSwitchSignature)
+        } else if (tabRec->table[0] == Instruction::kSparseSwitchSignature) {
             markSparseCaseLabels(cUnit, tabRec);
-        else {
+        } else {
             LOG(FATAL) << "Invalid switch table";
         }
     }
diff --git a/src/compiler/codegen/GenCommon.cc b/src/compiler/codegen/GenCommon.cc
index 1c4e6c8..6792f61 100644
--- a/src/compiler/codegen/GenCommon.cc
+++ b/src/compiler/codegen/GenCommon.cc
@@ -115,24 +115,24 @@
     ConditionCode cond;
     rlSrc1 = loadValue(cUnit, rlSrc1, kCoreReg);
     rlSrc2 = loadValue(cUnit, rlSrc2, kCoreReg);
-    Opcode opcode = mir->dalvikInsn.opcode;
+    Instruction::Code opcode = mir->dalvikInsn.opcode;
     switch(opcode) {
-        case OP_IF_EQ:
+        case Instruction::IF_EQ:
             cond = kCondEq;
             break;
-        case OP_IF_NE:
+        case Instruction::IF_NE:
             cond = kCondNe;
             break;
-        case OP_IF_LT:
+        case Instruction::IF_LT:
             cond = kCondLt;
             break;
-        case OP_IF_GE:
+        case Instruction::IF_GE:
             cond = kCondGe;
             break;
-        case OP_IF_GT:
+        case Instruction::IF_GT:
             cond = kCondGt;
             break;
-        case OP_IF_LE:
+        case Instruction::IF_LE:
             cond = kCondLe;
             break;
         default:
@@ -154,24 +154,24 @@
 {
     ConditionCode cond;
     rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
-    Opcode opcode = mir->dalvikInsn.opcode;
+    Instruction::Code opcode = mir->dalvikInsn.opcode;
     switch(opcode) {
-        case OP_IF_EQZ:
+        case Instruction::IF_EQZ:
             cond = kCondEq;
             break;
-        case OP_IF_NEZ:
+        case Instruction::IF_NEZ:
             cond = kCondNe;
             break;
-        case OP_IF_LTZ:
+        case Instruction::IF_LTZ:
             cond = kCondLt;
             break;
-        case OP_IF_GEZ:
+        case Instruction::IF_GEZ:
             cond = kCondGe;
             break;
-        case OP_IF_GTZ:
+        case Instruction::IF_GTZ:
             cond = kCondGt;
             break;
-        case OP_IF_LEZ:
+        case Instruction::IF_LEZ:
             cond = kCondLe;
             break;
         default:
@@ -208,13 +208,13 @@
      RegLocation rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
      OpKind op = kOpInvalid;
      switch(mir->dalvikInsn.opcode) {
-         case OP_INT_TO_BYTE:
+         case Instruction::INT_TO_BYTE:
              op = kOp2Byte;
              break;
-         case OP_INT_TO_SHORT:
+         case Instruction::INT_TO_SHORT:
               op = kOp2Short;
               break;
-         case OP_INT_TO_CHAR:
+         case Instruction::INT_TO_CHAR:
               op = kOp2Char;
               break;
          default:
@@ -280,7 +280,7 @@
     loadConstant(cUnit, rARG2, elems);               // arg2 <- count
     callRuntimeHelper(cUnit, rTgt);
     /*
-     * NOTE: the implicit target for OP_FILLED_NEW_ARRAY is the
+     * NOTE: the implicit target for Instruction::FILLED_NEW_ARRAY is the
      * return region.  Because AllocFromCode placed the new array
      * in rRET0, we'll just lock it into place.  When debugger support is
      * added, it may be necessary to additionally copy all return
@@ -1383,16 +1383,16 @@
     int funcOffset;
 
     switch( mir->dalvikInsn.opcode) {
-        case OP_SHL_LONG:
-        case OP_SHL_LONG_2ADDR:
+        case Instruction::SHL_LONG:
+        case Instruction::SHL_LONG_2ADDR:
             funcOffset = OFFSETOF_MEMBER(Thread, pShlLong);
             break;
-        case OP_SHR_LONG:
-        case OP_SHR_LONG_2ADDR:
+        case Instruction::SHR_LONG:
+        case Instruction::SHR_LONG_2ADDR:
             funcOffset = OFFSETOF_MEMBER(Thread, pShrLong);
             break;
-        case OP_USHR_LONG:
-        case OP_USHR_LONG_2ADDR:
+        case Instruction::USHR_LONG:
+        case Instruction::USHR_LONG_2ADDR:
             funcOffset = OFFSETOF_MEMBER(Thread, pUshrLong);
             break;
         default:
@@ -1423,65 +1423,65 @@
     bool shiftOp = false;
 
     switch (mir->dalvikInsn.opcode) {
-        case OP_NEG_INT:
+        case Instruction::NEG_INT:
             op = kOpNeg;
             unary = true;
             break;
-        case OP_NOT_INT:
+        case Instruction::NOT_INT:
             op = kOpMvn;
             unary = true;
             break;
-        case OP_ADD_INT:
-        case OP_ADD_INT_2ADDR:
+        case Instruction::ADD_INT:
+        case Instruction::ADD_INT_2ADDR:
             op = kOpAdd;
             break;
-        case OP_SUB_INT:
-        case OP_SUB_INT_2ADDR:
+        case Instruction::SUB_INT:
+        case Instruction::SUB_INT_2ADDR:
             op = kOpSub;
             break;
-        case OP_MUL_INT:
-        case OP_MUL_INT_2ADDR:
+        case Instruction::MUL_INT:
+        case Instruction::MUL_INT_2ADDR:
             op = kOpMul;
             break;
-        case OP_DIV_INT:
-        case OP_DIV_INT_2ADDR:
+        case Instruction::DIV_INT:
+        case Instruction::DIV_INT_2ADDR:
             callOut = true;
             checkZero = true;
             funcOffset = OFFSETOF_MEMBER(Thread, pIdiv);
             retReg = rRET0;
             break;
         /* NOTE: returns in rARG1 */
-        case OP_REM_INT:
-        case OP_REM_INT_2ADDR:
+        case Instruction::REM_INT:
+        case Instruction::REM_INT_2ADDR:
             callOut = true;
             checkZero = true;
             funcOffset = OFFSETOF_MEMBER(Thread, pIdivmod);
             retReg = rRET1;
             break;
-        case OP_AND_INT:
-        case OP_AND_INT_2ADDR:
+        case Instruction::AND_INT:
+        case Instruction::AND_INT_2ADDR:
             op = kOpAnd;
             break;
-        case OP_OR_INT:
-        case OP_OR_INT_2ADDR:
+        case Instruction::OR_INT:
+        case Instruction::OR_INT_2ADDR:
             op = kOpOr;
             break;
-        case OP_XOR_INT:
-        case OP_XOR_INT_2ADDR:
+        case Instruction::XOR_INT:
+        case Instruction::XOR_INT_2ADDR:
             op = kOpXor;
             break;
-        case OP_SHL_INT:
-        case OP_SHL_INT_2ADDR:
+        case Instruction::SHL_INT:
+        case Instruction::SHL_INT_2ADDR:
             shiftOp = true;
             op = kOpLsl;
             break;
-        case OP_SHR_INT:
-        case OP_SHR_INT_2ADDR:
+        case Instruction::SHR_INT:
+        case Instruction::SHR_INT_2ADDR:
             shiftOp = true;
             op = kOpAsr;
             break;
-        case OP_USHR_INT:
-        case OP_USHR_INT_2ADDR:
+        case Instruction::USHR_INT:
+        case Instruction::USHR_INT_2ADDR:
             shiftOp = true;
             op = kOpLsr;
             break;
@@ -1564,7 +1564,7 @@
 
 // Returns true if it added instructions to 'cUnit' to divide 'rlSrc' by 'lit'
 // and store the result in 'rlDest'.
-bool handleEasyDivide(CompilationUnit* cUnit, Opcode dalvikOpcode,
+bool handleEasyDivide(CompilationUnit* cUnit, Instruction::Code dalvikOpcode,
                       RegLocation rlSrc, RegLocation rlDest, int lit)
 {
     if (lit < 2 || !isPowerOfTwo(lit)) {
@@ -1575,8 +1575,8 @@
         // Avoid special cases.
         return false;
     }
-    bool div = (dalvikOpcode == OP_DIV_INT_LIT8 ||
-                dalvikOpcode == OP_DIV_INT_LIT16);
+    bool div = (dalvikOpcode == Instruction::DIV_INT_LIT8 ||
+                dalvikOpcode == Instruction::DIV_INT_LIT16);
     rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
     RegLocation rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
     if (div) {
@@ -1680,7 +1680,7 @@
 bool genArithOpIntLit(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
                       RegLocation rlSrc, int lit)
 {
-    Opcode dalvikOpcode = mir->dalvikInsn.opcode;
+    Instruction::Code dalvikOpcode = mir->dalvikInsn.opcode;
     RegLocation rlResult;
     OpKind op = (OpKind)0;      /* Make gcc happy */
     int shiftOp = false;
@@ -1689,8 +1689,8 @@
     int rTgt;
 
     switch (dalvikOpcode) {
-        case OP_RSUB_INT_LIT8:
-        case OP_RSUB_INT: {
+        case Instruction::RSUB_INT_LIT8:
+        case Instruction::RSUB_INT: {
             int tReg;
             //TUNING: add support for use of Arm rsub op
             rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
@@ -1704,50 +1704,50 @@
             break;
         }
 
-        case OP_ADD_INT_LIT8:
-        case OP_ADD_INT_LIT16:
+        case Instruction::ADD_INT_LIT8:
+        case Instruction::ADD_INT_LIT16:
             op = kOpAdd;
             break;
-        case OP_MUL_INT_LIT8:
-        case OP_MUL_INT_LIT16: {
+        case Instruction::MUL_INT_LIT8:
+        case Instruction::MUL_INT_LIT16: {
             if (handleEasyMultiply(cUnit, rlSrc, rlDest, lit)) {
                 return false;
             }
             op = kOpMul;
             break;
         }
-        case OP_AND_INT_LIT8:
-        case OP_AND_INT_LIT16:
+        case Instruction::AND_INT_LIT8:
+        case Instruction::AND_INT_LIT16:
             op = kOpAnd;
             break;
-        case OP_OR_INT_LIT8:
-        case OP_OR_INT_LIT16:
+        case Instruction::OR_INT_LIT8:
+        case Instruction::OR_INT_LIT16:
             op = kOpOr;
             break;
-        case OP_XOR_INT_LIT8:
-        case OP_XOR_INT_LIT16:
+        case Instruction::XOR_INT_LIT8:
+        case Instruction::XOR_INT_LIT16:
             op = kOpXor;
             break;
-        case OP_SHL_INT_LIT8:
+        case Instruction::SHL_INT_LIT8:
             lit &= 31;
             shiftOp = true;
             op = kOpLsl;
             break;
-        case OP_SHR_INT_LIT8:
+        case Instruction::SHR_INT_LIT8:
             lit &= 31;
             shiftOp = true;
             op = kOpAsr;
             break;
-        case OP_USHR_INT_LIT8:
+        case Instruction::USHR_INT_LIT8:
             lit &= 31;
             shiftOp = true;
             op = kOpLsr;
             break;
 
-        case OP_DIV_INT_LIT8:
-        case OP_DIV_INT_LIT16:
-        case OP_REM_INT_LIT8:
-        case OP_REM_INT_LIT16:
+        case Instruction::DIV_INT_LIT8:
+        case Instruction::DIV_INT_LIT16:
+        case Instruction::REM_INT_LIT8:
+        case Instruction::REM_INT_LIT16:
             if (lit == 0) {
                 genImmedCheck(cUnit, kCondAl, 0, 0, mir, kThrowDivZero);
                 return false;
@@ -1758,8 +1758,8 @@
             oatFlushAllRegs(cUnit);   /* Everything to home location */
             loadValueDirectFixed(cUnit, rlSrc, rARG0);
             oatClobber(cUnit, rARG0);
-            if ((dalvikOpcode == OP_DIV_INT_LIT8) ||
-                (dalvikOpcode == OP_DIV_INT_LIT16)) {
+            if ((dalvikOpcode == Instruction::DIV_INT_LIT8) ||
+                (dalvikOpcode == Instruction::DIV_INT_LIT16)) {
                 funcOffset = OFFSETOF_MEMBER(Thread, pIdiv);
                 isDiv = true;
             } else {
@@ -1807,7 +1807,7 @@
     int retReg = rRET0;
 
     switch (mir->dalvikInsn.opcode) {
-        case OP_NOT_LONG:
+        case Instruction::NOT_LONG:
             rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
             rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
             // Check for destructive overlap
@@ -1824,8 +1824,8 @@
             storeValueWide(cUnit, rlDest, rlResult);
             return false;
             break;
-        case OP_ADD_LONG:
-        case OP_ADD_LONG_2ADDR:
+        case Instruction::ADD_LONG:
+        case Instruction::ADD_LONG_2ADDR:
 #if defined(TARGET_MIPS)
             return genAddLong(cUnit, mir, rlDest, rlSrc1, rlSrc2);
 #else
@@ -1833,8 +1833,8 @@
             secondOp = kOpAdc;
             break;
 #endif
-        case OP_SUB_LONG:
-        case OP_SUB_LONG_2ADDR:
+        case Instruction::SUB_LONG:
+        case Instruction::SUB_LONG_2ADDR:
 #if defined(TARGET_MIPS)
             return genSubLong(cUnit, mir, rlDest, rlSrc1, rlSrc2);
 #else
@@ -1842,14 +1842,14 @@
             secondOp = kOpSbc;
             break;
 #endif
-        case OP_MUL_LONG:
-        case OP_MUL_LONG_2ADDR:
+        case Instruction::MUL_LONG:
+        case Instruction::MUL_LONG_2ADDR:
             callOut = true;
             retReg = rRET0;
             funcOffset = OFFSETOF_MEMBER(Thread, pLmul);
             break;
-        case OP_DIV_LONG:
-        case OP_DIV_LONG_2ADDR:
+        case Instruction::DIV_LONG:
+        case Instruction::DIV_LONG_2ADDR:
             callOut = true;
             checkZero = true;
             retReg = rRET0;
@@ -1857,29 +1857,29 @@
             break;
         /* NOTE - result is in rARG2/rARG3 instead of rRET0/rRET1 */
         // FIXME: is true, or could be made true, or other targets?
-        case OP_REM_LONG:
-        case OP_REM_LONG_2ADDR:
+        case Instruction::REM_LONG:
+        case Instruction::REM_LONG_2ADDR:
             callOut = true;
             checkZero = true;
             funcOffset = OFFSETOF_MEMBER(Thread, pLdivmod);
             retReg = rARG2;
             break;
-        case OP_AND_LONG_2ADDR:
-        case OP_AND_LONG:
+        case Instruction::AND_LONG_2ADDR:
+        case Instruction::AND_LONG:
             firstOp = kOpAnd;
             secondOp = kOpAnd;
             break;
-        case OP_OR_LONG:
-        case OP_OR_LONG_2ADDR:
+        case Instruction::OR_LONG:
+        case Instruction::OR_LONG_2ADDR:
             firstOp = kOpOr;
             secondOp = kOpOr;
             break;
-        case OP_XOR_LONG:
-        case OP_XOR_LONG_2ADDR:
+        case Instruction::XOR_LONG:
+        case Instruction::XOR_LONG_2ADDR:
             firstOp = kOpXor;
             secondOp = kOpXor;
             break;
-        case OP_NEG_LONG: {
+        case Instruction::NEG_LONG: {
             return genNegLong(cUnit, mir, rlDest, rlSrc2);
         }
         default:
@@ -1963,27 +1963,27 @@
     int funcOffset;
 
     switch (mir->dalvikInsn.opcode) {
-        case OP_ADD_FLOAT_2ADDR:
-        case OP_ADD_FLOAT:
+        case Instruction::ADD_FLOAT_2ADDR:
+        case Instruction::ADD_FLOAT:
             funcOffset = OFFSETOF_MEMBER(Thread, pFadd);
             break;
-        case OP_SUB_FLOAT_2ADDR:
-        case OP_SUB_FLOAT:
+        case Instruction::SUB_FLOAT_2ADDR:
+        case Instruction::SUB_FLOAT:
             funcOffset = OFFSETOF_MEMBER(Thread, pFsub);
             break;
-        case OP_DIV_FLOAT_2ADDR:
-        case OP_DIV_FLOAT:
+        case Instruction::DIV_FLOAT_2ADDR:
+        case Instruction::DIV_FLOAT:
             funcOffset = OFFSETOF_MEMBER(Thread, pFdiv);
             break;
-        case OP_MUL_FLOAT_2ADDR:
-        case OP_MUL_FLOAT:
+        case Instruction::MUL_FLOAT_2ADDR:
+        case Instruction::MUL_FLOAT:
             funcOffset = OFFSETOF_MEMBER(Thread, pFmul);
             break;
-        case OP_REM_FLOAT_2ADDR:
-        case OP_REM_FLOAT:
+        case Instruction::REM_FLOAT_2ADDR:
+        case Instruction::REM_FLOAT:
             funcOffset = OFFSETOF_MEMBER(Thread, pFmodf);
             break;
-        case OP_NEG_FLOAT: {
+        case Instruction::NEG_FLOAT: {
             genNegFloat(cUnit, rlDest, rlSrc1);
             return false;
         }
@@ -2014,27 +2014,27 @@
     int funcOffset;
 
     switch (mir->dalvikInsn.opcode) {
-        case OP_ADD_DOUBLE_2ADDR:
-        case OP_ADD_DOUBLE:
+        case Instruction::ADD_DOUBLE_2ADDR:
+        case Instruction::ADD_DOUBLE:
             funcOffset = OFFSETOF_MEMBER(Thread, pDadd);
             break;
-        case OP_SUB_DOUBLE_2ADDR:
-        case OP_SUB_DOUBLE:
+        case Instruction::SUB_DOUBLE_2ADDR:
+        case Instruction::SUB_DOUBLE:
             funcOffset = OFFSETOF_MEMBER(Thread, pDsub);
             break;
-        case OP_DIV_DOUBLE_2ADDR:
-        case OP_DIV_DOUBLE:
+        case Instruction::DIV_DOUBLE_2ADDR:
+        case Instruction::DIV_DOUBLE:
             funcOffset = OFFSETOF_MEMBER(Thread, pDdiv);
             break;
-        case OP_MUL_DOUBLE_2ADDR:
-        case OP_MUL_DOUBLE:
+        case Instruction::MUL_DOUBLE_2ADDR:
+        case Instruction::MUL_DOUBLE:
             funcOffset = OFFSETOF_MEMBER(Thread, pDmul);
             break;
-        case OP_REM_DOUBLE_2ADDR:
-        case OP_REM_DOUBLE:
+        case Instruction::REM_DOUBLE_2ADDR:
+        case Instruction::REM_DOUBLE:
             funcOffset = OFFSETOF_MEMBER(Thread, pFmod);
             break;
-        case OP_NEG_DOUBLE: {
+        case Instruction::NEG_DOUBLE: {
             genNegDouble(cUnit, rlDest, rlSrc1);
             return false;
         }
@@ -2054,37 +2054,37 @@
 
 bool genConversionPortable(CompilationUnit* cUnit, MIR* mir)
 {
-    Opcode opcode = mir->dalvikInsn.opcode;
+    Instruction::Code opcode = mir->dalvikInsn.opcode;
 
     switch (opcode) {
-        case OP_INT_TO_FLOAT:
+        case Instruction::INT_TO_FLOAT:
             return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pI2f),
                                      1, 1);
-        case OP_FLOAT_TO_INT:
+        case Instruction::FLOAT_TO_INT:
             return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pF2iz),
                                      1, 1);
-        case OP_DOUBLE_TO_FLOAT:
+        case Instruction::DOUBLE_TO_FLOAT:
             return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pD2f),
                                      2, 1);
-        case OP_FLOAT_TO_DOUBLE:
+        case Instruction::FLOAT_TO_DOUBLE:
             return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pF2d),
                                      1, 2);
-        case OP_INT_TO_DOUBLE:
+        case Instruction::INT_TO_DOUBLE:
             return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pI2d),
                                      1, 2);
-        case OP_DOUBLE_TO_INT:
+        case Instruction::DOUBLE_TO_INT:
             return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pD2iz),
                                      2, 1);
-        case OP_FLOAT_TO_LONG:
+        case Instruction::FLOAT_TO_LONG:
             return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread,
                                      pF2l), 1, 2);
-        case OP_LONG_TO_FLOAT:
+        case Instruction::LONG_TO_FLOAT:
             return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pL2f),
                                      2, 1);
-        case OP_DOUBLE_TO_LONG:
+        case Instruction::DOUBLE_TO_LONG:
             return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread,
                                      pD2l), 2, 2);
-        case OP_LONG_TO_DOUBLE:
+        case Instruction::LONG_TO_DOUBLE:
             return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pL2d),
                                      2, 2);
         default:
diff --git a/src/compiler/codegen/MethodCodegenDriver.cc b/src/compiler/codegen/MethodCodegenDriver.cc
index f25c7e5..8dd099e 100644
--- a/src/compiler/codegen/MethodCodegenDriver.cc
+++ b/src/compiler/codegen/MethodCodegenDriver.cc
@@ -122,7 +122,7 @@
     RegLocation rlSrc[3];
     RegLocation rlDest = badLoc;
     RegLocation rlResult = badLoc;
-    Opcode opcode = mir->dalvikInsn.opcode;
+    Instruction::Code opcode = mir->dalvikInsn.opcode;
 
     /* Prep Src and Dest locations */
     int nextSreg = 0;
@@ -158,12 +158,12 @@
     }
 
     switch(opcode) {
-        case OP_NOP:
+        case Instruction::NOP:
             break;
 
-        case OP_MOVE_EXCEPTION:
+        case Instruction::MOVE_EXCEPTION:
 #if defined(TARGET_X86)
-            UNIMPLEMENTED(WARNING) << "OP_MOVE_EXCEPTION";
+            UNIMPLEMENTED(WARNING) << "Instruction::MOVE_EXCEPTION";
 #else
             int exOffset;
             int resetReg;
@@ -177,66 +177,66 @@
 #endif
             break;
 
-        case OP_RETURN_VOID:
+        case Instruction::RETURN_VOID:
             genSuspendTest(cUnit, mir);
             break;
 
-        case OP_RETURN:
-        case OP_RETURN_OBJECT:
+        case Instruction::RETURN:
+        case Instruction::RETURN_OBJECT:
             genSuspendTest(cUnit, mir);
             storeValue(cUnit, getRetLoc(cUnit), rlSrc[0]);
             break;
 
-        case OP_RETURN_WIDE:
+        case Instruction::RETURN_WIDE:
             genSuspendTest(cUnit, mir);
             storeValueWide(cUnit, getRetLocWide(cUnit), rlSrc[0]);
             break;
 
-        case OP_MOVE_RESULT_WIDE:
+        case Instruction::MOVE_RESULT_WIDE:
             if (mir->optimizationFlags & MIR_INLINED)
                 break;  // Nop - combined w/ previous invoke
             storeValueWide(cUnit, rlDest, getRetLocWide(cUnit));
             break;
 
-        case OP_MOVE_RESULT:
-        case OP_MOVE_RESULT_OBJECT:
+        case Instruction::MOVE_RESULT:
+        case Instruction::MOVE_RESULT_OBJECT:
             if (mir->optimizationFlags & MIR_INLINED)
                 break;  // Nop - combined w/ previous invoke
             storeValue(cUnit, rlDest, getRetLoc(cUnit));
             break;
 
-        case OP_MOVE:
-        case OP_MOVE_OBJECT:
-        case OP_MOVE_16:
-        case OP_MOVE_OBJECT_16:
-        case OP_MOVE_FROM16:
-        case OP_MOVE_OBJECT_FROM16:
+        case Instruction::MOVE:
+        case Instruction::MOVE_OBJECT:
+        case Instruction::MOVE_16:
+        case Instruction::MOVE_OBJECT_16:
+        case Instruction::MOVE_FROM16:
+        case Instruction::MOVE_OBJECT_FROM16:
             storeValue(cUnit, rlDest, rlSrc[0]);
             break;
 
-        case OP_MOVE_WIDE:
-        case OP_MOVE_WIDE_16:
-        case OP_MOVE_WIDE_FROM16:
+        case Instruction::MOVE_WIDE:
+        case Instruction::MOVE_WIDE_16:
+        case Instruction::MOVE_WIDE_FROM16:
             storeValueWide(cUnit, rlDest, rlSrc[0]);
             break;
 
-        case OP_CONST:
-        case OP_CONST_4:
-        case OP_CONST_16:
+        case Instruction::CONST:
+        case Instruction::CONST_4:
+        case Instruction::CONST_16:
             rlResult = oatEvalLoc(cUnit, rlDest, kAnyReg, true);
             loadConstantNoClobber(cUnit, rlResult.lowReg, mir->dalvikInsn.vB);
             storeValue(cUnit, rlDest, rlResult);
             break;
 
-        case OP_CONST_HIGH16:
+        case Instruction::CONST_HIGH16:
             rlResult = oatEvalLoc(cUnit, rlDest, kAnyReg, true);
             loadConstantNoClobber(cUnit, rlResult.lowReg,
                                   mir->dalvikInsn.vB << 16);
             storeValue(cUnit, rlDest, rlResult);
             break;
 
-        case OP_CONST_WIDE_16:
-        case OP_CONST_WIDE_32:
+        case Instruction::CONST_WIDE_16:
+        case Instruction::CONST_WIDE_32:
             rlResult = oatEvalLoc(cUnit, rlDest, kAnyReg, true);
             loadConstantValueWide(cUnit, rlResult.lowReg, rlResult.highReg,
                                   mir->dalvikInsn.vB,
@@ -244,7 +244,7 @@
             storeValueWide(cUnit, rlDest, rlResult);
             break;
 
-        case OP_CONST_WIDE:
+        case Instruction::CONST_WIDE:
             rlResult = oatEvalLoc(cUnit, rlDest, kAnyReg, true);
             loadConstantValueWide(cUnit, rlResult.lowReg, rlResult.highReg,
                           mir->dalvikInsn.vB_wide & 0xffffffff,
@@ -252,42 +252,42 @@
             storeValueWide(cUnit, rlDest, rlResult);
             break;
 
-        case OP_CONST_WIDE_HIGH16:
+        case Instruction::CONST_WIDE_HIGH16:
             rlResult = oatEvalLoc(cUnit, rlDest, kAnyReg, true);
             loadConstantValueWide(cUnit, rlResult.lowReg, rlResult.highReg,
                                   0, mir->dalvikInsn.vB << 16);
             storeValueWide(cUnit, rlDest, rlResult);
             break;
 
-        case OP_MONITOR_ENTER:
+        case Instruction::MONITOR_ENTER:
             genMonitorEnter(cUnit, mir, rlSrc[0]);
             break;
 
-        case OP_MONITOR_EXIT:
+        case Instruction::MONITOR_EXIT:
             genMonitorExit(cUnit, mir, rlSrc[0]);
             break;
 
-        case OP_CHECK_CAST:
+        case Instruction::CHECK_CAST:
             genCheckCast(cUnit, mir, rlSrc[0]);
             break;
 
-        case OP_INSTANCE_OF:
+        case Instruction::INSTANCE_OF:
             genInstanceof(cUnit, mir, rlDest, rlSrc[0]);
             break;
 
-        case OP_NEW_INSTANCE:
+        case Instruction::NEW_INSTANCE:
             genNewInstance(cUnit, mir, rlDest);
             break;
 
-        case OP_THROW:
+        case Instruction::THROW:
             genThrow(cUnit, mir, rlSrc[0]);
             break;
 
-        case OP_THROW_VERIFICATION_ERROR:
+        case Instruction::THROW_VERIFICATION_ERROR:
             genThrowVerificationError(cUnit, mir);
             break;
 
-        case OP_ARRAY_LENGTH:
+        case Instruction::ARRAY_LENGTH:
             int lenOffset;
             lenOffset = Array::LengthOffset().Int32Value();
             rlSrc[0] = loadValue(cUnit, rlSrc[0], kCoreReg);
@@ -298,65 +298,65 @@
             storeValue(cUnit, rlDest, rlResult);
             break;
 
-        case OP_CONST_STRING:
-        case OP_CONST_STRING_JUMBO:
+        case Instruction::CONST_STRING:
+        case Instruction::CONST_STRING_JUMBO:
             genConstString(cUnit, mir, rlDest, rlSrc[0]);
             break;
 
-        case OP_CONST_CLASS:
+        case Instruction::CONST_CLASS:
             genConstClass(cUnit, mir, rlDest, rlSrc[0]);
             break;
 
-        case OP_FILL_ARRAY_DATA:
+        case Instruction::FILL_ARRAY_DATA:
             genFillArrayData(cUnit, mir, rlSrc[0]);
             break;
 
-        case OP_FILLED_NEW_ARRAY:
+        case Instruction::FILLED_NEW_ARRAY:
             genFilledNewArray(cUnit, mir, false /* not range */);
             break;
 
-        case OP_FILLED_NEW_ARRAY_RANGE:
+        case Instruction::FILLED_NEW_ARRAY_RANGE:
             genFilledNewArray(cUnit, mir, true /* range */);
             break;
 
-        case OP_NEW_ARRAY:
+        case Instruction::NEW_ARRAY:
             genNewArray(cUnit, mir, rlDest, rlSrc[0]);
             break;
 
-        case OP_GOTO:
-        case OP_GOTO_16:
-        case OP_GOTO_32:
+        case Instruction::GOTO:
+        case Instruction::GOTO_16:
+        case Instruction::GOTO_32:
             if (bb->taken->startOffset <= mir->offset) {
                 genSuspendTest(cUnit, mir);
             }
             opUnconditionalBranch(cUnit, &labelList[bb->taken->id]);
             break;
 
-        case OP_PACKED_SWITCH:
+        case Instruction::PACKED_SWITCH:
             genPackedSwitch(cUnit, mir, rlSrc[0]);
             break;
 
-        case OP_SPARSE_SWITCH:
+        case Instruction::SPARSE_SWITCH:
             genSparseSwitch(cUnit, mir, rlSrc[0]);
             break;
 
-        case OP_CMPL_FLOAT:
-        case OP_CMPG_FLOAT:
-        case OP_CMPL_DOUBLE:
-        case OP_CMPG_DOUBLE:
+        case Instruction::CMPL_FLOAT:
+        case Instruction::CMPG_FLOAT:
+        case Instruction::CMPL_DOUBLE:
+        case Instruction::CMPG_DOUBLE:
             res = genCmpFP(cUnit, mir, rlDest, rlSrc[0], rlSrc[1]);
             break;
 
-        case OP_CMP_LONG:
+        case Instruction::CMP_LONG:
             genCmpLong(cUnit, mir, rlDest, rlSrc[0], rlSrc[1]);
             break;
 
-        case OP_IF_EQ:
-        case OP_IF_NE:
-        case OP_IF_LT:
-        case OP_IF_GE:
-        case OP_IF_GT:
-        case OP_IF_LE: {
+        case Instruction::IF_EQ:
+        case Instruction::IF_NE:
+        case Instruction::IF_LT:
+        case Instruction::IF_GE:
+        case Instruction::IF_GT:
+        case Instruction::IF_LE: {
             bool backwardBranch;
             backwardBranch = (bb->taken->startOffset <= mir->offset);
             if (backwardBranch) {
@@ -366,12 +366,12 @@
             break;
             }
 
-        case OP_IF_EQZ:
-        case OP_IF_NEZ:
-        case OP_IF_LTZ:
-        case OP_IF_GEZ:
-        case OP_IF_GTZ:
-        case OP_IF_LEZ: {
+        case Instruction::IF_EQZ:
+        case Instruction::IF_NEZ:
+        case Instruction::IF_LTZ:
+        case Instruction::IF_GEZ:
+        case Instruction::IF_GTZ:
+        case Instruction::IF_LEZ: {
             bool backwardBranch;
             backwardBranch = (bb->taken->startOffset <= mir->offset);
             if (backwardBranch) {
@@ -381,314 +381,314 @@
             break;
             }
 
-      case OP_AGET_WIDE:
+      case Instruction::AGET_WIDE:
             genArrayGet(cUnit, mir, kLong, rlSrc[0], rlSrc[1], rlDest, 3);
             break;
-        case OP_AGET:
-        case OP_AGET_OBJECT:
+        case Instruction::AGET:
+        case Instruction::AGET_OBJECT:
             genArrayGet(cUnit, mir, kWord, rlSrc[0], rlSrc[1], rlDest, 2);
             break;
-        case OP_AGET_BOOLEAN:
+        case Instruction::AGET_BOOLEAN:
             genArrayGet(cUnit, mir, kUnsignedByte, rlSrc[0], rlSrc[1],
                         rlDest, 0);
             break;
-        case OP_AGET_BYTE:
+        case Instruction::AGET_BYTE:
             genArrayGet(cUnit, mir, kSignedByte, rlSrc[0], rlSrc[1], rlDest, 0);
             break;
-        case OP_AGET_CHAR:
+        case Instruction::AGET_CHAR:
             genArrayGet(cUnit, mir, kUnsignedHalf, rlSrc[0], rlSrc[1],
                         rlDest, 1);
             break;
-        case OP_AGET_SHORT:
+        case Instruction::AGET_SHORT:
             genArrayGet(cUnit, mir, kSignedHalf, rlSrc[0], rlSrc[1], rlDest, 1);
             break;
-        case OP_APUT_WIDE:
+        case Instruction::APUT_WIDE:
             genArrayPut(cUnit, mir, kLong, rlSrc[1], rlSrc[2], rlSrc[0], 3);
             break;
-        case OP_APUT:
+        case Instruction::APUT:
             genArrayPut(cUnit, mir, kWord, rlSrc[1], rlSrc[2], rlSrc[0], 2);
             break;
-        case OP_APUT_OBJECT:
+        case Instruction::APUT_OBJECT:
             genArrayObjPut(cUnit, mir, rlSrc[1], rlSrc[2], rlSrc[0], 2);
             break;
-        case OP_APUT_SHORT:
-        case OP_APUT_CHAR:
+        case Instruction::APUT_SHORT:
+        case Instruction::APUT_CHAR:
             genArrayPut(cUnit, mir, kUnsignedHalf, rlSrc[1], rlSrc[2],
                         rlSrc[0], 1);
             break;
-        case OP_APUT_BYTE:
-        case OP_APUT_BOOLEAN:
+        case Instruction::APUT_BYTE:
+        case Instruction::APUT_BOOLEAN:
             genArrayPut(cUnit, mir, kUnsignedByte, rlSrc[1], rlSrc[2],
                         rlSrc[0], 0);
             break;
 
-        case OP_IGET_OBJECT:
-        case OP_IGET_OBJECT_VOLATILE:
+        case Instruction::IGET_OBJECT:
+        //case Instruction::IGET_OBJECT_VOLATILE:
             genIGet(cUnit, mir, kWord, rlDest, rlSrc[0], false, true);
             break;
 
-        case OP_IGET_WIDE:
-        case OP_IGET_WIDE_VOLATILE:
+        case Instruction::IGET_WIDE:
+        //case Instruction::IGET_WIDE_VOLATILE:
             genIGet(cUnit, mir, kLong, rlDest, rlSrc[0], true, false);
             break;
 
-        case OP_IGET:
-        case OP_IGET_VOLATILE:
+        case Instruction::IGET:
+        //case Instruction::IGET_VOLATILE:
             genIGet(cUnit, mir, kWord, rlDest, rlSrc[0], false, false);
             break;
 
-        case OP_IGET_CHAR:
+        case Instruction::IGET_CHAR:
             genIGet(cUnit, mir, kUnsignedHalf, rlDest, rlSrc[0], false, false);
             break;
 
-        case OP_IGET_SHORT:
+        case Instruction::IGET_SHORT:
             genIGet(cUnit, mir, kSignedHalf, rlDest, rlSrc[0], false, false);
             break;
 
-        case OP_IGET_BOOLEAN:
-        case OP_IGET_BYTE:
+        case Instruction::IGET_BOOLEAN:
+        case Instruction::IGET_BYTE:
             genIGet(cUnit, mir, kUnsignedByte, rlDest, rlSrc[0], false, false);
             break;
 
-        case OP_IPUT_WIDE:
-        case OP_IPUT_WIDE_VOLATILE:
+        case Instruction::IPUT_WIDE:
+        //case Instruction::IPUT_WIDE_VOLATILE:
             genIPut(cUnit, mir, kLong, rlSrc[0], rlSrc[1], true, false);
             break;
 
-        case OP_IPUT_OBJECT:
-        case OP_IPUT_OBJECT_VOLATILE:
+        case Instruction::IPUT_OBJECT:
+        //case Instruction::IPUT_OBJECT_VOLATILE:
             genIPut(cUnit, mir, kWord, rlSrc[0], rlSrc[1], false, true);
             break;
 
-        case OP_IPUT:
-        case OP_IPUT_VOLATILE:
+        case Instruction::IPUT:
+        //case Instruction::IPUT_VOLATILE:
             genIPut(cUnit, mir, kWord, rlSrc[0], rlSrc[1], false, false);
             break;
 
-        case OP_IPUT_BOOLEAN:
-        case OP_IPUT_BYTE:
+        case Instruction::IPUT_BOOLEAN:
+        case Instruction::IPUT_BYTE:
             genIPut(cUnit, mir, kUnsignedByte, rlSrc[0], rlSrc[1], false, false);
             break;
 
-        case OP_IPUT_CHAR:
+        case Instruction::IPUT_CHAR:
             genIPut(cUnit, mir, kUnsignedHalf, rlSrc[0], rlSrc[1], false, false);
             break;
 
-        case OP_IPUT_SHORT:
+        case Instruction::IPUT_SHORT:
             genIPut(cUnit, mir, kSignedHalf, rlSrc[0], rlSrc[1], false, false);
             break;
 
-        case OP_SGET_OBJECT:
+        case Instruction::SGET_OBJECT:
             genSget(cUnit, mir, rlDest, false, true);
             break;
-        case OP_SGET:
-        case OP_SGET_BOOLEAN:
-        case OP_SGET_BYTE:
-        case OP_SGET_CHAR:
-        case OP_SGET_SHORT:
+        case Instruction::SGET:
+        case Instruction::SGET_BOOLEAN:
+        case Instruction::SGET_BYTE:
+        case Instruction::SGET_CHAR:
+        case Instruction::SGET_SHORT:
             genSget(cUnit, mir, rlDest, false, false);
             break;
 
-        case OP_SGET_WIDE:
+        case Instruction::SGET_WIDE:
             genSget(cUnit, mir, rlDest, true, false);
             break;
 
-        case OP_SPUT_OBJECT:
+        case Instruction::SPUT_OBJECT:
             genSput(cUnit, mir, rlSrc[0], false, true);
             break;
 
-        case OP_SPUT:
-        case OP_SPUT_BOOLEAN:
-        case OP_SPUT_BYTE:
-        case OP_SPUT_CHAR:
-        case OP_SPUT_SHORT:
+        case Instruction::SPUT:
+        case Instruction::SPUT_BOOLEAN:
+        case Instruction::SPUT_BYTE:
+        case Instruction::SPUT_CHAR:
+        case Instruction::SPUT_SHORT:
             genSput(cUnit, mir, rlSrc[0], false, false);
             break;
 
-        case OP_SPUT_WIDE:
+        case Instruction::SPUT_WIDE:
             genSput(cUnit, mir, rlSrc[0], true, false);
             break;
 
-        case OP_INVOKE_STATIC_RANGE:
+        case Instruction::INVOKE_STATIC_RANGE:
             genInvoke(cUnit, mir, kStatic, true /*range*/);
             break;
-        case OP_INVOKE_STATIC:
+        case Instruction::INVOKE_STATIC:
             genInvoke(cUnit, mir, kStatic, false /*range*/);
             break;
 
-        case OP_INVOKE_DIRECT:
+        case Instruction::INVOKE_DIRECT:
             genInvoke(cUnit, mir, kDirect, false /*range*/);
             break;
-        case OP_INVOKE_DIRECT_RANGE:
+        case Instruction::INVOKE_DIRECT_RANGE:
             genInvoke(cUnit, mir, kDirect, true /*range*/);
             break;
 
-        case OP_INVOKE_VIRTUAL:
+        case Instruction::INVOKE_VIRTUAL:
             genInvoke(cUnit, mir, kVirtual, false /*range*/);
             break;
-        case OP_INVOKE_VIRTUAL_RANGE:
+        case Instruction::INVOKE_VIRTUAL_RANGE:
             genInvoke(cUnit, mir, kVirtual, true /*range*/);
             break;
 
-        case OP_INVOKE_SUPER:
+        case Instruction::INVOKE_SUPER:
             genInvoke(cUnit, mir, kSuper, false /*range*/);
             break;
-        case OP_INVOKE_SUPER_RANGE:
+        case Instruction::INVOKE_SUPER_RANGE:
             genInvoke(cUnit, mir, kSuper, true /*range*/);
             break;
 
-        case OP_INVOKE_INTERFACE:
+        case Instruction::INVOKE_INTERFACE:
             genInvoke(cUnit, mir, kInterface, false /*range*/);
             break;
-        case OP_INVOKE_INTERFACE_RANGE:
+        case Instruction::INVOKE_INTERFACE_RANGE:
             genInvoke(cUnit, mir, kInterface, true /*range*/);
             break;
 
-        case OP_NEG_INT:
-        case OP_NOT_INT:
+        case Instruction::NEG_INT:
+        case Instruction::NOT_INT:
             res = genArithOpInt(cUnit, mir, rlDest, rlSrc[0], rlSrc[0]);
             break;
 
-        case OP_NEG_LONG:
-        case OP_NOT_LONG:
+        case Instruction::NEG_LONG:
+        case Instruction::NOT_LONG:
             res = genArithOpLong(cUnit, mir, rlDest, rlSrc[0], rlSrc[0]);
             break;
 
-        case OP_NEG_FLOAT:
+        case Instruction::NEG_FLOAT:
             res = genArithOpFloat(cUnit, mir, rlDest, rlSrc[0], rlSrc[0]);
             break;
 
-        case OP_NEG_DOUBLE:
+        case Instruction::NEG_DOUBLE:
             res = genArithOpDouble(cUnit, mir, rlDest, rlSrc[0], rlSrc[0]);
             break;
 
-        case OP_INT_TO_LONG:
+        case Instruction::INT_TO_LONG:
             genIntToLong(cUnit, mir, rlDest, rlSrc[0]);
             break;
 
-        case OP_LONG_TO_INT:
+        case Instruction::LONG_TO_INT:
             rlSrc[0] = oatUpdateLocWide(cUnit, rlSrc[0]);
             rlSrc[0] = oatWideToNarrow(cUnit, rlSrc[0]);
             storeValue(cUnit, rlDest, rlSrc[0]);
             break;
 
-        case OP_INT_TO_BYTE:
-        case OP_INT_TO_SHORT:
-        case OP_INT_TO_CHAR:
+        case Instruction::INT_TO_BYTE:
+        case Instruction::INT_TO_SHORT:
+        case Instruction::INT_TO_CHAR:
             genIntNarrowing(cUnit, mir, rlDest, rlSrc[0]);
             break;
 
-        case OP_INT_TO_FLOAT:
-        case OP_INT_TO_DOUBLE:
-        case OP_LONG_TO_FLOAT:
-        case OP_LONG_TO_DOUBLE:
-        case OP_FLOAT_TO_INT:
-        case OP_FLOAT_TO_LONG:
-        case OP_FLOAT_TO_DOUBLE:
-        case OP_DOUBLE_TO_INT:
-        case OP_DOUBLE_TO_LONG:
-        case OP_DOUBLE_TO_FLOAT:
+        case Instruction::INT_TO_FLOAT:
+        case Instruction::INT_TO_DOUBLE:
+        case Instruction::LONG_TO_FLOAT:
+        case Instruction::LONG_TO_DOUBLE:
+        case Instruction::FLOAT_TO_INT:
+        case Instruction::FLOAT_TO_LONG:
+        case Instruction::FLOAT_TO_DOUBLE:
+        case Instruction::DOUBLE_TO_INT:
+        case Instruction::DOUBLE_TO_LONG:
+        case Instruction::DOUBLE_TO_FLOAT:
             genConversion(cUnit, mir);
             break;
 
-        case OP_ADD_INT:
-        case OP_SUB_INT:
-        case OP_MUL_INT:
-        case OP_DIV_INT:
-        case OP_REM_INT:
-        case OP_AND_INT:
-        case OP_OR_INT:
-        case OP_XOR_INT:
-        case OP_SHL_INT:
-        case OP_SHR_INT:
-        case OP_USHR_INT:
-        case OP_ADD_INT_2ADDR:
-        case OP_SUB_INT_2ADDR:
-        case OP_MUL_INT_2ADDR:
-        case OP_DIV_INT_2ADDR:
-        case OP_REM_INT_2ADDR:
-        case OP_AND_INT_2ADDR:
-        case OP_OR_INT_2ADDR:
-        case OP_XOR_INT_2ADDR:
-        case OP_SHL_INT_2ADDR:
-        case OP_SHR_INT_2ADDR:
-        case OP_USHR_INT_2ADDR:
+        case Instruction::ADD_INT:
+        case Instruction::SUB_INT:
+        case Instruction::MUL_INT:
+        case Instruction::DIV_INT:
+        case Instruction::REM_INT:
+        case Instruction::AND_INT:
+        case Instruction::OR_INT:
+        case Instruction::XOR_INT:
+        case Instruction::SHL_INT:
+        case Instruction::SHR_INT:
+        case Instruction::USHR_INT:
+        case Instruction::ADD_INT_2ADDR:
+        case Instruction::SUB_INT_2ADDR:
+        case Instruction::MUL_INT_2ADDR:
+        case Instruction::DIV_INT_2ADDR:
+        case Instruction::REM_INT_2ADDR:
+        case Instruction::AND_INT_2ADDR:
+        case Instruction::OR_INT_2ADDR:
+        case Instruction::XOR_INT_2ADDR:
+        case Instruction::SHL_INT_2ADDR:
+        case Instruction::SHR_INT_2ADDR:
+        case Instruction::USHR_INT_2ADDR:
             genArithOpInt(cUnit, mir, rlDest, rlSrc[0], rlSrc[1]);
             break;
 
-        case OP_ADD_LONG:
-        case OP_SUB_LONG:
-        case OP_MUL_LONG:
-        case OP_DIV_LONG:
-        case OP_REM_LONG:
-        case OP_AND_LONG:
-        case OP_OR_LONG:
-        case OP_XOR_LONG:
-        case OP_ADD_LONG_2ADDR:
-        case OP_SUB_LONG_2ADDR:
-        case OP_MUL_LONG_2ADDR:
-        case OP_DIV_LONG_2ADDR:
-        case OP_REM_LONG_2ADDR:
-        case OP_AND_LONG_2ADDR:
-        case OP_OR_LONG_2ADDR:
-        case OP_XOR_LONG_2ADDR:
+        case Instruction::ADD_LONG:
+        case Instruction::SUB_LONG:
+        case Instruction::MUL_LONG:
+        case Instruction::DIV_LONG:
+        case Instruction::REM_LONG:
+        case Instruction::AND_LONG:
+        case Instruction::OR_LONG:
+        case Instruction::XOR_LONG:
+        case Instruction::ADD_LONG_2ADDR:
+        case Instruction::SUB_LONG_2ADDR:
+        case Instruction::MUL_LONG_2ADDR:
+        case Instruction::DIV_LONG_2ADDR:
+        case Instruction::REM_LONG_2ADDR:
+        case Instruction::AND_LONG_2ADDR:
+        case Instruction::OR_LONG_2ADDR:
+        case Instruction::XOR_LONG_2ADDR:
             genArithOpLong(cUnit, mir, rlDest, rlSrc[0], rlSrc[1]);
             break;
 
-        case OP_SHL_LONG:
-        case OP_SHR_LONG:
-        case OP_USHR_LONG:
-        case OP_SHL_LONG_2ADDR:
-        case OP_SHR_LONG_2ADDR:
-        case OP_USHR_LONG_2ADDR:
+        case Instruction::SHL_LONG:
+        case Instruction::SHR_LONG:
+        case Instruction::USHR_LONG:
+        case Instruction::SHL_LONG_2ADDR:
+        case Instruction::SHR_LONG_2ADDR:
+        case Instruction::USHR_LONG_2ADDR:
             genShiftOpLong(cUnit,mir, rlDest, rlSrc[0], rlSrc[1]);
             break;
 
-        case OP_ADD_FLOAT:
-        case OP_SUB_FLOAT:
-        case OP_MUL_FLOAT:
-        case OP_DIV_FLOAT:
-        case OP_REM_FLOAT:
-        case OP_ADD_FLOAT_2ADDR:
-        case OP_SUB_FLOAT_2ADDR:
-        case OP_MUL_FLOAT_2ADDR:
-        case OP_DIV_FLOAT_2ADDR:
-        case OP_REM_FLOAT_2ADDR:
+        case Instruction::ADD_FLOAT:
+        case Instruction::SUB_FLOAT:
+        case Instruction::MUL_FLOAT:
+        case Instruction::DIV_FLOAT:
+        case Instruction::REM_FLOAT:
+        case Instruction::ADD_FLOAT_2ADDR:
+        case Instruction::SUB_FLOAT_2ADDR:
+        case Instruction::MUL_FLOAT_2ADDR:
+        case Instruction::DIV_FLOAT_2ADDR:
+        case Instruction::REM_FLOAT_2ADDR:
             genArithOpFloat(cUnit, mir, rlDest, rlSrc[0], rlSrc[1]);
             break;
 
-        case OP_ADD_DOUBLE:
-        case OP_SUB_DOUBLE:
-        case OP_MUL_DOUBLE:
-        case OP_DIV_DOUBLE:
-        case OP_REM_DOUBLE:
-        case OP_ADD_DOUBLE_2ADDR:
-        case OP_SUB_DOUBLE_2ADDR:
-        case OP_MUL_DOUBLE_2ADDR:
-        case OP_DIV_DOUBLE_2ADDR:
-        case OP_REM_DOUBLE_2ADDR:
+        case Instruction::ADD_DOUBLE:
+        case Instruction::SUB_DOUBLE:
+        case Instruction::MUL_DOUBLE:
+        case Instruction::DIV_DOUBLE:
+        case Instruction::REM_DOUBLE:
+        case Instruction::ADD_DOUBLE_2ADDR:
+        case Instruction::SUB_DOUBLE_2ADDR:
+        case Instruction::MUL_DOUBLE_2ADDR:
+        case Instruction::DIV_DOUBLE_2ADDR:
+        case Instruction::REM_DOUBLE_2ADDR:
             genArithOpDouble(cUnit, mir, rlDest, rlSrc[0], rlSrc[1]);
             break;
 
-        case OP_RSUB_INT:
-        case OP_ADD_INT_LIT16:
-        case OP_MUL_INT_LIT16:
-        case OP_DIV_INT_LIT16:
-        case OP_REM_INT_LIT16:
-        case OP_AND_INT_LIT16:
-        case OP_OR_INT_LIT16:
-        case OP_XOR_INT_LIT16:
-        case OP_ADD_INT_LIT8:
-        case OP_RSUB_INT_LIT8:
-        case OP_MUL_INT_LIT8:
-        case OP_DIV_INT_LIT8:
-        case OP_REM_INT_LIT8:
-        case OP_AND_INT_LIT8:
-        case OP_OR_INT_LIT8:
-        case OP_XOR_INT_LIT8:
-        case OP_SHL_INT_LIT8:
-        case OP_SHR_INT_LIT8:
-        case OP_USHR_INT_LIT8:
+        case Instruction::RSUB_INT:
+        case Instruction::ADD_INT_LIT16:
+        case Instruction::MUL_INT_LIT16:
+        case Instruction::DIV_INT_LIT16:
+        case Instruction::REM_INT_LIT16:
+        case Instruction::AND_INT_LIT16:
+        case Instruction::OR_INT_LIT16:
+        case Instruction::XOR_INT_LIT16:
+        case Instruction::ADD_INT_LIT8:
+        case Instruction::RSUB_INT_LIT8:
+        case Instruction::MUL_INT_LIT8:
+        case Instruction::DIV_INT_LIT8:
+        case Instruction::REM_INT_LIT8:
+        case Instruction::AND_INT_LIT8:
+        case Instruction::OR_INT_LIT8:
+        case Instruction::XOR_INT_LIT8:
+        case Instruction::SHL_INT_LIT8:
+        case Instruction::SHR_INT_LIT8:
+        case Instruction::USHR_INT_LIT8:
             genArithOpIntLit(cUnit, mir, rlDest, rlSrc[0], mir->dalvikInsn.vC);
             break;
 
@@ -779,15 +779,14 @@
 
         cUnit->currentDalvikOffset = mir->offset;
 
-        Opcode dalvikOpcode = mir->dalvikInsn.opcode;
-        InstructionFormat dalvikFormat =
-            dexGetFormatFromOpcode(dalvikOpcode);
+        Instruction::Code dalvikOpcode = mir->dalvikInsn.opcode;
+        Instruction::Format dalvikFormat = Instruction::FormatOf(dalvikOpcode);
 
         LIR* boundaryLIR;
 
         /* Mark the beginning of a Dalvik instruction for line tracking */
         char* instStr = cUnit->printMe ?
-           oatGetDalvikDisassembly(cUnit, &mir->dalvikInsn, "") : NULL;
+           oatGetDalvikDisassembly(cUnit, mir->dalvikInsn, "") : NULL;
         boundaryLIR = newLIR1(cUnit, kPseudoDalvikByteCodeBoundary,
                               (intptr_t) instStr);
         cUnit->boundaryMap.insert(std::make_pair(mir->offset,
@@ -811,14 +810,10 @@
         }
 
         bool notHandled = compileDalvikInstruction(cUnit, mir, bb, labelList);
-
         if (notHandled) {
-            char buf[100];
-            snprintf(buf, 100, "%#06x: Opcode %#x (%s) / Fmt %d not handled",
-                 mir->offset,
-                 dalvikOpcode, dexGetOpcodeName(dalvikOpcode),
-                 dalvikFormat);
-            LOG(FATAL) << buf;
+          LOG(FATAL) << StringPrintf("%#06x: Opcode %#x (%s) / Fmt %d not handled",
+                                     mir->offset, dalvikOpcode, Instruction::Name(dalvikOpcode), dalvikFormat);
+
         }
     }
 
diff --git a/src/compiler/codegen/arm/FP/Thumb2VFP.cc b/src/compiler/codegen/arm/FP/Thumb2VFP.cc
index 9ef7b7b..7f372aa 100644
--- a/src/compiler/codegen/arm/FP/Thumb2VFP.cc
+++ b/src/compiler/codegen/arm/FP/Thumb2VFP.cc
@@ -27,25 +27,25 @@
      * the handlers.
      */
     switch (mir->dalvikInsn.opcode) {
-        case OP_ADD_FLOAT_2ADDR:
-        case OP_ADD_FLOAT:
+        case Instruction::ADD_FLOAT_2ADDR:
+        case Instruction::ADD_FLOAT:
             op = kThumb2Vadds;
             break;
-        case OP_SUB_FLOAT_2ADDR:
-        case OP_SUB_FLOAT:
+        case Instruction::SUB_FLOAT_2ADDR:
+        case Instruction::SUB_FLOAT:
             op = kThumb2Vsubs;
             break;
-        case OP_DIV_FLOAT_2ADDR:
-        case OP_DIV_FLOAT:
+        case Instruction::DIV_FLOAT_2ADDR:
+        case Instruction::DIV_FLOAT:
             op = kThumb2Vdivs;
             break;
-        case OP_MUL_FLOAT_2ADDR:
-        case OP_MUL_FLOAT:
+        case Instruction::MUL_FLOAT_2ADDR:
+        case Instruction::MUL_FLOAT:
             op = kThumb2Vmuls;
             break;
-        case OP_REM_FLOAT_2ADDR:
-        case OP_REM_FLOAT:
-        case OP_NEG_FLOAT: {
+        case Instruction::REM_FLOAT_2ADDR:
+        case Instruction::REM_FLOAT:
+        case Instruction::NEG_FLOAT: {
             return genArithOpFloatPortable(cUnit, mir, rlDest, rlSrc1,
                                               rlSrc2);
         }
@@ -68,25 +68,25 @@
     RegLocation rlResult;
 
     switch (mir->dalvikInsn.opcode) {
-        case OP_ADD_DOUBLE_2ADDR:
-        case OP_ADD_DOUBLE:
+        case Instruction::ADD_DOUBLE_2ADDR:
+        case Instruction::ADD_DOUBLE:
             op = kThumb2Vaddd;
             break;
-        case OP_SUB_DOUBLE_2ADDR:
-        case OP_SUB_DOUBLE:
+        case Instruction::SUB_DOUBLE_2ADDR:
+        case Instruction::SUB_DOUBLE:
             op = kThumb2Vsubd;
             break;
-        case OP_DIV_DOUBLE_2ADDR:
-        case OP_DIV_DOUBLE:
+        case Instruction::DIV_DOUBLE_2ADDR:
+        case Instruction::DIV_DOUBLE:
             op = kThumb2Vdivd;
             break;
-        case OP_MUL_DOUBLE_2ADDR:
-        case OP_MUL_DOUBLE:
+        case Instruction::MUL_DOUBLE_2ADDR:
+        case Instruction::MUL_DOUBLE:
             op = kThumb2Vmuld;
             break;
-        case OP_REM_DOUBLE_2ADDR:
-        case OP_REM_DOUBLE:
-        case OP_NEG_DOUBLE: {
+        case Instruction::REM_DOUBLE_2ADDR:
+        case Instruction::REM_DOUBLE:
+        case Instruction::NEG_DOUBLE: {
             return genArithOpDoublePortable(cUnit, mir, rlDest, rlSrc1,
                                                rlSrc2);
         }
@@ -110,7 +110,7 @@
 
 bool genConversion(CompilationUnit* cUnit, MIR* mir)
 {
-    Opcode opcode = mir->dalvikInsn.opcode;
+    Instruction::Code opcode = mir->dalvikInsn.opcode;
     int op = kThumbBkpt;
     bool longSrc = false;
     bool longDest = false;
@@ -120,40 +120,40 @@
     RegLocation rlResult;
 
     switch (opcode) {
-        case OP_INT_TO_FLOAT:
+        case Instruction::INT_TO_FLOAT:
             longSrc = false;
             longDest = false;
             op = kThumb2VcvtIF;
             break;
-        case OP_FLOAT_TO_INT:
+        case Instruction::FLOAT_TO_INT:
             longSrc = false;
             longDest = false;
             op = kThumb2VcvtFI;
             break;
-        case OP_DOUBLE_TO_FLOAT:
+        case Instruction::DOUBLE_TO_FLOAT:
             longSrc = true;
             longDest = false;
             op = kThumb2VcvtDF;
             break;
-        case OP_FLOAT_TO_DOUBLE:
+        case Instruction::FLOAT_TO_DOUBLE:
             longSrc = false;
             longDest = true;
             op = kThumb2VcvtFd;
             break;
-        case OP_INT_TO_DOUBLE:
+        case Instruction::INT_TO_DOUBLE:
             longSrc = false;
             longDest = true;
             op = kThumb2VcvtID;
             break;
-        case OP_DOUBLE_TO_INT:
+        case Instruction::DOUBLE_TO_INT:
             longSrc = true;
             longDest = false;
             op = kThumb2VcvtDI;
             break;
-        case OP_LONG_TO_DOUBLE:
-        case OP_FLOAT_TO_LONG:
-        case OP_LONG_TO_FLOAT:
-        case OP_DOUBLE_TO_LONG:
+        case Instruction::LONG_TO_DOUBLE:
+        case Instruction::FLOAT_TO_LONG:
+        case Instruction::LONG_TO_FLOAT:
+        case Instruction::DOUBLE_TO_LONG:
             return genConversionPortable(cUnit, mir);
         default:
             return true;
@@ -190,19 +190,19 @@
     RegLocation rlResult;
 
     switch(mir->dalvikInsn.opcode) {
-        case OP_CMPL_FLOAT:
+        case Instruction::CMPL_FLOAT:
             isDouble = false;
             defaultResult = -1;
             break;
-        case OP_CMPG_FLOAT:
+        case Instruction::CMPG_FLOAT:
             isDouble = false;
             defaultResult = 1;
             break;
-        case OP_CMPL_DOUBLE:
+        case Instruction::CMPL_DOUBLE:
             isDouble = true;
             defaultResult = -1;
             break;
-        case OP_CMPG_DOUBLE:
+        case Instruction::CMPG_DOUBLE:
             isDouble = true;
             defaultResult = 1;
             break;
diff --git a/src/compiler/codegen/mips/FP/MipsFP.cc b/src/compiler/codegen/mips/FP/MipsFP.cc
index 64061fe..3bbb3d7 100644
--- a/src/compiler/codegen/mips/FP/MipsFP.cc
+++ b/src/compiler/codegen/mips/FP/MipsFP.cc
@@ -28,25 +28,25 @@
      * the handlers.
      */
     switch (mir->dalvikInsn.opcode) {
-        case OP_ADD_FLOAT_2ADDR:
-        case OP_ADD_FLOAT:
+        case Instruction::ADD_FLOAT_2ADDR:
+        case Instruction::ADD_FLOAT:
             op = kMipsFadds;
             break;
-        case OP_SUB_FLOAT_2ADDR:
-        case OP_SUB_FLOAT:
+        case Instruction::SUB_FLOAT_2ADDR:
+        case Instruction::SUB_FLOAT:
             op = kMipsFsubs;
             break;
-        case OP_DIV_FLOAT_2ADDR:
-        case OP_DIV_FLOAT:
+        case Instruction::DIV_FLOAT_2ADDR:
+        case Instruction::DIV_FLOAT:
             op = kMipsFdivs;
             break;
-        case OP_MUL_FLOAT_2ADDR:
-        case OP_MUL_FLOAT:
+        case Instruction::MUL_FLOAT_2ADDR:
+        case Instruction::MUL_FLOAT:
             op = kMipsFmuls;
             break;
-        case OP_REM_FLOAT_2ADDR:
-        case OP_REM_FLOAT:
-        case OP_NEG_FLOAT: {
+        case Instruction::REM_FLOAT_2ADDR:
+        case Instruction::REM_FLOAT:
+        case Instruction::NEG_FLOAT: {
             return genArithOpFloatPortable(cUnit, mir, rlDest, rlSrc1, rlSrc2);
         }
         default:
@@ -74,25 +74,25 @@
     RegLocation rlResult;
 
     switch (mir->dalvikInsn.opcode) {
-        case OP_ADD_DOUBLE_2ADDR:
-        case OP_ADD_DOUBLE:
+        case Instruction::ADD_DOUBLE_2ADDR:
+        case Instruction::ADD_DOUBLE:
             op = kMipsFaddd;
             break;
-        case OP_SUB_DOUBLE_2ADDR:
-        case OP_SUB_DOUBLE:
+        case Instruction::SUB_DOUBLE_2ADDR:
+        case Instruction::SUB_DOUBLE:
             op = kMipsFsubd;
             break;
-        case OP_DIV_DOUBLE_2ADDR:
-        case OP_DIV_DOUBLE:
+        case Instruction::DIV_DOUBLE_2ADDR:
+        case Instruction::DIV_DOUBLE:
             op = kMipsFdivd;
             break;
-        case OP_MUL_DOUBLE_2ADDR:
-        case OP_MUL_DOUBLE:
+        case Instruction::MUL_DOUBLE_2ADDR:
+        case Instruction::MUL_DOUBLE:
             op = kMipsFmuld;
             break;
-        case OP_REM_DOUBLE_2ADDR:
-        case OP_REM_DOUBLE:
-        case OP_NEG_DOUBLE: {
+        case Instruction::REM_DOUBLE_2ADDR:
+        case Instruction::REM_DOUBLE:
+        case Instruction::NEG_DOUBLE: {
             return genArithOpDoublePortable(cUnit, mir, rlDest, rlSrc1, rlSrc2);
         }
         default:
@@ -118,7 +118,7 @@
 static bool genConversion(CompilationUnit *cUnit, MIR *mir)
 {
 #ifdef __mips_hard_float
-    Opcode opcode = mir->dalvikInsn.opcode;
+    Instruction::Code opcode = mir->dalvikInsn.opcode;
     bool longSrc = false;
     bool longDest = false;
     RegLocation rlSrc;
@@ -127,32 +127,32 @@
     int srcReg;
     RegLocation rlResult;
     switch (opcode) {
-        case OP_INT_TO_FLOAT:
+        case Instruction::INT_TO_FLOAT:
             longSrc = false;
             longDest = false;
             op = kMipsFcvtsw;
             break;
-        case OP_DOUBLE_TO_FLOAT:
+        case Instruction::DOUBLE_TO_FLOAT:
             longSrc = true;
             longDest = false;
             op = kMipsFcvtsd;
             break;
-        case OP_FLOAT_TO_DOUBLE:
+        case Instruction::FLOAT_TO_DOUBLE:
             longSrc = false;
             longDest = true;
             op = kMipsFcvtds;
             break;
-        case OP_INT_TO_DOUBLE:
+        case Instruction::INT_TO_DOUBLE:
             longSrc = false;
             longDest = true;
             op = kMipsFcvtdw;
             break;
-        case OP_FLOAT_TO_INT:
-        case OP_DOUBLE_TO_INT:
-        case OP_LONG_TO_DOUBLE:
-        case OP_FLOAT_TO_LONG:
-        case OP_LONG_TO_FLOAT:
-        case OP_DOUBLE_TO_LONG:
+        case Instruction::FLOAT_TO_INT:
+        case Instruction::DOUBLE_TO_INT:
+        case Instruction::LONG_TO_DOUBLE:
+        case Instruction::FLOAT_TO_LONG:
+        case Instruction::LONG_TO_FLOAT:
+        case Instruction::DOUBLE_TO_LONG:
             return genConversionPortable(cUnit, mir);
         default:
             return true;
@@ -190,18 +190,18 @@
     int offset;
 
     switch(mir->dalvikInsn.opcode) {
-        case OP_CMPL_FLOAT:
+        case Instruction::CMPL_FLOAT:
             offset = OFFSETOF_MEMBER(Thread, pCmplFloat);
             wide = false;
             break;
-        case OP_CMPG_FLOAT:
+        case Instruction::CMPG_FLOAT:
             offset = OFFSETOF_MEMBER(Thread, pCmpgFloat);
             wide = false;
             break;
-        case OP_CMPL_DOUBLE:
+        case Instruction::CMPL_DOUBLE:
             offset = OFFSETOF_MEMBER(Thread, pCmplDouble);
             break;
-        case OP_CMPG_DOUBLE:
+        case Instruction::CMPG_DOUBLE:
             offset = OFFSETOF_MEMBER(Thread, pCmpgDouble);
             break;
         default:
diff --git a/src/compiler/codegen/x86/FP/X86FP.cc b/src/compiler/codegen/x86/FP/X86FP.cc
index 57cde49..5e59b56 100644
--- a/src/compiler/codegen/x86/FP/X86FP.cc
+++ b/src/compiler/codegen/x86/FP/X86FP.cc
@@ -30,25 +30,25 @@
      * the handlers.
      */
     switch (mir->dalvikInsn.opcode) {
-        case OP_ADD_FLOAT_2ADDR:
-        case OP_ADD_FLOAT:
+        case Instruction::ADD_FLOAT_2ADDR:
+        case Instruction::ADD_FLOAT:
             op = kX86Fadds;
             break;
-        case OP_SUB_FLOAT_2ADDR:
-        case OP_SUB_FLOAT:
+        case Instruction::SUB_FLOAT_2ADDR:
+        case Instruction::SUB_FLOAT:
             op = kX86Fsubs;
             break;
-        case OP_DIV_FLOAT_2ADDR:
-        case OP_DIV_FLOAT:
+        case Instruction::DIV_FLOAT_2ADDR:
+        case Instruction::DIV_FLOAT:
             op = kX86Fdivs;
             break;
-        case OP_MUL_FLOAT_2ADDR:
-        case OP_MUL_FLOAT:
+        case Instruction::MUL_FLOAT_2ADDR:
+        case Instruction::MUL_FLOAT:
             op = kX86Fmuls;
             break;
-        case OP_REM_FLOAT_2ADDR:
-        case OP_REM_FLOAT:
-        case OP_NEG_FLOAT: {
+        case Instruction::REM_FLOAT_2ADDR:
+        case Instruction::REM_FLOAT:
+        case Instruction::NEG_FLOAT: {
             return genArithOpFloatPortable(cUnit, mir, rlDest, rlSrc1, rlSrc2);
         }
         default:
@@ -76,25 +76,25 @@
     RegLocation rlResult;
 
     switch (mir->dalvikInsn.opcode) {
-        case OP_ADD_DOUBLE_2ADDR:
-        case OP_ADD_DOUBLE:
+        case Instruction::ADD_DOUBLE_2ADDR:
+        case Instruction::ADD_DOUBLE:
             op = kX86Faddd;
             break;
-        case OP_SUB_DOUBLE_2ADDR:
-        case OP_SUB_DOUBLE:
+        case Instruction::SUB_DOUBLE_2ADDR:
+        case Instruction::SUB_DOUBLE:
             op = kX86Fsubd;
             break;
-        case OP_DIV_DOUBLE_2ADDR:
-        case OP_DIV_DOUBLE:
+        case Instruction::DIV_DOUBLE_2ADDR:
+        case Instruction::DIV_DOUBLE:
             op = kX86Fdivd;
             break;
-        case OP_MUL_DOUBLE_2ADDR:
-        case OP_MUL_DOUBLE:
+        case Instruction::MUL_DOUBLE_2ADDR:
+        case Instruction::MUL_DOUBLE:
             op = kX86Fmuld;
             break;
-        case OP_REM_DOUBLE_2ADDR:
-        case OP_REM_DOUBLE:
-        case OP_NEG_DOUBLE: {
+        case Instruction::REM_DOUBLE_2ADDR:
+        case Instruction::REM_DOUBLE:
+        case Instruction::NEG_DOUBLE: {
             return genArithOpDoublePortable(cUnit, mir, rlDest, rlSrc1, rlSrc2);
         }
         default:
@@ -120,7 +120,7 @@
     UNIMPLEMENTED(WARNING) << "genConversion";
     return false;
 #if 0
-    Opcode opcode = mir->dalvikInsn.opcode;
+    Instruction::Code opcode = mir->dalvikInsn.opcode;
     bool longSrc = false;
     bool longDest = false;
     RegLocation rlSrc;
@@ -129,32 +129,32 @@
     int srcReg;
     RegLocation rlResult;
     switch (opcode) {
-        case OP_INT_TO_FLOAT:
+        case Instruction::INT_TO_FLOAT:
             longSrc = false;
             longDest = false;
             op = kX86Fcvtsw;
             break;
-        case OP_DOUBLE_TO_FLOAT:
+        case Instruction::DOUBLE_TO_FLOAT:
             longSrc = true;
             longDest = false;
             op = kX86Fcvtsd;
             break;
-        case OP_FLOAT_TO_DOUBLE:
+        case Instruction::FLOAT_TO_DOUBLE:
             longSrc = false;
             longDest = true;
             op = kX86Fcvtds;
             break;
-        case OP_INT_TO_DOUBLE:
+        case Instruction::INT_TO_DOUBLE:
             longSrc = false;
             longDest = true;
             op = kX86Fcvtdw;
             break;
-        case OP_FLOAT_TO_INT:
-        case OP_DOUBLE_TO_INT:
-        case OP_LONG_TO_DOUBLE:
-        case OP_FLOAT_TO_LONG:
-        case OP_LONG_TO_FLOAT:
-        case OP_DOUBLE_TO_LONG:
+        case Instruction::FLOAT_TO_INT:
+        case Instruction::DOUBLE_TO_INT:
+        case Instruction::LONG_TO_DOUBLE:
+        case Instruction::FLOAT_TO_LONG:
+        case Instruction::LONG_TO_FLOAT:
+        case Instruction::DOUBLE_TO_LONG:
             return genConversionPortable(cUnit, mir);
         default:
             return true;
@@ -192,18 +192,18 @@
     int offset;
 
     switch(mir->dalvikInsn.opcode) {
-        case OP_CMPL_FLOAT:
+        case Instruction::CMPL_FLOAT:
             offset = OFFSETOF_MEMBER(Thread, pCmplFloat);
             wide = false;
             break;
-        case OP_CMPG_FLOAT:
+        case Instruction::CMPG_FLOAT:
             offset = OFFSETOF_MEMBER(Thread, pCmpgFloat);
             wide = false;
             break;
-        case OP_CMPL_DOUBLE:
+        case Instruction::CMPL_DOUBLE:
             offset = OFFSETOF_MEMBER(Thread, pCmplDouble);
             break;
-        case OP_CMPG_DOUBLE:
+        case Instruction::CMPG_DOUBLE:
             offset = OFFSETOF_MEMBER(Thread, pCmpgDouble);
             break;
         default:
diff --git a/src/compiler_llvm/method_compiler.cc b/src/compiler_llvm/method_compiler.cc
index 4694777..c1c9e19 100644
--- a/src/compiler_llvm/method_compiler.cc
+++ b/src/compiler_llvm/method_compiler.cc
@@ -1144,10 +1144,10 @@
                                    Instruction const* insn,
                                    JType jty) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB_, jty, kReg);
-  EmitStoreDalvikReg(dec_insn.vA_, jty, kReg, src_value);
+  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB, jty, kReg);
+  EmitStoreDalvikReg(dec_insn.vA, jty, kReg, src_value);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -1157,10 +1157,10 @@
                                          Instruction const* insn,
                                          JType jty) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   llvm::Value* src_value = EmitLoadDalvikRetValReg(jty, kReg);
-  EmitStoreDalvikReg(dec_insn.vA_, jty, kReg, src_value);
+  EmitStoreDalvikReg(dec_insn.vA, jty, kReg, src_value);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -1169,7 +1169,7 @@
 void MethodCompiler::EmitInsn_MoveException(uint32_t dex_pc,
                                             Instruction const* insn) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   // Get thread-local exception field address
   llvm::Constant* exception_field_offset =
@@ -1189,7 +1189,7 @@
   irb_.CreateStore(irb_.getJNull(), exception_field_addr);
 
   // Keep the exception object in the Dalvik register
-  EmitStoreDalvikReg(dec_insn.vA_, kObject, kAccurate, exception_object_addr);
+  EmitStoreDalvikReg(dec_insn.vA, kObject, kAccurate, exception_object_addr);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -1198,10 +1198,10 @@
 void MethodCompiler::EmitInsn_ThrowException(uint32_t dex_pc,
                                              Instruction const* insn) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   llvm::Value* exception_addr =
-    EmitLoadDalvikReg(dec_insn.vA_, kObject, kAccurate);
+    EmitLoadDalvikReg(dec_insn.vA, kObject, kAccurate);
 
   EmitUpdateLineNumFromDexPC(dex_pc);
 
@@ -1227,7 +1227,7 @@
 void MethodCompiler::EmitInsn_Return(uint32_t dex_pc,
                                      Instruction const* insn) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   // Garbage collection safe-point
   EmitGuard_GarbageCollectionSuspend(dex_pc);
@@ -1239,7 +1239,7 @@
 
   // Return!
   char ret_shorty = method_helper_.GetShorty()[0];
-  llvm::Value* retval = EmitLoadDalvikReg(dec_insn.vA_, ret_shorty, kAccurate);
+  llvm::Value* retval = EmitLoadDalvikReg(dec_insn.vA, ret_shorty, kAccurate);
 
   irb_.CreateRet(retval);
 }
@@ -1249,7 +1249,7 @@
                                            Instruction const* insn,
                                            JType imm_jty) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   DCHECK(imm_jty == kInt || imm_jty == kLong) << imm_jty;
 
@@ -1262,22 +1262,22 @@
   case Instruction::CONST:
   case Instruction::CONST_WIDE_16:
   case Instruction::CONST_WIDE_32:
-    imm = static_cast<int64_t>(static_cast<int32_t>(dec_insn.vB_));
+    imm = static_cast<int64_t>(static_cast<int32_t>(dec_insn.vB));
     break;
 
   case Instruction::CONST_HIGH16:
     imm = static_cast<int64_t>(static_cast<int32_t>(
-          static_cast<uint32_t>(static_cast<uint16_t>(dec_insn.vB_)) << 16));
+          static_cast<uint32_t>(static_cast<uint16_t>(dec_insn.vB)) << 16));
     break;
 
   // 64-bit Immediate
   case Instruction::CONST_WIDE:
-    imm = static_cast<int64_t>(dec_insn.vB_wide_);
+    imm = static_cast<int64_t>(dec_insn.vB_wide);
     break;
 
   case Instruction::CONST_WIDE_HIGH16:
     imm = static_cast<int64_t>(
-          static_cast<uint64_t>(static_cast<uint16_t>(dec_insn.vB_)) << 48);
+          static_cast<uint64_t>(static_cast<uint16_t>(dec_insn.vB)) << 48);
     break;
 
   // Unknown opcode for load constant (unreachable)
@@ -1289,11 +1289,11 @@
   // Store the non-object register
   llvm::Type* imm_type = irb_.getJType(imm_jty, kAccurate);
   llvm::Constant* imm_value = llvm::ConstantInt::getSigned(imm_type, imm);
-  EmitStoreDalvikReg(dec_insn.vA_, imm_jty, kAccurate, imm_value);
+  EmitStoreDalvikReg(dec_insn.vA, imm_jty, kAccurate, imm_value);
 
   // Store the object register if it is possible to be null.
   if (imm_jty == kInt && imm == 0) {
-    EmitStoreDalvikReg(dec_insn.vA_, kObject, kAccurate, irb_.getJNull());
+    EmitStoreDalvikReg(dec_insn.vA, kObject, kAccurate, irb_.getJNull());
   }
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
@@ -1303,9 +1303,9 @@
 void MethodCompiler::EmitInsn_LoadConstantString(uint32_t dex_pc,
                                                  Instruction const* insn) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  uint32_t string_idx = dec_insn.vB_;
+  uint32_t string_idx = dec_insn.vB;
 
   llvm::Value* string_field_addr = EmitLoadDexCacheStringFieldAddr(string_idx);
 
@@ -1325,7 +1325,7 @@
 
     // String is resolved, go to next basic block.
     irb_.SetInsertPoint(block_str_exist);
-    EmitStoreDalvikReg(dec_insn.vA_, kObject, kAccurate, string_addr);
+    EmitStoreDalvikReg(dec_insn.vA, kObject, kAccurate, string_addr);
     irb_.CreateBr(GetNextBasicBlock(dex_pc));
 
     // String is not resolved yet, resolve it now.
@@ -1346,7 +1346,7 @@
   }
 
   // Store the string object to the Dalvik register
-  EmitStoreDalvikReg(dec_insn.vA_, kObject, kAccurate, string_addr);
+  EmitStoreDalvikReg(dec_insn.vA, kObject, kAccurate, string_addr);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -1433,10 +1433,10 @@
 void MethodCompiler::EmitInsn_LoadConstantClass(uint32_t dex_pc,
                                                 Instruction const* insn) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  llvm::Value* type_object_addr = EmitLoadConstantClass(dex_pc, dec_insn.vB_);
-  EmitStoreDalvikReg(dec_insn.vA_, kObject, kAccurate, type_object_addr);
+  llvm::Value* type_object_addr = EmitLoadConstantClass(dex_pc, dec_insn.vB);
+  EmitStoreDalvikReg(dec_insn.vA, kObject, kAccurate, type_object_addr);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -1445,10 +1445,10 @@
 void MethodCompiler::EmitInsn_MonitorEnter(uint32_t dex_pc,
                                            Instruction const* insn) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   llvm::Value* object_addr =
-    EmitLoadDalvikReg(dec_insn.vA_, kObject, kAccurate);
+    EmitLoadDalvikReg(dec_insn.vA, kObject, kAccurate);
 
   // TODO: Slow path always. May not need NullPointerException check.
   EmitGuard_NullPointerException(dex_pc, object_addr);
@@ -1465,10 +1465,10 @@
 void MethodCompiler::EmitInsn_MonitorExit(uint32_t dex_pc,
                                           Instruction const* insn) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   llvm::Value* object_addr =
-    EmitLoadDalvikReg(dec_insn.vA_, kObject, kAccurate);
+    EmitLoadDalvikReg(dec_insn.vA, kObject, kAccurate);
 
   EmitGuard_NullPointerException(dex_pc, object_addr);
 
@@ -1484,7 +1484,7 @@
 void MethodCompiler::EmitInsn_CheckCast(uint32_t dex_pc,
                                         Instruction const* insn) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   llvm::BasicBlock* block_test_class =
     CreateBasicBlockWithDexPC(dex_pc, "test_class");
@@ -1493,7 +1493,7 @@
     CreateBasicBlockWithDexPC(dex_pc, "test_sub_class");
 
   llvm::Value* object_addr =
-    EmitLoadDalvikReg(dec_insn.vA_, kObject, kAccurate);
+    EmitLoadDalvikReg(dec_insn.vA, kObject, kAccurate);
 
   // Test: Is the reference equal to null?  Act as no-op when it is null.
   llvm::Value* equal_null = irb_.CreateICmpEQ(object_addr, irb_.getJNull());
@@ -1504,7 +1504,7 @@
 
   // Test: Is the object instantiated from the given class?
   irb_.SetInsertPoint(block_test_class);
-  llvm::Value* type_object_addr = EmitLoadConstantClass(dex_pc, dec_insn.vB_);
+  llvm::Value* type_object_addr = EmitLoadConstantClass(dex_pc, dec_insn.vB);
   DCHECK_EQ(Object::ClassOffset().Int32Value(), 0);
 
   llvm::PointerType* jobject_ptr_ty = irb_.getJObjectTy();
@@ -1539,7 +1539,7 @@
 void MethodCompiler::EmitInsn_InstanceOf(uint32_t dex_pc,
                                          Instruction const* insn) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   llvm::Constant* zero = irb_.getJInt(0);
   llvm::Constant* one = irb_.getJInt(1);
@@ -1556,7 +1556,7 @@
     CreateBasicBlockWithDexPC(dex_pc, "test_sub_class");
 
   llvm::Value* object_addr =
-    EmitLoadDalvikReg(dec_insn.vB_, kObject, kAccurate);
+    EmitLoadDalvikReg(dec_insn.vB, kObject, kAccurate);
 
   // Overview of the following code :
   // We check for null, if so, then false, otherwise check for class == . If so
@@ -1568,12 +1568,12 @@
   irb_.CreateCondBr(equal_null, block_nullp, block_test_class);
 
   irb_.SetInsertPoint(block_nullp);
-  EmitStoreDalvikReg(dec_insn.vA_, kInt, kAccurate, zero);
+  EmitStoreDalvikReg(dec_insn.vA, kInt, kAccurate, zero);
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 
   // Test: Is the object instantiated from the given class?
   irb_.SetInsertPoint(block_test_class);
-  llvm::Value* type_object_addr = EmitLoadConstantClass(dex_pc, dec_insn.vC_);
+  llvm::Value* type_object_addr = EmitLoadConstantClass(dex_pc, dec_insn.vC);
   DCHECK_EQ(Object::ClassOffset().Int32Value(), 0);
 
   llvm::PointerType* jobject_ptr_ty = irb_.getJObjectTy();
@@ -1590,7 +1590,7 @@
   irb_.CreateCondBr(equal_class, block_class_equals, block_test_sub_class);
 
   irb_.SetInsertPoint(block_class_equals);
-  EmitStoreDalvikReg(dec_insn.vA_, kInt, kAccurate, one);
+  EmitStoreDalvikReg(dec_insn.vA, kInt, kAccurate, one);
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 
   // Test: Is the object instantiated from the subclass of the given class?
@@ -1600,7 +1600,7 @@
     irb_.CreateCall2(irb_.GetRuntime(IsAssignable),
                      type_object_addr, object_type_object_addr);
 
-  EmitStoreDalvikReg(dec_insn.vA_, kInt, kAccurate, result);
+  EmitStoreDalvikReg(dec_insn.vA, kInt, kAccurate, result);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -1623,15 +1623,15 @@
 void MethodCompiler::EmitInsn_ArrayLength(uint32_t dex_pc,
                                           Instruction const* insn) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   // Get the array object address
-  llvm::Value* array_addr = EmitLoadDalvikReg(dec_insn.vB_, kObject, kAccurate);
+  llvm::Value* array_addr = EmitLoadDalvikReg(dec_insn.vB, kObject, kAccurate);
   EmitGuard_NullPointerException(dex_pc, array_addr);
 
   // Get the array length and store it to the register
   llvm::Value* array_len = EmitLoadArrayLength(array_addr);
-  EmitStoreDalvikReg(dec_insn.vA_, kInt, kAccurate, array_len);
+  EmitStoreDalvikReg(dec_insn.vA, kInt, kAccurate, array_len);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -1640,17 +1640,17 @@
 void MethodCompiler::EmitInsn_NewInstance(uint32_t dex_pc,
                                           Instruction const* insn) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   llvm::Function* runtime_func;
   if (compiler_->CanAccessTypeWithoutChecks(method_idx_, dex_cache_,
-                                            *dex_file_, dec_insn.vB_)) {
+                                            *dex_file_, dec_insn.vB)) {
     runtime_func = irb_.GetRuntime(AllocObject);
   } else {
     runtime_func = irb_.GetRuntime(AllocObjectWithAccessCheck);
   }
 
-  llvm::Constant* type_index_value = irb_.getInt32(dec_insn.vB_);
+  llvm::Constant* type_index_value = irb_.getInt32(dec_insn.vB);
 
   llvm::Value* method_object_addr = EmitLoadMethodObjectAddr();
 
@@ -1661,7 +1661,7 @@
 
   EmitGuard_ExceptionLandingPad(dex_pc);
 
-  EmitStoreDalvikReg(dec_insn.vA_, kObject, kAccurate, object_addr);
+  EmitStoreDalvikReg(dec_insn.vA, kObject, kAccurate, object_addr);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -1708,12 +1708,12 @@
 void MethodCompiler::EmitInsn_NewArray(uint32_t dex_pc,
                                        Instruction const* insn) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   llvm::Value* object_addr =
-    EmitAllocNewArray(dex_pc, dec_insn.vB_, dec_insn.vC_, false);
+    EmitAllocNewArray(dex_pc, dec_insn.vB, dec_insn.vC, false);
 
-  EmitStoreDalvikReg(dec_insn.vA_, kObject, kAccurate, object_addr);
+  EmitStoreDalvikReg(dec_insn.vA, kObject, kAccurate, object_addr);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -1723,12 +1723,12 @@
                                              Instruction const* insn,
                                              bool is_range) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   llvm::Value* object_addr =
-    EmitAllocNewArray(dex_pc, dec_insn.vA_, dec_insn.vB_, true);
+    EmitAllocNewArray(dex_pc, dec_insn.vA, dec_insn.vB, true);
 
-  if (dec_insn.vA_ > 0) {
+  if (dec_insn.vA > 0) {
     llvm::Value* object_addr_int =
       irb_.CreatePtrToInt(object_addr, irb_.getPtrEquivIntTy());
 
@@ -1741,7 +1741,7 @@
     llvm::Value* data_field_addr_int =
       irb_.CreateAdd(object_addr_int, data_field_offset);
 
-    Class* klass = method_->GetDexCacheResolvedTypes()->Get(dec_insn.vB_);
+    Class* klass = method_->GetDexCacheResolvedTypes()->Get(dec_insn.vB);
     CHECK_NE(klass, static_cast<Class*>(NULL));
     // Moved this below already: CHECK(!klass->IsPrimitive() || klass->IsPrimitiveInt());
 
@@ -1759,15 +1759,15 @@
     // one element which may be very space consuming.  Maybe changing to use
     // memcpy may help; however, since we can't guarantee that the alloca of
     // dalvik register are continuous, we can't perform such optimization yet.
-    for (uint32_t i = 0; i < dec_insn.vA_; ++i) {
+    for (uint32_t i = 0; i < dec_insn.vA; ++i) {
       llvm::Value* data_field_addr =
         irb_.CreateIntToPtr(data_field_addr_int, field_type);
 
       int reg_index;
       if (is_range) {
-        reg_index = dec_insn.vC_ + i;
+        reg_index = dec_insn.vC + i;
       } else {
-        reg_index = dec_insn.arg_[i];
+        reg_index = dec_insn.arg[i];
       }
 
       llvm::Value* reg_value;
@@ -1792,7 +1792,7 @@
 void MethodCompiler::EmitInsn_FillArrayData(uint32_t dex_pc,
                                             Instruction const* insn) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   // Read the payload
   struct PACKED Payload {
@@ -1803,7 +1803,7 @@
   };
 
   int32_t payload_offset = static_cast<int32_t>(dex_pc) +
-                           static_cast<int32_t>(dec_insn.vB_);
+                           static_cast<int32_t>(dec_insn.vB);
 
   Payload const* payload =
     reinterpret_cast<Payload const*>(code_item_->insns_ + payload_offset);
@@ -1811,7 +1811,7 @@
   uint32_t size_in_bytes = payload->elem_width_ * payload->num_elems_;
 
   // Load and check the array
-  llvm::Value* array_addr = EmitLoadDalvikReg(dec_insn.vA_, kObject, kAccurate);
+  llvm::Value* array_addr = EmitLoadDalvikReg(dec_insn.vA, kObject, kAccurate);
 
   EmitGuard_NullPointerException(dex_pc, array_addr);
 
@@ -1879,9 +1879,9 @@
 void MethodCompiler::EmitInsn_UnconditionalBranch(uint32_t dex_pc,
                                                   Instruction const* insn) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  int32_t branch_offset = dec_insn.vA_;
+  int32_t branch_offset = dec_insn.vA;
 
   if (branch_offset <= 0) {
     // Garbage collection safe-point on backward branch
@@ -1895,7 +1895,7 @@
 void MethodCompiler::EmitInsn_PackedSwitch(uint32_t dex_pc,
                                            Instruction const* insn) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   struct PACKED Payload {
     uint16_t ident_;
@@ -1905,12 +1905,12 @@
   };
 
   int32_t payload_offset = static_cast<int32_t>(dex_pc) +
-                           static_cast<int32_t>(dec_insn.vB_);
+                           static_cast<int32_t>(dec_insn.vB);
 
   Payload const* payload =
     reinterpret_cast<Payload const*>(code_item_->insns_ + payload_offset);
 
-  llvm::Value* value = EmitLoadDalvikReg(dec_insn.vA_, kInt, kAccurate);
+  llvm::Value* value = EmitLoadDalvikReg(dec_insn.vA, kInt, kAccurate);
 
   llvm::SwitchInst* sw =
     irb_.CreateSwitch(value, GetNextBasicBlock(dex_pc), payload->num_cases_);
@@ -1925,7 +1925,7 @@
 void MethodCompiler::EmitInsn_SparseSwitch(uint32_t dex_pc,
                                            Instruction const* insn) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   struct PACKED Payload {
     uint16_t ident_;
@@ -1934,7 +1934,7 @@
   };
 
   int32_t payload_offset = static_cast<int32_t>(dex_pc) +
-                           static_cast<int32_t>(dec_insn.vB_);
+                           static_cast<int32_t>(dec_insn.vB);
 
   Payload const* payload =
     reinterpret_cast<Payload const*>(code_item_->insns_ + payload_offset);
@@ -1942,7 +1942,7 @@
   int32_t const* keys = payload->keys_and_targets_;
   int32_t const* targets = payload->keys_and_targets_ + payload->num_cases_;
 
-  llvm::Value* value = EmitLoadDalvikReg(dec_insn.vA_, kInt, kAccurate);
+  llvm::Value* value = EmitLoadDalvikReg(dec_insn.vA, kInt, kAccurate);
 
   llvm::SwitchInst* sw =
     irb_.CreateSwitch(value, GetNextBasicBlock(dex_pc), payload->num_cases_);
@@ -1958,12 +1958,12 @@
                                         JType fp_jty,
                                         bool gt_bias) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   DCHECK(fp_jty == kFloat || fp_jty == kDouble) << "JType: " << fp_jty;
 
-  llvm::Value* src1_value = EmitLoadDalvikReg(dec_insn.vB_, fp_jty, kAccurate);
-  llvm::Value* src2_value = EmitLoadDalvikReg(dec_insn.vC_, fp_jty, kAccurate);
+  llvm::Value* src1_value = EmitLoadDalvikReg(dec_insn.vB, fp_jty, kAccurate);
+  llvm::Value* src2_value = EmitLoadDalvikReg(dec_insn.vC, fp_jty, kAccurate);
 
   llvm::Value* cmp_eq = irb_.CreateFCmpOEQ(src1_value, src2_value);
   llvm::Value* cmp_lt;
@@ -1975,7 +1975,7 @@
   }
 
   llvm::Value* result = EmitCompareResultSelection(cmp_eq, cmp_lt);
-  EmitStoreDalvikReg(dec_insn.vA_, kInt, kAccurate, result);
+  EmitStoreDalvikReg(dec_insn.vA, kInt, kAccurate, result);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -1984,16 +1984,16 @@
 void MethodCompiler::EmitInsn_LongCompare(uint32_t dex_pc,
                                           Instruction const* insn) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  llvm::Value* src1_value = EmitLoadDalvikReg(dec_insn.vB_, kLong, kAccurate);
-  llvm::Value* src2_value = EmitLoadDalvikReg(dec_insn.vC_, kLong, kAccurate);
+  llvm::Value* src1_value = EmitLoadDalvikReg(dec_insn.vB, kLong, kAccurate);
+  llvm::Value* src2_value = EmitLoadDalvikReg(dec_insn.vC, kLong, kAccurate);
 
   llvm::Value* cmp_eq = irb_.CreateICmpEQ(src1_value, src2_value);
   llvm::Value* cmp_lt = irb_.CreateICmpSLT(src1_value, src2_value);
 
   llvm::Value* result = EmitCompareResultSelection(cmp_eq, cmp_lt);
-  EmitStoreDalvikReg(dec_insn.vA_, kInt, kAccurate, result);
+  EmitStoreDalvikReg(dec_insn.vA, kInt, kAccurate, result);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -2017,17 +2017,17 @@
                                                       Instruction const* insn,
                                                       CondBranchKind cond) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  int8_t src1_reg_cat = GetInferredRegCategory(dex_pc, dec_insn.vA_);
-  int8_t src2_reg_cat = GetInferredRegCategory(dex_pc, dec_insn.vB_);
+  int8_t src1_reg_cat = GetInferredRegCategory(dex_pc, dec_insn.vA);
+  int8_t src2_reg_cat = GetInferredRegCategory(dex_pc, dec_insn.vB);
 
   DCHECK_NE(kRegUnknown, src1_reg_cat);
   DCHECK_NE(kRegUnknown, src2_reg_cat);
   DCHECK_NE(kRegCat2, src1_reg_cat);
   DCHECK_NE(kRegCat2, src2_reg_cat);
 
-  int32_t branch_offset = dec_insn.vC_;
+  int32_t branch_offset = dec_insn.vC;
 
   if (branch_offset <= 0) {
     // Garbage collection safe-point on backward branch
@@ -2046,11 +2046,11 @@
     CHECK_EQ(src1_reg_cat, src2_reg_cat);
 
     if (src1_reg_cat == kRegCat1nr) {
-      src1_value = EmitLoadDalvikReg(dec_insn.vA_, kInt, kAccurate);
-      src2_value = EmitLoadDalvikReg(dec_insn.vB_, kInt, kAccurate);
+      src1_value = EmitLoadDalvikReg(dec_insn.vA, kInt, kAccurate);
+      src2_value = EmitLoadDalvikReg(dec_insn.vB, kInt, kAccurate);
     } else {
-      src1_value = EmitLoadDalvikReg(dec_insn.vA_, kObject, kAccurate);
-      src2_value = EmitLoadDalvikReg(dec_insn.vB_, kObject, kAccurate);
+      src1_value = EmitLoadDalvikReg(dec_insn.vA, kObject, kAccurate);
+      src2_value = EmitLoadDalvikReg(dec_insn.vB, kObject, kAccurate);
     }
   } else {
     DCHECK(src1_reg_cat == kRegZero ||
@@ -2059,17 +2059,17 @@
     if (src1_reg_cat == kRegZero) {
       if (src2_reg_cat == kRegCat1nr) {
         src1_value = irb_.getJInt(0);
-        src2_value = EmitLoadDalvikReg(dec_insn.vA_, kInt, kAccurate);
+        src2_value = EmitLoadDalvikReg(dec_insn.vA, kInt, kAccurate);
       } else {
         src1_value = irb_.getJNull();
-        src2_value = EmitLoadDalvikReg(dec_insn.vA_, kObject, kAccurate);
+        src2_value = EmitLoadDalvikReg(dec_insn.vA, kObject, kAccurate);
       }
     } else { // src2_reg_cat == kRegZero
       if (src2_reg_cat == kRegCat1nr) {
-        src1_value = EmitLoadDalvikReg(dec_insn.vA_, kInt, kAccurate);
+        src1_value = EmitLoadDalvikReg(dec_insn.vA, kInt, kAccurate);
         src2_value = irb_.getJInt(0);
       } else {
-        src1_value = EmitLoadDalvikReg(dec_insn.vA_, kObject, kAccurate);
+        src1_value = EmitLoadDalvikReg(dec_insn.vA, kObject, kAccurate);
         src2_value = irb_.getJNull();
       }
     }
@@ -2088,14 +2088,14 @@
                                                      Instruction const* insn,
                                                      CondBranchKind cond) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  int8_t src_reg_cat = GetInferredRegCategory(dex_pc, dec_insn.vA_);
+  int8_t src_reg_cat = GetInferredRegCategory(dex_pc, dec_insn.vA);
 
   DCHECK_NE(kRegUnknown, src_reg_cat);
   DCHECK_NE(kRegCat2, src_reg_cat);
 
-  int32_t branch_offset = dec_insn.vB_;
+  int32_t branch_offset = dec_insn.vB;
 
   if (branch_offset <= 0) {
     // Garbage collection safe-point on backward branch
@@ -2111,10 +2111,10 @@
   llvm::Value* src2_value;
 
   if (src_reg_cat == kRegCat1nr) {
-    src1_value = EmitLoadDalvikReg(dec_insn.vA_, kInt, kAccurate);
+    src1_value = EmitLoadDalvikReg(dec_insn.vA, kInt, kAccurate);
     src2_value = irb_.getInt32(0);
   } else {
-    src1_value = EmitLoadDalvikReg(dec_insn.vA_, kObject, kAccurate);
+    src1_value = EmitLoadDalvikReg(dec_insn.vA, kObject, kAccurate);
     src2_value = irb_.getJNull();
   }
 
@@ -2228,10 +2228,10 @@
                                    Instruction const* insn,
                                    JType elem_jty) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  llvm::Value* array_addr = EmitLoadDalvikReg(dec_insn.vB_, kObject, kAccurate);
-  llvm::Value* index_value = EmitLoadDalvikReg(dec_insn.vC_, kInt, kAccurate);
+  llvm::Value* array_addr = EmitLoadDalvikReg(dec_insn.vB, kObject, kAccurate);
+  llvm::Value* index_value = EmitLoadDalvikReg(dec_insn.vC, kInt, kAccurate);
 
   EmitGuard_ArrayException(dex_pc, array_addr, index_value);
 
@@ -2242,7 +2242,7 @@
 
   llvm::Value* array_elem_value = irb_.CreateLoad(array_elem_addr);
 
-  EmitStoreDalvikReg(dec_insn.vA_, elem_jty, kArray, array_elem_value);
+  EmitStoreDalvikReg(dec_insn.vA, elem_jty, kArray, array_elem_value);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -2252,10 +2252,10 @@
                                    Instruction const* insn,
                                    JType elem_jty) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  llvm::Value* array_addr = EmitLoadDalvikReg(dec_insn.vB_, kObject, kAccurate);
-  llvm::Value* index_value = EmitLoadDalvikReg(dec_insn.vC_, kInt, kAccurate);
+  llvm::Value* array_addr = EmitLoadDalvikReg(dec_insn.vB, kObject, kAccurate);
+  llvm::Value* index_value = EmitLoadDalvikReg(dec_insn.vC, kInt, kAccurate);
 
   EmitGuard_ArrayException(dex_pc, array_addr, index_value);
 
@@ -2264,7 +2264,7 @@
   llvm::Value* array_elem_addr =
     EmitArrayGEP(array_addr, index_value, elem_type, elem_jty);
 
-  llvm::Value* new_value = EmitLoadDalvikReg(dec_insn.vA_, elem_jty, kArray);
+  llvm::Value* new_value = EmitLoadDalvikReg(dec_insn.vA, elem_jty, kArray);
 
   irb_.CreateStore(new_value, array_elem_addr);
 
@@ -2286,10 +2286,10 @@
                                    Instruction const* insn,
                                    JType field_jty) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  uint32_t reg_idx = dec_insn.vB_;
-  uint32_t field_idx = dec_insn.vC_;
+  uint32_t reg_idx = dec_insn.vB;
+  uint32_t field_idx = dec_insn.vC;
 
   Field* field = dex_cache_->GetResolvedField(field_idx);
 
@@ -2336,7 +2336,7 @@
     field_value = irb_.CreateLoad(field_addr);
   }
 
-  EmitStoreDalvikReg(dec_insn.vA_, field_jty, kField, field_value);
+  EmitStoreDalvikReg(dec_insn.vA, field_jty, kField, field_value);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -2346,10 +2346,10 @@
                                    Instruction const* insn,
                                    JType field_jty) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  uint32_t reg_idx = dec_insn.vB_;
-  uint32_t field_idx = dec_insn.vC_;
+  uint32_t reg_idx = dec_insn.vB;
+  uint32_t field_idx = dec_insn.vC;
 
   Field* field = dex_cache_->GetResolvedField(field_idx);
 
@@ -2357,7 +2357,7 @@
 
   EmitGuard_NullPointerException(dex_pc, object_addr);
 
-  llvm::Value* new_value = EmitLoadDalvikReg(dec_insn.vA_, field_jty, kField);
+  llvm::Value* new_value = EmitLoadDalvikReg(dec_insn.vA, field_jty, kField);
 
   if (field == NULL) {
     PrintUnresolvedFieldWarning(field_idx);
@@ -2563,11 +2563,11 @@
                                    Instruction const* insn,
                                    JType field_jty) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   uint32_t declaring_type_idx = DexFile::kDexNoIndex;
 
-  Field* field = FindFieldAndDeclaringTypeIdx(dec_insn.vB_, declaring_type_idx);
+  Field* field = FindFieldAndDeclaringTypeIdx(dec_insn.vB, declaring_type_idx);
 
   llvm::Value* static_field_value;
 
@@ -2582,7 +2582,7 @@
       runtime_func = irb_.GetRuntime(Get32Static);
     }
 
-    llvm::Constant* field_idx_value = irb_.getInt32(dec_insn.vB_);
+    llvm::Constant* field_idx_value = irb_.getInt32(dec_insn.vB);
 
     llvm::Value* method_object_addr = EmitLoadMethodObjectAddr();
 
@@ -2607,7 +2607,7 @@
     static_field_value = irb_.CreateLoad(static_field_addr);
   }
 
-  EmitStoreDalvikReg(dec_insn.vA_, field_jty, kField, static_field_value);
+  EmitStoreDalvikReg(dec_insn.vA, field_jty, kField, static_field_value);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -2617,13 +2617,13 @@
                                    Instruction const* insn,
                                    JType field_jty) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   uint32_t declaring_type_idx = DexFile::kDexNoIndex;
 
-  Field* field = FindFieldAndDeclaringTypeIdx(dec_insn.vB_, declaring_type_idx);
+  Field* field = FindFieldAndDeclaringTypeIdx(dec_insn.vB, declaring_type_idx);
 
-  llvm::Value* new_value = EmitLoadDalvikReg(dec_insn.vA_, field_jty, kField);
+  llvm::Value* new_value = EmitLoadDalvikReg(dec_insn.vA, field_jty, kField);
 
   if (field == NULL) {
     llvm::Function* runtime_func;
@@ -2636,7 +2636,7 @@
       runtime_func = irb_.GetRuntime(Set32Static);
     }
 
-    llvm::Constant* field_idx_value = irb_.getInt32(dec_insn.vB_);
+    llvm::Constant* field_idx_value = irb_.getInt32(dec_insn.vB);
 
     llvm::Value* method_object_addr = EmitLoadMethodObjectAddr();
 
@@ -2665,13 +2665,11 @@
 }
 
 
-llvm::Value* MethodCompiler::
-EmitLoadCalleeThis(Instruction::DecodedInstruction const& dec_insn,
-                   bool is_range) {
+llvm::Value* MethodCompiler::EmitLoadCalleeThis(DecodedInstruction const& dec_insn, bool is_range) {
   if (is_range) {
-    return EmitLoadDalvikReg(dec_insn.vC_, kObject, kAccurate);
+    return EmitLoadDalvikReg(dec_insn.vC, kObject, kAccurate);
   } else {
-    return EmitLoadDalvikReg(dec_insn.arg_[0], kObject, kAccurate);
+    return EmitLoadDalvikReg(dec_insn.arg[0], kObject, kAccurate);
   }
 }
 
@@ -2679,7 +2677,7 @@
 void MethodCompiler::
 EmitLoadActualParameters(std::vector<llvm::Value*>& args,
                          uint32_t callee_method_idx,
-                         Instruction::DecodedInstruction const& dec_insn,
+                         DecodedInstruction const& dec_insn,
                          bool is_range,
                          bool is_static) {
 
@@ -2699,8 +2697,8 @@
   }
 
   for (uint32_t i = 1; i < shorty_size; ++i) {
-    uint32_t reg_idx = (is_range) ? (dec_insn.vC_ + reg_count)
-                                  : (dec_insn.arg_[reg_count]);
+    uint32_t reg_idx = (is_range) ? (dec_insn.vC + reg_count)
+                                  : (dec_insn.arg[reg_count]);
 
     args.push_back(EmitLoadDalvikReg(reg_idx, shorty[i], kAccurate));
 
@@ -2712,7 +2710,7 @@
     }
   }
 
-  DCHECK_EQ(reg_count, dec_insn.vA_)
+  DCHECK_EQ(reg_count, dec_insn.vA)
     << "Actual argument mismatch for callee: "
     << PrettyMethod(callee_method_idx, *dex_file_);
 }
@@ -2723,9 +2721,9 @@
                                             Instruction const* insn,
                                             bool is_range) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  uint32_t callee_method_idx = dec_insn.vB_;
+  uint32_t callee_method_idx = dec_insn.vB;
 
   // Find the method object at compile time
   Method* callee_method = ResolveMethod(callee_method_idx);
@@ -2782,9 +2780,9 @@
                                           Instruction const* insn,
                                           bool is_range) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  uint32_t callee_method_idx = dec_insn.vB_;
+  uint32_t callee_method_idx = dec_insn.vB;
 
   // Find the method object at compile time
   Method* callee_overiding_method = ResolveMethod(callee_method_idx);
@@ -2877,9 +2875,9 @@
                                                  InvokeType invoke_type,
                                                  bool is_range) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  uint32_t callee_method_idx = dec_insn.vB_;
+  uint32_t callee_method_idx = dec_insn.vB;
 
   bool is_static = (invoke_type == kStatic);
 
@@ -2941,9 +2939,9 @@
                                               Instruction const* insn,
                                               bool is_range) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  uint32_t callee_method_idx = dec_insn.vB_;
+  uint32_t callee_method_idx = dec_insn.vB;
 
   // Resolve callee method
   Method* callee_method = ResolveMethod(callee_method_idx);
@@ -2994,13 +2992,13 @@
                                   Instruction const* insn,
                                   JType op_jty) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   DCHECK(op_jty == kInt || op_jty == kLong) << op_jty;
 
-  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB_, op_jty, kAccurate);
+  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB, op_jty, kAccurate);
   llvm::Value* result_value = irb_.CreateNeg(src_value);
-  EmitStoreDalvikReg(dec_insn.vA_, op_jty, kAccurate, result_value);
+  EmitStoreDalvikReg(dec_insn.vA, op_jty, kAccurate, result_value);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -3010,15 +3008,15 @@
                                   Instruction const* insn,
                                   JType op_jty) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   DCHECK(op_jty == kInt || op_jty == kLong) << op_jty;
 
-  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB_, op_jty, kAccurate);
+  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB, op_jty, kAccurate);
   llvm::Value* result_value =
     irb_.CreateXor(src_value, static_cast<uint64_t>(-1));
 
-  EmitStoreDalvikReg(dec_insn.vA_, op_jty, kAccurate, result_value);
+  EmitStoreDalvikReg(dec_insn.vA, op_jty, kAccurate, result_value);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -3027,11 +3025,11 @@
 void MethodCompiler::EmitInsn_SExt(uint32_t dex_pc,
                                    Instruction const* insn) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB_, kInt, kAccurate);
+  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB, kInt, kAccurate);
   llvm::Value* result_value = irb_.CreateSExt(src_value, irb_.getJLongTy());
-  EmitStoreDalvikReg(dec_insn.vA_, kLong, kAccurate, result_value);
+  EmitStoreDalvikReg(dec_insn.vA, kLong, kAccurate, result_value);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -3040,11 +3038,11 @@
 void MethodCompiler::EmitInsn_Trunc(uint32_t dex_pc,
                                     Instruction const* insn) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB_, kLong, kAccurate);
+  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB, kLong, kAccurate);
   llvm::Value* result_value = irb_.CreateTrunc(src_value, irb_.getJIntTy());
-  EmitStoreDalvikReg(dec_insn.vA_, kInt, kAccurate, result_value);
+  EmitStoreDalvikReg(dec_insn.vA, kInt, kAccurate, result_value);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -3054,16 +3052,16 @@
                                            Instruction const* insn,
                                            unsigned N) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB_, kInt, kAccurate);
+  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB, kInt, kAccurate);
 
   llvm::Value* trunc_value =
     irb_.CreateTrunc(src_value, llvm::Type::getIntNTy(*context_, N));
 
   llvm::Value* result_value = irb_.CreateSExt(trunc_value, irb_.getJIntTy());
 
-  EmitStoreDalvikReg(dec_insn.vA_, kInt, kAccurate, result_value);
+  EmitStoreDalvikReg(dec_insn.vA, kInt, kAccurate, result_value);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -3073,16 +3071,16 @@
                                            Instruction const* insn,
                                            unsigned N) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB_, kInt, kAccurate);
+  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB, kInt, kAccurate);
 
   llvm::Value* trunc_value =
     irb_.CreateTrunc(src_value, llvm::Type::getIntNTy(*context_, N));
 
   llvm::Value* result_value = irb_.CreateZExt(trunc_value, irb_.getJIntTy());
 
-  EmitStoreDalvikReg(dec_insn.vA_, kInt, kAccurate, result_value);
+  EmitStoreDalvikReg(dec_insn.vA, kInt, kAccurate, result_value);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -3092,13 +3090,13 @@
                                    Instruction const* insn,
                                    JType op_jty) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   DCHECK(op_jty == kFloat || op_jty == kDouble) << op_jty;
 
-  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB_, op_jty, kAccurate);
+  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB, op_jty, kAccurate);
   llvm::Value* result_value = irb_.CreateFNeg(src_value);
-  EmitStoreDalvikReg(dec_insn.vA_, op_jty, kAccurate, result_value);
+  EmitStoreDalvikReg(dec_insn.vA, op_jty, kAccurate, result_value);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -3109,15 +3107,15 @@
                                       JType src_jty,
                                       JType dest_jty) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   DCHECK(src_jty == kInt || src_jty == kLong) << src_jty;
   DCHECK(dest_jty == kFloat || dest_jty == kDouble) << dest_jty;
 
-  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB_, src_jty, kAccurate);
+  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB, src_jty, kAccurate);
   llvm::Type* dest_type = irb_.getJType(dest_jty, kAccurate);
   llvm::Value* dest_value = irb_.CreateSIToFP(src_value, dest_type);
-  EmitStoreDalvikReg(dec_insn.vA_, dest_jty, kAccurate, dest_value);
+  EmitStoreDalvikReg(dec_insn.vA, dest_jty, kAccurate, dest_value);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -3128,15 +3126,15 @@
                                       JType src_jty,
                                       JType dest_jty) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   DCHECK(src_jty == kFloat || src_jty == kDouble) << src_jty;
   DCHECK(dest_jty == kInt || dest_jty == kLong) << dest_jty;
 
-  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB_, src_jty, kAccurate);
+  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB, src_jty, kAccurate);
   llvm::Type* dest_type = irb_.getJType(dest_jty, kAccurate);
   llvm::Value* dest_value = irb_.CreateFPToSI(src_value, dest_type);
-  EmitStoreDalvikReg(dec_insn.vA_, dest_jty, kAccurate, dest_value);
+  EmitStoreDalvikReg(dec_insn.vA, dest_jty, kAccurate, dest_value);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -3145,11 +3143,11 @@
 void MethodCompiler::EmitInsn_FExt(uint32_t dex_pc,
                                    Instruction const* insn) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB_, kFloat, kAccurate);
+  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB, kFloat, kAccurate);
   llvm::Value* result_value = irb_.CreateFPExt(src_value, irb_.getJDoubleTy());
-  EmitStoreDalvikReg(dec_insn.vA_, kDouble, kAccurate, result_value);
+  EmitStoreDalvikReg(dec_insn.vA, kDouble, kAccurate, result_value);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -3158,11 +3156,11 @@
 void MethodCompiler::EmitInsn_FTrunc(uint32_t dex_pc,
                                      Instruction const* insn) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB_, kDouble, kAccurate);
+  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB, kDouble, kAccurate);
   llvm::Value* result_value = irb_.CreateFPTrunc(src_value, irb_.getJFloatTy());
-  EmitStoreDalvikReg(dec_insn.vA_, kFloat, kAccurate, result_value);
+  EmitStoreDalvikReg(dec_insn.vA, kFloat, kAccurate, result_value);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -3174,7 +3172,7 @@
                                         JType op_jty,
                                         bool is_2addr) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   DCHECK(op_jty == kInt || op_jty == kLong) << op_jty;
 
@@ -3182,18 +3180,18 @@
   llvm::Value* src2_value;
 
   if (is_2addr) {
-    src1_value = EmitLoadDalvikReg(dec_insn.vA_, op_jty, kAccurate);
-    src2_value = EmitLoadDalvikReg(dec_insn.vB_, op_jty, kAccurate);
+    src1_value = EmitLoadDalvikReg(dec_insn.vA, op_jty, kAccurate);
+    src2_value = EmitLoadDalvikReg(dec_insn.vB, op_jty, kAccurate);
   } else {
-    src1_value = EmitLoadDalvikReg(dec_insn.vB_, op_jty, kAccurate);
-    src2_value = EmitLoadDalvikReg(dec_insn.vC_, op_jty, kAccurate);
+    src1_value = EmitLoadDalvikReg(dec_insn.vB, op_jty, kAccurate);
+    src2_value = EmitLoadDalvikReg(dec_insn.vC, op_jty, kAccurate);
   }
 
   llvm::Value* result_value =
     EmitIntArithmResultComputation(dex_pc, src1_value, src2_value,
                                    arithm, op_jty);
 
-  EmitStoreDalvikReg(dec_insn.vA_, op_jty, kAccurate, result_value);
+  EmitStoreDalvikReg(dec_insn.vA, op_jty, kAccurate, result_value);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -3203,16 +3201,16 @@
                                                  Instruction const* insn,
                                                  IntArithmKind arithm) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB_, kInt, kAccurate);
+  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB, kInt, kAccurate);
 
-  llvm::Value* imm_value = irb_.getInt32(dec_insn.vC_);
+  llvm::Value* imm_value = irb_.getInt32(dec_insn.vC);
 
   llvm::Value* result_value =
     EmitIntArithmResultComputation(dex_pc, src_value, imm_value, arithm, kInt);
 
-  EmitStoreDalvikReg(dec_insn.vA_, kInt, kAccurate, result_value);
+  EmitStoreDalvikReg(dec_insn.vA, kInt, kAccurate, result_value);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -3284,12 +3282,12 @@
 void MethodCompiler::EmitInsn_RSubImmediate(uint32_t dex_pc,
                                             Instruction const* insn) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
-  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB_, kInt, kAccurate);
-  llvm::Value* imm_value = irb_.getInt32(dec_insn.vC_);
+  llvm::Value* src_value = EmitLoadDalvikReg(dec_insn.vB, kInt, kAccurate);
+  llvm::Value* imm_value = irb_.getInt32(dec_insn.vC);
   llvm::Value* result_value = irb_.CreateSub(imm_value, src_value);
-  EmitStoreDalvikReg(dec_insn.vA_, kInt, kAccurate, result_value);
+  EmitStoreDalvikReg(dec_insn.vA, kInt, kAccurate, result_value);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
@@ -3301,7 +3299,7 @@
                                        JType op_jty,
                                        bool is_2addr) {
 
-  Instruction::DecodedInstruction dec_insn(insn);
+  DecodedInstruction dec_insn(insn);
 
   DCHECK(op_jty == kFloat || op_jty == kDouble) << op_jty;
 
@@ -3309,17 +3307,17 @@
   llvm::Value* src2_value;
 
   if (is_2addr) {
-    src1_value = EmitLoadDalvikReg(dec_insn.vA_, op_jty, kAccurate);
-    src2_value = EmitLoadDalvikReg(dec_insn.vB_, op_jty, kAccurate);
+    src1_value = EmitLoadDalvikReg(dec_insn.vA, op_jty, kAccurate);
+    src2_value = EmitLoadDalvikReg(dec_insn.vB, op_jty, kAccurate);
   } else {
-    src1_value = EmitLoadDalvikReg(dec_insn.vB_, op_jty, kAccurate);
-    src2_value = EmitLoadDalvikReg(dec_insn.vC_, op_jty, kAccurate);
+    src1_value = EmitLoadDalvikReg(dec_insn.vB, op_jty, kAccurate);
+    src2_value = EmitLoadDalvikReg(dec_insn.vC, op_jty, kAccurate);
   }
 
   llvm::Value* result_value =
     EmitFPArithmResultComputation(dex_pc, src1_value, src2_value, arithm);
 
-  EmitStoreDalvikReg(dec_insn.vA_, op_jty, kAccurate, result_value);
+  EmitStoreDalvikReg(dec_insn.vA, op_jty, kAccurate, result_value);
 
   irb_.CreateBr(GetNextBasicBlock(dex_pc));
 }
diff --git a/src/compiler_llvm/method_compiler.h b/src/compiler_llvm/method_compiler.h
index ea5534c..c9e03a4 100644
--- a/src/compiler_llvm/method_compiler.h
+++ b/src/compiler_llvm/method_compiler.h
@@ -302,12 +302,11 @@
 
   llvm::Value* EmitLoadStaticStorage(uint32_t dex_pc, uint32_t type_idx);
 
-  llvm::Value* EmitLoadCalleeThis(Instruction::DecodedInstruction const& di,
-                                  bool is_range);
+  llvm::Value* EmitLoadCalleeThis(DecodedInstruction const& di, bool is_range);
 
   void EmitLoadActualParameters(std::vector<llvm::Value*>& args,
                                 uint32_t callee_method_idx,
-                                Instruction::DecodedInstruction const& di,
+                                DecodedInstruction const& di,
                                 bool is_range,
                                 bool is_static);
 
diff --git a/src/dex_instruction.cc b/src/dex_instruction.cc
index 31e9d3a..4073938 100644
--- a/src/dex_instruction.cc
+++ b/src/dex_instruction.cc
@@ -29,7 +29,7 @@
 #undef INSTRUCTION_NAME
 };
 
-Instruction::InstructionFormat const Instruction::kInstructionFormats[] = {
+Instruction::Format const Instruction::kInstructionFormats[] = {
 #define INSTRUCTION_FORMAT(o, c, p, format, r, i, a, v) format,
 #include "dex_instruction_list.h"
   DEX_INSTRUCTION_LIST(INSTRUCTION_FORMAT)
@@ -72,7 +72,7 @@
   uint16_t insn = *insns;
   int opcode = insn & 0xFF;
 
-  switch (Format()) {
+  switch (FormatOf(Opcode())) {
     case k10x:       // op
       /* nothing to do; copy the AA bits out for the verifier */
       vA = INST_AA(insn);
@@ -203,16 +203,16 @@
       vB_wide = FETCH_u4(1) | ((uint64_t) FETCH_u4(3) << 32);
       break;
     default:
-      LOG(ERROR) << "Can't decode unexpected format " << static_cast<int>(Format()) << " (op=" << opcode << ")";
+      LOG(ERROR) << "Can't decode unexpected format " << static_cast<int>(FormatOf(Opcode())) << " (op=" << opcode << ")";
       return;
   }
 }
 
 size_t Instruction::SizeInCodeUnits() const {
   const uint16_t* insns = reinterpret_cast<const uint16_t*>(this);
-  if (*insns == kPackedSwitchSignature) {
+  if (*insns == Instruction::kPackedSwitchSignature) {
     return (4 + insns[1] * 2);
-  } else if (*insns == kSparseSwitchSignature) {
+  } else if (*insns == Instruction::kSparseSwitchSignature) {
     return (2 + insns[1] * 4);
   } else if (*insns == kArrayDataSignature) {
     uint16_t element_size = insns[1];
@@ -220,7 +220,7 @@
     // The plus 1 is to round up for odd size and width.
     return (4 + (element_size * length + 1) / 2);
   } else {
-    switch (Format()) {
+    switch (FormatOf(Opcode())) {
       case k10x:
       case k12x:
       case k11n:
@@ -288,64 +288,69 @@
 std::string Instruction::DumpString(const DexFile* file) const {
   DecodedInstruction insn(this);
   std::ostringstream os;
-  const char* opcode = kInstructionNames[insn.opcode_];
-  switch (Format()) {
+  const char* opcode = kInstructionNames[insn.opcode];
+  switch (FormatOf(Opcode())) {
     case k10x:  os << opcode; break;
-    case k12x:  os << StringPrintf("%s v%d, v%d", opcode, insn.vA_, insn.vB_); break;
-    case k11n:  os << StringPrintf("%s v%d, #%+d", opcode, insn.vA_, insn.vB_); break;
-    case k11x:  os << StringPrintf("%s v%d", opcode, insn.vA_); break;
-    case k10t:  os << StringPrintf("%s %+d", opcode, insn.vA_); break;
-    case k20bc: os << StringPrintf("%s %d, kind@%d", opcode, insn.vA_, insn.vB_); break;
-    case k20t:  os << StringPrintf("%s %+d", opcode, insn.vA_); break;
-    case k22x:  os << StringPrintf("%s v%d, v%d", opcode, insn.vA_, insn.vB_); break;
-    case k21t:  os << StringPrintf("%s v%d, %+d", opcode, insn.vA_, insn.vB_); break;
-    case k21s:  os << StringPrintf("%s v%d, #%+d", opcode, insn.vA_, insn.vB_); break;
-    case k21h:  os << StringPrintf("%s v%d, #%+d00000[00000000]", opcode, insn.vA_, insn.vB_); break;
-    case k21c:  os << StringPrintf("%s v%d, thing@%d", opcode, insn.vA_, insn.vB_); break;
-    case k23x:  os << StringPrintf("%s v%d, v%d, v%d", opcode, insn.vA_, insn.vB_, insn.vC_); break;
-    case k22b:  os << StringPrintf("%s v%d, v%d, #%+d", opcode, insn.vA_, insn.vB_, insn.vC_); break;
-    case k22t:  os << StringPrintf("%s v%d, v%d, %+d", opcode, insn.vA_, insn.vB_, insn.vC_); break;
-    case k22s:  os << StringPrintf("%s v%d, v%d, #%+d", opcode, insn.vA_, insn.vB_, insn.vC_); break;
-    case k22c:  os << StringPrintf("%s v%d, v%d, thing@%d", opcode, insn.vA_, insn.vB_, insn.vC_); break;
-    case k32x:  os << StringPrintf("%s v%d, v%d", opcode, insn.vA_, insn.vB_); break;
-    case k30t:  os << StringPrintf("%s %+d", opcode, insn.vA_); break;
-    case k31t:  os << StringPrintf("%s v%d, %+d", opcode, insn.vA_, insn.vB_); break;
-    case k31i:  os << StringPrintf("%s v%d, #%+d", opcode, insn.vA_, insn.vB_); break;
-    case k31c:  os << StringPrintf("%s v%d, thing@%d", opcode, insn.vA_, insn.vB_); break;
+    case k12x:  os << StringPrintf("%s v%d, v%d", opcode, insn.vA, insn.vB); break;
+    case k11n:  os << StringPrintf("%s v%d, #%+d", opcode, insn.vA, insn.vB); break;
+    case k11x:  os << StringPrintf("%s v%d", opcode, insn.vA); break;
+    case k10t:  os << StringPrintf("%s %+d", opcode, insn.vA); break;
+    case k20bc: os << StringPrintf("%s %d, kind@%d", opcode, insn.vA, insn.vB); break;
+    case k20t:  os << StringPrintf("%s %+d", opcode, insn.vA); break;
+    case k22x:  os << StringPrintf("%s v%d, v%d", opcode, insn.vA, insn.vB); break;
+    case k21t:  os << StringPrintf("%s v%d, %+d", opcode, insn.vA, insn.vB); break;
+    case k21s:  os << StringPrintf("%s v%d, #%+d", opcode, insn.vA, insn.vB); break;
+    case k21h:  os << StringPrintf("%s v%d, #%+d00000[00000000]", opcode, insn.vA, insn.vB); break;
+    case k21c:  os << StringPrintf("%s v%d, thing@%d", opcode, insn.vA, insn.vB); break;
+    case k23x:  os << StringPrintf("%s v%d, v%d, v%d", opcode, insn.vA, insn.vB, insn.vC); break;
+    case k22b:  os << StringPrintf("%s v%d, v%d, #%+d", opcode, insn.vA, insn.vB, insn.vC); break;
+    case k22t:  os << StringPrintf("%s v%d, v%d, %+d", opcode, insn.vA, insn.vB, insn.vC); break;
+    case k22s:  os << StringPrintf("%s v%d, v%d, #%+d", opcode, insn.vA, insn.vB, insn.vC); break;
+    case k22c:  os << StringPrintf("%s v%d, v%d, thing@%d", opcode, insn.vA, insn.vB, insn.vC); break;
+    case k32x:  os << StringPrintf("%s v%d, v%d", opcode, insn.vA, insn.vB); break;
+    case k30t:  os << StringPrintf("%s %+d", opcode, insn.vA); break;
+    case k31t:  os << StringPrintf("%s v%d, %+d", opcode, insn.vA, insn.vB); break;
+    case k31i:  os << StringPrintf("%s v%d, #%+d", opcode, insn.vA, insn.vB); break;
+    case k31c:  os << StringPrintf("%s v%d, thing@%d", opcode, insn.vA, insn.vB); break;
     case k35c: {
-      switch (insn.opcode_) {
+      switch (insn.opcode) {
         case INVOKE_VIRTUAL:
         case INVOKE_SUPER:
         case INVOKE_DIRECT:
         case INVOKE_STATIC:
         case INVOKE_INTERFACE:
           if (file != NULL) {
-            const DexFile::MethodId& meth_id = file->GetMethodId(insn.vB_);
+            const DexFile::MethodId& meth_id = file->GetMethodId(insn.vB);
             os << opcode << " {";
-            for (size_t i = 0; i < insn.vA_; ++i) {
+            for (size_t i = 0; i < insn.vA; ++i) {
               if (i != 0) {
                 os << ", ";
               }
-              os << "v" << insn.arg_[i];
+              os << "v" << insn.arg[i];
             }
             os << "}, "
                << file->GetMethodDeclaringClassDescriptor(meth_id) << "."
                << file->GetMethodName(meth_id) << file->GetMethodSignature(meth_id)
-               << " // method@" << insn.vB_;
+               << " // method@" << insn.vB;
             break;
           }  // else fall-through
         default:
-          os << opcode << " {v" << insn.arg_[0] << ", v" << insn.arg_[1] << ", v" << insn.arg_[2]
-                       << ", v" << insn.arg_[3] << ", v" << insn.arg_[4] << "}, thing@" << insn.vB_;
+          os << opcode << " {v" << insn.arg[0] << ", v" << insn.arg[1] << ", v" << insn.arg[2]
+                       << ", v" << insn.arg[3] << ", v" << insn.arg[4] << "}, thing@" << insn.vB;
           break;
       }
       break;
     }
-    case k3rc: os << StringPrintf("%s, {v%d .. v%d}, method@%d", opcode, insn.vC_, (insn.vC_+ insn.vA_ - 1), insn.vB_); break;
-    case k51l: os << StringPrintf("%s v%d, #%+d", opcode, insn.vA_, insn.vB_); break;
+    case k3rc: os << StringPrintf("%s, {v%d .. v%d}, method@%d", opcode, insn.vC, (insn.vC + insn.vA - 1), insn.vB); break;
+    case k51l: os << StringPrintf("%s v%d, #%+d", opcode, insn.vA, insn.vB); break;
     default: os << " unknown format (" << DumpHex(5) << ")"; break;
   }
   return os.str();
 }
 
+DecodedInstruction::DecodedInstruction(const Instruction* inst) {
+  inst->Decode(vA, vB, vB_wide, vC, arg);
+  opcode = inst->Opcode();
+}
+
 }  // namespace art
diff --git a/src/dex_instruction.h b/src/dex_instruction.h
index 975ec86..278a61d 100644
--- a/src/dex_instruction.h
+++ b/src/dex_instruction.h
@@ -25,13 +25,17 @@
 
 class DexFile;
 
+enum {
+  kNumPackedOpcodes = 0x100
+};
+
 class Instruction {
  public:
   // NOP-encoded switch-statement signatures.
   enum {
     kPackedSwitchSignature = 0x0100,
     kSparseSwitchSignature = 0x0200,
-    kArrayDataSignature = 0x0300
+    kArrayDataSignature = 0x0300,
   };
 
   enum Code {
@@ -42,7 +46,7 @@
 #undef INSTRUCTION_ENUM
   };
 
-  enum InstructionFormat {
+  enum Format {
     k10x,  // op
     k12x,  // op vA, vB
     k11n,  // op vA, #+B
@@ -104,35 +108,23 @@
     kVerifyError           = 0x80000,
   };
 
-  /*
-   * Holds the contents of a decoded instruction.
-   */
-  struct DecodedInstruction {
-    uint32_t vA_;
-    uint32_t vB_;
-    uint64_t vB_wide_;        /* for kFmt51l */
-    uint32_t vC_;
-    uint32_t arg_[5];         /* vC/D/E/F/G in invoke or filled-new-array */
-    Code     opcode_;
-
-    explicit DecodedInstruction(const Instruction* inst) {
-      inst->Decode(vA_, vB_, vB_wide_, vC_, arg_);
-      opcode_ = inst->Opcode();
-    }
-  };
-
   // Decodes this instruction, populating its arguments.
   void Decode(uint32_t &vA, uint32_t &vB, uint64_t &vB_wide, uint32_t &vC, uint32_t arg[]) const;
 
-  // Returns the size in 2 byte code units, for this instruction.
+  // Returns the size (in 2 byte code units) of this instruction.
   size_t SizeInCodeUnits() const;
 
   // Returns a pointer to the next instruction in the stream.
   const Instruction* Next() const;
 
-  // Name of the instruction.
+  // Returns the name of this instruction's opcode.
   const char* Name() const {
-    return kInstructionNames[Opcode()];
+    return Instruction::Name(Opcode());
+  }
+
+  // Returns the name of the given opcode.
+  static const char* Name(Code opcode) {
+    return kInstructionNames[opcode];
   }
 
   // Returns the opcode field of the instruction.
@@ -144,14 +136,14 @@
     return reinterpret_cast<const Instruction*>(code);
   }
 
-  // Returns the format of the current instruction.
-  InstructionFormat Format() const {
-    return kInstructionFormats[Opcode()];
+  // Returns the format of the given opcode.
+  static Format FormatOf(Code opcode) {
+    return kInstructionFormats[opcode];
   }
 
-  // Returns the flags for the current instruction.
-  int Flag() const {
-    return kInstructionFlags[Opcode()];
+  // Returns the flags for the given opcode.
+  static int Flags(Code opcode) {
+    return kInstructionFlags[opcode];
   }
 
   // Returns true if this instruction is a branch.
@@ -211,12 +203,25 @@
 
  private:
   static const char* const kInstructionNames[];
-  static InstructionFormat const kInstructionFormats[];
+  static Format const kInstructionFormats[];
   static int const kInstructionFlags[];
   static int const kInstructionVerifyFlags[];
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction);
 };
-std::ostream& operator<<(std::ostream& os, const Instruction& rhs);
+
+/*
+ * Holds the contents of a decoded instruction.
+ */
+struct DecodedInstruction {
+  uint32_t vA;
+  uint32_t vB;
+  uint64_t vB_wide;        /* for k51l */
+  uint32_t vC;
+  uint32_t arg[5];         /* vC/D/E/F/G in invoke or filled-new-array */
+  Instruction::Code opcode;
+
+  explicit DecodedInstruction(const Instruction* inst);
+};
 
 }  // namespace art
 
diff --git a/src/dex_verifier.cc b/src/dex_verifier.cc
index 064aa44..5b8102a 100644
--- a/src/dex_verifier.cc
+++ b/src/dex_verifier.cc
@@ -623,16 +623,16 @@
   return verifier_->GetRegTypeCache()->GetFromId(line_[vsrc]);
 }
 
-const RegType& RegisterLine::GetInvocationThis(const Instruction::DecodedInstruction& dec_insn) {
-  if (dec_insn.vA_ < 1) {
+const RegType& RegisterLine::GetInvocationThis(const DecodedInstruction& dec_insn) {
+  if (dec_insn.vA < 1) {
     verifier_->Fail(VERIFY_ERROR_GENERIC) << "invoke lacks 'this'";
     return verifier_->GetRegTypeCache()->Unknown();
   }
   /* get the element type of the array held in vsrc */
-  const RegType& this_type = GetRegisterType(dec_insn.vC_);
+  const RegType& this_type = GetRegisterType(dec_insn.vC);
   if (!this_type.IsReferenceTypes()) {
     verifier_->Fail(VERIFY_ERROR_GENERIC) << "tried to get class from non-reference register v"
-                                          << dec_insn.vC_ << " (type=" << this_type << ")";
+                                          << dec_insn.vC << " (type=" << this_type << ")";
     return verifier_->GetRegTypeCache()->Unknown();
   }
   return this_type;
@@ -741,62 +741,62 @@
   }
 }
 
-void RegisterLine::CheckUnaryOp(const Instruction::DecodedInstruction& dec_insn,
+void RegisterLine::CheckUnaryOp(const DecodedInstruction& dec_insn,
                                 const RegType& dst_type, const RegType& src_type) {
-  if (VerifyRegisterType(dec_insn.vB_, src_type)) {
-    SetRegisterType(dec_insn.vA_, dst_type);
+  if (VerifyRegisterType(dec_insn.vB, src_type)) {
+    SetRegisterType(dec_insn.vA, dst_type);
   }
 }
 
-void RegisterLine::CheckBinaryOp(const Instruction::DecodedInstruction& dec_insn,
+void RegisterLine::CheckBinaryOp(const DecodedInstruction& dec_insn,
                                  const RegType& dst_type,
                                  const RegType& src_type1, const RegType& src_type2,
                                  bool check_boolean_op) {
-  if (VerifyRegisterType(dec_insn.vB_, src_type1) &&
-      VerifyRegisterType(dec_insn.vC_, src_type2)) {
+  if (VerifyRegisterType(dec_insn.vB, src_type1) &&
+      VerifyRegisterType(dec_insn.vC, src_type2)) {
     if (check_boolean_op) {
       DCHECK(dst_type.IsInteger());
-      if (GetRegisterType(dec_insn.vB_).IsBooleanTypes() &&
-          GetRegisterType(dec_insn.vC_).IsBooleanTypes()) {
-        SetRegisterType(dec_insn.vA_, verifier_->GetRegTypeCache()->Boolean());
+      if (GetRegisterType(dec_insn.vB).IsBooleanTypes() &&
+          GetRegisterType(dec_insn.vC).IsBooleanTypes()) {
+        SetRegisterType(dec_insn.vA, verifier_->GetRegTypeCache()->Boolean());
         return;
       }
     }
-    SetRegisterType(dec_insn.vA_, dst_type);
+    SetRegisterType(dec_insn.vA, dst_type);
   }
 }
 
-void RegisterLine::CheckBinaryOp2addr(const Instruction::DecodedInstruction& dec_insn,
+void RegisterLine::CheckBinaryOp2addr(const DecodedInstruction& dec_insn,
                                       const RegType& dst_type, const RegType& src_type1,
                                       const RegType& src_type2, bool check_boolean_op) {
-  if (VerifyRegisterType(dec_insn.vA_, src_type1) &&
-      VerifyRegisterType(dec_insn.vB_, src_type2)) {
+  if (VerifyRegisterType(dec_insn.vA, src_type1) &&
+      VerifyRegisterType(dec_insn.vB, src_type2)) {
     if (check_boolean_op) {
       DCHECK(dst_type.IsInteger());
-      if (GetRegisterType(dec_insn.vA_).IsBooleanTypes() &&
-          GetRegisterType(dec_insn.vB_).IsBooleanTypes()) {
-        SetRegisterType(dec_insn.vA_, verifier_->GetRegTypeCache()->Boolean());
+      if (GetRegisterType(dec_insn.vA).IsBooleanTypes() &&
+          GetRegisterType(dec_insn.vB).IsBooleanTypes()) {
+        SetRegisterType(dec_insn.vA, verifier_->GetRegTypeCache()->Boolean());
         return;
       }
     }
-    SetRegisterType(dec_insn.vA_, dst_type);
+    SetRegisterType(dec_insn.vA, dst_type);
   }
 }
 
-void RegisterLine::CheckLiteralOp(const Instruction::DecodedInstruction& dec_insn,
+void RegisterLine::CheckLiteralOp(const DecodedInstruction& dec_insn,
                                   const RegType& dst_type, const RegType& src_type,
                                   bool check_boolean_op) {
-  if (VerifyRegisterType(dec_insn.vB_, src_type)) {
+  if (VerifyRegisterType(dec_insn.vB, src_type)) {
     if (check_boolean_op) {
       DCHECK(dst_type.IsInteger());
       /* check vB with the call, then check the constant manually */
-      if (GetRegisterType(dec_insn.vB_).IsBooleanTypes() &&
-          (dec_insn.vC_ == 0 || dec_insn.vC_ == 1)) {
-        SetRegisterType(dec_insn.vA_, verifier_->GetRegTypeCache()->Boolean());
+      if (GetRegisterType(dec_insn.vB).IsBooleanTypes() &&
+          (dec_insn.vC == 0 || dec_insn.vC == 1)) {
+        SetRegisterType(dec_insn.vA, verifier_->GetRegTypeCache()->Boolean());
         return;
       }
     }
-    SetRegisterType(dec_insn.vA_, dst_type);
+    SetRegisterType(dec_insn.vA, dst_type);
   }
 }
 
@@ -1275,54 +1275,54 @@
 }
 
 bool DexVerifier::VerifyInstruction(const Instruction* inst, uint32_t code_offset) {
-  Instruction::DecodedInstruction dec_insn(inst);
+  DecodedInstruction dec_insn(inst);
   bool result = true;
   switch (inst->GetVerifyTypeArgumentA()) {
     case Instruction::kVerifyRegA:
-      result = result && CheckRegisterIndex(dec_insn.vA_);
+      result = result && CheckRegisterIndex(dec_insn.vA);
       break;
     case Instruction::kVerifyRegAWide:
-      result = result && CheckWideRegisterIndex(dec_insn.vA_);
+      result = result && CheckWideRegisterIndex(dec_insn.vA);
       break;
   }
   switch (inst->GetVerifyTypeArgumentB()) {
     case Instruction::kVerifyRegB:
-      result = result && CheckRegisterIndex(dec_insn.vB_);
+      result = result && CheckRegisterIndex(dec_insn.vB);
       break;
     case Instruction::kVerifyRegBField:
-      result = result && CheckFieldIndex(dec_insn.vB_);
+      result = result && CheckFieldIndex(dec_insn.vB);
       break;
     case Instruction::kVerifyRegBMethod:
-      result = result && CheckMethodIndex(dec_insn.vB_);
+      result = result && CheckMethodIndex(dec_insn.vB);
       break;
     case Instruction::kVerifyRegBNewInstance:
-      result = result && CheckNewInstance(dec_insn.vB_);
+      result = result && CheckNewInstance(dec_insn.vB);
       break;
     case Instruction::kVerifyRegBString:
-      result = result && CheckStringIndex(dec_insn.vB_);
+      result = result && CheckStringIndex(dec_insn.vB);
       break;
     case Instruction::kVerifyRegBType:
-      result = result && CheckTypeIndex(dec_insn.vB_);
+      result = result && CheckTypeIndex(dec_insn.vB);
       break;
     case Instruction::kVerifyRegBWide:
-      result = result && CheckWideRegisterIndex(dec_insn.vB_);
+      result = result && CheckWideRegisterIndex(dec_insn.vB);
       break;
   }
   switch (inst->GetVerifyTypeArgumentC()) {
     case Instruction::kVerifyRegC:
-      result = result && CheckRegisterIndex(dec_insn.vC_);
+      result = result && CheckRegisterIndex(dec_insn.vC);
       break;
     case Instruction::kVerifyRegCField:
-      result = result && CheckFieldIndex(dec_insn.vC_);
+      result = result && CheckFieldIndex(dec_insn.vC);
       break;
     case Instruction::kVerifyRegCNewArray:
-      result = result && CheckNewArray(dec_insn.vC_);
+      result = result && CheckNewArray(dec_insn.vC);
       break;
     case Instruction::kVerifyRegCType:
-      result = result && CheckTypeIndex(dec_insn.vC_);
+      result = result && CheckTypeIndex(dec_insn.vC);
       break;
     case Instruction::kVerifyRegCWide:
-      result = result && CheckWideRegisterIndex(dec_insn.vC_);
+      result = result && CheckWideRegisterIndex(dec_insn.vC);
       break;
   }
   switch (inst->GetVerifyExtraFlags()) {
@@ -1336,10 +1336,10 @@
       result = result && CheckSwitchTargets(code_offset);
       break;
     case Instruction::kVerifyVarArg:
-      result = result && CheckVarArgRegs(dec_insn.vA_, dec_insn.arg_);
+      result = result && CheckVarArgRegs(dec_insn.vA, dec_insn.arg);
       break;
     case Instruction::kVerifyVarArgRange:
-      result = result && CheckVarArgRangeRegs(dec_insn.vA_, dec_insn.vC_);
+      result = result && CheckVarArgRangeRegs(dec_insn.vA, dec_insn.vC);
       break;
     case Instruction::kVerifyError:
       Fail(VERIFY_ERROR_GENERIC) << "unexpected opcode " << inst->Name();
@@ -2003,12 +2003,12 @@
    * We can also return, in which case there is no successor instruction
    * from this point.
    *
-   * The behavior can be determined from the OpcodeFlags.
+   * The behavior can be determined from the opcode flags.
    */
   const uint16_t* insns = code_item_->insns_ + work_insn_idx_;
   const Instruction* inst = Instruction::At(insns);
-  Instruction::DecodedInstruction dec_insn(inst);
-  int opcode_flag = inst->Flag();
+  DecodedInstruction dec_insn(inst);
+  int opcode_flags = Instruction::Flags(inst->Opcode());
 
   int32_t branch_target = 0;
   bool just_set_result = false;
@@ -2025,7 +2025,7 @@
    * from the "successful" code path (e.g. a check-cast that "improves"
    * a type) to be visible to the exception handler.
    */
-  if ((opcode_flag & Instruction::kThrow) != 0 && CurrentInsnFlags().IsInTry()) {
+  if ((opcode_flags & Instruction::kThrow) != 0 && CurrentInsnFlags().IsInTry()) {
     saved_line_->CopyFromLine(work_line_.get());
   } else {
 #ifndef NDEBUG
@@ -2033,14 +2033,14 @@
 #endif
   }
 
-  switch (dec_insn.opcode_) {
+  switch (dec_insn.opcode) {
     case Instruction::NOP:
       /*
        * A "pure" NOP has no effect on anything. Data tables start with
        * a signature that looks like a NOP; if we see one of these in
        * the course of executing code then we have a problem.
        */
-      if (dec_insn.vA_ != 0) {
+      if (dec_insn.vA != 0) {
         Fail(VERIFY_ERROR_GENERIC) << "encountered data table in instruction stream";
       }
       break;
@@ -2048,17 +2048,17 @@
     case Instruction::MOVE:
     case Instruction::MOVE_FROM16:
     case Instruction::MOVE_16:
-      work_line_->CopyRegister1(dec_insn.vA_, dec_insn.vB_, kTypeCategory1nr);
+      work_line_->CopyRegister1(dec_insn.vA, dec_insn.vB, kTypeCategory1nr);
       break;
     case Instruction::MOVE_WIDE:
     case Instruction::MOVE_WIDE_FROM16:
     case Instruction::MOVE_WIDE_16:
-      work_line_->CopyRegister2(dec_insn.vA_, dec_insn.vB_);
+      work_line_->CopyRegister2(dec_insn.vA, dec_insn.vB);
       break;
     case Instruction::MOVE_OBJECT:
     case Instruction::MOVE_OBJECT_FROM16:
     case Instruction::MOVE_OBJECT_16:
-      work_line_->CopyRegister1(dec_insn.vA_, dec_insn.vB_, kTypeCategoryRef);
+      work_line_->CopyRegister1(dec_insn.vA, dec_insn.vB, kTypeCategoryRef);
       break;
 
     /*
@@ -2073,13 +2073,13 @@
      * easier to read in some cases.)
      */
     case Instruction::MOVE_RESULT:
-      work_line_->CopyResultRegister1(dec_insn.vA_, false);
+      work_line_->CopyResultRegister1(dec_insn.vA, false);
       break;
     case Instruction::MOVE_RESULT_WIDE:
-      work_line_->CopyResultRegister2(dec_insn.vA_);
+      work_line_->CopyResultRegister2(dec_insn.vA);
       break;
     case Instruction::MOVE_RESULT_OBJECT:
-      work_line_->CopyResultRegister1(dec_insn.vA_, true);
+      work_line_->CopyResultRegister1(dec_insn.vA, true);
       break;
 
     case Instruction::MOVE_EXCEPTION: {
@@ -2088,7 +2088,7 @@
        * that as part of extracting the exception type from the catch block list.
        */
       const RegType& res_type = GetCaughtExceptionType();
-      work_line_->SetRegisterType(dec_insn.vA_, res_type);
+      work_line_->SetRegisterType(dec_insn.vA, res_type);
       break;
     }
     case Instruction::RETURN_VOID:
@@ -2107,15 +2107,15 @@
         } else {
           // Compilers may generate synthetic functions that write byte values into boolean fields.
           // Also, it may use integer values for boolean, byte, short, and character return types.
-          const RegType& src_type = work_line_->GetRegisterType(dec_insn.vA_);
+          const RegType& src_type = work_line_->GetRegisterType(dec_insn.vA);
           bool use_src = ((return_type.IsBoolean() && src_type.IsByte()) ||
                           ((return_type.IsBoolean() || return_type.IsByte() ||
                            return_type.IsShort() || return_type.IsChar()) &&
                            src_type.IsInteger()));
           /* check the register contents */
-          work_line_->VerifyRegisterType(dec_insn.vA_, use_src ? src_type : return_type);
+          work_line_->VerifyRegisterType(dec_insn.vA, use_src ? src_type : return_type);
           if (failure_ != VERIFY_ERROR_NONE) {
-            fail_messages_ << " return-1nr on invalid register v" << dec_insn.vA_;
+            fail_messages_ << " return-1nr on invalid register v" << dec_insn.vA;
           }
         }
       }
@@ -2128,9 +2128,9 @@
           Fail(VERIFY_ERROR_GENERIC) << "return-wide not expected";
         } else {
           /* check the register contents */
-          work_line_->VerifyRegisterType(dec_insn.vA_, return_type);
+          work_line_->VerifyRegisterType(dec_insn.vA, return_type);
           if (failure_ != VERIFY_ERROR_NONE) {
-            fail_messages_ << " return-wide on invalid register pair v" << dec_insn.vA_;
+            fail_messages_ << " return-wide on invalid register pair v" << dec_insn.vA;
           }
         }
       }
@@ -2144,7 +2144,7 @@
           /* return_type is the *expected* return type, not register value */
           DCHECK(!return_type.IsZero());
           DCHECK(!return_type.IsUninitializedReference());
-          const RegType& reg_type = work_line_->GetRegisterType(dec_insn.vA_);
+          const RegType& reg_type = work_line_->GetRegisterType(dec_insn.vA);
           // Disallow returning uninitialized values and verify that the reference in vAA is an
           // instance of the "return_type"
           if (reg_type.IsUninitializedTypes()) {
@@ -2161,35 +2161,35 @@
     case Instruction::CONST_16:
     case Instruction::CONST:
       /* could be boolean, int, float, or a null reference */
-      work_line_->SetRegisterType(dec_insn.vA_, reg_types_.FromCat1Const((int32_t) dec_insn.vB_));
+      work_line_->SetRegisterType(dec_insn.vA, reg_types_.FromCat1Const((int32_t) dec_insn.vB));
       break;
     case Instruction::CONST_HIGH16:
       /* could be boolean, int, float, or a null reference */
-      work_line_->SetRegisterType(dec_insn.vA_,
-                                  reg_types_.FromCat1Const((int32_t) dec_insn.vB_ << 16));
+      work_line_->SetRegisterType(dec_insn.vA,
+                                  reg_types_.FromCat1Const((int32_t) dec_insn.vB << 16));
       break;
     case Instruction::CONST_WIDE_16:
     case Instruction::CONST_WIDE_32:
     case Instruction::CONST_WIDE:
     case Instruction::CONST_WIDE_HIGH16:
       /* could be long or double; resolved upon use */
-      work_line_->SetRegisterType(dec_insn.vA_, reg_types_.ConstLo());
+      work_line_->SetRegisterType(dec_insn.vA, reg_types_.ConstLo());
       break;
     case Instruction::CONST_STRING:
     case Instruction::CONST_STRING_JUMBO:
-      work_line_->SetRegisterType(dec_insn.vA_, reg_types_.JavaLangString());
+      work_line_->SetRegisterType(dec_insn.vA, reg_types_.JavaLangString());
       break;
     case Instruction::CONST_CLASS: {
       // Get type from instruction if unresolved then we need an access check
       // TODO: check Compiler::CanAccessTypeWithoutChecks returns false when res_type is unresolved
-      const RegType& res_type = ResolveClassAndCheckAccess(dec_insn.vB_);
+      const RegType& res_type = ResolveClassAndCheckAccess(dec_insn.vB);
       // Register holds class, ie its type is class, but on error we keep it Unknown
-      work_line_->SetRegisterType(dec_insn.vA_,
+      work_line_->SetRegisterType(dec_insn.vA,
                                   res_type.IsUnknown() ? res_type : reg_types_.JavaLangClass());
       break;
     }
     case Instruction::MONITOR_ENTER:
-      work_line_->PushMonitor(dec_insn.vA_, work_insn_idx_);
+      work_line_->PushMonitor(dec_insn.vA, work_insn_idx_);
       break;
     case Instruction::MONITOR_EXIT:
       /*
@@ -2212,8 +2212,8 @@
        * we skip them here); if we can't, then the code path could be
        * "live" so we still need to check it.
        */
-      opcode_flag &= ~Instruction::kThrow;
-      work_line_->PopMonitor(dec_insn.vA_);
+      opcode_flags &= ~Instruction::kThrow;
+      work_line_->PopMonitor(dec_insn.vA);
       break;
 
     case Instruction::CHECK_CAST:
@@ -2223,44 +2223,44 @@
        * could be a "upcast" -- not expected, so we don't try to address it.)
        *
        * If it fails, an exception is thrown, which we deal with later by ignoring the update to
-       * dec_insn.vA_ when branching to a handler.
+       * dec_insn.vA when branching to a handler.
        */
-      bool is_checkcast = dec_insn.opcode_ == Instruction::CHECK_CAST;
+      bool is_checkcast = dec_insn.opcode == Instruction::CHECK_CAST;
       const RegType& res_type =
-          ResolveClassAndCheckAccess(is_checkcast ? dec_insn.vB_ : dec_insn.vC_);
+          ResolveClassAndCheckAccess(is_checkcast ? dec_insn.vB : dec_insn.vC);
       if (res_type.IsUnknown()) {
         CHECK_NE(failure_, VERIFY_ERROR_NONE);
         break;  // couldn't resolve class
       }
       // TODO: check Compiler::CanAccessTypeWithoutChecks returns false when res_type is unresolved
       const RegType& orig_type =
-          work_line_->GetRegisterType(is_checkcast ? dec_insn.vA_ : dec_insn.vB_);
+          work_line_->GetRegisterType(is_checkcast ? dec_insn.vA : dec_insn.vB);
       if (!res_type.IsNonZeroReferenceTypes()) {
         Fail(VERIFY_ERROR_GENERIC) << "check-cast on unexpected class " << res_type;
       } else if (!orig_type.IsReferenceTypes()) {
-        Fail(VERIFY_ERROR_GENERIC) << "check-cast on non-reference in v" << dec_insn.vA_;
+        Fail(VERIFY_ERROR_GENERIC) << "check-cast on non-reference in v" << dec_insn.vA;
       } else {
         if (is_checkcast) {
-          work_line_->SetRegisterType(dec_insn.vA_, res_type);
+          work_line_->SetRegisterType(dec_insn.vA, res_type);
         } else {
-          work_line_->SetRegisterType(dec_insn.vA_, reg_types_.Boolean());
+          work_line_->SetRegisterType(dec_insn.vA, reg_types_.Boolean());
         }
       }
       break;
     }
     case Instruction::ARRAY_LENGTH: {
-      const RegType& res_type = work_line_->GetRegisterType(dec_insn.vB_);
+      const RegType& res_type = work_line_->GetRegisterType(dec_insn.vB);
       if (res_type.IsReferenceTypes()) {
         if (!res_type.IsArrayTypes() && !res_type.IsZero()) {  // ie not an array or null
           Fail(VERIFY_ERROR_GENERIC) << "array-length on non-array " << res_type;
         } else {
-          work_line_->SetRegisterType(dec_insn.vA_, reg_types_.Integer());
+          work_line_->SetRegisterType(dec_insn.vA, reg_types_.Integer());
         }
       }
       break;
     }
     case Instruction::NEW_INSTANCE: {
-      const RegType& res_type = ResolveClassAndCheckAccess(dec_insn.vB_);
+      const RegType& res_type = ResolveClassAndCheckAccess(dec_insn.vB);
       if (res_type.IsUnknown()) {
         CHECK_NE(failure_, VERIFY_ERROR_NONE);
         break;  // couldn't resolve class
@@ -2276,7 +2276,7 @@
         // initialized must be marked invalid.
         work_line_->MarkUninitRefsAsInvalid(uninit_type);
         // add the new uninitialized reference to the register state
-        work_line_->SetRegisterType(dec_insn.vA_, uninit_type);
+        work_line_->SetRegisterType(dec_insn.vA, uninit_type);
       }
       break;
     }
@@ -2293,35 +2293,35 @@
       break;
     case Instruction::CMPL_FLOAT:
     case Instruction::CMPG_FLOAT:
-      if (!work_line_->VerifyRegisterType(dec_insn.vB_, reg_types_.Float())) {
+      if (!work_line_->VerifyRegisterType(dec_insn.vB, reg_types_.Float())) {
         break;
       }
-      if (!work_line_->VerifyRegisterType(dec_insn.vC_, reg_types_.Float())) {
+      if (!work_line_->VerifyRegisterType(dec_insn.vC, reg_types_.Float())) {
         break;
       }
-      work_line_->SetRegisterType(dec_insn.vA_, reg_types_.Integer());
+      work_line_->SetRegisterType(dec_insn.vA, reg_types_.Integer());
       break;
     case Instruction::CMPL_DOUBLE:
     case Instruction::CMPG_DOUBLE:
-      if (!work_line_->VerifyRegisterType(dec_insn.vB_, reg_types_.Double())) {
+      if (!work_line_->VerifyRegisterType(dec_insn.vB, reg_types_.Double())) {
         break;
       }
-      if (!work_line_->VerifyRegisterType(dec_insn.vC_, reg_types_.Double())) {
+      if (!work_line_->VerifyRegisterType(dec_insn.vC, reg_types_.Double())) {
         break;
       }
-      work_line_->SetRegisterType(dec_insn.vA_, reg_types_.Integer());
+      work_line_->SetRegisterType(dec_insn.vA, reg_types_.Integer());
       break;
     case Instruction::CMP_LONG:
-      if (!work_line_->VerifyRegisterType(dec_insn.vB_, reg_types_.Long())) {
+      if (!work_line_->VerifyRegisterType(dec_insn.vB, reg_types_.Long())) {
         break;
       }
-      if (!work_line_->VerifyRegisterType(dec_insn.vC_, reg_types_.Long())) {
+      if (!work_line_->VerifyRegisterType(dec_insn.vC, reg_types_.Long())) {
         break;
       }
-      work_line_->SetRegisterType(dec_insn.vA_, reg_types_.Integer());
+      work_line_->SetRegisterType(dec_insn.vA, reg_types_.Integer());
       break;
     case Instruction::THROW: {
-      const RegType& res_type = work_line_->GetRegisterType(dec_insn.vA_);
+      const RegType& res_type = work_line_->GetRegisterType(dec_insn.vA);
       if (!reg_types_.JavaLangThrowable().IsAssignableFrom(res_type)) {
         Fail(VERIFY_ERROR_GENERIC) << "thrown class " << res_type << " not instanceof Throwable";
       }
@@ -2336,12 +2336,12 @@
     case Instruction::PACKED_SWITCH:
     case Instruction::SPARSE_SWITCH:
       /* verify that vAA is an integer, or can be converted to one */
-      work_line_->VerifyRegisterType(dec_insn.vA_, reg_types_.Integer());
+      work_line_->VerifyRegisterType(dec_insn.vA, reg_types_.Integer());
       break;
 
     case Instruction::FILL_ARRAY_DATA: {
       /* Similar to the verification done for APUT */
-      const RegType& array_type = work_line_->GetRegisterType(dec_insn.vA_);
+      const RegType& array_type = work_line_->GetRegisterType(dec_insn.vA);
       /* array_type can be null if the reg type is Zero */
       if (!array_type.IsZero()) {
         if (!array_type.IsArrayTypes()) {
@@ -2375,8 +2375,8 @@
     }
     case Instruction::IF_EQ:
     case Instruction::IF_NE: {
-      const RegType& reg_type1 = work_line_->GetRegisterType(dec_insn.vA_);
-      const RegType& reg_type2 = work_line_->GetRegisterType(dec_insn.vB_);
+      const RegType& reg_type1 = work_line_->GetRegisterType(dec_insn.vA);
+      const RegType& reg_type2 = work_line_->GetRegisterType(dec_insn.vB);
       bool mismatch = false;
       if (reg_type1.IsZero()) {  // zero then integral or reference expected
         mismatch = !reg_type2.IsReferenceTypes() && !reg_type2.IsIntegralTypes();
@@ -2395,8 +2395,8 @@
     case Instruction::IF_GE:
     case Instruction::IF_GT:
     case Instruction::IF_LE: {
-      const RegType& reg_type1 = work_line_->GetRegisterType(dec_insn.vA_);
-      const RegType& reg_type2 = work_line_->GetRegisterType(dec_insn.vB_);
+      const RegType& reg_type1 = work_line_->GetRegisterType(dec_insn.vA);
+      const RegType& reg_type2 = work_line_->GetRegisterType(dec_insn.vB);
       if (!reg_type1.IsIntegralTypes() || !reg_type2.IsIntegralTypes()) {
         Fail(VERIFY_ERROR_GENERIC) << "args to 'if' (" << reg_type1 << ","
                                    << reg_type2 << ") must be integral";
@@ -2405,7 +2405,7 @@
     }
     case Instruction::IF_EQZ:
     case Instruction::IF_NEZ: {
-      const RegType& reg_type = work_line_->GetRegisterType(dec_insn.vA_);
+      const RegType& reg_type = work_line_->GetRegisterType(dec_insn.vA);
       if (!reg_type.IsReferenceTypes() && !reg_type.IsIntegralTypes()) {
         Fail(VERIFY_ERROR_GENERIC) << "type " << reg_type << " unexpected as arg to if-eqz/if-nez";
       }
@@ -2415,7 +2415,7 @@
     case Instruction::IF_GEZ:
     case Instruction::IF_GTZ:
     case Instruction::IF_LEZ: {
-      const RegType& reg_type = work_line_->GetRegisterType(dec_insn.vA_);
+      const RegType& reg_type = work_line_->GetRegisterType(dec_insn.vA);
       if (!reg_type.IsIntegralTypes()) {
         Fail(VERIFY_ERROR_GENERIC) << "type " << reg_type
                                    << " unexpected as arg to if-ltz/if-gez/if-gtz/if-lez";
@@ -2558,15 +2558,15 @@
     case Instruction::INVOKE_VIRTUAL_RANGE:
     case Instruction::INVOKE_SUPER:
     case Instruction::INVOKE_SUPER_RANGE: {
-      bool is_range = (dec_insn.opcode_ == Instruction::INVOKE_VIRTUAL_RANGE ||
-                       dec_insn.opcode_ == Instruction::INVOKE_SUPER_RANGE);
-      bool is_super =  (dec_insn.opcode_ == Instruction::INVOKE_SUPER ||
-                        dec_insn.opcode_ == Instruction::INVOKE_SUPER_RANGE);
+      bool is_range = (dec_insn.opcode == Instruction::INVOKE_VIRTUAL_RANGE ||
+                       dec_insn.opcode == Instruction::INVOKE_SUPER_RANGE);
+      bool is_super =  (dec_insn.opcode == Instruction::INVOKE_SUPER ||
+                        dec_insn.opcode == Instruction::INVOKE_SUPER_RANGE);
       Method* called_method = VerifyInvocationArgs(dec_insn, METHOD_VIRTUAL, is_range, is_super);
       if (failure_ == VERIFY_ERROR_NONE) {
         const char* descriptor;
         if (called_method == NULL) {
-          uint32_t method_idx = dec_insn.vB_;
+          uint32_t method_idx = dec_insn.vB;
           const DexFile::MethodId& method_id = dex_file_->GetMethodId(method_idx);
           uint32_t return_type_idx = dex_file_->GetProtoId(method_id.proto_idx_).return_type_idx_;
           descriptor =  dex_file_->StringByTypeIdx(return_type_idx);
@@ -2582,7 +2582,7 @@
     }
     case Instruction::INVOKE_DIRECT:
     case Instruction::INVOKE_DIRECT_RANGE: {
-      bool is_range = (dec_insn.opcode_ == Instruction::INVOKE_DIRECT_RANGE);
+      bool is_range = (dec_insn.opcode == Instruction::INVOKE_DIRECT_RANGE);
       Method* called_method = VerifyInvocationArgs(dec_insn, METHOD_DIRECT, is_range, false);
       if (failure_ == VERIFY_ERROR_NONE) {
         /*
@@ -2596,7 +2596,7 @@
         if (called_method != NULL) {
           is_constructor = called_method->IsConstructor();
         } else {
-          uint32_t method_idx = dec_insn.vB_;
+          uint32_t method_idx = dec_insn.vB;
           const DexFile::MethodId& method_id = dex_file_->GetMethodId(method_idx);
           const char* name = dex_file_->GetMethodName(method_id);
           is_constructor = strcmp(name, "<init>") == 0;
@@ -2644,7 +2644,7 @@
         }
         const char* descriptor;
         if (called_method == NULL) {
-          uint32_t method_idx = dec_insn.vB_;
+          uint32_t method_idx = dec_insn.vB;
           const DexFile::MethodId& method_id = dex_file_->GetMethodId(method_idx);
           uint32_t return_type_idx = dex_file_->GetProtoId(method_id.proto_idx_).return_type_idx_;
           descriptor =  dex_file_->StringByTypeIdx(return_type_idx);
@@ -2660,12 +2660,12 @@
     }
     case Instruction::INVOKE_STATIC:
     case Instruction::INVOKE_STATIC_RANGE: {
-        bool is_range = (dec_insn.opcode_ == Instruction::INVOKE_STATIC_RANGE);
+        bool is_range = (dec_insn.opcode == Instruction::INVOKE_STATIC_RANGE);
         Method* called_method = VerifyInvocationArgs(dec_insn, METHOD_STATIC, is_range, false);
         if (failure_ == VERIFY_ERROR_NONE) {
           const char* descriptor;
           if (called_method == NULL) {
-            uint32_t method_idx = dec_insn.vB_;
+            uint32_t method_idx = dec_insn.vB;
             const DexFile::MethodId& method_id = dex_file_->GetMethodId(method_idx);
             uint32_t return_type_idx = dex_file_->GetProtoId(method_id.proto_idx_).return_type_idx_;
             descriptor =  dex_file_->StringByTypeIdx(return_type_idx);
@@ -2681,7 +2681,7 @@
       break;
     case Instruction::INVOKE_INTERFACE:
     case Instruction::INVOKE_INTERFACE_RANGE: {
-      bool is_range =  (dec_insn.opcode_ == Instruction::INVOKE_INTERFACE_RANGE);
+      bool is_range =  (dec_insn.opcode == Instruction::INVOKE_INTERFACE_RANGE);
       Method* abs_method = VerifyInvocationArgs(dec_insn, METHOD_INTERFACE, is_range, false);
       if (failure_ == VERIFY_ERROR_NONE) {
         if (abs_method != NULL) {
@@ -2720,7 +2720,7 @@
          */
         const char* descriptor;
         if (abs_method == NULL) {
-          uint32_t method_idx = dec_insn.vB_;
+          uint32_t method_idx = dec_insn.vB;
           const DexFile::MethodId& method_id = dex_file_->GetMethodId(method_idx);
           uint32_t return_type_idx = dex_file_->GetProtoId(method_id.proto_idx_).return_type_idx_;
           descriptor =  dex_file_->StringByTypeIdx(return_type_idx);
@@ -2967,7 +2967,7 @@
      * DO NOT add a "default" clause here. Without it the compiler will
      * complain if an instruction is missing (which is desirable).
      */
-  }  // end - switch (dec_insn.opcode_)
+  }  // end - switch (dec_insn.opcode)
 
   if (failure_ != VERIFY_ERROR_NONE) {
     if (failure_ == VERIFY_ERROR_GENERIC) {
@@ -2982,7 +2982,7 @@
       insns = code_item_->insns_ + work_insn_idx_;
       /* continue on as if we just handled a throw-verification-error */
       failure_ = VERIFY_ERROR_NONE;
-      opcode_flag = Instruction::kThrow;
+      opcode_flags = Instruction::kThrow;
     }
   }
   /*
@@ -2995,7 +2995,7 @@
   }
 
   /* Handle "continue". Tag the next consecutive instruction. */
-  if ((opcode_flag & Instruction::kContinue) != 0) {
+  if ((opcode_flags & Instruction::kContinue) != 0) {
     uint32_t next_insn_idx = work_insn_idx_ + CurrentInsnFlags().GetLengthInCodeUnits();
     if (next_insn_idx >= code_item_->insns_size_in_code_units_) {
       Fail(VERIFY_ERROR_GENERIC) << "Execution can walk off end of code area";
@@ -3034,14 +3034,14 @@
    *
    * TODO: avoid re-fetching the branch target
    */
-  if ((opcode_flag & Instruction::kBranch) != 0) {
+  if ((opcode_flags & Instruction::kBranch) != 0) {
     bool isConditional, selfOkay;
     if (!GetBranchOffset(work_insn_idx_, &branch_target, &isConditional, &selfOkay)) {
       /* should never happen after static verification */
       Fail(VERIFY_ERROR_GENERIC) << "bad branch";
       return false;
     }
-    DCHECK_EQ(isConditional, (opcode_flag & Instruction::kContinue) != 0);
+    DCHECK_EQ(isConditional, (opcode_flags & Instruction::kContinue) != 0);
     if (!CheckMoveException(code_item_->insns_, work_insn_idx_ + branch_target)) {
       return false;
     }
@@ -3057,7 +3057,7 @@
    * We've already verified that the table is structurally sound, so we
    * just need to walk through and tag the targets.
    */
-  if ((opcode_flag & Instruction::kSwitch) != 0) {
+  if ((opcode_flags & Instruction::kSwitch) != 0) {
     int offset_to_switch = insns[1] | (((int32_t) insns[2]) << 16);
     const uint16_t* switch_insns = insns + offset_to_switch;
     int switch_count = switch_insns[1];
@@ -3094,7 +3094,7 @@
    * Handle instructions that can throw and that are sitting in a "try" block. (If they're not in a
    * "try" block when they throw, control transfers out of the method.)
    */
-  if ((opcode_flag & Instruction::kThrow) != 0 && insn_flags_[work_insn_idx_].IsInTry()) {
+  if ((opcode_flags & Instruction::kThrow) != 0 && insn_flags_[work_insn_idx_].IsInTry()) {
     bool within_catch_all = false;
     CatchHandlerIterator iterator(*code_item_, work_insn_idx_);
 
@@ -3122,7 +3122,7 @@
        * monitor-enter and the monitor stack was empty, we don't need a catch-all (if it throws,
        * it will do so before grabbing the lock).
        */
-      if (dec_insn.opcode_ != Instruction::MONITOR_ENTER || work_line_->MonitorStackDepth() != 1) {
+      if (dec_insn.opcode != Instruction::MONITOR_ENTER || work_line_->MonitorStackDepth() != 1) {
         Fail(VERIFY_ERROR_GENERIC)
             << "expected to be within a catch-all for an instruction where a monitor is held";
         return false;
@@ -3131,7 +3131,7 @@
   }
 
   /* If we're returning from the method, make sure monitor stack is empty. */
-  if ((opcode_flag & Instruction::kReturn) != 0) {
+  if ((opcode_flags & Instruction::kReturn) != 0) {
     if(!work_line_->VerifyMonitorStackEmpty()) {
       return false;
     }
@@ -3143,9 +3143,9 @@
    * neither of those exists we're in a return or throw; leave start_guess
    * alone and let the caller sort it out.
    */
-  if ((opcode_flag & Instruction::kContinue) != 0) {
+  if ((opcode_flags & Instruction::kContinue) != 0) {
     *start_guess = work_insn_idx_ + insn_flags_[work_insn_idx_].GetLengthInCodeUnits();
-  } else if ((opcode_flag & Instruction::kBranch) != 0) {
+  } else if ((opcode_flags & Instruction::kBranch) != 0) {
     /* we're still okay if branch_target is zero */
     *start_guess = work_insn_idx_ + branch_target;
   }
@@ -3314,11 +3314,11 @@
   return res_method;
 }
 
-Method* DexVerifier::VerifyInvocationArgs(const Instruction::DecodedInstruction& dec_insn,
+Method* DexVerifier::VerifyInvocationArgs(const DecodedInstruction& dec_insn,
                                           MethodType method_type, bool is_range, bool is_super) {
   // Resolve the method. This could be an abstract or concrete method depending on what sort of call
   // we're making.
-  Method* res_method = ResolveMethodAndCheckAccess(dec_insn.vB_, method_type);
+  Method* res_method = ResolveMethodAndCheckAccess(dec_insn.vB, method_type);
   if (res_method == NULL) {  // error or class is unresolved
     return NULL;
   }
@@ -3345,7 +3345,7 @@
   // We use vAA as our expected arg count, rather than res_method->insSize, because we need to
   // match the call to the signature. Also, we might might be calling through an abstract method
   // definition (which doesn't have register count values).
-  size_t expected_args = dec_insn.vA_;
+  size_t expected_args = dec_insn.vA;
   /* caught by static verifier */
   DCHECK(is_range || expected_args <= 5);
   if (expected_args > code_item_->outs_size_) {
@@ -3403,7 +3403,7 @@
     }
     const RegType& reg_type =
         reg_types_.FromDescriptor(method_->GetDeclaringClass()->GetClassLoader(), descriptor);
-    uint32_t get_reg = is_range ? dec_insn.vC_ + actual_args : dec_insn.arg_[actual_args];
+    uint32_t get_reg = is_range ? dec_insn.vC + actual_args : dec_insn.arg[actual_args];
     if (!work_line_->VerifyRegisterType(get_reg, reg_type)) {
       return NULL;
     }
@@ -3423,9 +3423,9 @@
                                    MethodHelper(method_).GetReturnTypeDescriptor());
 }
 
-void DexVerifier::VerifyNewArray(const Instruction::DecodedInstruction& dec_insn, bool is_filled,
+void DexVerifier::VerifyNewArray(const DecodedInstruction& dec_insn, bool is_filled,
                                  bool is_range) {
-  const RegType& res_type = ResolveClassAndCheckAccess(is_filled ? dec_insn.vB_ : dec_insn.vC_);
+  const RegType& res_type = ResolveClassAndCheckAccess(is_filled ? dec_insn.vB : dec_insn.vC);
   if (res_type.IsUnknown()) {
     CHECK_NE(failure_, VERIFY_ERROR_NONE);
   } else {
@@ -3434,17 +3434,17 @@
       Fail(VERIFY_ERROR_GENERIC) << "new-array on non-array class " << res_type;
     } else if (!is_filled) {
       /* make sure "size" register is valid type */
-      work_line_->VerifyRegisterType(dec_insn.vB_, reg_types_.Integer());
+      work_line_->VerifyRegisterType(dec_insn.vB, reg_types_.Integer());
       /* set register type to array class */
-      work_line_->SetRegisterType(dec_insn.vA_, res_type);
+      work_line_->SetRegisterType(dec_insn.vA, res_type);
     } else {
       // Verify each register. If "arg_count" is bad, VerifyRegisterType() will run off the end of
       // the list and fail. It's legal, if silly, for arg_count to be zero.
       const RegType& expected_type = reg_types_.GetComponentType(res_type,
                                                     method_->GetDeclaringClass()->GetClassLoader());
-      uint32_t arg_count = dec_insn.vA_;
+      uint32_t arg_count = dec_insn.vA;
       for (size_t ui = 0; ui < arg_count; ui++) {
-        uint32_t get_reg = is_range ? dec_insn.vC_ + ui : dec_insn.arg_[ui];
+        uint32_t get_reg = is_range ? dec_insn.vC + ui : dec_insn.arg[ui];
         if (!work_line_->VerifyRegisterType(get_reg, expected_type)) {
           work_line_->SetResultRegisterType(reg_types_.Unknown());
           return;
@@ -3456,22 +3456,22 @@
   }
 }
 
-void DexVerifier::VerifyAGet(const Instruction::DecodedInstruction& dec_insn,
+void DexVerifier::VerifyAGet(const DecodedInstruction& dec_insn,
                              const RegType& insn_type, bool is_primitive) {
-  const RegType& index_type = work_line_->GetRegisterType(dec_insn.vC_);
+  const RegType& index_type = work_line_->GetRegisterType(dec_insn.vC);
   if (!index_type.IsArrayIndexTypes()) {
     Fail(VERIFY_ERROR_GENERIC) << "Invalid reg type for array index (" << index_type << ")";
   } else {
-    const RegType& array_type = work_line_->GetRegisterType(dec_insn.vB_);
+    const RegType& array_type = work_line_->GetRegisterType(dec_insn.vB);
     if (array_type.IsZero()) {
       // Null array class; this code path will fail at runtime. Infer a merge-able type from the
       // instruction type. TODO: have a proper notion of bottom here.
       if (!is_primitive || insn_type.IsCategory1Types()) {
         // Reference or category 1
-        work_line_->SetRegisterType(dec_insn.vA_, reg_types_.Zero());
+        work_line_->SetRegisterType(dec_insn.vA, reg_types_.Zero());
       } else {
         // Category 2
-        work_line_->SetRegisterType(dec_insn.vA_, reg_types_.ConstLo());
+        work_line_->SetRegisterType(dec_insn.vA, reg_types_.ConstLo());
       }
     } else if (!array_type.IsArrayTypes()) {
       Fail(VERIFY_ERROR_GENERIC) << "not array type " << array_type << " with aget";
@@ -3494,19 +3494,19 @@
           // Use knowledge of the field type which is stronger than the type inferred from the
           // instruction, which can't differentiate object types and ints from floats, longs from
           // doubles.
-          work_line_->SetRegisterType(dec_insn.vA_, component_type);
+          work_line_->SetRegisterType(dec_insn.vA, component_type);
       }
     }
   }
 }
 
-void DexVerifier::VerifyAPut(const Instruction::DecodedInstruction& dec_insn,
+void DexVerifier::VerifyAPut(const DecodedInstruction& dec_insn,
                              const RegType& insn_type, bool is_primitive) {
-  const RegType& index_type = work_line_->GetRegisterType(dec_insn.vC_);
+  const RegType& index_type = work_line_->GetRegisterType(dec_insn.vC);
   if (!index_type.IsArrayIndexTypes()) {
     Fail(VERIFY_ERROR_GENERIC) << "Invalid reg type for array index (" << index_type << ")";
   } else {
-    const RegType& array_type = work_line_->GetRegisterType(dec_insn.vB_);
+    const RegType& array_type = work_line_->GetRegisterType(dec_insn.vB);
     if (array_type.IsZero()) {
       // Null array type; this code path will fail at runtime. Infer a merge-able type from the
       // instruction type.
@@ -3531,7 +3531,7 @@
         // The instruction agrees with the type of array, confirm the value to be stored does too
         // Note: we use the instruction type (rather than the component type) for aput-object as
         // incompatible classes will be caught at runtime as an array store exception
-        work_line_->VerifyRegisterType(dec_insn.vA_, is_primitive ? component_type : insn_type);
+        work_line_->VerifyRegisterType(dec_insn.vA, is_primitive ? component_type : insn_type);
       }
     }
   }
@@ -3625,18 +3625,18 @@
   }
 }
 
-void DexVerifier::VerifyISGet(const Instruction::DecodedInstruction& dec_insn,
+void DexVerifier::VerifyISGet(const DecodedInstruction& dec_insn,
                               const RegType& insn_type, bool is_primitive, bool is_static) {
-  uint32_t field_idx = is_static ? dec_insn.vB_ : dec_insn.vC_;
+  uint32_t field_idx = is_static ? dec_insn.vB : dec_insn.vC;
   Field* field;
   if (is_static) {
     field = GetStaticField(field_idx);
   } else {
-    const RegType& object_type = work_line_->GetRegisterType(dec_insn.vB_);
+    const RegType& object_type = work_line_->GetRegisterType(dec_insn.vB);
     field = GetInstanceField(object_type, field_idx);
   }
   if (failure_ != VERIFY_ERROR_NONE) {
-    work_line_->SetRegisterType(dec_insn.vA_, reg_types_.Unknown());
+    work_line_->SetRegisterType(dec_insn.vA, reg_types_.Unknown());
   } else {
     const char* descriptor;
     const ClassLoader* loader;
@@ -3673,22 +3673,22 @@
         return;
       }
     }
-    work_line_->SetRegisterType(dec_insn.vA_, field_type);
+    work_line_->SetRegisterType(dec_insn.vA, field_type);
   }
 }
 
-void DexVerifier::VerifyISPut(const Instruction::DecodedInstruction& dec_insn,
+void DexVerifier::VerifyISPut(const DecodedInstruction& dec_insn,
                               const RegType& insn_type, bool is_primitive, bool is_static) {
-  uint32_t field_idx = is_static ? dec_insn.vB_ : dec_insn.vC_;
+  uint32_t field_idx = is_static ? dec_insn.vB : dec_insn.vC;
   Field* field;
   if (is_static) {
     field = GetStaticField(field_idx);
   } else {
-    const RegType& object_type = work_line_->GetRegisterType(dec_insn.vB_);
+    const RegType& object_type = work_line_->GetRegisterType(dec_insn.vB);
     field = GetInstanceField(object_type, field_idx);
   }
   if (failure_ != VERIFY_ERROR_NONE) {
-    work_line_->SetRegisterType(dec_insn.vA_, reg_types_.Unknown());
+    work_line_->SetRegisterType(dec_insn.vA, reg_types_.Unknown());
   } else {
     const char* descriptor;
     const ClassLoader* loader;
@@ -3712,7 +3712,7 @@
       // Primitive field assignability rules are weaker than regular assignability rules
       bool instruction_compatible;
       bool value_compatible;
-      const RegType& value_type = work_line_->GetRegisterType(dec_insn.vA_);
+      const RegType& value_type = work_line_->GetRegisterType(dec_insn.vA);
       if (field_type.IsIntegralTypes()) {
         instruction_compatible = insn_type.IsIntegralTypes();
         value_compatible = value_type.IsIntegralTypes();
@@ -3740,7 +3740,7 @@
         return;
       }
       if (!value_compatible) {
-        Fail(VERIFY_ERROR_GENERIC) << "unexpected value in v" << dec_insn.vA_
+        Fail(VERIFY_ERROR_GENERIC) << "unexpected value in v" << dec_insn.vA
                                    << " of type " << value_type
                                    << " but expected " << field_type
                                    << " for store to " << PrettyField(field) << " in put";
@@ -3754,7 +3754,7 @@
                                   << "' in put-object";
         return;
       }
-      work_line_->VerifyRegisterType(dec_insn.vA_, field_type);
+      work_line_->VerifyRegisterType(dec_insn.vA, field_type);
     }
   }
 }
diff --git a/src/dex_verifier.h b/src/dex_verifier.h
index f4c0f43..c2785c6 100644
--- a/src/dex_verifier.h
+++ b/src/dex_verifier.h
@@ -705,13 +705,13 @@
    * The argument count is in vA, and the first argument is in vC, for both "simple" and "range"
    * versions. We just need to make sure vA is >= 1 and then return vC.
    */
-  const RegType& GetInvocationThis(const Instruction::DecodedInstruction& dec_insn);
+  const RegType& GetInvocationThis(const DecodedInstruction& dec_insn);
 
   /*
    * Verify types for a simple two-register instruction (e.g. "neg-int").
    * "dst_type" is stored into vA, and "src_type" is verified against vB.
    */
-  void CheckUnaryOp(const Instruction::DecodedInstruction& dec_insn,
+  void CheckUnaryOp(const DecodedInstruction& dec_insn,
                     const RegType& dst_type, const RegType& src_type);
 
   /*
@@ -719,7 +719,7 @@
    * "dst_type" is stored into vA, and "src_type1"/"src_type2" are verified
    * against vB/vC.
    */
-  void CheckBinaryOp(const Instruction::DecodedInstruction& dec_insn,
+  void CheckBinaryOp(const DecodedInstruction& dec_insn,
                      const RegType& dst_type, const RegType& src_type1, const RegType& src_type2,
                      bool check_boolean_op);
 
@@ -727,7 +727,7 @@
    * Verify types for a binary "2addr" operation. "src_type1"/"src_type2"
    * are verified against vA/vB, then "dst_type" is stored into vA.
    */
-  void CheckBinaryOp2addr(const Instruction::DecodedInstruction& dec_insn,
+  void CheckBinaryOp2addr(const DecodedInstruction& dec_insn,
                           const RegType& dst_type,
                           const RegType& src_type1, const RegType& src_type2,
                           bool check_boolean_op);
@@ -738,7 +738,7 @@
    *
    * If "check_boolean_op" is set, we use the constant value in vC.
    */
-  void CheckLiteralOp(const Instruction::DecodedInstruction& dec_insn,
+  void CheckLiteralOp(const DecodedInstruction& dec_insn,
                       const RegType& dst_type, const RegType& src_type, bool check_boolean_op);
 
   // Verify/push monitor onto the monitor stack, locking the value in reg_idx at location insn_idx.
@@ -1165,18 +1165,18 @@
   bool CodeFlowVerifyInstruction(uint32_t* start_guess);
 
   // Perform verification of a new array instruction
-  void VerifyNewArray(const Instruction::DecodedInstruction& dec_insn, bool is_filled,
+  void VerifyNewArray(const DecodedInstruction& dec_insn, bool is_filled,
                       bool is_range);
 
   // Perform verification of an aget instruction. The destination register's type will be set to
   // be that of component type of the array unless the array type is unknown, in which case a
   // bottom type inferred from the type of instruction is used. is_primitive is false for an
   // aget-object.
-  void VerifyAGet(const Instruction::DecodedInstruction& insn, const RegType& insn_type,
+  void VerifyAGet(const DecodedInstruction& insn, const RegType& insn_type,
                   bool is_primitive);
 
   // Perform verification of an aput instruction.
-  void VerifyAPut(const Instruction::DecodedInstruction& insn, const RegType& insn_type,
+  void VerifyAPut(const DecodedInstruction& insn, const RegType& insn_type,
                   bool is_primitive);
 
   // Lookup instance field and fail for resolution violations
@@ -1186,11 +1186,11 @@
   Field* GetStaticField(int field_idx);
 
   // Perform verification of an iget or sget instruction.
-  void VerifyISGet(const Instruction::DecodedInstruction& insn, const RegType& insn_type,
+  void VerifyISGet(const DecodedInstruction& insn, const RegType& insn_type,
                    bool is_primitive, bool is_static);
 
   // Perform verification of an iput or sput instruction.
-  void VerifyISPut(const Instruction::DecodedInstruction& insn, const RegType& insn_type,
+  void VerifyISPut(const DecodedInstruction& insn, const RegType& insn_type,
                    bool is_primitive, bool is_static);
 
   // Resolves a class based on an index and performs access checks to ensure the referrer can
@@ -1233,7 +1233,7 @@
    * Returns the resolved method on success, NULL on failure (with *failure
    * set appropriately).
    */
-  Method* VerifyInvocationArgs(const Instruction::DecodedInstruction& dec_insn,
+  Method* VerifyInvocationArgs(const DecodedInstruction& dec_insn,
                                MethodType method_type, bool is_range, bool is_super);
 
   /*
diff --git a/src/runtime_support.cc b/src/runtime_support.cc
index c4771b0..9bf2086 100644
--- a/src/runtime_support.cc
+++ b/src/runtime_support.cc
@@ -483,8 +483,8 @@
            (instr_code == Instruction::INVOKE_DIRECT_RANGE) ||
            (instr_code == Instruction::INVOKE_VIRTUAL) ||
            (instr_code == Instruction::INVOKE_VIRTUAL_RANGE));
-    Instruction::DecodedInstruction dec_insn(instr);
-    dex_method_idx = dec_insn.vB_;
+    DecodedInstruction dec_insn(instr);
+    dex_method_idx = dec_insn.vB;
     shorty = linker->MethodShorty(dex_method_idx, caller, &shorty_len);
   } else {
     DCHECK(!called->IsRuntimeMethod());
@@ -1032,7 +1032,7 @@
   return AllocArrayFromCode(type_idx, method, component_count, self, true);
 }
 
-// Helper function to alloc array for OP_FILLED_NEW_ARRAY
+// Helper function to allocate array for FILLED_NEW_ARRAY.
 Array* CheckAndAllocArrayFromCode(uint32_t type_idx, Method* method, int32_t component_count,
                                   Thread* self, bool access_check) {
   if (UNLIKELY(component_count < 0)) {
diff --git a/src/runtime_support.h b/src/runtime_support.h
index bad74c8..e297e2f 100644
--- a/src/runtime_support.h
+++ b/src/runtime_support.h
@@ -102,34 +102,34 @@
   extern "C" void art_work_around_app_jni_bugs();
 
   /* Conversions */
-  extern "C" float __aeabi_i2f(int op1);             // OP_INT_TO_FLOAT
-  extern "C" int __aeabi_f2iz(float op1);            // OP_FLOAT_TO_INT
-  extern "C" float __aeabi_d2f(double op1);          // OP_DOUBLE_TO_FLOAT
-  extern "C" double __aeabi_f2d(float op1);          // OP_FLOAT_TO_DOUBLE
-  extern "C" double __aeabi_i2d(int op1);            // OP_INT_TO_DOUBLE
-  extern "C" int __aeabi_d2iz(double op1);           // OP_DOUBLE_TO_INT
-  extern "C" float __aeabi_l2f(long op1);            // OP_LONG_TO_FLOAT
-  extern "C" double __aeabi_l2d(long op1);           // OP_LONG_TO_DOUBLE
+  extern "C" float __aeabi_i2f(int op1);             // INT_TO_FLOAT
+  extern "C" int __aeabi_f2iz(float op1);            // FLOAT_TO_INT
+  extern "C" float __aeabi_d2f(double op1);          // DOUBLE_TO_FLOAT
+  extern "C" double __aeabi_f2d(float op1);          // FLOAT_TO_DOUBLE
+  extern "C" double __aeabi_i2d(int op1);            // INT_TO_DOUBLE
+  extern "C" int __aeabi_d2iz(double op1);           // DOUBLE_TO_INT
+  extern "C" float __aeabi_l2f(long op1);            // LONG_TO_FLOAT
+  extern "C" double __aeabi_l2d(long op1);           // LONG_TO_DOUBLE
 
   /* Single-precision FP arithmetics */
-  extern "C" float __aeabi_fadd(float a, float b);   // OP_ADD_FLOAT[_2ADDR]
-  extern "C" float __aeabi_fsub(float a, float b);   // OP_SUB_FLOAT[_2ADDR]
-  extern "C" float __aeabi_fdiv(float a, float b);   // OP_DIV_FLOAT[_2ADDR]
-  extern "C" float __aeabi_fmul(float a, float b);   // OP_MUL_FLOAT[_2ADDR]
-  extern "C" float fmodf(float a, float b);          // OP_REM_FLOAT[_2ADDR]
+  extern "C" float __aeabi_fadd(float a, float b);   // ADD_FLOAT[_2ADDR]
+  extern "C" float __aeabi_fsub(float a, float b);   // SUB_FLOAT[_2ADDR]
+  extern "C" float __aeabi_fdiv(float a, float b);   // DIV_FLOAT[_2ADDR]
+  extern "C" float __aeabi_fmul(float a, float b);   // MUL_FLOAT[_2ADDR]
+  extern "C" float fmodf(float a, float b);          // REM_FLOAT[_2ADDR]
 
   /* Double-precision FP arithmetics */
-  extern "C" double __aeabi_dadd(double a, double b); // OP_ADD_DOUBLE[_2ADDR]
-  extern "C" double __aeabi_dsub(double a, double b); // OP_SUB_DOUBLE[_2ADDR]
-  extern "C" double __aeabi_ddiv(double a, double b); // OP_DIV_DOUBLE[_2ADDR]
-  extern "C" double __aeabi_dmul(double a, double b); // OP_MUL_DOUBLE[_2ADDR]
-  extern "C" double fmod(double a, double b);         // OP_REM_DOUBLE[_2ADDR]
+  extern "C" double __aeabi_dadd(double a, double b); // ADD_DOUBLE[_2ADDR]
+  extern "C" double __aeabi_dsub(double a, double b); // SUB_DOUBLE[_2ADDR]
+  extern "C" double __aeabi_ddiv(double a, double b); // DIV_DOUBLE[_2ADDR]
+  extern "C" double __aeabi_dmul(double a, double b); // MUL_DOUBLE[_2ADDR]
+  extern "C" double fmod(double a, double b);         // REM_DOUBLE[_2ADDR]
 
   /* Integer arithmetics */
-  extern "C" int __aeabi_idivmod(int op1, int op2);  // OP_REM_INT[_2ADDR|_LIT8|_LIT16]
-  extern "C" int __aeabi_idiv(int op1, int op2);     // OP_DIV_INT[_2ADDR|_LIT8|_LIT16]
+  extern "C" int __aeabi_idivmod(int op1, int op2);  // REM_INT[_2ADDR|_LIT8|_LIT16]
+  extern "C" int __aeabi_idiv(int op1, int op2);     // DIV_INT[_2ADDR|_LIT8|_LIT16]
 
-  /* Long long arithmetics - OP_REM_LONG[_2ADDR] & OP_DIV_LONG[_2ADDR] */
+  /* Long long arithmetics - REM_LONG[_2ADDR] and DIV_LONG[_2ADDR] */
   extern "C" long long __aeabi_ldivmod(long long op1, long long op2);
   extern "C" long long __aeabi_lmul(long long op1, long long op2);
   extern "C" uint64_t art_shl_long(uint64_t, uint32_t);
@@ -140,32 +140,32 @@
 
 #if defined(__mips__)
   /* Conversions */
-  extern "C" float __floatsisf(int op1);             // OP_INT_TO_FLOAT
-  extern "C" int __fixsfsi(float op1);               // OP_FLOAT_TO_INT
-  extern "C" float __truncdfsf2(double op1);         // OP_DOUBLE_TO_FLOAT
-  extern "C" double __extendsfdf2(float op1);        // OP_FLOAT_TO_DOUBLE
-  extern "C" double __floatsidf(int op1);            // OP_INT_TO_DOUBLE
-  extern "C" int __fixdfsi(double op1);              // OP_DOUBLE_TO_INT
-  extern "C" float __floatdisf(long long op1);       // OP_LONG_TO_FLOAT
-  extern "C" double __floatdidf(long long op1);      // OP_LONG_TO_DOUBLE
-  extern "C" long long __fixsfdi(float op1);         // OP_FLOAT_TO_LONG
-  extern "C" long long __fixdfdi(double op1);        // OP_DOUBLE_TO_LONG
+  extern "C" float __floatsisf(int op1);             // INT_TO_FLOAT
+  extern "C" int __fixsfsi(float op1);               // FLOAT_TO_INT
+  extern "C" float __truncdfsf2(double op1);         // DOUBLE_TO_FLOAT
+  extern "C" double __extendsfdf2(float op1);        // FLOAT_TO_DOUBLE
+  extern "C" double __floatsidf(int op1);            // INT_TO_DOUBLE
+  extern "C" int __fixdfsi(double op1);              // DOUBLE_TO_INT
+  extern "C" float __floatdisf(long long op1);       // LONG_TO_FLOAT
+  extern "C" double __floatdidf(long long op1);      // LONG_TO_DOUBLE
+  extern "C" long long __fixsfdi(float op1);         // FLOAT_TO_LONG
+  extern "C" long long __fixdfdi(double op1);        // DOUBLE_TO_LONG
 
   /* Single-precision FP arithmetics */
-  extern "C" float __addsf3(float a, float b);   // OP_ADD_FLOAT[_2ADDR]
-  extern "C" float __subsf3(float a, float b);   // OP_SUB_FLOAT[_2ADDR]
-  extern "C" float __divsf3(float a, float b);   // OP_DIV_FLOAT[_2ADDR]
-  extern "C" float __mulsf3(float a, float b);   // OP_MUL_FLOAT[_2ADDR]
-  extern "C" float fmodf(float a, float b);          // OP_REM_FLOAT[_2ADDR]
+  extern "C" float __addsf3(float a, float b);   // ADD_FLOAT[_2ADDR]
+  extern "C" float __subsf3(float a, float b);   // SUB_FLOAT[_2ADDR]
+  extern "C" float __divsf3(float a, float b);   // DIV_FLOAT[_2ADDR]
+  extern "C" float __mulsf3(float a, float b);   // MUL_FLOAT[_2ADDR]
+  extern "C" float fmodf(float a, float b);      // REM_FLOAT[_2ADDR]
 
   /* Double-precision FP arithmetics */
-  extern "C" double __adddf3(double a, double b); // OP_ADD_DOUBLE[_2ADDR]
-  extern "C" double __subdf3(double a, double b); // OP_SUB_DOUBLE[_2ADDR]
-  extern "C" double __divdf3(double a, double b); // OP_DIV_DOUBLE[_2ADDR]
-  extern "C" double __muldf3(double a, double b); // OP_MUL_DOUBLE[_2ADDR]
-  extern "C" double fmod(double a, double b);         // OP_REM_DOUBLE[_2ADDR]
+  extern "C" double __adddf3(double a, double b); // ADD_DOUBLE[_2ADDR]
+  extern "C" double __subdf3(double a, double b); // SUB_DOUBLE[_2ADDR]
+  extern "C" double __divdf3(double a, double b); // DIV_DOUBLE[_2ADDR]
+  extern "C" double __muldf3(double a, double b); // MUL_DOUBLE[_2ADDR]
+  extern "C" double fmod(double a, double b);     // REM_DOUBLE[_2ADDR]
 
-  /* Long long arithmetics - OP_REM_LONG[_2ADDR] & OP_DIV_LONG[_2ADDR] */
+  /* Long long arithmetics - REM_LONG[_2ADDR] and DIV_LONG[_2ADDR] */
   extern "C" long long __divdi3(long long op1, long long op2);
   extern "C" long long __moddi3(long long op1, long long op2);
 
diff --git a/src/runtime_support_arm.S b/src/runtime_support_arm.S
index 3ee4dea..be6945b 100644
--- a/src/runtime_support_arm.S
+++ b/src/runtime_support_arm.S
@@ -645,7 +645,7 @@
     .global art_check_and_alloc_array_from_code
     .extern artCheckAndAllocArrayFromCode
     /*
-     * Called by managed code to allocate an array in a special case for OP_FILLED_NEW_ARRAY
+     * Called by managed code to allocate an array in a special case for FILLED_NEW_ARRAY
      */
 art_check_and_alloc_array_from_code:
     SETUP_REF_ONLY_CALLEE_SAVE_FRAME  @ save callee saves in case of GC
@@ -661,7 +661,7 @@
     .global art_check_and_alloc_array_from_code_with_access_check
     .extern artCheckAndAllocArrayFromCodeWithAccessCheck
     /*
-     * Called by managed code to allocate an array in a special case for OP_FILLED_NEW_ARRAY
+     * Called by managed code to allocate an array in a special case for FILLED_NEW_ARRAY
      */
 art_check_and_alloc_array_from_code_with_access_check:
     SETUP_REF_ONLY_CALLEE_SAVE_FRAME  @ save callee saves in case of GC