tree 2d63c98a1f729f1e17969bfbc4b7dc1da48f4567
parent 11f9d2130e938511efceb6d2a4793cee7dfdde35
author buzbee <buzbee@google.com> 1330901826 -0800
committer buzbee <buzbee@google.com> 1330902036 -0800

Complete MIPS code generation support

With this CL code generation for MIPS is complete (though untested on
actual hardware).  Core and the boot classpath compile without issue.

The primary thrust here was to support expanding of short branch
sequences to long form during assembly if the displacement field overflowed.
That led to a general cleanup of creation on LIR nodes outside of the
normal flow.

Also introduced is a README to describe the state of MIPS support, as well
as memory barrier handling.

Change-Id: I251a2ef8d74bc7183406dce9493464be24a9d7f7