tree 92b2cc6da112b027432ae4d5bc985118baebe376
parent ce4cc0d1818e872c1c7f3c3519a82259afd5c288
author buzbee <buzbee@google.com> 1354746404 -0800
committer buzbee <buzbee@google.com> 1354746404 -0800

Quick compiler: refactored listing & const fix

This CL started off as a simple fix to Issue 4959751, which
identified a case in which compiler debugging listings could read
uninitialized data.  The fix ended up pulling a few strings - we
had two distinct dex printing routines (one was focused on SSA names
and was used by the .dot graph dumper), while the other was used with
verbose codegen listing.

Ended up combining the two routines and significantly enhancing the
value of the verbose debug output.  We now always use ssa register
names, and also show the constant values of ssa names which are known
to be const following constant propagation.

Along the way, deleted a bit of useless code that remapped all
registers in a phi set to have the same name, and also got rid of
some duplicate listing helper LIR pseudo ops.

Somee examples of the new listing:

-------- dalvik offset: 0x2 @ const/4 v0_1#0x1, #1

the format of the vreg is:
   v<orignal Dalvik vnum>_<ssa instance>[#hex value of immediate]

In this example, we don't add any new info (the listing already had #1),
but we also show this form in uses:

invoke-virtual v0_2, v1_3#0x40

Also improved is the listing output of potentially throwing instructions
which are broken into two parts: the check portion and the work portion.
Both halves now show the full disassembly.  For example:

-------- dalvik offset: 0x13 @ Check1: invoke-virtual v0_2, v1_3#0x40
....code here
....code here
-------- dalvik offset: 0x13 @ Check2: invoke-virtual v0_2, v1_3#0x40

Dalvik instructions which are optimized away prior to code generation
are displayed in sqare brackets.  For example:

-------- dalvik offset: 0x16 @ [move-result-object v0_3]--optimized away

Finally, Phi nodes show which incoming block an operand came through.
In the following example:

-------- dalvik offset: 0x5 @ Phi v1_2 = (v1_1#0x0:4, v1_2:12, v1_3#0x1:14)

Sreg v1_2 is a merge of a constant 0x0 from incoming block 4, a non-const
value from block 12 and a const 0x1 from block 14.

Change-Id: Ib6c19c19ab8a48509d43d8b0e5ed3e8e7ce9fc82