Implement Intel QuasiAtomics.

Don't use striped locks for 64bit atomics on x86.
Modify QuasiAtomic::Swap to be QuasiAtomic::Write that fits our current use of
Swap and is closer to Intel's implementation.
Return that MIPS doesn't support 64bit compare-and-exchanges in AtomicLong.
Set the SSE2 flag for host and target Intel ART builds as our codegen assumes

Change-Id: Ic1cd5c3b06838e42c6f94e0dd91e77a2d0bb5868
7 files changed
tree: e2893a0096a9c61f400d1f0bf0573eac75ae630d
  1. .gitignore
  3. build/
  4. jdwpspy/
  5. src/
  6. test/
  7. tools/