diff --git a/src/compiler/Dataflow.cc b/src/compiler/Dataflow.cc
index 33ef0ad..ca9d865 100644
--- a/src/compiler/Dataflow.cc
+++ b/src/compiler/Dataflow.cc
@@ -1843,6 +1843,7 @@
           squashDupRangeChecks(cUnit, &tbb, mir, arrSreg, idxSreg);
         }
         break;
+#if defined(TARGET_ARM)
       case Instruction::CMPL_FLOAT:
       case Instruction::CMPL_DOUBLE:
       case Instruction::CMPG_FLOAT:
@@ -1912,6 +1913,7 @@
           }
         }
         break;
+#endif
       default:
         break;
     }
diff --git a/src/compiler/Frontend.cc b/src/compiler/Frontend.cc
index 236ab86..b68233b 100644
--- a/src/compiler/Frontend.cc
+++ b/src/compiler/Frontend.cc
@@ -799,9 +799,7 @@
 #endif
   if (cUnit->instructionSet == kX86) {
     // Disable some optimizations on X86 for now
-    cUnit->disableOpt |= (
-        (1 << kLoadStoreElimination) |
-        (1 << kPromoteRegs));
+    cUnit->disableOpt |= (1 << kLoadStoreElimination);
   }
   /* Are we generating code for the debugger? */
   if (compiler.IsDebuggingSupported()) {
diff --git a/src/compiler/codegen/CodegenUtil.cc b/src/compiler/codegen/CodegenUtil.cc
index 428b443..a33a162 100644
--- a/src/compiler/codegen/CodegenUtil.cc
+++ b/src/compiler/codegen/CodegenUtil.cc
@@ -74,14 +74,15 @@
 {
   u8 seed;
   int shift;
-  int regId = reg & 0x1f;
 
 #if defined(TARGET_X86)
+  int regId = reg & 0xf;
   /*
    * Double registers in x86 are just a single FP register
    */
   seed = 1;
 #else
+  int regId = reg & 0x1f;
   /*
    * Each double register is equal to a pair of single-precision FP registers
    */
diff --git a/src/compiler/codegen/x86/X86/Factory.cc b/src/compiler/codegen/x86/X86/Factory.cc
index f77a793..e88f7dc 100644
--- a/src/compiler/codegen/x86/X86/Factory.cc
+++ b/src/compiler/codegen/x86/X86/Factory.cc
@@ -299,7 +299,7 @@
     X86OpCode opcode = IS_SIMM8(value) ? kX86Imul32RRI8 : kX86Imul32RRI;
     return newLIR3(cUnit, opcode, rDest, rSrc, value);
   } else if (op == kOpAnd) {
-    if (value == 0xFF && rDest < 4) {
+    if (value == 0xFF && rSrc < 4) {
       return newLIR2(cUnit, kX86Movzx8RR, rDest, rSrc);
     } else if (value == 0xFFFF) {
       return newLIR2(cUnit, kX86Movzx16RR, rDest, rSrc);
diff --git a/src/disassembler_x86.cc b/src/disassembler_x86.cc
index d45d641..f70289f 100644
--- a/src/disassembler_x86.cc
+++ b/src/disassembler_x86.cc
@@ -513,6 +513,8 @@
         break;
       case 0xB6: opcode << "movzxb"; has_modrm = true; load = true; break;
       case 0xB7: opcode << "movzxw"; has_modrm = true; load = true; break;
+      case 0xBE: opcode << "movsxb"; has_modrm = true; load = true; break;
+      case 0xBF: opcode << "movsxw"; has_modrm = true; load = true; break;
       default:
         opcode << StringPrintf("unknown opcode '0F %02X'", *instr);
         break;