tree ac0d772535c1c34c7788e56fa0ae2dbc08d27668
parent 7b9ad926a160034c102dc8c7fad8f5112d57b360
author buzbee <buzbee@google.com> 1354235622 -0800
committer buzbee <buzbee@google.com> 1354319471 -0800

Quick compiler: tighten null/0/0.0 workaround

Change 255389 worked around an issue with the compiler and
garbage collector being out of sync regarding the type of a Dalvik
register loaded with a constant 0 value.

The workaround was to detect the case of a constant 0 loaded
into a promoted floating point register, and then also store a
zero in the core/reference identity of that Dalvik vreg.

This CL tightens the workaround by ensuring that the additional
store is only performed in cases in which the promoted-to-float
Dalvik vreg is also used as a reference at some point in the
method.

Additionally, it improves the code sequence somewhat by reusing
the register loaded with zero for the subsequent store.  Further,
an unrelated enhancement is made to the floating point immediate
loading code.  For Arm, a few floating point constant values are
supported via vmov immediate.  However, 0.0 is not a bit pattern
that can be directly generated.  Previously, we would load 0.0 from
the method's literal pool.  In this CL we instead materialize +2
in a core register, and then emit an vsub reg,reg,reg to convert
it to +0.0. This saves a few bytes of code space, and avoids a
memory reference.

In the future, we'll want to have more info about the target
CPU's capabilities.  A vector exclusive or would likely be
better here.

Change-Id: Icacd85c86112c5355d35b536e2f7a41c0357682c