commit 742e25ef8cc9655c7bb27f3c34a7e3b4e3607d99
author Elliott Hughes <enh@google.com> Tue Apr 24 18:11:08 2012 -0700
committer Elliott Hughes <enh@google.com> Tue Apr 24 18:11:08 2012 -0700
tree 950bbef9b3cd1f010a265be2315949720937e7a0
parent 98e2017cac7ca554602480fcefabbbe630a4a39b

More MIPS support.

Change-Id: I0c2433ecbcfc549720acea53a3ca79a687a87a55

src/compiled_method.cc

diff --git a/src/compiled_method.cc b/src/compiled_method.cc
index 2340cbd..980fdc9 100644
--- a/src/compiled_method.cc
+++ b/src/compiled_method.cc
@@ -134,10 +134,12 @@
     case kArm:
     case kThumb2:
       return RoundUp(offset, kArmAlignment);
+    case kMips:
+      return RoundUp(offset, kMipsAlignment);
     case kX86:
       return RoundUp(offset, kX86Alignment);
     default:
-      LOG(FATAL) << "Unknown InstructionSet: " << static_cast<int>(instruction_set);
+      LOG(FATAL) << "Unknown InstructionSet: " << instruction_set;
       return 0;
   }
 }
@@ -145,6 +147,7 @@
 size_t CompiledMethod::CodeDelta() const {
   switch (instruction_set_) {
     case kArm:
+    case kMips:
     case kX86:
       return 0;
     case kThumb2: {
@@ -152,7 +155,7 @@
       return 1;
     }
     default:
-      LOG(FATAL) << "Unknown InstructionSet: " << static_cast<int>(instruction_set_);
+      LOG(FATAL) << "Unknown InstructionSet: " << instruction_set_;
       return 0;
   }
 }
@@ -161,6 +164,7 @@
                                         InstructionSet instruction_set) {
   switch (instruction_set) {
     case kArm:
+    case kMips:
     case kX86:
       return code_pointer;
     case kThumb2: {
@@ -170,7 +174,7 @@
       return reinterpret_cast<const void*>(address);
     }
     default:
-      LOG(FATAL) << "Unknown InstructionSet: " << static_cast<int>(instruction_set);
+      LOG(FATAL) << "Unknown InstructionSet: " << instruction_set;
       return NULL;
   }
 }

src/globals.h

diff --git a/src/globals.h b/src/globals.h
index 35a2113..5f0987a 100644
--- a/src/globals.h
+++ b/src/globals.h
@@ -46,6 +46,9 @@
 // ARM instruction alignment. ARM processors require code to be 4-byte aligned.
 const int kArmAlignment = 4;
 
+// MIPS instruction alignment.  MIPS processors require code to be 4-byte aligned.
+const int kMipsAlignment = 4;
+
 // X86 instruction alignment. This is the recommended alignment for maximum performance.
 const int kX86Alignment = 16;