X86 Backend support for vectorized float and byte 16x16 operations
Add support for reserving vector registers for the duration of vector loop.
Add support for 16x16 multiplication, shifts, and add reduce.
Changed the vectorization implementation to be able to use the dataflow
elements for SSA recreation and fixed a few implementation details.
Signed-off-by: Jean Christophe Beyler <firstname.lastname@example.org>
Signed-off-by: Olivier Come <email@example.com>
Signed-off-by: Udayan Banerji <firstname.lastname@example.org>
9 files changed